aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorTobias Klauser <tklauser@distanz.ch>2009-12-23 08:14:34 -0500
committerEric Anholt <eric@anholt.net>2010-01-06 12:40:02 -0500
commit69e302a998ddfc3bd99033052f6d6152a46e7d6e (patch)
tree3b51e6835e49a2beb068a784813ebdbbd8d81ca3
parentcda9d05c499093c67b4a376a15009923acc2127a (diff)
drm/i915: Storage class should be before const qualifier
The C99 specification states in section 6.11.5: The placement of a storage-class specifier other than at the beginning of the declaration specifiers in a declaration is an obsolescent feature. Signed-off-by: Tobias Klauser <tklauser@distanz.ch> Signed-off-by: Eric Anholt <eric@anholt.net>
-rw-r--r--drivers/gpu/drm/i915/intel_display.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9187a1736b01..af61dd915f2b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2448,7 +2448,7 @@ static void pineview_enable_cxsr(struct drm_device *dev, unsigned long clock,
2448 * A value of 5us seems to be a good balance; safe for very low end 2448 * A value of 5us seems to be a good balance; safe for very low end
2449 * platforms but not overly aggressive on lower latency configs. 2449 * platforms but not overly aggressive on lower latency configs.
2450 */ 2450 */
2451const static int latency_ns = 5000; 2451static const int latency_ns = 5000;
2452 2452
2453static int i9xx_get_fifo_size(struct drm_device *dev, int plane) 2453static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2454{ 2454{
@@ -2559,7 +2559,7 @@ static void g4x_update_wm(struct drm_device *dev, int planea_clock,
2559 /* Calc sr entries for one plane configs */ 2559 /* Calc sr entries for one plane configs */
2560 if (sr_hdisplay && (!planea_clock || !planeb_clock)) { 2560 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2561 /* self-refresh has much higher latency */ 2561 /* self-refresh has much higher latency */
2562 const static int sr_latency_ns = 12000; 2562 static const int sr_latency_ns = 12000;
2563 2563
2564 sr_clock = planea_clock ? planea_clock : planeb_clock; 2564 sr_clock = planea_clock ? planea_clock : planeb_clock;
2565 line_time_us = ((sr_hdisplay * 1000) / sr_clock); 2565 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
@@ -2598,7 +2598,7 @@ static void i965_update_wm(struct drm_device *dev, int planea_clock,
2598 /* Calc sr entries for one plane configs */ 2598 /* Calc sr entries for one plane configs */
2599 if (sr_hdisplay && (!planea_clock || !planeb_clock)) { 2599 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2600 /* self-refresh has much higher latency */ 2600 /* self-refresh has much higher latency */
2601 const static int sr_latency_ns = 12000; 2601 static const int sr_latency_ns = 12000;
2602 2602
2603 sr_clock = planea_clock ? planea_clock : planeb_clock; 2603 sr_clock = planea_clock ? planea_clock : planeb_clock;
2604 line_time_us = ((sr_hdisplay * 1000) / sr_clock); 2604 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
@@ -2667,7 +2667,7 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2667 if (HAS_FW_BLC(dev) && sr_hdisplay && 2667 if (HAS_FW_BLC(dev) && sr_hdisplay &&
2668 (!planea_clock || !planeb_clock)) { 2668 (!planea_clock || !planeb_clock)) {
2669 /* self-refresh has much higher latency */ 2669 /* self-refresh has much higher latency */
2670 const static int sr_latency_ns = 6000; 2670 static const int sr_latency_ns = 6000;
2671 2671
2672 sr_clock = planea_clock ? planea_clock : planeb_clock; 2672 sr_clock = planea_clock ? planea_clock : planeb_clock;
2673 line_time_us = ((sr_hdisplay * 1000) / sr_clock); 2673 line_time_us = ((sr_hdisplay * 1000) / sr_clock);