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authorMike Isely <isely@pobox.com>2007-01-28 13:38:55 -0500
committerMauro Carvalho Chehab <mchehab@infradead.org>2007-02-21 10:35:12 -0500
commit567d7115b9ce8145c166e3368bf31fe613451f77 (patch)
tree7d5ce8468578501aefc54495df57abf742e6b7dd
parentedae96bd72155b88f8682c830c63338cd699d35c (diff)
V4L/DVB (5172): Pvrusb2: Control protocol cleanup
Several special-case FX2 commands were being issued through pvr2_write_u16() and pvr2_write_8(), but there's really nothing special case about them. These date from a very early time in the driver development. This patch removes these functions and replaces their use with calls to pvr2_send_request. Signed-off-by: Mike Isely <isely@pobox.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
-rw-r--r--drivers/media/video/pvrusb2/pvrusb2-fx2-cmd.h3
-rw-r--r--drivers/media/video/pvrusb2/pvrusb2-hdw.c50
2 files changed, 15 insertions, 38 deletions
diff --git a/drivers/media/video/pvrusb2/pvrusb2-fx2-cmd.h b/drivers/media/video/pvrusb2/pvrusb2-fx2-cmd.h
index c6aa9751a0d6..ffbc6d096108 100644
--- a/drivers/media/video/pvrusb2/pvrusb2-fx2-cmd.h
+++ b/drivers/media/video/pvrusb2/pvrusb2-fx2-cmd.h
@@ -29,6 +29,7 @@
29 29
30#define FX2CMD_REG_WRITE 0x04 30#define FX2CMD_REG_WRITE 0x04
31#define FX2CMD_REG_READ 0x05 31#define FX2CMD_REG_READ 0x05
32#define FX2CMD_MEMSEL 0x06
32 33
33#define FX2CMD_I2C_WRITE 0x08 34#define FX2CMD_I2C_WRITE 0x08
34#define FX2CMD_I2C_READ 0x09 35#define FX2CMD_I2C_READ 0x09
@@ -38,6 +39,8 @@
38#define FX2CMD_STREAMING_ON 0x36 39#define FX2CMD_STREAMING_ON 0x36
39#define FX2CMD_STREAMING_OFF 0x37 40#define FX2CMD_STREAMING_OFF 0x37
40 41
42#define FX2CMD_FWPOST1 0x52
43
41#define FX2CMD_POWER_OFF 0xdc 44#define FX2CMD_POWER_OFF 0xdc
42#define FX2CMD_POWER_ON 0xde 45#define FX2CMD_POWER_ON 0xde
43 46
diff --git a/drivers/media/video/pvrusb2/pvrusb2-hdw.c b/drivers/media/video/pvrusb2/pvrusb2-hdw.c
index ccd871ac4b60..8ba72968639b 100644
--- a/drivers/media/video/pvrusb2/pvrusb2-hdw.c
+++ b/drivers/media/video/pvrusb2/pvrusb2-hdw.c
@@ -271,8 +271,6 @@ static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
271 unsigned int timeout,int probe_fl, 271 unsigned int timeout,int probe_fl,
272 void *write_data,unsigned int write_len, 272 void *write_data,unsigned int write_len,
273 void *read_data,unsigned int read_len); 273 void *read_data,unsigned int read_len);
274static int pvr2_write_u16(struct pvr2_hdw *hdw, u16 data, int res);
275static int pvr2_write_u8(struct pvr2_hdw *hdw, u8 data, int res);
276 274
277static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp) 275static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
278{ 276{
@@ -1248,8 +1246,13 @@ int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1248 ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/ 1246 ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1249 ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/ 1247 ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1250 ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/ 1248 ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1251 ret |= pvr2_write_u8(hdw, 0x52, 0); 1249 LOCK_TAKE(hdw->ctl_lock); do {
1252 ret |= pvr2_write_u16(hdw, 0x0600, 0); 1250 hdw->cmd_buffer[0] = FX2CMD_FWPOST1;
1251 ret |= pvr2_send_request(hdw,hdw->cmd_buffer,1,0,0);
1252 hdw->cmd_buffer[0] = FX2CMD_MEMSEL;
1253 hdw->cmd_buffer[1] = 0;
1254 ret |= pvr2_send_request(hdw,hdw->cmd_buffer,2,0,0);
1255 } while (0); LOCK_GIVE(hdw->ctl_lock);
1253 1256
1254 if (ret) { 1257 if (ret) {
1255 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1258 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
@@ -1311,7 +1314,11 @@ int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1311 1314
1312 ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/ 1315 ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1313 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/ 1316 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1314 ret |= pvr2_write_u16(hdw, 0x0600, 0); 1317 LOCK_TAKE(hdw->ctl_lock); do {
1318 hdw->cmd_buffer[0] = FX2CMD_MEMSEL;
1319 hdw->cmd_buffer[1] = 0;
1320 ret |= pvr2_send_request(hdw,hdw->cmd_buffer,2,0,0);
1321 } while (0); LOCK_GIVE(hdw->ctl_lock);
1315 1322
1316 if (ret) { 1323 if (ret) {
1317 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1324 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
@@ -3016,39 +3023,6 @@ static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
3016} 3023}
3017 3024
3018 3025
3019static int pvr2_write_u16(struct pvr2_hdw *hdw, u16 data, int res)
3020{
3021 int ret;
3022
3023 LOCK_TAKE(hdw->ctl_lock);
3024
3025 hdw->cmd_buffer[0] = (data >> 8) & 0xff;
3026 hdw->cmd_buffer[1] = data & 0xff;
3027
3028 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 2, hdw->cmd_buffer, res);
3029
3030 LOCK_GIVE(hdw->ctl_lock);
3031
3032 return ret;
3033}
3034
3035
3036static int pvr2_write_u8(struct pvr2_hdw *hdw, u8 data, int res)
3037{
3038 int ret;
3039
3040 LOCK_TAKE(hdw->ctl_lock);
3041
3042 hdw->cmd_buffer[0] = data;
3043
3044 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 1, hdw->cmd_buffer, res);
3045
3046 LOCK_GIVE(hdw->ctl_lock);
3047
3048 return ret;
3049}
3050
3051
3052static void pvr2_hdw_render_useless_unlocked(struct pvr2_hdw *hdw) 3026static void pvr2_hdw_render_useless_unlocked(struct pvr2_hdw *hdw)
3053{ 3027{
3054 if (!hdw->flag_ok) return; 3028 if (!hdw->flag_ok) return;