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authorMagnus Damm <damm@igel.co.jp>2009-05-11 05:01:08 -0400
committerPaul Mundt <lethal@linux-sh.org>2009-05-11 08:59:58 -0400
commit3d6ad460214cc72b93333f51f498441a56d622e9 (patch)
treef6c5f19467d3f3c78b014d9adcf9e4a18eaa75fa
parentc42f32dca3855d8f867387ec6993d9b62516a00e (diff)
sh: multiple vectors per irq - sh7760
Update intc tables and platform data to use one linux irq per maskable interrupt source instead of keeping the one-to-one mapping between vectors and linux irqs. This fixes potential irq masking issues for sh7760 hardware blocks such as DMAC/TMU2/REF. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
-rw-r--r--arch/sh/drivers/dma/Kconfig3
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh7760.c31
2 files changed, 13 insertions, 21 deletions
diff --git a/arch/sh/drivers/dma/Kconfig b/arch/sh/drivers/dma/Kconfig
index 666713ac5fcf..63e9dd30b41c 100644
--- a/arch/sh/drivers/dma/Kconfig
+++ b/arch/sh/drivers/dma/Kconfig
@@ -16,7 +16,8 @@ config SH_DMA_IRQ_MULTI
16 CPU_SUBTYPE_SH7750S || CPU_SUBTYPE_SH7750R || \ 16 CPU_SUBTYPE_SH7750S || CPU_SUBTYPE_SH7750R || \
17 CPU_SUBTYPE_SH7751R || CPU_SUBTYPE_SH7091 || \ 17 CPU_SUBTYPE_SH7751R || CPU_SUBTYPE_SH7091 || \
18 CPU_SUBTYPE_SH7763 || CPU_SUBTYPE_SH7764 || \ 18 CPU_SUBTYPE_SH7763 || CPU_SUBTYPE_SH7764 || \
19 CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785 19 CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785 || \
20 CPU_SUBTYPE_SH7760
20 21
21config NR_ONCHIP_DMA_CHANNELS 22config NR_ONCHIP_DMA_CHANNELS
22 int 23 int
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7760.c b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
index 4a6fd0d3c7bc..cd097335758f 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7760.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
@@ -19,10 +19,7 @@ enum {
19 19
20 /* interrupt sources */ 20 /* interrupt sources */
21 IRL0, IRL1, IRL2, IRL3, 21 IRL0, IRL1, IRL2, IRL3,
22 HUDI, GPIOI, 22 HUDI, GPIOI, DMAC,
23 DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3,
24 DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7,
25 DMAC_DMAE,
26 IRQ4, IRQ5, IRQ6, IRQ7, 23 IRQ4, IRQ5, IRQ6, IRQ7,
27 HCAN20, HCAN21, 24 HCAN20, HCAN21,
28 SSI0, SSI1, 25 SSI0, SSI1,
@@ -37,21 +34,20 @@ enum {
37 HSPI, 34 HSPI,
38 MMCIF0, MMCIF1, MMCIF2, MMCIF3, 35 MMCIF0, MMCIF1, MMCIF2, MMCIF3,
39 MFI, ADC, CMT, 36 MFI, ADC, CMT,
40 TMU0, TMU1, TMU2_TUNI, TMU2_TICPI, 37 TMU0, TMU1, TMU2,
41 WDT, 38 WDT, REF,
42 REF_RCMI, REF_ROVI,
43 39
44 /* interrupt groups */ 40 /* interrupt groups */
45 DMAC, DMABRG, SCIF0, SCIF1, SCIF2, SIM, MMCIF, TMU2, REF, 41 DMABRG, SCIF0, SCIF1, SCIF2, SIM, MMCIF,
46}; 42};
47 43
48static struct intc_vect vectors[] __initdata = { 44static struct intc_vect vectors[] __initdata = {
49 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620), 45 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
50 INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), 46 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
51 INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), 47 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
52 INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0), 48 INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
53 INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0), 49 INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0),
54 INTC_VECT(DMAC_DMAE, 0x6c0), 50 INTC_VECT(DMAC, 0x6c0),
55 INTC_VECT(IRQ4, 0x800), INTC_VECT(IRQ5, 0x820), 51 INTC_VECT(IRQ4, 0x800), INTC_VECT(IRQ5, 0x820),
56 INTC_VECT(IRQ6, 0x840), INTC_VECT(IRQ6, 0x860), 52 INTC_VECT(IRQ6, 0x840), INTC_VECT(IRQ6, 0x860),
57 INTC_VECT(HCAN20, 0x900), INTC_VECT(HCAN21, 0x920), 53 INTC_VECT(HCAN20, 0x900), INTC_VECT(HCAN21, 0x920),
@@ -75,23 +71,18 @@ static struct intc_vect vectors[] __initdata = {
75 INTC_VECT(MFI, 0xe80), /* 0xf80 according to data sheet */ 71 INTC_VECT(MFI, 0xe80), /* 0xf80 according to data sheet */
76 INTC_VECT(ADC, 0xf80), INTC_VECT(CMT, 0xfa0), 72 INTC_VECT(ADC, 0xf80), INTC_VECT(CMT, 0xfa0),
77 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 73 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
78 INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460), 74 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
79 INTC_VECT(WDT, 0x560), 75 INTC_VECT(WDT, 0x560),
80 INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0), 76 INTC_VECT(REF, 0x580), INTC_VECT(REF, 0x5a0),
81}; 77};
82 78
83static struct intc_group groups[] __initdata = { 79static struct intc_group groups[] __initdata = {
84 INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
85 DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5,
86 DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE),
87 INTC_GROUP(DMABRG, DMABRG0, DMABRG1, DMABRG2), 80 INTC_GROUP(DMABRG, DMABRG0, DMABRG1, DMABRG2),
88 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI), 81 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
89 INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI), 82 INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
90 INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI), 83 INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
91 INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI), 84 INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
92 INTC_GROUP(MMCIF, MMCIF0, MMCIF1, MMCIF2, MMCIF3), 85 INTC_GROUP(MMCIF, MMCIF0, MMCIF1, MMCIF2, MMCIF3),
93 INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
94 INTC_GROUP(REF, REF_RCMI, REF_ROVI),
95}; 86};
96 87
97static struct intc_mask_reg mask_registers[] __initdata = { 88static struct intc_mask_reg mask_registers[] __initdata = {