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authorMatt Carlson <mcarlson@broadcom.com>2008-11-21 20:22:19 -0500
committerDavid S. Miller <davem@davemloft.net>2008-11-21 20:22:19 -0500
commit321d32a052d6b5f71111ebad4fbebea5577f8974 (patch)
tree76dae255ad9ae62ea8e3bf1e147a3bf0b1d0bfac
parent22435849a6dcde2ce10d1870aba461a54e347fe3 (diff)
tg3: Add 57780 support
This patch adds support for the 57780 ASIC revision. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat
-rw-r--r--drivers/net/tg3.c239
-rw-r--r--drivers/net/tg3.h14
2 files changed, 175 insertions, 78 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 07bf05673da7..d6d50a6ad6db 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -213,6 +213,10 @@ static struct pci_device_id tg3_pci_tbl[] = {
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)}, 213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)}, 214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5785)}, 215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5785)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57720)},
216 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)}, 220 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
217 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)}, 221 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
218 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)}, 222 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
@@ -1036,6 +1040,9 @@ static int tg3_mdio_init(struct tg3 *tp)
1036 } 1040 }
1037 1041
1038 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { 1042 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1043 case TG3_PHY_ID_BCM57780:
1044 phydev->interface = PHY_INTERFACE_MODE_GMII;
1045 break;
1039 case TG3_PHY_ID_BCM50610: 1046 case TG3_PHY_ID_BCM50610:
1040 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE) 1047 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1041 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE; 1048 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
@@ -1409,10 +1416,13 @@ static int tg3_phy_init(struct tg3 *tp)
1409 switch (phydev->interface) { 1416 switch (phydev->interface) {
1410 case PHY_INTERFACE_MODE_GMII: 1417 case PHY_INTERFACE_MODE_GMII:
1411 case PHY_INTERFACE_MODE_RGMII: 1418 case PHY_INTERFACE_MODE_RGMII:
1412 phydev->supported &= (PHY_GBIT_FEATURES | 1419 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1413 SUPPORTED_Pause | 1420 phydev->supported &= (PHY_GBIT_FEATURES |
1414 SUPPORTED_Asym_Pause); 1421 SUPPORTED_Pause |
1415 break; 1422 SUPPORTED_Asym_Pause);
1423 break;
1424 }
1425 /* fallthru */
1416 case PHY_INTERFACE_MODE_MII: 1426 case PHY_INTERFACE_MODE_MII:
1417 phydev->supported &= (PHY_BASIC_FEATURES | 1427 phydev->supported &= (PHY_BASIC_FEATURES |
1418 SUPPORTED_Pause | 1428 SUPPORTED_Pause |
@@ -5991,11 +6001,7 @@ static int tg3_chip_reset(struct tg3 *tp)
5991 tg3_save_pci_state(tp); 6001 tg3_save_pci_state(tp);
5992 6002
5993 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || 6003 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
5994 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || 6004 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
5995 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
5996 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
5997 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
5998 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
5999 tw32(GRC_FASTBOOT_PC, 0); 6005 tw32(GRC_FASTBOOT_PC, 0);
6000 6006
6001 /* 6007 /*
@@ -7511,7 +7517,8 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7511 RDMAC_MODE_LNGREAD_ENAB); 7517 RDMAC_MODE_LNGREAD_ENAB);
7512 7518
7513 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || 7519 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7514 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) 7520 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7521 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7515 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB | 7522 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7516 RDMAC_MODE_MBUF_RBD_CRPT_ENAB | 7523 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7517 RDMAC_MODE_MBUF_SBD_CRPT_ENAB; 7524 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
@@ -7680,11 +7687,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7680 } 7687 }
7681 7688
7682 /* Enable host coalescing bug fix */ 7689 /* Enable host coalescing bug fix */
7683 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) || 7690 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7684 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) ||
7685 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784) ||
7686 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) ||
7687 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785))
7688 val |= WDMAC_MODE_STATUS_TAG_FIX; 7691 val |= WDMAC_MODE_STATUS_TAG_FIX;
7689 7692
7690 tw32_f(WDMAC_MODE, val); 7693 tw32_f(WDMAC_MODE, val);
@@ -7745,10 +7748,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7745 udelay(100); 7748 udelay(100);
7746 7749
7747 tp->rx_mode = RX_MODE_ENABLE; 7750 tp->rx_mode = RX_MODE_ENABLE;
7748 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || 7751 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7749 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7750 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
7751 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
7752 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE; 7752 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7753 7753
7754 tw32_f(MAC_RX_MODE, tp->rx_mode); 7754 tw32_f(MAC_RX_MODE, tp->rx_mode);
@@ -9303,7 +9303,8 @@ static int tg3_set_tso(struct net_device *dev, u32 value)
9303 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || 9303 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9304 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && 9304 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9305 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) || 9305 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9306 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) 9306 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9307 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9307 dev->features |= NETIF_F_TSO_ECN; 9308 dev->features |= NETIF_F_TSO_ECN;
9308 } else 9309 } else
9309 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN); 9310 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
@@ -9558,11 +9559,7 @@ static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9558 return 0; 9559 return 0;
9559 } 9560 }
9560 9561
9561 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || 9562 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9562 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9563 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9564 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9565 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
9566 ethtool_op_set_tx_ipv6_csum(dev, data); 9563 ethtool_op_set_tx_ipv6_csum(dev, data);
9567 else 9564 else
9568 ethtool_op_set_tx_csum(dev, data); 9565 ethtool_op_set_tx_csum(dev, data);
@@ -10079,18 +10076,13 @@ static int tg3_test_memory(struct tg3 *tp)
10079 int err = 0; 10076 int err = 0;
10080 int i; 10077 int i;
10081 10078
10082 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { 10079 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10083 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || 10080 mem_tbl = mem_tbl_5755;
10084 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || 10081 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10085 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || 10082 mem_tbl = mem_tbl_5906;
10086 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || 10083 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10087 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) 10084 mem_tbl = mem_tbl_5705;
10088 mem_tbl = mem_tbl_5755; 10085 else
10089 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10090 mem_tbl = mem_tbl_5906;
10091 else
10092 mem_tbl = mem_tbl_5705;
10093 } else
10094 mem_tbl = mem_tbl_570x; 10086 mem_tbl = mem_tbl_570x;
10095 10087
10096 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) { 10088 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
@@ -10294,9 +10286,7 @@ static int tg3_test_loopback(struct tg3 *tp)
10294 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD) 10286 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10295 tg3_phy_toggle_apd(tp, false); 10287 tg3_phy_toggle_apd(tp, false);
10296 10288
10297 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || 10289 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10298 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
10299 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
10300 int i; 10290 int i;
10301 u32 status; 10291 u32 status;
10302 10292
@@ -10323,9 +10313,7 @@ static int tg3_test_loopback(struct tg3 *tp)
10323 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK)) 10313 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10324 err |= TG3_MAC_LOOPBACK_FAILED; 10314 err |= TG3_MAC_LOOPBACK_FAILED;
10325 10315
10326 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || 10316 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10327 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
10328 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
10329 tw32(TG3_CPMU_CTRL, cpmuctrl); 10317 tw32(TG3_CPMU_CTRL, cpmuctrl);
10330 10318
10331 /* Release the mutex */ 10319 /* Release the mutex */
@@ -10944,6 +10932,102 @@ static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
10944 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; 10932 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10945} 10933}
10946 10934
10935static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
10936{
10937 u32 nvcfg1;
10938
10939 nvcfg1 = tr32(NVRAM_CFG1);
10940
10941 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10942 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10943 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10944 tp->nvram_jedecnum = JEDEC_ATMEL;
10945 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10946 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10947
10948 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10949 tw32(NVRAM_CFG1, nvcfg1);
10950 return;
10951 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10952 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10953 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10954 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10955 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10956 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10957 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10958 tp->nvram_jedecnum = JEDEC_ATMEL;
10959 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10960 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10961
10962 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10963 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10964 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10965 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10966 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10967 break;
10968 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10969 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10970 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10971 break;
10972 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10973 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10974 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10975 break;
10976 }
10977 break;
10978 case FLASH_5752VENDOR_ST_M45PE10:
10979 case FLASH_5752VENDOR_ST_M45PE20:
10980 case FLASH_5752VENDOR_ST_M45PE40:
10981 tp->nvram_jedecnum = JEDEC_ST;
10982 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10983 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10984
10985 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10986 case FLASH_5752VENDOR_ST_M45PE10:
10987 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10988 break;
10989 case FLASH_5752VENDOR_ST_M45PE20:
10990 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10991 break;
10992 case FLASH_5752VENDOR_ST_M45PE40:
10993 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10994 break;
10995 }
10996 break;
10997 default:
10998 return;
10999 }
11000
11001 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11002 case FLASH_5752PAGE_SIZE_256:
11003 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11004 tp->nvram_pagesize = 256;
11005 break;
11006 case FLASH_5752PAGE_SIZE_512:
11007 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11008 tp->nvram_pagesize = 512;
11009 break;
11010 case FLASH_5752PAGE_SIZE_1K:
11011 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11012 tp->nvram_pagesize = 1024;
11013 break;
11014 case FLASH_5752PAGE_SIZE_2K:
11015 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11016 tp->nvram_pagesize = 2048;
11017 break;
11018 case FLASH_5752PAGE_SIZE_4K:
11019 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11020 tp->nvram_pagesize = 4096;
11021 break;
11022 case FLASH_5752PAGE_SIZE_264:
11023 tp->nvram_pagesize = 264;
11024 break;
11025 case FLASH_5752PAGE_SIZE_528:
11026 tp->nvram_pagesize = 528;
11027 break;
11028 }
11029}
11030
10947/* Chips other than 5700/5701 use the NVRAM for fetching info. */ 11031/* Chips other than 5700/5701 use the NVRAM for fetching info. */
10948static void __devinit tg3_nvram_init(struct tg3 *tp) 11032static void __devinit tg3_nvram_init(struct tg3 *tp)
10949{ 11033{
@@ -10984,6 +11068,8 @@ static void __devinit tg3_nvram_init(struct tg3 *tp)
10984 tg3_get_5761_nvram_info(tp); 11068 tg3_get_5761_nvram_info(tp);
10985 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) 11069 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10986 tg3_get_5906_nvram_info(tp); 11070 tg3_get_5906_nvram_info(tp);
11071 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11072 tg3_get_57780_nvram_info(tp);
10987 else 11073 else
10988 tg3_get_nvram_info(tp); 11074 tg3_get_nvram_info(tp);
10989 11075
@@ -11304,12 +11390,8 @@ static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11304 if (i == (len - 4)) 11390 if (i == (len - 4))
11305 nvram_cmd |= NVRAM_CMD_LAST; 11391 nvram_cmd |= NVRAM_CMD_LAST;
11306 11392
11307 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) && 11393 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11308 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) && 11394 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11309 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
11310 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784) &&
11311 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) &&
11312 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) &&
11313 (tp->nvram_jedecnum == JEDEC_ST) && 11395 (tp->nvram_jedecnum == JEDEC_ST) &&
11314 (nvram_cmd & NVRAM_CMD_FIRST)) { 11396 (nvram_cmd & NVRAM_CMD_FIRST)) {
11315 11397
@@ -11630,8 +11712,8 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
11630 if (cfg2 & (1 << 18)) 11712 if (cfg2 & (1 << 18))
11631 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS; 11713 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
11632 11714
11633 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && 11715 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11634 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX && 11716 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
11635 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN)) 11717 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11636 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD; 11718 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11637 11719
@@ -12130,7 +12212,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
12130 12212
12131 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV, 12213 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12132 &prod_id_asic_rev); 12214 &prod_id_asic_rev);
12133 tp->pci_chip_rev_id = prod_id_asic_rev & PROD_ID_ASIC_REV_MASK; 12215 tp->pci_chip_rev_id = prod_id_asic_rev;
12134 } 12216 }
12135 12217
12136 /* Wrong chip ID in 5752 A0. This code can be removed later 12218 /* Wrong chip ID in 5752 A0. This code can be removed later
@@ -12279,14 +12361,19 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
12279 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) 12361 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
12280 tp->pdev_peer = tg3_find_peer(tp); 12362 tp->pdev_peer = tg3_find_peer(tp);
12281 12363
12282 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || 12364 /* Intentionally exclude ASIC_REV_5906 */
12283 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || 12365 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12284 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12285 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || 12366 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12286 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || 12367 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12287 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || 12368 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12288 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || 12369 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12370 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12371 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
12372
12373 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12374 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12289 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 || 12375 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
12376 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12290 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) 12377 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12291 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS; 12378 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12292 12379
@@ -12303,11 +12390,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
12303 tp->pdev_peer == tp->pdev)) 12390 tp->pdev_peer == tp->pdev))
12304 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI; 12391 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12305 12392
12306 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || 12393 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12307 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12308 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12309 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12310 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12311 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { 12394 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12312 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2; 12395 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
12313 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI; 12396 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
@@ -12342,7 +12425,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
12342 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) 12425 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12343 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2; 12426 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
12344 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || 12427 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12345 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) 12428 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12429 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12346 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG; 12430 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
12347 } 12431 }
12348 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { 12432 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
@@ -12513,7 +12597,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
12513 12597
12514 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || 12598 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12515 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || 12599 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12516 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) 12600 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12601 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12517 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT; 12602 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12518 12603
12519 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state(). 12604 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
@@ -12531,7 +12616,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
12531 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) 12616 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12532 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; 12617 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
12533 12618
12534 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) 12619 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12620 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12535 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; 12621 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12536 12622
12537 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761) { 12623 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761) {
@@ -12589,7 +12675,10 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
12589 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) 12675 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12590 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG; 12676 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12591 12677
12592 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { 12678 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
12679 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906 &&
12680 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12681 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780) {
12593 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || 12682 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12594 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || 12683 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12595 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || 12684 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
@@ -12599,8 +12688,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
12599 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG; 12688 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
12600 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M) 12689 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12601 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM; 12690 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
12602 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906 && 12691 } else
12603 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
12604 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG; 12692 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12605 } 12693 }
12606 12694
@@ -12621,7 +12709,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
12621 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX) 12709 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
12622 tp->coalesce_mode |= HOSTCC_MODE_32BYTE; 12710 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
12623 12711
12624 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) 12712 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12713 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12625 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB; 12714 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
12626 12715
12627 err = tg3_mdio_init(tp); 12716 err = tg3_mdio_init(tp);
@@ -12706,6 +12795,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
12706 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F || 12795 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
12707 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F || 12796 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
12708 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) || 12797 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
12798 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
12709 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) 12799 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12710 tp->tg3_flags |= TG3_FLAG_10_100_ONLY; 12800 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
12711 12801
@@ -13623,11 +13713,7 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
13623 goto err_out_iounmap; 13713 goto err_out_iounmap;
13624 } 13714 }
13625 13715
13626 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || 13716 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13627 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13628 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13629 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13630 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13631 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) 13717 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13632 dev->netdev_ops = &tg3_netdev_ops; 13718 dev->netdev_ops = &tg3_netdev_ops;
13633 else 13719 else
@@ -13700,7 +13786,8 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
13700 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || 13786 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13701 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && 13787 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13702 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) || 13788 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
13703 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) 13789 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13790 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13704 dev->features |= NETIF_F_TSO_ECN; 13791 dev->features |= NETIF_F_TSO_ECN;
13705 } 13792 }
13706 13793
@@ -13753,11 +13840,7 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
13753 */ 13840 */
13754 if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) { 13841 if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
13755 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG; 13842 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
13756 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || 13843 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13757 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13758 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13759 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13760 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
13761 dev->features |= NETIF_F_IPV6_CSUM; 13844 dev->features |= NETIF_F_IPV6_CSUM;
13762 13845
13763 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS; 13846 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 42f60ef4fa39..61556764a505 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -40,6 +40,10 @@
40#define TG3PCI_DEVICE_TIGON3_4 0x1647 /* BCM5703 */ 40#define TG3PCI_DEVICE_TIGON3_4 0x1647 /* BCM5703 */
41#define TG3PCI_DEVICE_TIGON3_5761S 0x1688 41#define TG3PCI_DEVICE_TIGON3_5761S 0x1688
42#define TG3PCI_DEVICE_TIGON3_5761SE 0x1689 42#define TG3PCI_DEVICE_TIGON3_5761SE 0x1689
43#define TG3PCI_DEVICE_TIGON3_57780 0x1692
44#define TG3PCI_DEVICE_TIGON3_57760 0x1690
45#define TG3PCI_DEVICE_TIGON3_57790 0x1694
46#define TG3PCI_DEVICE_TIGON3_57720 0x168c
43#define TG3PCI_COMMAND 0x00000004 47#define TG3PCI_COMMAND 0x00000004
44#define TG3PCI_STATUS 0x00000006 48#define TG3PCI_STATUS 0x00000006
45#define TG3PCI_CCREVID 0x00000008 49#define TG3PCI_CCREVID 0x00000008
@@ -131,6 +135,7 @@
131#define ASIC_REV_5784 0x5784 135#define ASIC_REV_5784 0x5784
132#define ASIC_REV_5761 0x5761 136#define ASIC_REV_5761 0x5761
133#define ASIC_REV_5785 0x5785 137#define ASIC_REV_5785 0x5785
138#define ASIC_REV_57780 0x57780
134#define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8) 139#define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8)
135#define CHIPREV_5700_AX 0x70 140#define CHIPREV_5700_AX 0x70
136#define CHIPREV_5700_BX 0x71 141#define CHIPREV_5700_BX 0x71
@@ -1648,6 +1653,12 @@
1648#define FLASH_5761VENDOR_ST_A_M45PE40 0x02000000 1653#define FLASH_5761VENDOR_ST_A_M45PE40 0x02000000
1649#define FLASH_5761VENDOR_ST_A_M45PE80 0x02000002 1654#define FLASH_5761VENDOR_ST_A_M45PE80 0x02000002
1650#define FLASH_5761VENDOR_ST_A_M45PE16 0x02000003 1655#define FLASH_5761VENDOR_ST_A_M45PE16 0x02000003
1656#define FLASH_57780VENDOR_ATMEL_AT45DB011D 0x00400000
1657#define FLASH_57780VENDOR_ATMEL_AT45DB011B 0x03400000
1658#define FLASH_57780VENDOR_ATMEL_AT45DB021D 0x00400002
1659#define FLASH_57780VENDOR_ATMEL_AT45DB021B 0x03400002
1660#define FLASH_57780VENDOR_ATMEL_AT45DB041D 0x00400001
1661#define FLASH_57780VENDOR_ATMEL_AT45DB041B 0x03400001
1651#define NVRAM_CFG1_5752PAGE_SIZE_MASK 0x70000000 1662#define NVRAM_CFG1_5752PAGE_SIZE_MASK 0x70000000
1652#define FLASH_5752PAGE_SIZE_256 0x00000000 1663#define FLASH_5752PAGE_SIZE_256 0x00000000
1653#define FLASH_5752PAGE_SIZE_512 0x10000000 1664#define FLASH_5752PAGE_SIZE_512 0x10000000
@@ -1655,6 +1666,7 @@
1655#define FLASH_5752PAGE_SIZE_2K 0x30000000 1666#define FLASH_5752PAGE_SIZE_2K 0x30000000
1656#define FLASH_5752PAGE_SIZE_4K 0x40000000 1667#define FLASH_5752PAGE_SIZE_4K 0x40000000
1657#define FLASH_5752PAGE_SIZE_264 0x50000000 1668#define FLASH_5752PAGE_SIZE_264 0x50000000
1669#define FLASH_5752PAGE_SIZE_528 0x60000000
1658#define NVRAM_CFG2 0x00007018 1670#define NVRAM_CFG2 0x00007018
1659#define NVRAM_CFG3 0x0000701c 1671#define NVRAM_CFG3 0x0000701c
1660#define NVRAM_SWARB 0x00007020 1672#define NVRAM_SWARB 0x00007020
@@ -2632,6 +2644,7 @@ struct tg3 {
2632#define TG3_FLG3_RGMII_EXT_IBND_TX_EN 0x00000400 2644#define TG3_FLG3_RGMII_EXT_IBND_TX_EN 0x00000400
2633#define TG3_FLG3_CLKREQ_BUG 0x00000800 2645#define TG3_FLG3_CLKREQ_BUG 0x00000800
2634#define TG3_FLG3_PHY_ENABLE_APD 0x00001000 2646#define TG3_FLG3_PHY_ENABLE_APD 0x00001000
2647#define TG3_FLG3_5755_PLUS 0x00002000
2635 2648
2636 struct timer_list timer; 2649 struct timer_list timer;
2637 u16 timer_counter; 2650 u16 timer_counter;
@@ -2709,6 +2722,7 @@ struct tg3 {
2709#define TG3_PHY_ID_BCMAC131 0x143bc70 2722#define TG3_PHY_ID_BCMAC131 0x143bc70
2710#define TG3_PHY_ID_RTL8211C 0x001cc910 2723#define TG3_PHY_ID_RTL8211C 0x001cc910
2711#define TG3_PHY_ID_RTL8201E 0x00008200 2724#define TG3_PHY_ID_RTL8201E 0x00008200
2725#define TG3_PHY_ID_BCM57780 0x03625d90
2712#define TG3_PHY_OUI_MASK 0xfffffc00 2726#define TG3_PHY_OUI_MASK 0xfffffc00
2713#define TG3_PHY_OUI_1 0x00206000 2727#define TG3_PHY_OUI_1 0x00206000
2714#define TG3_PHY_OUI_2 0x0143bc00 2728#define TG3_PHY_OUI_2 0x0143bc00
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-20 02:33:36 -0500