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authorBryan Wu <cooloney@kernel.org>2008-11-18 04:48:21 -0500
committerBryan Wu <cooloney@kernel.org>2008-11-18 04:48:21 -0500
commit2f6f4bcdd611cb968b800f7569c4383727856668 (patch)
treee9de0755bfa40a932c2ca44e532aef8ae704ab9b
parent2563265bdb5fb21396cdc2125c8260e57f7c3991 (diff)
Blackfin arch: add support for Blackfin latest processor family BF51x
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat
-rw-r--r--arch/blackfin/Kconfig48
-rw-r--r--arch/blackfin/Makefile8
-rw-r--r--arch/blackfin/configs/BF518F-EZBRD_defconfig1130
-rw-r--r--arch/blackfin/include/asm/gpio.h51
-rw-r--r--arch/blackfin/kernel/bfin_gpio.c22
-rw-r--r--arch/blackfin/mach-bf518/Kconfig233
-rw-r--r--arch/blackfin/mach-bf518/Makefile7
-rw-r--r--arch/blackfin/mach-bf518/boards/Kconfig12
-rw-r--r--arch/blackfin/mach-bf518/boards/Makefile5
-rw-r--r--arch/blackfin/mach-bf518/boards/ezbrd.c613
-rw-r--r--arch/blackfin/mach-bf518/dma.c118
-rw-r--r--arch/blackfin/mach-bf518/head.S146
-rw-r--r--arch/blackfin/mach-bf518/include/mach/anomaly.h77
-rw-r--r--arch/blackfin/mach-bf518/include/mach/bf518.h132
-rw-r--r--arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h169
-rw-r--r--arch/blackfin/mach-bf518/include/mach/bfin_sir.h142
-rw-r--r--arch/blackfin/mach-bf518/include/mach/blackfin.h105
-rw-r--r--arch/blackfin/mach-bf518/include/mach/cdefBF512.h46
-rw-r--r--arch/blackfin/mach-bf518/include/mach/cdefBF514.h48
-rw-r--r--arch/blackfin/mach-bf518/include/mach/cdefBF516.h48
-rw-r--r--arch/blackfin/mach-bf518/include/mach/cdefBF518.h48
-rw-r--r--arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h1204
-rw-r--r--arch/blackfin/mach-bf518/include/mach/defBF512.h42
-rw-r--r--arch/blackfin/mach-bf518/include/mach/defBF514.h113
-rw-r--r--arch/blackfin/mach-bf518/include/mach/defBF516.h490
-rw-r--r--arch/blackfin/mach-bf518/include/mach/defBF518.h516
-rw-r--r--arch/blackfin/mach-bf518/include/mach/defBF51x_base.h1940
-rw-r--r--arch/blackfin/mach-bf518/include/mach/dma.h57
-rw-r--r--arch/blackfin/mach-bf518/include/mach/irq.h260
-rw-r--r--arch/blackfin/mach-bf518/include/mach/mem_init.h310
-rw-r--r--arch/blackfin/mach-bf518/include/mach/mem_map.h102
-rw-r--r--arch/blackfin/mach-bf518/include/mach/portmux.h188
-rw-r--r--arch/blackfin/mach-bf518/ints-priority.c99
-rw-r--r--arch/blackfin/mach-common/dpmc_modes.S2
-rw-r--r--arch/blackfin/mach-common/ints-priority.c20
-rw-r--r--arch/blackfin/mach-common/pm.c4
36 files changed, 8524 insertions, 31 deletions
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index be54e36e8b69..19b43f37e1a3 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -77,6 +77,26 @@ choice
77 prompt "CPU" 77 prompt "CPU"
78 default BF533 78 default BF533
79 79
80config BF512
81 bool "BF512"
82 help
83 BF512 Processor Support.
84
85config BF514
86 bool "BF514"
87 help
88 BF514 Processor Support.
89
90config BF516
91 bool "BF516"
92 help
93 BF516 Processor Support.
94
95config BF518
96 bool "BF518"
97 help
98 BF518 Processor Support.
99
80config BF522 100config BF522
81 bool "BF522" 101 bool "BF522"
82 help 102 help
@@ -181,27 +201,27 @@ endchoice
181 201
182config BF_REV_MIN 202config BF_REV_MIN
183 int 203 int
184 default 0 if (BF52x || BF54x) 204 default 0 if (BF51x || BF52x || BF54x)
185 default 2 if (BF537 || BF536 || BF534) 205 default 2 if (BF537 || BF536 || BF534)
186 default 3 if (BF561 ||BF533 || BF532 || BF531) 206 default 3 if (BF561 ||BF533 || BF532 || BF531)
187 default 4 if (BF538 || BF539) 207 default 4 if (BF538 || BF539)
188 208
189config BF_REV_MAX 209config BF_REV_MAX
190 int 210 int
191 default 2 if (BF52x || BF54x) 211 default 2 if (BF51x || BF52x || BF54x)
192 default 3 if (BF537 || BF536 || BF534) 212 default 3 if (BF537 || BF536 || BF534)
193 default 5 if (BF561|| BF538 || BF539) 213 default 5 if (BF561 || BF538 || BF539)
194 default 6 if (BF533 || BF532 || BF531) 214 default 6 if (BF533 || BF532 || BF531)
195 215
196choice 216choice
197 prompt "Silicon Rev" 217 prompt "Silicon Rev"
198 default BF_REV_0_1 if (BF52x || BF54x) 218 default BF_REV_0_1 if (BF51x || BF52x || BF54x)
199 default BF_REV_0_2 if (BF534 || BF536 || BF537) 219 default BF_REV_0_2 if (BF534 || BF536 || BF537)
200 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF561) 220 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF561)
201 221
202config BF_REV_0_0 222config BF_REV_0_0
203 bool "0.0" 223 bool "0.0"
204 depends on (BF52x || BF54x) 224 depends on (BF51x || BF52x || BF54x)
205 225
206config BF_REV_0_1 226config BF_REV_0_1
207 bool "0.1" 227 bool "0.1"
@@ -235,6 +255,11 @@ config BF_REV_NONE
235 255
236endchoice 256endchoice
237 257
258config BF51x
259 bool
260 depends on (BF512 || BF514 || BF516 || BF518)
261 default y
262
238config BF52x 263config BF52x
239 bool 264 bool
240 depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527) 265 depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
@@ -282,6 +307,7 @@ config MEM_MT48LC32M16A2TG_75
282 depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD) 307 depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)
283 default y 308 default y
284 309
310source "arch/blackfin/mach-bf518/Kconfig"
285source "arch/blackfin/mach-bf527/Kconfig" 311source "arch/blackfin/mach-bf527/Kconfig"
286source "arch/blackfin/mach-bf533/Kconfig" 312source "arch/blackfin/mach-bf533/Kconfig"
287source "arch/blackfin/mach-bf561/Kconfig" 313source "arch/blackfin/mach-bf561/Kconfig"
@@ -330,7 +356,7 @@ config CLKIN_HZ
330 int "Frequency of the crystal on the board in Hz" 356 int "Frequency of the crystal on the board in Hz"
331 default "11059200" if BFIN533_STAMP 357 default "11059200" if BFIN533_STAMP
332 default "27000000" if BFIN533_EZKIT 358 default "27000000" if BFIN533_EZKIT
333 default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN538_EZKIT) 359 default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN538_EZKIT || BFIN518F-EZBRD)
334 default "30000000" if BFIN561_EZKIT 360 default "30000000" if BFIN561_EZKIT
335 default "24576000" if PNAV10 361 default "24576000" if PNAV10
336 default "10000000" if BFIN532_IP0X 362 default "10000000" if BFIN532_IP0X
@@ -370,7 +396,7 @@ config VCO_MULT
370 default "22" if BFIN533_BLUETECHNIX_CM 396 default "22" if BFIN533_BLUETECHNIX_CM
371 default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM) 397 default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
372 default "20" if BFIN561_EZKIT 398 default "20" if BFIN561_EZKIT
373 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD) 399 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
374 help 400 help
375 This controls the frequency of the on-chip PLL. This can be between 1 and 64. 401 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
376 PLL Frequency = (Crystal Frequency) * (this setting) 402 PLL Frequency = (Crystal Frequency) * (this setting)
@@ -432,6 +458,10 @@ config MAX_MEM_SIZE
432# 458#
433config MAX_VCO_HZ 459config MAX_VCO_HZ
434 int 460 int
461 default 400000000 if BF512
462 default 400000000 if BF514
463 default 400000000 if BF516
464 default 400000000 if BF518
435 default 600000000 if BF522 465 default 600000000 if BF522
436 default 400000000 if BF523 466 default 400000000 if BF523
437 default 400000000 if BF524 467 default 400000000 if BF524
@@ -1025,7 +1055,7 @@ comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1025 1055
1026config PM_BFIN_WAKE_PH6 1056config PM_BFIN_WAKE_PH6
1027 bool "Allow Wake-Up from on-chip PHY or PH6 GP" 1057 bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1028 depends on PM && (BF52x || BF534 || BF536 || BF537) 1058 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1029 default n 1059 default n
1030 help 1060 help
1031 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up) 1061 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
diff --git a/arch/blackfin/Makefile b/arch/blackfin/Makefile
index ce45df3708e8..2faad124db59 100644
--- a/arch/blackfin/Makefile
+++ b/arch/blackfin/Makefile
@@ -21,6 +21,10 @@ KALLSYMS += --symbol-prefix=_
21KBUILD_DEFCONFIG := BF537-STAMP_defconfig 21KBUILD_DEFCONFIG := BF537-STAMP_defconfig
22 22
23# setup the machine name and the machine dependent settings 23# setup the machine name and the machine dependent settings
24machine-$(CONFIG_BF512) := bf518
25machine-$(CONFIG_BF514) := bf518
26machine-$(CONFIG_BF516) := bf518
27machine-$(CONFIG_BF518) := bf518
24machine-$(CONFIG_BF522) := bf527 28machine-$(CONFIG_BF522) := bf527
25machine-$(CONFIG_BF523) := bf527 29machine-$(CONFIG_BF523) := bf527
26machine-$(CONFIG_BF524) := bf527 30machine-$(CONFIG_BF524) := bf527
@@ -44,6 +48,10 @@ machine-$(CONFIG_BF561) := bf561
44MACHINE := $(machine-y) 48MACHINE := $(machine-y)
45export MACHINE 49export MACHINE
46 50
51cpu-$(CONFIG_BF512) := bf512
52cpu-$(CONFIG_BF514) := bf514
53cpu-$(CONFIG_BF516) := bf516
54cpu-$(CONFIG_BF518) := bf518
47cpu-$(CONFIG_BF522) := bf522 55cpu-$(CONFIG_BF522) := bf522
48cpu-$(CONFIG_BF523) := bf523 56cpu-$(CONFIG_BF523) := bf523
49cpu-$(CONFIG_BF524) := bf524 57cpu-$(CONFIG_BF524) := bf524
diff --git a/arch/blackfin/configs/BF518F-EZBRD_defconfig b/arch/blackfin/configs/BF518F-EZBRD_defconfig
new file mode 100644
index 000000000000..f4c4fd7d0e7b
--- /dev/null
+++ b/arch/blackfin/configs/BF518F-EZBRD_defconfig
@@ -0,0 +1,1130 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26.5
4# Thu Oct 23 21:38:19 2008
5#
6# CONFIG_MMU is not set
7# CONFIG_FPU is not set
8CONFIG_RWSEM_GENERIC_SPINLOCK=y
9# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
10CONFIG_BLACKFIN=y
11CONFIG_ZONE_DMA=y
12CONFIG_GENERIC_FIND_NEXT_BIT=y
13CONFIG_GENERIC_HWEIGHT=y
14CONFIG_GENERIC_HARDIRQS=y
15CONFIG_GENERIC_IRQ_PROBE=y
16CONFIG_GENERIC_GPIO=y
17CONFIG_FORCE_MAX_ZONEORDER=14
18CONFIG_GENERIC_CALIBRATE_DELAY=y
19CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
20
21#
22# General setup
23#
24CONFIG_EXPERIMENTAL=y
25CONFIG_BROKEN_ON_SMP=y
26CONFIG_INIT_ENV_ARG_LIMIT=32
27CONFIG_LOCALVERSION=""
28CONFIG_LOCALVERSION_AUTO=y
29CONFIG_SYSVIPC=y
30CONFIG_SYSVIPC_SYSCTL=y
31# CONFIG_POSIX_MQUEUE is not set
32# CONFIG_BSD_PROCESS_ACCT is not set
33# CONFIG_TASKSTATS is not set
34# CONFIG_AUDIT is not set
35CONFIG_IKCONFIG=y
36CONFIG_IKCONFIG_PROC=y
37CONFIG_LOG_BUF_SHIFT=14
38# CONFIG_CGROUPS is not set
39# CONFIG_GROUP_SCHED is not set
40# CONFIG_SYSFS_DEPRECATED is not set
41# CONFIG_SYSFS_DEPRECATED_V2 is not set
42# CONFIG_RELAY is not set
43# CONFIG_NAMESPACES is not set
44CONFIG_BLK_DEV_INITRD=y
45CONFIG_INITRAMFS_SOURCE=""
46# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
47CONFIG_SYSCTL=y
48CONFIG_EMBEDDED=y
49CONFIG_UID16=y
50CONFIG_SYSCTL_SYSCALL=y
51CONFIG_SYSCTL_SYSCALL_CHECK=y
52CONFIG_KALLSYMS=y
53# CONFIG_KALLSYMS_EXTRA_PASS is not set
54CONFIG_HOTPLUG=y
55CONFIG_PRINTK=y
56CONFIG_BUG=y
57CONFIG_ELF_CORE=y
58CONFIG_COMPAT_BRK=y
59CONFIG_BASE_FULL=y
60CONFIG_FUTEX=y
61CONFIG_ANON_INODES=y
62CONFIG_EPOLL=y
63CONFIG_SIGNALFD=y
64CONFIG_TIMERFD=y
65CONFIG_EVENTFD=y
66CONFIG_VM_EVENT_COUNTERS=y
67CONFIG_SLAB=y
68# CONFIG_SLUB is not set
69# CONFIG_SLOB is not set
70# CONFIG_PROFILING is not set
71# CONFIG_MARKERS is not set
72CONFIG_HAVE_OPROFILE=y
73# CONFIG_HAVE_KPROBES is not set
74# CONFIG_HAVE_KRETPROBES is not set
75# CONFIG_HAVE_DMA_ATTRS is not set
76CONFIG_SLABINFO=y
77CONFIG_RT_MUTEXES=y
78CONFIG_TINY_SHMEM=y
79CONFIG_BASE_SMALL=0
80CONFIG_MODULES=y
81# CONFIG_MODULE_FORCE_LOAD is not set
82CONFIG_MODULE_UNLOAD=y
83# CONFIG_MODULE_FORCE_UNLOAD is not set
84# CONFIG_MODVERSIONS is not set
85# CONFIG_MODULE_SRCVERSION_ALL is not set
86CONFIG_KMOD=y
87CONFIG_BLOCK=y
88# CONFIG_LBD is not set
89# CONFIG_BLK_DEV_IO_TRACE is not set
90# CONFIG_LSF is not set
91# CONFIG_BLK_DEV_BSG is not set
92
93#
94# IO Schedulers
95#
96CONFIG_IOSCHED_NOOP=y
97# CONFIG_IOSCHED_AS is not set
98# CONFIG_IOSCHED_DEADLINE is not set
99# CONFIG_IOSCHED_CFQ is not set
100# CONFIG_DEFAULT_AS is not set
101# CONFIG_DEFAULT_DEADLINE is not set
102# CONFIG_DEFAULT_CFQ is not set
103CONFIG_DEFAULT_NOOP=y
104CONFIG_DEFAULT_IOSCHED="noop"
105CONFIG_CLASSIC_RCU=y
106# CONFIG_PREEMPT_NONE is not set
107CONFIG_PREEMPT_VOLUNTARY=y
108# CONFIG_PREEMPT is not set
109
110#
111# Blackfin Processor Options
112#
113
114#
115# Processor and Board Settings
116#
117# CONFIG_BF512 is not set
118# CONFIG_BF514 is not set
119# CONFIG_BF516 is not set
120CONFIG_BF518=y
121# CONFIG_BF522 is not set
122# CONFIG_BF523 is not set
123# CONFIG_BF524 is not set
124# CONFIG_BF525 is not set
125# CONFIG_BF526 is not set
126# CONFIG_BF527 is not set
127# CONFIG_BF531 is not set
128# CONFIG_BF532 is not set
129# CONFIG_BF533 is not set
130# CONFIG_BF534 is not set
131# CONFIG_BF536 is not set
132# CONFIG_BF537 is not set
133# CONFIG_BF538 is not set
134# CONFIG_BF539 is not set
135# CONFIG_BF542 is not set
136# CONFIG_BF544 is not set
137# CONFIG_BF547 is not set
138# CONFIG_BF548 is not set
139# CONFIG_BF549 is not set
140# CONFIG_BF561 is not set
141CONFIG_BF_REV_MIN=0
142CONFIG_BF_REV_MAX=2
143CONFIG_BF_REV_0_0=y
144# CONFIG_BF_REV_0_1 is not set
145# CONFIG_BF_REV_0_2 is not set
146# CONFIG_BF_REV_0_3 is not set
147# CONFIG_BF_REV_0_4 is not set
148# CONFIG_BF_REV_0_5 is not set
149# CONFIG_BF_REV_0_6 is not set
150# CONFIG_BF_REV_ANY is not set
151# CONFIG_BF_REV_NONE is not set
152CONFIG_BF51x=y
153CONFIG_BFIN518F_EZBRD=y
154
155#
156# BF518 Specific Configuration
157#
158
159#
160# Alternative Multiplexing Scheme
161#
162# CONFIG_BF518_SPORT0_PORTF is not set
163CONFIG_BF518_SPORT0_PORTG=y
164CONFIG_BF518_SPORT0_TSCLK_PG10=y
165# CONFIG_BF518_SPORT0_TSCLK_PG14 is not set
166CONFIG_BF518_UART1_PORTF=y
167# CONFIG_BF518_UART1_PORTG is not set
168
169#
170# Interrupt Priority Assignment
171#
172
173#
174# Priority
175#
176CONFIG_IRQ_PLL_WAKEUP=7
177CONFIG_IRQ_DMA0_ERROR=7
178CONFIG_IRQ_DMAR0_BLK=7
179CONFIG_IRQ_DMAR1_BLK=7
180CONFIG_IRQ_DMAR0_OVR=7
181CONFIG_IRQ_DMAR1_OVR=7
182CONFIG_IRQ_PPI_ERROR=7
183CONFIG_IRQ_MAC_ERROR=7
184CONFIG_IRQ_SPORT0_ERROR=7
185CONFIG_IRQ_SPORT1_ERROR=7
186CONFIG_IRQ_PTP_ERROR=7
187CONFIG_IRQ_UART0_ERROR=7
188CONFIG_IRQ_UART1_ERROR=7
189CONFIG_IRQ_RTC=8
190CONFIG_IRQ_PPI=8
191CONFIG_IRQ_SPORT0_RX=9
192CONFIG_IRQ_SPORT0_TX=9
193CONFIG_IRQ_SPORT1_RX=9
194CONFIG_IRQ_SPORT1_TX=9
195CONFIG_IRQ_TWI=10
196CONFIG_IRQ_SPI0=10
197CONFIG_IRQ_UART0_RX=10
198CONFIG_IRQ_UART0_TX=10
199CONFIG_IRQ_UART1_RX=10
200CONFIG_IRQ_UART1_TX=10
201CONFIG_IRQ_OPTSEC=11
202CONFIG_IRQ_CNT=11
203CONFIG_IRQ_MAC_RX=11
204CONFIG_IRQ_PORTH_INTA=11
205CONFIG_IRQ_MAC_TX=11
206CONFIG_IRQ_PORTH_INTB=11
207CONFIG_IRQ_TMR0=12
208CONFIG_IRQ_TMR1=12
209CONFIG_IRQ_TMR2=12
210CONFIG_IRQ_TMR3=12
211CONFIG_IRQ_TMR4=12
212CONFIG_IRQ_TMR5=12
213CONFIG_IRQ_TMR6=12
214CONFIG_IRQ_TMR7=12
215CONFIG_IRQ_PORTG_INTA=12
216CONFIG_IRQ_PORTG_INTB=12
217CONFIG_IRQ_MEM_DMA0=13
218CONFIG_IRQ_MEM_DMA1=13
219CONFIG_IRQ_WATCH=13
220CONFIG_IRQ_PORTF_INTA=13
221CONFIG_IRQ_PORTF_INTB=13
222CONFIG_IRQ_SPI0_ERROR=7
223CONFIG_IRQ_SPI1_ERROR=7
224CONFIG_IRQ_RSI_INT0=7
225CONFIG_IRQ_RSI_INT1=7
226CONFIG_IRQ_PWM_TRIP=10
227CONFIG_IRQ_PWM_SYNC=10
228CONFIG_IRQ_PTP_STAT=10
229
230#
231# Board customizations
232#
233# CONFIG_CMDLINE_BOOL is not set
234CONFIG_BOOT_LOAD=0x1000
235CONFIG_ROM_BASE=0x20040000
236
237#
238# Clock/PLL Setup
239#
240CONFIG_CLKIN_HZ=25000000
241# CONFIG_BFIN_KERNEL_CLOCK is not set
242CONFIG_MAX_MEM_SIZE=512
243CONFIG_MAX_VCO_HZ=400000000
244CONFIG_MIN_VCO_HZ=50000000
245CONFIG_MAX_SCLK_HZ=133333333
246CONFIG_MIN_SCLK_HZ=27000000
247
248#
249# Kernel Timer/Scheduler
250#
251# CONFIG_HZ_100 is not set
252CONFIG_HZ_250=y
253# CONFIG_HZ_300 is not set
254# CONFIG_HZ_1000 is not set
255CONFIG_HZ=250
256# CONFIG_SCHED_HRTICK is not set
257CONFIG_GENERIC_TIME=y
258CONFIG_GENERIC_CLOCKEVENTS=y
259# CONFIG_CYCLES_CLOCKSOURCE is not set
260# CONFIG_TICK_ONESHOT is not set
261# CONFIG_NO_HZ is not set
262# CONFIG_HIGH_RES_TIMERS is not set
263CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
264
265#
266# Misc
267#
268CONFIG_BFIN_SCRATCH_REG_RETN=y
269# CONFIG_BFIN_SCRATCH_REG_RETE is not set
270# CONFIG_BFIN_SCRATCH_REG_CYCLES is not set
271
272#
273# Blackfin Kernel Optimizations
274#
275
276#
277# Memory Optimizations
278#
279CONFIG_I_ENTRY_L1=y
280CONFIG_EXCPT_IRQ_SYSC_L1=y
281CONFIG_DO_IRQ_L1=y
282CONFIG_CORE_TIMER_IRQ_L1=y
283CONFIG_IDLE_L1=y
284# CONFIG_SCHEDULE_L1 is not set
285CONFIG_ARITHMETIC_OPS_L1=y
286CONFIG_ACCESS_OK_L1=y
287# CONFIG_MEMSET_L1 is not set
288# CONFIG_MEMCPY_L1 is not set
289# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
290# CONFIG_IP_CHECKSUM_L1 is not set
291CONFIG_CACHELINE_ALIGNED_L1=y
292# CONFIG_SYSCALL_TAB_L1 is not set
293# CONFIG_CPLB_SWITCH_TAB_L1 is not set
294CONFIG_APP_STACK_L1=y
295
296#
297# Speed Optimizations
298#
299CONFIG_BFIN_INS_LOWOVERHEAD=y
300CONFIG_RAMKERNEL=y
301# CONFIG_ROMKERNEL is not set
302CONFIG_SELECT_MEMORY_MODEL=y
303CONFIG_FLATMEM_MANUAL=y
304# CONFIG_DISCONTIGMEM_MANUAL is not set
305# CONFIG_SPARSEMEM_MANUAL is not set
306CONFIG_FLATMEM=y
307CONFIG_FLAT_NODE_MEM_MAP=y
308# CONFIG_SPARSEMEM_STATIC is not set
309# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
310CONFIG_PAGEFLAGS_EXTENDED=y
311CONFIG_SPLIT_PTLOCK_CPUS=4
312# CONFIG_RESOURCES_64BIT is not set
313CONFIG_ZONE_DMA_FLAG=1
314CONFIG_VIRT_TO_BUS=y
315CONFIG_BFIN_GPTIMERS=y
316CONFIG_BFIN_DMA_5XX=y
317# CONFIG_DMA_UNCACHED_4M is not set
318# CONFIG_DMA_UNCACHED_2M is not set
319CONFIG_DMA_UNCACHED_1M=y
320# CONFIG_DMA_UNCACHED_NONE is not set
321
322#
323# Cache Support
324#
325CONFIG_BFIN_ICACHE=y
326CONFIG_BFIN_DCACHE=y
327# CONFIG_BFIN_DCACHE_BANKA is not set
328# CONFIG_BFIN_ICACHE_LOCK is not set
329CONFIG_BFIN_WB=y
330# CONFIG_BFIN_WT is not set
331# CONFIG_MPU is not set
332
333#
334# Asynchonous Memory Configuration
335#
336
337#
338# EBIU_AMGCTL Global Control
339#
340CONFIG_C_AMCKEN=y
341CONFIG_C_CDPRIO=y
342# CONFIG_C_AMBEN is not set
343# CONFIG_C_AMBEN_B0 is not set
344# CONFIG_C_AMBEN_B0_B1 is not set
345# CONFIG_C_AMBEN_B0_B1_B2 is not set
346CONFIG_C_AMBEN_ALL=y
347
348#
349# EBIU_AMBCTL Control
350#
351CONFIG_BANK_0=0x7BB0
352CONFIG_BANK_1=0x5554
353CONFIG_BANK_2=0x7BB0
354CONFIG_BANK_3=0xFFC0
355
356#
357# Bus options (PCI, PCMCIA, EISA, MCA, ISA)
358#
359# CONFIG_ARCH_SUPPORTS_MSI is not set
360# CONFIG_PCCARD is not set
361
362#
363# Executable file formats
364#
365CONFIG_BINFMT_ELF_FDPIC=y
366CONFIG_BINFMT_FLAT=y
367CONFIG_BINFMT_ZFLAT=y
368# CONFIG_BINFMT_SHARED_FLAT is not set
369# CONFIG_BINFMT_MISC is not set
370
371#
372# Power management options
373#
374# CONFIG_PM is not set
375CONFIG_ARCH_SUSPEND_POSSIBLE=y
376# CONFIG_PM_WAKEUP_BY_GPIO is not set
377
378#
379# CPU Frequency scaling
380#
381# CONFIG_CPU_FREQ is not set
382
383#
384# Networking
385#
386CONFIG_NET=y
387
388#
389# Networking options
390#
391CONFIG_PACKET=y
392# CONFIG_PACKET_MMAP is not set
393CONFIG_UNIX=y
394CONFIG_XFRM=y
395# CONFIG_XFRM_USER is not set
396# CONFIG_XFRM_SUB_POLICY is not set
397# CONFIG_XFRM_MIGRATE is not set
398# CONFIG_XFRM_STATISTICS is not set
399# CONFIG_NET_KEY is not set
400CONFIG_INET=y
401# CONFIG_IP_MULTICAST is not set
402# CONFIG_IP_ADVANCED_ROUTER is not set
403CONFIG_IP_FIB_HASH=y
404CONFIG_IP_PNP=y
405# CONFIG_IP_PNP_DHCP is not set
406# CONFIG_IP_PNP_BOOTP is not set
407# CONFIG_IP_PNP_RARP is not set
408# CONFIG_NET_IPIP is not set
409# CONFIG_NET_IPGRE is not set
410# CONFIG_ARPD is not set
411CONFIG_SYN_COOKIES=y
412# CONFIG_INET_AH is not set
413# CONFIG_INET_ESP is not set
414# CONFIG_INET_IPCOMP is not set
415# CONFIG_INET_XFRM_TUNNEL is not set
416# CONFIG_INET_TUNNEL is not set
417CONFIG_INET_XFRM_MODE_TRANSPORT=y
418CONFIG_INET_XFRM_MODE_TUNNEL=y
419CONFIG_INET_XFRM_MODE_BEET=y
420# CONFIG_INET_LRO is not set
421CONFIG_INET_DIAG=y
422CONFIG_INET_TCP_DIAG=y
423# CONFIG_TCP_CONG_ADVANCED is not set
424CONFIG_TCP_CONG_CUBIC=y
425CONFIG_DEFAULT_TCP_CONG="cubic"
426# CONFIG_TCP_MD5SIG is not set
427# CONFIG_IPV6 is not set
428# CONFIG_NETLABEL is not set
429# CONFIG_NETWORK_SECMARK is not set
430# CONFIG_NETFILTER is not set
431# CONFIG_IP_DCCP is not set
432# CONFIG_IP_SCTP is not set
433# CONFIG_TIPC is not set
434# CONFIG_ATM is not set
435# CONFIG_BRIDGE is not set
436# CONFIG_VLAN_8021Q is not set
437# CONFIG_DECNET is not set
438# CONFIG_LLC2 is not set
439# CONFIG_IPX is not set
440# CONFIG_ATALK is not set
441# CONFIG_X25 is not set
442# CONFIG_LAPB is not set
443# CONFIG_ECONET is not set
444# CONFIG_WAN_ROUTER is not set
445# CONFIG_NET_SCHED is not set
446
447#
448# Network testing
449#
450# CONFIG_NET_PKTGEN is not set
451# CONFIG_HAMRADIO is not set
452# CONFIG_CAN is not set
453# CONFIG_IRDA is not set
454# CONFIG_BT is not set
455# CONFIG_AF_RXRPC is not set
456
457#
458# Wireless
459#
460# CONFIG_CFG80211 is not set
461# CONFIG_WIRELESS_EXT is not set
462# CONFIG_MAC80211 is not set
463# CONFIG_IEEE80211 is not set
464# CONFIG_RFKILL is not set
465# CONFIG_NET_9P is not set
466
467#
468# Device Drivers
469#
470
471#
472# Generic Driver Options
473#
474CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
475CONFIG_STANDALONE=y
476CONFIG_PREVENT_FIRMWARE_BUILD=y
477# CONFIG_FW_LOADER is not set
478# CONFIG_SYS_HYPERVISOR is not set
479# CONFIG_CONNECTOR is not set
480CONFIG_MTD=y
481# CONFIG_MTD_DEBUG is not set
482# CONFIG_MTD_CONCAT is not set
483CONFIG_MTD_PARTITIONS=y
484# CONFIG_MTD_REDBOOT_PARTS is not set
485# CONFIG_MTD_CMDLINE_PARTS is not set
486# CONFIG_MTD_AR7_PARTS is not set
487
488#
489# User Modules And Translation Layers
490#
491CONFIG_MTD_CHAR=y
492CONFIG_MTD_BLKDEVS=y
493CONFIG_MTD_BLOCK=y
494# CONFIG_FTL is not set
495# CONFIG_NFTL is not set
496# CONFIG_INFTL is not set
497# CONFIG_RFD_FTL is not set
498# CONFIG_SSFDC is not set
499# CONFIG_MTD_OOPS is not set
500
501#
502# RAM/ROM/Flash chip drivers
503#
504# CONFIG_MTD_CFI is not set
505CONFIG_MTD_JEDECPROBE=m
506CONFIG_MTD_GEN_PROBE=m
507# CONFIG_MTD_CFI_ADV_OPTIONS is not set
508CONFIG_MTD_MAP_BANK_WIDTH_1=y
509CONFIG_MTD_MAP_BANK_WIDTH_2=y
510CONFIG_MTD_MAP_BANK_WIDTH_4=y
511# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
512# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
513# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
514CONFIG_MTD_CFI_I1=y
515CONFIG_MTD_CFI_I2=y
516# CONFIG_MTD_CFI_I4 is not set
517# CONFIG_MTD_CFI_I8 is not set
518# CONFIG_MTD_CFI_INTELEXT is not set
519# CONFIG_MTD_CFI_AMDSTD is not set
520# CONFIG_MTD_CFI_STAA is not set
521CONFIG_MTD_RAM=y
522CONFIG_MTD_ROM=m
523# CONFIG_MTD_ABSENT is not set
524
525#
526# Mapping drivers for chip access
527#
528CONFIG_MTD_COMPLEX_MAPPINGS=y
529# CONFIG_MTD_PHYSMAP is not set
530# CONFIG_MTD_GPIO_ADDR is not set
531# CONFIG_MTD_UCLINUX is not set
532# CONFIG_MTD_PLATRAM is not set
533
534#
535# Self-contained MTD device drivers
536#
537# CONFIG_MTD_SLRAM is not set
538# CONFIG_MTD_PHRAM is not set
539# CONFIG_MTD_MTDRAM is not set
540# CONFIG_MTD_BLOCK2MTD is not set
541
542#
543# Disk-On-Chip Device Drivers
544#
545# CONFIG_MTD_DOC2000 is not set
546# CONFIG_MTD_DOC2001 is not set
547# CONFIG_MTD_DOC2001PLUS is not set
548# CONFIG_MTD_NAND is not set
549# CONFIG_MTD_ONENAND is not set
550
551#
552# UBI - Unsorted block images
553#
554# CONFIG_MTD_UBI is not set
555# CONFIG_PARPORT is not set
556CONFIG_BLK_DEV=y
557# CONFIG_BLK_DEV_COW_COMMON is not set
558# CONFIG_BLK_DEV_LOOP is not set
559# CONFIG_BLK_DEV_NBD is not set
560CONFIG_BLK_DEV_RAM=y
561CONFIG_BLK_DEV_RAM_COUNT=16
562CONFIG_BLK_DEV_RAM_SIZE=4096
563# CONFIG_BLK_DEV_XIP is not set
564# CONFIG_CDROM_PKTCDVD is not set
565# CONFIG_ATA_OVER_ETH is not set
566CONFIG_MISC_DEVICES=y
567# CONFIG_EEPROM_93CX6 is not set
568# CONFIG_ENCLOSURE_SERVICES is not set
569CONFIG_HAVE_IDE=y
570# CONFIG_IDE is not set
571
572#
573# SCSI device support
574#
575# CONFIG_RAID_ATTRS is not set
576# CONFIG_SCSI is not set
577# CONFIG_SCSI_DMA is not set
578# CONFIG_SCSI_NETLINK is not set
579# CONFIG_ATA is not set
580# CONFIG_MD is not set
581CONFIG_NETDEVICES=y
582# CONFIG_NETDEVICES_MULTIQUEUE is not set
583# CONFIG_DUMMY is not set
584# CONFIG_BONDING is not set
585# CONFIG_MACVLAN is not set
586# CONFIG_EQUALIZER is not set
587# CONFIG_TUN is not set
588# CONFIG_VETH is not set
589CONFIG_PHYLIB=y
590
591#
592# MII PHY device drivers
593#
594# CONFIG_MARVELL_PHY is not set
595# CONFIG_DAVICOM_PHY is not set
596# CONFIG_QSEMI_PHY is not set
597# CONFIG_LXT_PHY is not set
598# CONFIG_CICADA_PHY is not set
599# CONFIG_VITESSE_PHY is not set
600# CONFIG_SMSC_PHY is not set
601# CONFIG_BROADCOM_PHY is not set
602# CONFIG_ICPLUS_PHY is not set
603# CONFIG_REALTEK_PHY is not set
604# CONFIG_FIXED_PHY is not set
605# CONFIG_MDIO_BITBANG is not set
606CONFIG_NET_ETHERNET=y
607CONFIG_MII=y
608# CONFIG_SMC91X is not set
609# CONFIG_SMSC911X is not set
610# CONFIG_DM9000 is not set
611# CONFIG_IBM_NEW_EMAC_ZMII is not set
612# CONFIG_IBM_NEW_EMAC_RGMII is not set
613# CONFIG_IBM_NEW_EMAC_TAH is not set
614# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
615# CONFIG_B44 is not set
616# CONFIG_NETDEV_1000 is not set
617# CONFIG_NETDEV_10000 is not set
618
619#
620# Wireless LAN
621#
622# CONFIG_WLAN_PRE80211 is not set
623# CONFIG_WLAN_80211 is not set
624# CONFIG_IWLWIFI_LEDS is not set
625# CONFIG_WAN is not set
626# CONFIG_PPP is not set
627# CONFIG_SLIP is not set
628# CONFIG_NETCONSOLE is not set
629# CONFIG_NETPOLL is not set
630# CONFIG_NET_POLL_CONTROLLER is not set
631# CONFIG_ISDN is not set
632# CONFIG_PHONE is not set
633
634#
635# Input device support
636#
637CONFIG_INPUT=y
638# CONFIG_INPUT_FF_MEMLESS is not set
639# CONFIG_INPUT_POLLDEV is not set
640
641#
642# Userland interfaces
643#
644# CONFIG_INPUT_MOUSEDEV is not set
645# CONFIG_INPUT_JOYDEV is not set
646# CONFIG_INPUT_EVDEV is not set
647# CONFIG_INPUT_EVBUG is not set
648
649#
650# Input Device Drivers
651#
652# CONFIG_INPUT_KEYBOARD is not set
653# CONFIG_INPUT_MOUSE is not set
654# CONFIG_INPUT_JOYSTICK is not set
655# CONFIG_INPUT_TABLET is not set
656# CONFIG_INPUT_TOUCHSCREEN is not set
657CONFIG_INPUT_MISC=y
658# CONFIG_INPUT_UINPUT is not set
659# CONFIG_TWI_KEYPAD is not set
660
661#
662# Hardware I/O ports
663#
664# CONFIG_SERIO is not set
665# CONFIG_GAMEPORT is not set
666
667#
668# Character devices
669#
670# CONFIG_AD9960 is not set
671# CONFIG_SPI_ADC_BF533 is not set
672# CONFIG_BF5xx_PPIFCD is not set
673# CONFIG_BFIN_SIMPLE_TIMER is not set
674# CONFIG_BF5xx_PPI is not set
675# CONFIG_BFIN_SPORT is not set
676# CONFIG_BFIN_TIMER_LATENCY is not set
677# CONFIG_TWI_LCD is not set
678CONFIG_SIMPLE_GPIO=m
679CONFIG_VT=y
680CONFIG_VT_CONSOLE=y
681CONFIG_HW_CONSOLE=y
682# CONFIG_VT_HW_CONSOLE_BINDING is not set
683# CONFIG_DEVKMEM is not set
684# CONFIG_BFIN_JTAG_COMM is not set
685# CONFIG_SERIAL_NONSTANDARD is not set
686
687#
688# Serial drivers
689#
690# CONFIG_SERIAL_8250 is not set
691
692#
693# Non-8250 serial port support
694#
695CONFIG_SERIAL_BFIN=y
696CONFIG_SERIAL_BFIN_CONSOLE=y
697CONFIG_SERIAL_BFIN_DMA=y
698# CONFIG_SERIAL_BFIN_PIO is not set
699CONFIG_SERIAL_BFIN_UART0=y
700# CONFIG_BFIN_UART0_CTSRTS is not set
701# CONFIG_SERIAL_BFIN_UART1 is not set
702CONFIG_SERIAL_CORE=y
703CONFIG_SERIAL_CORE_CONSOLE=y
704# CONFIG_SERIAL_BFIN_SPORT is not set
705CONFIG_UNIX98_PTYS=y
706# CONFIG_LEGACY_PTYS is not set
707
708#
709# CAN, the car bus and industrial fieldbus
710#
711# CONFIG_CAN4LINUX is not set
712# CONFIG_IPMI_HANDLER is not set
713# CONFIG_HW_RANDOM is not set
714# CONFIG_R3964 is not set
715# CONFIG_RAW_DRIVER is not set
716# CONFIG_TCG_TPM is not set
717CONFIG_I2C=y
718CONFIG_I2C_BOARDINFO=y
719CONFIG_I2C_CHARDEV=y
720CONFIG_I2C_HELPER_AUTO=y
721
722#
723# I2C Hardware Bus support
724#
725CONFIG_I2C_BLACKFIN_TWI=y
726CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=50
727# CONFIG_I2C_GPIO is not set
728# CONFIG_I2C_OCORES is not set
729# CONFIG_I2C_PARPORT_LIGHT is not set
730# CONFIG_I2C_SIMTEC is not set
731# CONFIG_I2C_TAOS_EVM is not set
732# CONFIG_I2C_STUB is not set
733# CONFIG_I2C_PCA_PLATFORM is not set
734
735#
736# Miscellaneous I2C Chip support
737#
738# CONFIG_DS1682 is not set
739# CONFIG_SENSORS_AD5252 is not set
740# CONFIG_SENSORS_EEPROM is not set
741# CONFIG_SENSORS_PCF8574 is not set
742# CONFIG_PCF8575 is not set
743# CONFIG_SENSORS_PCF8591 is not set
744# CONFIG_SENSORS_MAX6875 is not set
745# CONFIG_SENSORS_TSL2550 is not set
746# CONFIG_I2C_DEBUG_CORE is not set
747# CONFIG_I2C_DEBUG_ALGO is not set
748# CONFIG_I2C_DEBUG_BUS is not set
749# CONFIG_I2C_DEBUG_CHIP is not set
750# CONFIG_SPI is not set
751# CONFIG_W1 is not set
752# CONFIG_POWER_SUPPLY is not set
753# CONFIG_HWMON is not set
754# CONFIG_THERMAL is not set
755# CONFIG_THERMAL_HWMON is not set
756CONFIG_WATCHDOG=y
757# CONFIG_WATCHDOG_NOWAYOUT is not set
758
759#
760# Watchdog Device Drivers
761#
762# CONFIG_SOFT_WATCHDOG is not set
763CONFIG_BFIN_WDT=y
764
765#
766# Sonics Silicon Backplane
767#
768CONFIG_SSB_POSSIBLE=y
769# CONFIG_SSB is not set
770
771#
772# Multifunction device drivers
773#
774# CONFIG_MFD_SM501 is not set
775# CONFIG_HTC_PASIC3 is not set
776
777#
778# Multimedia devices
779#
780
781#
782# Multimedia core support
783#
784# CONFIG_VIDEO_DEV is not set
785# CONFIG_DVB_CORE is not set
786# CONFIG_VIDEO_MEDIA is not set
787
788#
789# Multimedia drivers
790#
791# CONFIG_DAB is not set
792
793#
794# Graphics support
795#
796# CONFIG_VGASTATE is not set
797# CONFIG_VIDEO_OUTPUT_CONTROL is not set
798# CONFIG_FB is not set
799# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
800
801#
802# Display device support
803#
804# CONFIG_DISPLAY_SUPPORT is not set
805
806#
807# Console display driver support
808#
809CONFIG_DUMMY_CONSOLE=y
810
811#
812# Sound
813#
814# CONFIG_SOUND is not set
815# CONFIG_HID_SUPPORT is not set
816# CONFIG_USB_SUPPORT is not set
817# CONFIG_MMC is not set
818# CONFIG_MEMSTICK is not set
819# CONFIG_NEW_LEDS is not set
820# CONFIG_ACCESSIBILITY is not set
821CONFIG_RTC_LIB=y
822CONFIG_RTC_CLASS=y
823CONFIG_RTC_HCTOSYS=y
824CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
825# CONFIG_RTC_DEBUG is not set
826
827#
828# RTC interfaces
829#
830CONFIG_RTC_INTF_SYSFS=y
831CONFIG_RTC_INTF_PROC=y
832CONFIG_RTC_INTF_DEV=y
833# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
834# CONFIG_RTC_DRV_TEST is not set
835
836#
837# I2C RTC drivers
838#
839# CONFIG_RTC_DRV_DS1307 is not set
840# CONFIG_RTC_DRV_DS1374 is not set
841# CONFIG_RTC_DRV_DS1672 is not set
842# CONFIG_RTC_DRV_MAX6900 is not set
843# CONFIG_RTC_DRV_RS5C372 is not set
844# CONFIG_RTC_DRV_ISL1208 is not set
845# CONFIG_RTC_DRV_X1205 is not set
846# CONFIG_RTC_DRV_PCF8563 is not set
847# CONFIG_RTC_DRV_PCF8583 is not set
848# CONFIG_RTC_DRV_M41T80 is not set
849# CONFIG_RTC_DRV_S35390A is not set
850# CONFIG_RTC_DRV_FM3130 is not set
851
852#
853# SPI RTC drivers
854#
855
856#
857# Platform RTC drivers
858#
859# CONFIG_RTC_DRV_DS1511 is not set
860# CONFIG_RTC_DRV_DS1553 is not set
861# CONFIG_RTC_DRV_DS1742 is not set
862# CONFIG_RTC_DRV_STK17TA8 is not set
863# CONFIG_RTC_DRV_M48T86 is not set
864# CONFIG_RTC_DRV_M48T59 is not set
865# CONFIG_RTC_DRV_V3020 is not set
866
867#
868# on-CPU RTC drivers
869#
870CONFIG_RTC_DRV_BFIN=y
871# CONFIG_UIO is not set
872
873#
874# File systems
875#
876# CONFIG_EXT2_FS is not set
877# CONFIG_EXT3_FS is not set
878# CONFIG_EXT4DEV_FS is not set
879# CONFIG_REISERFS_FS is not set
880# CONFIG_JFS_FS is not set
881# CONFIG_FS_POSIX_ACL is not set
882# CONFIG_XFS_FS is not set
883# CONFIG_OCFS2_FS is not set
884# CONFIG_DNOTIFY is not set
885CONFIG_INOTIFY=y
886CONFIG_INOTIFY_USER=y
887# CONFIG_QUOTA is not set
888# CONFIG_AUTOFS_FS is not set
889# CONFIG_AUTOFS4_FS is not set
890# CONFIG_FUSE_FS is not set
891
892#
893# CD-ROM/DVD Filesystems
894#
895# CONFIG_ISO9660_FS is not set
896# CONFIG_UDF_FS is not set
897
898#
899# DOS/FAT/NT Filesystems
900#
901# CONFIG_MSDOS_FS is not set
902# CONFIG_VFAT_FS is not set
903# CONFIG_NTFS_FS is not set
904
905#
906# Pseudo filesystems
907#
908CONFIG_PROC_FS=y
909CONFIG_PROC_SYSCTL=y
910CONFIG_SYSFS=y
911# CONFIG_TMPFS is not set
912# CONFIG_HUGETLB_PAGE is not set
913# CONFIG_CONFIGFS_FS is not set
914
915#
916# Miscellaneous filesystems
917#
918# CONFIG_ADFS_FS is not set
919# CONFIG_AFFS_FS is not set
920# CONFIG_HFS_FS is not set
921# CONFIG_HFSPLUS_FS is not set
922# CONFIG_BEFS_FS is not set
923# CONFIG_BFS_FS is not set
924# CONFIG_EFS_FS is not set
925# CONFIG_YAFFS_FS is not set
926# CONFIG_JFFS2_FS is not set
927# CONFIG_CRAMFS is not set
928# CONFIG_VXFS_FS is not set
929# CONFIG_MINIX_FS is not set
930# CONFIG_HPFS_FS is not set
931# CONFIG_QNX4FS_FS is not set
932# CONFIG_ROMFS_FS is not set
933# CONFIG_SYSV_FS is not set
934# CONFIG_UFS_FS is not set
935CONFIG_NETWORK_FILESYSTEMS=y
936CONFIG_NFS_FS=m
937CONFIG_NFS_V3=y
938# CONFIG_NFS_V3_ACL is not set
939# CONFIG_NFS_V4 is not set
940# CONFIG_NFSD is not set
941CONFIG_LOCKD=m
942CONFIG_LOCKD_V4=y
943CONFIG_NFS_COMMON=y
944CONFIG_SUNRPC=m
945# CONFIG_SUNRPC_BIND34 is not set
946# CONFIG_RPCSEC_GSS_KRB5 is not set
947# CONFIG_RPCSEC_GSS_SPKM3 is not set
948CONFIG_SMB_FS=m
949# CONFIG_SMB_NLS_DEFAULT is not set
950# CONFIG_CIFS is not set
951# CONFIG_NCP_FS is not set
952# CONFIG_CODA_FS is not set
953# CONFIG_AFS_FS is not set
954
955#
956# Partition Types
957#
958# CONFIG_PARTITION_ADVANCED is not set
959CONFIG_MSDOS_PARTITION=y
960CONFIG_NLS=y
961CONFIG_NLS_DEFAULT="iso8859-1"
962CONFIG_NLS_CODEPAGE_437=y
963# CONFIG_NLS_CODEPAGE_737 is not set
964# CONFIG_NLS_CODEPAGE_775 is not set
965# CONFIG_NLS_CODEPAGE_850 is not set
966# CONFIG_NLS_CODEPAGE_852 is not set
967# CONFIG_NLS_CODEPAGE_855 is not set
968# CONFIG_NLS_CODEPAGE_857 is not set
969# CONFIG_NLS_CODEPAGE_860 is not set
970# CONFIG_NLS_CODEPAGE_861 is not set
971# CONFIG_NLS_CODEPAGE_862 is not set
972# CONFIG_NLS_CODEPAGE_863 is not set
973# CONFIG_NLS_CODEPAGE_864 is not set
974# CONFIG_NLS_CODEPAGE_865 is not set
975# CONFIG_NLS_CODEPAGE_866 is not set
976# CONFIG_NLS_CODEPAGE_869 is not set
977# CONFIG_NLS_CODEPAGE_936 is not set
978# CONFIG_NLS_CODEPAGE_950 is not set
979# CONFIG_NLS_CODEPAGE_932 is not set
980# CONFIG_NLS_CODEPAGE_949 is not set
981# CONFIG_NLS_CODEPAGE_874 is not set
982# CONFIG_NLS_ISO8859_8 is not set
983# CONFIG_NLS_CODEPAGE_1250 is not set
984# CONFIG_NLS_CODEPAGE_1251 is not set
985# CONFIG_NLS_ASCII is not set
986CONFIG_NLS_ISO8859_1=y
987# CONFIG_NLS_ISO8859_2 is not set
988# CONFIG_NLS_ISO8859_3 is not set
989# CONFIG_NLS_ISO8859_4 is not set
990# CONFIG_NLS_ISO8859_5 is not set
991# CONFIG_NLS_ISO8859_6 is not set
992# CONFIG_NLS_ISO8859_7 is not set
993# CONFIG_NLS_ISO8859_9 is not set
994# CONFIG_NLS_ISO8859_13 is not set
995# CONFIG_NLS_ISO8859_14 is not set
996# CONFIG_NLS_ISO8859_15 is not set
997# CONFIG_NLS_KOI8_R is not set
998# CONFIG_NLS_KOI8_U is not set
999# CONFIG_NLS_UTF8 is not set
1000# CONFIG_DLM is not set
1001
1002#
1003# Kernel hacking
1004#
1005# CONFIG_PRINTK_TIME is not set
1006CONFIG_ENABLE_WARN_DEPRECATED=y
1007CONFIG_ENABLE_MUST_CHECK=y
1008CONFIG_FRAME_WARN=1024
1009# CONFIG_MAGIC_SYSRQ is not set
1010# CONFIG_UNUSED_SYMBOLS is not set
1011CONFIG_DEBUG_FS=y
1012# CONFIG_HEADERS_CHECK is not set
1013# CONFIG_DEBUG_KERNEL is not set
1014# CONFIG_DEBUG_BUGVERBOSE is not set
1015# CONFIG_SAMPLES is not set
1016CONFIG_HAVE_ARCH_KGDB=y
1017CONFIG_DEBUG_VERBOSE=y
1018CONFIG_DEBUG_MMRS=y
1019# CONFIG_DEBUG_DOUBLEFAULT is not set
1020CONFIG_DEBUG_HUNT_FOR_ZERO=y
1021CONFIG_DEBUG_BFIN_HWTRACE_ON=y
1022CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
1023# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE is not set
1024# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set
1025CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0
1026# CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set
1027# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
1028CONFIG_EARLY_PRINTK=y
1029CONFIG_CPLB_INFO=y
1030CONFIG_ACCESS_CHECK=y
1031
1032#
1033# Security options
1034#
1035# CONFIG_KEYS is not set
1036CONFIG_SECURITY=y
1037# CONFIG_SECURITY_NETWORK is not set
1038# CONFIG_SECURITY_CAPABILITIES is not set
1039CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0
1040CONFIG_CRYPTO=y
1041
1042#
1043# Crypto core or helper
1044#
1045# CONFIG_CRYPTO_MANAGER is not set
1046# CONFIG_CRYPTO_GF128MUL is not set
1047# CONFIG_CRYPTO_NULL is not set
1048# CONFIG_CRYPTO_CRYPTD is not set
1049# CONFIG_CRYPTO_AUTHENC is not set
1050# CONFIG_CRYPTO_TEST is not set
1051
1052#
1053# Authenticated Encryption with Associated Data
1054#
1055# CONFIG_CRYPTO_CCM is not set
1056# CONFIG_CRYPTO_GCM is not set
1057# CONFIG_CRYPTO_SEQIV is not set
1058
1059#
1060# Block modes
1061#
1062# CONFIG_CRYPTO_CBC is not set
1063# CONFIG_CRYPTO_CTR is not set
1064# CONFIG_CRYPTO_CTS is not set
1065# CONFIG_CRYPTO_ECB is not set
1066# CONFIG_CRYPTO_LRW is not set
1067# CONFIG_CRYPTO_PCBC is not set
1068# CONFIG_CRYPTO_XTS is not set
1069
1070#
1071# Hash modes
1072#
1073# CONFIG_CRYPTO_HMAC is not set
1074# CONFIG_CRYPTO_XCBC is not set
1075
1076#
1077# Digest
1078#
1079# CONFIG_CRYPTO_CRC32C is not set
1080# CONFIG_CRYPTO_MD4 is not set
1081# CONFIG_CRYPTO_MD5 is not set
1082# CONFIG_CRYPTO_MICHAEL_MIC is not set
1083# CONFIG_CRYPTO_SHA1 is not set
1084# CONFIG_CRYPTO_SHA256 is not set
1085# CONFIG_CRYPTO_SHA512 is not set
1086# CONFIG_CRYPTO_TGR192 is not set
1087# CONFIG_CRYPTO_WP512 is not set
1088
1089#
1090# Ciphers
1091#
1092# CONFIG_CRYPTO_AES is not set
1093# CONFIG_CRYPTO_ANUBIS is not set
1094# CONFIG_CRYPTO_ARC4 is not set
1095# CONFIG_CRYPTO_BLOWFISH is not set
1096# CONFIG_CRYPTO_CAMELLIA is not set
1097# CONFIG_CRYPTO_CAST5 is not set
1098# CONFIG_CRYPTO_CAST6 is not set
1099# CONFIG_CRYPTO_DES is not set
1100# CONFIG_CRYPTO_FCRYPT is not set
1101# CONFIG_CRYPTO_KHAZAD is not set
1102# CONFIG_CRYPTO_SALSA20 is not set
1103# CONFIG_CRYPTO_SEED is not set
1104# CONFIG_CRYPTO_SERPENT is not set
1105# CONFIG_CRYPTO_TEA is not set
1106# CONFIG_CRYPTO_TWOFISH is not set
1107
1108#
1109# Compression
1110#
1111# CONFIG_CRYPTO_DEFLATE is not set
1112# CONFIG_CRYPTO_LZO is not set
1113CONFIG_CRYPTO_HW=y
1114
1115#
1116# Library routines
1117#
1118CONFIG_BITREVERSE=y
1119# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1120CONFIG_CRC_CCITT=m
1121# CONFIG_CRC16 is not set
1122# CONFIG_CRC_ITU_T is not set
1123CONFIG_CRC32=y
1124# CONFIG_CRC7 is not set
1125# CONFIG_LIBCRC32C is not set
1126CONFIG_ZLIB_INFLATE=y
1127CONFIG_PLIST=y
1128CONFIG_HAS_IOMEM=y
1129CONFIG_HAS_IOPORT=y
1130CONFIG_HAS_DMA=y
diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h
index c7d287ca5d0a..d8485624006a 100644
--- a/arch/blackfin/include/asm/gpio.h
+++ b/arch/blackfin/include/asm/gpio.h
@@ -143,6 +143,57 @@
143#define PERIPHERAL_USAGE 1 143#define PERIPHERAL_USAGE 1
144#define GPIO_USAGE 0 144#define GPIO_USAGE 0
145 145
146#if defined(BF518_FAMILY)
147#define MAX_BLACKFIN_GPIOS 40
148
149#define GPIO_PF0 0
150#define GPIO_PF1 1
151#define GPIO_PF2 2
152#define GPIO_PF3 3
153#define GPIO_PF4 4
154#define GPIO_PF5 5
155#define GPIO_PF6 6
156#define GPIO_PF7 7
157#define GPIO_PF8 8
158#define GPIO_PF9 9
159#define GPIO_PF10 10
160#define GPIO_PF11 11
161#define GPIO_PF12 12
162#define GPIO_PF13 13
163#define GPIO_PF14 14
164#define GPIO_PF15 15
165#define GPIO_PG0 16
166#define GPIO_PG1 17
167#define GPIO_PG2 18
168#define GPIO_PG3 19
169#define GPIO_PG4 20
170#define GPIO_PG5 21
171#define GPIO_PG6 22
172#define GPIO_PG7 23
173#define GPIO_PG8 24
174#define GPIO_PG9 25
175#define GPIO_PG10 26
176#define GPIO_PG11 27
177#define GPIO_PG12 28
178#define GPIO_PG13 29
179#define GPIO_PG14 30
180#define GPIO_PG15 31
181#define GPIO_PH0 32
182#define GPIO_PH1 33
183#define GPIO_PH2 34
184#define GPIO_PH3 35
185#define GPIO_PH4 36
186#define GPIO_PH5 37
187#define GPIO_PH6 38
188#define GPIO_PH7 39
189
190#define PORT_F GPIO_PF0
191#define PORT_G GPIO_PG0
192#define PORT_H GPIO_PH0
193
194#endif
195
196
146#ifdef BF533_FAMILY 197#ifdef BF533_FAMILY
147#define MAX_BLACKFIN_GPIOS 16 198#define MAX_BLACKFIN_GPIOS 16
148 199
diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c
index e129102ad09b..5556e13993bf 100644
--- a/arch/blackfin/kernel/bfin_gpio.c
+++ b/arch/blackfin/kernel/bfin_gpio.c
@@ -125,7 +125,7 @@ static struct gpio_port_t *gpio_bankb[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
125}; 125};
126#endif 126#endif
127 127
128#if defined(BF527_FAMILY) || defined(BF537_FAMILY) 128#if defined(BF527_FAMILY) || defined(BF537_FAMILY) || defined(BF518_FAMILY)
129static struct gpio_port_t *gpio_bankb[gpio_bank(MAX_BLACKFIN_GPIOS)] = { 129static struct gpio_port_t *gpio_bankb[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
130 (struct gpio_port_t *) PORTFIO, 130 (struct gpio_port_t *) PORTFIO,
131 (struct gpio_port_t *) PORTGIO, 131 (struct gpio_port_t *) PORTGIO,
@@ -139,7 +139,7 @@ static unsigned short *port_fer[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
139}; 139};
140#endif 140#endif
141 141
142#ifdef BF527_FAMILY 142#if defined(BF527_FAMILY) || defined(BF518_FAMILY)
143static unsigned short *port_mux[gpio_bank(MAX_BLACKFIN_GPIOS)] = { 143static unsigned short *port_mux[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
144 (unsigned short *) PORTF_MUX, 144 (unsigned short *) PORTF_MUX,
145 (unsigned short *) PORTG_MUX, 145 (unsigned short *) PORTG_MUX,
@@ -206,7 +206,7 @@ static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PROG_INTB
206static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PORTF_INTB}; 206static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PORTF_INTB};
207#endif 207#endif
208 208
209#ifdef BF527_FAMILY 209#if defined(BF527_FAMILY) || defined(BF518_FAMILY)
210static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PORTF_INTB, IRQ_PORTG_INTB, IRQ_PORTH_INTB}; 210static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PORTF_INTB, IRQ_PORTG_INTB, IRQ_PORTH_INTB};
211#endif 211#endif
212 212
@@ -268,7 +268,7 @@ static int cmp_label(unsigned short ident, const char *label)
268 return -EINVAL; 268 return -EINVAL;
269} 269}
270 270
271#if defined(BF527_FAMILY) || defined(BF537_FAMILY) 271#if defined(BF527_FAMILY) || defined(BF537_FAMILY) || defined(BF518_FAMILY)
272static void port_setup(unsigned gpio, unsigned short usage) 272static void port_setup(unsigned gpio, unsigned short usage)
273{ 273{
274 if (!check_gpio(gpio)) { 274 if (!check_gpio(gpio)) {
@@ -383,7 +383,7 @@ inline u16 get_portmux(unsigned short portno)
383 383
384 return (pmux >> (2 * gpio_sub_n(portno)) & 0x3); 384 return (pmux >> (2 * gpio_sub_n(portno)) & 0x3);
385} 385}
386#elif defined(BF527_FAMILY) 386#elif defined(BF527_FAMILY) || defined(BF518_FAMILY)
387inline void portmux_setup(unsigned short portno, unsigned short function) 387inline void portmux_setup(unsigned short portno, unsigned short function)
388{ 388{
389 u16 pmux, ident = P_IDENT(portno); 389 u16 pmux, ident = P_IDENT(portno);
@@ -683,7 +683,7 @@ u32 bfin_pm_standby_setup(void)
683 gpio_bankb[bank]->maskb = 0; 683 gpio_bankb[bank]->maskb = 0;
684 684
685 if (mask) { 685 if (mask) {
686#if defined(BF527_FAMILY) || defined(BF537_FAMILY) 686#if defined(BF527_FAMILY) || defined(BF537_FAMILY) || defined(BF518_FAMILY)
687 gpio_bank_saved[bank].fer = *port_fer[bank]; 687 gpio_bank_saved[bank].fer = *port_fer[bank];
688#endif 688#endif
689 gpio_bank_saved[bank].inen = gpio_bankb[bank]->inen; 689 gpio_bank_saved[bank].inen = gpio_bankb[bank]->inen;
@@ -728,7 +728,7 @@ void bfin_pm_standby_restore(void)
728 bank = gpio_bank(i); 728 bank = gpio_bank(i);
729 729
730 if (mask) { 730 if (mask) {
731#if defined(BF527_FAMILY) || defined(BF537_FAMILY) 731#if defined(BF527_FAMILY) || defined(BF537_FAMILY) || defined(BF518_FAMILY)
732 *port_fer[bank] = gpio_bank_saved[bank].fer; 732 *port_fer[bank] = gpio_bank_saved[bank].fer;
733#endif 733#endif
734 gpio_bankb[bank]->inen = gpio_bank_saved[bank].inen; 734 gpio_bankb[bank]->inen = gpio_bank_saved[bank].inen;
@@ -754,9 +754,9 @@ void bfin_gpio_pm_hibernate_suspend(void)
754 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) { 754 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
755 bank = gpio_bank(i); 755 bank = gpio_bank(i);
756 756
757#if defined(BF527_FAMILY) || defined(BF537_FAMILY) 757#if defined(BF527_FAMILY) || defined(BF537_FAMILY) || defined(BF518_FAMILY)
758 gpio_bank_saved[bank].fer = *port_fer[bank]; 758 gpio_bank_saved[bank].fer = *port_fer[bank];
759#ifdef BF527_FAMILY 759#if defined(BF527_FAMILY) || defined(BF518_FAMILY)
760 gpio_bank_saved[bank].mux = *port_mux[bank]; 760 gpio_bank_saved[bank].mux = *port_mux[bank];
761#else 761#else
762 if (bank == 0) 762 if (bank == 0)
@@ -782,8 +782,8 @@ void bfin_gpio_pm_hibernate_restore(void)
782 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) { 782 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
783 bank = gpio_bank(i); 783 bank = gpio_bank(i);
784 784
785#if defined(BF527_FAMILY) || defined(BF537_FAMILY) 785#if defined(BF527_FAMILY) || defined(BF537_FAMILY) || defined(BF518_FAMILY)
786#ifdef BF527_FAMILY 786#if defined(BF527_FAMILY) || defined(BF518_FAMILY)
787 *port_mux[bank] = gpio_bank_saved[bank].mux; 787 *port_mux[bank] = gpio_bank_saved[bank].mux;
788#else 788#else
789 if (bank == 0) 789 if (bank == 0)
diff --git a/arch/blackfin/mach-bf518/Kconfig b/arch/blackfin/mach-bf518/Kconfig
new file mode 100644
index 000000000000..00f2d3700637
--- /dev/null
+++ b/arch/blackfin/mach-bf518/Kconfig
@@ -0,0 +1,233 @@
1if (BF51x)
2
3source "arch/blackfin/mach-bf518/boards/Kconfig"
4
5menu "BF518 Specific Configuration"
6
7comment "Alternative Multiplexing Scheme"
8
9choice
10 prompt "SPORT0"
11 default BF518_SPORT0_PORTG
12 help
13 Select PORT used for SPORT0. See Hardware Reference Manual
14
15config BF518_SPORT0_PORTF
16 bool "PORT F"
17 help
18 PORT F
19
20config BF518_SPORT0_PORTG
21 bool "PORT G"
22 help
23 PORT G
24endchoice
25
26choice
27 prompt "SPORT0 TSCLK Location"
28 depends on BF518_SPORT0_PORTG
29 default BF518_SPORT0_TSCLK_PG10
30 help
31 Select PIN used for SPORT0_TSCLK. See Hardware Reference Manual
32
33config BF518_SPORT0_TSCLK_PG10
34 bool "PORT PG10"
35 help
36 PORT PG10
37
38config BF518_SPORT0_TSCLK_PG14
39 bool "PORT PG14"
40 help
41 PORT PG14
42endchoice
43
44choice
45 prompt "UART1"
46 default BF518_UART1_PORTF
47 help
48 Select PORT used for UART1. See Hardware Reference Manual
49
50config BF518_UART1_PORTF
51 bool "PORT F"
52 help
53 PORT F
54
55config BF518_UART1_PORTG
56 bool "PORT G"
57 help
58 PORT G
59endchoice
60
61comment "Interrupt Priority Assignment"
62menu "Priority"
63
64config IRQ_PLL_WAKEUP
65 int "IRQ_PLL_WAKEUP"
66 default 7
67config IRQ_DMA0_ERROR
68 int "IRQ_DMA0_ERROR"
69 default 7
70config IRQ_DMAR0_BLK
71 int "IRQ_DMAR0_BLK"
72 default 7
73config IRQ_DMAR1_BLK
74 int "IRQ_DMAR1_BLK"
75 default 7
76config IRQ_DMAR0_OVR
77 int "IRQ_DMAR0_OVR"
78 default 7
79config IRQ_DMAR1_OVR
80 int "IRQ_DMAR1_OVR"
81 default 7
82config IRQ_PPI_ERROR
83 int "IRQ_PPI_ERROR"
84 default 7
85config IRQ_MAC_ERROR
86 int "IRQ_MAC_ERROR"
87 default 7
88config IRQ_SPORT0_ERROR
89 int "IRQ_SPORT0_ERROR"
90 default 7
91config IRQ_SPORT1_ERROR
92 int "IRQ_SPORT1_ERROR"
93 default 7
94config IRQ_PTP_ERROR
95 int "IRQ_PTP_ERROR"
96 default 7
97config IRQ_UART0_ERROR
98 int "IRQ_UART0_ERROR"
99 default 7
100config IRQ_UART1_ERROR
101 int "IRQ_UART1_ERROR"
102 default 7
103config IRQ_RTC
104 int "IRQ_RTC"
105 default 8
106config IRQ_PPI
107 int "IRQ_PPI"
108 default 8
109config IRQ_SPORT0_RX
110 int "IRQ_SPORT0_RX"
111 default 9
112config IRQ_SPORT0_TX
113 int "IRQ_SPORT0_TX"
114 default 9
115config IRQ_SPORT1_RX
116 int "IRQ_SPORT1_RX"
117 default 9
118config IRQ_SPORT1_TX
119 int "IRQ_SPORT1_TX"
120 default 9
121config IRQ_TWI
122 int "IRQ_TWI"
123 default 10
124config IRQ_SPI0
125 int "IRQ_SPI"
126 default 10
127config IRQ_UART0_RX
128 int "IRQ_UART0_RX"
129 default 10
130config IRQ_UART0_TX
131 int "IRQ_UART0_TX"
132 default 10
133config IRQ_UART1_RX
134 int "IRQ_UART1_RX"
135 default 10
136config IRQ_UART1_TX
137 int "IRQ_UART1_TX"
138 default 10
139config IRQ_OPTSEC
140 int "IRQ_OPTSEC"
141 default 11
142config IRQ_CNT
143 int "IRQ_CNT"
144 default 11
145config IRQ_MAC_RX
146 int "IRQ_MAC_RX"
147 default 11
148config IRQ_PORTH_INTA
149 int "IRQ_PORTH_INTA"
150 default 11
151config IRQ_MAC_TX
152 int "IRQ_MAC_TX/NFC"
153 default 11
154config IRQ_PORTH_INTB
155 int "IRQ_PORTH_INTB"
156 default 11
157config IRQ_TMR0
158 int "IRQ_TMR0"
159 default 12
160config IRQ_TMR1
161 int "IRQ_TMR1"
162 default 12
163config IRQ_TMR2
164 int "IRQ_TMR2"
165 default 12
166config IRQ_TMR3
167 int "IRQ_TMR3"
168 default 12
169config IRQ_TMR4
170 int "IRQ_TMR4"
171 default 12
172config IRQ_TMR5
173 int "IRQ_TMR5"
174 default 12
175config IRQ_TMR6
176 int "IRQ_TMR6"
177 default 12
178config IRQ_TMR7
179 int "IRQ_TMR7"
180 default 12
181config IRQ_PORTG_INTA
182 int "IRQ_PORTG_INTA"
183 default 12
184config IRQ_PORTG_INTB
185 int "IRQ_PORTG_INTB"
186 default 12
187config IRQ_MEM_DMA0
188 int "IRQ_MEM_DMA0"
189 default 13
190config IRQ_MEM_DMA1
191 int "IRQ_MEM_DMA1"
192 default 13
193config IRQ_WATCH
194 int "IRQ_WATCH"
195 default 13
196config IRQ_PORTF_INTA
197 int "IRQ_PORTF_INTA"
198 default 13
199config IRQ_PORTF_INTB
200 int "IRQ_PORTF_INTB"
201 default 13
202config IRQ_SPI0_ERROR
203 int "IRQ_SPI0_ERROR"
204 default 7
205config IRQ_SPI1_ERROR
206 int "IRQ_SPI1_ERROR"
207 default 7
208config IRQ_RSI_INT0
209 int "IRQ_RSI_INT0"
210 default 7
211config IRQ_RSI_INT1
212 int "IRQ_RSI_INT1"
213 default 7
214config IRQ_PWM_TRIP
215 int "IRQ_PWM_TRIP"
216 default 10
217config IRQ_PWM_SYNC
218 int "IRQ_PWM_SYNC"
219 default 10
220config IRQ_PTP_STAT
221 int "IRQ_PTP_STAT"
222 default 10
223
224 help
225 Enter the priority numbers between 7-13 ONLY. Others are Reserved.
226 This applies to all the above. It is not recommended to assign the
227 highest priority number 7 to UART or any other device.
228
229endmenu
230
231endmenu
232
233endif
diff --git a/arch/blackfin/mach-bf518/Makefile b/arch/blackfin/mach-bf518/Makefile
new file mode 100644
index 000000000000..9d5e16d07b5e
--- /dev/null
+++ b/arch/blackfin/mach-bf518/Makefile
@@ -0,0 +1,7 @@
1#
2# arch/blackfin/mach-bf518/Makefile
3#
4
5extra-y := head.o
6
7obj-y := ints-priority.o dma.o
diff --git a/arch/blackfin/mach-bf518/boards/Kconfig b/arch/blackfin/mach-bf518/boards/Kconfig
new file mode 100644
index 000000000000..96163514ed22
--- /dev/null
+++ b/arch/blackfin/mach-bf518/boards/Kconfig
@@ -0,0 +1,12 @@
1choice
2 prompt "System type"
3 default BFIN518F_EZBRD
4 help
5 Select your board!
6
7config BFIN518F_EZBRD
8 bool "BF518F-EZBRD"
9 help
10 BF518-EZBRD board support.
11
12endchoice
diff --git a/arch/blackfin/mach-bf518/boards/Makefile b/arch/blackfin/mach-bf518/boards/Makefile
new file mode 100644
index 000000000000..172e859c3a7f
--- /dev/null
+++ b/arch/blackfin/mach-bf518/boards/Makefile
@@ -0,0 +1,5 @@
1#
2# arch/blackfin/mach-bf518/boards/Makefile
3#
4
5obj-$(CONFIG_BFIN518F_EZBRD) += ezbrd.o
diff --git a/arch/blackfin/mach-bf518/boards/ezbrd.c b/arch/blackfin/mach-bf518/boards/ezbrd.c
new file mode 100644
index 000000000000..65bc602b5c99
--- /dev/null
+++ b/arch/blackfin/mach-bf518/boards/ezbrd.c
@@ -0,0 +1,613 @@
1/*
2 * File: arch/blackfin/mach-bf518/boards/ezbrd.c
3 * Based on: arch/blackfin/mach-bf527/boards/ezbrd.c
4 * Author: Bryan Wu <cooloney@kernel.org>
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2005 National ICT Australia (NICTA)
11 * Copyright 2004-2008 Analog Devices Inc.
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see the file COPYING, or write
27 * to the Free Software Foundation, Inc.,
28 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 */
30
31#include <linux/device.h>
32#include <linux/platform_device.h>
33#include <linux/mtd/mtd.h>
34#include <linux/mtd/partitions.h>
35#include <linux/mtd/physmap.h>
36#include <linux/spi/spi.h>
37#include <linux/spi/flash.h>
38
39#include <linux/i2c.h>
40#include <linux/irq.h>
41#include <linux/interrupt.h>
42#include <asm/dma.h>
43#include <asm/bfin5xx_spi.h>
44#include <asm/reboot.h>
45#include <asm/portmux.h>
46#include <asm/dpmc.h>
47#include <linux/spi/ad7877.h>
48
49/*
50 * Name the Board for the /proc/cpuinfo
51 */
52const char bfin_board_name[] = "BF518F-EZBRD";
53
54/*
55 * Driver needs to know address, irq and flag pin.
56 */
57
58#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
59static struct mtd_partition ezbrd_partitions[] = {
60 {
61 .name = "bootloader(nor)",
62 .size = 0x40000,
63 .offset = 0,
64 }, {
65 .name = "linux kernel(nor)",
66 .size = 0x1C0000,
67 .offset = MTDPART_OFS_APPEND,
68 }, {
69 .name = "file system(nor)",
70 .size = MTDPART_SIZ_FULL,
71 .offset = MTDPART_OFS_APPEND,
72 }
73};
74
75static struct physmap_flash_data ezbrd_flash_data = {
76 .width = 2,
77 .parts = ezbrd_partitions,
78 .nr_parts = ARRAY_SIZE(ezbrd_partitions),
79};
80
81static struct resource ezbrd_flash_resource = {
82 .start = 0x20000000,
83 .end = 0x203fffff,
84 .flags = IORESOURCE_MEM,
85};
86
87static struct platform_device ezbrd_flash_device = {
88 .name = "physmap-flash",
89 .id = 0,
90 .dev = {
91 .platform_data = &ezbrd_flash_data,
92 },
93 .num_resources = 1,
94 .resource = &ezbrd_flash_resource,
95};
96#endif
97
98#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
99static struct platform_device rtc_device = {
100 .name = "rtc-bfin",
101 .id = -1,
102};
103#endif
104
105#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
106static struct platform_device bfin_mac_device = {
107 .name = "bfin_mac",
108};
109#endif
110
111#if defined(CONFIG_MTD_M25P80) \
112 || defined(CONFIG_MTD_M25P80_MODULE)
113static struct mtd_partition bfin_spi_flash_partitions[] = {
114 {
115 .name = "bootloader(spi)",
116 .size = 0x00040000,
117 .offset = 0,
118 .mask_flags = MTD_CAP_ROM
119 }, {
120 .name = "linux kernel(spi)",
121 .size = MTDPART_SIZ_FULL,
122 .offset = MTDPART_OFS_APPEND,
123 }
124};
125
126static struct flash_platform_data bfin_spi_flash_data = {
127 .name = "m25p80",
128 .parts = bfin_spi_flash_partitions,
129 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
130 .type = "m25p16",
131};
132
133/* SPI flash chip (m25p64) */
134static struct bfin5xx_spi_chip spi_flash_chip_info = {
135 .enable_dma = 0, /* use dma transfer with this chip*/
136 .bits_per_word = 8,
137};
138#endif
139
140#if defined(CONFIG_SPI_ADC_BF533) \
141 || defined(CONFIG_SPI_ADC_BF533_MODULE)
142/* SPI ADC chip */
143static struct bfin5xx_spi_chip spi_adc_chip_info = {
144 .enable_dma = 1, /* use dma transfer with this chip*/
145 .bits_per_word = 16,
146};
147#endif
148
149#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
150static struct bfin5xx_spi_chip spi_mmc_chip_info = {
151 .enable_dma = 1,
152 .bits_per_word = 8,
153};
154#endif
155
156#if defined(CONFIG_PBX)
157static struct bfin5xx_spi_chip spi_si3xxx_chip_info = {
158 .ctl_reg = 0x4, /* send zero */
159 .enable_dma = 0,
160 .bits_per_word = 8,
161 .cs_change_per_word = 1,
162};
163#endif
164
165#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
166static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
167 .enable_dma = 0,
168 .bits_per_word = 16,
169};
170
171static const struct ad7877_platform_data bfin_ad7877_ts_info = {
172 .model = 7877,
173 .vref_delay_usecs = 50, /* internal, no capacitor */
174 .x_plate_ohms = 419,
175 .y_plate_ohms = 486,
176 .pressure_max = 1000,
177 .pressure_min = 0,
178 .stopacq_polarity = 1,
179 .first_conversion_delay = 3,
180 .acquisition_time = 1,
181 .averaging = 1,
182 .pen_down_acc_interval = 1,
183};
184#endif
185
186#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
187 && defined(CONFIG_SND_SOC_WM8731_SPI)
188static struct bfin5xx_spi_chip spi_wm8731_chip_info = {
189 .enable_dma = 0,
190 .bits_per_word = 16,
191};
192#endif
193
194#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
195static struct bfin5xx_spi_chip spidev_chip_info = {
196 .enable_dma = 0,
197 .bits_per_word = 8,
198};
199#endif
200
201static struct spi_board_info bfin_spi_board_info[] __initdata = {
202#if defined(CONFIG_MTD_M25P80) \
203 || defined(CONFIG_MTD_M25P80_MODULE)
204 {
205 /* the modalias must be the same as spi device driver name */
206 .modalias = "m25p80", /* Name of spi_driver for this device */
207 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
208 .bus_num = 0, /* Framework bus number */
209 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
210 .platform_data = &bfin_spi_flash_data,
211 .controller_data = &spi_flash_chip_info,
212 .mode = SPI_MODE_3,
213 },
214#endif
215
216#if defined(CONFIG_SPI_ADC_BF533) \
217 || defined(CONFIG_SPI_ADC_BF533_MODULE)
218 {
219 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
220 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
221 .bus_num = 0, /* Framework bus number */
222 .chip_select = 1, /* Framework chip select. */
223 .platform_data = NULL, /* No spi_driver specific config */
224 .controller_data = &spi_adc_chip_info,
225 },
226#endif
227
228#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
229 {
230 .modalias = "spi_mmc_dummy",
231 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
232 .bus_num = 0,
233 .chip_select = 0,
234 .platform_data = NULL,
235 .controller_data = &spi_mmc_chip_info,
236 .mode = SPI_MODE_3,
237 },
238 {
239 .modalias = "spi_mmc",
240 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
241 .bus_num = 0,
242 .chip_select = CONFIG_SPI_MMC_CS_CHAN,
243 .platform_data = NULL,
244 .controller_data = &spi_mmc_chip_info,
245 .mode = SPI_MODE_3,
246 },
247#endif
248#if defined(CONFIG_PBX)
249 {
250 .modalias = "fxs-spi",
251 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
252 .bus_num = 0,
253 .chip_select = 8 - CONFIG_J11_JUMPER,
254 .controller_data = &spi_si3xxx_chip_info,
255 .mode = SPI_MODE_3,
256 },
257 {
258 .modalias = "fxo-spi",
259 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
260 .bus_num = 0,
261 .chip_select = 8 - CONFIG_J19_JUMPER,
262 .controller_data = &spi_si3xxx_chip_info,
263 .mode = SPI_MODE_3,
264 },
265#endif
266#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
267 {
268 .modalias = "ad7877",
269 .platform_data = &bfin_ad7877_ts_info,
270 .irq = IRQ_PF8,
271 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
272 .bus_num = 0,
273 .chip_select = 2,
274 .controller_data = &spi_ad7877_chip_info,
275 },
276#endif
277#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
278 && defined(CONFIG_SND_SOC_WM8731_SPI)
279 {
280 .modalias = "wm8731",
281 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
282 .bus_num = 0,
283 .chip_select = 5,
284 .controller_data = &spi_wm8731_chip_info,
285 .mode = SPI_MODE_0,
286 },
287#endif
288#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
289 {
290 .modalias = "spidev",
291 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
292 .bus_num = 0,
293 .chip_select = 1,
294 .controller_data = &spidev_chip_info,
295 },
296#endif
297#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
298 {
299 .modalias = "bfin-lq035q1-spi",
300 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
301 .bus_num = 0,
302 .chip_select = 1,
303 .controller_data = &lq035q1_spi_chip_info,
304 .mode = SPI_CPHA | SPI_CPOL,
305 },
306#endif
307};
308
309/* SPI controller data */
310#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
311/* SPI (0) */
312static struct bfin5xx_spi_master bfin_spi0_info = {
313 .num_chipselect = 5,
314 .enable_dma = 1, /* master has the ability to do dma transfer */
315 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
316};
317
318static struct resource bfin_spi0_resource[] = {
319 [0] = {
320 .start = SPI0_REGBASE,
321 .end = SPI0_REGBASE + 0xFF,
322 .flags = IORESOURCE_MEM,
323 },
324 [1] = {
325 .start = CH_SPI0,
326 .end = CH_SPI0,
327 .flags = IORESOURCE_IRQ,
328 },
329};
330
331static struct platform_device bfin_spi0_device = {
332 .name = "bfin-spi",
333 .id = 0, /* Bus number */
334 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
335 .resource = bfin_spi0_resource,
336 .dev = {
337 .platform_data = &bfin_spi0_info, /* Passed to driver */
338 },
339};
340
341/* SPI (1) */
342static struct bfin5xx_spi_master bfin_spi1_info = {
343 .num_chipselect = 5,
344 .enable_dma = 1, /* master has the ability to do dma transfer */
345 .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
346};
347
348static struct resource bfin_spi1_resource[] = {
349 [0] = {
350 .start = SPI1_REGBASE,
351 .end = SPI1_REGBASE + 0xFF,
352 .flags = IORESOURCE_MEM,
353 },
354 [1] = {
355 .start = CH_SPI1,
356 .end = CH_SPI1,
357 .flags = IORESOURCE_IRQ,
358 },
359};
360
361static struct platform_device bfin_spi1_device = {
362 .name = "bfin-spi",
363 .id = 1, /* Bus number */
364 .num_resources = ARRAY_SIZE(bfin_spi1_resource),
365 .resource = bfin_spi1_resource,
366 .dev = {
367 .platform_data = &bfin_spi1_info, /* Passed to driver */
368 },
369};
370#endif /* spi master and devices */
371
372#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
373static struct resource bfin_uart_resources[] = {
374#ifdef CONFIG_SERIAL_BFIN_UART0
375 {
376 .start = 0xFFC00400,
377 .end = 0xFFC004FF,
378 .flags = IORESOURCE_MEM,
379 },
380#endif
381#ifdef CONFIG_SERIAL_BFIN_UART1
382 {
383 .start = 0xFFC02000,
384 .end = 0xFFC020FF,
385 .flags = IORESOURCE_MEM,
386 },
387#endif
388};
389
390static struct platform_device bfin_uart_device = {
391 .name = "bfin-uart",
392 .id = 1,
393 .num_resources = ARRAY_SIZE(bfin_uart_resources),
394 .resource = bfin_uart_resources,
395};
396#endif
397
398#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
399static struct resource bfin_sir_resources[] = {
400#ifdef CONFIG_BFIN_SIR0
401 {
402 .start = 0xFFC00400,
403 .end = 0xFFC004FF,
404 .flags = IORESOURCE_MEM,
405 },
406#endif
407#ifdef CONFIG_BFIN_SIR1
408 {
409 .start = 0xFFC02000,
410 .end = 0xFFC020FF,
411 .flags = IORESOURCE_MEM,
412 },
413#endif
414};
415
416static struct platform_device bfin_sir_device = {
417 .name = "bfin_sir",
418 .id = 0,
419 .num_resources = ARRAY_SIZE(bfin_sir_resources),
420 .resource = bfin_sir_resources,
421};
422#endif
423
424#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
425static struct resource bfin_twi0_resource[] = {
426 [0] = {
427 .start = TWI0_REGBASE,
428 .end = TWI0_REGBASE,
429 .flags = IORESOURCE_MEM,
430 },
431 [1] = {
432 .start = IRQ_TWI,
433 .end = IRQ_TWI,
434 .flags = IORESOURCE_IRQ,
435 },
436};
437
438static struct platform_device i2c_bfin_twi_device = {
439 .name = "i2c-bfin-twi",
440 .id = 0,
441 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
442 .resource = bfin_twi0_resource,
443};
444#endif
445
446#ifdef CONFIG_I2C_BOARDINFO
447static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
448#if defined(CONFIG_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE)
449 {
450 I2C_BOARD_INFO("pcf8574_lcd", 0x22),
451 },
452#endif
453#if defined(CONFIG_TWI_KEYPAD) || defined(CONFIG_TWI_KEYPAD_MODULE)
454 {
455 I2C_BOARD_INFO("pcf8574_keypad", 0x27),
456 .irq = IRQ_PF8,
457 },
458#endif
459};
460#endif
461
462#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
463static struct platform_device bfin_sport0_uart_device = {
464 .name = "bfin-sport-uart",
465 .id = 0,
466};
467
468static struct platform_device bfin_sport1_uart_device = {
469 .name = "bfin-sport-uart",
470 .id = 1,
471};
472#endif
473
474#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
475#include <linux/input.h>
476#include <linux/gpio_keys.h>
477
478static struct gpio_keys_button bfin_gpio_keys_table[] = {
479 {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"},
480 {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"},
481};
482
483static struct gpio_keys_platform_data bfin_gpio_keys_data = {
484 .buttons = bfin_gpio_keys_table,
485 .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
486};
487
488static struct platform_device bfin_device_gpiokeys = {
489 .name = "gpio-keys",
490 .dev = {
491 .platform_data = &bfin_gpio_keys_data,
492 },
493};
494#endif
495
496static struct resource bfin_gpios_resources = {
497 .start = 0,
498 .end = MAX_BLACKFIN_GPIOS - 1,
499 .flags = IORESOURCE_IRQ,
500};
501
502static struct platform_device bfin_gpios_device = {
503 .name = "simple-gpio",
504 .id = -1,
505 .num_resources = 1,
506 .resource = &bfin_gpios_resources,
507};
508
509static const unsigned int cclk_vlev_datasheet[] =
510{
511 VRPAIR(VLEV_100, 400000000),
512 VRPAIR(VLEV_105, 426000000),
513 VRPAIR(VLEV_110, 500000000),
514 VRPAIR(VLEV_115, 533000000),
515 VRPAIR(VLEV_120, 600000000),
516};
517
518static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
519 .tuple_tab = cclk_vlev_datasheet,
520 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
521 .vr_settling_time = 25 /* us */,
522};
523
524static struct platform_device bfin_dpmc = {
525 .name = "bfin dpmc",
526 .dev = {
527 .platform_data = &bfin_dmpc_vreg_data,
528 },
529};
530
531static struct platform_device *stamp_devices[] __initdata = {
532
533 &bfin_dpmc,
534
535#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
536 &rtc_device,
537#endif
538
539#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
540 &bfin_mac_device,
541#endif
542
543#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
544 &bfin_spi0_device,
545 &bfin_spi1_device,
546#endif
547
548#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
549 &bfin_uart_device,
550#endif
551
552#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
553 &bfin_sir_device,
554#endif
555
556#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
557 &i2c_bfin_twi_device,
558#endif
559
560#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
561 &bfin_sport0_uart_device,
562 &bfin_sport1_uart_device,
563#endif
564
565#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
566 &bfin_device_gpiokeys,
567#endif
568
569#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
570 &ezbrd_flash_device,
571#endif
572
573 &bfin_gpios_device,
574};
575
576static int __init ezbrd_init(void)
577{
578 printk(KERN_INFO "%s(): registering device resources\n", __func__);
579
580#ifdef CONFIG_I2C_BOARDINFO
581 i2c_register_board_info(0, bfin_i2c_board_info,
582 ARRAY_SIZE(bfin_i2c_board_info));
583#endif
584
585 platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
586 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
587 return 0;
588}
589
590arch_initcall(ezbrd_init);
591
592void native_machine_restart(char *cmd)
593{
594 /* workaround reboot hang when booting from SPI */
595 if ((bfin_read_SYSCR() & 0x7) == 0x3)
596 bfin_gpio_reset_spi0_ssel1();
597}
598
599void bfin_get_ether_addr(char *addr)
600{
601 /* the MAC is stored in OTP memory page 0xDF */
602 u32 ret;
603 u64 otp_mac;
604 u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
605
606 ret = otp_read(0xDF, 0x00, &otp_mac);
607 if (!(ret & 0x1)) {
608 char *otp_mac_p = (char *)&otp_mac;
609 for (ret = 0; ret < 6; ++ret)
610 addr[ret] = otp_mac_p[5 - ret];
611 }
612}
613EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf518/dma.c b/arch/blackfin/mach-bf518/dma.c
new file mode 100644
index 000000000000..0d06ced01ced
--- /dev/null
+++ b/arch/blackfin/mach-bf518/dma.c
@@ -0,0 +1,118 @@
1/*
2 * File: arch/blackfin/mach-bf518/dma.c
3 * Based on:
4 * Author: Bryan Wu <cooloney@kernel.org>
5 *
6 * Created:
7 * Description: This file contains the simple DMA Implementation for Blackfin
8 *
9 * Modified:
10 * Copyright 2004-2008 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29#include <linux/module.h>
30
31#include <asm/blackfin.h>
32#include <asm/dma.h>
33
34struct dma_register *dma_io_base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
35 (struct dma_register *) DMA0_NEXT_DESC_PTR,
36 (struct dma_register *) DMA1_NEXT_DESC_PTR,
37 (struct dma_register *) DMA2_NEXT_DESC_PTR,
38 (struct dma_register *) DMA3_NEXT_DESC_PTR,
39 (struct dma_register *) DMA4_NEXT_DESC_PTR,
40 (struct dma_register *) DMA5_NEXT_DESC_PTR,
41 (struct dma_register *) DMA6_NEXT_DESC_PTR,
42 (struct dma_register *) DMA7_NEXT_DESC_PTR,
43 (struct dma_register *) DMA8_NEXT_DESC_PTR,
44 (struct dma_register *) DMA9_NEXT_DESC_PTR,
45 (struct dma_register *) DMA10_NEXT_DESC_PTR,
46 (struct dma_register *) DMA11_NEXT_DESC_PTR,
47 (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
48 (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
49 (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
50 (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
51};
52EXPORT_SYMBOL(dma_io_base_addr);
53
54int channel2irq(unsigned int channel)
55{
56 int ret_irq = -1;
57
58 switch (channel) {
59 case CH_PPI:
60 ret_irq = IRQ_PPI;
61 break;
62
63 case CH_EMAC_RX:
64 ret_irq = IRQ_MAC_RX;
65 break;
66
67 case CH_EMAC_TX:
68 ret_irq = IRQ_MAC_TX;
69 break;
70
71 case CH_UART1_RX:
72 ret_irq = IRQ_UART1_RX;
73 break;
74
75 case CH_UART1_TX:
76 ret_irq = IRQ_UART1_TX;
77 break;
78
79 case CH_SPORT0_RX:
80 ret_irq = IRQ_SPORT0_RX;
81 break;
82
83 case CH_SPORT0_TX:
84 ret_irq = IRQ_SPORT0_TX;
85 break;
86
87 case CH_SPORT1_RX:
88 ret_irq = IRQ_SPORT1_RX;
89 break;
90
91 case CH_SPORT1_TX:
92 ret_irq = IRQ_SPORT1_TX;
93 break;
94
95 case CH_SPI0:
96 ret_irq = IRQ_SPI0;
97 break;
98
99 case CH_UART0_RX:
100 ret_irq = IRQ_UART0_RX;
101 break;
102
103 case CH_UART0_TX:
104 ret_irq = IRQ_UART0_TX;
105 break;
106
107 case CH_MEM_STREAM0_SRC:
108 case CH_MEM_STREAM0_DEST:
109 ret_irq = IRQ_MEM_DMA0;
110 break;
111
112 case CH_MEM_STREAM1_SRC:
113 case CH_MEM_STREAM1_DEST:
114 ret_irq = IRQ_MEM_DMA1;
115 break;
116 }
117 return ret_irq;
118}
diff --git a/arch/blackfin/mach-bf518/head.S b/arch/blackfin/mach-bf518/head.S
new file mode 100644
index 000000000000..771bf7e477ff
--- /dev/null
+++ b/arch/blackfin/mach-bf518/head.S
@@ -0,0 +1,146 @@
1/*
2 * File: arch/blackfin/mach-bf518/head.S
3 * Based on: arch/blackfin/mach-bf527/head.S
4 * Author: Bryan Wu <cooloney@kernel.org>
5 *
6 * Created: 2008
7 * Description: Startup code for Blackfin BF51x
8 *
9 * Modified:
10 * Copyright 2004-2008 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <linux/linkage.h>
31#include <linux/init.h>
32#include <asm/blackfin.h>
33#ifdef CONFIG_BFIN_KERNEL_CLOCK
34#include <asm/mach-common/clocks.h>
35#include <asm/mach/mem_init.h>
36#endif
37
38.section .l1.text
39#ifdef CONFIG_BFIN_KERNEL_CLOCK
40ENTRY(_start_dma_code)
41
42 /* Enable PHY CLK buffer output */
43 p0.h = hi(VR_CTL);
44 p0.l = lo(VR_CTL);
45 r0.l = w[p0];
46 bitset(r0, 14);
47 w[p0] = r0.l;
48 ssync;
49
50 p0.h = hi(SIC_IWR0);
51 p0.l = lo(SIC_IWR0);
52 r0.l = 0x1;
53 r0.h = 0x0;
54 [p0] = r0;
55 ssync;
56
57 /*
58 * Set PLL_CTL
59 * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
60 * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
61 * - [7] = output delay (add 200ps of delay to mem signals)
62 * - [6] = input delay (add 200ps of input delay to mem signals)
63 * - [5] = PDWN : 1=All Clocks off
64 * - [3] = STOPCK : 1=Core Clock off
65 * - [1] = PLL_OFF : 1=Disable Power to PLL
66 * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
67 * all other bits set to zero
68 */
69
70 p0.h = hi(PLL_LOCKCNT);
71 p0.l = lo(PLL_LOCKCNT);
72 r0 = 0x300(Z);
73 w[p0] = r0.l;
74 ssync;
75
76 P2.H = hi(EBIU_SDGCTL);
77 P2.L = lo(EBIU_SDGCTL);
78 R0 = [P2];
79 BITSET (R0, 24);
80 [P2] = R0;
81 ssync;
82
83 r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
84 r0 = r0 << 9; /* Shift it over, */
85 r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
86 r0 = r1 | r0;
87 r1 = PLL_BYPASS; /* Bypass the PLL? */
88 r1 = r1 << 8; /* Shift it over */
89 r0 = r1 | r0; /* add them all together */
90#ifdef ANOMALY_05000265
91 BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
92#endif
93
94 p0.h = hi(PLL_CTL);
95 p0.l = lo(PLL_CTL); /* Load the address */
96 cli r2; /* Disable interrupts */
97 ssync;
98 w[p0] = r0.l; /* Set the value */
99 idle; /* Wait for the PLL to stablize */
100 sti r2; /* Enable interrupts */
101
102.Lcheck_again:
103 p0.h = hi(PLL_STAT);
104 p0.l = lo(PLL_STAT);
105 R0 = W[P0](Z);
106 CC = BITTST(R0,5);
107 if ! CC jump .Lcheck_again;
108
109 /* Configure SCLK & CCLK Dividers */
110 r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
111 p0.h = hi(PLL_DIV);
112 p0.l = lo(PLL_DIV);
113 w[p0] = r0.l;
114 ssync;
115
116 p0.l = lo(EBIU_SDRRC);
117 p0.h = hi(EBIU_SDRRC);
118 r0 = mem_SDRRC;
119 w[p0] = r0.l;
120 ssync;
121
122 P2.H = hi(EBIU_SDGCTL);
123 P2.L = lo(EBIU_SDGCTL);
124 R0 = [P2];
125 BITCLR (R0, 24);
126 p0.h = hi(EBIU_SDSTAT);
127 p0.l = lo(EBIU_SDSTAT);
128 r2.l = w[p0];
129 cc = bittst(r2,3);
130 if !cc jump .Lskip;
131 NOP;
132 BITSET (R0, 23);
133.Lskip:
134 [P2] = R0;
135 SSYNC;
136
137 R0.L = lo(mem_SDGCTL);
138 R0.H = hi(mem_SDGCTL);
139 R1 = [p2];
140 R1 = R1 | R0;
141 [P2] = R1;
142 SSYNC;
143
144 RTS;
145ENDPROC(_start_dma_code)
146#endif /* CONFIG_BFIN_KERNEL_CLOCK */
diff --git a/arch/blackfin/mach-bf518/include/mach/anomaly.h b/arch/blackfin/mach-bf518/include/mach/anomaly.h
new file mode 100644
index 000000000000..5a94f97f04ad
--- /dev/null
+++ b/arch/blackfin/mach-bf518/include/mach/anomaly.h
@@ -0,0 +1,77 @@
1/*
2 * File: include/asm-blackfin/mach-bf518/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 *
5 * Copyright (C) 2004-2008 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
7 */
8
9/* This file shoule be up to date with:
10 * - ????
11 */
12
13#ifndef _MACH_ANOMALY_H_
14#define _MACH_ANOMALY_H_
15
16/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
17#define ANOMALY_05000074 (1)
18/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
19#define ANOMALY_05000122 (1)
20/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
21#define ANOMALY_05000245 (1)
22/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
23#define ANOMALY_05000265 (1)
24/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
25#define ANOMALY_05000310 (1)
26/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
27#define ANOMALY_05000366 (1)
28/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
29#define ANOMALY_05000405 (1)
30/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
31#define ANOMALY_05000408 (1)
32/* Speculative Fetches Can Cause Undesired External FIFO Operations */
33#define ANOMALY_05000416 (1)
34/* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */
35#define ANOMALY_05000421 (1)
36/* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */
37#define ANOMALY_05000422 (1)
38/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
39#define ANOMALY_05000426 (1)
40/* Software System Reset Corrupts PLL_LOCKCNT Register */
41#define ANOMALY_05000430 (1)
42/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
43#define ANOMALY_05000431 (1)
44/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
45#define ANOMALY_05000435 (1)
46/* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */
47#define ANOMALY_05000438 (1)
48/* Preboot Cannot be Used to Program the PLL_DIV Register */
49#define ANOMALY_05000439 (1)
50/* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */
51#define ANOMALY_05000440 (1)
52/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
53#define ANOMALY_05000443 (1)
54/* Incorrect L1 Instruction Bank B Memory Map Location */
55#define ANOMALY_05000444 (1)
56
57/* Anomalies that don't exist on this proc */
58#define ANOMALY_05000125 (0)
59#define ANOMALY_05000158 (0)
60#define ANOMALY_05000183 (0)
61#define ANOMALY_05000198 (0)
62#define ANOMALY_05000230 (0)
63#define ANOMALY_05000244 (0)
64#define ANOMALY_05000261 (0)
65#define ANOMALY_05000263 (0)
66#define ANOMALY_05000266 (0)
67#define ANOMALY_05000273 (0)
68#define ANOMALY_05000285 (0)
69#define ANOMALY_05000307 (0)
70#define ANOMALY_05000311 (0)
71#define ANOMALY_05000312 (0)
72#define ANOMALY_05000323 (0)
73#define ANOMALY_05000353 (0)
74#define ANOMALY_05000363 (0)
75#define ANOMALY_05000386 (0)
76
77#endif
diff --git a/arch/blackfin/mach-bf518/include/mach/bf518.h b/arch/blackfin/mach-bf518/include/mach/bf518.h
new file mode 100644
index 000000000000..78da1a07ee73
--- /dev/null
+++ b/arch/blackfin/mach-bf518/include/mach/bf518.h
@@ -0,0 +1,132 @@
1/*
2 * File: include/asm-blackfin/mach-bf518/bf518.h
3 * Based on: include/asm-blackfin/mach-bf527/bf527.h
4 * Author: Michael Hennerich (michael.hennerich@analog.com)
5 *
6 * Created:
7 * Description: SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF518
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#ifndef __MACH_BF518_H__
31#define __MACH_BF518_H__
32
33#define OFFSET_(x) ((x) & 0x0000FFFF)
34
35/*some misc defines*/
36#define IMASK_IVG15 0x8000
37#define IMASK_IVG14 0x4000
38#define IMASK_IVG13 0x2000
39#define IMASK_IVG12 0x1000
40
41#define IMASK_IVG11 0x0800
42#define IMASK_IVG10 0x0400
43#define IMASK_IVG9 0x0200
44#define IMASK_IVG8 0x0100
45
46#define IMASK_IVG7 0x0080
47#define IMASK_IVGTMR 0x0040
48#define IMASK_IVGHW 0x0020
49
50/***************************/
51
52#define BFIN_DSUBBANKS 4
53#define BFIN_DWAYS 2
54#define BFIN_DLINES 64
55#define BFIN_ISUBBANKS 4
56#define BFIN_IWAYS 4
57#define BFIN_ILINES 32
58
59#define WAY0_L 0x1
60#define WAY1_L 0x2
61#define WAY01_L 0x3
62#define WAY2_L 0x4
63#define WAY02_L 0x5
64#define WAY12_L 0x6
65#define WAY012_L 0x7
66
67#define WAY3_L 0x8
68#define WAY03_L 0x9
69#define WAY13_L 0xA
70#define WAY013_L 0xB
71
72#define WAY32_L 0xC
73#define WAY320_L 0xD
74#define WAY321_L 0xE
75#define WAYALL_L 0xF
76
77#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
78
79/********************************* EBIU Settings ************************************/
80#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
81#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
82
83#ifdef CONFIG_C_AMBEN_ALL
84#define V_AMBEN AMBEN_ALL
85#endif
86#ifdef CONFIG_C_AMBEN
87#define V_AMBEN 0x0
88#endif
89#ifdef CONFIG_C_AMBEN_B0
90#define V_AMBEN AMBEN_B0
91#endif
92#ifdef CONFIG_C_AMBEN_B0_B1
93#define V_AMBEN AMBEN_B0_B1
94#endif
95#ifdef CONFIG_C_AMBEN_B0_B1_B2
96#define V_AMBEN AMBEN_B0_B1_B2
97#endif
98#ifdef CONFIG_C_AMCKEN
99#define V_AMCKEN AMCKEN
100#else
101#define V_AMCKEN 0x0
102#endif
103#ifdef CONFIG_C_CDPRIO
104#define V_CDPRIO 0x100
105#else
106#define V_CDPRIO 0x0
107#endif
108
109#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
110
111#ifdef CONFIG_BF518
112#define CPU "BF518"
113#define CPUID 0x27e8
114#endif
115#ifdef CONFIG_BF516
116#define CPU "BF516"
117#define CPUID 0x27e8
118#endif
119#ifdef CONFIG_BF514
120#define CPU "BF514"
121#define CPUID 0x27e8
122#endif
123#ifdef CONFIG_BF512
124#define CPU "BF512"
125#define CPUID 0x27e8
126#endif
127
128#ifndef CPU
129#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
130#endif
131
132#endif /* __MACH_BF518_H__ */
diff --git a/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h
new file mode 100644
index 000000000000..b50a63b975a2
--- /dev/null
+++ b/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h
@@ -0,0 +1,169 @@
1/*
2 * file: include/asm-blackfin/mach-bf518/bfin_serial_5xx.h
3 * based on:
4 * author:
5 *
6 * created:
7 * description:
8 * blackfin serial driver head file
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
32#include <linux/serial.h>
33#include <asm/dma.h>
34#include <asm/portmux.h>
35
36#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
37#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
38#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
39#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
40#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
41#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
42#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
43
44#define UART_PUT_CHAR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_THR), v)
45#define UART_PUT_DLL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLL), v)
46#define UART_PUT_IER(uart, v) bfin_write16(((uart)->port.membase + OFFSET_IER), v)
47#define UART_SET_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
48#define UART_CLEAR_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
49#define UART_PUT_DLH(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLH), v)
50#define UART_PUT_LCR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_LCR), v)
51#define UART_PUT_GCTL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_GCTL), v)
52
53#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
54#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
55
56#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
57#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1)
58#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0)
59#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
60#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
61
62#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
63# define CONFIG_SERIAL_BFIN_CTSRTS
64
65# ifndef CONFIG_UART0_CTS_PIN
66# define CONFIG_UART0_CTS_PIN -1
67# endif
68
69# ifndef CONFIG_UART0_RTS_PIN
70# define CONFIG_UART0_RTS_PIN -1
71# endif
72
73# ifndef CONFIG_UART1_CTS_PIN
74# define CONFIG_UART1_CTS_PIN -1
75# endif
76
77# ifndef CONFIG_UART1_RTS_PIN
78# define CONFIG_UART1_RTS_PIN -1
79# endif
80#endif
81
82#define BFIN_UART_TX_FIFO_SIZE 2
83
84/*
85 * The pin configuration is different from schematic
86 */
87struct bfin_serial_port {
88 struct uart_port port;
89 unsigned int old_status;
90 unsigned int lsr;
91#ifdef CONFIG_SERIAL_BFIN_DMA
92 int tx_done;
93 int tx_count;
94 struct circ_buf rx_dma_buf;
95 struct timer_list rx_dma_timer;
96 int rx_dma_nrows;
97 unsigned int tx_dma_channel;
98 unsigned int rx_dma_channel;
99 struct work_struct tx_dma_workqueue;
100#endif
101#ifdef CONFIG_SERIAL_BFIN_CTSRTS
102 struct timer_list cts_timer;
103 int cts_pin;
104 int rts_pin;
105#endif
106};
107
108/* The hardware clears the LSR bits upon read, so we need to cache
109 * some of the more fun bits in software so they don't get lost
110 * when checking the LSR in other code paths (TX).
111 */
112static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
113{
114 unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
115 uart->lsr |= (lsr & (BI|FE|PE|OE));
116 return lsr | uart->lsr;
117}
118
119static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
120{
121 uart->lsr = 0;
122 bfin_write16(uart->port.membase + OFFSET_LSR, -1);
123}
124
125struct bfin_serial_res {
126 unsigned long uart_base_addr;
127 int uart_irq;
128#ifdef CONFIG_SERIAL_BFIN_DMA
129 unsigned int uart_tx_dma_channel;
130 unsigned int uart_rx_dma_channel;
131#endif
132#ifdef CONFIG_SERIAL_BFIN_CTSRTS
133 int uart_cts_pin;
134 int uart_rts_pin;
135#endif
136};
137
138struct bfin_serial_res bfin_serial_resource[] = {
139#ifdef CONFIG_SERIAL_BFIN_UART0
140 {
141 0xFFC00400,
142 IRQ_UART0_RX,
143#ifdef CONFIG_SERIAL_BFIN_DMA
144 CH_UART0_TX,
145 CH_UART0_RX,
146#endif
147#ifdef CONFIG_BFIN_UART0_CTSRTS
148 CONFIG_UART0_CTS_PIN,
149 CONFIG_UART0_RTS_PIN,
150#endif
151 },
152#endif
153#ifdef CONFIG_SERIAL_BFIN_UART1
154 {
155 0xFFC02000,
156 IRQ_UART1_RX,
157#ifdef CONFIG_SERIAL_BFIN_DMA
158 CH_UART1_TX,
159 CH_UART1_RX,
160#endif
161#ifdef CONFIG_BFIN_UART1_CTSRTS
162 CONFIG_UART1_CTS_PIN,
163 CONFIG_UART1_RTS_PIN,
164#endif
165 },
166#endif
167};
168
169#define DRIVER_NAME "bfin-uart"
diff --git a/arch/blackfin/mach-bf518/include/mach/bfin_sir.h b/arch/blackfin/mach-bf518/include/mach/bfin_sir.h
new file mode 100644
index 000000000000..cfd8ad4f1f2c
--- /dev/null
+++ b/arch/blackfin/mach-bf518/include/mach/bfin_sir.h
@@ -0,0 +1,142 @@
1/*
2 * Blackfin Infra-red Driver
3 *
4 * Copyright 2006-2008 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 *
10 */
11
12#include <linux/serial.h>
13#include <asm/dma.h>
14#include <asm/portmux.h>
15
16#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR)
17#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL)
18#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER)
19#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH)
20#define SIR_UART_GET_IIR(port) bfin_read16((port)->membase + OFFSET_IIR)
21#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR)
22#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL)
23
24#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
25#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v)
26#define SIR_UART_PUT_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER), v)
27#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v)
28#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v)
29#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
30
31#ifdef CONFIG_SIR_BFIN_DMA
32struct dma_rx_buf {
33 char *buf;
34 int head;
35 int tail;
36 };
37#endif /* CONFIG_SIR_BFIN_DMA */
38
39struct bfin_sir_port {
40 unsigned char __iomem *membase;
41 unsigned int irq;
42 unsigned int lsr;
43 unsigned long clk;
44 struct net_device *dev;
45#ifdef CONFIG_SIR_BFIN_DMA
46 int tx_done;
47 struct dma_rx_buf rx_dma_buf;
48 struct timer_list rx_dma_timer;
49 int rx_dma_nrows;
50#endif /* CONFIG_SIR_BFIN_DMA */
51 unsigned int tx_dma_channel;
52 unsigned int rx_dma_channel;
53};
54
55struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
56
57struct bfin_sir_port_res {
58 unsigned long base_addr;
59 int irq;
60 unsigned int rx_dma_channel;
61 unsigned int tx_dma_channel;
62};
63
64struct bfin_sir_port_res bfin_sir_port_resource[] = {
65#ifdef CONFIG_BFIN_SIR0
66 {
67 0xFFC00400,
68 IRQ_UART0_RX,
69 CH_UART0_RX,
70 CH_UART0_TX,
71 },
72#endif
73#ifdef CONFIG_BFIN_SIR1
74 {
75 0xFFC02000,
76 IRQ_UART1_RX,
77 CH_UART1_RX,
78 CH_UART1_TX,
79 },
80#endif
81};
82
83int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
84
85struct bfin_sir_self {
86 struct bfin_sir_port *sir_port;
87 spinlock_t lock;
88 unsigned int open;
89 int speed;
90 int newspeed;
91
92 struct sk_buff *txskb;
93 struct sk_buff *rxskb;
94 struct net_device_stats stats;
95 struct device *dev;
96 struct irlap_cb *irlap;
97 struct qos_info qos;
98
99 iobuff_t tx_buff;
100 iobuff_t rx_buff;
101
102 struct work_struct work;
103 int mtt;
104};
105
106static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port)
107{
108 unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR);
109 port->lsr |= (lsr & (BI|FE|PE|OE));
110 return lsr | port->lsr;
111}
112
113static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
114{
115 port->lsr = 0;
116 bfin_read16(port->membase + OFFSET_LSR);
117}
118
119#define DRIVER_NAME "bfin_sir"
120
121static int bfin_sir_hw_init(void)
122{
123 int ret = -ENODEV;
124#ifdef CONFIG_BFIN_SIR0
125 ret = peripheral_request(P_UART0_TX, DRIVER_NAME);
126 if (ret)
127 return ret;
128 ret = peripheral_request(P_UART0_RX, DRIVER_NAME);
129 if (ret)
130 return ret;
131#endif
132
133#ifdef CONFIG_BFIN_SIR1
134 ret = peripheral_request(P_UART1_TX, DRIVER_NAME);
135 if (ret)
136 return ret;
137 ret = peripheral_request(P_UART1_RX, DRIVER_NAME);
138 if (ret)
139 return ret;
140#endif
141 return ret;
142}
diff --git a/arch/blackfin/mach-bf518/include/mach/blackfin.h b/arch/blackfin/mach-bf518/include/mach/blackfin.h
new file mode 100644
index 000000000000..d1a2b9ca6227
--- /dev/null
+++ b/arch/blackfin/mach-bf518/include/mach/blackfin.h
@@ -0,0 +1,105 @@
1/*
2 * File: include/asm-blackfin/mach-bf518/blackfin.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#ifndef _MACH_BLACKFIN_H_
33#define _MACH_BLACKFIN_H_
34
35#define BF518_FAMILY
36
37#include "bf518.h"
38#include "mem_map.h"
39#include "defBF512.h"
40#include "anomaly.h"
41
42#if defined(CONFIG_BF518)
43#include "defBF518.h"
44#endif
45
46#if defined(CONFIG_BF516)
47#include "defBF516.h"
48#endif
49
50#if defined(CONFIG_BF514)
51#include "defBF514.h"
52#endif
53
54#if defined(CONFIG_BF512)
55#include "defBF512.h"
56#endif
57
58#if !defined(__ASSEMBLY__)
59#include "cdefBF512.h"
60
61#if defined(CONFIG_BF518)
62#include "cdefBF518.h"
63#endif
64
65#if defined(CONFIG_BF516)
66#include "cdefBF516.h"
67#endif
68
69#if defined(CONFIG_BF514)
70#include "cdefBF514.h"
71#endif
72#endif
73
74/* UART_IIR Register */
75#define STATUS(x) ((x << 1) & 0x06)
76#define STATUS_P1 0x02
77#define STATUS_P0 0x01
78
79#define BFIN_UART_NR_PORTS 2
80
81#define OFFSET_THR 0x00 /* Transmit Holding register */
82#define OFFSET_RBR 0x00 /* Receive Buffer register */
83#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
84#define OFFSET_IER 0x04 /* Interrupt Enable Register */
85#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
86#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
87#define OFFSET_LCR 0x0C /* Line Control Register */
88#define OFFSET_MCR 0x10 /* Modem Control Register */
89#define OFFSET_LSR 0x14 /* Line Status Register */
90#define OFFSET_MSR 0x18 /* Modem Status Register */
91#define OFFSET_SCR 0x1C /* SCR Scratch Register */
92#define OFFSET_GCTL 0x24 /* Global Control Register */
93
94/* DPMC*/
95#define bfin_read_STOPCK_OFF() bfin_read_STOPCK()
96#define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val)
97#define STOPCK_OFF STOPCK
98
99/* PLL_DIV Masks */
100#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
101#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */
102#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */
103#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */
104
105#endif
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF512.h b/arch/blackfin/mach-bf518/include/mach/cdefBF512.h
new file mode 100644
index 000000000000..820c13c4daaa
--- /dev/null
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF512.h
@@ -0,0 +1,46 @@
1/*
2 * File: include/asm-blackfin/mach-bf518/cdefbf512.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: system mmr register map
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#ifndef _CDEF_BF512_H
33#define _CDEF_BF512_H
34
35/* include all Core registers and bit definitions */
36#include "defBF512.h"
37
38/* include core specific register pointer definitions */
39#include <asm/cdef_LPBlackfin.h>
40
41/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF512 */
42
43/* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
44#include "cdefBF51x_base.h"
45
46#endif /* _CDEF_BF512_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF514.h b/arch/blackfin/mach-bf518/include/mach/cdefBF514.h
new file mode 100644
index 000000000000..9521e178fb28
--- /dev/null
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF514.h
@@ -0,0 +1,48 @@
1/*
2 * File: include/asm-blackfin/mach-bf518/cdefbf514.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: system mmr register map
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#ifndef _CDEF_BF514_H
33#define _CDEF_BF514_H
34
35/* include all Core registers and bit definitions */
36#include "defBF514.h"
37
38/* include core specific register pointer definitions */
39#include <asm/cdef_LPBlackfin.h>
40
41/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF514 */
42
43/* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
44#include "cdefBF51x_base.h"
45
46/* The following are the #defines needed by ADSP-BF514 that are not in the common header */
47
48#endif /* _CDEF_BF514_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF516.h b/arch/blackfin/mach-bf518/include/mach/cdefBF516.h
new file mode 100644
index 000000000000..17be34cbb7bf
--- /dev/null
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF516.h
@@ -0,0 +1,48 @@
1/*
2 * File: include/asm-blackfin/mach-bf518/cdefbf516.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: system mmr register map
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#ifndef _CDEF_BF516_H
33#define _CDEF_BF516_H
34
35/* include all Core registers and bit definitions */
36#include "defBF516.h"
37
38/* include core specific register pointer definitions */
39#include <asm/cdef_LPBlackfin.h>
40
41/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF516 */
42
43/* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
44#include "cdefBF51x_base.h"
45
46/* The following are the #defines needed by ADSP-BF516 that are not in the common header */
47
48#endif /* _CDEF_BF516_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF518.h b/arch/blackfin/mach-bf518/include/mach/cdefBF518.h
new file mode 100644
index 000000000000..5f978d48cc6d
--- /dev/null
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF518.h
@@ -0,0 +1,48 @@
1/*
2 * File: include/asm-blackfin/mach-bf518/cdefbf518.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: system mmr register map
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#ifndef _CDEF_BF518_H
33#define _CDEF_BF518_H
34
35/* include all Core registers and bit definitions */
36#include "defBF518.h"
37
38/* include core specific register pointer definitions */
39#include <asm/cdef_LPBlackfin.h>
40
41/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF518 */
42
43/* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
44#include "cdefBF51x_base.h"
45
46/* The following are the #defines needed by ADSP-BF518 that are not in the common header */
47
48#endif /* _CDEF_BF518_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h b/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h
new file mode 100644
index 000000000000..95d54e625970
--- /dev/null
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h
@@ -0,0 +1,1204 @@
1/*
2 * File: include/asm-blackfin/mach-bf518/cdefBF51x_base.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _CDEF_BF52X_H
32#define _CDEF_BF52X_H
33
34#include <asm/system.h>
35#include <asm/blackfin.h>
36
37#include "defBF51x_base.h"
38
39/* Include core specific register pointer definitions */
40#include <asm/cdef_LPBlackfin.h>
41
42/* ==== begin from cdefBF534.h ==== */
43
44/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
45#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
46/* Writing to PLL_CTL initiates a PLL relock sequence. */
47static __inline__ void bfin_write_PLL_CTL(unsigned int val)
48{
49 unsigned long flags, iwr0, iwr1;
50
51 if (val == bfin_read_PLL_CTL())
52 return;
53
54 local_irq_save(flags);
55 /* Enable the PLL Wakeup bit in SIC IWR */
56 iwr0 = bfin_read32(SIC_IWR0);
57 iwr1 = bfin_read32(SIC_IWR1);
58 /* Only allow PPL Wakeup) */
59 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
60 bfin_write32(SIC_IWR1, 0);
61
62 bfin_write16(PLL_CTL, val);
63 SSYNC();
64 asm("IDLE;");
65
66 bfin_write32(SIC_IWR0, iwr0);
67 bfin_write32(SIC_IWR1, iwr1);
68 local_irq_restore(flags);
69}
70#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
71#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
72#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
73/* Writing to VR_CTL initiates a PLL relock sequence. */
74static __inline__ void bfin_write_VR_CTL(unsigned int val)
75{
76 unsigned long flags, iwr0, iwr1;
77
78 if (val == bfin_read_VR_CTL())
79 return;
80
81 local_irq_save(flags);
82 /* Enable the PLL Wakeup bit in SIC IWR */
83 iwr0 = bfin_read32(SIC_IWR0);
84 iwr1 = bfin_read32(SIC_IWR1);
85 /* Only allow PPL Wakeup) */
86 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
87 bfin_write32(SIC_IWR1, 0);
88
89 bfin_write16(VR_CTL, val);
90 SSYNC();
91 asm("IDLE;");
92
93 bfin_write32(SIC_IWR0, iwr0);
94 bfin_write32(SIC_IWR1, iwr1);
95 local_irq_restore(flags);
96}
97#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
98#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
99#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
100#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
101#define bfin_read_CHIPID() bfin_read32(CHIPID)
102#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
103
104
105/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
106#define bfin_read_SWRST() bfin_read16(SWRST)
107#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
108#define bfin_read_SYSCR() bfin_read16(SYSCR)
109#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
110
111#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT)
112#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val)
113#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
114#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
115#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 6))
116#define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 6)), val)
117
118#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
119#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
120#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
121#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
122#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
123#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
124#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
125#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
126
127#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
128#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
129#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 6))
130#define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val)
131
132#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
133#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
134#define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + (x << 6))
135#define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + (x << 6)), val)
136
137/* SIC Additions to ADSP-BF51x (0xFFC0014C - 0xFFC00162) */
138
139#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
140#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
141#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
142#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
143#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
144#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
145#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
146#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
147#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
148#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
149#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
150#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
151#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
152#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
153
154/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
155#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
156#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
157#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
158#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
159#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
160#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
161
162
163/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
164#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
165#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
166#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
167#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
168#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
169#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
170#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
171#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
172#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
173#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
174#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST)
175#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST, val)
176#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
177#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
178
179
180/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
181#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
182#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
183#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
184#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
185#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
186#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
187#define bfin_read_UART0_IER() bfin_read16(UART0_IER)
188#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val)
189#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
190#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
191#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR)
192#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val)
193#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
194#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
195#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
196#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
197#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
198#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
199#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
200#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
201#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
202#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
203#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
204#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
205
206
207/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
208#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
209#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val)
210#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
211#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val)
212#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
213#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val)
214#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
215#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val)
216#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
217#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val)
218#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
219#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val)
220#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
221#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val)
222
223
224/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
225#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
226#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
227#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
228#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
229#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
230#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
231#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
232#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
233
234#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
235#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
236#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
237#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
238#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
239#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
240#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
241#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
242
243#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
244#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
245#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
246#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
247#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
248#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
249#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
250#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
251
252#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
253#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
254#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
255#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
256#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
257#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
258#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
259#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
260
261#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
262#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
263#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
264#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
265#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
266#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
267#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
268#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
269
270#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
271#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
272#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
273#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
274#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
275#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
276#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
277#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
278
279#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
280#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
281#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
282#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
283#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
284#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
285#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
286#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
287
288#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
289#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
290#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
291#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
292#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
293#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
294#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
295#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
296
297#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
298#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val)
299#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
300#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val)
301#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS)
302#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val)
303
304
305/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
306#define bfin_read_PORTFIO() bfin_read16(PORTFIO)
307#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val)
308#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR)
309#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val)
310#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET)
311#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val)
312#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE)
313#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
314#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA)
315#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val)
316#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
317#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
318#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET)
319#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
320#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
321#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
322#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB)
323#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val)
324#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
325#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
326#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET)
327#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
328#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
329#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
330#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR)
331#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val)
332#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR)
333#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val)
334#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE)
335#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val)
336#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH)
337#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val)
338#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN)
339#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val)
340
341
342/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
343#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
344#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
345#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
346#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
347#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
348#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
349#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
350#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
351#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
352#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
353#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
354#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
355#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX32)
356#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX32, val)
357#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX32)
358#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX32, val)
359#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX16)
360#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX16, val)
361#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX16)
362#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX16, val)
363#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
364#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
365#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
366#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
367#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
368#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
369#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
370#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
371#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
372#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
373#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
374#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
375#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
376#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
377#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
378#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
379#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
380#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
381#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
382#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
383#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
384#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
385#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
386#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
387#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
388#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
389#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
390#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
391#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
392#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
393#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
394#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
395
396
397/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
398#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
399#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
400#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
401#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
402#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
403#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
404#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
405#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
406#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
407#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
408#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
409#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
410#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX32)
411#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX32, val)
412#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX32)
413#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX32, val)
414#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX16)
415#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX16, val)
416#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX16)
417#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX16, val)
418#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
419#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
420#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
421#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
422#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
423#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
424#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
425#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
426#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
427#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
428#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
429#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
430#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
431#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
432#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
433#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
434#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
435#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
436#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
437#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
438#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
439#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
440#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
441#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
442#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
443#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
444#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
445#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
446#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
447#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
448#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
449#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
450
451
452/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
453#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
454#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
455#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
456#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
457#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
458#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
459#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
460#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val)
461#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
462#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
463#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
464#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val)
465#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
466#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val)
467
468
469/* DMA Traffic Control Registers */
470#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER)
471#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER, val)
472#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT)
473#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val)
474
475/* Alternate deprecated register names (below) provided for backwards code compatibility */
476#define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER)
477#define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER, val)
478#define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT)
479#define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT, val)
480
481/* DMA Controller */
482#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
483#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
484#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
485#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
486#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
487#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
488#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
489#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
490#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
491#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
492#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
493#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
494#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
495#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
496#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
497#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
498#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
499#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
500#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
501#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
502#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
503#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
504#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
505#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
506#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
507#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
508
509#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
510#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
511#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
512#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
513#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
514#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
515#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
516#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
517#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
518#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
519#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
520#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
521#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
522#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
523#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
524#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
525#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
526#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
527#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
528#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
529#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
530#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
531#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
532#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
533#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
534#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
535
536#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
537#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
538#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
539#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
540#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
541#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
542#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
543#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
544#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
545#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
546#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
547#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
548#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
549#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
550#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
551#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
552#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
553#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
554#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
555#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
556#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
557#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
558#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
559#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
560#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
561#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
562
563#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
564#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
565#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
566#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
567#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
568#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
569#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
570#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
571#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
572#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
573#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
574#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
575#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
576#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
577#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
578#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
579#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
580#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
581#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
582#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
583#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
584#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
585#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
586#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
587#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
588#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
589
590#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
591#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
592#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
593#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
594#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
595#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
596#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
597#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
598#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
599#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
600#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
601#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
602#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
603#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
604#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
605#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
606#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
607#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
608#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
609#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
610#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
611#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
612#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
613#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
614#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
615#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
616
617#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
618#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
619#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
620#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
621#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
622#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
623#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
624#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
625#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
626#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
627#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
628#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
629#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
630#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
631#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
632#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
633#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
634#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
635#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
636#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
637#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
638#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
639#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
640#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
641#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
642#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
643
644#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
645#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
646#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
647#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
648#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
649#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
650#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
651#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
652#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
653#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
654#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
655#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
656#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
657#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
658#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
659#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
660#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
661#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
662#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
663#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
664#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
665#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
666#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
667#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
668#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
669#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
670
671#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
672#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
673#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
674#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
675#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
676#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
677#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
678#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
679#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
680#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
681#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
682#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
683#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
684#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
685#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
686#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
687#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
688#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
689#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
690#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
691#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
692#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
693#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
694#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
695#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
696#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
697
698#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
699#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
700#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR)
701#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val)
702#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR)
703#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val)
704#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
705#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
706#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
707#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
708#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
709#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
710#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
711#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
712#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR)
713#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val)
714#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR)
715#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val)
716#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
717#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
718#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
719#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
720#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
721#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
722#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
723#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
724
725#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
726#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
727#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR)
728#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val)
729#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR)
730#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val)
731#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
732#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
733#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
734#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
735#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
736#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
737#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
738#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
739#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR)
740#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val)
741#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR)
742#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val)
743#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
744#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
745#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
746#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
747#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
748#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
749#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
750#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
751
752#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
753#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
754#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR)
755#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val)
756#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR)
757#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val)
758#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
759#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
760#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
761#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
762#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
763#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
764#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
765#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
766#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR)
767#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val)
768#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR)
769#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val)
770#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
771#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
772#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
773#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
774#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
775#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
776#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
777#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
778
779#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
780#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
781#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR)
782#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val)
783#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR)
784#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val)
785#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
786#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
787#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
788#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
789#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
790#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
791#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
792#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
793#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR)
794#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val)
795#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR)
796#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val)
797#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
798#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
799#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
800#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
801#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
802#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
803#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
804#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
805
806#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
807#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
808#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
809#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
810#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
811#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val)
812#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
813#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
814#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
815#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
816#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
817#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
818#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
819#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
820#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
821#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
822#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
823#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val)
824#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
825#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
826#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
827#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
828#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
829#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
830#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
831#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
832
833#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
834#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
835#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
836#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
837#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
838#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val)
839#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
840#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
841#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
842#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
843#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
844#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
845#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
846#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
847#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
848#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
849#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
850#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val)
851#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
852#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
853#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
854#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
855#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
856#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
857#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
858#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
859
860#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
861#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
862#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
863#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
864#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
865#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val)
866#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
867#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
868#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
869#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
870#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
871#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
872#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
873#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
874#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
875#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
876#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
877#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val)
878#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
879#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
880#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
881#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
882#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
883#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
884#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
885#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
886
887#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
888#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
889#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
890#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
891#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
892#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val)
893#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
894#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
895#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
896#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
897#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
898#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
899#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
900#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
901#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
902#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
903#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
904#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val)
905#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
906#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
907#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
908#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
909#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
910#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
911#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
912#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
913
914
915/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
916#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
917#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val)
918#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
919#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val)
920#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
921#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val)
922#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
923#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val)
924#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
925#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val)
926
927
928/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
929
930/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
931#define bfin_read_PORTGIO() bfin_read16(PORTGIO)
932#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val)
933#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR)
934#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val)
935#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET)
936#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val)
937#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE)
938#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val)
939#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA)
940#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val)
941#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
942#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val)
943#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET)
944#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val)
945#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
946#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val)
947#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB)
948#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val)
949#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
950#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val)
951#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET)
952#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val)
953#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
954#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val)
955#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR)
956#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val)
957#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR)
958#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val)
959#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE)
960#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val)
961#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH)
962#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val)
963#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN)
964#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val)
965
966
967/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
968#define bfin_read_PORTHIO() bfin_read16(PORTHIO)
969#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val)
970#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR)
971#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val)
972#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET)
973#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val)
974#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE)
975#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val)
976#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA)
977#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val)
978#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
979#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val)
980#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET)
981#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val)
982#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
983#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val)
984#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB)
985#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val)
986#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
987#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val)
988#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET)
989#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val)
990#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
991#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val)
992#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR)
993#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val)
994#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR)
995#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val)
996#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE)
997#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val)
998#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH)
999#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val)
1000#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN)
1001#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val)
1002
1003
1004/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
1005#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
1006#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
1007#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
1008#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
1009#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
1010#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
1011#define bfin_read_UART1_IER() bfin_read16(UART1_IER)
1012#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val)
1013#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
1014#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
1015#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR)
1016#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val)
1017#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
1018#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
1019#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
1020#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
1021#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
1022#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
1023#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
1024#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
1025#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
1026#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
1027#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
1028#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
1029
1030/* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF51x processor) */
1031
1032/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
1033#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
1034#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
1035#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
1036#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
1037#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
1038#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
1039#define bfin_read_PORT_MUX() bfin_read16(PORT_MUX)
1040#define bfin_write_PORT_MUX(val) bfin_write16(PORT_MUX, val)
1041
1042
1043/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
1044#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
1045#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
1046#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
1047#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
1048#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
1049#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
1050#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
1051#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
1052#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
1053#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
1054#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
1055#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
1056#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
1057#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
1058
1059#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
1060#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
1061#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
1062#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
1063#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
1064#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
1065#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
1066#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
1067#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
1068#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
1069#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
1070#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
1071#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
1072#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
1073
1074/* ==== end from cdefBF534.h ==== */
1075
1076/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
1077
1078#define bfin_read_PORTF_MUX() bfin_read16(PORTF_MUX)
1079#define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val)
1080#define bfin_read_PORTG_MUX() bfin_read16(PORTG_MUX)
1081#define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val)
1082#define bfin_read_PORTH_MUX() bfin_read16(PORTH_MUX)
1083#define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val)
1084
1085#define bfin_read_PORTF_DRIVE() bfin_read16(PORTF_DRIVE)
1086#define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val)
1087#define bfin_read_PORTG_DRIVE() bfin_read16(PORTG_DRIVE)
1088#define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val)
1089#define bfin_read_PORTH_DRIVE() bfin_read16(PORTH_DRIVE)
1090#define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val)
1091#define bfin_read_PORTF_SLEW() bfin_read16(PORTF_SLEW)
1092#define bfin_write_PORTF_SLEW(val) bfin_write16(PORTF_SLEW, val)
1093#define bfin_read_PORTG_SLEW() bfin_read16(PORTG_SLEW)
1094#define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val)
1095#define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW)
1096#define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val)
1097#define bfin_read_PORTF_HYSTERISIS() bfin_read16(PORTF_HYSTERISIS)
1098#define bfin_write_PORTF_HYSTERISIS(val) bfin_write16(PORTF_HYSTERISIS, val)
1099#define bfin_read_PORTG_HYSTERISIS() bfin_read16(PORTG_HYSTERISIS)
1100#define bfin_write_PORTG_HYSTERISIS(val) bfin_write16(PORTG_HYSTERISIS, val)
1101#define bfin_read_PORTH_HYSTERISIS() bfin_read16(PORTH_HYSTERISIS)
1102#define bfin_write_PORTH_HYSTERISIS(val) bfin_write16(PORTH_HYSTERISIS, val)
1103#define bfin_read_MISCPORT_DRIVE() bfin_read16(MISCPORT_DRIVE)
1104#define bfin_write_MISCPORT_DRIVE(val) bfin_write16(MISCPORT_DRIVE, val)
1105#define bfin_read_MISCPORT_SLEW() bfin_read16(MISCPORT_SLEW)
1106#define bfin_write_MISCPORT_SLEW(val) bfin_write16(MISCPORT_SLEW, val)
1107#define bfin_read_MISCPORT_HYSTERISIS() bfin_read16(MISCPORT_HYSTERISIS)
1108#define bfin_write_MISCPORT_HYSTERISIS(val) bfin_write16(MISCPORT_HYSTERISIS, val)
1109
1110/* HOST Port Registers */
1111
1112#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
1113#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
1114#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
1115#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
1116#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
1117#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
1118
1119/* Counter Registers */
1120
1121#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG)
1122#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
1123#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK)
1124#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
1125#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS)
1126#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
1127#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND)
1128#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
1129#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE)
1130#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
1131#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER)
1132#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
1133#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX)
1134#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
1135#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
1136#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
1137
1138/* OTP/FUSE Registers */
1139
1140#define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL)
1141#define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val)
1142#define bfin_read_OTP_BEN() bfin_read16(OTP_BEN)
1143#define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val)
1144#define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS)
1145#define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val)
1146#define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING)
1147#define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val)
1148
1149/* Security Registers */
1150
1151#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
1152#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val)
1153#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL)
1154#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
1155#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS)
1156#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
1157
1158/* OTP Read/Write Data Buffer Registers */
1159
1160#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0)
1161#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val)
1162#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1)
1163#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val)
1164#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2)
1165#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val)
1166#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3)
1167#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val)
1168
1169/* NFC Registers */
1170
1171#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL)
1172#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val)
1173#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT)
1174#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val)
1175#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT)
1176#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val)
1177#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK)
1178#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val)
1179#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0)
1180#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val)
1181#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1)
1182#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val)
1183#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2)
1184#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val)
1185#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3)
1186#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val)
1187#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT)
1188#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val)
1189#define bfin_read_NFC_RST() bfin_read16(NFC_RST)
1190#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val)
1191#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL)
1192#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val)
1193#define bfin_read_NFC_READ() bfin_read16(NFC_READ)
1194#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val)
1195#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR)
1196#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val)
1197#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD)
1198#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val)
1199#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR)
1200#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val)
1201#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD)
1202#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val)
1203
1204#endif /* _CDEF_BF52X_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF512.h b/arch/blackfin/mach-bf518/include/mach/defBF512.h
new file mode 100644
index 000000000000..a96ca90154dd
--- /dev/null
+++ b/arch/blackfin/mach-bf518/include/mach/defBF512.h
@@ -0,0 +1,42 @@
1/*
2 * File: include/asm-blackfin/mach-bf518/defBF512.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _DEF_BF512_H
32#define _DEF_BF512_H
33
34/* Include all Core registers and bit definitions */
35#include <asm/def_LPBlackfin.h>
36
37/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF512 */
38
39/* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
40#include "defBF51x_base.h"
41
42#endif /* _DEF_BF512_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF514.h b/arch/blackfin/mach-bf518/include/mach/defBF514.h
new file mode 100644
index 000000000000..543f2913b3f5
--- /dev/null
+++ b/arch/blackfin/mach-bf518/include/mach/defBF514.h
@@ -0,0 +1,113 @@
1/*
2 * File: include/asm-blackfin/mach-bf518/defBF514.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _DEF_BF514_H
32#define _DEF_BF514_H
33
34/* Include all Core registers and bit definitions */
35#include <asm/def_LPBlackfin.h>
36
37/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF514 */
38
39/* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
40#include "defBF51x_base.h"
41
42/* The following are the #defines needed by ADSP-BF514 that are not in the common header */
43
44/* SDH Registers */
45
46#define SDH_PWR_CTL 0xFFC03900 /* SDH Power Control */
47#define SDH_CLK_CTL 0xFFC03904 /* SDH Clock Control */
48#define SDH_ARGUMENT 0xFFC03908 /* SDH Argument */
49#define SDH_COMMAND 0xFFC0390C /* SDH Command */
50#define SDH_RESP_CMD 0xFFC03910 /* SDH Response Command */
51#define SDH_RESPONSE0 0xFFC03914 /* SDH Response0 */
52#define SDH_RESPONSE1 0xFFC03918 /* SDH Response1 */
53#define SDH_RESPONSE2 0xFFC0391C /* SDH Response2 */
54#define SDH_RESPONSE3 0xFFC03920 /* SDH Response3 */
55#define SDH_DATA_TIMER 0xFFC03924 /* SDH Data Timer */
56#define SDH_DATA_LGTH 0xFFC03928 /* SDH Data Length */
57#define SDH_DATA_CTL 0xFFC0392C /* SDH Data Control */
58#define SDH_DATA_CNT 0xFFC03930 /* SDH Data Counter */
59#define SDH_STATUS 0xFFC03934 /* SDH Status */
60#define SDH_STATUS_CLR 0xFFC03938 /* SDH Status Clear */
61#define SDH_MASK0 0xFFC0393C /* SDH Interrupt0 Mask */
62#define SDH_MASK1 0xFFC03940 /* SDH Interrupt1 Mask */
63#define SDH_FIFO_CNT 0xFFC03948 /* SDH FIFO Counter */
64#define SDH_FIFO 0xFFC03980 /* SDH Data FIFO */
65#define SDH_E_STATUS 0xFFC039C0 /* SDH Exception Status */
66#define SDH_E_MASK 0xFFC039C4 /* SDH Exception Mask */
67#define SDH_CFG 0xFFC039C8 /* SDH Configuration */
68#define SDH_RD_WAIT_EN 0xFFC039CC /* SDH Read Wait Enable */
69#define SDH_PID0 0xFFC039D0 /* SDH Peripheral Identification0 */
70#define SDH_PID1 0xFFC039D4 /* SDH Peripheral Identification1 */
71#define SDH_PID2 0xFFC039D8 /* SDH Peripheral Identification2 */
72#define SDH_PID3 0xFFC039DC /* SDH Peripheral Identification3 */
73#define SDH_PID4 0xFFC039E0 /* SDH Peripheral Identification4 */
74#define SDH_PID5 0xFFC039E4 /* SDH Peripheral Identification5 */
75#define SDH_PID6 0xFFC039E8 /* SDH Peripheral Identification6 */
76#define SDH_PID7 0xFFC039EC /* SDH Peripheral Identification7 */
77
78/* Removable Storage Interface Registers */
79
80#define RSI_PWR_CONTROL 0xFFC03800 /* RSI Power Control Register */
81#define RSI_CLK_CONTROL 0xFFC03804 /* RSI Clock Control Register */
82#define RSI_ARGUMENT 0xFFC03808 /* RSI Argument Register */
83#define RSI_COMMAND 0xFFC0380C /* RSI Command Register */
84#define RSI_RESP_CMD 0xFFC03810 /* RSI Response Command Register */
85#define RSI_RESPONSE0 0xFFC03814 /* RSI Response Register */
86#define RSI_RESPONSE1 0xFFC03818 /* RSI Response Register */
87#define RSI_RESPONSE2 0xFFC0381C /* RSI Response Register */
88#define RSI_RESPONSE3 0xFFC03820 /* RSI Response Register */
89#define RSI_DATA_TIMER 0xFFC03824 /* RSI Data Timer Register */
90#define RSI_DATA_LGTH 0xFFC03828 /* RSI Data Length Register */
91#define RSI_DATA_CONTROL 0xFFC0382C /* RSI Data Control Register */
92#define RSI_DATA_CNT 0xFFC03830 /* RSI Data Counter Register */
93#define RSI_STATUS 0xFFC03834 /* RSI Status Register */
94#define RSI_STATUSCL 0xFFC03838 /* RSI Status Clear Register */
95#define RSI_MASK0 0xFFC0383C /* RSI Interrupt 0 Mask Register */
96#define RSI_MASK1 0xFFC03840 /* RSI Interrupt 1 Mask Register */
97#define RSI_FIFO_CNT 0xFFC03848 /* RSI FIFO Counter Register */
98#define RSI_CEATA_CONTROL 0xFFC0384C /* RSI CEATA Register */
99#define RSI_FIFO 0xFFC03880 /* RSI Data FIFO Register */
100#define RSI_ESTAT 0xFFC038C0 /* RSI Exception Status Register */
101#define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */
102#define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */
103#define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */
104#define RSI_PID0 0xFFC03FE0 /* RSI Peripheral ID Register 0 */
105#define RSI_PID1 0xFFC03FE4 /* RSI Peripheral ID Register 1 */
106#define RSI_PID2 0xFFC03FE8 /* RSI Peripheral ID Register 2 */
107#define RSI_PID3 0xFFC03FEC /* RSI Peripheral ID Register 3 */
108#define RSI_PID4 0xFFC03FF0 /* RSI Peripheral ID Register 4 */
109#define RSI_PID5 0xFFC03FF4 /* RSI Peripheral ID Register 5 */
110#define RSI_PID6 0xFFC03FF8 /* RSI Peripheral ID Register 6 */
111#define RSI_PID7 0xFFC03FFC /* RSI Peripheral ID Register 7 */
112
113#endif /* _DEF_BF514_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF516.h b/arch/blackfin/mach-bf518/include/mach/defBF516.h
new file mode 100644
index 000000000000..149a269306c5
--- /dev/null
+++ b/arch/blackfin/mach-bf518/include/mach/defBF516.h
@@ -0,0 +1,490 @@
1/*
2 * File: include/asm-blackfin/mach-bf518/defBF516.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _DEF_BF516_H
32#define _DEF_BF516_H
33
34/* Include all Core registers and bit definitions */
35#include <asm/def_LPBlackfin.h>
36
37/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF516 */
38
39/* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
40#include "defBF51x_base.h"
41
42/* The following are the #defines needed by ADSP-BF516 that are not in the common header */
43/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
44
45#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
46#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
47#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
48#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
49#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
50#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
51#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
52#define EMAC_FLC 0xFFC0301C /* Flow Control Register */
53#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
54#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
55#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
56#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
57#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
58#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
59#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
60#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
61#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
62#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
63#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
64
65#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
66#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
67#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
68#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
69#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
70#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
71#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
72#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
73
74#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
75#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
76#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
77#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
78#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
79
80#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
81#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
82#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
83#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
84#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
85#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
86#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
87#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
88#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
89#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
90#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
91#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
92#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
93#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
94#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
95#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
96#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
97#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
98#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
99#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 < x < 128 */
100#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
101#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
102#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
103#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
104
105#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
106#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
107#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
108#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
109#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
110#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
111#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
112#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
113#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
114#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
115#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
116#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
117#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
118#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
119#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
120#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
121#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
122#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 < x < 128 */
123#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
124#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
125#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
126#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
127#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
128
129/* Listing for IEEE-Supported Count Registers */
130
131#define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */
132#define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */
133#define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */
134#define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */
135#define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */
136#define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */
137#define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */
138#define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */
139#define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */
140#define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */
141#define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */
142#define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */
143#define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */
144#define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */
145#define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */
146#define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */
147#define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */
148#define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */
149#define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */
150#define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 < x < 128 */
151#define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
152#define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
153#define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
154#define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */
155
156#define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */
157#define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */
158#define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */
159#define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */
160#define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */
161#define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */
162#define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */
163#define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */
164#define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */
165#define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */
166#define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */
167#define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */
168#define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */
169#define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */
170#define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */
171#define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */
172#define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */
173#define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 < x < 128 */
174#define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
175#define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */
176#define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
177#define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */
178#define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */
179
180/***********************************************************************************
181** System MMR Register Bits And Macros
182**
183** Disclaimer: All macros are intended to make C and Assembly code more readable.
184** Use these macros carefully, as any that do left shifts for field
185** depositing will result in the lower order bits being destroyed. Any
186** macro that shifts left to properly position the bit-field should be
187** used as part of an OR to initialize a register and NOT as a dynamic
188** modifier UNLESS the lower order bits are saved and ORed back in when
189** the macro is used.
190*************************************************************************************/
191
192/************************ ETHERNET 10/100 CONTROLLER MASKS ************************/
193
194/* EMAC_OPMODE Masks */
195
196#define RE 0x00000001 /* Receiver Enable */
197#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */
198#define HU 0x00000010 /* Hash Filter Unicast Address */
199#define HM 0x00000020 /* Hash Filter Multicast Address */
200#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */
201#define PR 0x00000080 /* Promiscuous Mode Enable */
202#define IFE 0x00000100 /* Inverse Filtering Enable */
203#define DBF 0x00000200 /* Disable Broadcast Frame Reception */
204#define PBF 0x00000400 /* Pass Bad Frames Enable */
205#define PSF 0x00000800 /* Pass Short Frames Enable */
206#define RAF 0x00001000 /* Receive-All Mode */
207#define TE 0x00010000 /* Transmitter Enable */
208#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */
209#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */
210#define DC 0x00080000 /* Deferral Check */
211#define BOLMT 0x00300000 /* Back-Off Limit */
212#define BOLMT_10 0x00000000 /* 10-bit range */
213#define BOLMT_8 0x00100000 /* 8-bit range */
214#define BOLMT_4 0x00200000 /* 4-bit range */
215#define BOLMT_1 0x00300000 /* 1-bit range */
216#define DRTY 0x00400000 /* Disable TX Retry On Collision */
217#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */
218#define RMII 0x01000000 /* RMII/MII* Mode */
219#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */
220#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */
221#define LB 0x08000000 /* Internal Loopback Enable */
222#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */
223
224/* EMAC_STAADD Masks */
225
226#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */
227#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */
228#define STADISPRE 0x00000004 /* Disable Preamble Generation */
229#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */
230#define REGAD 0x000007C0 /* STA Register Address */
231#define PHYAD 0x0000F800 /* PHY Device Address */
232
233#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */
234#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */
235
236/* EMAC_STADAT Mask */
237
238#define STADATA 0x0000FFFF /* Station Management Data */
239
240/* EMAC_FLC Masks */
241
242#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
243#define FLCE 0x00000002 /* Flow Control Enable */
244#define PCF 0x00000004 /* Pass Control Frames */
245#define BKPRSEN 0x00000008 /* Enable Backpressure */
246#define FLCPAUSE 0xFFFF0000 /* Pause Time */
247
248#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */
249
250/* EMAC_WKUP_CTL Masks */
251
252#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */
253#define MPKE 0x00000002 /* Magic Packet Enable */
254#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */
255#define GUWKE 0x00000008 /* Global Unicast Wake Enable */
256#define MPKS 0x00000020 /* Magic Packet Received Status */
257#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */
258
259/* EMAC_WKUP_FFCMD Masks */
260
261#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */
262#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
263#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */
264#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
265#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */
266#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
267#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */
268#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
269
270/* EMAC_WKUP_FFOFF Masks */
271
272#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */
273#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */
274#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */
275#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */
276
277#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
278#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
279#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
280#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
281/* Set ALL Offsets */
282#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
283
284/* EMAC_WKUP_FFCRC0 Masks */
285
286#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */
287#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */
288
289#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */
290#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */
291
292/* EMAC_WKUP_FFCRC1 Masks */
293
294#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */
295#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */
296
297#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */
298#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */
299
300/* EMAC_SYSCTL Masks */
301
302#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
303#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
304#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
305#define TXDWA 0x00000010 /* Transmit Frame DMA Word Alignment (Odd/Even*) */
306#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
307
308#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */
309
310/* EMAC_SYSTAT Masks */
311
312#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */
313#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */
314#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */
315#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */
316#define WAKEDET 0x00000010 /* Wake-Up Detected Status */
317#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */
318#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */
319#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */
320
321/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
322
323#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */
324#define RX_COMP 0x00001000 /* RX Frame Complete */
325#define RX_OK 0x00002000 /* RX Frame Received With No Errors */
326#define RX_LONG 0x00004000 /* RX Frame Too Long Error */
327#define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */
328#define RX_CRC 0x00010000 /* RX Frame CRC Error */
329#define RX_LEN 0x00020000 /* RX Frame Length Error */
330#define RX_FRAG 0x00040000 /* RX Frame Fragment Error */
331#define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */
332#define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */
333#define RX_PHY 0x00200000 /* RX Frame PHY Error */
334#define RX_LATE 0x00400000 /* RX Frame Late Collision Error */
335#define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */
336#define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */
337#define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */
338#define RX_CTL 0x04000000 /* RX Control Frame Indicator */
339#define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */
340#define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */
341#define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */
342#define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */
343#define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */
344
345/* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */
346
347#define TX_COMP 0x00000001 /* TX Frame Complete */
348#define TX_OK 0x00000002 /* TX Frame Sent With No Errors */
349#define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */
350#define TX_LATE 0x00000008 /* TX Frame Late Collision Error */
351#define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */
352#define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */
353#define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */
354#define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */
355#define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */
356#define TX_CCNT 0x00000F00 /* TX Frame Collision Count */
357#define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */
358#define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */
359#define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */
360#define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */
361#define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */
362
363/* EMAC_MMC_CTL Masks */
364#define RSTC 0x00000001 /* Reset All Counters */
365#define CROLL 0x00000002 /* Counter Roll-Over Enable */
366#define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */
367#define MMCE 0x00000008 /* Enable MMC Counter Operation */
368
369/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
370#define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */
371#define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */
372#define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */
373#define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */
374#define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */
375#define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */
376#define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */
377#define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */
378#define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */
379#define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */
380#define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */
381#define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */
382#define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */
383#define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */
384#define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */
385#define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */
386#define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */
387#define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */
388#define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */
389#define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */
390#define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */
391#define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */
392#define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */
393#define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */
394
395/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
396
397#define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */
398#define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */
399#define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */
400#define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */
401#define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */
402#define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */
403#define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */
404#define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */
405#define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */
406#define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */
407#define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */
408#define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */
409#define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */
410#define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */
411#define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */
412#define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */
413#define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */
414#define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */
415#define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */
416#define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */
417#define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */
418#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */
419#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */
420
421/* SDH Registers */
422
423#define SDH_PWR_CTL 0xFFC03900 /* SDH Power Control */
424#define SDH_CLK_CTL 0xFFC03904 /* SDH Clock Control */
425#define SDH_ARGUMENT 0xFFC03908 /* SDH Argument */
426#define SDH_COMMAND 0xFFC0390C /* SDH Command */
427#define SDH_RESP_CMD 0xFFC03910 /* SDH Response Command */
428#define SDH_RESPONSE0 0xFFC03914 /* SDH Response0 */
429#define SDH_RESPONSE1 0xFFC03918 /* SDH Response1 */
430#define SDH_RESPONSE2 0xFFC0391C /* SDH Response2 */
431#define SDH_RESPONSE3 0xFFC03920 /* SDH Response3 */
432#define SDH_DATA_TIMER 0xFFC03924 /* SDH Data Timer */
433#define SDH_DATA_LGTH 0xFFC03928 /* SDH Data Length */
434#define SDH_DATA_CTL 0xFFC0392C /* SDH Data Control */
435#define SDH_DATA_CNT 0xFFC03930 /* SDH Data Counter */
436#define SDH_STATUS 0xFFC03934 /* SDH Status */
437#define SDH_STATUS_CLR 0xFFC03938 /* SDH Status Clear */
438#define SDH_MASK0 0xFFC0393C /* SDH Interrupt0 Mask */
439#define SDH_MASK1 0xFFC03940 /* SDH Interrupt1 Mask */
440#define SDH_FIFO_CNT 0xFFC03948 /* SDH FIFO Counter */
441#define SDH_FIFO 0xFFC03980 /* SDH Data FIFO */
442#define SDH_E_STATUS 0xFFC039C0 /* SDH Exception Status */
443#define SDH_E_MASK 0xFFC039C4 /* SDH Exception Mask */
444#define SDH_CFG 0xFFC039C8 /* SDH Configuration */
445#define SDH_RD_WAIT_EN 0xFFC039CC /* SDH Read Wait Enable */
446#define SDH_PID0 0xFFC039D0 /* SDH Peripheral Identification0 */
447#define SDH_PID1 0xFFC039D4 /* SDH Peripheral Identification1 */
448#define SDH_PID2 0xFFC039D8 /* SDH Peripheral Identification2 */
449#define SDH_PID3 0xFFC039DC /* SDH Peripheral Identification3 */
450#define SDH_PID4 0xFFC039E0 /* SDH Peripheral Identification4 */
451#define SDH_PID5 0xFFC039E4 /* SDH Peripheral Identification5 */
452#define SDH_PID6 0xFFC039E8 /* SDH Peripheral Identification6 */
453#define SDH_PID7 0xFFC039EC /* SDH Peripheral Identification7 */
454
455/* Removable Storage Interface Registers */
456
457#define RSI_PWR_CONTROL 0xFFC03800 /* RSI Power Control Register */
458#define RSI_CLK_CONTROL 0xFFC03804 /* RSI Clock Control Register */
459#define RSI_ARGUMENT 0xFFC03808 /* RSI Argument Register */
460#define RSI_COMMAND 0xFFC0380C /* RSI Command Register */
461#define RSI_RESP_CMD 0xFFC03810 /* RSI Response Command Register */
462#define RSI_RESPONSE0 0xFFC03814 /* RSI Response Register */
463#define RSI_RESPONSE1 0xFFC03818 /* RSI Response Register */
464#define RSI_RESPONSE2 0xFFC0381C /* RSI Response Register */
465#define RSI_RESPONSE3 0xFFC03820 /* RSI Response Register */
466#define RSI_DATA_TIMER 0xFFC03824 /* RSI Data Timer Register */
467#define RSI_DATA_LGTH 0xFFC03828 /* RSI Data Length Register */
468#define RSI_DATA_CONTROL 0xFFC0382C /* RSI Data Control Register */
469#define RSI_DATA_CNT 0xFFC03830 /* RSI Data Counter Register */
470#define RSI_STATUS 0xFFC03834 /* RSI Status Register */
471#define RSI_STATUSCL 0xFFC03838 /* RSI Status Clear Register */
472#define RSI_MASK0 0xFFC0383C /* RSI Interrupt 0 Mask Register */
473#define RSI_MASK1 0xFFC03840 /* RSI Interrupt 1 Mask Register */
474#define RSI_FIFO_CNT 0xFFC03848 /* RSI FIFO Counter Register */
475#define RSI_CEATA_CONTROL 0xFFC0384C /* RSI CEATA Register */
476#define RSI_FIFO 0xFFC03880 /* RSI Data FIFO Register */
477#define RSI_ESTAT 0xFFC038C0 /* RSI Exception Status Register */
478#define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */
479#define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */
480#define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */
481#define RSI_PID0 0xFFC03FE0 /* RSI Peripheral ID Register 0 */
482#define RSI_PID1 0xFFC03FE4 /* RSI Peripheral ID Register 1 */
483#define RSI_PID2 0xFFC03FE8 /* RSI Peripheral ID Register 2 */
484#define RSI_PID3 0xFFC03FEC /* RSI Peripheral ID Register 3 */
485#define RSI_PID4 0xFFC03FF0 /* RSI Peripheral ID Register 4 */
486#define RSI_PID5 0xFFC03FF4 /* RSI Peripheral ID Register 5 */
487#define RSI_PID6 0xFFC03FF8 /* RSI Peripheral ID Register 6 */
488#define RSI_PID7 0xFFC03FFC /* RSI Peripheral ID Register 7 */
489
490#endif /* _DEF_BF516_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF518.h b/arch/blackfin/mach-bf518/include/mach/defBF518.h
new file mode 100644
index 000000000000..4eaade15dd76
--- /dev/null
+++ b/arch/blackfin/mach-bf518/include/mach/defBF518.h
@@ -0,0 +1,516 @@
1/*
2 * File: include/asm-blackfin/mach-bf518/defBF518.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _DEF_BF518_H
32#define _DEF_BF518_H
33
34/* Include all Core registers and bit definitions */
35#include <asm/def_LPBlackfin.h>
36
37/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF518 */
38
39/* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
40#include "defBF51x_base.h"
41
42/* The following are the #defines needed by ADSP-BF518 that are not in the common header */
43/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
44
45#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
46#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
47#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
48#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
49#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
50#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
51#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
52#define EMAC_FLC 0xFFC0301C /* Flow Control Register */
53#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
54#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
55#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
56#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
57#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
58#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
59#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
60#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
61#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
62#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
63#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
64
65#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
66#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
67#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
68#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
69#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
70#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
71#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
72#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
73
74#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
75#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
76#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
77#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
78#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
79
80#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
81#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
82#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
83#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
84#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
85#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
86#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
87#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
88#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
89#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
90#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
91#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
92#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
93#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
94#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
95#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
96#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
97#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
98#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
99#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 < x < 128 */
100#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
101#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
102#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
103#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
104
105#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
106#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
107#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
108#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
109#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
110#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
111#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
112#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
113#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
114#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
115#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
116#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
117#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
118#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
119#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
120#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
121#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
122#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 < x < 128 */
123#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
124#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
125#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
126#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
127#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
128
129/* Listing for IEEE-Supported Count Registers */
130
131#define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */
132#define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */
133#define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */
134#define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */
135#define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */
136#define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */
137#define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */
138#define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */
139#define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */
140#define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */
141#define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */
142#define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */
143#define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */
144#define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */
145#define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */
146#define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */
147#define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */
148#define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */
149#define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */
150#define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 < x < 128 */
151#define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
152#define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
153#define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
154#define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */
155
156#define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */
157#define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */
158#define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */
159#define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */
160#define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */
161#define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */
162#define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */
163#define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */
164#define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */
165#define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */
166#define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */
167#define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */
168#define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */
169#define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */
170#define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */
171#define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */
172#define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */
173#define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 < x < 128 */
174#define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
175#define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */
176#define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
177#define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */
178#define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */
179
180/***********************************************************************************
181** System MMR Register Bits And Macros
182**
183** Disclaimer: All macros are intended to make C and Assembly code more readable.
184** Use these macros carefully, as any that do left shifts for field
185** depositing will result in the lower order bits being destroyed. Any
186** macro that shifts left to properly position the bit-field should be
187** used as part of an OR to initialize a register and NOT as a dynamic
188** modifier UNLESS the lower order bits are saved and ORed back in when
189** the macro is used.
190*************************************************************************************/
191
192/************************ ETHERNET 10/100 CONTROLLER MASKS ************************/
193
194/* EMAC_OPMODE Masks */
195
196#define RE 0x00000001 /* Receiver Enable */
197#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */
198#define HU 0x00000010 /* Hash Filter Unicast Address */
199#define HM 0x00000020 /* Hash Filter Multicast Address */
200#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */
201#define PR 0x00000080 /* Promiscuous Mode Enable */
202#define IFE 0x00000100 /* Inverse Filtering Enable */
203#define DBF 0x00000200 /* Disable Broadcast Frame Reception */
204#define PBF 0x00000400 /* Pass Bad Frames Enable */
205#define PSF 0x00000800 /* Pass Short Frames Enable */
206#define RAF 0x00001000 /* Receive-All Mode */
207#define TE 0x00010000 /* Transmitter Enable */
208#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */
209#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */
210#define DC 0x00080000 /* Deferral Check */
211#define BOLMT 0x00300000 /* Back-Off Limit */
212#define BOLMT_10 0x00000000 /* 10-bit range */
213#define BOLMT_8 0x00100000 /* 8-bit range */
214#define BOLMT_4 0x00200000 /* 4-bit range */
215#define BOLMT_1 0x00300000 /* 1-bit range */
216#define DRTY 0x00400000 /* Disable TX Retry On Collision */
217#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */
218#define RMII 0x01000000 /* RMII/MII* Mode */
219#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */
220#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */
221#define LB 0x08000000 /* Internal Loopback Enable */
222#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */
223
224/* EMAC_STAADD Masks */
225
226#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */
227#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */
228#define STADISPRE 0x00000004 /* Disable Preamble Generation */
229#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */
230#define REGAD 0x000007C0 /* STA Register Address */
231#define PHYAD 0x0000F800 /* PHY Device Address */
232
233#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */
234#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */
235
236/* EMAC_STADAT Mask */
237
238#define STADATA 0x0000FFFF /* Station Management Data */
239
240/* EMAC_FLC Masks */
241
242#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
243#define FLCE 0x00000002 /* Flow Control Enable */
244#define PCF 0x00000004 /* Pass Control Frames */
245#define BKPRSEN 0x00000008 /* Enable Backpressure */
246#define FLCPAUSE 0xFFFF0000 /* Pause Time */
247
248#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */
249
250/* EMAC_WKUP_CTL Masks */
251
252#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */
253#define MPKE 0x00000002 /* Magic Packet Enable */
254#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */
255#define GUWKE 0x00000008 /* Global Unicast Wake Enable */
256#define MPKS 0x00000020 /* Magic Packet Received Status */
257#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */
258
259/* EMAC_WKUP_FFCMD Masks */
260
261#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */
262#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
263#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */
264#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
265#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */
266#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
267#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */
268#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
269
270/* EMAC_WKUP_FFOFF Masks */
271
272#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */
273#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */
274#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */
275#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */
276
277#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
278#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
279#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
280#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
281/* Set ALL Offsets */
282#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
283
284/* EMAC_WKUP_FFCRC0 Masks */
285
286#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */
287#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */
288
289#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */
290#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */
291
292/* EMAC_WKUP_FFCRC1 Masks */
293
294#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */
295#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */
296
297#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */
298#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */
299
300/* EMAC_SYSCTL Masks */
301
302#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
303#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
304#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
305#define TXDWA 0x00000010 /* Transmit Frame DMA Word Alignment (Odd/Even*) */
306#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
307
308#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */
309
310/* EMAC_SYSTAT Masks */
311
312#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */
313#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */
314#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */
315#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */
316#define WAKEDET 0x00000010 /* Wake-Up Detected Status */
317#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */
318#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */
319#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */
320
321/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
322
323#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */
324#define RX_COMP 0x00001000 /* RX Frame Complete */
325#define RX_OK 0x00002000 /* RX Frame Received With No Errors */
326#define RX_LONG 0x00004000 /* RX Frame Too Long Error */
327#define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */
328#define RX_CRC 0x00010000 /* RX Frame CRC Error */
329#define RX_LEN 0x00020000 /* RX Frame Length Error */
330#define RX_FRAG 0x00040000 /* RX Frame Fragment Error */
331#define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */
332#define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */
333#define RX_PHY 0x00200000 /* RX Frame PHY Error */
334#define RX_LATE 0x00400000 /* RX Frame Late Collision Error */
335#define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */
336#define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */
337#define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */
338#define RX_CTL 0x04000000 /* RX Control Frame Indicator */
339#define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */
340#define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */
341#define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */
342#define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */
343#define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */
344
345/* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */
346
347#define TX_COMP 0x00000001 /* TX Frame Complete */
348#define TX_OK 0x00000002 /* TX Frame Sent With No Errors */
349#define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */
350#define TX_LATE 0x00000008 /* TX Frame Late Collision Error */
351#define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */
352#define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */
353#define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */
354#define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */
355#define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */
356#define TX_CCNT 0x00000F00 /* TX Frame Collision Count */
357#define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */
358#define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */
359#define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */
360#define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */
361#define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */
362
363/* EMAC_MMC_CTL Masks */
364#define RSTC 0x00000001 /* Reset All Counters */
365#define CROLL 0x00000002 /* Counter Roll-Over Enable */
366#define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */
367#define MMCE 0x00000008 /* Enable MMC Counter Operation */
368
369/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
370#define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */
371#define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */
372#define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */
373#define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */
374#define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */
375#define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */
376#define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */
377#define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */
378#define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */
379#define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */
380#define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */
381#define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */
382#define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */
383#define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */
384#define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */
385#define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */
386#define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */
387#define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */
388#define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */
389#define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */
390#define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */
391#define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */
392#define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */
393#define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */
394
395/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
396
397#define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */
398#define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */
399#define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */
400#define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */
401#define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */
402#define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */
403#define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */
404#define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */
405#define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */
406#define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */
407#define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */
408#define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */
409#define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */
410#define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */
411#define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */
412#define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */
413#define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */
414#define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */
415#define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */
416#define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */
417#define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */
418#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */
419#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */
420
421/* SDH Registers */
422
423#define SDH_PWR_CTL 0xFFC03900 /* SDH Power Control */
424#define SDH_CLK_CTL 0xFFC03904 /* SDH Clock Control */
425#define SDH_ARGUMENT 0xFFC03908 /* SDH Argument */
426#define SDH_COMMAND 0xFFC0390C /* SDH Command */
427#define SDH_RESP_CMD 0xFFC03910 /* SDH Response Command */
428#define SDH_RESPONSE0 0xFFC03914 /* SDH Response0 */
429#define SDH_RESPONSE1 0xFFC03918 /* SDH Response1 */
430#define SDH_RESPONSE2 0xFFC0391C /* SDH Response2 */
431#define SDH_RESPONSE3 0xFFC03920 /* SDH Response3 */
432#define SDH_DATA_TIMER 0xFFC03924 /* SDH Data Timer */
433#define SDH_DATA_LGTH 0xFFC03928 /* SDH Data Length */
434#define SDH_DATA_CTL 0xFFC0392C /* SDH Data Control */
435#define SDH_DATA_CNT 0xFFC03930 /* SDH Data Counter */
436#define SDH_STATUS 0xFFC03934 /* SDH Status */
437#define SDH_STATUS_CLR 0xFFC03938 /* SDH Status Clear */
438#define SDH_MASK0 0xFFC0393C /* SDH Interrupt0 Mask */
439#define SDH_MASK1 0xFFC03940 /* SDH Interrupt1 Mask */
440#define SDH_FIFO_CNT 0xFFC03948 /* SDH FIFO Counter */
441#define SDH_FIFO 0xFFC03980 /* SDH Data FIFO */
442#define SDH_E_STATUS 0xFFC039C0 /* SDH Exception Status */
443#define SDH_E_MASK 0xFFC039C4 /* SDH Exception Mask */
444#define SDH_CFG 0xFFC039C8 /* SDH Configuration */
445#define SDH_RD_WAIT_EN 0xFFC039CC /* SDH Read Wait Enable */
446#define SDH_PID0 0xFFC039D0 /* SDH Peripheral Identification0 */
447#define SDH_PID1 0xFFC039D4 /* SDH Peripheral Identification1 */
448#define SDH_PID2 0xFFC039D8 /* SDH Peripheral Identification2 */
449#define SDH_PID3 0xFFC039DC /* SDH Peripheral Identification3 */
450#define SDH_PID4 0xFFC039E0 /* SDH Peripheral Identification4 */
451#define SDH_PID5 0xFFC039E4 /* SDH Peripheral Identification5 */
452#define SDH_PID6 0xFFC039E8 /* SDH Peripheral Identification6 */
453#define SDH_PID7 0xFFC039EC /* SDH Peripheral Identification7 */
454
455/* Removable Storage Interface Registers */
456
457#define RSI_PWR_CONTROL 0xFFC03800 /* RSI Power Control Register */
458#define RSI_CLK_CONTROL 0xFFC03804 /* RSI Clock Control Register */
459#define RSI_ARGUMENT 0xFFC03808 /* RSI Argument Register */
460#define RSI_COMMAND 0xFFC0380C /* RSI Command Register */
461#define RSI_RESP_CMD 0xFFC03810 /* RSI Response Command Register */
462#define RSI_RESPONSE0 0xFFC03814 /* RSI Response Register */
463#define RSI_RESPONSE1 0xFFC03818 /* RSI Response Register */
464#define RSI_RESPONSE2 0xFFC0381C /* RSI Response Register */
465#define RSI_RESPONSE3 0xFFC03820 /* RSI Response Register */
466#define RSI_DATA_TIMER 0xFFC03824 /* RSI Data Timer Register */
467#define RSI_DATA_LGTH 0xFFC03828 /* RSI Data Length Register */
468#define RSI_DATA_CONTROL 0xFFC0382C /* RSI Data Control Register */
469#define RSI_DATA_CNT 0xFFC03830 /* RSI Data Counter Register */
470#define RSI_STATUS 0xFFC03834 /* RSI Status Register */
471#define RSI_STATUSCL 0xFFC03838 /* RSI Status Clear Register */
472#define RSI_MASK0 0xFFC0383C /* RSI Interrupt 0 Mask Register */
473#define RSI_MASK1 0xFFC03840 /* RSI Interrupt 1 Mask Register */
474#define RSI_FIFO_CNT 0xFFC03848 /* RSI FIFO Counter Register */
475#define RSI_CEATA_CONTROL 0xFFC0384C /* RSI CEATA Register */
476#define RSI_FIFO 0xFFC03880 /* RSI Data FIFO Register */
477#define RSI_ESTAT 0xFFC038C0 /* RSI Exception Status Register */
478#define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */
479#define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */
480#define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */
481#define RSI_PID0 0xFFC03FE0 /* RSI Peripheral ID Register 0 */
482#define RSI_PID1 0xFFC03FE4 /* RSI Peripheral ID Register 1 */
483#define RSI_PID2 0xFFC03FE8 /* RSI Peripheral ID Register 2 */
484#define RSI_PID3 0xFFC03FEC /* RSI Peripheral ID Register 3 */
485#define RSI_PID4 0xFFC03FF0 /* RSI Peripheral ID Register 4 */
486#define RSI_PID5 0xFFC03FF4 /* RSI Peripheral ID Register 5 */
487#define RSI_PID6 0xFFC03FF8 /* RSI Peripheral ID Register 6 */
488#define RSI_PID7 0xFFC03FFC /* RSI Peripheral ID Register 7 */
489
490/* PTP TSYNC Registers */
491
492#define EMAC_PTP_CTL 0xFFC030A0 /* PTP Block Control */
493#define EMAC_PTP_IE 0xFFC030A4 /* PTP Block Interrupt Enable */
494#define EMAC_PTP_ISTAT 0xFFC030A8 /* PTP Block Interrupt Status */
495#define EMAC_PTP_FOFF 0xFFC030AC /* PTP Filter offset Register */
496#define EMAC_PTP_FV1 0xFFC030B0 /* PTP Filter Value Register 1 */
497#define EMAC_PTP_FV2 0xFFC030B4 /* PTP Filter Value Register 2 */
498#define EMAC_PTP_FV3 0xFFC030B8 /* PTP Filter Value Register 3 */
499#define EMAC_PTP_ADDEND 0xFFC030BC /* PTP Addend for Frequency Compensation */
500#define EMAC_PTP_ACCR 0xFFC030C0 /* PTP Accumulator for Frequency Compensation */
501#define EMAC_PTP_OFFSET 0xFFC030C4 /* PTP Time Offset Register */
502#define EMAC_PTP_TIMELO 0xFFC030C8 /* PTP Precision Clock Time Low */
503#define EMAC_PTP_TIMEHI 0xFFC030CC /* PTP Precision Clock Time High */
504#define EMAC_PTP_RXSNAPLO 0xFFC030D0 /* PTP Receive Snapshot Register Low */
505#define EMAC_PTP_RXSNAPHI 0xFFC030D4 /* PTP Receive Snapshot Register High */
506#define EMAC_PTP_TXSNAPLO 0xFFC030D8 /* PTP Transmit Snapshot Register Low */
507#define EMAC_PTP_TXSNAPHI 0xFFC030DC /* PTP Transmit Snapshot Register High */
508#define EMAC_PTP_ALARMLO 0xFFC030E0 /* PTP Alarm time Low */
509#define EMAC_PTP_ALARMHI 0xFFC030E4 /* PTP Alarm time High */
510#define EMAC_PTP_ID_OFF 0xFFC030E8 /* PTP Capture ID offset register */
511#define EMAC_PTP_ID_SNAP 0xFFC030EC /* PTP Capture ID register */
512#define EMAC_PTP_PPS_STARTLO 0xFFC030F0 /* PPS Start Time Low */
513#define EMAC_PTP_PPS_STARTHI 0xFFC030F4 /* PPS Start Time High */
514#define EMAC_PTP_PPS_PERIOD 0xFFC030F8 /* PPS Count Register */
515
516#endif /* _DEF_BF518_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
new file mode 100644
index 000000000000..1bec8d1c2a73
--- /dev/null
+++ b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
@@ -0,0 +1,1940 @@
1/*
2 * File: include/asm-blackfin/mach-bf518/defBF51x_base.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _DEF_BF51X_H
32#define _DEF_BF51X_H
33
34
35/* ************************************************************** */
36/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF51x */
37/* ************************************************************** */
38
39/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
40#define PLL_CTL 0xFFC00000 /* PLL Control Register */
41#define PLL_DIV 0xFFC00004 /* PLL Divide Register */
42#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
43#define PLL_STAT 0xFFC0000C /* PLL Status Register */
44#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
45#define CHIPID 0xFFC00014 /* Device ID Register */
46
47/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
48#define SWRST 0xFFC00100 /* Software Reset Register */
49#define SYSCR 0xFFC00104 /* System Configuration Register */
50#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
51
52#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */
53#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
54#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
55#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
56#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
57#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */
58#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */
59
60/* SIC Additions to ADSP-BF51x (0xFFC0014C - 0xFFC00162) */
61#define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */
62#define SIC_IAR4 0xFFC00150 /* Interrupt Assignment register4 */
63#define SIC_IAR5 0xFFC00154 /* Interrupt Assignment register5 */
64#define SIC_IAR6 0xFFC00158 /* Interrupt Assignment register6 */
65#define SIC_IAR7 0xFFC0015C /* Interrupt Assignment register7 */
66#define SIC_ISR1 0xFFC00160 /* Interrupt Statur register */
67#define SIC_IWR1 0xFFC00164 /* Interrupt Wakeup register */
68
69
70/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
71#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
72#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
73#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
74
75
76/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
77#define RTC_STAT 0xFFC00300 /* RTC Status Register */
78#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
79#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
80#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
81#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
82#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
83#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */
84
85
86/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
87#define UART0_THR 0xFFC00400 /* Transmit Holding register */
88#define UART0_RBR 0xFFC00400 /* Receive Buffer register */
89#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
90#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
91#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
92#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
93#define UART0_LCR 0xFFC0040C /* Line Control Register */
94#define UART0_MCR 0xFFC00410 /* Modem Control Register */
95#define UART0_LSR 0xFFC00414 /* Line Status Register */
96#define UART0_MSR 0xFFC00418 /* Modem Status Register */
97#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
98#define UART0_GCTL 0xFFC00424 /* Global Control Register */
99
100/* SPI0 Controller (0xFFC00500 - 0xFFC005FF) */
101#define SPI0_REGBASE 0xFFC00500
102#define SPI0_CTL 0xFFC00500 /* SPI Control Register */
103#define SPI0_FLG 0xFFC00504 /* SPI Flag register */
104#define SPI0_STAT 0xFFC00508 /* SPI Status register */
105#define SPI0_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
106#define SPI0_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
107#define SPI0_BAUD 0xFFC00514 /* SPI Baud rate Register */
108#define SPI0_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
109
110/* SPI1 Controller (0xFFC03400 - 0xFFC034FF) */
111#define SPI1_REGBASE 0xFFC03400
112#define SPI1_CTL 0xFFC03400 /* SPI Control Register */
113#define SPI1_FLG 0xFFC03404 /* SPI Flag register */
114#define SPI1_STAT 0xFFC03408 /* SPI Status register */
115#define SPI1_TDBR 0xFFC0340C /* SPI Transmit Data Buffer Register */
116#define SPI1_RDBR 0xFFC03410 /* SPI Receive Data Buffer Register */
117#define SPI1_BAUD 0xFFC03414 /* SPI Baud rate Register */
118#define SPI1_SHADOW 0xFFC03418 /* SPI_RDBR Shadow Register */
119
120/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
121#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
122#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
123#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
124#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
125
126#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
127#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
128#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
129#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
130
131#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
132#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
133#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
134#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
135
136#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */
137#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */
138#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */
139#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */
140
141#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */
142#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */
143#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */
144#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */
145
146#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */
147#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */
148#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */
149#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */
150
151#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */
152#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */
153#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */
154#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */
155
156#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */
157#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */
158#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */
159#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */
160
161#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */
162#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */
163#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */
164
165/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
166#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */
167#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
168#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
169#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */
170#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
171#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
172#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
173#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
174#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
175#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
176#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
177#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
178#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */
179#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */
180#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */
181#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
182#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */
183
184/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
185#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
186#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
187#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
188#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
189#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
190#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
191#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
192#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
193#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
194#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
195#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
196#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
197#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
198#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
199#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
200#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
201#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
202#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
203#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
204#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
205#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
206#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
207
208/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
209#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
210#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
211#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
212#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
213#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
214#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
215#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
216#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
217#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
218#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
219#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
220#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
221#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
222#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
223#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
224#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
225#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
226#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
227#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
228#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
229#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
230#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
231
232/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
233#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
234#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
235#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
236#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
237#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
238#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
239#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
240
241/* DMA Traffic Control Registers */
242#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
243#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
244
245/* Alternate deprecated register names (below) provided for backwards code compatibility */
246#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
247#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
248
249/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
250#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
251#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
252#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
253#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
254#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
255#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
256#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
257#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
258#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
259#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
260#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
261#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
262#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
263
264#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
265#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
266#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
267#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
268#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
269#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
270#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
271#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
272#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
273#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
274#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
275#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
276#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
277
278#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
279#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
280#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
281#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
282#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
283#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
284#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
285#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
286#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
287#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
288#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
289#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
290#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
291
292#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
293#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
294#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
295#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
296#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
297#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
298#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
299#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
300#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
301#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
302#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
303#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
304#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
305
306#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
307#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
308#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
309#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
310#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
311#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
312#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
313#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
314#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
315#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
316#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
317#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
318#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
319
320#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
321#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
322#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
323#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
324#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
325#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
326#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
327#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
328#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
329#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
330#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
331#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
332#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
333
334#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
335#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
336#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
337#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
338#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
339#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
340#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
341#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
342#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
343#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
344#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
345#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
346#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
347
348#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
349#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
350#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
351#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
352#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
353#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
354#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
355#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
356#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
357#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
358#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
359#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
360#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
361
362#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
363#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */
364#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */
365#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */
366#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */
367#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */
368#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */
369#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
370#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */
371#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
372#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
373#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */
374#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
375
376#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
377#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */
378#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */
379#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */
380#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */
381#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */
382#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */
383#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
384#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */
385#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
386#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
387#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */
388#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
389
390#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
391#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */
392#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */
393#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */
394#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */
395#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */
396#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
397#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
398#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */
399#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
400#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
401#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
402#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
403
404#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
405#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */
406#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */
407#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */
408#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
409#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */
410#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
411#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
412#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */
413#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
414#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
415#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
416#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
417
418#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
419#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
420#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
421#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
422#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
423#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
424#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
425#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
426#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
427#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
428#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
429#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
430#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
431
432#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
433#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
434#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
435#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
436#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
437#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
438#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
439#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
440#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
441#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
442#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
443#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
444#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
445
446#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
447#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
448#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
449#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
450#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
451#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
452#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
453#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
454#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
455#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
456#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
457#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
458#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
459
460#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
461#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
462#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
463#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
464#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
465#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
466#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
467#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
468#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
469#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
470#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
471#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
472#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
473
474
475/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
476#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
477#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
478#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
479#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
480#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
481
482
483/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
484#define TWI0_REGBASE 0xFFC01400
485#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
486#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */
487#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
488#define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
489#define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
490#define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
491#define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
492#define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
493#define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
494#define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
495#define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
496#define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
497#define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
498#define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
499#define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
500#define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
501
502
503/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
504#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */
505#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
506#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
507#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */
508#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
509#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
510#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
511#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
512#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
513#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
514#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
515#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
516#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */
517#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */
518#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */
519#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
520#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */
521
522
523/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
524#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */
525#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
526#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
527#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */
528#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
529#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
530#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
531#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
532#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
533#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
534#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
535#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
536#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */
537#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */
538#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */
539#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
540#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */
541
542
543/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
544#define UART1_THR 0xFFC02000 /* Transmit Holding register */
545#define UART1_RBR 0xFFC02000 /* Receive Buffer register */
546#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
547#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
548#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
549#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
550#define UART1_LCR 0xFFC0200C /* Line Control Register */
551#define UART1_MCR 0xFFC02010 /* Modem Control Register */
552#define UART1_LSR 0xFFC02014 /* Line Status Register */
553#define UART1_MSR 0xFFC02018 /* Modem Status Register */
554#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
555#define UART1_GCTL 0xFFC02024 /* Global Control Register */
556
557
558/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
559#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
560#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
561#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
562#define BFIN_PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */
563
564
565/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
566#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
567#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
568#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
569#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */
570#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
571#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
572#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
573
574#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
575#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
576#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
577#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */
578#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
579#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
580#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
581
582
583/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
584#define PORTF_MUX 0xFFC03210 /* Port F mux control */
585#define PORTG_MUX 0xFFC03214 /* Port G mux control */
586#define PORTH_MUX 0xFFC03218 /* Port H mux control */
587#define PORTF_DRIVE 0xFFC03220 /* Port F drive strength control */
588#define PORTG_DRIVE 0xFFC03224 /* Port G drive strength control */
589#define PORTH_DRIVE 0xFFC03228 /* Port H drive strength control */
590#define PORTF_SLEW 0xFFC03230 /* Port F slew control */
591#define PORTG_SLEW 0xFFC03234 /* Port G slew control */
592#define PORTH_SLEW 0xFFC03238 /* Port H slew control */
593#define PORTF_HYSTERISIS 0xFFC03240 /* Port F Schmitt trigger control */
594#define PORTG_HYSTERISIS 0xFFC03244 /* Port G Schmitt trigger control */
595#define PORTH_HYSTERISIS 0xFFC03248 /* Port H Schmitt trigger control */
596#define MISCPORT_DRIVE 0xFFC03280 /* Misc Port drive strength control */
597#define MISCPORT_SLEW 0xFFC03284 /* Misc Port slew control */
598#define MISCPORT_HYSTERISIS 0xFFC03288 /* Misc Port Schmitt trigger control */
599
600
601/***********************************************************************************
602** System MMR Register Bits And Macros
603**
604** Disclaimer: All macros are intended to make C and Assembly code more readable.
605** Use these macros carefully, as any that do left shifts for field
606** depositing will result in the lower order bits being destroyed. Any
607** macro that shifts left to properly position the bit-field should be
608** used as part of an OR to initialize a register and NOT as a dynamic
609** modifier UNLESS the lower order bits are saved and ORed back in when
610** the macro is used.
611*************************************************************************************/
612/*
613** ********************* PLL AND RESET MASKS ****************************************/
614/* PLL_CTL Masks */
615#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
616#define PLL_OFF 0x0002 /* PLL Not Powered */
617#define STOPCK 0x0008 /* Core Clock Off */
618#define PDWN 0x0020 /* Enter Deep Sleep Mode */
619#define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */
620#define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
621#define BYPASS 0x0100 /* Bypass the PLL */
622#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
623/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
624#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
625
626/* PLL_DIV Masks */
627#define SSEL 0x000F /* System Select */
628#define CSEL 0x0030 /* Core Select */
629#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
630#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
631#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
632#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
633/* PLL_DIV Macros */
634#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
635
636/* VR_CTL Masks */
637#define FREQ 0x3000 /* Switching Oscillator Frequency For Regulator */
638#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
639
640#define VLEV 0x00F0 /* Internal Voltage Level */
641#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
642#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
643#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
644#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
645#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
646#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
647#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
648#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
649#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
650#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
651
652#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
653#define USBWE 0x0200 /* Enable USB Wakeup From Hibernate */
654#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */
655#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */
656#define PHYCLKOE CLKBUFOE /* Alternative legacy name for the above */
657#define SCKELOW 0x8000 /* Enable Drive CKE Low During Reset */
658
659/* PLL_STAT Masks */
660#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
661#define FULL_ON 0x0002 /* Processor In Full On Mode */
662#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
663#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
664
665/* CHIPID Masks */
666#define CHIPID_VERSION 0xF0000000
667#define CHIPID_FAMILY 0x0FFFF000
668#define CHIPID_MANUFACTURE 0x00000FFE
669
670/* SWRST Masks */
671#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
672#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
673#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
674#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
675#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
676
677/* SYSCR Masks */
678#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */
679#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
680
681
682/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
683/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
684
685#if 0
686#define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */
687
688#define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */
689#define IRQ_ERROR2 0x00000004 /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */
690#define IRQ_RTC 0x00000008 /* Real Time Clock Interrupt */
691#define IRQ_DMA0 0x00000010 /* DMA Channel 0 (PPI) Interrupt */
692#define IRQ_DMA3 0x00000020 /* DMA Channel 3 (SPORT0 RX) Interrupt */
693#define IRQ_DMA4 0x00000040 /* DMA Channel 4 (SPORT0 TX) Interrupt */
694#define IRQ_DMA5 0x00000080 /* DMA Channel 5 (SPORT1 RX) Interrupt */
695
696#define IRQ_DMA6 0x00000100 /* DMA Channel 6 (SPORT1 TX) Interrupt */
697#define IRQ_TWI 0x00000200 /* TWI Interrupt */
698#define IRQ_DMA7 0x00000400 /* DMA Channel 7 (SPI) Interrupt */
699#define IRQ_DMA8 0x00000800 /* DMA Channel 8 (UART0 RX) Interrupt */
700#define IRQ_DMA9 0x00001000 /* DMA Channel 9 (UART0 TX) Interrupt */
701#define IRQ_DMA10 0x00002000 /* DMA Channel 10 (UART1 RX) Interrupt */
702#define IRQ_DMA11 0x00004000 /* DMA Channel 11 (UART1 TX) Interrupt */
703#define IRQ_CAN_RX 0x00008000 /* CAN Receive Interrupt */
704
705#define IRQ_CAN_TX 0x00010000 /* CAN Transmit Interrupt */
706#define IRQ_DMA1 0x00020000 /* DMA Channel 1 (Ethernet RX) Interrupt */
707#define IRQ_PFA_PORTH 0x00020000 /* PF Port H (PF47:32) Interrupt A */
708#define IRQ_DMA2 0x00040000 /* DMA Channel 2 (Ethernet TX) Interrupt */
709#define IRQ_PFB_PORTH 0x00040000 /* PF Port H (PF47:32) Interrupt B */
710#define IRQ_TIMER0 0x00080000 /* Timer 0 Interrupt */
711#define IRQ_TIMER1 0x00100000 /* Timer 1 Interrupt */
712#define IRQ_TIMER2 0x00200000 /* Timer 2 Interrupt */
713#define IRQ_TIMER3 0x00400000 /* Timer 3 Interrupt */
714#define IRQ_TIMER4 0x00800000 /* Timer 4 Interrupt */
715
716#define IRQ_TIMER5 0x01000000 /* Timer 5 Interrupt */
717#define IRQ_TIMER6 0x02000000 /* Timer 6 Interrupt */
718#define IRQ_TIMER7 0x04000000 /* Timer 7 Interrupt */
719#define IRQ_PFA_PORTFG 0x08000000 /* PF Ports F&G (PF31:0) Interrupt A */
720#define IRQ_PFB_PORTF 0x80000000 /* PF Port F (PF15:0) Interrupt B */
721#define IRQ_DMA12 0x20000000 /* DMA Channels 12 (MDMA1 Source) RX Interrupt */
722#define IRQ_DMA13 0x20000000 /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */
723#define IRQ_DMA14 0x40000000 /* DMA Channels 14 (MDMA0 Source) RX Interrupt */
724#define IRQ_DMA15 0x40000000 /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */
725#define IRQ_WDOG 0x80000000 /* Software Watchdog Timer Interrupt */
726#define IRQ_PFB_PORTG 0x10000000 /* PF Port G (PF31:16) Interrupt B */
727#endif
728
729/* SIC_IAR0 Macros */
730#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */
731#define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
732#define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
733#define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */
734#define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
735#define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
736#define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
737#define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
738
739/* SIC_IAR1 Macros */
740#define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */
741#define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
742#define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
743#define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */
744#define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
745#define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
746#define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
747#define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
748
749/* SIC_IAR2 Macros */
750#define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */
751#define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
752#define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
753#define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */
754#define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
755#define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
756#define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
757#define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
758
759/* SIC_IAR3 Macros */
760#define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */
761#define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */
762#define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */
763#define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */
764#define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */
765#define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */
766#define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */
767#define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */
768
769
770/* SIC_IMASK Masks */
771#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
772#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
773#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
774#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
775
776/* SIC_IWR Masks */
777#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
778#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
779#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
780#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
781
782
783/* ********* WATCHDOG TIMER MASKS ******************** */
784
785/* Watchdog Timer WDOG_CTL Register Masks */
786
787#define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */
788#define WDEV_RESET 0x0000 /* generate reset event on roll over */
789#define WDEV_NMI 0x0002 /* generate NMI event on roll over */
790#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */
791#define WDEV_NONE 0x0006 /* no event on roll over */
792#define WDEN 0x0FF0 /* enable watchdog */
793#define WDDIS 0x0AD0 /* disable watchdog */
794#define WDRO 0x8000 /* watchdog rolled over latch */
795
796/* depreciated WDOG_CTL Register Masks for legacy code */
797
798
799#define ICTL WDEV
800#define ENABLE_RESET WDEV_RESET
801#define WDOG_RESET WDEV_RESET
802#define ENABLE_NMI WDEV_NMI
803#define WDOG_NMI WDEV_NMI
804#define ENABLE_GPI WDEV_GPI
805#define WDOG_GPI WDEV_GPI
806#define DISABLE_EVT WDEV_NONE
807#define WDOG_NONE WDEV_NONE
808
809#define TMR_EN WDEN
810#define TMR_DIS WDDIS
811#define TRO WDRO
812#define ICTL_P0 0x01
813 #define ICTL_P1 0x02
814#define TRO_P 0x0F
815
816
817
818/* *************** REAL TIME CLOCK MASKS **************************/
819/* RTC_STAT and RTC_ALARM Masks */
820#define RTC_SEC 0x0000003F /* Real-Time Clock Seconds */
821#define RTC_MIN 0x00000FC0 /* Real-Time Clock Minutes */
822#define RTC_HR 0x0001F000 /* Real-Time Clock Hours */
823#define RTC_DAY 0xFFFE0000 /* Real-Time Clock Days */
824
825/* RTC_ALARM Macro z=day y=hr x=min w=sec */
826#define SET_ALARM(z,y,x,w) ((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F))
827
828/* RTC_ICTL and RTC_ISTAT Masks */
829#define STOPWATCH 0x0001 /* Stopwatch Interrupt Enable */
830#define ALARM 0x0002 /* Alarm Interrupt Enable */
831#define SECOND 0x0004 /* Seconds (1 Hz) Interrupt Enable */
832#define MINUTE 0x0008 /* Minutes Interrupt Enable */
833#define HOUR 0x0010 /* Hours Interrupt Enable */
834#define DAY 0x0020 /* 24 Hours (Days) Interrupt Enable */
835#define DAY_ALARM 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
836#define WRITE_PENDING 0x4000 /* Write Pending Status */
837#define WRITE_COMPLETE 0x8000 /* Write Complete Interrupt Enable */
838
839/* RTC_FAST / RTC_PREN Mask */
840#define PREN 0x0001 /* Enable Prescaler, RTC Runs @1 Hz */
841
842
843/* ************** UART CONTROLLER MASKS *************************/
844/* UARTx_LCR Masks */
845#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
846#define STB 0x04 /* Stop Bits */
847#define PEN 0x08 /* Parity Enable */
848#define EPS 0x10 /* Even Parity Select */
849#define STP 0x20 /* Stick Parity */
850#define SB 0x40 /* Set Break */
851#define DLAB 0x80 /* Divisor Latch Access */
852
853/* UARTx_MCR Mask */
854#define LOOP_ENA 0x10 /* Loopback Mode Enable */
855#define LOOP_ENA_P 0x04
856
857/* UARTx_LSR Masks */
858#define DR 0x01 /* Data Ready */
859#define OE 0x02 /* Overrun Error */
860#define PE 0x04 /* Parity Error */
861#define FE 0x08 /* Framing Error */
862#define BI 0x10 /* Break Interrupt */
863#define THRE 0x20 /* THR Empty */
864#define TEMT 0x40 /* TSR and UART_THR Empty */
865
866/* UARTx_IER Masks */
867#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
868#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
869#define ELSI 0x04 /* Enable RX Status Interrupt */
870
871/* UARTx_IIR Masks */
872#define NINT 0x01 /* Pending Interrupt */
873#define IIR_TX_READY 0x02 /* UART_THR empty */
874#define IIR_RX_READY 0x04 /* Receive data ready */
875#define IIR_LINE_CHANGE 0x06 /* Receive line status */
876#define IIR_STATUS 0x06 /* Highest Priority Pending Interrupt */
877
878/* UARTx_GCTL Masks */
879#define UCEN 0x01 /* Enable UARTx Clocks */
880#define IREN 0x02 /* Enable IrDA Mode */
881#define TPOLC 0x04 /* IrDA TX Polarity Change */
882#define RPOLC 0x08 /* IrDA RX Polarity Change */
883#define FPE 0x10 /* Force Parity Error On Transmit */
884#define FFE 0x20 /* Force Framing Error On Transmit */
885
886
887/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS ****************************/
888/* SPI_CTL Masks */
889#define TIMOD 0x0003 /* Transfer Initiate Mode */
890#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */
891#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */
892#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */
893#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */
894#define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */
895#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */
896#define PSSE 0x0010 /* Slave-Select Input Enable */
897#define EMISO 0x0020 /* Enable MISO As Output */
898#define SIZE 0x0100 /* Size of Words (16/8* Bits) */
899#define LSBF 0x0200 /* LSB First */
900#define CPHA 0x0400 /* Clock Phase */
901#define CPOL 0x0800 /* Clock Polarity */
902#define MSTR 0x1000 /* Master/Slave* */
903#define WOM 0x2000 /* Write Open Drain Master */
904#define SPE 0x4000 /* SPI Enable */
905
906/* SPI_FLG Masks */
907#define FLS1 0x0002 /* Enables SPI_FLOUT1 as SPI Slave-Select Output */
908#define FLS2 0x0004 /* Enables SPI_FLOUT2 as SPI Slave-Select Output */
909#define FLS3 0x0008 /* Enables SPI_FLOUT3 as SPI Slave-Select Output */
910#define FLS4 0x0010 /* Enables SPI_FLOUT4 as SPI Slave-Select Output */
911#define FLS5 0x0020 /* Enables SPI_FLOUT5 as SPI Slave-Select Output */
912#define FLS6 0x0040 /* Enables SPI_FLOUT6 as SPI Slave-Select Output */
913#define FLS7 0x0080 /* Enables SPI_FLOUT7 as SPI Slave-Select Output */
914#define FLG1 0xFDFF /* Activates SPI_FLOUT1 */
915#define FLG2 0xFBFF /* Activates SPI_FLOUT2 */
916#define FLG3 0xF7FF /* Activates SPI_FLOUT3 */
917#define FLG4 0xEFFF /* Activates SPI_FLOUT4 */
918#define FLG5 0xDFFF /* Activates SPI_FLOUT5 */
919#define FLG6 0xBFFF /* Activates SPI_FLOUT6 */
920#define FLG7 0x7FFF /* Activates SPI_FLOUT7 */
921
922/* SPI_STAT Masks */
923#define SPIF 0x0001 /* SPI Finished (Single-Word Transfer Complete) */
924#define MODF 0x0002 /* Mode Fault Error (Another Device Tried To Become Master) */
925#define TXE 0x0004 /* Transmission Error (Data Sent With No New Data In TDBR) */
926#define TXS 0x0008 /* SPI_TDBR Data Buffer Status (Full/Empty*) */
927#define RBSY 0x0010 /* Receive Error (Data Received With RDBR Full) */
928#define RXS 0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty*) */
929#define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */
930
931
932/* **************** GENERAL PURPOSE TIMER MASKS **********************/
933/* TIMER_ENABLE Masks */
934#define TIMEN0 0x0001 /* Enable Timer 0 */
935#define TIMEN1 0x0002 /* Enable Timer 1 */
936#define TIMEN2 0x0004 /* Enable Timer 2 */
937#define TIMEN3 0x0008 /* Enable Timer 3 */
938#define TIMEN4 0x0010 /* Enable Timer 4 */
939#define TIMEN5 0x0020 /* Enable Timer 5 */
940#define TIMEN6 0x0040 /* Enable Timer 6 */
941#define TIMEN7 0x0080 /* Enable Timer 7 */
942
943/* TIMER_DISABLE Masks */
944#define TIMDIS0 TIMEN0 /* Disable Timer 0 */
945#define TIMDIS1 TIMEN1 /* Disable Timer 1 */
946#define TIMDIS2 TIMEN2 /* Disable Timer 2 */
947#define TIMDIS3 TIMEN3 /* Disable Timer 3 */
948#define TIMDIS4 TIMEN4 /* Disable Timer 4 */
949#define TIMDIS5 TIMEN5 /* Disable Timer 5 */
950#define TIMDIS6 TIMEN6 /* Disable Timer 6 */
951#define TIMDIS7 TIMEN7 /* Disable Timer 7 */
952
953/* TIMER_STATUS Masks */
954#define TIMIL0 0x00000001 /* Timer 0 Interrupt */
955#define TIMIL1 0x00000002 /* Timer 1 Interrupt */
956#define TIMIL2 0x00000004 /* Timer 2 Interrupt */
957#define TIMIL3 0x00000008 /* Timer 3 Interrupt */
958#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */
959#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */
960#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */
961#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */
962#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */
963#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */
964#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */
965#define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */
966#define TIMIL4 0x00010000 /* Timer 4 Interrupt */
967#define TIMIL5 0x00020000 /* Timer 5 Interrupt */
968#define TIMIL6 0x00040000 /* Timer 6 Interrupt */
969#define TIMIL7 0x00080000 /* Timer 7 Interrupt */
970#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */
971#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */
972#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */
973#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */
974#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
975#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
976#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
977#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
978
979/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
980#define TOVL_ERR0 TOVF_ERR0
981#define TOVL_ERR1 TOVF_ERR1
982#define TOVL_ERR2 TOVF_ERR2
983#define TOVL_ERR3 TOVF_ERR3
984#define TOVL_ERR4 TOVF_ERR4
985#define TOVL_ERR5 TOVF_ERR5
986#define TOVL_ERR6 TOVF_ERR6
987#define TOVL_ERR7 TOVF_ERR7
988
989/* TIMERx_CONFIG Masks */
990#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */
991#define WDTH_CAP 0x0002 /* Width Capture Input Mode */
992#define EXT_CLK 0x0003 /* External Clock Mode */
993#define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */
994#define PERIOD_CNT 0x0008 /* Period Count */
995#define IRQ_ENA 0x0010 /* Interrupt Request Enable */
996#define TIN_SEL 0x0020 /* Timer Input Select */
997#define OUT_DIS 0x0040 /* Output Pad Disable */
998#define CLK_SEL 0x0080 /* Timer Clock Select */
999#define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */
1000#define EMU_RUN 0x0200 /* Emulation Behavior Select */
1001#define ERR_TYP 0xC000 /* Error Type */
1002
1003
1004/* ****************** GPIO PORTS F, G, H MASKS ***********************/
1005/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */
1006/* Port F Masks */
1007#define PF0 0x0001
1008#define PF1 0x0002
1009#define PF2 0x0004
1010#define PF3 0x0008
1011#define PF4 0x0010
1012#define PF5 0x0020
1013#define PF6 0x0040
1014#define PF7 0x0080
1015#define PF8 0x0100
1016#define PF9 0x0200
1017#define PF10 0x0400
1018#define PF11 0x0800
1019#define PF12 0x1000
1020#define PF13 0x2000
1021#define PF14 0x4000
1022#define PF15 0x8000
1023
1024/* Port G Masks */
1025#define PG0 0x0001
1026#define PG1 0x0002
1027#define PG2 0x0004
1028#define PG3 0x0008
1029#define PG4 0x0010
1030#define PG5 0x0020
1031#define PG6 0x0040
1032#define PG7 0x0080
1033#define PG8 0x0100
1034#define PG9 0x0200
1035#define PG10 0x0400
1036#define PG11 0x0800
1037#define PG12 0x1000
1038#define PG13 0x2000
1039#define PG14 0x4000
1040#define PG15 0x8000
1041
1042/* Port H Masks */
1043#define PH0 0x0001
1044#define PH1 0x0002
1045#define PH2 0x0004
1046#define PH3 0x0008
1047#define PH4 0x0010
1048#define PH5 0x0020
1049#define PH6 0x0040
1050#define PH7 0x0080
1051
1052
1053/* ******************* SERIAL PORT MASKS **************************************/
1054/* SPORTx_TCR1 Masks */
1055#define TSPEN 0x0001 /* Transmit Enable */
1056#define ITCLK 0x0002 /* Internal Transmit Clock Select */
1057#define DTYPE_NORM 0x0004 /* Data Format Normal */
1058#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
1059#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
1060#define TLSBIT 0x0010 /* Transmit Bit Order */
1061#define ITFS 0x0200 /* Internal Transmit Frame Sync Select */
1062#define TFSR 0x0400 /* Transmit Frame Sync Required Select */
1063#define DITFS 0x0800 /* Data-Independent Transmit Frame Sync Select */
1064#define LTFS 0x1000 /* Low Transmit Frame Sync Select */
1065#define LATFS 0x2000 /* Late Transmit Frame Sync Select */
1066#define TCKFE 0x4000 /* Clock Falling Edge Select */
1067
1068/* SPORTx_TCR2 Masks and Macro */
1069#define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
1070#define TXSE 0x0100 /* TX Secondary Enable */
1071#define TSFSE 0x0200 /* Transmit Stereo Frame Sync Enable */
1072#define TRFST 0x0400 /* Left/Right Order (1 = Right Channel 1st) */
1073
1074/* SPORTx_RCR1 Masks */
1075#define RSPEN 0x0001 /* Receive Enable */
1076#define IRCLK 0x0002 /* Internal Receive Clock Select */
1077#define DTYPE_NORM 0x0004 /* Data Format Normal */
1078#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
1079#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
1080#define RLSBIT 0x0010 /* Receive Bit Order */
1081#define IRFS 0x0200 /* Internal Receive Frame Sync Select */
1082#define RFSR 0x0400 /* Receive Frame Sync Required Select */
1083#define LRFS 0x1000 /* Low Receive Frame Sync Select */
1084#define LARFS 0x2000 /* Late Receive Frame Sync Select */
1085#define RCKFE 0x4000 /* Clock Falling Edge Select */
1086
1087/* SPORTx_RCR2 Masks */
1088#define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */
1089#define RXSE 0x0100 /* RX Secondary Enable */
1090#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
1091#define RRFST 0x0400 /* Right-First Data Order */
1092
1093/* SPORTx_STAT Masks */
1094#define RXNE 0x0001 /* Receive FIFO Not Empty Status */
1095#define RUVF 0x0002 /* Sticky Receive Underflow Status */
1096#define ROVF 0x0004 /* Sticky Receive Overflow Status */
1097#define TXF 0x0008 /* Transmit FIFO Full Status */
1098#define TUVF 0x0010 /* Sticky Transmit Underflow Status */
1099#define TOVF 0x0020 /* Sticky Transmit Overflow Status */
1100#define TXHRE 0x0040 /* Transmit Hold Register Empty */
1101
1102/* SPORTx_MCMC1 Macros */
1103#define SP_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
1104
1105/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */
1106#define SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
1107
1108/* SPORTx_MCMC2 Masks */
1109#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
1110#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
1111#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
1112#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */
1113#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */
1114#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */
1115#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */
1116#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
1117#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
1118#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
1119#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
1120#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
1121#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
1122#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
1123#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
1124#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
1125#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
1126#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
1127#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
1128#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
1129#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
1130#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
1131#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
1132
1133
1134/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
1135/* EBIU_AMGCTL Masks */
1136#define AMCKEN 0x0001 /* Enable CLKOUT */
1137#define AMBEN_NONE 0x0000 /* All Banks Disabled */
1138#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
1139#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
1140#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
1141#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
1142
1143/* EBIU_AMBCTL0 Masks */
1144#define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */
1145#define B0RDYPOL 0x00000002 /* B0 RDY Active High */
1146#define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */
1147#define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */
1148#define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */
1149#define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */
1150#define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */
1151#define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */
1152#define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */
1153#define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */
1154#define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1155#define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1156#define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1157#define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1158#define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */
1159#define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */
1160#define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */
1161#define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */
1162#define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */
1163#define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */
1164#define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */
1165#define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */
1166#define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */
1167#define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */
1168#define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */
1169#define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */
1170#define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */
1171#define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */
1172#define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */
1173#define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */
1174#define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */
1175#define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */
1176#define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */
1177#define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */
1178#define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */
1179#define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */
1180#define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */
1181#define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */
1182#define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */
1183#define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */
1184#define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */
1185#define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */
1186#define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */
1187#define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */
1188
1189#define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */
1190#define B1RDYPOL 0x00020000 /* B1 RDY Active High */
1191#define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */
1192#define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */
1193#define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */
1194#define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */
1195#define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */
1196#define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */
1197#define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */
1198#define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */
1199#define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1200#define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1201#define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1202#define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1203#define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */
1204#define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */
1205#define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */
1206#define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */
1207#define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */
1208#define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */
1209#define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */
1210#define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */
1211#define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */
1212#define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */
1213#define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */
1214#define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */
1215#define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */
1216#define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */
1217#define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */
1218#define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */
1219#define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */
1220#define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */
1221#define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */
1222#define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */
1223#define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */
1224#define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */
1225#define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */
1226#define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */
1227#define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */
1228#define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */
1229#define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */
1230#define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */
1231#define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */
1232#define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */
1233
1234/* EBIU_AMBCTL1 Masks */
1235#define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */
1236#define B2RDYPOL 0x00000002 /* B2 RDY Active High */
1237#define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */
1238#define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */
1239#define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */
1240#define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */
1241#define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */
1242#define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */
1243#define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */
1244#define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */
1245#define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1246#define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1247#define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1248#define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1249#define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */
1250#define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */
1251#define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */
1252#define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */
1253#define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */
1254#define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */
1255#define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */
1256#define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */
1257#define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */
1258#define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */
1259#define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */
1260#define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */
1261#define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */
1262#define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */
1263#define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */
1264#define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */
1265#define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */
1266#define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */
1267#define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */
1268#define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */
1269#define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */
1270#define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */
1271#define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */
1272#define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */
1273#define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */
1274#define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */
1275#define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */
1276#define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */
1277#define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */
1278#define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */
1279
1280#define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */
1281#define B3RDYPOL 0x00020000 /* B3 RDY Active High */
1282#define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */
1283#define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */
1284#define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */
1285#define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */
1286#define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */
1287#define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */
1288#define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */
1289#define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */
1290#define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1291#define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1292#define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1293#define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1294#define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */
1295#define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */
1296#define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */
1297#define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */
1298#define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */
1299#define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */
1300#define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */
1301#define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */
1302#define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */
1303#define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */
1304#define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */
1305#define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */
1306#define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */
1307#define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */
1308#define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */
1309#define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */
1310#define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */
1311#define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */
1312#define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */
1313#define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */
1314#define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */
1315#define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */
1316#define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */
1317#define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */
1318#define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */
1319#define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */
1320#define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */
1321#define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */
1322#define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */
1323#define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */
1324
1325
1326/* ********************** SDRAM CONTROLLER MASKS **********************************************/
1327/* EBIU_SDGCTL Masks */
1328#define SCTLE 0x00000001 /* Enable SDRAM Signals */
1329#define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */
1330#define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */
1331#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
1332#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
1333#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
1334#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
1335#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
1336#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
1337#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
1338#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
1339#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
1340#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
1341#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
1342#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
1343#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
1344#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
1345#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
1346#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
1347#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
1348#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
1349#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
1350#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
1351#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
1352#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
1353#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
1354#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
1355#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
1356#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
1357#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
1358#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
1359#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
1360#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
1361#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
1362#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
1363#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
1364#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
1365#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
1366#define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */
1367#define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */
1368#define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */
1369#define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */
1370#define EBUFE 0x02000000 /* Enable External Buffering Timing */
1371#define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */
1372#define EMREN 0x10000000 /* Extended Mode Register Enable */
1373#define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */
1374#define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */
1375
1376/* EBIU_SDBCTL Masks */
1377#define EBE 0x0001 /* Enable SDRAM External Bank */
1378#define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */
1379#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */
1380#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */
1381#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */
1382#define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */
1383#define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */
1384#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */
1385#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */
1386#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */
1387#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */
1388
1389/* EBIU_SDSTAT Masks */
1390#define SDCI 0x0001 /* SDRAM Controller Idle */
1391#define SDSRA 0x0002 /* SDRAM Self-Refresh Active */
1392#define SDPUA 0x0004 /* SDRAM Power-Up Active */
1393#define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */
1394#define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */
1395#define BGSTAT 0x0020 /* Bus Grant Status */
1396
1397
1398/* ************************** DMA CONTROLLER MASKS ********************************/
1399/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */
1400#define DMAEN 0x0001 /* DMA Channel Enable */
1401#define WNR 0x0002 /* Channel Direction (W/R*) */
1402#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
1403#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
1404#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
1405#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
1406#define RESTART 0x0020 /* DMA Buffer Clear */
1407#define DI_SEL 0x0040 /* Data Interrupt Timing Select */
1408#define DI_EN 0x0080 /* Data Interrupt Enable */
1409#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
1410#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
1411#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
1412#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
1413#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
1414#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
1415#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
1416#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
1417#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
1418#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
1419#define NDSIZE 0x0900 /* Next Descriptor Size */
1420#define DMAFLOW 0x7000 /* Flow Control */
1421#define DMAFLOW_STOP 0x0000 /* Stop Mode */
1422#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
1423#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
1424#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
1425#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
1426
1427/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
1428#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
1429#define PMAP 0xF000 /* Peripheral Mapped To This Channel */
1430#define PMAP_PPI 0x0000 /* PPI Port DMA */
1431#define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */
1432#define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */
1433#define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */
1434#define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */
1435#define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */
1436#define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */
1437#define PMAP_SPI 0x7000 /* SPI Port DMA */
1438#define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */
1439#define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */
1440#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */
1441#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */
1442
1443/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
1444#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
1445#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
1446#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
1447#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
1448
1449
1450/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
1451/* PPI_CONTROL Masks */
1452#define PORT_EN 0x0001 /* PPI Port Enable */
1453#define PORT_DIR 0x0002 /* PPI Port Direction */
1454#define XFR_TYPE 0x000C /* PPI Transfer Type */
1455#define PORT_CFG 0x0030 /* PPI Port Configuration */
1456#define FLD_SEL 0x0040 /* PPI Active Field Select */
1457#define PACK_EN 0x0080 /* PPI Packing Mode */
1458#define DMA32 0x0100 /* PPI 32-bit DMA Enable */
1459#define SKIP_EN 0x0200 /* PPI Skip Element Enable */
1460#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
1461#define DLEN_8 0x0000 /* Data Length = 8 Bits */
1462#define DLEN_10 0x0800 /* Data Length = 10 Bits */
1463#define DLEN_11 0x1000 /* Data Length = 11 Bits */
1464#define DLEN_12 0x1800 /* Data Length = 12 Bits */
1465#define DLEN_13 0x2000 /* Data Length = 13 Bits */
1466#define DLEN_14 0x2800 /* Data Length = 14 Bits */
1467#define DLEN_15 0x3000 /* Data Length = 15 Bits */
1468#define DLEN_16 0x3800 /* Data Length = 16 Bits */
1469#define DLENGTH 0x3800 /* PPI Data Length */
1470#define POLC 0x4000 /* PPI Clock Polarity */
1471#define POLS 0x8000 /* PPI Frame Sync Polarity */
1472
1473/* PPI_STATUS Masks */
1474#define FLD 0x0400 /* Field Indicator */
1475#define FT_ERR 0x0800 /* Frame Track Error */
1476#define OVR 0x1000 /* FIFO Overflow Error */
1477#define UNDR 0x2000 /* FIFO Underrun Error */
1478#define ERR_DET 0x4000 /* Error Detected Indicator */
1479#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
1480
1481
1482/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/
1483/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
1484#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
1485#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
1486
1487/* TWI_PRESCALE Masks */
1488#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
1489#define TWI_ENA 0x0080 /* TWI Enable */
1490#define SCCB 0x0200 /* SCCB Compatibility Enable */
1491
1492/* TWI_SLAVE_CTRL Masks */
1493#define SEN 0x0001 /* Slave Enable */
1494#define SADD_LEN 0x0002 /* Slave Address Length */
1495#define STDVAL 0x0004 /* Slave Transmit Data Valid */
1496#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
1497#define GEN 0x0010 /* General Call Adrress Matching Enabled */
1498
1499/* TWI_SLAVE_STAT Masks */
1500#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
1501#define GCALL 0x0002 /* General Call Indicator */
1502
1503/* TWI_MASTER_CTRL Masks */
1504#define MEN 0x0001 /* Master Mode Enable */
1505#define MADD_LEN 0x0002 /* Master Address Length */
1506#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
1507#define FAST 0x0008 /* Use Fast Mode Timing Specs */
1508#define STOP 0x0010 /* Issue Stop Condition */
1509#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
1510#define DCNT 0x3FC0 /* Data Bytes To Transfer */
1511#define SDAOVR 0x4000 /* Serial Data Override */
1512#define SCLOVR 0x8000 /* Serial Clock Override */
1513
1514/* TWI_MASTER_STAT Masks */
1515#define MPROG 0x0001 /* Master Transfer In Progress */
1516#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
1517#define ANAK 0x0004 /* Address Not Acknowledged */
1518#define DNAK 0x0008 /* Data Not Acknowledged */
1519#define BUFRDERR 0x0010 /* Buffer Read Error */
1520#define BUFWRERR 0x0020 /* Buffer Write Error */
1521#define SDASEN 0x0040 /* Serial Data Sense */
1522#define SCLSEN 0x0080 /* Serial Clock Sense */
1523#define BUSBUSY 0x0100 /* Bus Busy Indicator */
1524
1525/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
1526#define SINIT 0x0001 /* Slave Transfer Initiated */
1527#define SCOMP 0x0002 /* Slave Transfer Complete */
1528#define SERR 0x0004 /* Slave Transfer Error */
1529#define SOVF 0x0008 /* Slave Overflow */
1530#define MCOMP 0x0010 /* Master Transfer Complete */
1531#define MERR 0x0020 /* Master Transfer Error */
1532#define XMTSERV 0x0040 /* Transmit FIFO Service */
1533#define RCVSERV 0x0080 /* Receive FIFO Service */
1534
1535/* TWI_FIFO_CTRL Masks */
1536#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
1537#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
1538#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
1539#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
1540
1541/* TWI_FIFO_STAT Masks */
1542#define XMTSTAT 0x0003 /* Transmit FIFO Status */
1543#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
1544#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
1545#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
1546
1547#define RCVSTAT 0x000C /* Receive FIFO Status */
1548#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
1549#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
1550#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
1551
1552
1553/* ******************* PIN CONTROL REGISTER MASKS ************************/
1554/* PORT_MUX Masks */
1555#define PJSE 0x0001 /* Port J SPI/SPORT Enable */
1556#define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */
1557#define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */
1558
1559#define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */
1560#define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */
1561#define PJCE_CAN 0x0002 /* Enable CAN RX/TX */
1562#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */
1563
1564#define PFDE 0x0008 /* Port F DMA Request Enable */
1565#define PFDE_UART 0x0000 /* Enable UART0 RX/TX */
1566#define PFDE_DMA 0x0008 /* Enable DMAR1:0 */
1567
1568#define PFTE 0x0010 /* Port F Timer Enable */
1569#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */
1570#define PFTE_TIMER 0x0010 /* Enable TMR7:6 */
1571
1572#define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */
1573#define PFS6E_TIMER 0x0000 /* Enable TMR5 */
1574#define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */
1575
1576#define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */
1577#define PFS5E_TIMER 0x0000 /* Enable TMR4 */
1578#define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */
1579
1580#define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */
1581#define PFS4E_TIMER 0x0000 /* Enable TMR3 */
1582#define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */
1583
1584#define PFFE 0x0100 /* Port F PPI Frame Sync Enable */
1585#define PFFE_TIMER 0x0000 /* Enable TMR2 */
1586#define PFFE_PPI 0x0100 /* Enable PPI FS3 */
1587
1588#define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */
1589#define PGSE_PPI 0x0000 /* Enable PPI D9:8 */
1590#define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */
1591
1592#define PGRE 0x0400 /* Port G SPORT1 Receive Enable */
1593#define PGRE_PPI 0x0000 /* Enable PPI D12:10 */
1594#define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */
1595
1596#define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */
1597#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */
1598#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */
1599
1600
1601/* ****************** HANDSHAKE DMA (HDMA) MASKS *********************/
1602/* HDMAx_CTL Masks */
1603#define HMDMAEN 0x0001 /* Enable Handshake DMA 0/1 */
1604#define REP 0x0002 /* HDMA Request Polarity */
1605#define UTE 0x0004 /* Urgency Threshold Enable */
1606#define OIE 0x0010 /* Overflow Interrupt Enable */
1607#define BDIE 0x0020 /* Block Done Interrupt Enable */
1608#define MBDI 0x0040 /* Mask Block Done IRQ If Pending ECNT */
1609#define DRQ 0x0300 /* HDMA Request Type */
1610#define DRQ_NONE 0x0000 /* No Request */
1611#define DRQ_SINGLE 0x0100 /* Channels Request Single */
1612#define DRQ_MULTI 0x0200 /* Channels Request Multi (Default) */
1613#define DRQ_URGENT 0x0300 /* Channels Request Multi Urgent */
1614#define RBC 0x1000 /* Reload BCNT With IBCNT */
1615#define PS 0x2000 /* HDMA Pin Status */
1616#define OI 0x4000 /* Overflow Interrupt Generated */
1617#define BDI 0x8000 /* Block Done Interrupt Generated */
1618
1619/* entry addresses of the user-callable Boot ROM functions */
1620
1621#define _BOOTROM_RESET 0xEF000000
1622#define _BOOTROM_FINAL_INIT 0xEF000002
1623#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
1624#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
1625#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
1626#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
1627#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
1628#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
1629#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
1630
1631/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
1632#define PGDE_UART PFDE_UART
1633#define PGDE_DMA PFDE_DMA
1634#define CKELOW SCKELOW
1635
1636/* HOST Port Registers */
1637
1638#define HOST_CONTROL 0xffc03400 /* HOST Control Register */
1639#define HOST_STATUS 0xffc03404 /* HOST Status Register */
1640#define HOST_TIMEOUT 0xffc03408 /* HOST Acknowledge Mode Timeout Register */
1641
1642/* Counter Registers */
1643
1644#define CNT_CONFIG 0xffc03500 /* Configuration Register */
1645#define CNT_IMASK 0xffc03504 /* Interrupt Mask Register */
1646#define CNT_STATUS 0xffc03508 /* Status Register */
1647#define CNT_COMMAND 0xffc0350c /* Command Register */
1648#define CNT_DEBOUNCE 0xffc03510 /* Debounce Register */
1649#define CNT_COUNTER 0xffc03514 /* Counter Register */
1650#define CNT_MAX 0xffc03518 /* Maximal Count Register */
1651#define CNT_MIN 0xffc0351c /* Minimal Count Register */
1652
1653/* OTP/FUSE Registers */
1654
1655#define OTP_CONTROL 0xffc03600 /* OTP/Fuse Control Register */
1656#define OTP_BEN 0xffc03604 /* OTP/Fuse Byte Enable */
1657#define OTP_STATUS 0xffc03608 /* OTP/Fuse Status */
1658#define OTP_TIMING 0xffc0360c /* OTP/Fuse Access Timing */
1659
1660/* Security Registers */
1661
1662#define SECURE_SYSSWT 0xffc03620 /* Secure System Switches */
1663#define SECURE_CONTROL 0xffc03624 /* Secure Control */
1664#define SECURE_STATUS 0xffc03628 /* Secure Status */
1665
1666/* OTP Read/Write Data Buffer Registers */
1667
1668#define OTP_DATA0 0xffc03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1669#define OTP_DATA1 0xffc03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1670#define OTP_DATA2 0xffc03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1671#define OTP_DATA3 0xffc0368c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1672
1673/* Motor Control PWM Registers */
1674
1675#define PWM_CTRL 0xffc03700 /* PWM Control Register */
1676#define PWM_STAT 0xffc03704 /* PWM Status Register */
1677#define PWM_TM 0xffc03708 /* PWM Period Register */
1678#define PWM_DT 0xffc0370c /* PWM Dead Time Register */
1679#define PWM_GATE 0xffc03710 /* PWM Chopping Control */
1680#define PWM_CHA 0xffc03714 /* PWM Channel A Duty Control */
1681#define PWM_CHB 0xffc03718 /* PWM Channel B Duty Control */
1682#define PWM_CHC 0xffc0371c /* PWM Channel C Duty Control */
1683#define PWM_SEG 0xffc03720 /* PWM Crossover and Output Enable */
1684#define PWM_SYNCWT 0xffc03724 /* PWM Sync Pluse Width Control */
1685#define PWM_CHAL 0xffc03728 /* PWM Channel AL Duty Control (SR mode only) */
1686#define PWM_CHBL 0xffc0372c /* PWM Channel BL Duty Control (SR mode only) */
1687#define PWM_CHCL 0xffc03730 /* PWM Channel CL Duty Control (SR mode only) */
1688#define PWM_LSI 0xffc03734 /* PWM Low Side Invert (SR mode only) */
1689#define PWM_STAT2 0xffc03738 /* PWM Status Register 2 */
1690
1691
1692/* ********************************************************** */
1693/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
1694/* and MULTI BIT READ MACROS */
1695/* ********************************************************** */
1696
1697/* Bit masks for HOST_CONTROL */
1698
1699#define HOST_CNTR_HOST_EN 0x1 /* Host Enable */
1700#define HOST_CNTR_nHOST_EN 0x0
1701#define HOST_CNTR_HOST_END 0x2 /* Host Endianess */
1702#define HOST_CNTR_nHOST_END 0x0
1703#define HOST_CNTR_DATA_SIZE 0x4 /* Data Size */
1704#define HOST_CNTR_nDATA_SIZE 0x0
1705#define HOST_CNTR_HOST_RST 0x8 /* Host Reset */
1706#define HOST_CNTR_nHOST_RST 0x0
1707#define HOST_CNTR_HRDY_OVR 0x20 /* Host Ready Override */
1708#define HOST_CNTR_nHRDY_OVR 0x0
1709#define HOST_CNTR_INT_MODE 0x40 /* Interrupt Mode */
1710#define HOST_CNTR_nINT_MODE 0x0
1711#define HOST_CNTR_BT_EN 0x80 /* Bus Timeout Enable */
1712#define HOST_CNTR_ nBT_EN 0x0
1713#define HOST_CNTR_EHW 0x100 /* Enable Host Write */
1714#define HOST_CNTR_nEHW 0x0
1715#define HOST_CNTR_EHR 0x200 /* Enable Host Read */
1716#define HOST_CNTR_nEHR 0x0
1717#define HOST_CNTR_BDR 0x400 /* Burst DMA Requests */
1718#define HOST_CNTR_nBDR 0x0
1719
1720/* Bit masks for HOST_STATUS */
1721
1722#define HOST_STAT_READY 0x1 /* DMA Ready */
1723#define HOST_STAT_nREADY 0x0
1724#define HOST_STAT_FIFOFULL 0x2 /* FIFO Full */
1725#define HOST_STAT_nFIFOFULL 0x0
1726#define HOST_STAT_FIFOEMPTY 0x4 /* FIFO Empty */
1727#define HOST_STAT_nFIFOEMPTY 0x0
1728#define HOST_STAT_COMPLETE 0x8 /* DMA Complete */
1729#define HOST_STAT_nCOMPLETE 0x0
1730#define HOST_STAT_HSHK 0x10 /* Host Handshake */
1731#define HOST_STAT_nHSHK 0x0
1732#define HOST_STAT_TIMEOUT 0x20 /* Host Timeout */
1733#define HOST_STAT_nTIMEOUT 0x0
1734#define HOST_STAT_HIRQ 0x40 /* Host Interrupt Request */
1735#define HOST_STAT_nHIRQ 0x0
1736#define HOST_STAT_ALLOW_CNFG 0x80 /* Allow New Configuration */
1737#define HOST_STAT_nALLOW_CNFG 0x0
1738#define HOST_STAT_DMA_DIR 0x100 /* DMA Direction */
1739#define HOST_STAT_nDMA_DIR 0x0
1740#define HOST_STAT_BTE 0x200 /* Bus Timeout Enabled */
1741#define HOST_STAT_nBTE 0x0
1742#define HOST_STAT_HOSTRD_DONE 0x8000 /* Host Read Completion Interrupt */
1743#define HOST_STAT_nHOSTRD_DONE 0x0
1744
1745/* Bit masks for HOST_TIMEOUT */
1746
1747#define HOST_COUNT_TIMEOUT 0x7ff /* Host Timeout count */
1748
1749/* Bit masks for CNT_CONFIG */
1750
1751#define CNTE 0x1 /* Counter Enable */
1752#define nCNTE 0x0
1753#define DEBE 0x2 /* Debounce Enable */
1754#define nDEBE 0x0
1755#define CDGINV 0x10 /* CDG Pin Polarity Invert */
1756#define nCDGINV 0x0
1757#define CUDINV 0x20 /* CUD Pin Polarity Invert */
1758#define nCUDINV 0x0
1759#define CZMINV 0x40 /* CZM Pin Polarity Invert */
1760#define nCZMINV 0x0
1761#define CNTMODE 0x700 /* Counter Operating Mode */
1762#define ZMZC 0x800 /* CZM Zeroes Counter Enable */
1763#define nZMZC 0x0
1764#define BNDMODE 0x3000 /* Boundary register Mode */
1765#define INPDIS 0x8000 /* CUG and CDG Input Disable */
1766#define nINPDIS 0x0
1767
1768/* Bit masks for CNT_IMASK */
1769
1770#define ICIE 0x1 /* Illegal Gray/Binary Code Interrupt Enable */
1771#define nICIE 0x0
1772#define UCIE 0x2 /* Up count Interrupt Enable */
1773#define nUCIE 0x0
1774#define DCIE 0x4 /* Down count Interrupt Enable */
1775#define nDCIE 0x0
1776#define MINCIE 0x8 /* Min Count Interrupt Enable */
1777#define nMINCIE 0x0
1778#define MAXCIE 0x10 /* Max Count Interrupt Enable */
1779#define nMAXCIE 0x0
1780#define COV31IE 0x20 /* Bit 31 Overflow Interrupt Enable */
1781#define nCOV31IE 0x0
1782#define COV15IE 0x40 /* Bit 15 Overflow Interrupt Enable */
1783#define nCOV15IE 0x0
1784#define CZEROIE 0x80 /* Count to Zero Interrupt Enable */
1785#define nCZEROIE 0x0
1786#define CZMIE 0x100 /* CZM Pin Interrupt Enable */
1787#define nCZMIE 0x0
1788#define CZMEIE 0x200 /* CZM Error Interrupt Enable */
1789#define nCZMEIE 0x0
1790#define CZMZIE 0x400 /* CZM Zeroes Counter Interrupt Enable */
1791#define nCZMZIE 0x0
1792
1793/* Bit masks for CNT_STATUS */
1794
1795#define ICII 0x1 /* Illegal Gray/Binary Code Interrupt Identifier */
1796#define nICII 0x0
1797#define UCII 0x2 /* Up count Interrupt Identifier */
1798#define nUCII 0x0
1799#define DCII 0x4 /* Down count Interrupt Identifier */
1800#define nDCII 0x0
1801#define MINCII 0x8 /* Min Count Interrupt Identifier */
1802#define nMINCII 0x0
1803#define MAXCII 0x10 /* Max Count Interrupt Identifier */
1804#define nMAXCII 0x0
1805#define COV31II 0x20 /* Bit 31 Overflow Interrupt Identifier */
1806#define nCOV31II 0x0
1807#define COV15II 0x40 /* Bit 15 Overflow Interrupt Identifier */
1808#define nCOV15II 0x0
1809#define CZEROII 0x80 /* Count to Zero Interrupt Identifier */
1810#define nCZEROII 0x0
1811#define CZMII 0x100 /* CZM Pin Interrupt Identifier */
1812#define nCZMII 0x0
1813#define CZMEII 0x200 /* CZM Error Interrupt Identifier */
1814#define nCZMEII 0x0
1815#define CZMZII 0x400 /* CZM Zeroes Counter Interrupt Identifier */
1816#define nCZMZII 0x0
1817
1818/* Bit masks for CNT_COMMAND */
1819
1820#define W1LCNT 0xf /* Load Counter Register */
1821#define W1LMIN 0xf0 /* Load Min Register */
1822#define W1LMAX 0xf00 /* Load Max Register */
1823#define W1ZMONCE 0x1000 /* Enable CZM Clear Counter Once */
1824#define nW1ZMONCE 0x0
1825
1826/* Bit masks for CNT_DEBOUNCE */
1827
1828#define DPRESCALE 0xf /* Load Counter Register */
1829
1830/* CNT_COMMAND bit field options */
1831
1832#define W1LCNT_ZERO 0x0001 /* write 1 to load CNT_COUNTER with zero */
1833#define W1LCNT_MIN 0x0004 /* write 1 to load CNT_COUNTER from CNT_MIN */
1834#define W1LCNT_MAX 0x0008 /* write 1 to load CNT_COUNTER from CNT_MAX */
1835
1836#define W1LMIN_ZERO 0x0010 /* write 1 to load CNT_MIN with zero */
1837#define W1LMIN_CNT 0x0020 /* write 1 to load CNT_MIN from CNT_COUNTER */
1838#define W1LMIN_MAX 0x0080 /* write 1 to load CNT_MIN from CNT_MAX */
1839
1840#define W1LMAX_ZERO 0x0100 /* write 1 to load CNT_MAX with zero */
1841#define W1LMAX_CNT 0x0200 /* write 1 to load CNT_MAX from CNT_COUNTER */
1842#define W1LMAX_MIN 0x0400 /* write 1 to load CNT_MAX from CNT_MIN */
1843
1844/* CNT_CONFIG bit field options */
1845
1846#define CNTMODE_QUADENC 0x0000 /* quadrature encoder mode */
1847#define CNTMODE_BINENC 0x0100 /* binary encoder mode */
1848#define CNTMODE_UDCNT 0x0200 /* up/down counter mode */
1849#define CNTMODE_DIRCNT 0x0400 /* direction counter mode */
1850#define CNTMODE_DIRTMR 0x0500 /* direction timer mode */
1851
1852#define BNDMODE_COMP 0x0000 /* boundary compare mode */
1853#define BNDMODE_ZERO 0x1000 /* boundary compare and zero mode */
1854#define BNDMODE_CAPT 0x2000 /* boundary capture mode */
1855#define BNDMODE_AEXT 0x3000 /* boundary auto-extend mode */
1856
1857/* Bit masks for OTP_CONTROL */
1858
1859#define FUSE_FADDR 0x1ff /* OTP/Fuse Address */
1860#define FIEN 0x800 /* OTP/Fuse Interrupt Enable */
1861#define nFIEN 0x0
1862#define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */
1863#define nFTESTDEC 0x0
1864#define FWRTEST 0x2000 /* OTP/Fuse Write Test */
1865#define nFWRTEST 0x0
1866#define FRDEN 0x4000 /* OTP/Fuse Read Enable */
1867#define nFRDEN 0x0
1868#define FWREN 0x8000 /* OTP/Fuse Write Enable */
1869#define nFWREN 0x0
1870
1871/* Bit masks for OTP_BEN */
1872
1873#define FBEN 0xffff /* OTP/Fuse Byte Enable */
1874
1875/* Bit masks for OTP_STATUS */
1876
1877#define FCOMP 0x1 /* OTP/Fuse Access Complete */
1878#define nFCOMP 0x0
1879#define FERROR 0x2 /* OTP/Fuse Access Error */
1880#define nFERROR 0x0
1881#define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */
1882#define nMMRGLOAD 0x0
1883#define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */
1884#define nMMRGLOCK 0x0
1885#define FPGMEN 0x40 /* OTP/Fuse Program Enable */
1886#define nFPGMEN 0x0
1887
1888/* Bit masks for OTP_TIMING */
1889
1890#define USECDIV 0xff /* Micro Second Divider */
1891#define READACC 0x7f00 /* Read Access Time */
1892#define CPUMPRL 0x38000 /* Charge Pump Release Time */
1893#define CPUMPSU 0xc0000 /* Charge Pump Setup Time */
1894#define CPUMPHD 0xf00000 /* Charge Pump Hold Time */
1895#define PGMTIME 0xff000000 /* Program Time */
1896
1897/* Bit masks for SECURE_SYSSWT */
1898
1899#define EMUDABL 0x1 /* Emulation Disable. */
1900#define nEMUDABL 0x0
1901#define RSTDABL 0x2 /* Reset Disable */
1902#define nRSTDABL 0x0
1903#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */
1904#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */
1905#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */
1906#define DMA0OVR 0x800 /* DMA0 Memory Access Override */
1907#define nDMA0OVR 0x0
1908#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */
1909#define nDMA1OVR 0x0
1910#define EMUOVR 0x4000 /* Emulation Override */
1911#define nEMUOVR 0x0
1912#define OTPSEN 0x8000 /* OTP Secrets Enable. */
1913#define nOTPSEN 0x0
1914#define L2DABL 0x70000 /* L2 Memory Disable. */
1915
1916/* Bit masks for SECURE_CONTROL */
1917
1918#define SECURE0 0x1 /* SECURE 0 */
1919#define nSECURE0 0x0
1920#define SECURE1 0x2 /* SECURE 1 */
1921#define nSECURE1 0x0
1922#define SECURE2 0x4 /* SECURE 2 */
1923#define nSECURE2 0x0
1924#define SECURE3 0x8 /* SECURE 3 */
1925#define nSECURE3 0x0
1926
1927/* Bit masks for SECURE_STATUS */
1928
1929#define SECMODE 0x3 /* Secured Mode Control State */
1930#define NMI 0x4 /* Non Maskable Interrupt */
1931#define nNMI 0x0
1932#define AFVALID 0x8 /* Authentication Firmware Valid */
1933#define nAFVALID 0x0
1934#define AFEXIT 0x10 /* Authentication Firmware Exit */
1935#define nAFEXIT 0x0
1936#define SECSTAT 0xe0 /* Secure Status */
1937
1938
1939
1940#endif /* _DEF_BF51X_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/dma.h b/arch/blackfin/mach-bf518/include/mach/dma.h
new file mode 100644
index 000000000000..e2a71ba907e9
--- /dev/null
+++ b/arch/blackfin/mach-bf518/include/mach/dma.h
@@ -0,0 +1,57 @@
1/*
2 * file: include/asm-blackfin/mach-bf518/dma.h
3 * based on: include/asm-blackfin/mach-bf527/dma.h
4 * author: Michael Hennerich (michael.hennerich@analog.com)
5 *
6 * created:
7 * description:
8 * system DMA map
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
32#ifndef _MACH_DMA_H_
33#define _MACH_DMA_H_
34
35#define MAX_BLACKFIN_DMA_CHANNEL 16
36
37#define CH_PPI 0 /* PPI receive/transmit */
38#define CH_EMAC_RX 1 /* Ethernet MAC receive */
39#define CH_EMAC_TX 2 /* Ethernet MAC transmit */
40#define CH_SPORT0_RX 3 /* SPORT0 receive */
41#define CH_SPORT0_TX 4 /* SPORT0 transmit */
42#define CH_RSI 4 /* RSI */
43#define CH_SPORT1_RX 5 /* SPORT1 receive */
44#define CH_SPI1 5 /* SPI1 transmit/receive */
45#define CH_SPORT1_TX 6 /* SPORT1 transmit */
46#define CH_SPI0 7 /* SPI0 transmit/receive */
47#define CH_UART0_RX 8 /* UART0 receive */
48#define CH_UART0_TX 9 /* UART0 transmit */
49#define CH_UART1_RX 10 /* UART1 receive */
50#define CH_UART1_TX 11 /* UART1 transmit */
51
52#define CH_MEM_STREAM0_SRC 12 /* RX */
53#define CH_MEM_STREAM0_DEST 13 /* TX */
54#define CH_MEM_STREAM1_SRC 14 /* RX */
55#define CH_MEM_STREAM1_DEST 15 /* TX */
56
57#endif
diff --git a/arch/blackfin/mach-bf518/include/mach/irq.h b/arch/blackfin/mach-bf518/include/mach/irq.h
new file mode 100644
index 000000000000..e5062f107ae2
--- /dev/null
+++ b/arch/blackfin/mach-bf518/include/mach/irq.h
@@ -0,0 +1,260 @@
1/*
2 * file: include/asm-blackfin/mach-bf518/irq.h
3 * based on: include/asm-blackfin/mach-bf527/irq.h
4 * author: Michael Hennerich (michael.hennerich@analog.com)
5 *
6 * created:
7 * description:
8 * system mmr register map
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
32#ifndef _BF518_IRQ_H_
33#define _BF518_IRQ_H_
34
35/*
36 * Interrupt source definitions
37 Event Source Core Event Name
38 Core Emulation **
39 Events (highest priority) EMU 0
40 Reset RST 1
41 NMI NMI 2
42 Exception EVX 3
43 Reserved -- 4
44 Hardware Error IVHW 5
45 Core Timer IVTMR 6 *
46
47 .....
48
49 Software Interrupt 1 IVG14 31
50 Software Interrupt 2 --
51 (lowest priority) IVG15 32 *
52*/
53
54#define NR_PERI_INTS (2 * 32)
55
56/* The ABSTRACT IRQ definitions */
57/** the first seven of the following are fixed, the rest you change if you need to **/
58#define IRQ_EMU 0 /* Emulation */
59#define IRQ_RST 1 /* reset */
60#define IRQ_NMI 2 /* Non Maskable */
61#define IRQ_EVX 3 /* Exception */
62#define IRQ_UNUSED 4 /* - unused interrupt */
63#define IRQ_HWERR 5 /* Hardware Error */
64#define IRQ_CORETMR 6 /* Core timer */
65
66#define BFIN_IRQ(x) ((x) + 7)
67
68#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
69#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
70#define IRQ_DMAR0_BLK BFIN_IRQ(2) /* DMAR0 Block Interrupt */
71#define IRQ_DMAR1_BLK BFIN_IRQ(3) /* DMAR1 Block Interrupt */
72#define IRQ_DMAR0_OVR BFIN_IRQ(4) /* DMAR0 Overflow Error */
73#define IRQ_DMAR1_OVR BFIN_IRQ(5) /* DMAR1 Overflow Error */
74#define IRQ_PPI_ERROR BFIN_IRQ(6) /* PPI Error */
75#define IRQ_MAC_ERROR BFIN_IRQ(7) /* MAC Status */
76#define IRQ_SPORT0_ERROR BFIN_IRQ(8) /* SPORT0 Status */
77#define IRQ_SPORT1_ERROR BFIN_IRQ(9) /* SPORT1 Status */
78#define IRQ_PTP_ERROR BFIN_IRQ(10) /* PTP Error Interrupt */
79#define IRQ_UART0_ERROR BFIN_IRQ(12) /* UART0 Status */
80#define IRQ_UART1_ERROR BFIN_IRQ(13) /* UART1 Status */
81#define IRQ_RTC BFIN_IRQ(14) /* RTC */
82#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI) */
83#define IRQ_SPORT0_RX BFIN_IRQ(16) /* DMA 3 Channel (SPORT0 RX) */
84#define IRQ_SPORT0_TX BFIN_IRQ(17) /* DMA 4 Channel (SPORT0 TX) */
85#define IRQ_RSI BFIN_IRQ(17) /* DMA 4 Channel (RSI) */
86#define IRQ_SPORT1_RX BFIN_IRQ(18) /* DMA 5 Channel (SPORT1 RX/SPI) */
87#define IRQ_SPI1 BFIN_IRQ(18) /* DMA 5 Channel (SPI1) */
88#define IRQ_SPORT1_TX BFIN_IRQ(19) /* DMA 6 Channel (SPORT1 TX) */
89#define IRQ_TWI BFIN_IRQ(20) /* TWI */
90#define IRQ_SPI0 BFIN_IRQ(21) /* DMA 7 Channel (SPI0) */
91#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */
92#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */
93#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */
94#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */
95#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */
96#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */
97#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX) */
98#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */
99#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX) */
100#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */
101#define IRQ_TMR0 BFIN_IRQ(32) /* Timer 0 */
102#define IRQ_TMR1 BFIN_IRQ(33) /* Timer 1 */
103#define IRQ_TMR2 BFIN_IRQ(34) /* Timer 2 */
104#define IRQ_TMR3 BFIN_IRQ(35) /* Timer 3 */
105#define IRQ_TMR4 BFIN_IRQ(36) /* Timer 4 */
106#define IRQ_TMR5 BFIN_IRQ(37) /* Timer 5 */
107#define IRQ_TMR6 BFIN_IRQ(38) /* Timer 6 */
108#define IRQ_TMR7 BFIN_IRQ(39) /* Timer 7 */
109#define IRQ_PORTG_INTA BFIN_IRQ(40) /* Port G Interrupt A */
110#define IRQ_PORTG_INTB BFIN_IRQ(41) /* Port G Interrupt B */
111#define IRQ_MEM_DMA0 BFIN_IRQ(42) /* MDMA Stream 0 */
112#define IRQ_MEM_DMA1 BFIN_IRQ(43) /* MDMA Stream 1 */
113#define IRQ_WATCH BFIN_IRQ(44) /* Software Watchdog Timer */
114#define IRQ_PORTF_INTA BFIN_IRQ(45) /* Port F Interrupt A */
115#define IRQ_PORTF_INTB BFIN_IRQ(46) /* Port F Interrupt B */
116#define IRQ_SPI0_ERROR BFIN_IRQ(47) /* SPI0 Status */
117#define IRQ_SPI1_ERROR BFIN_IRQ(48) /* SPI1 Error */
118#define IRQ_RSI_INT0 BFIN_IRQ(51) /* RSI Interrupt0 */
119#define IRQ_RSI_INT1 BFIN_IRQ(52) /* RSI Interrupt1 */
120#define IRQ_PWM_TRIP BFIN_IRQ(53) /* PWM Trip Interrupt */
121#define IRQ_PWM_SYNC BFIN_IRQ(54) /* PWM Sync Interrupt */
122#define IRQ_PTP_STAT BFIN_IRQ(55) /* PTP Stat Interrupt */
123
124#define SYS_IRQS BFIN_IRQ(63) /* 70 */
125
126#define IRQ_PF0 71
127#define IRQ_PF1 72
128#define IRQ_PF2 73
129#define IRQ_PF3 74
130#define IRQ_PF4 75
131#define IRQ_PF5 76
132#define IRQ_PF6 77
133#define IRQ_PF7 78
134#define IRQ_PF8 79
135#define IRQ_PF9 80
136#define IRQ_PF10 81
137#define IRQ_PF11 82
138#define IRQ_PF12 83
139#define IRQ_PF13 84
140#define IRQ_PF14 85
141#define IRQ_PF15 86
142
143#define IRQ_PG0 87
144#define IRQ_PG1 88
145#define IRQ_PG2 89
146#define IRQ_PG3 90
147#define IRQ_PG4 91
148#define IRQ_PG5 92
149#define IRQ_PG6 93
150#define IRQ_PG7 94
151#define IRQ_PG8 95
152#define IRQ_PG9 96
153#define IRQ_PG10 97
154#define IRQ_PG11 98
155#define IRQ_PG12 99
156#define IRQ_PG13 100
157#define IRQ_PG14 101
158#define IRQ_PG15 102
159
160#define IRQ_PH0 103
161#define IRQ_PH1 104
162#define IRQ_PH2 105
163#define IRQ_PH3 106
164#define IRQ_PH4 107
165#define IRQ_PH5 108
166#define IRQ_PH6 109
167#define IRQ_PH7 110
168#define IRQ_PH8 111
169#define IRQ_PH9 112
170#define IRQ_PH10 113
171#define IRQ_PH11 114
172#define IRQ_PH12 115
173#define IRQ_PH13 116
174#define IRQ_PH14 117
175#define IRQ_PH15 118
176
177#define GPIO_IRQ_BASE IRQ_PF0
178
179#define NR_IRQS (IRQ_PH15 + 1)
180
181#define IVG7 7
182#define IVG8 8
183#define IVG9 9
184#define IVG10 10
185#define IVG11 11
186#define IVG12 12
187#define IVG13 13
188#define IVG14 14
189#define IVG15 15
190
191/* IAR0 BIT FIELDS */
192#define IRQ_PLL_WAKEUP_POS 0
193#define IRQ_DMA0_ERROR_POS 4
194#define IRQ_DMAR0_BLK_POS 8
195#define IRQ_DMAR1_BLK_POS 12
196#define IRQ_DMAR0_OVR_POS 16
197#define IRQ_DMAR1_OVR_POS 20
198#define IRQ_PPI_ERROR_POS 24
199#define IRQ_MAC_ERROR_POS 28
200
201/* IAR1 BIT FIELDS */
202#define IRQ_SPORT0_ERROR_POS 0
203#define IRQ_SPORT1_ERROR_POS 4
204#define IRQ_PTP_ERROR_POS 8
205#define IRQ_UART0_ERROR_POS 16
206#define IRQ_UART1_ERROR_POS 20
207#define IRQ_RTC_POS 24
208#define IRQ_PPI_POS 28
209
210/* IAR2 BIT FIELDS */
211#define IRQ_SPORT0_RX_POS 0
212#define IRQ_SPORT0_TX_POS 4
213#define IRQ_RSI_POS 4
214#define IRQ_SPORT1_RX_POS 8
215#define IRQ_SPI1_POS 8
216#define IRQ_SPORT1_TX_POS 12
217#define IRQ_TWI_POS 16
218#define IRQ_SPI0_POS 20
219#define IRQ_UART0_RX_POS 24
220#define IRQ_UART0_TX_POS 28
221
222/* IAR3 BIT FIELDS */
223#define IRQ_UART1_RX_POS 0
224#define IRQ_UART1_TX_POS 4
225#define IRQ_OPTSEC_POS 8
226#define IRQ_CNT_POS 12
227#define IRQ_MAC_RX_POS 16
228#define IRQ_PORTH_INTA_POS 20
229#define IRQ_MAC_TX_POS 24
230#define IRQ_PORTH_INTB_POS 28
231
232/* IAR4 BIT FIELDS */
233#define IRQ_TMR0_POS 0
234#define IRQ_TMR1_POS 4
235#define IRQ_TMR2_POS 8
236#define IRQ_TMR3_POS 12
237#define IRQ_TMR4_POS 16
238#define IRQ_TMR5_POS 20
239#define IRQ_TMR6_POS 24
240#define IRQ_TMR7_POS 28
241
242/* IAR5 BIT FIELDS */
243#define IRQ_PORTG_INTA_POS 0
244#define IRQ_PORTG_INTB_POS 4
245#define IRQ_MEM_DMA0_POS 8
246#define IRQ_MEM_DMA1_POS 12
247#define IRQ_WATCH_POS 16
248#define IRQ_PORTF_INTA_POS 20
249#define IRQ_PORTF_INTB_POS 24
250#define IRQ_SPI0_ERROR_POS 28
251
252/* IAR6 BIT FIELDS */
253#define IRQ_SPI1_ERROR_POS 0
254#define IRQ_RSI_INT0_POS 12
255#define IRQ_RSI_INT1_POS 16
256#define IRQ_PWM_TRIP_POS 20
257#define IRQ_PWM_SYNC_POS 24
258#define IRQ_PTP_STAT_POS 28
259
260#endif /* _BF518_IRQ_H_ */
diff --git a/arch/blackfin/mach-bf518/include/mach/mem_init.h b/arch/blackfin/mach-bf518/include/mach/mem_init.h
new file mode 100644
index 000000000000..2f4f4092fb54
--- /dev/null
+++ b/arch/blackfin/mach-bf518/include/mach/mem_init.h
@@ -0,0 +1,310 @@
1/*
2 * File: include/asm-blackfin/mach-bf518/mem_init.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 * Copyright 2004-2007 Analog Devices Inc.
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_MT48LC16M8A2TG_75 || CONFIG_MEM_GENERIC_BOARD || CONFIG_MEM_MT48LC32M8A2_75 || CONFIG_MEM_MT48LC32M16A2TG_75)
33#if (CONFIG_SCLK_HZ > 119402985)
34#define SDRAM_tRP TRP_2
35#define SDRAM_tRP_num 2
36#define SDRAM_tRAS TRAS_7
37#define SDRAM_tRAS_num 7
38#define SDRAM_tRCD TRCD_2
39#define SDRAM_tWR TWR_2
40#endif
41#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
42#define SDRAM_tRP TRP_2
43#define SDRAM_tRP_num 2
44#define SDRAM_tRAS TRAS_6
45#define SDRAM_tRAS_num 6
46#define SDRAM_tRCD TRCD_2
47#define SDRAM_tWR TWR_2
48#endif
49#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
50#define SDRAM_tRP TRP_2
51#define SDRAM_tRP_num 2
52#define SDRAM_tRAS TRAS_5
53#define SDRAM_tRAS_num 5
54#define SDRAM_tRCD TRCD_2
55#define SDRAM_tWR TWR_2
56#endif
57#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
58#define SDRAM_tRP TRP_2
59#define SDRAM_tRP_num 2
60#define SDRAM_tRAS TRAS_4
61#define SDRAM_tRAS_num 4
62#define SDRAM_tRCD TRCD_2
63#define SDRAM_tWR TWR_2
64#endif
65#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
66#define SDRAM_tRP TRP_2
67#define SDRAM_tRP_num 2
68#define SDRAM_tRAS TRAS_3
69#define SDRAM_tRAS_num 3
70#define SDRAM_tRCD TRCD_2
71#define SDRAM_tWR TWR_2
72#endif
73#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
74#define SDRAM_tRP TRP_1
75#define SDRAM_tRP_num 1
76#define SDRAM_tRAS TRAS_4
77#define SDRAM_tRAS_num 3
78#define SDRAM_tRCD TRCD_1
79#define SDRAM_tWR TWR_2
80#endif
81#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
82#define SDRAM_tRP TRP_1
83#define SDRAM_tRP_num 1
84#define SDRAM_tRAS TRAS_3
85#define SDRAM_tRAS_num 3
86#define SDRAM_tRCD TRCD_1
87#define SDRAM_tWR TWR_2
88#endif
89#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
90#define SDRAM_tRP TRP_1
91#define SDRAM_tRP_num 1
92#define SDRAM_tRAS TRAS_2
93#define SDRAM_tRAS_num 2
94#define SDRAM_tRCD TRCD_1
95#define SDRAM_tWR TWR_2
96#endif
97#if (CONFIG_SCLK_HZ <= 29850746)
98#define SDRAM_tRP TRP_1
99#define SDRAM_tRP_num 1
100#define SDRAM_tRAS TRAS_1
101#define SDRAM_tRAS_num 1
102#define SDRAM_tRCD TRCD_1
103#define SDRAM_tWR TWR_2
104#endif
105#endif
106
107#if (CONFIG_MEM_MT48LC16M16A2TG_75)
108 /*SDRAM INFORMATION: */
109#define SDRAM_Tref 64 /* Refresh period in milliseconds */
110#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
111#define SDRAM_CL CL_3
112#endif
113
114#if (CONFIG_MEM_MT48LC16M8A2TG_75)
115 /*SDRAM INFORMATION: */
116#define SDRAM_Tref 64 /* Refresh period in milliseconds */
117#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
118#define SDRAM_CL CL_3
119#endif
120
121#if (CONFIG_MEM_MT48LC32M8A2_75)
122 /*SDRAM INFORMATION: */
123#define SDRAM_Tref 64 /* Refresh period in milliseconds */
124#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
125#define SDRAM_CL CL_3
126#endif
127
128#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
129 /*SDRAM INFORMATION: */
130#define SDRAM_Tref 64 /* Refresh period in milliseconds */
131#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
132#define SDRAM_CL CL_3
133#endif
134
135#if (CONFIG_MEM_GENERIC_BOARD)
136 /*SDRAM INFORMATION: Modify this for your board */
137#define SDRAM_Tref 64 /* Refresh period in milliseconds */
138#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
139#define SDRAM_CL CL_3
140#endif
141
142#if (CONFIG_MEM_MT48LC32M16A2TG_75)
143 /*SDRAM INFORMATION: */
144#define SDRAM_Tref 64 /* Refresh period in milliseconds */
145#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
146#define SDRAM_CL CL_3
147#endif
148
149/* Equation from section 17 (p17-46) of BF533 HRM */
150#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
151
152/* Enable SCLK Out */
153#define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
154
155#if defined CONFIG_CLKIN_HALF
156#define CLKIN_HALF 1
157#else
158#define CLKIN_HALF 0
159#endif
160
161#if defined CONFIG_PLL_BYPASS
162#define PLL_BYPASS 1
163#else
164#define PLL_BYPASS 0
165#endif
166
167/***************************************Currently Not Being Used *********************************/
168#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
169#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
170#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ))
171#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
172#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
173
174#if (flash_EBIU_AMBCTL_TT > 3)
175#define flash_EBIU_AMBCTL0_TT B0TT_4
176#endif
177#if (flash_EBIU_AMBCTL_TT == 3)
178#define flash_EBIU_AMBCTL0_TT B0TT_3
179#endif
180#if (flash_EBIU_AMBCTL_TT == 2)
181#define flash_EBIU_AMBCTL0_TT B0TT_2
182#endif
183#if (flash_EBIU_AMBCTL_TT < 2)
184#define flash_EBIU_AMBCTL0_TT B0TT_1
185#endif
186
187#if (flash_EBIU_AMBCTL_ST > 3)
188#define flash_EBIU_AMBCTL0_ST B0ST_4
189#endif
190#if (flash_EBIU_AMBCTL_ST == 3)
191#define flash_EBIU_AMBCTL0_ST B0ST_3
192#endif
193#if (flash_EBIU_AMBCTL_ST == 2)
194#define flash_EBIU_AMBCTL0_ST B0ST_2
195#endif
196#if (flash_EBIU_AMBCTL_ST < 2)
197#define flash_EBIU_AMBCTL0_ST B0ST_1
198#endif
199
200#if (flash_EBIU_AMBCTL_HT > 2)
201#define flash_EBIU_AMBCTL0_HT B0HT_3
202#endif
203#if (flash_EBIU_AMBCTL_HT == 2)
204#define flash_EBIU_AMBCTL0_HT B0HT_2
205#endif
206#if (flash_EBIU_AMBCTL_HT == 1)
207#define flash_EBIU_AMBCTL0_HT B0HT_1
208#endif
209#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
210#define flash_EBIU_AMBCTL0_HT B0HT_0
211#endif
212#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
213#define flash_EBIU_AMBCTL0_HT B0HT_1
214#endif
215
216#if (flash_EBIU_AMBCTL_WAT > 14)
217#define flash_EBIU_AMBCTL0_WAT B0WAT_15
218#endif
219#if (flash_EBIU_AMBCTL_WAT == 14)
220#define flash_EBIU_AMBCTL0_WAT B0WAT_14
221#endif
222#if (flash_EBIU_AMBCTL_WAT == 13)
223#define flash_EBIU_AMBCTL0_WAT B0WAT_13
224#endif
225#if (flash_EBIU_AMBCTL_WAT == 12)
226#define flash_EBIU_AMBCTL0_WAT B0WAT_12
227#endif
228#if (flash_EBIU_AMBCTL_WAT == 11)
229#define flash_EBIU_AMBCTL0_WAT B0WAT_11
230#endif
231#if (flash_EBIU_AMBCTL_WAT == 10)
232#define flash_EBIU_AMBCTL0_WAT B0WAT_10
233#endif
234#if (flash_EBIU_AMBCTL_WAT == 9)
235#define flash_EBIU_AMBCTL0_WAT B0WAT_9
236#endif
237#if (flash_EBIU_AMBCTL_WAT == 8)
238#define flash_EBIU_AMBCTL0_WAT B0WAT_8
239#endif
240#if (flash_EBIU_AMBCTL_WAT == 7)
241#define flash_EBIU_AMBCTL0_WAT B0WAT_7
242#endif
243#if (flash_EBIU_AMBCTL_WAT == 6)
244#define flash_EBIU_AMBCTL0_WAT B0WAT_6
245#endif
246#if (flash_EBIU_AMBCTL_WAT == 5)
247#define flash_EBIU_AMBCTL0_WAT B0WAT_5
248#endif
249#if (flash_EBIU_AMBCTL_WAT == 4)
250#define flash_EBIU_AMBCTL0_WAT B0WAT_4
251#endif
252#if (flash_EBIU_AMBCTL_WAT == 3)
253#define flash_EBIU_AMBCTL0_WAT B0WAT_3
254#endif
255#if (flash_EBIU_AMBCTL_WAT == 2)
256#define flash_EBIU_AMBCTL0_WAT B0WAT_2
257#endif
258#if (flash_EBIU_AMBCTL_WAT == 1)
259#define flash_EBIU_AMBCTL0_WAT B0WAT_1
260#endif
261
262#if (flash_EBIU_AMBCTL_RAT > 14)
263#define flash_EBIU_AMBCTL0_RAT B0RAT_15
264#endif
265#if (flash_EBIU_AMBCTL_RAT == 14)
266#define flash_EBIU_AMBCTL0_RAT B0RAT_14
267#endif
268#if (flash_EBIU_AMBCTL_RAT == 13)
269#define flash_EBIU_AMBCTL0_RAT B0RAT_13
270#endif
271#if (flash_EBIU_AMBCTL_RAT == 12)
272#define flash_EBIU_AMBCTL0_RAT B0RAT_12
273#endif
274#if (flash_EBIU_AMBCTL_RAT == 11)
275#define flash_EBIU_AMBCTL0_RAT B0RAT_11
276#endif
277#if (flash_EBIU_AMBCTL_RAT == 10)
278#define flash_EBIU_AMBCTL0_RAT B0RAT_10
279#endif
280#if (flash_EBIU_AMBCTL_RAT == 9)
281#define flash_EBIU_AMBCTL0_RAT B0RAT_9
282#endif
283#if (flash_EBIU_AMBCTL_RAT == 8)
284#define flash_EBIU_AMBCTL0_RAT B0RAT_8
285#endif
286#if (flash_EBIU_AMBCTL_RAT == 7)
287#define flash_EBIU_AMBCTL0_RAT B0RAT_7
288#endif
289#if (flash_EBIU_AMBCTL_RAT == 6)
290#define flash_EBIU_AMBCTL0_RAT B0RAT_6
291#endif
292#if (flash_EBIU_AMBCTL_RAT == 5)
293#define flash_EBIU_AMBCTL0_RAT B0RAT_5
294#endif
295#if (flash_EBIU_AMBCTL_RAT == 4)
296#define flash_EBIU_AMBCTL0_RAT B0RAT_4
297#endif
298#if (flash_EBIU_AMBCTL_RAT == 3)
299#define flash_EBIU_AMBCTL0_RAT B0RAT_3
300#endif
301#if (flash_EBIU_AMBCTL_RAT == 2)
302#define flash_EBIU_AMBCTL0_RAT B0RAT_2
303#endif
304#if (flash_EBIU_AMBCTL_RAT == 1)
305#define flash_EBIU_AMBCTL0_RAT B0RAT_1
306#endif
307
308#define flash_EBIU_AMBCTL0 \
309 (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
310 flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
diff --git a/arch/blackfin/mach-bf518/include/mach/mem_map.h b/arch/blackfin/mach-bf518/include/mach/mem_map.h
new file mode 100644
index 000000000000..10f678f3c5c0
--- /dev/null
+++ b/arch/blackfin/mach-bf518/include/mach/mem_map.h
@@ -0,0 +1,102 @@
1/*
2 * file: include/asm-blackfin/mach-bf518/mem_map.h
3 * based on: include/asm-blackfin/mach-bf527/mem_map.h
4 * author: Bryan Wu <cooloney@kernel.org>
5 *
6 * created:
7 * description:
8 * Memory MAP Common header file for blackfin BF518/6/4/2 of processors.
9 * rev:
10 *
11 * modified:
12 *
13 * bugs: enter bugs at http://blackfin.uclinux.org/
14 *
15 * this program is free software; you can redistribute it and/or modify
16 * it under the terms of the gnu general public license as published by
17 * the free software foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * this program is distributed in the hope that it will be useful,
21 * but without any warranty; without even the implied warranty of
22 * merchantability or fitness for a particular purpose. see the
23 * gnu general public license for more details.
24 *
25 * you should have received a copy of the gnu general public license
26 * along with this program; see the file copying.
27 * if not, write to the free software foundation,
28 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
29 */
30
31#ifndef _MEM_MAP_518_H_
32#define _MEM_MAP_518_H_
33
34#define COREMMR_BASE 0xFFE00000 /* Core MMRs */
35#define SYSMMR_BASE 0xFFC00000 /* System MMRs */
36
37/* Async Memory Banks */
38#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
39#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */
40#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */
41#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */
42#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */
43#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */
44#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
45#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */
46
47/* Boot ROM Memory */
48
49#define BOOT_ROM_START 0xEF000000
50#define BOOT_ROM_LENGTH 0x8000
51
52/* Level 1 Memory */
53
54/* Memory Map for ADSP-BF518/6/4/2 processors */
55
56#ifdef CONFIG_BFIN_ICACHE
57#define BFIN_ICACHESIZE (16 * 1024)
58#else
59#define BFIN_ICACHESIZE (0)
60#endif
61
62#define L1_CODE_START 0xFFA00000
63#define L1_DATA_A_START 0xFF800000
64#define L1_DATA_B_START 0xFF900000
65
66#define L1_CODE_LENGTH 0xC000
67
68#ifdef CONFIG_BFIN_DCACHE
69
70#ifdef CONFIG_BFIN_DCACHE_BANKA
71#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
72#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
73#define L1_DATA_B_LENGTH 0x8000
74#define BFIN_DCACHESIZE (16 * 1024)
75#define BFIN_DSUPBANKS 1
76#else
77#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
78#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
79#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
80#define BFIN_DCACHESIZE (32 * 1024)
81#define BFIN_DSUPBANKS 2
82#endif
83
84#else
85#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
86#define L1_DATA_A_LENGTH 0x8000
87#define L1_DATA_B_LENGTH 0x8000
88#define BFIN_DCACHESIZE 0
89#define BFIN_DSUPBANKS 0
90#endif /*CONFIG_BFIN_DCACHE */
91
92/* Level 2 Memory - none */
93
94#define L2_START 0
95#define L2_LENGTH 0
96
97/* Scratch Pad Memory */
98
99#define L1_SCRATCH_START 0xFFB00000
100#define L1_SCRATCH_LENGTH 0x1000
101
102#endif /* _MEM_MAP_518_H_ */
diff --git a/arch/blackfin/mach-bf518/include/mach/portmux.h b/arch/blackfin/mach-bf518/include/mach/portmux.h
new file mode 100644
index 000000000000..5af30c8ecfe7
--- /dev/null
+++ b/arch/blackfin/mach-bf518/include/mach/portmux.h
@@ -0,0 +1,188 @@
1#ifndef _MACH_PORTMUX_H_
2#define _MACH_PORTMUX_H_
3
4#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
5
6/* EMAC MII/RMII Port Mux */
7#define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
8#define P_MII0_ERxD2 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
9#define P_MII0_ETxD3 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
10#define P_MII0_ERxD3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
11#define P_MII0_ERxCLK (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
12#define P_MII0_ERxDV (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
13#define P_MII0_COL (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
14
15#define P_MII0_MDC (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
16#define P_MII0_MDIO (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
17#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
18#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
19#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
20#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
21#define P_MII0_ETxEn (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
22#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
23#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
24#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
25#define P_MII0_ETxCLK (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
26
27#define P_MII {\
28 P_MII0_ETxD0, \
29 P_MII0_ETxD1, \
30 P_MII0_ETxD2, \
31 P_MII0_ETxD3, \
32 P_MII0_ETxEN, \
33 P_MII0_TxCLK, \
34 P_MII0_PHYINT, \
35 P_MII0_COL, \
36 P_MII0_ERxD0, \
37 P_MII0_ERxD1, \
38 P_MII0_ERxD2, \
39 P_MII0_ERxD3, \
40 P_MII0_ERxDV, \
41 P_MII0_ERxCLK, \
42 P_MII0_ERxER, \
43 P_MII0_CRS, \
44 P_MII0_MDC, \
45 P_MII0_MDIO, 0}
46
47#define P_RMII {\
48 P_MII0_ETxD0, \
49 P_MII0_ETxD1, \
50 P_MII0_ETxEN, \
51 P_MII0_ERxD0, \
52 P_MII0_ERxD1, \
53 P_MII0_ERxER, \
54 P_MII0_TxCLK, \
55 P_MII0_PHYINT, \
56 P_MII0_CRS, \
57 P_MII0_MDC, \
58 P_MII0_MDIO, 0}
59
60/* PPI Port Mux */
61#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
62#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
63#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
64#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
65#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
66#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
67#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
68#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
69#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
70#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
71#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
72#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
73#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
74#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
75#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
76#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
77
78#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
79#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
80#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
81#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
82
83/* SPI Port Mux */
84#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
85#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
86#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
87#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
88
89#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
90#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
91#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
92#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(2))
93#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
94
95#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
96#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
97#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
98#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1))
99
100#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(2))
101#define P_SPI1_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2))
102#define P_SPI1_SSEL3 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(2))
103#define P_SPI1_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(2))
104#define P_SPI1_SSEL5 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(2))
105
106/* SPORT Port Mux */
107#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
108#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
109#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
110#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
111#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
112#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
113#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
114#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
115
116#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
117#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
118#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
119#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
120#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
121#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
122#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
123#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
124
125/* UART Port Mux */
126#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
127#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
128
129#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
130#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(1))
131
132/* Timer */
133#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2))
134#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
135#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
136#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2))
137#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2))
138#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(2))
139#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
140#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(2))
141#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(2))
142
143/* DMA */
144#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(1))
145#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1))
146
147/* TWI */
148#define P_TWI0_SCL (P_DONTCARE)
149#define P_TWI0_SDA (P_DONTCARE)
150
151/* PWM */
152#define P_PWM0_AH (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
153#define P_PWM0_AL (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
154#define P_PWM0_BH (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
155#define P_PWM0_BL (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
156#define P_PWM0_CH (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
157#define P_PWM0_CL (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
158#define P_PWM0_SYNC (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
159
160#define P_PWM1_AH (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(2))
161#define P_PWM1_AL (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
162#define P_PWM1_BH (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
163#define P_PWM1_BL (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
164#define P_PWM1_CH (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
165#define P_PWM1_CL (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
166#define P_PWM1_SYNC (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
167
168#define P_PWM_TRIPB (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
169
170/* RSI */
171#define P_RSI_DATA0 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
172#define P_RSI_DATA1 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
173#define P_RSI_DATA2 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
174#define P_RSI_DATA3 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
175#define P_RSI_DATA4 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(2))
176#define P_RSI_DATA5 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(2))
177#define P_RSI_DATA6 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2))
178#define P_RSI_DATA7 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2))
179#define P_RSI_CMD (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
180#define P_RSI_CLK (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
181
182/* PTP */
183#define P_PTP_PPS (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2))
184#define P_PTP_CLKOUT (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2))
185
186#define P_HWAIT (P_DEFINED | P_IDENT(GPIO_PG000000000) | P_FUNCT(1))
187
188#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/mach-bf518/ints-priority.c b/arch/blackfin/mach-bf518/ints-priority.c
new file mode 100644
index 000000000000..c490c79194c0
--- /dev/null
+++ b/arch/blackfin/mach-bf518/ints-priority.c
@@ -0,0 +1,99 @@
1/*
2 * File: arch/blackfin/mach-bf518/ints-priority.c
3 * Based on: arch/blackfin/mach-bf527/ints-priority.c
4 * Author: Bryan Wu <cooloney@kernel.org>
5 *
6 * Created:
7 * Description: Set up the interrupt priorities
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <linux/module.h>
31#include <linux/irq.h>
32#include <asm/blackfin.h>
33
34void __init program_IAR(void)
35{
36 /* Program the IAR0 Register with the configured priority */
37 bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
38 ((CONFIG_IRQ_DMA0_ERROR - 7) << IRQ_DMA0_ERROR_POS) |
39 ((CONFIG_IRQ_DMAR0_BLK - 7) << IRQ_DMAR0_BLK_POS) |
40 ((CONFIG_IRQ_DMAR1_BLK - 7) << IRQ_DMAR1_BLK_POS) |
41 ((CONFIG_IRQ_DMAR0_OVR - 7) << IRQ_DMAR0_OVR_POS) |
42 ((CONFIG_IRQ_DMAR1_OVR - 7) << IRQ_DMAR1_OVR_POS) |
43 ((CONFIG_IRQ_PPI_ERROR - 7) << IRQ_PPI_ERROR_POS) |
44 ((CONFIG_IRQ_MAC_ERROR - 7) << IRQ_MAC_ERROR_POS));
45
46
47 bfin_write_SIC_IAR1(((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) |
48 ((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS) |
49 ((CONFIG_IRQ_PTP_ERROR - 7) << IRQ_PTP_ERROR_POS) |
50 ((CONFIG_IRQ_UART0_ERROR - 7) << IRQ_UART0_ERROR_POS) |
51 ((CONFIG_IRQ_UART1_ERROR - 7) << IRQ_UART1_ERROR_POS) |
52 ((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS) |
53 ((CONFIG_IRQ_PPI - 7) << IRQ_PPI_POS));
54
55 bfin_write_SIC_IAR2(((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) |
56 ((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) |
57 ((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS) |
58 ((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) |
59 ((CONFIG_IRQ_TWI - 7) << IRQ_TWI_POS) |
60 ((CONFIG_IRQ_SPI0 - 7) << IRQ_SPI0_POS) |
61 ((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
62 ((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS));
63
64 bfin_write_SIC_IAR3(((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) |
65 ((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) |
66 ((CONFIG_IRQ_OPTSEC - 7) << IRQ_OPTSEC_POS) |
67 ((CONFIG_IRQ_CNT - 7) << IRQ_CNT_POS) |
68 ((CONFIG_IRQ_MAC_RX - 7) << IRQ_MAC_RX_POS) |
69 ((CONFIG_IRQ_PORTH_INTA - 7) << IRQ_PORTH_INTA_POS) |
70 ((CONFIG_IRQ_MAC_TX - 7) << IRQ_MAC_TX_POS) |
71 ((CONFIG_IRQ_PORTH_INTB - 7) << IRQ_PORTH_INTB_POS));
72
73 bfin_write_SIC_IAR4(((CONFIG_IRQ_TMR0 - 7) << IRQ_TMR0_POS) |
74 ((CONFIG_IRQ_TMR1 - 7) << IRQ_TMR1_POS) |
75 ((CONFIG_IRQ_TMR2 - 7) << IRQ_TMR2_POS) |
76 ((CONFIG_IRQ_TMR3 - 7) << IRQ_TMR3_POS) |
77 ((CONFIG_IRQ_TMR4 - 7) << IRQ_TMR4_POS) |
78 ((CONFIG_IRQ_TMR5 - 7) << IRQ_TMR5_POS) |
79 ((CONFIG_IRQ_TMR6 - 7) << IRQ_TMR6_POS) |
80 ((CONFIG_IRQ_TMR7 - 7) << IRQ_TMR7_POS));
81
82 bfin_write_SIC_IAR5(((CONFIG_IRQ_PORTG_INTA - 7) << IRQ_PORTG_INTA_POS) |
83 ((CONFIG_IRQ_PORTG_INTB - 7) << IRQ_PORTG_INTB_POS) |
84 ((CONFIG_IRQ_MEM_DMA0 - 7) << IRQ_MEM_DMA0_POS) |
85 ((CONFIG_IRQ_MEM_DMA1 - 7) << IRQ_MEM_DMA1_POS) |
86 ((CONFIG_IRQ_WATCH - 7) << IRQ_WATCH_POS) |
87 ((CONFIG_IRQ_PORTF_INTA - 7) << IRQ_PORTF_INTA_POS) |
88 ((CONFIG_IRQ_PORTF_INTB - 7) << IRQ_PORTF_INTB_POS) |
89 ((CONFIG_IRQ_SPI0_ERROR - 7) << IRQ_SPI0_ERROR_POS));
90
91 bfin_write_SIC_IAR6(((CONFIG_IRQ_SPI1_ERROR - 7) << IRQ_SPI1_ERROR_POS) |
92 ((CONFIG_IRQ_RSI_INT0 - 7) << IRQ_RSI_INT0_POS) |
93 ((CONFIG_IRQ_RSI_INT1 - 7) << IRQ_RSI_INT1_POS) |
94 ((CONFIG_IRQ_PWM_TRIP - 7) << IRQ_PWM_TRIP_POS) |
95 ((CONFIG_IRQ_PWM_SYNC - 7) << IRQ_PWM_SYNC_POS) |
96 ((CONFIG_IRQ_PTP_STAT - 7) << IRQ_PTP_STAT_POS));
97
98 SSYNC();
99}
diff --git a/arch/blackfin/mach-common/dpmc_modes.S b/arch/blackfin/mach-common/dpmc_modes.S
index 21f61605f1f3..4da50bcd9300 100644
--- a/arch/blackfin/mach-common/dpmc_modes.S
+++ b/arch/blackfin/mach-common/dpmc_modes.S
@@ -248,7 +248,7 @@ ENDPROC(_unset_dram_srfs)
248 248
249ENTRY(_set_sic_iwr) 249ENTRY(_set_sic_iwr)
250#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) || \ 250#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) || \
251 defined(CONFIG_BF538) || defined(CONFIG_BF539) 251 defined(CONFIG_BF538) || defined(CONFIG_BF539) || defined(CONFIG_BF51x)
252 P0.H = hi(SIC_IWR0); 252 P0.H = hi(SIC_IWR0);
253 P0.L = lo(SIC_IWR0); 253 P0.L = lo(SIC_IWR0);
254 P1.H = hi(SIC_IWR1); 254 P1.H = hi(SIC_IWR1);
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index 5ae507f59885..c32fa695f8cc 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -104,7 +104,8 @@ static void __init search_IAR(void)
104 for (irqn = 0; irqn < NR_PERI_INTS; irqn++) { 104 for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
105 int iar_shift = (irqn & 7) * 4; 105 int iar_shift = (irqn & 7) * 4;
106 if (ivg == (0xf & 106 if (ivg == (0xf &
107#if defined(CONFIG_BF52x) || defined(CONFIG_BF538) || defined(CONFIG_BF539) 107#if defined(CONFIG_BF52x) || defined(CONFIG_BF538) \
108 || defined(CONFIG_BF539) || defined(CONFIG_BF51x)
108 bfin_read32((unsigned long *)SIC_IAR0 + 109 bfin_read32((unsigned long *)SIC_IAR0 +
109 ((irqn % 32) >> 3) + ((irqn / 32) * 110 ((irqn % 32) >> 3) + ((irqn / 32) *
110 ((SIC_IAR4 - SIC_IAR0) / 4))) >> iar_shift)) { 111 ((SIC_IAR4 - SIC_IAR0) / 4))) >> iar_shift)) {
@@ -543,7 +544,7 @@ static void bfin_demux_gpio_irq(unsigned int inta_irq,
543 case IRQ_PORTF_INTA: 544 case IRQ_PORTF_INTA:
544 irq = IRQ_PF0; 545 irq = IRQ_PF0;
545 break; 546 break;
546#elif defined(CONFIG_BF52x) 547#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
547 case IRQ_PORTF_INTA: 548 case IRQ_PORTF_INTA:
548 irq = IRQ_PF0; 549 irq = IRQ_PF0;
549 break; 550 break;
@@ -990,7 +991,8 @@ int __init init_arch_irq(void)
990 int irq; 991 int irq;
991 unsigned long ilat = 0; 992 unsigned long ilat = 0;
992 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */ 993 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
993#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) || defined(BF538_FAMILY) 994#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
995 || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
994 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL); 996 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
995 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL); 997 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
996# ifdef CONFIG_BF54x 998# ifdef CONFIG_BF54x
@@ -1035,7 +1037,7 @@ int __init init_arch_irq(void)
1035 case IRQ_PINT1: 1037 case IRQ_PINT1:
1036 case IRQ_PINT2: 1038 case IRQ_PINT2:
1037 case IRQ_PINT3: 1039 case IRQ_PINT3:
1038#elif defined(CONFIG_BF52x) 1040#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
1039 case IRQ_PORTF_INTA: 1041 case IRQ_PORTF_INTA:
1040 case IRQ_PORTG_INTA: 1042 case IRQ_PORTG_INTA:
1041 case IRQ_PORTH_INTA: 1043 case IRQ_PORTH_INTA:
@@ -1094,10 +1096,11 @@ int __init init_arch_irq(void)
1094 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 | 1096 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1095 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; 1097 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1096 1098
1097#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) || defined(BF538_FAMILY) 1099#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
1100 || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
1098 bfin_write_SIC_IWR0(IWR_DISABLE_ALL); 1101 bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
1099#if defined(CONFIG_BF52x) 1102#if defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
1100 /* BF52x system reset does not properly reset SIC_IWR1 which 1103 /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which
1101 * will screw up the bootrom as it relies on MDMA0/1 waking it 1104 * will screw up the bootrom as it relies on MDMA0/1 waking it
1102 * up from IDLE instructions. See this report for more info: 1105 * up from IDLE instructions. See this report for more info:
1103 * http://blackfin.uclinux.org/gf/tracker/4323 1106 * http://blackfin.uclinux.org/gf/tracker/4323
@@ -1126,7 +1129,8 @@ void do_irq(int vec, struct pt_regs *fp)
1126 } else { 1129 } else {
1127 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst; 1130 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1128 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop; 1131 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
1129#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) || defined(BF538_FAMILY) 1132#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
1133 || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
1130 unsigned long sic_status[3]; 1134 unsigned long sic_status[3];
1131 1135
1132 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0(); 1136 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c
index f774d8aa5b03..ee33a8a988bd 100644
--- a/arch/blackfin/mach-common/pm.c
+++ b/arch/blackfin/mach-common/pm.c
@@ -83,9 +83,9 @@ void bfin_pm_suspend_standby_enter(void)
83 bfin_pm_standby_restore(); 83 bfin_pm_standby_restore();
84 84
85#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) || \ 85#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) || \
86 defined(CONFIG_BF538) || defined(CONFIG_BF539) 86 defined(CONFIG_BF538) || defined(CONFIG_BF539) || defined(CONFIG_BF51x)
87 bfin_write_SIC_IWR0(IWR_DISABLE_ALL); 87 bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
88#if defined(CONFIG_BF52x) 88#if defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
89 /* BF52x system reset does not properly reset SIC_IWR1 which 89 /* BF52x system reset does not properly reset SIC_IWR1 which
90 * will screw up the bootrom as it relies on MDMA0/1 waking it 90 * will screw up the bootrom as it relies on MDMA0/1 waking it
91 * up from IDLE instructions. See this report for more info: 91 * up from IDLE instructions. See this report for more info:
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-14 19:12:04 -0500