diff options
author | Andy Fleming <afleming@freescale.com> | 2008-03-24 11:53:28 -0400 |
---|---|---|
committer | Jeff Garzik <jeff@garzik.org> | 2008-03-26 00:44:47 -0400 |
commit | 2f4489112896770d66dc2960f71174d69ee23004 (patch) | |
tree | d91605f48735267a9c827ad1b7c1cc1324c2992d | |
parent | 99da5003a5b085c12d996da1010e276e9b88672f (diff) |
gianfar: Fix Rx/Tx HW interrupt coalescing counter reset procedure.
- Fix Rx/Tx HW interrupt coalescing counter reset logic. Disabling
is required before resetting the counter.
- Update the Default both Rx and Tx coalescing timer
threshold. Formerly 4 is set which is equal to 1.5 frame at the line
rate of 1GbE interface, and it doesn't match to the coalescing frame
count which is set to 16. Threashold 21 is matched to frame count 16.
Signed-off-by: Dai Haruki <dai.haruki@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
-rw-r--r-- | drivers/net/gianfar.c | 18 | ||||
-rw-r--r-- | drivers/net/gianfar.h | 4 |
2 files changed, 11 insertions, 11 deletions
diff --git a/drivers/net/gianfar.c b/drivers/net/gianfar.c index a59edf7eacdc..601f93e482c6 100644 --- a/drivers/net/gianfar.c +++ b/drivers/net/gianfar.c | |||
@@ -1299,11 +1299,11 @@ static irqreturn_t gfar_transmit(int irq, void *dev_id) | |||
1299 | 1299 | ||
1300 | /* If we are coalescing the interrupts, reset the timer */ | 1300 | /* If we are coalescing the interrupts, reset the timer */ |
1301 | /* Otherwise, clear it */ | 1301 | /* Otherwise, clear it */ |
1302 | if (priv->txcoalescing) | 1302 | if (likely(priv->txcoalescing)) { |
1303 | gfar_write(&priv->regs->txic, 0); | ||
1303 | gfar_write(&priv->regs->txic, | 1304 | gfar_write(&priv->regs->txic, |
1304 | mk_ic_value(priv->txcount, priv->txtime)); | 1305 | mk_ic_value(priv->txcount, priv->txtime)); |
1305 | else | 1306 | } |
1306 | gfar_write(&priv->regs->txic, 0); | ||
1307 | 1307 | ||
1308 | spin_unlock(&priv->txlock); | 1308 | spin_unlock(&priv->txlock); |
1309 | 1309 | ||
@@ -1417,11 +1417,11 @@ irqreturn_t gfar_receive(int irq, void *dev_id) | |||
1417 | 1417 | ||
1418 | /* If we are coalescing interrupts, update the timer */ | 1418 | /* If we are coalescing interrupts, update the timer */ |
1419 | /* Otherwise, clear it */ | 1419 | /* Otherwise, clear it */ |
1420 | if (priv->rxcoalescing) | 1420 | if (likely(priv->rxcoalescing)) { |
1421 | gfar_write(&priv->regs->rxic, 0); | ||
1421 | gfar_write(&priv->regs->rxic, | 1422 | gfar_write(&priv->regs->rxic, |
1422 | mk_ic_value(priv->rxcount, priv->rxtime)); | 1423 | mk_ic_value(priv->rxcount, priv->rxtime)); |
1423 | else | 1424 | } |
1424 | gfar_write(&priv->regs->rxic, 0); | ||
1425 | 1425 | ||
1426 | spin_unlock_irqrestore(&priv->rxlock, flags); | 1426 | spin_unlock_irqrestore(&priv->rxlock, flags); |
1427 | #endif | 1427 | #endif |
@@ -1593,11 +1593,11 @@ static int gfar_poll(struct napi_struct *napi, int budget) | |||
1593 | 1593 | ||
1594 | /* If we are coalescing interrupts, update the timer */ | 1594 | /* If we are coalescing interrupts, update the timer */ |
1595 | /* Otherwise, clear it */ | 1595 | /* Otherwise, clear it */ |
1596 | if (priv->rxcoalescing) | 1596 | if (likely(priv->rxcoalescing)) { |
1597 | gfar_write(&priv->regs->rxic, 0); | ||
1597 | gfar_write(&priv->regs->rxic, | 1598 | gfar_write(&priv->regs->rxic, |
1598 | mk_ic_value(priv->rxcount, priv->rxtime)); | 1599 | mk_ic_value(priv->rxcount, priv->rxtime)); |
1599 | else | 1600 | } |
1600 | gfar_write(&priv->regs->rxic, 0); | ||
1601 | } | 1601 | } |
1602 | 1602 | ||
1603 | return howmany; | 1603 | return howmany; |
diff --git a/drivers/net/gianfar.h b/drivers/net/gianfar.h index fcfa1bd57280..ea8671f87bce 100644 --- a/drivers/net/gianfar.h +++ b/drivers/net/gianfar.h | |||
@@ -124,11 +124,11 @@ extern const char gfar_driver_version[]; | |||
124 | 124 | ||
125 | #define DEFAULT_TX_COALESCE 1 | 125 | #define DEFAULT_TX_COALESCE 1 |
126 | #define DEFAULT_TXCOUNT 16 | 126 | #define DEFAULT_TXCOUNT 16 |
127 | #define DEFAULT_TXTIME 4 | 127 | #define DEFAULT_TXTIME 21 |
128 | 128 | ||
129 | #define DEFAULT_RX_COALESCE 1 | 129 | #define DEFAULT_RX_COALESCE 1 |
130 | #define DEFAULT_RXCOUNT 16 | 130 | #define DEFAULT_RXCOUNT 16 |
131 | #define DEFAULT_RXTIME 4 | 131 | #define DEFAULT_RXTIME 21 |
132 | 132 | ||
133 | #define TBIPA_VALUE 0x1f | 133 | #define TBIPA_VALUE 0x1f |
134 | #define MIIMCFG_INIT_VALUE 0x00000007 | 134 | #define MIIMCFG_INIT_VALUE 0x00000007 |