diff options
author | Marek Szyprowski <m.szyprowski@samsung.com> | 2010-05-20 01:51:09 -0400 |
---|---|---|
committer | Ben Dooks <ben-linux@fluff.org> | 2010-05-20 02:28:43 -0400 |
commit | 23686a07b6222d5c40ea403705325e49d360603e (patch) | |
tree | 0b2ecdde9c30bbcbe43fe40e4a1249de7315775a | |
parent | acc84707d3487735fc666fdeab76185d086428c0 (diff) |
ARM: S5PC100: Add support for gpio interrupt
This patch moves support for gpio interrupts from plat-s5pc1xx to
mach-s5pc100 directory.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
-rw-r--r-- | arch/arm/mach-s5pc100/Makefile | 2 | ||||
-rw-r--r-- | arch/arm/mach-s5pc100/gpiolib.c | 9 | ||||
-rw-r--r-- | arch/arm/mach-s5pc100/irq-gpio.c (renamed from arch/arm/plat-s5pc1xx/irq-gpio.c) | 78 |
3 files changed, 44 insertions, 45 deletions
diff --git a/arch/arm/mach-s5pc100/Makefile b/arch/arm/mach-s5pc100/Makefile index 9b52d2af013f..6e3f57c39c97 100644 --- a/arch/arm/mach-s5pc100/Makefile +++ b/arch/arm/mach-s5pc100/Makefile | |||
@@ -11,7 +11,7 @@ obj- := | |||
11 | 11 | ||
12 | # Core support for S5PC100 system | 12 | # Core support for S5PC100 system |
13 | 13 | ||
14 | obj-$(CONFIG_CPU_S5PC100) += cpu.o init.o clock.o gpiolib.o | 14 | obj-$(CONFIG_CPU_S5PC100) += cpu.o init.o clock.o gpiolib.o irq-gpio.o |
15 | obj-$(CONFIG_CPU_S5PC100) += setup-i2c0.o | 15 | obj-$(CONFIG_CPU_S5PC100) += setup-i2c0.o |
16 | 16 | ||
17 | # Helper and device support | 17 | # Helper and device support |
diff --git a/arch/arm/mach-s5pc100/gpiolib.c b/arch/arm/mach-s5pc100/gpiolib.c index 494a53b10479..88dd913c86d4 100644 --- a/arch/arm/mach-s5pc100/gpiolib.c +++ b/arch/arm/mach-s5pc100/gpiolib.c | |||
@@ -387,7 +387,6 @@ extern void s5pc100_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc) | |||
387 | 387 | ||
388 | static __init void s5pc100_gpiolib_link(struct s3c_gpio_chip *chip) | 388 | static __init void s5pc100_gpiolib_link(struct s3c_gpio_chip *chip) |
389 | { | 389 | { |
390 | #if 0 | ||
391 | /* Interrupt */ | 390 | /* Interrupt */ |
392 | if (chip->config == &gpio_cfg) { | 391 | if (chip->config == &gpio_cfg) { |
393 | int i, irq; | 392 | int i, irq; |
@@ -401,9 +400,9 @@ static __init void s5pc100_gpiolib_link(struct s3c_gpio_chip *chip) | |||
401 | set_irq_handler(irq, handle_level_irq); | 400 | set_irq_handler(irq, handle_level_irq); |
402 | set_irq_flags(irq, IRQF_VALID); | 401 | set_irq_flags(irq, IRQF_VALID); |
403 | } | 402 | } |
404 | } else if (chip->config == &gpio_cfg_eint) | 403 | } else if (chip->config == &gpio_cfg_eint) { |
405 | chip->chip.to_irq = s5pc100_gpiolib_to_eint; | 404 | chip->chip.to_irq = s5pc100_gpiolib_to_eint; |
406 | #endif | 405 | } |
407 | } | 406 | } |
408 | 407 | ||
409 | static __init int s5pc100_gpiolib_init(void) | 408 | static __init int s5pc100_gpiolib_init(void) |
@@ -419,10 +418,10 @@ static __init int s5pc100_gpiolib_init(void) | |||
419 | 418 | ||
420 | samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips, | 419 | samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips, |
421 | ARRAY_SIZE(s5pc100_gpio_chips)); | 420 | ARRAY_SIZE(s5pc100_gpio_chips)); |
422 | #if 0 | 421 | |
423 | /* Interrupt */ | 422 | /* Interrupt */ |
424 | set_irq_chained_handler(IRQ_GPIOINT, s5pc100_irq_gpioint_handler); | 423 | set_irq_chained_handler(IRQ_GPIOINT, s5pc100_irq_gpioint_handler); |
425 | #endif | 424 | |
426 | return 0; | 425 | return 0; |
427 | } | 426 | } |
428 | core_initcall(s5pc100_gpiolib_init); | 427 | core_initcall(s5pc100_gpiolib_init); |
diff --git a/arch/arm/plat-s5pc1xx/irq-gpio.c b/arch/arm/mach-s5pc100/irq-gpio.c index fecca7a679b0..2bf86c18bc73 100644 --- a/arch/arm/plat-s5pc1xx/irq-gpio.c +++ b/arch/arm/mach-s5pc100/irq-gpio.c | |||
@@ -1,9 +1,9 @@ | |||
1 | /* | 1 | /* |
2 | * arch/arm/plat-s5pc1xx/irq-gpio.c | 2 | * arch/arm/mach-s5pc100/irq-gpio.c |
3 | * | 3 | * |
4 | * Copyright (C) 2009 Samsung Electronics | 4 | * Copyright (C) 2009 Samsung Electronics |
5 | * | 5 | * |
6 | * S5PC1XX - Interrupt handling for IRQ_GPIO${group}(x) | 6 | * S5PC100 - Interrupt handling for IRQ_GPIO${group}(x) |
7 | * | 7 | * |
8 | * This program is free software; you can redistribute it and/or modify | 8 | * This program is free software; you can redistribute it and/or modify |
9 | * it under the terms of the GNU General Public License version 2 as | 9 | * it under the terms of the GNU General Public License version 2 as |
@@ -19,7 +19,7 @@ | |||
19 | #include <mach/map.h> | 19 | #include <mach/map.h> |
20 | #include <plat/gpio-cfg.h> | 20 | #include <plat/gpio-cfg.h> |
21 | 21 | ||
22 | #define S5PC1XX_GPIOREG(x) (S5PC1XX_VA_GPIO + (x)) | 22 | #define S5P_GPIOREG(x) (S5P_VA_GPIO + (x)) |
23 | 23 | ||
24 | #define CON_OFFSET 0x700 | 24 | #define CON_OFFSET 0x700 |
25 | #define MASK_OFFSET 0x900 | 25 | #define MASK_OFFSET 0x900 |
@@ -49,7 +49,7 @@ static int group_to_pend_offset(int group) | |||
49 | return group << 2; | 49 | return group << 2; |
50 | } | 50 | } |
51 | 51 | ||
52 | static int s5pc1xx_get_start(unsigned int group) | 52 | static int s5pc100_get_start(unsigned int group) |
53 | { | 53 | { |
54 | switch (group) { | 54 | switch (group) { |
55 | case 0: return S5PC100_GPIO_A0_START; | 55 | case 0: return S5PC100_GPIO_A0_START; |
@@ -80,7 +80,7 @@ static int s5pc1xx_get_start(unsigned int group) | |||
80 | return -EINVAL; | 80 | return -EINVAL; |
81 | } | 81 | } |
82 | 82 | ||
83 | static int s5pc1xx_get_group(unsigned int irq) | 83 | static int s5pc100_get_group(unsigned int irq) |
84 | { | 84 | { |
85 | irq -= S3C_IRQ_GPIO(0); | 85 | irq -= S3C_IRQ_GPIO(0); |
86 | 86 | ||
@@ -134,67 +134,67 @@ static int s5pc1xx_get_group(unsigned int irq) | |||
134 | return -EINVAL; | 134 | return -EINVAL; |
135 | } | 135 | } |
136 | 136 | ||
137 | static int s5pc1xx_get_offset(unsigned int irq) | 137 | static int s5pc100_get_offset(unsigned int irq) |
138 | { | 138 | { |
139 | struct gpio_chip *chip = get_irq_data(irq); | 139 | struct gpio_chip *chip = get_irq_data(irq); |
140 | return irq - S3C_IRQ_GPIO(chip->base); | 140 | return irq - S3C_IRQ_GPIO(chip->base); |
141 | } | 141 | } |
142 | 142 | ||
143 | static void s5pc1xx_gpioint_ack(unsigned int irq) | 143 | static void s5pc100_gpioint_ack(unsigned int irq) |
144 | { | 144 | { |
145 | int group, offset, pend_offset; | 145 | int group, offset, pend_offset; |
146 | unsigned int value; | 146 | unsigned int value; |
147 | 147 | ||
148 | group = s5pc1xx_get_group(irq); | 148 | group = s5pc100_get_group(irq); |
149 | offset = s5pc1xx_get_offset(irq); | 149 | offset = s5pc100_get_offset(irq); |
150 | pend_offset = group_to_pend_offset(group); | 150 | pend_offset = group_to_pend_offset(group); |
151 | 151 | ||
152 | value = __raw_readl(S5PC1XX_GPIOREG(PEND_OFFSET) + pend_offset); | 152 | value = __raw_readl(S5P_GPIOREG(PEND_OFFSET) + pend_offset); |
153 | value |= 1 << offset; | 153 | value |= 1 << offset; |
154 | __raw_writel(value, S5PC1XX_GPIOREG(PEND_OFFSET) + pend_offset); | 154 | __raw_writel(value, S5P_GPIOREG(PEND_OFFSET) + pend_offset); |
155 | } | 155 | } |
156 | 156 | ||
157 | static void s5pc1xx_gpioint_mask(unsigned int irq) | 157 | static void s5pc100_gpioint_mask(unsigned int irq) |
158 | { | 158 | { |
159 | int group, offset, mask_offset; | 159 | int group, offset, mask_offset; |
160 | unsigned int value; | 160 | unsigned int value; |
161 | 161 | ||
162 | group = s5pc1xx_get_group(irq); | 162 | group = s5pc100_get_group(irq); |
163 | offset = s5pc1xx_get_offset(irq); | 163 | offset = s5pc100_get_offset(irq); |
164 | mask_offset = group_to_mask_offset(group); | 164 | mask_offset = group_to_mask_offset(group); |
165 | 165 | ||
166 | value = __raw_readl(S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset); | 166 | value = __raw_readl(S5P_GPIOREG(MASK_OFFSET) + mask_offset); |
167 | value |= 1 << offset; | 167 | value |= 1 << offset; |
168 | __raw_writel(value, S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset); | 168 | __raw_writel(value, S5P_GPIOREG(MASK_OFFSET) + mask_offset); |
169 | } | 169 | } |
170 | 170 | ||
171 | static void s5pc1xx_gpioint_unmask(unsigned int irq) | 171 | static void s5pc100_gpioint_unmask(unsigned int irq) |
172 | { | 172 | { |
173 | int group, offset, mask_offset; | 173 | int group, offset, mask_offset; |
174 | unsigned int value; | 174 | unsigned int value; |
175 | 175 | ||
176 | group = s5pc1xx_get_group(irq); | 176 | group = s5pc100_get_group(irq); |
177 | offset = s5pc1xx_get_offset(irq); | 177 | offset = s5pc100_get_offset(irq); |
178 | mask_offset = group_to_mask_offset(group); | 178 | mask_offset = group_to_mask_offset(group); |
179 | 179 | ||
180 | value = __raw_readl(S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset); | 180 | value = __raw_readl(S5P_GPIOREG(MASK_OFFSET) + mask_offset); |
181 | value &= ~(1 << offset); | 181 | value &= ~(1 << offset); |
182 | __raw_writel(value, S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset); | 182 | __raw_writel(value, S5P_GPIOREG(MASK_OFFSET) + mask_offset); |
183 | } | 183 | } |
184 | 184 | ||
185 | static void s5pc1xx_gpioint_mask_ack(unsigned int irq) | 185 | static void s5pc100_gpioint_mask_ack(unsigned int irq) |
186 | { | 186 | { |
187 | s5pc1xx_gpioint_mask(irq); | 187 | s5pc100_gpioint_mask(irq); |
188 | s5pc1xx_gpioint_ack(irq); | 188 | s5pc100_gpioint_ack(irq); |
189 | } | 189 | } |
190 | 190 | ||
191 | static int s5pc1xx_gpioint_set_type(unsigned int irq, unsigned int type) | 191 | static int s5pc100_gpioint_set_type(unsigned int irq, unsigned int type) |
192 | { | 192 | { |
193 | int group, offset, con_offset; | 193 | int group, offset, con_offset; |
194 | unsigned int value; | 194 | unsigned int value; |
195 | 195 | ||
196 | group = s5pc1xx_get_group(irq); | 196 | group = s5pc100_get_group(irq); |
197 | offset = s5pc1xx_get_offset(irq); | 197 | offset = s5pc100_get_offset(irq); |
198 | con_offset = group_to_con_offset(group); | 198 | con_offset = group_to_con_offset(group); |
199 | 199 | ||
200 | switch (type) { | 200 | switch (type) { |
@@ -221,24 +221,24 @@ static int s5pc1xx_gpioint_set_type(unsigned int irq, unsigned int type) | |||
221 | } | 221 | } |
222 | 222 | ||
223 | 223 | ||
224 | value = __raw_readl(S5PC1XX_GPIOREG(CON_OFFSET) + con_offset); | 224 | value = __raw_readl(S5P_GPIOREG(CON_OFFSET) + con_offset); |
225 | value &= ~(0xf << (offset * 0x4)); | 225 | value &= ~(0xf << (offset * 0x4)); |
226 | value |= (type << (offset * 0x4)); | 226 | value |= (type << (offset * 0x4)); |
227 | __raw_writel(value, S5PC1XX_GPIOREG(CON_OFFSET) + con_offset); | 227 | __raw_writel(value, S5P_GPIOREG(CON_OFFSET) + con_offset); |
228 | 228 | ||
229 | return 0; | 229 | return 0; |
230 | } | 230 | } |
231 | 231 | ||
232 | struct irq_chip s5pc1xx_gpioint = { | 232 | struct irq_chip s5pc100_gpioint = { |
233 | .name = "GPIO", | 233 | .name = "GPIO", |
234 | .ack = s5pc1xx_gpioint_ack, | 234 | .ack = s5pc100_gpioint_ack, |
235 | .mask = s5pc1xx_gpioint_mask, | 235 | .mask = s5pc100_gpioint_mask, |
236 | .mask_ack = s5pc1xx_gpioint_mask_ack, | 236 | .mask_ack = s5pc100_gpioint_mask_ack, |
237 | .unmask = s5pc1xx_gpioint_unmask, | 237 | .unmask = s5pc100_gpioint_unmask, |
238 | .set_type = s5pc1xx_gpioint_set_type, | 238 | .set_type = s5pc100_gpioint_set_type, |
239 | }; | 239 | }; |
240 | 240 | ||
241 | void s5pc1xx_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc) | 241 | void s5pc100_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc) |
242 | { | 242 | { |
243 | int group, offset, pend_offset, mask_offset; | 243 | int group, offset, pend_offset, mask_offset; |
244 | int real_irq, group_end; | 244 | int real_irq, group_end; |
@@ -248,17 +248,17 @@ void s5pc1xx_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc) | |||
248 | 248 | ||
249 | for (group = 0; group < group_end; group++) { | 249 | for (group = 0; group < group_end; group++) { |
250 | pend_offset = group_to_pend_offset(group); | 250 | pend_offset = group_to_pend_offset(group); |
251 | pend = __raw_readl(S5PC1XX_GPIOREG(PEND_OFFSET) + pend_offset); | 251 | pend = __raw_readl(S5P_GPIOREG(PEND_OFFSET) + pend_offset); |
252 | if (!pend) | 252 | if (!pend) |
253 | continue; | 253 | continue; |
254 | 254 | ||
255 | mask_offset = group_to_mask_offset(group); | 255 | mask_offset = group_to_mask_offset(group); |
256 | mask = __raw_readl(S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset); | 256 | mask = __raw_readl(S5P_GPIOREG(MASK_OFFSET) + mask_offset); |
257 | pend &= ~mask; | 257 | pend &= ~mask; |
258 | 258 | ||
259 | for (offset = 0; offset < 8; offset++) { | 259 | for (offset = 0; offset < 8; offset++) { |
260 | if (pend & (1 << offset)) { | 260 | if (pend & (1 << offset)) { |
261 | real_irq = s5pc1xx_get_start(group) + offset; | 261 | real_irq = s5pc100_get_start(group) + offset; |
262 | generic_handle_irq(S3C_IRQ_GPIO(real_irq)); | 262 | generic_handle_irq(S3C_IRQ_GPIO(real_irq)); |
263 | } | 263 | } |
264 | } | 264 | } |