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authorRalf Baechle <ralf@linux-mips.org>2005-09-03 18:56:06 -0400
committerLinus Torvalds <torvalds@evo.osdl.org>2005-09-05 03:06:02 -0400
commit0fdda107e10133583f31c72326959555bfb61042 (patch)
tree0173750da11cd60fbe9b2062349ad473401bfe4c
parent8bb670c1407c2a4890810fd3e348dac1b89e669e (diff)
[PATCH] mips: remove VR4181 support
There seem to be no more users or interest in the NEC Osprey evaluation system for the NEC VR4181 SOC which is an old part anyway, so remove the code. More information on the Osprey can be found at http://www.linux-mips.org/wiki/Osprey. Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat
-rw-r--r--arch/mips/configs/osprey_defconfig618
-rw-r--r--arch/mips/vr4181/common/Makefile7
-rw-r--r--arch/mips/vr4181/common/int_handler.S206
-rw-r--r--arch/mips/vr4181/common/irq.c239
-rw-r--r--arch/mips/vr4181/common/serial.c51
-rw-r--r--arch/mips/vr4181/common/time.c145
-rw-r--r--arch/mips/vr4181/osprey/Makefile7
-rw-r--r--arch/mips/vr4181/osprey/dbg_io.c136
-rw-r--r--arch/mips/vr4181/osprey/prom.c49
-rw-r--r--arch/mips/vr4181/osprey/reset.c40
-rw-r--r--arch/mips/vr4181/osprey/setup.c68
-rw-r--r--include/asm-mips/vr4181/irq.h122
-rw-r--r--include/asm-mips/vr4181/vr4181.h413
13 files changed, 0 insertions, 2101 deletions
diff --git a/arch/mips/configs/osprey_defconfig b/arch/mips/configs/osprey_defconfig
deleted file mode 100644
index 989cb9e7ae83..000000000000
--- a/arch/mips/configs/osprey_defconfig
+++ /dev/null
@@ -1,618 +0,0 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.11-rc2
4# Wed Jan 26 02:49:08 2005
5#
6CONFIG_MIPS=y
7# CONFIG_MIPS64 is not set
8# CONFIG_64BIT is not set
9CONFIG_MIPS32=y
10
11#
12# Code maturity level options
13#
14CONFIG_EXPERIMENTAL=y
15CONFIG_CLEAN_COMPILE=y
16CONFIG_BROKEN_ON_SMP=y
17
18#
19# General setup
20#
21CONFIG_LOCALVERSION=""
22CONFIG_SWAP=y
23CONFIG_SYSVIPC=y
24# CONFIG_POSIX_MQUEUE is not set
25# CONFIG_BSD_PROCESS_ACCT is not set
26CONFIG_SYSCTL=y
27# CONFIG_AUDIT is not set
28CONFIG_LOG_BUF_SHIFT=14
29# CONFIG_HOTPLUG is not set
30CONFIG_KOBJECT_UEVENT=y
31# CONFIG_IKCONFIG is not set
32CONFIG_EMBEDDED=y
33CONFIG_KALLSYMS=y
34# CONFIG_KALLSYMS_EXTRA_PASS is not set
35CONFIG_FUTEX=y
36CONFIG_EPOLL=y
37# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
38CONFIG_SHMEM=y
39CONFIG_CC_ALIGN_FUNCTIONS=0
40CONFIG_CC_ALIGN_LABELS=0
41CONFIG_CC_ALIGN_LOOPS=0
42CONFIG_CC_ALIGN_JUMPS=0
43# CONFIG_TINY_SHMEM is not set
44
45#
46# Loadable module support
47#
48CONFIG_MODULES=y
49CONFIG_MODULE_UNLOAD=y
50# CONFIG_MODULE_FORCE_UNLOAD is not set
51CONFIG_OBSOLETE_MODPARM=y
52CONFIG_MODVERSIONS=y
53CONFIG_MODULE_SRCVERSION_ALL=y
54CONFIG_KMOD=y
55
56#
57# Machine selection
58#
59# CONFIG_MACH_JAZZ is not set
60# CONFIG_MACH_VR41XX is not set
61# CONFIG_TOSHIBA_JMR3927 is not set
62# CONFIG_MIPS_COBALT is not set
63# CONFIG_MACH_DECSTATION is not set
64# CONFIG_MIPS_EV64120 is not set
65# CONFIG_MIPS_EV96100 is not set
66# CONFIG_MIPS_IVR is not set
67# CONFIG_LASAT is not set
68# CONFIG_MIPS_ITE8172 is not set
69# CONFIG_MIPS_ATLAS is not set
70# CONFIG_MIPS_MALTA is not set
71# CONFIG_MIPS_SEAD is not set
72# CONFIG_MOMENCO_OCELOT is not set
73# CONFIG_MOMENCO_OCELOT_G is not set
74# CONFIG_MOMENCO_OCELOT_C is not set
75# CONFIG_MOMENCO_OCELOT_3 is not set
76# CONFIG_MOMENCO_JAGUAR_ATX is not set
77# CONFIG_PMC_YOSEMITE is not set
78# CONFIG_DDB5074 is not set
79# CONFIG_DDB5476 is not set
80# CONFIG_DDB5477 is not set
81CONFIG_NEC_OSPREY=y
82# CONFIG_SGI_IP22 is not set
83# CONFIG_SOC_AU1X00 is not set
84# CONFIG_SIBYTE_SB1xxx_SOC is not set
85# CONFIG_SNI_RM200_PCI is not set
86# CONFIG_TOSHIBA_RBTX4927 is not set
87CONFIG_RWSEM_GENERIC_SPINLOCK=y
88CONFIG_GENERIC_CALIBRATE_DELAY=y
89CONFIG_HAVE_DEC_LOCK=y
90CONFIG_DMA_NONCOHERENT=y
91CONFIG_CPU_LITTLE_ENDIAN=y
92CONFIG_IRQ_CPU=y
93CONFIG_MIPS_L1_CACHE_SHIFT=5
94CONFIG_VR4181=y
95
96#
97# CPU selection
98#
99# CONFIG_CPU_MIPS32 is not set
100# CONFIG_CPU_MIPS64 is not set
101# CONFIG_CPU_R3000 is not set
102# CONFIG_CPU_TX39XX is not set
103CONFIG_CPU_VR41XX=y
104# CONFIG_CPU_R4300 is not set
105# CONFIG_CPU_R4X00 is not set
106# CONFIG_CPU_TX49XX is not set
107# CONFIG_CPU_R5000 is not set
108# CONFIG_CPU_R5432 is not set
109# CONFIG_CPU_R6000 is not set
110# CONFIG_CPU_NEVADA is not set
111# CONFIG_CPU_R8000 is not set
112# CONFIG_CPU_R10000 is not set
113# CONFIG_CPU_RM7000 is not set
114# CONFIG_CPU_RM9000 is not set
115# CONFIG_CPU_SB1 is not set
116CONFIG_PAGE_SIZE_4KB=y
117# CONFIG_PAGE_SIZE_8KB is not set
118# CONFIG_PAGE_SIZE_16KB is not set
119# CONFIG_PAGE_SIZE_64KB is not set
120# CONFIG_CPU_ADVANCED is not set
121CONFIG_CPU_HAS_SYNC=y
122# CONFIG_PREEMPT is not set
123
124#
125# Bus options (PCI, PCMCIA, EISA, ISA, TC)
126#
127CONFIG_MMU=y
128
129#
130# PCCARD (PCMCIA/CardBus) support
131#
132# CONFIG_PCCARD is not set
133
134#
135# PC-card bridges
136#
137
138#
139# PCI Hotplug Support
140#
141
142#
143# Executable file formats
144#
145CONFIG_BINFMT_ELF=y
146# CONFIG_BINFMT_MISC is not set
147CONFIG_TRAD_SIGNALS=y
148
149#
150# Device Drivers
151#
152
153#
154# Generic Driver Options
155#
156CONFIG_STANDALONE=y
157CONFIG_PREVENT_FIRMWARE_BUILD=y
158# CONFIG_FW_LOADER is not set
159
160#
161# Memory Technology Devices (MTD)
162#
163# CONFIG_MTD is not set
164
165#
166# Parallel port support
167#
168# CONFIG_PARPORT is not set
169
170#
171# Plug and Play support
172#
173
174#
175# Block devices
176#
177# CONFIG_BLK_DEV_FD is not set
178# CONFIG_BLK_DEV_COW_COMMON is not set
179# CONFIG_BLK_DEV_LOOP is not set
180# CONFIG_BLK_DEV_NBD is not set
181# CONFIG_BLK_DEV_RAM is not set
182CONFIG_BLK_DEV_RAM_COUNT=16
183CONFIG_INITRAMFS_SOURCE=""
184# CONFIG_LBD is not set
185CONFIG_CDROM_PKTCDVD=m
186CONFIG_CDROM_PKTCDVD_BUFFERS=8
187# CONFIG_CDROM_PKTCDVD_WCACHE is not set
188
189#
190# IO Schedulers
191#
192CONFIG_IOSCHED_NOOP=y
193CONFIG_IOSCHED_AS=y
194CONFIG_IOSCHED_DEADLINE=y
195CONFIG_IOSCHED_CFQ=y
196CONFIG_ATA_OVER_ETH=m
197
198#
199# ATA/ATAPI/MFM/RLL support
200#
201# CONFIG_IDE is not set
202
203#
204# SCSI device support
205#
206# CONFIG_SCSI is not set
207
208#
209# Multi-device support (RAID and LVM)
210#
211# CONFIG_MD is not set
212
213#
214# Fusion MPT device support
215#
216
217#
218# IEEE 1394 (FireWire) support
219#
220
221#
222# I2O device support
223#
224
225#
226# Networking support
227#
228CONFIG_NET=y
229
230#
231# Networking options
232#
233CONFIG_PACKET=y
234# CONFIG_PACKET_MMAP is not set
235CONFIG_NETLINK_DEV=y
236CONFIG_UNIX=y
237CONFIG_NET_KEY=y
238CONFIG_INET=y
239# CONFIG_IP_MULTICAST is not set
240# CONFIG_IP_ADVANCED_ROUTER is not set
241CONFIG_IP_PNP=y
242# CONFIG_IP_PNP_DHCP is not set
243CONFIG_IP_PNP_BOOTP=y
244# CONFIG_IP_PNP_RARP is not set
245# CONFIG_NET_IPIP is not set
246# CONFIG_NET_IPGRE is not set
247# CONFIG_ARPD is not set
248# CONFIG_SYN_COOKIES is not set
249# CONFIG_INET_AH is not set
250# CONFIG_INET_ESP is not set
251# CONFIG_INET_IPCOMP is not set
252CONFIG_INET_TUNNEL=m
253CONFIG_IP_TCPDIAG=m
254# CONFIG_IP_TCPDIAG_IPV6 is not set
255# CONFIG_IPV6 is not set
256# CONFIG_NETFILTER is not set
257CONFIG_XFRM=y
258CONFIG_XFRM_USER=m
259
260#
261# SCTP Configuration (EXPERIMENTAL)
262#
263# CONFIG_IP_SCTP is not set
264# CONFIG_ATM is not set
265# CONFIG_BRIDGE is not set
266# CONFIG_VLAN_8021Q is not set
267# CONFIG_DECNET is not set
268# CONFIG_LLC2 is not set
269# CONFIG_IPX is not set
270# CONFIG_ATALK is not set
271# CONFIG_X25 is not set
272# CONFIG_LAPB is not set
273# CONFIG_NET_DIVERT is not set
274# CONFIG_ECONET is not set
275# CONFIG_WAN_ROUTER is not set
276
277#
278# QoS and/or fair queueing
279#
280# CONFIG_NET_SCHED is not set
281# CONFIG_NET_CLS_ROUTE is not set
282
283#
284# Network testing
285#
286# CONFIG_NET_PKTGEN is not set
287# CONFIG_NETPOLL is not set
288# CONFIG_NET_POLL_CONTROLLER is not set
289# CONFIG_HAMRADIO is not set
290# CONFIG_IRDA is not set
291# CONFIG_BT is not set
292CONFIG_NETDEVICES=y
293# CONFIG_DUMMY is not set
294# CONFIG_BONDING is not set
295# CONFIG_EQUALIZER is not set
296# CONFIG_TUN is not set
297# CONFIG_ETHERTAP is not set
298
299#
300# Ethernet (10 or 100Mbit)
301#
302CONFIG_NET_ETHERNET=y
303# CONFIG_MII is not set
304
305#
306# Ethernet (1000 Mbit)
307#
308
309#
310# Ethernet (10000 Mbit)
311#
312
313#
314# Token Ring devices
315#
316
317#
318# Wireless LAN (non-hamradio)
319#
320# CONFIG_NET_RADIO is not set
321
322#
323# Wan interfaces
324#
325# CONFIG_WAN is not set
326# CONFIG_PPP is not set
327# CONFIG_SLIP is not set
328# CONFIG_SHAPER is not set
329# CONFIG_NETCONSOLE is not set
330
331#
332# ISDN subsystem
333#
334# CONFIG_ISDN is not set
335
336#
337# Telephony Support
338#
339# CONFIG_PHONE is not set
340
341#
342# Input device support
343#
344CONFIG_INPUT=y
345
346#
347# Userland interfaces
348#
349CONFIG_INPUT_MOUSEDEV=y
350CONFIG_INPUT_MOUSEDEV_PSAUX=y
351CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
352CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
353# CONFIG_INPUT_JOYDEV is not set
354# CONFIG_INPUT_TSDEV is not set
355# CONFIG_INPUT_EVDEV is not set
356# CONFIG_INPUT_EVBUG is not set
357
358#
359# Input I/O drivers
360#
361# CONFIG_GAMEPORT is not set
362CONFIG_SOUND_GAMEPORT=y
363CONFIG_SERIO=y
364# CONFIG_SERIO_I8042 is not set
365CONFIG_SERIO_SERPORT=y
366# CONFIG_SERIO_CT82C710 is not set
367# CONFIG_SERIO_LIBPS2 is not set
368CONFIG_SERIO_RAW=m
369
370#
371# Input Device Drivers
372#
373# CONFIG_INPUT_KEYBOARD is not set
374# CONFIG_INPUT_MOUSE is not set
375# CONFIG_INPUT_JOYSTICK is not set
376# CONFIG_INPUT_TOUCHSCREEN is not set
377# CONFIG_INPUT_MISC is not set
378
379#
380# Character devices
381#
382CONFIG_VT=y
383CONFIG_VT_CONSOLE=y
384CONFIG_HW_CONSOLE=y
385# CONFIG_SERIAL_NONSTANDARD is not set
386
387#
388# Serial drivers
389#
390CONFIG_SERIAL_8250=y
391CONFIG_SERIAL_8250_CONSOLE=y
392CONFIG_SERIAL_8250_NR_UARTS=4
393# CONFIG_SERIAL_8250_EXTENDED is not set
394
395#
396# Non-8250 serial port support
397#
398CONFIG_SERIAL_CORE=y
399CONFIG_SERIAL_CORE_CONSOLE=y
400CONFIG_UNIX98_PTYS=y
401CONFIG_LEGACY_PTYS=y
402CONFIG_LEGACY_PTY_COUNT=256
403
404#
405# IPMI
406#
407# CONFIG_IPMI_HANDLER is not set
408
409#
410# Watchdog Cards
411#
412# CONFIG_WATCHDOG is not set
413# CONFIG_RTC is not set
414# CONFIG_GEN_RTC is not set
415# CONFIG_DTLK is not set
416# CONFIG_R3964 is not set
417
418#
419# Ftape, the floppy tape device driver
420#
421# CONFIG_DRM is not set
422# CONFIG_RAW_DRIVER is not set
423
424#
425# I2C support
426#
427# CONFIG_I2C is not set
428
429#
430# Dallas's 1-wire bus
431#
432# CONFIG_W1 is not set
433
434#
435# Misc devices
436#
437
438#
439# Multimedia devices
440#
441# CONFIG_VIDEO_DEV is not set
442
443#
444# Digital Video Broadcasting Devices
445#
446# CONFIG_DVB is not set
447
448#
449# Graphics support
450#
451# CONFIG_FB is not set
452
453#
454# Console display driver support
455#
456# CONFIG_VGA_CONSOLE is not set
457CONFIG_DUMMY_CONSOLE=y
458# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
459
460#
461# Sound
462#
463# CONFIG_SOUND is not set
464
465#
466# USB support
467#
468# CONFIG_USB_ARCH_HAS_HCD is not set
469# CONFIG_USB_ARCH_HAS_OHCI is not set
470
471#
472# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
473#
474
475#
476# USB Gadget Support
477#
478# CONFIG_USB_GADGET is not set
479
480#
481# MMC/SD Card support
482#
483# CONFIG_MMC is not set
484
485#
486# InfiniBand support
487#
488# CONFIG_INFINIBAND is not set
489
490#
491# File systems
492#
493CONFIG_EXT2_FS=y
494# CONFIG_EXT2_FS_XATTR is not set
495# CONFIG_EXT3_FS is not set
496# CONFIG_JBD is not set
497# CONFIG_REISERFS_FS is not set
498# CONFIG_JFS_FS is not set
499# CONFIG_XFS_FS is not set
500# CONFIG_MINIX_FS is not set
501# CONFIG_ROMFS_FS is not set
502# CONFIG_QUOTA is not set
503CONFIG_DNOTIFY=y
504# CONFIG_AUTOFS_FS is not set
505# CONFIG_AUTOFS4_FS is not set
506
507#
508# CD-ROM/DVD Filesystems
509#
510# CONFIG_ISO9660_FS is not set
511# CONFIG_UDF_FS is not set
512
513#
514# DOS/FAT/NT Filesystems
515#
516# CONFIG_MSDOS_FS is not set
517# CONFIG_VFAT_FS is not set
518# CONFIG_NTFS_FS is not set
519
520#
521# Pseudo filesystems
522#
523CONFIG_PROC_FS=y
524CONFIG_PROC_KCORE=y
525CONFIG_SYSFS=y
526# CONFIG_DEVFS_FS is not set
527CONFIG_DEVPTS_FS_XATTR=y
528CONFIG_DEVPTS_FS_SECURITY=y
529# CONFIG_TMPFS is not set
530# CONFIG_HUGETLB_PAGE is not set
531CONFIG_RAMFS=y
532
533#
534# Miscellaneous filesystems
535#
536# CONFIG_ADFS_FS is not set
537# CONFIG_AFFS_FS is not set
538# CONFIG_HFS_FS is not set
539# CONFIG_HFSPLUS_FS is not set
540# CONFIG_BEFS_FS is not set
541# CONFIG_BFS_FS is not set
542# CONFIG_EFS_FS is not set
543# CONFIG_CRAMFS is not set
544# CONFIG_VXFS_FS is not set
545# CONFIG_HPFS_FS is not set
546# CONFIG_QNX4FS_FS is not set
547# CONFIG_SYSV_FS is not set
548# CONFIG_UFS_FS is not set
549
550#
551# Network File Systems
552#
553CONFIG_NFS_FS=y
554# CONFIG_NFS_V3 is not set
555# CONFIG_NFS_V4 is not set
556# CONFIG_NFS_DIRECTIO is not set
557CONFIG_NFSD=y
558# CONFIG_NFSD_V3 is not set
559# CONFIG_NFSD_TCP is not set
560CONFIG_ROOT_NFS=y
561CONFIG_LOCKD=y
562CONFIG_EXPORTFS=y
563CONFIG_SUNRPC=y
564# CONFIG_RPCSEC_GSS_KRB5 is not set
565# CONFIG_RPCSEC_GSS_SPKM3 is not set
566# CONFIG_SMB_FS is not set
567# CONFIG_CIFS is not set
568# CONFIG_NCP_FS is not set
569# CONFIG_CODA_FS is not set
570# CONFIG_AFS_FS is not set
571
572#
573# Partition Types
574#
575# CONFIG_PARTITION_ADVANCED is not set
576CONFIG_MSDOS_PARTITION=y
577
578#
579# Native Language Support
580#
581# CONFIG_NLS is not set
582
583#
584# Profiling support
585#
586# CONFIG_PROFILING is not set
587
588#
589# Kernel hacking
590#
591# CONFIG_DEBUG_KERNEL is not set
592CONFIG_CROSSCOMPILE=y
593CONFIG_CMDLINE="ip=bootp ether=46,0x03fe0300,eth0"
594
595#
596# Security options
597#
598CONFIG_KEYS=y
599CONFIG_KEYS_DEBUG_PROC_KEYS=y
600# CONFIG_SECURITY is not set
601
602#
603# Cryptographic options
604#
605# CONFIG_CRYPTO is not set
606
607#
608# Hardware crypto devices
609#
610
611#
612# Library routines
613#
614# CONFIG_CRC_CCITT is not set
615# CONFIG_CRC32 is not set
616CONFIG_LIBCRC32C=m
617CONFIG_GENERIC_HARDIRQS=y
618CONFIG_GENERIC_IRQ_PROBE=y
diff --git a/arch/mips/vr4181/common/Makefile b/arch/mips/vr4181/common/Makefile
deleted file mode 100644
index f7587ca64ead..000000000000
--- a/arch/mips/vr4181/common/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
1#
2# Makefile for common code of NEC vr4181 based boards
3#
4
5obj-y := irq.o int_handler.o serial.o time.o
6
7EXTRA_AFLAGS := $(CFLAGS)
diff --git a/arch/mips/vr4181/common/int_handler.S b/arch/mips/vr4181/common/int_handler.S
deleted file mode 100644
index 2c041b8ee52b..000000000000
--- a/arch/mips/vr4181/common/int_handler.S
+++ /dev/null
@@ -1,206 +0,0 @@
1/*
2 * arch/mips/vr4181/common/int_handler.S
3 *
4 * Adapted to the VR4181 and almost entirely rewritten:
5 * Copyright (C) 1999 Bradley D. LaRonde and Michael Klar
6 *
7 * Clean up to conform to the new IRQ
8 * Copyright (C) 2001 MontaVista Software Inc.
9 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 *
15 */
16
17#include <asm/asm.h>
18#include <asm/regdef.h>
19#include <asm/mipsregs.h>
20#include <asm/stackframe.h>
21
22#include <asm/vr4181/vr4181.h>
23
24/*
25 * [jsun]
26 * See include/asm/vr4181/irq.h for IRQ assignment and strategy.
27 */
28
29 .text
30 .set noreorder
31
32 .align 5
33 NESTED(vr4181_handle_irq, PT_SIZE, ra)
34
35 .set noat
36 SAVE_ALL
37 CLI
38
39 .set at
40 .set noreorder
41
42 mfc0 t0, CP0_CAUSE
43 mfc0 t2, CP0_STATUS
44
45 and t0, t2
46
47 /* we check IP3 first; it happens most frequently */
48 andi t1, t0, STATUSF_IP3
49 bnez t1, ll_cpu_ip3
50 andi t1, t0, STATUSF_IP2
51 bnez t1, ll_cpu_ip2
52 andi t1, t0, STATUSF_IP7 /* cpu timer */
53 bnez t1, ll_cputimer_irq
54 andi t1, t0, STATUSF_IP4
55 bnez t1, ll_cpu_ip4
56 andi t1, t0, STATUSF_IP5
57 bnez t1, ll_cpu_ip5
58 andi t1, t0, STATUSF_IP6
59 bnez t1, ll_cpu_ip6
60 andi t1, t0, STATUSF_IP0 /* software int 0 */
61 bnez t1, ll_cpu_ip0
62 andi t1, t0, STATUSF_IP1 /* software int 1 */
63 bnez t1, ll_cpu_ip1
64 nop
65
66 .set reorder
67do_spurious:
68 j spurious_interrupt
69
70/*
71 * regular CPU irqs
72 */
73ll_cputimer_irq:
74 li a0, VR4181_IRQ_TIMER
75 move a1, sp
76 jal do_IRQ
77 j ret_from_irq
78
79
80ll_cpu_ip0:
81 li a0, VR4181_IRQ_SW1
82 move a1, sp
83 jal do_IRQ
84 j ret_from_irq
85
86ll_cpu_ip1:
87 li a0, VR4181_IRQ_SW2
88 move a1, sp
89 jal do_IRQ
90 j ret_from_irq
91
92ll_cpu_ip3:
93 li a0, VR4181_IRQ_INT1
94 move a1, sp
95 jal do_IRQ
96 j ret_from_irq
97
98ll_cpu_ip4:
99 li a0, VR4181_IRQ_INT2
100 move a1, sp
101 jal do_IRQ
102 j ret_from_irq
103
104ll_cpu_ip5:
105 li a0, VR4181_IRQ_INT3
106 move a1, sp
107 jal do_IRQ
108 j ret_from_irq
109
110ll_cpu_ip6:
111 li a0, VR4181_IRQ_INT4
112 move a1, sp
113 jal do_IRQ
114 j ret_from_irq
115
116/*
117 * One of the sys irq has happend.
118 *
119 * In the interest of speed, we first determine in the following order
120 * which 16-irq block have pending interrupts:
121 * sysint1 (16 sources, including cascading intrs from GPIO)
122 * sysint2
123 * gpio (16 intr sources)
124 *
125 * Then we do binary search to find the exact interrupt source.
126 */
127ll_cpu_ip2:
128
129 lui t3,%hi(VR4181_SYSINT1REG)
130 lhu t0,%lo(VR4181_SYSINT1REG)(t3)
131 lhu t2,%lo(VR4181_MSYSINT1REG)(t3)
132 and t0, 0xfffb /* hack - remove RTC Long 1 intr */
133 and t0, t2
134 beqz t0, check_sysint2
135
136 /* check for GPIO interrupts */
137 andi t1, t0, 0x0100
138 bnez t1, check_gpio_int
139
140 /* so we have an interrupt in sysint1 which is not gpio int */
141 li a0, VR4181_SYS_IRQ_BASE - 1
142 j check_16
143
144check_sysint2:
145
146 lhu t0,%lo(VR4181_SYSINT2REG)(t3)
147 lhu t2,%lo(VR4181_MSYSINT2REG)(t3)
148 and t0, 0xfffe /* hack - remove RTC Long 2 intr */
149 and t0, t2
150 li a0, VR4181_SYS_IRQ_BASE + 16 - 1
151 j check_16
152
153check_gpio_int:
154 lui t3,%hi(VR4181_GPINTMSK)
155 lhu t0,%lo(VR4181_GPINTMSK)(t3)
156 lhu t2,%lo(VR4181_GPINTSTAT)(t3)
157 xori t0, 0xffff /* why? reverse logic? */
158 and t0, t2
159 li a0, VR4181_GPIO_IRQ_BASE - 1
160 j check_16
161
162/*
163 * When we reach check_16, we have 16-bit status in t0 and base irq number
164 * in a0.
165 */
166check_16:
167 andi t1, t0, 0xff
168 bnez t1, check_8
169
170 srl t0, 8
171 addi a0, 8
172 j check_8
173
174/*
175 * When we reach check_8, we have 8-bit status in t0 and base irq number
176 * in a0.
177 */
178check_8:
179 andi t1, t0, 0xf
180 bnez t1, check_4
181
182 srl t0, 4
183 addi a0, 4
184 j check_4
185
186/*
187 * When we reach check_4, we have 4-bit status in t0 and base irq number
188 * in a0.
189 */
190check_4:
191 andi t0, t0, 0xf
192 beqz t0, do_spurious
193
194loop:
195 andi t2, t0, 0x1
196 srl t0, 1
197 addi a0, 1
198 beqz t2, loop
199
200found_it:
201 move a1, sp
202 jal do_IRQ
203
204 j ret_from_irq
205
206 END(vr4181_handle_irq)
diff --git a/arch/mips/vr4181/common/irq.c b/arch/mips/vr4181/common/irq.c
deleted file mode 100644
index 2cdf77c5cb3e..000000000000
--- a/arch/mips/vr4181/common/irq.c
+++ /dev/null
@@ -1,239 +0,0 @@
1/*
2 * Copyright (C) 2001 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
4 * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
5 *
6 * linux/arch/mips/vr4181/common/irq.c
7 * Completely re-written to use the new irq.c
8 *
9 * Credits to Bradley D. LaRonde and Michael Klar for writing the original
10 * irq.c file which was derived from the common irq.c file.
11 *
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file "COPYING" in the main directory of this archive
14 * for more details.
15 */
16#include <linux/types.h>
17#include <linux/init.h>
18#include <linux/kernel_stat.h>
19#include <linux/signal.h>
20#include <linux/sched.h>
21#include <linux/interrupt.h>
22#include <linux/slab.h>
23#include <linux/random.h>
24
25#include <asm/irq.h>
26#include <asm/mipsregs.h>
27#include <asm/gdb-stub.h>
28
29#include <asm/vr4181/vr4181.h>
30
31/*
32 * Strategy:
33 *
34 * We essentially have three irq controllers, CPU, system, and gpio.
35 *
36 * CPU irq controller is taken care by arch/mips/kernel/irq_cpu.c and
37 * CONFIG_IRQ_CPU config option.
38 *
39 * We here provide sys_irq and gpio_irq controller code.
40 */
41
42static int sys_irq_base;
43static int gpio_irq_base;
44
45/* ---------------------- sys irq ------------------------ */
46static void
47sys_irq_enable(unsigned int irq)
48{
49 irq -= sys_irq_base;
50 if (irq < 16) {
51 *VR4181_MSYSINT1REG |= (u16)(1 << irq);
52 } else {
53 irq -= 16;
54 *VR4181_MSYSINT2REG |= (u16)(1 << irq);
55 }
56}
57
58static void
59sys_irq_disable(unsigned int irq)
60{
61 irq -= sys_irq_base;
62 if (irq < 16) {
63 *VR4181_MSYSINT1REG &= ~((u16)(1 << irq));
64 } else {
65 irq -= 16;
66 *VR4181_MSYSINT2REG &= ~((u16)(1 << irq));
67 }
68
69}
70
71static unsigned int
72sys_irq_startup(unsigned int irq)
73{
74 sys_irq_enable(irq);
75 return 0;
76}
77
78#define sys_irq_shutdown sys_irq_disable
79#define sys_irq_ack sys_irq_disable
80
81static void
82sys_irq_end(unsigned int irq)
83{
84 if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
85 sys_irq_enable(irq);
86}
87
88static hw_irq_controller sys_irq_controller = {
89 "vr4181_sys_irq",
90 sys_irq_startup,
91 sys_irq_shutdown,
92 sys_irq_enable,
93 sys_irq_disable,
94 sys_irq_ack,
95 sys_irq_end,
96 NULL /* no affinity stuff for UP */
97};
98
99/* ---------------------- gpio irq ------------------------ */
100/* gpio irq lines use reverse logic */
101static void
102gpio_irq_enable(unsigned int irq)
103{
104 irq -= gpio_irq_base;
105 *VR4181_GPINTMSK &= ~((u16)(1 << irq));
106}
107
108static void
109gpio_irq_disable(unsigned int irq)
110{
111 irq -= gpio_irq_base;
112 *VR4181_GPINTMSK |= (u16)(1 << irq);
113}
114
115static unsigned int
116gpio_irq_startup(unsigned int irq)
117{
118 gpio_irq_enable(irq);
119
120 irq -= gpio_irq_base;
121 *VR4181_GPINTEN |= (u16)(1 << irq );
122
123 return 0;
124}
125
126static void
127gpio_irq_shutdown(unsigned int irq)
128{
129 gpio_irq_disable(irq);
130
131 irq -= gpio_irq_base;
132 *VR4181_GPINTEN &= ~((u16)(1 << irq ));
133}
134
135static void
136gpio_irq_ack(unsigned int irq)
137{
138 u16 irqtype;
139 u16 irqshift;
140
141 gpio_irq_disable(irq);
142
143 /* we clear interrupt if it is edge triggered */
144 irq -= gpio_irq_base;
145 if (irq < 8) {
146 irqtype = *VR4181_GPINTTYPL;
147 irqshift = 2 << (irq*2);
148 } else {
149 irqtype = *VR4181_GPINTTYPH;
150 irqshift = 2 << ((irq-8)*2);
151 }
152 if ( ! (irqtype & irqshift) ) {
153 *VR4181_GPINTSTAT = (u16) (1 << irq);
154 }
155}
156
157static void
158gpio_irq_end(unsigned int irq)
159{
160 if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
161 gpio_irq_enable(irq);
162}
163
164static hw_irq_controller gpio_irq_controller = {
165 "vr4181_gpio_irq",
166 gpio_irq_startup,
167 gpio_irq_shutdown,
168 gpio_irq_enable,
169 gpio_irq_disable,
170 gpio_irq_ack,
171 gpio_irq_end,
172 NULL /* no affinity stuff for UP */
173};
174
175/* --------------------- IRQ init stuff ---------------------- */
176
177extern asmlinkage void vr4181_handle_irq(void);
178extern void breakpoint(void);
179extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
180extern void mips_cpu_irq_init(u32 irq_base);
181
182static struct irqaction cascade =
183 { no_action, SA_INTERRUPT, CPU_MASK_NONE, "cascade", NULL, NULL };
184static struct irqaction reserved =
185 { no_action, SA_INTERRUPT, CPU_MASK_NONE, "cascade", NULL, NULL };
186
187void __init arch_init_irq(void)
188{
189 int i;
190
191 set_except_vector(0, vr4181_handle_irq);
192
193 /* init CPU irqs */
194 mips_cpu_irq_init(VR4181_CPU_IRQ_BASE);
195
196 /* init sys irqs */
197 sys_irq_base = VR4181_SYS_IRQ_BASE;
198 for (i=sys_irq_base; i < sys_irq_base + VR4181_NUM_SYS_IRQ; i++) {
199 irq_desc[i].status = IRQ_DISABLED;
200 irq_desc[i].action = NULL;
201 irq_desc[i].depth = 1;
202 irq_desc[i].handler = &sys_irq_controller;
203 }
204
205 /* init gpio irqs */
206 gpio_irq_base = VR4181_GPIO_IRQ_BASE;
207 for (i=gpio_irq_base; i < gpio_irq_base + VR4181_NUM_GPIO_IRQ; i++) {
208 irq_desc[i].status = IRQ_DISABLED;
209 irq_desc[i].action = NULL;
210 irq_desc[i].depth = 1;
211 irq_desc[i].handler = &gpio_irq_controller;
212 }
213
214 /* Default all ICU IRQs to off ... */
215 *VR4181_MSYSINT1REG = 0;
216 *VR4181_MSYSINT2REG = 0;
217
218 /* We initialize the level 2 ICU registers to all bits disabled. */
219 *VR4181_MPIUINTREG = 0;
220 *VR4181_MAIUINTREG = 0;
221 *VR4181_MKIUINTREG = 0;
222
223 /* disable all GPIO intrs */
224 *VR4181_GPINTMSK = 0xffff;
225
226 /* vector handler. What these do is register the IRQ as non-sharable */
227 setup_irq(VR4181_IRQ_INT0, &cascade);
228 setup_irq(VR4181_IRQ_GIU, &cascade);
229
230 /*
231 * RTC interrupts are interesting. They have two destinations.
232 * One is at sys irq controller, and the other is at CPU IP3 and IP4.
233 * RTC timer is used as system timer.
234 * We enable them here, but timer routine will register later
235 * with CPU IP3/IP4.
236 */
237 setup_irq(VR4181_IRQ_RTCL1, &reserved);
238 setup_irq(VR4181_IRQ_RTCL2, &reserved);
239}
diff --git a/arch/mips/vr4181/common/serial.c b/arch/mips/vr4181/common/serial.c
deleted file mode 100644
index 3f62c62b107f..000000000000
--- a/arch/mips/vr4181/common/serial.c
+++ /dev/null
@@ -1,51 +0,0 @@
1/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
4 *
5 * arch/mips/vr4181/common/serial.c
6 * initialize serial port on vr4181.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15/*
16 * [jsun, 010925]
17 * You need to make sure rs_table has at least one element in
18 * drivers/char/serial.c file. There is no good way to do it right
19 * now. A workaround is to include CONFIG_SERIAL_MANY_PORTS in your
20 * configure file, which would gives you 64 ports and wastes 11K ram.
21 */
22
23#include <linux/types.h>
24#include <linux/kernel.h>
25#include <linux/init.h>
26#include <linux/serial.h>
27
28#include <asm/vr4181/vr4181.h>
29
30void __init vr4181_init_serial(void)
31{
32 struct serial_struct s;
33
34 /* turn on UART clock */
35 *VR4181_CMUCLKMSK |= VR4181_CMUCLKMSK_MSKSIU;
36
37 /* clear memory */
38 memset(&s, 0, sizeof(s));
39
40 s.line = 0; /* we set the first one */
41 s.baud_base = 1152000;
42 s.irq = VR4181_IRQ_SIU;
43 s.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST; /* STD_COM_FLAGS */
44 s.iomem_base = (u8*)VR4181_SIURB;
45 s.iomem_reg_shift = 0;
46 s.io_type = SERIAL_IO_MEM;
47 if (early_serial_setup(&s) != 0) {
48 panic("vr4181_init_serial() failed!");
49 }
50}
51
diff --git a/arch/mips/vr4181/common/time.c b/arch/mips/vr4181/common/time.c
deleted file mode 100644
index 17814076b6f4..000000000000
--- a/arch/mips/vr4181/common/time.c
+++ /dev/null
@@ -1,145 +0,0 @@
1/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: jsun@mvista.com or jsun@junsun.net
4 *
5 * rtc and time ops for vr4181. Part of code is drived from
6 * linux-vr, originally written by Bradley D. LaRonde & Michael Klar.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#include <linux/kernel.h>
16#include <linux/spinlock.h>
17#include <linux/param.h> /* for HZ */
18#include <linux/time.h>
19#include <linux/interrupt.h>
20
21#include <asm/system.h>
22#include <asm/time.h>
23
24#include <asm/vr4181/vr4181.h>
25
26#define COUNTS_PER_JIFFY ((32768 + HZ/2) / HZ)
27
28/*
29 * RTC ops
30 */
31
32DEFINE_SPINLOCK(rtc_lock);
33
34/* per VR41xx docs, bad data can be read if between 2 counts */
35static inline unsigned short
36read_time_reg(volatile unsigned short *reg)
37{
38 unsigned short value;
39 do {
40 value = *reg;
41 barrier();
42 } while (value != *reg);
43 return value;
44}
45
46static unsigned long
47vr4181_rtc_get_time(void)
48{
49 unsigned short regh, regm, regl;
50
51 // why this crazy order, you ask? to guarantee that neither m
52 // nor l wrap before all 3 read
53 do {
54 regm = read_time_reg(VR4181_ETIMEMREG);
55 barrier();
56 regh = read_time_reg(VR4181_ETIMEHREG);
57 barrier();
58 regl = read_time_reg(VR4181_ETIMELREG);
59 } while (regm != read_time_reg(VR4181_ETIMEMREG));
60 return ((regh << 17) | (regm << 1) | (regl >> 15));
61}
62
63static int
64vr4181_rtc_set_time(unsigned long timeval)
65{
66 unsigned short intreg;
67 unsigned long flags;
68
69 spin_lock_irqsave(&rtc_lock, flags);
70 intreg = *VR4181_RTCINTREG & 0x05;
71 barrier();
72 *VR4181_ETIMELREG = timeval << 15;
73 *VR4181_ETIMEMREG = timeval >> 1;
74 *VR4181_ETIMEHREG = timeval >> 17;
75 barrier();
76 // assume that any ints that just triggered are invalid, since the
77 // time value is written non-atomically in 3 separate regs
78 *VR4181_RTCINTREG = 0x05 ^ intreg;
79 spin_unlock_irqrestore(&rtc_lock, flags);
80
81 return 0;
82}
83
84
85/*
86 * timer interrupt routine (wrapper)
87 *
88 * we need our own interrupt routine because we need to clear
89 * RTC1 interrupt.
90 */
91static void
92vr4181_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
93{
94 /* Clear the interrupt. */
95 *VR4181_RTCINTREG = 0x2;
96
97 /* call the generic one */
98 timer_interrupt(irq, dev_id, regs);
99}
100
101
102/*
103 * vr4181_time_init:
104 *
105 * We pick the following choices:
106 * . we use elapsed timer as the RTC. We set some reasonable init data since
107 * it does not persist across reset
108 * . we use RTC1 as the system timer interrupt source.
109 * . we use CPU counter for fast_gettimeoffset and we calivrate the cpu
110 * frequency. In other words, we use calibrate_div64_gettimeoffset().
111 * . we use our own timer interrupt routine which clears the interrupt
112 * and then calls the generic high-level timer interrupt routine.
113 *
114 */
115
116extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
117
118static void
119vr4181_timer_setup(struct irqaction *irq)
120{
121 /* over-write the handler to be our own one */
122 irq->handler = vr4181_timer_interrupt;
123
124 /* sets up the frequency */
125 *VR4181_RTCL1LREG = COUNTS_PER_JIFFY;
126 *VR4181_RTCL1HREG = 0;
127
128 /* and ack any pending ints */
129 *VR4181_RTCINTREG = 0x2;
130
131 /* setup irqaction */
132 setup_irq(VR4181_IRQ_INT1, irq);
133
134}
135
136void
137vr4181_init_time(void)
138{
139 /* setup hookup functions */
140 rtc_get_time = vr4181_rtc_get_time;
141 rtc_set_time = vr4181_rtc_set_time;
142
143 board_timer_setup = vr4181_timer_setup;
144}
145
diff --git a/arch/mips/vr4181/osprey/Makefile b/arch/mips/vr4181/osprey/Makefile
deleted file mode 100644
index 34be05790883..000000000000
--- a/arch/mips/vr4181/osprey/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
1#
2# Makefile for common code of NEC Osprey board
3#
4
5obj-y := setup.o prom.o reset.o
6
7obj-$(CONFIG_KGDB) += dbg_io.o
diff --git a/arch/mips/vr4181/osprey/dbg_io.c b/arch/mips/vr4181/osprey/dbg_io.c
deleted file mode 100644
index 5e8a84072d5b..000000000000
--- a/arch/mips/vr4181/osprey/dbg_io.c
+++ /dev/null
@@ -1,136 +0,0 @@
1/*
2 * kgdb io functions for osprey. We use the serial port on debug board.
3 *
4 * Copyright (C) 2001 MontaVista Software Inc.
5 * Author: jsun@mvista.com or jsun@junsun.net
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13
14/* ======================= CONFIG ======================== */
15
16/* [jsun] we use the second serial port for kdb */
17#define BASE 0xb7fffff0
18#define MAX_BAUD 115200
19
20/* distance in bytes between two serial registers */
21#define REG_OFFSET 1
22
23/*
24 * 0 - kgdb does serial init
25 * 1 - kgdb skip serial init
26 */
27static int remoteDebugInitialized = 1;
28
29/*
30 * the default baud rate *if* kgdb does serial init
31 */
32#define BAUD_DEFAULT UART16550_BAUD_38400
33
34/* ======================= END OF CONFIG ======================== */
35
36typedef unsigned char uint8;
37typedef unsigned int uint32;
38
39#define UART16550_BAUD_2400 2400
40#define UART16550_BAUD_4800 4800
41#define UART16550_BAUD_9600 9600
42#define UART16550_BAUD_19200 19200
43#define UART16550_BAUD_38400 38400
44#define UART16550_BAUD_57600 57600
45#define UART16550_BAUD_115200 115200
46
47#define UART16550_PARITY_NONE 0
48#define UART16550_PARITY_ODD 0x08
49#define UART16550_PARITY_EVEN 0x18
50#define UART16550_PARITY_MARK 0x28
51#define UART16550_PARITY_SPACE 0x38
52
53#define UART16550_DATA_5BIT 0x0
54#define UART16550_DATA_6BIT 0x1
55#define UART16550_DATA_7BIT 0x2
56#define UART16550_DATA_8BIT 0x3
57
58#define UART16550_STOP_1BIT 0x0
59#define UART16550_STOP_2BIT 0x4
60
61/* register offset */
62#define OFS_RCV_BUFFER 0
63#define OFS_TRANS_HOLD 0
64#define OFS_SEND_BUFFER 0
65#define OFS_INTR_ENABLE (1*REG_OFFSET)
66#define OFS_INTR_ID (2*REG_OFFSET)
67#define OFS_DATA_FORMAT (3*REG_OFFSET)
68#define OFS_LINE_CONTROL (3*REG_OFFSET)
69#define OFS_MODEM_CONTROL (4*REG_OFFSET)
70#define OFS_RS232_OUTPUT (4*REG_OFFSET)
71#define OFS_LINE_STATUS (5*REG_OFFSET)
72#define OFS_MODEM_STATUS (6*REG_OFFSET)
73#define OFS_RS232_INPUT (6*REG_OFFSET)
74#define OFS_SCRATCH_PAD (7*REG_OFFSET)
75
76#define OFS_DIVISOR_LSB (0*REG_OFFSET)
77#define OFS_DIVISOR_MSB (1*REG_OFFSET)
78
79
80/* memory-mapped read/write of the port */
81#define UART16550_READ(y) (*((volatile uint8*)(BASE + y)))
82#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z)
83
84void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
85{
86 /* disable interrupts */
87 UART16550_WRITE(OFS_INTR_ENABLE, 0);
88
89 /* set up buad rate */
90 {
91 uint32 divisor;
92
93 /* set DIAB bit */
94 UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
95
96 /* set divisor */
97 divisor = MAX_BAUD / baud;
98 UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
99 UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
100
101 /* clear DIAB bit */
102 UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
103 }
104
105 /* set data format */
106 UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
107}
108
109
110uint8 getDebugChar(void)
111{
112 if (!remoteDebugInitialized) {
113 remoteDebugInitialized = 1;
114 debugInit(BAUD_DEFAULT,
115 UART16550_DATA_8BIT,
116 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
117 }
118
119 while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
120 return UART16550_READ(OFS_RCV_BUFFER);
121}
122
123
124int putDebugChar(uint8 byte)
125{
126 if (!remoteDebugInitialized) {
127 remoteDebugInitialized = 1;
128 debugInit(BAUD_DEFAULT,
129 UART16550_DATA_8BIT,
130 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
131 }
132
133 while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
134 UART16550_WRITE(OFS_SEND_BUFFER, byte);
135 return 1;
136}
diff --git a/arch/mips/vr4181/osprey/prom.c b/arch/mips/vr4181/osprey/prom.c
deleted file mode 100644
index af0d14561619..000000000000
--- a/arch/mips/vr4181/osprey/prom.c
+++ /dev/null
@@ -1,49 +0,0 @@
1/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: jsun@mvista.com or jsun@junsun.net
4 *
5 * arch/mips/vr4181/osprey/prom.c
6 * prom code for osprey.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/string.h>
17#include <linux/mm.h>
18#include <linux/bootmem.h>
19#include <asm/bootinfo.h>
20#include <asm/addrspace.h>
21
22const char *get_system_type(void)
23{
24 return "NEC_Vr41xx Osprey";
25}
26
27/*
28 * [jsun] right now we assume it is the nec debug monitor, which does
29 * not pass any arguments.
30 */
31void __init prom_init(void)
32{
33 // cmdline is now set in default config
34 // strcpy(arcs_cmdline, "ip=bootp ");
35 // strcat(arcs_cmdline, "ether=46,0x03fe0300,eth0 ");
36 // strcpy(arcs_cmdline, "ether=0,0x0300,eth0 "
37 // strcat(arcs_cmdline, "video=vr4181fb:xres:240,yres:320,bpp:8 ");
38
39 mips_machgroup = MACH_GROUP_NEC_VR41XX;
40 mips_machtype = MACH_NEC_OSPREY;
41
42 /* 16MB fixed */
43 add_memory_region(0, 16 << 20, BOOT_MEM_RAM);
44}
45
46unsigned long __init prom_free_prom_memory(void)
47{
48 return 0;
49}
diff --git a/arch/mips/vr4181/osprey/reset.c b/arch/mips/vr4181/osprey/reset.c
deleted file mode 100644
index 036ae83d89d6..000000000000
--- a/arch/mips/vr4181/osprey/reset.c
+++ /dev/null
@@ -1,40 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * Copyright (C) 1997, 2001 Ralf Baechle
8 * Copyright 2001 MontaVista Software Inc.
9 * Author: jsun@mvista.com or jsun@junsun.net
10 */
11#include <linux/sched.h>
12#include <linux/mm.h>
13#include <asm/io.h>
14#include <asm/cacheflush.h>
15#include <asm/processor.h>
16#include <asm/reboot.h>
17#include <asm/system.h>
18
19void nec_osprey_restart(char *command)
20{
21 set_c0_status(ST0_ERL);
22 change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
23 flush_cache_all();
24 write_c0_wired(0);
25 __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
26}
27
28void nec_osprey_halt(void)
29{
30 printk(KERN_NOTICE "\n** You can safely turn off the power\n");
31 while (1)
32 __asm__(".set\tmips3\n\t"
33 "wait\n\t"
34 ".set\tmips0");
35}
36
37void nec_osprey_power_off(void)
38{
39 nec_osprey_halt();
40}
diff --git a/arch/mips/vr4181/osprey/setup.c b/arch/mips/vr4181/osprey/setup.c
deleted file mode 100644
index 2ff7140e7ed7..000000000000
--- a/arch/mips/vr4181/osprey/setup.c
+++ /dev/null
@@ -1,68 +0,0 @@
1/*
2 * linux/arch/mips/vr4181/setup.c
3 *
4 * VR41xx setup routines
5 *
6 * Copyright (C) 1999 Bradley D. LaRonde
7 * Copyright (C) 1999, 2000 Michael Klar
8 *
9 * Copyright 2001 MontaVista Software Inc.
10 * Author: jsun@mvista.com or jsun@junsun.net
11 * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
12 *
13 * This file is subject to the terms and conditions of the GNU General Public
14 * License. See the file "COPYING" in the main directory of this archive
15 * for more details.
16 *
17 */
18
19#include <linux/ide.h>
20#include <linux/init.h>
21#include <linux/delay.h>
22#include <asm/reboot.h>
23#include <asm/vr4181/vr4181.h>
24#include <asm/io.h>
25
26
27extern void nec_osprey_restart(char* c);
28extern void nec_osprey_halt(void);
29extern void nec_osprey_power_off(void);
30
31extern void vr4181_init_serial(void);
32extern void vr4181_init_time(void);
33
34static void __init nec_osprey_setup(void)
35{
36 set_io_port_base(VR4181_PORT_BASE);
37 isa_slot_offset = VR4181_ISAMEM_BASE;
38
39 vr4181_init_serial();
40 vr4181_init_time();
41
42 _machine_restart = nec_osprey_restart;
43 _machine_halt = nec_osprey_halt;
44 _machine_power_off = nec_osprey_power_off;
45
46 /* setup resource limit */
47 ioport_resource.end = 0xffffffff;
48 iomem_resource.end = 0xffffffff;
49
50 /* [jsun] hack */
51 /*
52 printk("[jsun] hack to change external ISA control register, %x -> %x\n",
53 (*VR4181_XISACTL),
54 (*VR4181_XISACTL) | 0x2);
55 *VR4181_XISACTL |= 0x2;
56 */
57
58 // *VR4181_GPHIBSTH = 0x2000;
59 // *VR4181_GPMD0REG = 0x00c0;
60 // *VR4181_GPINTEN = 1<<6;
61
62 /* [jsun] I believe this will get the interrupt type right
63 * for the ether port.
64 */
65 *VR4181_GPINTTYPL = 0x3000;
66}
67
68early_initcall(nec_osprey_setup);
diff --git a/include/asm-mips/vr4181/irq.h b/include/asm-mips/vr4181/irq.h
deleted file mode 100644
index 4bf0ea970ed0..000000000000
--- a/include/asm-mips/vr4181/irq.h
+++ /dev/null
@@ -1,122 +0,0 @@
1/*
2 * Macros for vr4181 IRQ numbers.
3 *
4 * Copyright (C) 2001 MontaVista Software Inc.
5 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13
14/*
15 * Strategy:
16 *
17 * Vr4181 has conceptually three levels of interrupt controllers:
18 * 1. the CPU itself with 8 intr level.
19 * 2. system interrupt controller, cascaded from int0 pin in CPU, 32 intrs
20 * 3. GPIO interrupts : forwarding external interrupts to sys intr controller
21 */
22
23/* decide the irq block assignment */
24#define VR4181_NUM_CPU_IRQ 8
25#define VR4181_NUM_SYS_IRQ 32
26#define VR4181_NUM_GPIO_IRQ 16
27
28#define VR4181_IRQ_BASE 0
29
30#define VR4181_CPU_IRQ_BASE VR4181_IRQ_BASE
31#define VR4181_SYS_IRQ_BASE (VR4181_CPU_IRQ_BASE + VR4181_NUM_CPU_IRQ)
32#define VR4181_GPIO_IRQ_BASE (VR4181_SYS_IRQ_BASE + VR4181_NUM_SYS_IRQ)
33
34/* CPU interrupts */
35
36/*
37 IP0 - Software interrupt
38 IP1 - Software interrupt
39 IP2 - All but battery, high speed modem, and real time clock
40 IP3 - RTC Long1 (system timer)
41 IP4 - RTC Long2
42 IP5 - High Speed Modem (unused on VR4181)
43 IP6 - Unused
44 IP7 - Timer interrupt from CPO_COMPARE
45*/
46
47#define VR4181_IRQ_SW1 (VR4181_CPU_IRQ_BASE + 0)
48#define VR4181_IRQ_SW2 (VR4181_CPU_IRQ_BASE + 1)
49#define VR4181_IRQ_INT0 (VR4181_CPU_IRQ_BASE + 2)
50#define VR4181_IRQ_INT1 (VR4181_CPU_IRQ_BASE + 3)
51#define VR4181_IRQ_INT2 (VR4181_CPU_IRQ_BASE + 4)
52#define VR4181_IRQ_INT3 (VR4181_CPU_IRQ_BASE + 5)
53#define VR4181_IRQ_INT4 (VR4181_CPU_IRQ_BASE + 6)
54#define VR4181_IRQ_TIMER (VR4181_CPU_IRQ_BASE + 7)
55
56
57/* Cascaded from VR4181_IRQ_INT0 (ICU mapped interrupts) */
58
59/*
60 IP2 - same as VR4181_IRQ_INT1
61 IP8 - This is a cascade to GPIO IRQ's. Do not use.
62 IP16 - same as VR4181_IRQ_INT2
63 IP18 - CompactFlash
64*/
65
66#define VR4181_IRQ_BATTERY (VR4181_SYS_IRQ_BASE + 0)
67#define VR4181_IRQ_POWER (VR4181_SYS_IRQ_BASE + 1)
68#define VR4181_IRQ_RTCL1 (VR4181_SYS_IRQ_BASE + 2)
69#define VR4181_IRQ_ETIMER (VR4181_SYS_IRQ_BASE + 3)
70#define VR4181_IRQ_RFU12 (VR4181_SYS_IRQ_BASE + 4)
71#define VR4181_IRQ_PIU (VR4181_SYS_IRQ_BASE + 5)
72#define VR4181_IRQ_AIU (VR4181_SYS_IRQ_BASE + 6)
73#define VR4181_IRQ_KIU (VR4181_SYS_IRQ_BASE + 7)
74#define VR4181_IRQ_GIU (VR4181_SYS_IRQ_BASE + 8)
75#define VR4181_IRQ_SIU (VR4181_SYS_IRQ_BASE + 9)
76#define VR4181_IRQ_RFU18 (VR4181_SYS_IRQ_BASE + 10)
77#define VR4181_IRQ_SOFT (VR4181_SYS_IRQ_BASE + 11)
78#define VR4181_IRQ_RFU20 (VR4181_SYS_IRQ_BASE + 12)
79#define VR4181_IRQ_DOZEPIU (VR4181_SYS_IRQ_BASE + 13)
80#define VR4181_IRQ_RFU22 (VR4181_SYS_IRQ_BASE + 14)
81#define VR4181_IRQ_RFU23 (VR4181_SYS_IRQ_BASE + 15)
82#define VR4181_IRQ_RTCL2 (VR4181_SYS_IRQ_BASE + 16)
83#define VR4181_IRQ_LED (VR4181_SYS_IRQ_BASE + 17)
84#define VR4181_IRQ_ECU (VR4181_SYS_IRQ_BASE + 18)
85#define VR4181_IRQ_CSU (VR4181_SYS_IRQ_BASE + 19)
86#define VR4181_IRQ_USB (VR4181_SYS_IRQ_BASE + 20)
87#define VR4181_IRQ_DMA (VR4181_SYS_IRQ_BASE + 21)
88#define VR4181_IRQ_LCD (VR4181_SYS_IRQ_BASE + 22)
89#define VR4181_IRQ_RFU31 (VR4181_SYS_IRQ_BASE + 23)
90#define VR4181_IRQ_RFU32 (VR4181_SYS_IRQ_BASE + 24)
91#define VR4181_IRQ_RFU33 (VR4181_SYS_IRQ_BASE + 25)
92#define VR4181_IRQ_RFU34 (VR4181_SYS_IRQ_BASE + 26)
93#define VR4181_IRQ_RFU35 (VR4181_SYS_IRQ_BASE + 27)
94#define VR4181_IRQ_RFU36 (VR4181_SYS_IRQ_BASE + 28)
95#define VR4181_IRQ_RFU37 (VR4181_SYS_IRQ_BASE + 29)
96#define VR4181_IRQ_RFU38 (VR4181_SYS_IRQ_BASE + 30)
97#define VR4181_IRQ_RFU39 (VR4181_SYS_IRQ_BASE + 31)
98
99/* Cascaded from VR4181_IRQ_GIU */
100#define VR4181_IRQ_GPIO0 (VR4181_GPIO_IRQ_BASE + 0)
101#define VR4181_IRQ_GPIO1 (VR4181_GPIO_IRQ_BASE + 1)
102#define VR4181_IRQ_GPIO2 (VR4181_GPIO_IRQ_BASE + 2)
103#define VR4181_IRQ_GPIO3 (VR4181_GPIO_IRQ_BASE + 3)
104#define VR4181_IRQ_GPIO4 (VR4181_GPIO_IRQ_BASE + 4)
105#define VR4181_IRQ_GPIO5 (VR4181_GPIO_IRQ_BASE + 5)
106#define VR4181_IRQ_GPIO6 (VR4181_GPIO_IRQ_BASE + 6)
107#define VR4181_IRQ_GPIO7 (VR4181_GPIO_IRQ_BASE + 7)
108#define VR4181_IRQ_GPIO8 (VR4181_GPIO_IRQ_BASE + 8)
109#define VR4181_IRQ_GPIO9 (VR4181_GPIO_IRQ_BASE + 9)
110#define VR4181_IRQ_GPIO10 (VR4181_GPIO_IRQ_BASE + 10)
111#define VR4181_IRQ_GPIO11 (VR4181_GPIO_IRQ_BASE + 11)
112#define VR4181_IRQ_GPIO12 (VR4181_GPIO_IRQ_BASE + 12)
113#define VR4181_IRQ_GPIO13 (VR4181_GPIO_IRQ_BASE + 13)
114#define VR4181_IRQ_GPIO14 (VR4181_GPIO_IRQ_BASE + 14)
115#define VR4181_IRQ_GPIO15 (VR4181_GPIO_IRQ_BASE + 15)
116
117
118// Alternative to above GPIO IRQ defines
119#define VR4181_IRQ_GPIO(pin) ((VR4181_IRQ_GPIO0) + (pin))
120
121#define VR4181_IRQ_MAX (VR4181_IRQ_BASE + VR4181_NUM_CPU_IRQ + \
122 VR4181_NUM_SYS_IRQ + VR4181_NUM_GPIO_IRQ)
diff --git a/include/asm-mips/vr4181/vr4181.h b/include/asm-mips/vr4181/vr4181.h
deleted file mode 100644
index 5c5d60741515..000000000000
--- a/include/asm-mips/vr4181/vr4181.h
+++ /dev/null
@@ -1,413 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1999 by Michael Klar
7 *
8 * Copyright 2001 MontaVista Software Inc.
9 * Author: jsun@mvista.com or jsun@junsun.net
10 *
11 */
12#ifndef __ASM_VR4181_VR4181_H
13#define __ASM_VR4181_VR4181_H
14
15#include <asm/addrspace.h>
16
17#include <asm/vr4181/irq.h>
18
19#ifndef __ASSEMBLY__
20#define __preg8 (volatile unsigned char*)
21#define __preg16 (volatile unsigned short*)
22#define __preg32 (volatile unsigned int*)
23#else
24#define __preg8
25#define __preg16
26#define __preg32
27#endif
28
29// Embedded CPU peripheral registers
30// Note that many of the registers have different physical address for VR4181
31
32// Bus Control Unit (BCU)
33#define VR4181_BCUCNTREG1 __preg16(KSEG1 + 0x0A000000) /* BCU control register 1 (R/W) */
34#define VR4181_CMUCLKMSK __preg16(KSEG1 + 0x0A000004) /* Clock mask register (R/W) */
35#define VR4181_CMUCLKMSK_MSKCSUPCLK 0x0040
36#define VR4181_CMUCLKMSK_MSKAIUPCLK 0x0020
37#define VR4181_CMUCLKMSK_MSKPIUPCLK 0x0010
38#define VR4181_CMUCLKMSK_MSKADUPCLK 0x0008
39#define VR4181_CMUCLKMSK_MSKSIU18M 0x0004
40#define VR4181_CMUCLKMSK_MSKADU18M 0x0002
41#define VR4181_CMUCLKMSK_MSKUSB 0x0001
42#define VR4181_CMUCLKMSK_MSKSIU VR4181_CMUCLKMSK_MSKSIU18M
43#define VR4181_BCUSPEEDREG __preg16(KSEG1 + 0x0A00000C) /* BCU access time parameter (R/W) */
44#define VR4181_BCURFCNTREG __preg16(KSEG1 + 0x0A000010) /* BCU refresh control register (R/W) */
45#define VR4181_REVIDREG __preg16(KSEG1 + 0x0A000014) /* Revision ID register (R) */
46#define VR4181_CLKSPEEDREG __preg16(KSEG1 + 0x0A000018) /* Clock speed register (R) */
47#define VR4181_EDOMCYTREG __preg16(KSEG1 + 0x0A000300) /* Memory cycle timing register (R/W) */
48#define VR4181_MEMCFG_REG __preg16(KSEG1 + 0x0A000304) /* Memory configuration register (R/W) */
49#define VR4181_MODE_REG __preg16(KSEG1 + 0x0A000308) /* SDRAM mode register (R/W) */
50#define VR4181_SDTIMINGREG __preg16(KSEG1 + 0x0A00030C) /* SDRAM timing register (R/W) */
51
52// DMA Control Unit (DCU)
53#define VR4181_MICDEST1REG1 __preg16(KSEG1 + 0x0A000020) /* Microphone destination 1 address register 1 (R/W) */
54#define VR4181_MICDEST1REG2 __preg16(KSEG1 + 0x0A000022) /* Microphone destination 1 address register 2 (R/W) */
55#define VR4181_MICDEST2REG1 __preg16(KSEG1 + 0x0A000024) /* Microphone destination 2 address register 1 (R/W) */
56#define VR4181_MICDEST2REG2 __preg16(KSEG1 + 0x0A000026) /* Microphone destination 2 address register 2 (R/W) */
57#define VR4181_SPKRRC1REG1 __preg16(KSEG1 + 0x0A000028) /* Speaker Source 1 address register 1 (R/W) */
58#define VR4181_SPKRRC1REG2 __preg16(KSEG1 + 0x0A00002A) /* Speaker Source 1 address register 2 (R/W) */
59#define VR4181_SPKRRC2REG1 __preg16(KSEG1 + 0x0A00002C) /* Speaker Source 2 address register 1 (R/W) */
60#define VR4181_SPKRRC2REG2 __preg16(KSEG1 + 0x0A00002E) /* Speaker Source 2 address register 2 (R/W) */
61#define VR4181_DMARSTREG __preg16(KSEG1 + 0x0A000040) /* DMA Reset register (R/W) */
62#define VR4181_AIUDMAMSKREG __preg16(KSEG1 + 0x0A000046) /* Audio DMA mask register (R/W) */
63#define VR4181_USBDMAMSKREG __preg16(KSEG1 + 0x0A000600) /* USB DMA Mask register (R/W) */
64#define VR4181_USBRXS1AREG1 __preg16(KSEG1 + 0x0A000602) /* USB Rx source 1 address register 1 (R/W) */
65#define VR4181_USBRXS1AREG2 __preg16(KSEG1 + 0x0A000604) /* USB Rx source 1 address register 2 (R/W) */
66#define VR4181_USBRXS2AREG1 __preg16(KSEG1 + 0x0A000606) /* USB Rx source 2 address register 1 (R/W) */
67#define VR4181_USBRXS2AREG2 __preg16(KSEG1 + 0x0A000608) /* USB Rx source 2 address register 2 (R/W) */
68#define VR4181_USBTXS1AREG1 __preg16(KSEG1 + 0x0A00060A) /* USB Tx source 1 address register 1 (R/W) */
69#define VR4181_USBTXS1AREG2 __preg16(KSEG1 + 0x0A00060C) /* USB Tx source 1 address register 2 (R/W) */
70#define VR4181_USBTXS2AREG1 __preg16(KSEG1 + 0x0A00060E) /* USB Tx source 2 address register 1 (R/W) */
71#define VR4181_USBTXS2AREG2 __preg16(KSEG1 + 0x0A000610) /* USB Tx source 2 address register 2 (R/W) */
72#define VR4181_USBRXD1AREG1 __preg16(KSEG1 + 0x0A00062A) /* USB Rx destination 1 address register 1 (R/W) */
73#define VR4181_USBRXD1AREG2 __preg16(KSEG1 + 0x0A00062C) /* USB Rx destination 1 address register 2 (R/W) */
74#define VR4181_USBRXD2AREG1 __preg16(KSEG1 + 0x0A00062E) /* USB Rx destination 2 address register 1 (R/W) */
75#define VR4181_USBRXD2AREG2 __preg16(KSEG1 + 0x0A000630) /* USB Rx destination 2 address register 2 (R/W) */
76#define VR4181_USBTXD1AREG1 __preg16(KSEG1 + 0x0A000632) /* USB Tx destination 1 address register 1 (R/W) */
77#define VR4181_USBTXD1AREG2 __preg16(KSEG1 + 0x0A000634) /* USB Tx destination 1 address register 2 (R/W) */
78#define VR4181_USBTXD2AREG1 __preg16(KSEG1 + 0x0A000636) /* USB Tx destination 2 address register 1 (R/W) */
79#define VR4181_USBTXD2AREG2 __preg16(KSEG1 + 0x0A000638) /* USB Tx destination 2 address register 2 (R/W) */
80#define VR4181_RxRCLENREG __preg16(KSEG1 + 0x0A000652) /* USB Rx record length register (R/W) */
81#define VR4181_TxRCLENREG __preg16(KSEG1 + 0x0A000654) /* USB Tx record length register (R/W) */
82#define VR4181_MICRCLENREG __preg16(KSEG1 + 0x0A000658) /* Microphone record length register (R/W) */
83#define VR4181_SPKRCLENREG __preg16(KSEG1 + 0x0A00065A) /* Speaker record length register (R/W) */
84#define VR4181_USBCFGREG __preg16(KSEG1 + 0x0A00065C) /* USB configuration register (R/W) */
85#define VR4181_MICDMACFGREG __preg16(KSEG1 + 0x0A00065E) /* Microphone DMA configuration register (R/W) */
86#define VR4181_SPKDMACFGREG __preg16(KSEG1 + 0x0A000660) /* Speaker DMA configuration register (R/W) */
87#define VR4181_DMAITRQREG __preg16(KSEG1 + 0x0A000662) /* DMA interrupt request register (R/W) */
88#define VR4181_DMACLTREG __preg16(KSEG1 + 0x0A000664) /* DMA control register (R/W) */
89#define VR4181_DMAITMKREG __preg16(KSEG1 + 0x0A000666) /* DMA interrupt mask register (R/W) */
90
91// ISA Bridge
92#define VR4181_ISABRGCTL __preg16(KSEG1 + 0x0B0002C0) /* ISA Bridge Control Register (R/W) */
93#define VR4181_ISABRGSTS __preg16(KSEG1 + 0x0B0002C2) /* ISA Bridge Status Register (R/W) */
94#define VR4181_XISACTL __preg16(KSEG1 + 0x0B0002C4) /* External ISA Control Register (R/W) */
95
96// Clocked Serial Interface (CSI)
97#define VR4181_CSIMODE __preg16(KSEG1 + 0x0B000900) /* CSI Mode Register (R/W) */
98#define VR4181_CSIRXDATA __preg16(KSEG1 + 0x0B000902) /* CSI Receive Data Register (R) */
99#define VR4181_CSITXDATA __preg16(KSEG1 + 0x0B000904) /* CSI Transmit Data Register (R/W) */
100#define VR4181_CSILSTAT __preg16(KSEG1 + 0x0B000906) /* CSI Line Status Register (R/W) */
101#define VR4181_CSIINTMSK __preg16(KSEG1 + 0x0B000908) /* CSI Interrupt Mask Register (R/W) */
102#define VR4181_CSIINTSTAT __preg16(KSEG1 + 0x0B00090a) /* CSI Interrupt Status Register (R/W) */
103#define VR4181_CSITXBLEN __preg16(KSEG1 + 0x0B00090c) /* CSI Transmit Burst Length Register (R/W) */
104#define VR4181_CSIRXBLEN __preg16(KSEG1 + 0x0B00090e) /* CSI Receive Burst Length Register (R/W) */
105
106// Interrupt Control Unit (ICU)
107#define VR4181_SYSINT1REG __preg16(KSEG1 + 0x0A000080) /* Level 1 System interrupt register 1 (R) */
108#define VR4181_MSYSINT1REG __preg16(KSEG1 + 0x0A00008C) /* Level 1 mask system interrupt register 1 (R/W) */
109#define VR4181_NMIREG __preg16(KSEG1 + 0x0A000098) /* NMI register (R/W) */
110#define VR4181_SOFTINTREG __preg16(KSEG1 + 0x0A00009A) /* Software interrupt register (R/W) */
111#define VR4181_SYSINT2REG __preg16(KSEG1 + 0x0A000200) /* Level 1 System interrupt register 2 (R) */
112#define VR4181_MSYSINT2REG __preg16(KSEG1 + 0x0A000206) /* Level 1 mask system interrupt register 2 (R/W) */
113#define VR4181_PIUINTREGro __preg16(KSEG1 + 0x0B000082) /* Level 2 PIU interrupt register (R) */
114#define VR4181_AIUINTREG __preg16(KSEG1 + 0x0B000084) /* Level 2 AIU interrupt register (R) */
115#define VR4181_MPIUINTREG __preg16(KSEG1 + 0x0B00008E) /* Level 2 mask PIU interrupt register (R/W) */
116#define VR4181_MAIUINTREG __preg16(KSEG1 + 0x0B000090) /* Level 2 mask AIU interrupt register (R/W) */
117#define VR4181_MKIUINTREG __preg16(KSEG1 + 0x0B000092) /* Level 2 mask KIU interrupt register (R/W) */
118#define VR4181_KIUINTREG __preg16(KSEG1 + 0x0B000198) /* Level 2 KIU interrupt register (R) */
119
120// Power Management Unit (PMU)
121#define VR4181_PMUINTREG __preg16(KSEG1 + 0x0B0000A0) /* PMU Status Register (R/W) */
122#define VR4181_PMUINT_POWERSW 0x1 /* Power switch */
123#define VR4181_PMUINT_BATT 0x2 /* Low batt during normal operation */
124#define VR4181_PMUINT_DEADMAN 0x4 /* Deadman's switch */
125#define VR4181_PMUINT_RESET 0x8 /* Reset switch */
126#define VR4181_PMUINT_RTCRESET 0x10 /* RTC Reset */
127#define VR4181_PMUINT_TIMEOUT 0x20 /* HAL Timer Reset */
128#define VR4181_PMUINT_BATTLOW 0x100 /* Battery low */
129#define VR4181_PMUINT_RTC 0x200 /* RTC Alarm */
130#define VR4181_PMUINT_DCD 0x400 /* DCD# */
131#define VR4181_PMUINT_GPIO0 0x1000 /* GPIO0 */
132#define VR4181_PMUINT_GPIO1 0x2000 /* GPIO1 */
133#define VR4181_PMUINT_GPIO2 0x4000 /* GPIO2 */
134#define VR4181_PMUINT_GPIO3 0x8000 /* GPIO3 */
135
136#define VR4181_PMUCNTREG __preg16(KSEG1 + 0x0B0000A2) /* PMU Control Register (R/W) */
137#define VR4181_PMUWAITREG __preg16(KSEG1 + 0x0B0000A8) /* PMU Wait Counter Register (R/W) */
138#define VR4181_PMUDIVREG __preg16(KSEG1 + 0x0B0000AC) /* PMU Divide Mode Register (R/W) */
139#define VR4181_DRAMHIBCTL __preg16(KSEG1 + 0x0B0000B2) /* DRAM Hibernate Control Register (R/W) */
140
141// Real Time Clock Unit (RTC)
142#define VR4181_ETIMELREG __preg16(KSEG1 + 0x0B0000C0) /* Elapsed Time L Register (R/W) */
143#define VR4181_ETIMEMREG __preg16(KSEG1 + 0x0B0000C2) /* Elapsed Time M Register (R/W) */
144#define VR4181_ETIMEHREG __preg16(KSEG1 + 0x0B0000C4) /* Elapsed Time H Register (R/W) */
145#define VR4181_ECMPLREG __preg16(KSEG1 + 0x0B0000C8) /* Elapsed Compare L Register (R/W) */
146#define VR4181_ECMPMREG __preg16(KSEG1 + 0x0B0000CA) /* Elapsed Compare M Register (R/W) */
147#define VR4181_ECMPHREG __preg16(KSEG1 + 0x0B0000CC) /* Elapsed Compare H Register (R/W) */
148#define VR4181_RTCL1LREG __preg16(KSEG1 + 0x0B0000D0) /* RTC Long 1 L Register (R/W) */
149#define VR4181_RTCL1HREG __preg16(KSEG1 + 0x0B0000D2) /* RTC Long 1 H Register (R/W) */
150#define VR4181_RTCL1CNTLREG __preg16(KSEG1 + 0x0B0000D4) /* RTC Long 1 Count L Register (R) */
151#define VR4181_RTCL1CNTHREG __preg16(KSEG1 + 0x0B0000D6) /* RTC Long 1 Count H Register (R) */
152#define VR4181_RTCL2LREG __preg16(KSEG1 + 0x0B0000D8) /* RTC Long 2 L Register (R/W) */
153#define VR4181_RTCL2HREG __preg16(KSEG1 + 0x0B0000DA) /* RTC Long 2 H Register (R/W) */
154#define VR4181_RTCL2CNTLREG __preg16(KSEG1 + 0x0B0000DC) /* RTC Long 2 Count L Register (R) */
155#define VR4181_RTCL2CNTHREG __preg16(KSEG1 + 0x0B0000DE) /* RTC Long 2 Count H Register (R) */
156#define VR4181_RTCINTREG __preg16(KSEG1 + 0x0B0001DE) /* RTC Interrupt Register (R/W) */
157
158// Deadman's Switch Unit (DSU)
159#define VR4181_DSUCNTREG __preg16(KSEG1 + 0x0B0000E0) /* DSU Control Register (R/W) */
160#define VR4181_DSUSETREG __preg16(KSEG1 + 0x0B0000E2) /* DSU Dead Time Set Register (R/W) */
161#define VR4181_DSUCLRREG __preg16(KSEG1 + 0x0B0000E4) /* DSU Clear Register (W) */
162#define VR4181_DSUTIMREG __preg16(KSEG1 + 0x0B0000E6) /* DSU Elapsed Time Register (R/W) */
163
164// General Purpose I/O Unit (GIU)
165#define VR4181_GPMD0REG __preg16(KSEG1 + 0x0B000300) /* GPIO Mode 0 Register (R/W) */
166#define VR4181_GPMD1REG __preg16(KSEG1 + 0x0B000302) /* GPIO Mode 1 Register (R/W) */
167#define VR4181_GPMD2REG __preg16(KSEG1 + 0x0B000304) /* GPIO Mode 2 Register (R/W) */
168#define VR4181_GPMD3REG __preg16(KSEG1 + 0x0B000306) /* GPIO Mode 3 Register (R/W) */
169#define VR4181_GPDATHREG __preg16(KSEG1 + 0x0B000308) /* GPIO Data High Register (R/W) */
170#define VR4181_GPDATHREG_GPIO16 0x0001
171#define VR4181_GPDATHREG_GPIO17 0x0002
172#define VR4181_GPDATHREG_GPIO18 0x0004
173#define VR4181_GPDATHREG_GPIO19 0x0008
174#define VR4181_GPDATHREG_GPIO20 0x0010
175#define VR4181_GPDATHREG_GPIO21 0x0020
176#define VR4181_GPDATHREG_GPIO22 0x0040
177#define VR4181_GPDATHREG_GPIO23 0x0080
178#define VR4181_GPDATHREG_GPIO24 0x0100
179#define VR4181_GPDATHREG_GPIO25 0x0200
180#define VR4181_GPDATHREG_GPIO26 0x0400
181#define VR4181_GPDATHREG_GPIO27 0x0800
182#define VR4181_GPDATHREG_GPIO28 0x1000
183#define VR4181_GPDATHREG_GPIO29 0x2000
184#define VR4181_GPDATHREG_GPIO30 0x4000
185#define VR4181_GPDATHREG_GPIO31 0x8000
186#define VR4181_GPDATLREG __preg16(KSEG1 + 0x0B00030A) /* GPIO Data Low Register (R/W) */
187#define VR4181_GPDATLREG_GPIO0 0x0001
188#define VR4181_GPDATLREG_GPIO1 0x0002
189#define VR4181_GPDATLREG_GPIO2 0x0004
190#define VR4181_GPDATLREG_GPIO3 0x0008
191#define VR4181_GPDATLREG_GPIO4 0x0010
192#define VR4181_GPDATLREG_GPIO5 0x0020
193#define VR4181_GPDATLREG_GPIO6 0x0040
194#define VR4181_GPDATLREG_GPIO7 0x0080
195#define VR4181_GPDATLREG_GPIO8 0x0100
196#define VR4181_GPDATLREG_GPIO9 0x0200
197#define VR4181_GPDATLREG_GPIO10 0x0400
198#define VR4181_GPDATLREG_GPIO11 0x0800
199#define VR4181_GPDATLREG_GPIO12 0x1000
200#define VR4181_GPDATLREG_GPIO13 0x2000
201#define VR4181_GPDATLREG_GPIO14 0x4000
202#define VR4181_GPDATLREG_GPIO15 0x8000
203#define VR4181_GPINTEN __preg16(KSEG1 + 0x0B00030C) /* GPIO Interrupt Enable Register (R/W) */
204#define VR4181_GPINTMSK __preg16(KSEG1 + 0x0B00030E) /* GPIO Interrupt Mask Register (R/W) */
205#define VR4181_GPINTTYPH __preg16(KSEG1 + 0x0B000310) /* GPIO Interrupt Type High Register (R/W) */
206#define VR4181_GPINTTYPL __preg16(KSEG1 + 0x0B000312) /* GPIO Interrupt Type Low Register (R/W) */
207#define VR4181_GPINTSTAT __preg16(KSEG1 + 0x0B000314) /* GPIO Interrupt Status Register (R/W) */
208#define VR4181_GPHIBSTH __preg16(KSEG1 + 0x0B000316) /* GPIO Hibernate Pin State High Register (R/W) */
209#define VR4181_GPHIBSTL __preg16(KSEG1 + 0x0B000318) /* GPIO Hibernate Pin State Low Register (R/W) */
210#define VR4181_GPSICTL __preg16(KSEG1 + 0x0B00031A) /* GPIO Serial Interface Control Register (R/W) */
211#define VR4181_KEYEN __preg16(KSEG1 + 0x0B00031C) /* Keyboard Scan Pin Enable Register (R/W) */
212#define VR4181_PCS0STRA __preg16(KSEG1 + 0x0B000320) /* Programmable Chip Select [0] Start Address Register (R/W) */
213#define VR4181_PCS0STPA __preg16(KSEG1 + 0x0B000322) /* Programmable Chip Select [0] Stop Address Register (R/W) */
214#define VR4181_PCS0HIA __preg16(KSEG1 + 0x0B000324) /* Programmable Chip Select [0] High Address Register (R/W) */
215#define VR4181_PCS1STRA __preg16(KSEG1 + 0x0B000326) /* Programmable Chip Select [1] Start Address Register (R/W) */
216#define VR4181_PCS1STPA __preg16(KSEG1 + 0x0B000328) /* Programmable Chip Select [1] Stop Address Register (R/W) */
217#define VR4181_PCS1HIA __preg16(KSEG1 + 0x0B00032A) /* Programmable Chip Select [1] High Address Register (R/W) */
218#define VR4181_PCSMODE __preg16(KSEG1 + 0x0B00032C) /* Programmable Chip Select Mode Register (R/W) */
219#define VR4181_LCDGPMODE __preg16(KSEG1 + 0x0B00032E) /* LCD General Purpose Mode Register (R/W) */
220#define VR4181_MISCREG0 __preg16(KSEG1 + 0x0B000330) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
221#define VR4181_MISCREG1 __preg16(KSEG1 + 0x0B000332) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
222#define VR4181_MISCREG2 __preg16(KSEG1 + 0x0B000334) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
223#define VR4181_MISCREG3 __preg16(KSEG1 + 0x0B000336) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
224#define VR4181_MISCREG4 __preg16(KSEG1 + 0x0B000338) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
225#define VR4181_MISCREG5 __preg16(KSEG1 + 0x0B00033A) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
226#define VR4181_MISCREG6 __preg16(KSEG1 + 0x0B00033C) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
227#define VR4181_MISCREG7 __preg16(KSEG1 + 0x0B00033D) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
228#define VR4181_MISCREG8 __preg16(KSEG1 + 0x0B000340) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
229#define VR4181_MISCREG9 __preg16(KSEG1 + 0x0B000342) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
230#define VR4181_MISCREG10 __preg16(KSEG1 + 0x0B000344) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
231#define VR4181_MISCREG11 __preg16(KSEG1 + 0x0B000346) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
232#define VR4181_MISCREG12 __preg16(KSEG1 + 0x0B000348) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
233#define VR4181_MISCREG13 __preg16(KSEG1 + 0x0B00034A) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
234#define VR4181_MISCREG14 __preg16(KSEG1 + 0x0B00034C) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
235#define VR4181_MISCREG15 __preg16(KSEG1 + 0x0B00034E) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
236#define VR4181_SECIRQMASKL VR4181_GPINTEN
237// No SECIRQMASKH for VR4181
238
239// Touch Panel Interface Unit (PIU)
240#define VR4181_PIUCNTREG __preg16(KSEG1 + 0x0B000122) /* PIU Control register (R/W) */
241#define VR4181_PIUCNTREG_PIUSEQEN 0x0004
242#define VR4181_PIUCNTREG_PIUPWR 0x0002
243#define VR4181_PIUCNTREG_PADRST 0x0001
244
245#define VR4181_PIUINTREG __preg16(KSEG1 + 0x0B000124) /* PIU Interrupt cause register (R/W) */
246#define VR4181_PIUINTREG_OVP 0x8000
247#define VR4181_PIUINTREG_PADCMD 0x0040
248#define VR4181_PIUINTREG_PADADP 0x0020
249#define VR4181_PIUINTREG_PADPAGE1 0x0010
250#define VR4181_PIUINTREG_PADPAGE0 0x0008
251#define VR4181_PIUINTREG_PADDLOST 0x0004
252#define VR4181_PIUINTREG_PENCHG 0x0001
253
254#define VR4181_PIUSIVLREG __preg16(KSEG1 + 0x0B000126) /* PIU Data sampling interval register (R/W) */
255#define VR4181_PIUSTBLREG __preg16(KSEG1 + 0x0B000128) /* PIU A/D converter start delay register (R/W) */
256#define VR4181_PIUCMDREG __preg16(KSEG1 + 0x0B00012A) /* PIU A/D command register (R/W) */
257#define VR4181_PIUASCNREG __preg16(KSEG1 + 0x0B000130) /* PIU A/D port scan register (R/W) */
258#define VR4181_PIUAMSKREG __preg16(KSEG1 + 0x0B000132) /* PIU A/D scan mask register (R/W) */
259#define VR4181_PIUCIVLREG __preg16(KSEG1 + 0x0B00013E) /* PIU Check interval register (R) */
260#define VR4181_PIUPB00REG __preg16(KSEG1 + 0x0B0002A0) /* PIU Page 0 Buffer 0 register (R/W) */
261#define VR4181_PIUPB01REG __preg16(KSEG1 + 0x0B0002A2) /* PIU Page 0 Buffer 1 register (R/W) */
262#define VR4181_PIUPB02REG __preg16(KSEG1 + 0x0B0002A4) /* PIU Page 0 Buffer 2 register (R/W) */
263#define VR4181_PIUPB03REG __preg16(KSEG1 + 0x0B0002A6) /* PIU Page 0 Buffer 3 register (R/W) */
264#define VR4181_PIUPB10REG __preg16(KSEG1 + 0x0B0002A8) /* PIU Page 1 Buffer 0 register (R/W) */
265#define VR4181_PIUPB11REG __preg16(KSEG1 + 0x0B0002AA) /* PIU Page 1 Buffer 1 register (R/W) */
266#define VR4181_PIUPB12REG __preg16(KSEG1 + 0x0B0002AC) /* PIU Page 1 Buffer 2 register (R/W) */
267#define VR4181_PIUPB13REG __preg16(KSEG1 + 0x0B0002AE) /* PIU Page 1 Buffer 3 register (R/W) */
268#define VR4181_PIUAB0REG __preg16(KSEG1 + 0x0B0002B0) /* PIU A/D scan Buffer 0 register (R/W) */
269#define VR4181_PIUAB1REG __preg16(KSEG1 + 0x0B0002B2) /* PIU A/D scan Buffer 1 register (R/W) */
270#define VR4181_PIUAB2REG __preg16(KSEG1 + 0x0B0002B4) /* PIU A/D scan Buffer 2 register (R/W) */
271#define VR4181_PIUAB3REG __preg16(KSEG1 + 0x0B0002B6) /* PIU A/D scan Buffer 3 register (R/W) */
272#define VR4181_PIUPB04REG __preg16(KSEG1 + 0x0B0002BC) /* PIU Page 0 Buffer 4 register (R/W) */
273#define VR4181_PIUPB14REG __preg16(KSEG1 + 0x0B0002BE) /* PIU Page 1 Buffer 4 register (R/W) */
274
275// Audio Interface Unit (AIU)
276#define VR4181_SODATREG __preg16(KSEG1 + 0x0B000166) /* Speaker Output Data Register (R/W) */
277#define VR4181_SCNTREG __preg16(KSEG1 + 0x0B000168) /* Speaker Output Control Register (R/W) */
278#define VR4181_MIDATREG __preg16(KSEG1 + 0x0B000170) /* Mike Input Data Register (R/W) */
279#define VR4181_MCNTREG __preg16(KSEG1 + 0x0B000172) /* Mike Input Control Register (R/W) */
280#define VR4181_DVALIDREG __preg16(KSEG1 + 0x0B000178) /* Data Valid Register (R/W) */
281#define VR4181_SEQREG __preg16(KSEG1 + 0x0B00017A) /* Sequential Register (R/W) */
282#define VR4181_INTREG __preg16(KSEG1 + 0x0B00017C) /* Interrupt Register (R/W) */
283#define VR4181_SDMADATREG __preg16(KSEG1 + 0x0B000160) /* Speaker DMA Data Register (R/W) */
284#define VR4181_MDMADATREG __preg16(KSEG1 + 0x0B000162) /* Microphone DMA Data Register (R/W) */
285#define VR4181_DAVREF_SETUP __preg16(KSEG1 + 0x0B000164) /* DAC Vref setup register (R/W) */
286#define VR4181_SCNVC_END __preg16(KSEG1 + 0x0B00016E) /* Speaker sample rate control (R/W) */
287#define VR4181_MIDATREG __preg16(KSEG1 + 0x0B000170) /* Microphone Input Data Register (R/W) */
288#define VR4181_MCNTREG __preg16(KSEG1 + 0x0B000172) /* Microphone Input Control Register (R/W) */
289#define VR4181_MCNVC_END __preg16(KSEG1 + 0x0B00017E) /* Microphone sample rate control (R/W) */
290
291// Keyboard Interface Unit (KIU)
292#define VR4181_KIUDAT0 __preg16(KSEG1 + 0x0B000180) /* KIU Data0 Register (R/W) */
293#define VR4181_KIUDAT1 __preg16(KSEG1 + 0x0B000182) /* KIU Data1 Register (R/W) */
294#define VR4181_KIUDAT2 __preg16(KSEG1 + 0x0B000184) /* KIU Data2 Register (R/W) */
295#define VR4181_KIUDAT3 __preg16(KSEG1 + 0x0B000186) /* KIU Data3 Register (R/W) */
296#define VR4181_KIUDAT4 __preg16(KSEG1 + 0x0B000188) /* KIU Data4 Register (R/W) */
297#define VR4181_KIUDAT5 __preg16(KSEG1 + 0x0B00018A) /* KIU Data5 Register (R/W) */
298#define VR4181_KIUSCANREP __preg16(KSEG1 + 0x0B000190) /* KIU Scan/Repeat Register (R/W) */
299#define VR4181_KIUSCANREP_KEYEN 0x8000
300#define VR4181_KIUSCANREP_SCANSTP 0x0008
301#define VR4181_KIUSCANREP_SCANSTART 0x0004
302#define VR4181_KIUSCANREP_ATSTP 0x0002
303#define VR4181_KIUSCANREP_ATSCAN 0x0001
304#define VR4181_KIUSCANS __preg16(KSEG1 + 0x0B000192) /* KIU Scan Status Register (R) */
305#define VR4181_KIUWKS __preg16(KSEG1 + 0x0B000194) /* KIU Wait Keyscan Stable Register (R/W) */
306#define VR4181_KIUWKI __preg16(KSEG1 + 0x0B000196) /* KIU Wait Keyscan Interval Register (R/W) */
307#define VR4181_KIUINT __preg16(KSEG1 + 0x0B000198) /* KIU Interrupt Register (R/W) */
308#define VR4181_KIUINT_KDATLOST 0x0004
309#define VR4181_KIUINT_KDATRDY 0x0002
310#define VR4181_KIUINT_SCANINT 0x0001
311#define VR4181_KIUDAT6 __preg16(KSEG1 + 0x0B00018C) /* Scan Line 6 Key Data Register (R) */
312#define VR4181_KIUDAT7 __preg16(KSEG1 + 0x0B00018E) /* Scan Line 7 Key Data Register (R) */
313
314// CompactFlash Controller
315#define VR4181_PCCARDINDEX __preg8(KSEG1 + 0x0B0008E0) /* PC Card Controller Index Register */
316#define VR4181_PCCARDDATA __preg8(KSEG1 + 0x0B0008E1) /* PC Card Controller Data Register */
317#define VR4181_INTSTATREG __preg16(KSEG1 + 0x0B0008F8) /* Interrupt Status Register (R/W) */
318#define VR4181_INTMSKREG __preg16(KSEG1 + 0x0B0008FA) /* Interrupt Mask Register (R/W) */
319#define VR4181_CFG_REG_1 __preg16(KSEG1 + 0x0B0008FE) /* Configuration Register 1 */
320
321// LED Control Unit (LED)
322#define VR4181_LEDHTSREG __preg16(KSEG1 + 0x0B000240) /* LED H Time Set register (R/W) */
323#define VR4181_LEDLTSREG __preg16(KSEG1 + 0x0B000242) /* LED L Time Set register (R/W) */
324#define VR4181_LEDCNTREG __preg16(KSEG1 + 0x0B000248) /* LED Control register (R/W) */
325#define VR4181_LEDASTCREG __preg16(KSEG1 + 0x0B00024A) /* LED Auto Stop Time Count register (R/W) */
326#define VR4181_LEDINTREG __preg16(KSEG1 + 0x0B00024C) /* LED Interrupt register (R/W) */
327
328// Serial Interface Unit (SIU / SIU1 and SIU2)
329#define VR4181_SIURB __preg8(KSEG1 + 0x0C000010) /* Receiver Buffer Register (Read) DLAB = 0 (R) */
330#define VR4181_SIUTH __preg8(KSEG1 + 0x0C000010) /* Transmitter Holding Register (Write) DLAB = 0 (W) */
331#define VR4181_SIUDLL __preg8(KSEG1 + 0x0C000010) /* Divisor Latch (Least Significant Byte) DLAB = 1 (R/W) */
332#define VR4181_SIUIE __preg8(KSEG1 + 0x0C000011) /* Interrupt Enable DLAB = 0 (R/W) */
333#define VR4181_SIUDLM __preg8(KSEG1 + 0x0C000011) /* Divisor Latch (Most Significant Byte) DLAB = 1 (R/W) */
334#define VR4181_SIUIID __preg8(KSEG1 + 0x0C000012) /* Interrupt Identification Register (Read) (R) */
335#define VR4181_SIUFC __preg8(KSEG1 + 0x0C000012) /* FIFO Control Register (Write) (W) */
336#define VR4181_SIULC __preg8(KSEG1 + 0x0C000013) /* Line Control Register (R/W) */
337#define VR4181_SIUMC __preg8(KSEG1 + 0x0C000014) /* MODEM Control Register (R/W) */
338#define VR4181_SIULS __preg8(KSEG1 + 0x0C000015) /* Line Status Register (R/W) */
339#define VR4181_SIUMS __preg8(KSEG1 + 0x0C000016) /* MODEM Status Register (R/W) */
340#define VR4181_SIUSC __preg8(KSEG1 + 0x0C000017) /* Scratch Register (R/W) */
341#define VR4181_SIURESET __preg8(KSEG1 + 0x0C000019) /* SIU Reset Register (R/W) */
342#define VR4181_SIUACTMSK __preg8(KSEG1 + 0x0C00001C) /* SIU Activity Mask (R/W) */
343#define VR4181_SIUACTTMR __preg8(KSEG1 + 0x0C00001E) /* SIU Activity Timer (R/W) */
344#define VR4181_SIURB_2 __preg8(KSEG1 + 0x0C000000) /* Receive Buffer Register (Read) (R) */
345#define VR4181_SIUTH_2 __preg8(KSEG1 + 0x0C000000) /* Transmitter Holding Register (Write) (W) */
346#define VR4181_SIUDLL_2 __preg8(KSEG1 + 0x0C000000) /* Divisor Latch (Least Significant Byte) (R/W) */
347#define VR4181_SIUIE_2 __preg8(KSEG1 + 0x0C000001) /* Interrupt Enable (DLAB = 0) (R/W) */
348#define VR4181_SIUDLM_2 __preg8(KSEG1 + 0x0C000001) /* Divisor Latch (Most Significant Byte) (DLAB = 1) (R/W) */
349#define VR4181_SIUIID_2 __preg8(KSEG1 + 0x0C000002) /* Interrupt Identification Register (Read) (R) */
350#define VR4181_SIUFC_2 __preg8(KSEG1 + 0x0C000002) /* FIFO Control Register (Write) (W) */
351#define VR4181_SIULC_2 __preg8(KSEG1 + 0x0C000003) /* Line Control Register (R/W) */
352#define VR4181_SIUMC_2 __preg8(KSEG1 + 0x0C000004) /* Modem Control Register (R/W) */
353#define VR4181_SIULS_2 __preg8(KSEG1 + 0x0C000005) /* Line Status Register (R/W) */
354#define VR4181_SIUMS_2 __preg8(KSEG1 + 0x0C000006) /* Modem Status Register (R/W) */
355#define VR4181_SIUSC_2 __preg8(KSEG1 + 0x0C000007) /* Scratch Register (R/W) */
356#define VR4181_SIUIRSEL_2 __preg8(KSEG1 + 0x0C000008) /* SIU IrDA Selectot (R/W) */
357#define VR4181_SIURESET_2 __preg8(KSEG1 + 0x0C000009) /* SIU Reset Register (R/W) */
358#define VR4181_SIUCSEL_2 __preg8(KSEG1 + 0x0C00000A) /* IrDA Echo-back Control (R/W) */
359#define VR4181_SIUACTMSK_2 __preg8(KSEG1 + 0x0C00000C) /* SIU Activity Mask Register (R/W) */
360#define VR4181_SIUACTTMR_2 __preg8(KSEG1 + 0x0C00000E) /* SIU Activity Timer Register (R/W) */
361
362
363// USB Module
364#define VR4181_USBINFIFO __preg16(KSEG1 + 0x0B000780) /* USB Bulk Input FIFO (Bulk In End Point) (W) */
365#define VR4181_USBOUTFIFO __preg16(KSEG1 + 0x0B000782) /* USB Bulk Output FIFO (Bulk Out End Point) (R) */
366#define VR4181_USBCTLFIFO __preg16(KSEG1 + 0x0B000784) /* USB Control FIFO (Control End Point) (W) */
367#define VR4181_USBSTAT __preg16(KSEG1 + 0x0B000786) /* Interrupt Status Register (R/W) */
368#define VR4181_USBINTMSK __preg16(KSEG1 + 0x0B000788) /* Interrupt Mask Register (R/W) */
369#define VR4181_USBCTLREG __preg16(KSEG1 + 0x0B00078A) /* Control Register (R/W) */
370#define VR4181_USBSTPREG __preg16(KSEG1 + 0x0B00078C) /* USB Transfer Stop Register (R/W) */
371
372// LCD Controller
373#define VR4181_HRTOTALREG __preg16(KSEG1 + 0x0A000400) /* Horizontal total Register (R/W) */
374#define VR4181_HRVISIBREG __preg16(KSEG1 + 0x0A000402) /* Horizontal Visible Register (R/W) */
375#define VR4181_LDCLKSTREG __preg16(KSEG1 + 0x0A000404) /* Load clock start Register (R/W) */
376#define VR4181_LDCLKNDREG __preg16(KSEG1 + 0x0A000406) /* Load clock end Register (R/W) */
377#define VR4181_VRTOTALREG __preg16(KSEG1 + 0x0A000408) /* Vertical Total Register (R/W) */
378#define VR4181_VRVISIBREG __preg16(KSEG1 + 0x0A00040A) /* Vertical Visible Register (R/W) */
379#define VR4181_FVSTARTREG __preg16(KSEG1 + 0x0A00040C) /* FLM vertical start Register (R/W) */
380#define VR4181_FVENDREG __preg16(KSEG1 + 0x0A00040E) /* FLM vertical end Register (R/W) */
381#define VR4181_LCDCTRLREG __preg16(KSEG1 + 0x0A000410) /* LCD control Register (R/W) */
382#define VR4181_LCDINRQREG __preg16(KSEG1 + 0x0A000412) /* LCD Interrupt request Register (R/W) */
383#define VR4181_LCDCFGREG0 __preg16(KSEG1 + 0x0A000414) /* LCD Configuration Register 0 (R/W) */
384#define VR4181_LCDCFGREG1 __preg16(KSEG1 + 0x0A000416) /* LCD Configuration Register 1 (R/W) */
385#define VR4181_FBSTAD1REG __preg16(KSEG1 + 0x0A000418) /* Frame Buffer Start Address 1 Register (R/W) */
386#define VR4181_FBSTAD2REG __preg16(KSEG1 + 0x0A00041A) /* Frame Buffer Start Address 2 Register (R/W) */
387#define VR4181_FBNDAD1REG __preg16(KSEG1 + 0x0A000420) /* Frame Buffer End Address 1 Register (R/W) */
388#define VR4181_FBNDAD2REG __preg16(KSEG1 + 0x0A000422) /* Frame Buffer End Address 2 register (R/W) */
389#define VR4181_FHSTARTREG __preg16(KSEG1 + 0x0A000424) /* FLM horizontal Start Register (R/W) */
390#define VR4181_FHENDREG __preg16(KSEG1 + 0x0A000426) /* FLM horizontal End Register (R/W) */
391#define VR4181_PWRCONREG1 __preg16(KSEG1 + 0x0A000430) /* Power Control register 1 (R/W) */
392#define VR4181_PWRCONREG2 __preg16(KSEG1 + 0x0A000432) /* Power Control register 2 (R/W) */
393#define VR4181_LCDIMSKREG __preg16(KSEG1 + 0x0A000434) /* LCD Interrupt Mask register (R/W) */
394#define VR4181_CPINDCTREG __preg16(KSEG1 + 0x0A00047E) /* Color palette Index and control Register (R/W) */
395#define VR4181_CPALDATREG __preg32(KSEG1 + 0x0A000480) /* Color palette data register (32bits Register) (R/W) */
396
397// physical address spaces
398#define VR4181_LCD 0x0a000000
399#define VR4181_INTERNAL_IO_2 0x0b000000
400#define VR4181_INTERNAL_IO_1 0x0c000000
401#define VR4181_ISA_MEM 0x10000000
402#define VR4181_ISA_IO 0x14000000
403#define VR4181_ROM 0x18000000
404
405// This is the base address for IO port decoding to which the 16 bit IO port address
406// is added. Defining it to 0 will usually cause a kernel oops any time port IO is
407// attempted, which can be handy for turning up parts of the kernel that make
408// incorrect architecture assumptions (by assuming that everything acts like a PC),
409// but we need it correctly defined to use the PCMCIA/CF controller:
410#define VR4181_PORT_BASE (KSEG1 + VR4181_ISA_IO)
411#define VR4181_ISAMEM_BASE (KSEG1 + VR4181_ISA_MEM)
412
413#endif /* __ASM_VR4181_VR4181_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-21 21:33:02 -0500