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authorMark A. Greer <mgreer@mvista.com>2009-04-15 15:39:48 -0400
committerKevin Hilman <khilman@deeprootsystems.com>2009-05-26 11:17:16 -0400
commit0e585952ac6a06b3c77d6b8eadb9c359766a700d (patch)
treed8216964e80d9cd3d86b5aa9cb25f035efa26bef
parentd81d188cafecbc9e01df51527ac4c84a5b19e033 (diff)
davinci: Move pinmux setup info to SoC infrastructure
The pinmux register base and setup can be different for different SoCs so move the pinmux reg base, pinmux table (and its size) to the SoC infrastructure. Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
-rw-r--r--arch/arm/mach-davinci/dm355.c6
-rw-r--r--arch/arm/mach-davinci/dm644x.c6
-rw-r--r--arch/arm/mach-davinci/dm646x.c6
-rw-r--r--arch/arm/mach-davinci/include/mach/common.h3
-rw-r--r--arch/arm/mach-davinci/include/mach/mux.h6
-rw-r--r--arch/arm/mach-davinci/mux.c24
6 files changed, 25 insertions, 26 deletions
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 37f20a7214be..f735ed9d2d10 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -436,6 +436,7 @@ void __init dm355_init_spi0(unsigned chipselect_mask,
436 * reg offset mask mode 436 * reg offset mask mode
437 */ 437 */
438static const struct mux_config dm355_pins[] = { 438static const struct mux_config dm355_pins[] = {
439#ifdef CONFIG_DAVINCI_MUX
439MUX_CFG(DM355, MMCSD0, 4, 2, 1, 0, false) 440MUX_CFG(DM355, MMCSD0, 4, 2, 1, 0, false)
440 441
441MUX_CFG(DM355, SD1_CLK, 3, 6, 1, 1, false) 442MUX_CFG(DM355, SD1_CLK, 3, 6, 1, 1, false)
@@ -466,6 +467,7 @@ INT_CFG(DM355, INT_EDMA_TC1_ERR, 4, 1, 1, false)
466EVT_CFG(DM355, EVT8_ASP1_TX, 0, 1, 0, false) 467EVT_CFG(DM355, EVT8_ASP1_TX, 0, 1, 0, false)
467EVT_CFG(DM355, EVT9_ASP1_RX, 1, 1, 0, false) 468EVT_CFG(DM355, EVT9_ASP1_RX, 1, 1, 0, false)
468EVT_CFG(DM355, EVT26_MMC0_RX, 2, 1, 0, false) 469EVT_CFG(DM355, EVT26_MMC0_RX, 2, 1, 0, false)
470#endif
469}; 471};
470 472
471/*----------------------------------------------------------------------*/ 473/*----------------------------------------------------------------------*/
@@ -558,12 +560,14 @@ static struct davinci_soc_info davinci_soc_info_dm355 = {
558 .cpu_clks = dm355_clks, 560 .cpu_clks = dm355_clks,
559 .psc_bases = dm355_psc_bases, 561 .psc_bases = dm355_psc_bases,
560 .psc_bases_num = ARRAY_SIZE(dm355_psc_bases), 562 .psc_bases_num = ARRAY_SIZE(dm355_psc_bases),
563 .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
564 .pinmux_pins = dm355_pins,
565 .pinmux_pins_num = ARRAY_SIZE(dm355_pins),
561}; 566};
562 567
563void __init dm355_init(void) 568void __init dm355_init(void)
564{ 569{
565 davinci_common_init(&davinci_soc_info_dm355); 570 davinci_common_init(&davinci_soc_info_dm355);
566 davinci_mux_register(dm355_pins, ARRAY_SIZE(dm355_pins));;
567} 571}
568 572
569static int __init dm355_init_devices(void) 573static int __init dm355_init_devices(void)
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 7b15faba56ed..b7c17dd6795b 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -346,6 +346,7 @@ static struct platform_device dm644x_emac_device = {
346 * reg offset mask mode 346 * reg offset mask mode
347 */ 347 */
348static const struct mux_config dm644x_pins[] = { 348static const struct mux_config dm644x_pins[] = {
349#ifdef CONFIG_DAVINCI_MUX
349MUX_CFG(DM644X, HDIREN, 0, 16, 1, 1, true) 350MUX_CFG(DM644X, HDIREN, 0, 16, 1, 1, true)
350MUX_CFG(DM644X, ATAEN, 0, 17, 1, 1, true) 351MUX_CFG(DM644X, ATAEN, 0, 17, 1, 1, true)
351MUX_CFG(DM644X, ATAEN_DISABLE, 0, 17, 1, 0, true) 352MUX_CFG(DM644X, ATAEN_DISABLE, 0, 17, 1, 0, true)
@@ -386,6 +387,7 @@ MUX_CFG(DM644X, RGB666, 0, 22, 1, 1, true)
386 387
387MUX_CFG(DM644X, LOEEN, 0, 24, 1, 1, true) 388MUX_CFG(DM644X, LOEEN, 0, 24, 1, 1, true)
388MUX_CFG(DM644X, LFLDEN, 0, 25, 1, 1, false) 389MUX_CFG(DM644X, LFLDEN, 0, 25, 1, 1, false)
390#endif
389}; 391};
390 392
391/*----------------------------------------------------------------------*/ 393/*----------------------------------------------------------------------*/
@@ -498,12 +500,14 @@ static struct davinci_soc_info davinci_soc_info_dm644x = {
498 .cpu_clks = dm644x_clks, 500 .cpu_clks = dm644x_clks,
499 .psc_bases = dm644x_psc_bases, 501 .psc_bases = dm644x_psc_bases,
500 .psc_bases_num = ARRAY_SIZE(dm644x_psc_bases), 502 .psc_bases_num = ARRAY_SIZE(dm644x_psc_bases),
503 .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
504 .pinmux_pins = dm644x_pins,
505 .pinmux_pins_num = ARRAY_SIZE(dm644x_pins),
501}; 506};
502 507
503void __init dm644x_init(void) 508void __init dm644x_init(void)
504{ 509{
505 davinci_common_init(&davinci_soc_info_dm644x); 510 davinci_common_init(&davinci_soc_info_dm644x);
506 davinci_mux_register(dm644x_pins, ARRAY_SIZE(dm644x_pins));
507} 511}
508 512
509static int __init dm644x_init_devices(void) 513static int __init dm644x_init_devices(void)
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 3c61543c7cfa..299d8d9d26e0 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -327,6 +327,7 @@ static struct platform_device dm646x_emac_device = {
327 * reg offset mask mode 327 * reg offset mask mode
328 */ 328 */
329static const struct mux_config dm646x_pins[] = { 329static const struct mux_config dm646x_pins[] = {
330#ifdef CONFIG_DAVINCI_MUX
330MUX_CFG(DM646X, ATAEN, 0, 0, 1, 1, true) 331MUX_CFG(DM646X, ATAEN, 0, 0, 1, 1, true)
331 332
332MUX_CFG(DM646X, AUDCK1, 0, 29, 1, 0, false) 333MUX_CFG(DM646X, AUDCK1, 0, 29, 1, 0, false)
@@ -354,6 +355,7 @@ MUX_CFG(DM646X, PTSIMUX_PARALLEL, 0, 16, 3, 2, true)
354MUX_CFG(DM646X, PTSOMUX_SERIAL, 0, 18, 3, 3, true) 355MUX_CFG(DM646X, PTSOMUX_SERIAL, 0, 18, 3, 3, true)
355 356
356MUX_CFG(DM646X, PTSIMUX_SERIAL, 0, 16, 3, 3, true) 357MUX_CFG(DM646X, PTSIMUX_SERIAL, 0, 16, 3, 3, true)
358#endif
357}; 359};
358 360
359/*----------------------------------------------------------------------*/ 361/*----------------------------------------------------------------------*/
@@ -478,12 +480,14 @@ static struct davinci_soc_info davinci_soc_info_dm646x = {
478 .cpu_clks = dm646x_clks, 480 .cpu_clks = dm646x_clks,
479 .psc_bases = dm646x_psc_bases, 481 .psc_bases = dm646x_psc_bases,
480 .psc_bases_num = ARRAY_SIZE(dm646x_psc_bases), 482 .psc_bases_num = ARRAY_SIZE(dm646x_psc_bases),
483 .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
484 .pinmux_pins = dm646x_pins,
485 .pinmux_pins_num = ARRAY_SIZE(dm646x_pins),
481}; 486};
482 487
483void __init dm646x_init(void) 488void __init dm646x_init(void)
484{ 489{
485 davinci_common_init(&davinci_soc_info_dm646x); 490 davinci_common_init(&davinci_soc_info_dm646x);
486 davinci_mux_register(dm646x_pins, ARRAY_SIZE(dm646x_pins));
487} 491}
488 492
489static int __init dm646x_init_devices(void) 493static int __init dm646x_init_devices(void)
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index 7851d5680c13..c00d375946d1 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -36,6 +36,9 @@ struct davinci_soc_info {
36 struct davinci_clk *cpu_clks; 36 struct davinci_clk *cpu_clks;
37 void __iomem **psc_bases; 37 void __iomem **psc_bases;
38 unsigned long psc_bases_num; 38 unsigned long psc_bases_num;
39 void __iomem *pinmux_base;
40 const struct mux_config *pinmux_pins;
41 unsigned long pinmux_pins_num;
39}; 42};
40 43
41extern struct davinci_soc_info davinci_soc_info; 44extern struct davinci_soc_info davinci_soc_info;
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index bae22cb3e27b..5d6efa80af6f 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -168,15 +168,9 @@ enum davinci_dm355_index {
168 168
169#ifdef CONFIG_DAVINCI_MUX 169#ifdef CONFIG_DAVINCI_MUX
170/* setup pin muxing */ 170/* setup pin muxing */
171extern void davinci_mux_init(void);
172extern int davinci_mux_register(const struct mux_config *pins,
173 unsigned long size);
174extern int davinci_cfg_reg(unsigned long reg_cfg); 171extern int davinci_cfg_reg(unsigned long reg_cfg);
175#else 172#else
176/* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */ 173/* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */
177static inline void davinci_mux_init(void) {}
178static inline int davinci_mux_register(const struct mux_config *pins,
179 unsigned long size) { return 0; }
180static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; } 174static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; }
181#endif 175#endif
182 176
diff --git a/arch/arm/mach-davinci/mux.c b/arch/arm/mach-davinci/mux.c
index bbba0b247a44..d310f579aa85 100644
--- a/arch/arm/mach-davinci/mux.c
+++ b/arch/arm/mach-davinci/mux.c
@@ -21,18 +21,7 @@
21 21
22#include <mach/hardware.h> 22#include <mach/hardware.h>
23#include <mach/mux.h> 23#include <mach/mux.h>
24 24#include <mach/common.h>
25static const struct mux_config *mux_table;
26static unsigned long pin_table_sz;
27
28int __init davinci_mux_register(const struct mux_config *pins,
29 unsigned long size)
30{
31 mux_table = pins;
32 pin_table_sz = size;
33
34 return 0;
35}
36 25
37/* 26/*
38 * Sets the DAVINCI MUX register based on the table 27 * Sets the DAVINCI MUX register based on the table
@@ -40,23 +29,24 @@ int __init davinci_mux_register(const struct mux_config *pins,
40int __init_or_module davinci_cfg_reg(const unsigned long index) 29int __init_or_module davinci_cfg_reg(const unsigned long index)
41{ 30{
42 static DEFINE_SPINLOCK(mux_spin_lock); 31 static DEFINE_SPINLOCK(mux_spin_lock);
43 void __iomem *base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE); 32 struct davinci_soc_info *soc_info = &davinci_soc_info;
33 void __iomem *base = soc_info->pinmux_base;
44 unsigned long flags; 34 unsigned long flags;
45 const struct mux_config *cfg; 35 const struct mux_config *cfg;
46 unsigned int reg_orig = 0, reg = 0; 36 unsigned int reg_orig = 0, reg = 0;
47 unsigned int mask, warn = 0; 37 unsigned int mask, warn = 0;
48 38
49 if (!mux_table) 39 if (!soc_info->pinmux_pins)
50 BUG(); 40 BUG();
51 41
52 if (index >= pin_table_sz) { 42 if (index >= soc_info->pinmux_pins_num) {
53 printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n", 43 printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
54 index, pin_table_sz); 44 index, soc_info->pinmux_pins_num);
55 dump_stack(); 45 dump_stack();
56 return -ENODEV; 46 return -ENODEV;
57 } 47 }
58 48
59 cfg = &mux_table[index]; 49 cfg = &soc_info->pinmux_pins[index];
60 50
61 if (cfg->name == NULL) { 51 if (cfg->name == NULL) {
62 printk(KERN_ERR "No entry for the specified index\n"); 52 printk(KERN_ERR "No entry for the specified index\n");