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authorDenys Vlasenko <vda.linux@googlemail.com>2008-09-22 17:56:42 -0400
committerJames Bottomley <James.Bottomley@HansenPartnership.com>2008-10-23 12:42:12 -0400
commit060ae855a836d3ed3359faa13874e92caaa34763 (patch)
tree40471c6c232f0f7703b1db281260cae56b903208
parent7b61ab89f9981ef296fb04dc42ee46fcc922c14f (diff)
[SCSI] aic7xxx: update *_shipped files
Signed-off-by: Denys Vlasenko <vda.linux@googlemail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Acked-by: Hannes Reinecke <hare@suse.de> Signed-off-by: James Bottomley <James.Bottomley@HansenPartnership.com>
Diffstat
-rw-r--r--drivers/scsi/aic7xxx/aic79xx_reg.h_shipped567
-rw-r--r--drivers/scsi/aic7xxx/aic79xx_reg_print.c_shipped1723
-rw-r--r--drivers/scsi/aic7xxx/aic7xxx_reg.h_shipped875
-rw-r--r--drivers/scsi/aic7xxx/aic7xxx_reg_print.c_shipped1165
4 files changed, 133 insertions, 4197 deletions
diff --git a/drivers/scsi/aic7xxx/aic79xx_reg.h_shipped b/drivers/scsi/aic7xxx/aic79xx_reg.h_shipped
index c21ceab8e913..cdcead071ef6 100644
--- a/drivers/scsi/aic7xxx/aic79xx_reg.h_shipped
+++ b/drivers/scsi/aic7xxx/aic79xx_reg.h_shipped
@@ -34,13 +34,6 @@ ahd_reg_print_t ahd_seqintcode_print;
34#endif 34#endif
35 35
36#if AIC_DEBUG_REGISTERS 36#if AIC_DEBUG_REGISTERS
37ahd_reg_print_t ahd_clrint_print;
38#else
39#define ahd_clrint_print(regvalue, cur_col, wrap) \
40 ahd_print_register(NULL, 0, "CLRINT", 0x03, regvalue, cur_col, wrap)
41#endif
42
43#if AIC_DEBUG_REGISTERS
44ahd_reg_print_t ahd_error_print; 37ahd_reg_print_t ahd_error_print;
45#else 38#else
46#define ahd_error_print(regvalue, cur_col, wrap) \ 39#define ahd_error_print(regvalue, cur_col, wrap) \
@@ -48,20 +41,6 @@ ahd_reg_print_t ahd_error_print;
48#endif 41#endif
49 42
50#if AIC_DEBUG_REGISTERS 43#if AIC_DEBUG_REGISTERS
51ahd_reg_print_t ahd_hcntrl_print;
52#else
53#define ahd_hcntrl_print(regvalue, cur_col, wrap) \
54 ahd_print_register(NULL, 0, "HCNTRL", 0x05, regvalue, cur_col, wrap)
55#endif
56
57#if AIC_DEBUG_REGISTERS
58ahd_reg_print_t ahd_hnscb_qoff_print;
59#else
60#define ahd_hnscb_qoff_print(regvalue, cur_col, wrap) \
61 ahd_print_register(NULL, 0, "HNSCB_QOFF", 0x06, regvalue, cur_col, wrap)
62#endif
63
64#if AIC_DEBUG_REGISTERS
65ahd_reg_print_t ahd_hescb_qoff_print; 44ahd_reg_print_t ahd_hescb_qoff_print;
66#else 45#else
67#define ahd_hescb_qoff_print(regvalue, cur_col, wrap) \ 46#define ahd_hescb_qoff_print(regvalue, cur_col, wrap) \
@@ -97,13 +76,6 @@ ahd_reg_print_t ahd_swtimer_print;
97#endif 76#endif
98 77
99#if AIC_DEBUG_REGISTERS 78#if AIC_DEBUG_REGISTERS
100ahd_reg_print_t ahd_snscb_qoff_print;
101#else
102#define ahd_snscb_qoff_print(regvalue, cur_col, wrap) \
103 ahd_print_register(NULL, 0, "SNSCB_QOFF", 0x10, regvalue, cur_col, wrap)
104#endif
105
106#if AIC_DEBUG_REGISTERS
107ahd_reg_print_t ahd_sescb_qoff_print; 79ahd_reg_print_t ahd_sescb_qoff_print;
108#else 80#else
109#define ahd_sescb_qoff_print(regvalue, cur_col, wrap) \ 81#define ahd_sescb_qoff_print(regvalue, cur_col, wrap) \
@@ -111,20 +83,6 @@ ahd_reg_print_t ahd_sescb_qoff_print;
111#endif 83#endif
112 84
113#if AIC_DEBUG_REGISTERS 85#if AIC_DEBUG_REGISTERS
114ahd_reg_print_t ahd_sdscb_qoff_print;
115#else
116#define ahd_sdscb_qoff_print(regvalue, cur_col, wrap) \
117 ahd_print_register(NULL, 0, "SDSCB_QOFF", 0x14, regvalue, cur_col, wrap)
118#endif
119
120#if AIC_DEBUG_REGISTERS
121ahd_reg_print_t ahd_qoff_ctlsta_print;
122#else
123#define ahd_qoff_ctlsta_print(regvalue, cur_col, wrap) \
124 ahd_print_register(NULL, 0, "QOFF_CTLSTA", 0x16, regvalue, cur_col, wrap)
125#endif
126
127#if AIC_DEBUG_REGISTERS
128ahd_reg_print_t ahd_intctl_print; 86ahd_reg_print_t ahd_intctl_print;
129#else 87#else
130#define ahd_intctl_print(regvalue, cur_col, wrap) \ 88#define ahd_intctl_print(regvalue, cur_col, wrap) \
@@ -139,13 +97,6 @@ ahd_reg_print_t ahd_dfcntrl_print;
139#endif 97#endif
140 98
141#if AIC_DEBUG_REGISTERS 99#if AIC_DEBUG_REGISTERS
142ahd_reg_print_t ahd_dscommand0_print;
143#else
144#define ahd_dscommand0_print(regvalue, cur_col, wrap) \
145 ahd_print_register(NULL, 0, "DSCOMMAND0", 0x19, regvalue, cur_col, wrap)
146#endif
147
148#if AIC_DEBUG_REGISTERS
149ahd_reg_print_t ahd_dfstatus_print; 100ahd_reg_print_t ahd_dfstatus_print;
150#else 101#else
151#define ahd_dfstatus_print(regvalue, cur_col, wrap) \ 102#define ahd_dfstatus_print(regvalue, cur_col, wrap) \
@@ -160,13 +111,6 @@ ahd_reg_print_t ahd_sg_cache_shadow_print;
160#endif 111#endif
161 112
162#if AIC_DEBUG_REGISTERS 113#if AIC_DEBUG_REGISTERS
163ahd_reg_print_t ahd_sg_cache_pre_print;
164#else
165#define ahd_sg_cache_pre_print(regvalue, cur_col, wrap) \
166 ahd_print_register(NULL, 0, "SG_CACHE_PRE", 0x1b, regvalue, cur_col, wrap)
167#endif
168
169#if AIC_DEBUG_REGISTERS
170ahd_reg_print_t ahd_lqin_print; 114ahd_reg_print_t ahd_lqin_print;
171#else 115#else
172#define ahd_lqin_print(regvalue, cur_col, wrap) \ 116#define ahd_lqin_print(regvalue, cur_col, wrap) \
@@ -293,13 +237,6 @@ ahd_reg_print_t ahd_sxfrctl0_print;
293#endif 237#endif
294 238
295#if AIC_DEBUG_REGISTERS 239#if AIC_DEBUG_REGISTERS
296ahd_reg_print_t ahd_sxfrctl1_print;
297#else
298#define ahd_sxfrctl1_print(regvalue, cur_col, wrap) \
299 ahd_print_register(NULL, 0, "SXFRCTL1", 0x3d, regvalue, cur_col, wrap)
300#endif
301
302#if AIC_DEBUG_REGISTERS
303ahd_reg_print_t ahd_dffstat_print; 240ahd_reg_print_t ahd_dffstat_print;
304#else 241#else
305#define ahd_dffstat_print(regvalue, cur_col, wrap) \ 242#define ahd_dffstat_print(regvalue, cur_col, wrap) \
@@ -314,13 +251,6 @@ ahd_reg_print_t ahd_multargid_print;
314#endif 251#endif
315 252
316#if AIC_DEBUG_REGISTERS 253#if AIC_DEBUG_REGISTERS
317ahd_reg_print_t ahd_scsisigo_print;
318#else
319#define ahd_scsisigo_print(regvalue, cur_col, wrap) \
320 ahd_print_register(NULL, 0, "SCSISIGO", 0x40, regvalue, cur_col, wrap)
321#endif
322
323#if AIC_DEBUG_REGISTERS
324ahd_reg_print_t ahd_scsisigi_print; 254ahd_reg_print_t ahd_scsisigi_print;
325#else 255#else
326#define ahd_scsisigi_print(regvalue, cur_col, wrap) \ 256#define ahd_scsisigi_print(regvalue, cur_col, wrap) \
@@ -363,13 +293,6 @@ ahd_reg_print_t ahd_selid_print;
363#endif 293#endif
364 294
365#if AIC_DEBUG_REGISTERS 295#if AIC_DEBUG_REGISTERS
366ahd_reg_print_t ahd_optionmode_print;
367#else
368#define ahd_optionmode_print(regvalue, cur_col, wrap) \
369 ahd_print_register(NULL, 0, "OPTIONMODE", 0x4a, regvalue, cur_col, wrap)
370#endif
371
372#if AIC_DEBUG_REGISTERS
373ahd_reg_print_t ahd_sblkctl_print; 296ahd_reg_print_t ahd_sblkctl_print;
374#else 297#else
375#define ahd_sblkctl_print(regvalue, cur_col, wrap) \ 298#define ahd_sblkctl_print(regvalue, cur_col, wrap) \
@@ -391,13 +314,6 @@ ahd_reg_print_t ahd_simode0_print;
391#endif 314#endif
392 315
393#if AIC_DEBUG_REGISTERS 316#if AIC_DEBUG_REGISTERS
394ahd_reg_print_t ahd_clrsint0_print;
395#else
396#define ahd_clrsint0_print(regvalue, cur_col, wrap) \
397 ahd_print_register(NULL, 0, "CLRSINT0", 0x4b, regvalue, cur_col, wrap)
398#endif
399
400#if AIC_DEBUG_REGISTERS
401ahd_reg_print_t ahd_sstat1_print; 317ahd_reg_print_t ahd_sstat1_print;
402#else 318#else
403#define ahd_sstat1_print(regvalue, cur_col, wrap) \ 319#define ahd_sstat1_print(regvalue, cur_col, wrap) \
@@ -405,13 +321,6 @@ ahd_reg_print_t ahd_sstat1_print;
405#endif 321#endif
406 322
407#if AIC_DEBUG_REGISTERS 323#if AIC_DEBUG_REGISTERS
408ahd_reg_print_t ahd_clrsint1_print;
409#else
410#define ahd_clrsint1_print(regvalue, cur_col, wrap) \
411 ahd_print_register(NULL, 0, "CLRSINT1", 0x4c, regvalue, cur_col, wrap)
412#endif
413
414#if AIC_DEBUG_REGISTERS
415ahd_reg_print_t ahd_sstat2_print; 324ahd_reg_print_t ahd_sstat2_print;
416#else 325#else
417#define ahd_sstat2_print(regvalue, cur_col, wrap) \ 326#define ahd_sstat2_print(regvalue, cur_col, wrap) \
@@ -461,17 +370,17 @@ ahd_reg_print_t ahd_lqistat0_print;
461#endif 370#endif
462 371
463#if AIC_DEBUG_REGISTERS 372#if AIC_DEBUG_REGISTERS
464ahd_reg_print_t ahd_lqimode0_print; 373ahd_reg_print_t ahd_clrlqiint0_print;
465#else 374#else
466#define ahd_lqimode0_print(regvalue, cur_col, wrap) \ 375#define ahd_clrlqiint0_print(regvalue, cur_col, wrap) \
467 ahd_print_register(NULL, 0, "LQIMODE0", 0x50, regvalue, cur_col, wrap) 376 ahd_print_register(NULL, 0, "CLRLQIINT0", 0x50, regvalue, cur_col, wrap)
468#endif 377#endif
469 378
470#if AIC_DEBUG_REGISTERS 379#if AIC_DEBUG_REGISTERS
471ahd_reg_print_t ahd_clrlqiint0_print; 380ahd_reg_print_t ahd_lqimode0_print;
472#else 381#else
473#define ahd_clrlqiint0_print(regvalue, cur_col, wrap) \ 382#define ahd_lqimode0_print(regvalue, cur_col, wrap) \
474 ahd_print_register(NULL, 0, "CLRLQIINT0", 0x50, regvalue, cur_col, wrap) 383 ahd_print_register(NULL, 0, "LQIMODE0", 0x50, regvalue, cur_col, wrap)
475#endif 384#endif
476 385
477#if AIC_DEBUG_REGISTERS 386#if AIC_DEBUG_REGISTERS
@@ -629,17 +538,17 @@ ahd_reg_print_t ahd_seqintsrc_print;
629#endif 538#endif
630 539
631#if AIC_DEBUG_REGISTERS 540#if AIC_DEBUG_REGISTERS
632ahd_reg_print_t ahd_seqimode_print; 541ahd_reg_print_t ahd_currscb_print;
633#else 542#else
634#define ahd_seqimode_print(regvalue, cur_col, wrap) \ 543#define ahd_currscb_print(regvalue, cur_col, wrap) \
635 ahd_print_register(NULL, 0, "SEQIMODE", 0x5c, regvalue, cur_col, wrap) 544 ahd_print_register(NULL, 0, "CURRSCB", 0x5c, regvalue, cur_col, wrap)
636#endif 545#endif
637 546
638#if AIC_DEBUG_REGISTERS 547#if AIC_DEBUG_REGISTERS
639ahd_reg_print_t ahd_currscb_print; 548ahd_reg_print_t ahd_seqimode_print;
640#else 549#else
641#define ahd_currscb_print(regvalue, cur_col, wrap) \ 550#define ahd_seqimode_print(regvalue, cur_col, wrap) \
642 ahd_print_register(NULL, 0, "CURRSCB", 0x5c, regvalue, cur_col, wrap) 551 ahd_print_register(NULL, 0, "SEQIMODE", 0x5c, regvalue, cur_col, wrap)
643#endif 552#endif
644 553
645#if AIC_DEBUG_REGISTERS 554#if AIC_DEBUG_REGISTERS
@@ -657,13 +566,6 @@ ahd_reg_print_t ahd_lastscb_print;
657#endif 566#endif
658 567
659#if AIC_DEBUG_REGISTERS 568#if AIC_DEBUG_REGISTERS
660ahd_reg_print_t ahd_shaddr_print;
661#else
662#define ahd_shaddr_print(regvalue, cur_col, wrap) \
663 ahd_print_register(NULL, 0, "SHADDR", 0x60, regvalue, cur_col, wrap)
664#endif
665
666#if AIC_DEBUG_REGISTERS
667ahd_reg_print_t ahd_negoaddr_print; 569ahd_reg_print_t ahd_negoaddr_print;
668#else 570#else
669#define ahd_negoaddr_print(regvalue, cur_col, wrap) \ 571#define ahd_negoaddr_print(regvalue, cur_col, wrap) \
@@ -748,27 +650,6 @@ ahd_reg_print_t ahd_seloid_print;
748#endif 650#endif
749 651
750#if AIC_DEBUG_REGISTERS 652#if AIC_DEBUG_REGISTERS
751ahd_reg_print_t ahd_haddr_print;
752#else
753#define ahd_haddr_print(regvalue, cur_col, wrap) \
754 ahd_print_register(NULL, 0, "HADDR", 0x70, regvalue, cur_col, wrap)
755#endif
756
757#if AIC_DEBUG_REGISTERS
758ahd_reg_print_t ahd_hcnt_print;
759#else
760#define ahd_hcnt_print(regvalue, cur_col, wrap) \
761 ahd_print_register(NULL, 0, "HCNT", 0x78, regvalue, cur_col, wrap)
762#endif
763
764#if AIC_DEBUG_REGISTERS
765ahd_reg_print_t ahd_sghaddr_print;
766#else
767#define ahd_sghaddr_print(regvalue, cur_col, wrap) \
768 ahd_print_register(NULL, 0, "SGHADDR", 0x7c, regvalue, cur_col, wrap)
769#endif
770
771#if AIC_DEBUG_REGISTERS
772ahd_reg_print_t ahd_scbhaddr_print; 653ahd_reg_print_t ahd_scbhaddr_print;
773#else 654#else
774#define ahd_scbhaddr_print(regvalue, cur_col, wrap) \ 655#define ahd_scbhaddr_print(regvalue, cur_col, wrap) \
@@ -776,10 +657,10 @@ ahd_reg_print_t ahd_scbhaddr_print;
776#endif 657#endif
777 658
778#if AIC_DEBUG_REGISTERS 659#if AIC_DEBUG_REGISTERS
779ahd_reg_print_t ahd_sghcnt_print; 660ahd_reg_print_t ahd_sghaddr_print;
780#else 661#else
781#define ahd_sghcnt_print(regvalue, cur_col, wrap) \ 662#define ahd_sghaddr_print(regvalue, cur_col, wrap) \
782 ahd_print_register(NULL, 0, "SGHCNT", 0x84, regvalue, cur_col, wrap) 663 ahd_print_register(NULL, 0, "SGHADDR", 0x7c, regvalue, cur_col, wrap)
783#endif 664#endif
784 665
785#if AIC_DEBUG_REGISTERS 666#if AIC_DEBUG_REGISTERS
@@ -790,10 +671,10 @@ ahd_reg_print_t ahd_scbhcnt_print;
790#endif 671#endif
791 672
792#if AIC_DEBUG_REGISTERS 673#if AIC_DEBUG_REGISTERS
793ahd_reg_print_t ahd_dff_thrsh_print; 674ahd_reg_print_t ahd_sghcnt_print;
794#else 675#else
795#define ahd_dff_thrsh_print(regvalue, cur_col, wrap) \ 676#define ahd_sghcnt_print(regvalue, cur_col, wrap) \
796 ahd_print_register(NULL, 0, "DFF_THRSH", 0x88, regvalue, cur_col, wrap) 677 ahd_print_register(NULL, 0, "SGHCNT", 0x84, regvalue, cur_col, wrap)
797#endif 678#endif
798 679
799#if AIC_DEBUG_REGISTERS 680#if AIC_DEBUG_REGISTERS
@@ -867,13 +748,6 @@ ahd_reg_print_t ahd_targpcistat_print;
867#endif 748#endif
868 749
869#if AIC_DEBUG_REGISTERS 750#if AIC_DEBUG_REGISTERS
870ahd_reg_print_t ahd_scbptr_print;
871#else
872#define ahd_scbptr_print(regvalue, cur_col, wrap) \
873 ahd_print_register(NULL, 0, "SCBPTR", 0xa8, regvalue, cur_col, wrap)
874#endif
875
876#if AIC_DEBUG_REGISTERS
877ahd_reg_print_t ahd_scbautoptr_print; 751ahd_reg_print_t ahd_scbautoptr_print;
878#else 752#else
879#define ahd_scbautoptr_print(regvalue, cur_col, wrap) \ 753#define ahd_scbautoptr_print(regvalue, cur_col, wrap) \
@@ -881,13 +755,6 @@ ahd_reg_print_t ahd_scbautoptr_print;
881#endif 755#endif
882 756
883#if AIC_DEBUG_REGISTERS 757#if AIC_DEBUG_REGISTERS
884ahd_reg_print_t ahd_ccsgaddr_print;
885#else
886#define ahd_ccsgaddr_print(regvalue, cur_col, wrap) \
887 ahd_print_register(NULL, 0, "CCSGADDR", 0xac, regvalue, cur_col, wrap)
888#endif
889
890#if AIC_DEBUG_REGISTERS
891ahd_reg_print_t ahd_ccscbaddr_print; 758ahd_reg_print_t ahd_ccscbaddr_print;
892#else 759#else
893#define ahd_ccscbaddr_print(regvalue, cur_col, wrap) \ 760#define ahd_ccscbaddr_print(regvalue, cur_col, wrap) \
@@ -909,13 +776,6 @@ ahd_reg_print_t ahd_ccsgctl_print;
909#endif 776#endif
910 777
911#if AIC_DEBUG_REGISTERS 778#if AIC_DEBUG_REGISTERS
912ahd_reg_print_t ahd_ccsgram_print;
913#else
914#define ahd_ccsgram_print(regvalue, cur_col, wrap) \
915 ahd_print_register(NULL, 0, "CCSGRAM", 0xb0, regvalue, cur_col, wrap)
916#endif
917
918#if AIC_DEBUG_REGISTERS
919ahd_reg_print_t ahd_ccscbram_print; 779ahd_reg_print_t ahd_ccscbram_print;
920#else 780#else
921#define ahd_ccscbram_print(regvalue, cur_col, wrap) \ 781#define ahd_ccscbram_print(regvalue, cur_col, wrap) \
@@ -930,13 +790,6 @@ ahd_reg_print_t ahd_brddat_print;
930#endif 790#endif
931 791
932#if AIC_DEBUG_REGISTERS 792#if AIC_DEBUG_REGISTERS
933ahd_reg_print_t ahd_brdctl_print;
934#else
935#define ahd_brdctl_print(regvalue, cur_col, wrap) \
936 ahd_print_register(NULL, 0, "BRDCTL", 0xb9, regvalue, cur_col, wrap)
937#endif
938
939#if AIC_DEBUG_REGISTERS
940ahd_reg_print_t ahd_seeadr_print; 793ahd_reg_print_t ahd_seeadr_print;
941#else 794#else
942#define ahd_seeadr_print(regvalue, cur_col, wrap) \ 795#define ahd_seeadr_print(regvalue, cur_col, wrap) \
@@ -972,13 +825,6 @@ ahd_reg_print_t ahd_dspdatactl_print;
972#endif 825#endif
973 826
974#if AIC_DEBUG_REGISTERS 827#if AIC_DEBUG_REGISTERS
975ahd_reg_print_t ahd_dfdat_print;
976#else
977#define ahd_dfdat_print(regvalue, cur_col, wrap) \
978 ahd_print_register(NULL, 0, "DFDAT", 0xc4, regvalue, cur_col, wrap)
979#endif
980
981#if AIC_DEBUG_REGISTERS
982ahd_reg_print_t ahd_dspselect_print; 828ahd_reg_print_t ahd_dspselect_print;
983#else 829#else
984#define ahd_dspselect_print(regvalue, cur_col, wrap) \ 830#define ahd_dspselect_print(regvalue, cur_col, wrap) \
@@ -1000,13 +846,6 @@ ahd_reg_print_t ahd_seqctl0_print;
1000#endif 846#endif
1001 847
1002#if AIC_DEBUG_REGISTERS 848#if AIC_DEBUG_REGISTERS
1003ahd_reg_print_t ahd_flags_print;
1004#else
1005#define ahd_flags_print(regvalue, cur_col, wrap) \
1006 ahd_print_register(NULL, 0, "FLAGS", 0xd8, regvalue, cur_col, wrap)
1007#endif
1008
1009#if AIC_DEBUG_REGISTERS
1010ahd_reg_print_t ahd_seqintctl_print; 849ahd_reg_print_t ahd_seqintctl_print;
1011#else 850#else
1012#define ahd_seqintctl_print(regvalue, cur_col, wrap) \ 851#define ahd_seqintctl_print(regvalue, cur_col, wrap) \
@@ -1014,13 +853,6 @@ ahd_reg_print_t ahd_seqintctl_print;
1014#endif 853#endif
1015 854
1016#if AIC_DEBUG_REGISTERS 855#if AIC_DEBUG_REGISTERS
1017ahd_reg_print_t ahd_seqram_print;
1018#else
1019#define ahd_seqram_print(regvalue, cur_col, wrap) \
1020 ahd_print_register(NULL, 0, "SEQRAM", 0xda, regvalue, cur_col, wrap)
1021#endif
1022
1023#if AIC_DEBUG_REGISTERS
1024ahd_reg_print_t ahd_prgmcnt_print; 856ahd_reg_print_t ahd_prgmcnt_print;
1025#else 857#else
1026#define ahd_prgmcnt_print(regvalue, cur_col, wrap) \ 858#define ahd_prgmcnt_print(regvalue, cur_col, wrap) \
@@ -1028,41 +860,6 @@ ahd_reg_print_t ahd_prgmcnt_print;
1028#endif 860#endif
1029 861
1030#if AIC_DEBUG_REGISTERS 862#if AIC_DEBUG_REGISTERS
1031ahd_reg_print_t ahd_accum_print;
1032#else
1033#define ahd_accum_print(regvalue, cur_col, wrap) \
1034 ahd_print_register(NULL, 0, "ACCUM", 0xe0, regvalue, cur_col, wrap)
1035#endif
1036
1037#if AIC_DEBUG_REGISTERS
1038ahd_reg_print_t ahd_sindex_print;
1039#else
1040#define ahd_sindex_print(regvalue, cur_col, wrap) \
1041 ahd_print_register(NULL, 0, "SINDEX", 0xe2, regvalue, cur_col, wrap)
1042#endif
1043
1044#if AIC_DEBUG_REGISTERS
1045ahd_reg_print_t ahd_dindex_print;
1046#else
1047#define ahd_dindex_print(regvalue, cur_col, wrap) \
1048 ahd_print_register(NULL, 0, "DINDEX", 0xe4, regvalue, cur_col, wrap)
1049#endif
1050
1051#if AIC_DEBUG_REGISTERS
1052ahd_reg_print_t ahd_allones_print;
1053#else
1054#define ahd_allones_print(regvalue, cur_col, wrap) \
1055 ahd_print_register(NULL, 0, "ALLONES", 0xe8, regvalue, cur_col, wrap)
1056#endif
1057
1058#if AIC_DEBUG_REGISTERS
1059ahd_reg_print_t ahd_allzeros_print;
1060#else
1061#define ahd_allzeros_print(regvalue, cur_col, wrap) \
1062 ahd_print_register(NULL, 0, "ALLZEROS", 0xea, regvalue, cur_col, wrap)
1063#endif
1064
1065#if AIC_DEBUG_REGISTERS
1066ahd_reg_print_t ahd_none_print; 863ahd_reg_print_t ahd_none_print;
1067#else 864#else
1068#define ahd_none_print(regvalue, cur_col, wrap) \ 865#define ahd_none_print(regvalue, cur_col, wrap) \
@@ -1070,27 +867,6 @@ ahd_reg_print_t ahd_none_print;
1070#endif 867#endif
1071 868
1072#if AIC_DEBUG_REGISTERS 869#if AIC_DEBUG_REGISTERS
1073ahd_reg_print_t ahd_sindir_print;
1074#else
1075#define ahd_sindir_print(regvalue, cur_col, wrap) \
1076 ahd_print_register(NULL, 0, "SINDIR", 0xec, regvalue, cur_col, wrap)
1077#endif
1078
1079#if AIC_DEBUG_REGISTERS
1080ahd_reg_print_t ahd_dindir_print;
1081#else
1082#define ahd_dindir_print(regvalue, cur_col, wrap) \
1083 ahd_print_register(NULL, 0, "DINDIR", 0xed, regvalue, cur_col, wrap)
1084#endif
1085
1086#if AIC_DEBUG_REGISTERS
1087ahd_reg_print_t ahd_stack_print;
1088#else
1089#define ahd_stack_print(regvalue, cur_col, wrap) \
1090 ahd_print_register(NULL, 0, "STACK", 0xf2, regvalue, cur_col, wrap)
1091#endif
1092
1093#if AIC_DEBUG_REGISTERS
1094ahd_reg_print_t ahd_intvec1_addr_print; 870ahd_reg_print_t ahd_intvec1_addr_print;
1095#else 871#else
1096#define ahd_intvec1_addr_print(regvalue, cur_col, wrap) \ 872#define ahd_intvec1_addr_print(regvalue, cur_col, wrap) \
@@ -1126,17 +902,17 @@ ahd_reg_print_t ahd_accum_save_print;
1126#endif 902#endif
1127 903
1128#if AIC_DEBUG_REGISTERS 904#if AIC_DEBUG_REGISTERS
1129ahd_reg_print_t ahd_sram_base_print; 905ahd_reg_print_t ahd_waiting_scb_tails_print;
1130#else 906#else
1131#define ahd_sram_base_print(regvalue, cur_col, wrap) \ 907#define ahd_waiting_scb_tails_print(regvalue, cur_col, wrap) \
1132 ahd_print_register(NULL, 0, "SRAM_BASE", 0x100, regvalue, cur_col, wrap) 908 ahd_print_register(NULL, 0, "WAITING_SCB_TAILS", 0x100, regvalue, cur_col, wrap)
1133#endif 909#endif
1134 910
1135#if AIC_DEBUG_REGISTERS 911#if AIC_DEBUG_REGISTERS
1136ahd_reg_print_t ahd_waiting_scb_tails_print; 912ahd_reg_print_t ahd_sram_base_print;
1137#else 913#else
1138#define ahd_waiting_scb_tails_print(regvalue, cur_col, wrap) \ 914#define ahd_sram_base_print(regvalue, cur_col, wrap) \
1139 ahd_print_register(NULL, 0, "WAITING_SCB_TAILS", 0x100, regvalue, cur_col, wrap) 915 ahd_print_register(NULL, 0, "SRAM_BASE", 0x100, regvalue, cur_col, wrap)
1140#endif 916#endif
1141 917
1142#if AIC_DEBUG_REGISTERS 918#if AIC_DEBUG_REGISTERS
@@ -1224,13 +1000,6 @@ ahd_reg_print_t ahd_msg_out_print;
1224#endif 1000#endif
1225 1001
1226#if AIC_DEBUG_REGISTERS 1002#if AIC_DEBUG_REGISTERS
1227ahd_reg_print_t ahd_dmaparams_print;
1228#else
1229#define ahd_dmaparams_print(regvalue, cur_col, wrap) \
1230 ahd_print_register(NULL, 0, "DMAPARAMS", 0x138, regvalue, cur_col, wrap)
1231#endif
1232
1233#if AIC_DEBUG_REGISTERS
1234ahd_reg_print_t ahd_seq_flags_print; 1003ahd_reg_print_t ahd_seq_flags_print;
1235#else 1004#else
1236#define ahd_seq_flags_print(regvalue, cur_col, wrap) \ 1005#define ahd_seq_flags_print(regvalue, cur_col, wrap) \
@@ -1238,20 +1007,6 @@ ahd_reg_print_t ahd_seq_flags_print;
1238#endif 1007#endif
1239 1008
1240#if AIC_DEBUG_REGISTERS 1009#if AIC_DEBUG_REGISTERS
1241ahd_reg_print_t ahd_saved_scsiid_print;
1242#else
1243#define ahd_saved_scsiid_print(regvalue, cur_col, wrap) \
1244 ahd_print_register(NULL, 0, "SAVED_SCSIID", 0x13a, regvalue, cur_col, wrap)
1245#endif
1246
1247#if AIC_DEBUG_REGISTERS
1248ahd_reg_print_t ahd_saved_lun_print;
1249#else
1250#define ahd_saved_lun_print(regvalue, cur_col, wrap) \
1251 ahd_print_register(NULL, 0, "SAVED_LUN", 0x13b, regvalue, cur_col, wrap)
1252#endif
1253
1254#if AIC_DEBUG_REGISTERS
1255ahd_reg_print_t ahd_lastphase_print; 1010ahd_reg_print_t ahd_lastphase_print;
1256#else 1011#else
1257#define ahd_lastphase_print(regvalue, cur_col, wrap) \ 1012#define ahd_lastphase_print(regvalue, cur_col, wrap) \
@@ -1273,20 +1028,6 @@ ahd_reg_print_t ahd_kernel_tqinpos_print;
1273#endif 1028#endif
1274 1029
1275#if AIC_DEBUG_REGISTERS 1030#if AIC_DEBUG_REGISTERS
1276ahd_reg_print_t ahd_tqinpos_print;
1277#else
1278#define ahd_tqinpos_print(regvalue, cur_col, wrap) \
1279 ahd_print_register(NULL, 0, "TQINPOS", 0x13f, regvalue, cur_col, wrap)
1280#endif
1281
1282#if AIC_DEBUG_REGISTERS
1283ahd_reg_print_t ahd_shared_data_addr_print;
1284#else
1285#define ahd_shared_data_addr_print(regvalue, cur_col, wrap) \
1286 ahd_print_register(NULL, 0, "SHARED_DATA_ADDR", 0x140, regvalue, cur_col, wrap)
1287#endif
1288
1289#if AIC_DEBUG_REGISTERS
1290ahd_reg_print_t ahd_qoutfifo_next_addr_print; 1031ahd_reg_print_t ahd_qoutfifo_next_addr_print;
1291#else 1032#else
1292#define ahd_qoutfifo_next_addr_print(regvalue, cur_col, wrap) \ 1033#define ahd_qoutfifo_next_addr_print(regvalue, cur_col, wrap) \
@@ -1294,20 +1035,6 @@ ahd_reg_print_t ahd_qoutfifo_next_addr_print;
1294#endif 1035#endif
1295 1036
1296#if AIC_DEBUG_REGISTERS 1037#if AIC_DEBUG_REGISTERS
1297ahd_reg_print_t ahd_arg_1_print;
1298#else
1299#define ahd_arg_1_print(regvalue, cur_col, wrap) \
1300 ahd_print_register(NULL, 0, "ARG_1", 0x148, regvalue, cur_col, wrap)
1301#endif
1302
1303#if AIC_DEBUG_REGISTERS
1304ahd_reg_print_t ahd_arg_2_print;
1305#else
1306#define ahd_arg_2_print(regvalue, cur_col, wrap) \
1307 ahd_print_register(NULL, 0, "ARG_2", 0x149, regvalue, cur_col, wrap)
1308#endif
1309
1310#if AIC_DEBUG_REGISTERS
1311ahd_reg_print_t ahd_last_msg_print; 1038ahd_reg_print_t ahd_last_msg_print;
1312#else 1039#else
1313#define ahd_last_msg_print(regvalue, cur_col, wrap) \ 1040#define ahd_last_msg_print(regvalue, cur_col, wrap) \
@@ -1406,13 +1133,6 @@ ahd_reg_print_t ahd_mk_message_scsiid_print;
1406#endif 1133#endif
1407 1134
1408#if AIC_DEBUG_REGISTERS 1135#if AIC_DEBUG_REGISTERS
1409ahd_reg_print_t ahd_scb_residual_datacnt_print;
1410#else
1411#define ahd_scb_residual_datacnt_print(regvalue, cur_col, wrap) \
1412 ahd_print_register(NULL, 0, "SCB_RESIDUAL_DATACNT", 0x180, regvalue, cur_col, wrap)
1413#endif
1414
1415#if AIC_DEBUG_REGISTERS
1416ahd_reg_print_t ahd_scb_base_print; 1136ahd_reg_print_t ahd_scb_base_print;
1417#else 1137#else
1418#define ahd_scb_base_print(regvalue, cur_col, wrap) \ 1138#define ahd_scb_base_print(regvalue, cur_col, wrap) \
@@ -1420,17 +1140,10 @@ ahd_reg_print_t ahd_scb_base_print;
1420#endif 1140#endif
1421 1141
1422#if AIC_DEBUG_REGISTERS 1142#if AIC_DEBUG_REGISTERS
1423ahd_reg_print_t ahd_scb_residual_sgptr_print; 1143ahd_reg_print_t ahd_scb_residual_datacnt_print;
1424#else
1425#define ahd_scb_residual_sgptr_print(regvalue, cur_col, wrap) \
1426 ahd_print_register(NULL, 0, "SCB_RESIDUAL_SGPTR", 0x184, regvalue, cur_col, wrap)
1427#endif
1428
1429#if AIC_DEBUG_REGISTERS
1430ahd_reg_print_t ahd_scb_scsi_status_print;
1431#else 1144#else
1432#define ahd_scb_scsi_status_print(regvalue, cur_col, wrap) \ 1145#define ahd_scb_residual_datacnt_print(regvalue, cur_col, wrap) \
1433 ahd_print_register(NULL, 0, "SCB_SCSI_STATUS", 0x188, regvalue, cur_col, wrap) 1146 ahd_print_register(NULL, 0, "SCB_RESIDUAL_DATACNT", 0x180, regvalue, cur_col, wrap)
1434#endif 1147#endif
1435 1148
1436#if AIC_DEBUG_REGISTERS 1149#if AIC_DEBUG_REGISTERS
@@ -1476,13 +1189,6 @@ ahd_reg_print_t ahd_scb_task_attribute_print;
1476#endif 1189#endif
1477 1190
1478#if AIC_DEBUG_REGISTERS 1191#if AIC_DEBUG_REGISTERS
1479ahd_reg_print_t ahd_scb_cdb_len_print;
1480#else
1481#define ahd_scb_cdb_len_print(regvalue, cur_col, wrap) \
1482 ahd_print_register(NULL, 0, "SCB_CDB_LEN", 0x196, regvalue, cur_col, wrap)
1483#endif
1484
1485#if AIC_DEBUG_REGISTERS
1486ahd_reg_print_t ahd_scb_task_management_print; 1192ahd_reg_print_t ahd_scb_task_management_print;
1487#else 1193#else
1488#define ahd_scb_task_management_print(regvalue, cur_col, wrap) \ 1194#define ahd_scb_task_management_print(regvalue, cur_col, wrap) \
@@ -1518,13 +1224,6 @@ ahd_reg_print_t ahd_scb_busaddr_print;
1518#endif 1224#endif
1519 1225
1520#if AIC_DEBUG_REGISTERS 1226#if AIC_DEBUG_REGISTERS
1521ahd_reg_print_t ahd_scb_next_print;
1522#else
1523#define ahd_scb_next_print(regvalue, cur_col, wrap) \
1524 ahd_print_register(NULL, 0, "SCB_NEXT", 0x1ac, regvalue, cur_col, wrap)
1525#endif
1526
1527#if AIC_DEBUG_REGISTERS
1528ahd_reg_print_t ahd_scb_next2_print; 1227ahd_reg_print_t ahd_scb_next2_print;
1529#else 1228#else
1530#define ahd_scb_next2_print(regvalue, cur_col, wrap) \ 1229#define ahd_scb_next2_print(regvalue, cur_col, wrap) \
@@ -1717,10 +1416,10 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
1717 1416
1718#define SG_CACHE_PRE 0x1b 1417#define SG_CACHE_PRE 0x1b
1719 1418
1720#define TYPEPTR 0x20
1721
1722#define LQIN 0x20 1419#define LQIN 0x20
1723 1420
1421#define TYPEPTR 0x20
1422
1724#define TAGPTR 0x21 1423#define TAGPTR 0x21
1725 1424
1726#define LUNPTR 0x22 1425#define LUNPTR 0x22
@@ -1780,6 +1479,14 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
1780#define SINGLECMD 0x02 1479#define SINGLECMD 0x02
1781#define ABORTPENDING 0x01 1480#define ABORTPENDING 0x01
1782 1481
1482#define SCSBIST0 0x39
1483#define GSBISTERR 0x40
1484#define GSBISTDONE 0x20
1485#define GSBISTRUN 0x10
1486#define OSBISTERR 0x04
1487#define OSBISTDONE 0x02
1488#define OSBISTRUN 0x01
1489
1783#define LQCTL2 0x39 1490#define LQCTL2 0x39
1784#define LQIRETRY 0x80 1491#define LQIRETRY 0x80
1785#define LQICONTINUE 0x40 1492#define LQICONTINUE 0x40
@@ -1790,13 +1497,10 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
1790#define LQOTOIDLE 0x02 1497#define LQOTOIDLE 0x02
1791#define LQOPAUSE 0x01 1498#define LQOPAUSE 0x01
1792 1499
1793#define SCSBIST0 0x39 1500#define SCSBIST1 0x3a
1794#define GSBISTERR 0x40 1501#define NTBISTERR 0x04
1795#define GSBISTDONE 0x20 1502#define NTBISTDONE 0x02
1796#define GSBISTRUN 0x10 1503#define NTBISTRUN 0x01
1797#define OSBISTERR 0x04
1798#define OSBISTDONE 0x02
1799#define OSBISTRUN 0x01
1800 1504
1801#define SCSISEQ0 0x3a 1505#define SCSISEQ0 0x3a
1802#define TEMODEO 0x80 1506#define TEMODEO 0x80
@@ -1805,15 +1509,8 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
1805#define FORCEBUSFREE 0x10 1509#define FORCEBUSFREE 0x10
1806#define SCSIRSTO 0x01 1510#define SCSIRSTO 0x01
1807 1511
1808#define SCSBIST1 0x3a
1809#define NTBISTERR 0x04
1810#define NTBISTDONE 0x02
1811#define NTBISTRUN 0x01
1812
1813#define SCSISEQ1 0x3b 1512#define SCSISEQ1 0x3b
1814 1513
1815#define BUSINITID 0x3c
1816
1817#define SXFRCTL0 0x3c 1514#define SXFRCTL0 0x3c
1818#define DFON 0x80 1515#define DFON 0x80
1819#define DFPEXP 0x40 1516#define DFPEXP 0x40
@@ -1822,6 +1519,8 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
1822 1519
1823#define DLCOUNT 0x3c 1520#define DLCOUNT 0x3c
1824 1521
1522#define BUSINITID 0x3c
1523
1825#define SXFRCTL1 0x3d 1524#define SXFRCTL1 0x3d
1826#define BITBUCKET 0x80 1525#define BITBUCKET 0x80
1827#define ENSACHK 0x40 1526#define ENSACHK 0x40
@@ -1846,8 +1545,6 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
1846#define CURRFIFO_1 0x01 1545#define CURRFIFO_1 0x01
1847#define CURRFIFO_0 0x00 1546#define CURRFIFO_0 0x00
1848 1547
1849#define MULTARGID 0x40
1850
1851#define SCSISIGO 0x40 1548#define SCSISIGO 0x40
1852#define CDO 0x80 1549#define CDO 0x80
1853#define IOO 0x40 1550#define IOO 0x40
@@ -1858,6 +1555,8 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
1858#define REQO 0x02 1555#define REQO 0x02
1859#define ACKO 0x01 1556#define ACKO 0x01
1860 1557
1558#define MULTARGID 0x40
1559
1861#define SCSISIGI 0x41 1560#define SCSISIGI 0x41
1862#define ATNI 0x10 1561#define ATNI 0x10
1863#define SELI 0x08 1562#define SELI 0x08
@@ -1904,6 +1603,15 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
1904#define ENAB20 0x04 1603#define ENAB20 0x04
1905#define SELWIDE 0x02 1604#define SELWIDE 0x02
1906 1605
1606#define CLRSINT0 0x4b
1607#define CLRSELDO 0x40
1608#define CLRSELDI 0x20
1609#define CLRSELINGO 0x10
1610#define CLRIOERR 0x08
1611#define CLROVERRUN 0x04
1612#define CLRSPIORDY 0x02
1613#define CLRARBDO 0x01
1614
1907#define SSTAT0 0x4b 1615#define SSTAT0 0x4b
1908#define TARGET 0x80 1616#define TARGET 0x80
1909#define SELDO 0x40 1617#define SELDO 0x40
@@ -1923,14 +1631,14 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
1923#define ENSPIORDY 0x02 1631#define ENSPIORDY 0x02
1924#define ENARBDO 0x01 1632#define ENARBDO 0x01
1925 1633
1926#define CLRSINT0 0x4b 1634#define CLRSINT1 0x4c
1927#define CLRSELDO 0x40 1635#define CLRSELTIMEO 0x80
1928#define CLRSELDI 0x20 1636#define CLRATNO 0x40
1929#define CLRSELINGO 0x10 1637#define CLRSCSIRSTI 0x20
1930#define CLRIOERR 0x08 1638#define CLRBUSFREE 0x08
1931#define CLROVERRUN 0x04 1639#define CLRSCSIPERR 0x04
1932#define CLRSPIORDY 0x02 1640#define CLRSTRB2FAST 0x02
1933#define CLRARBDO 0x01 1641#define CLRREQINIT 0x01
1934 1642
1935#define SSTAT1 0x4c 1643#define SSTAT1 0x4c
1936#define SELTO 0x80 1644#define SELTO 0x80
@@ -1942,15 +1650,6 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
1942#define STRB2FAST 0x02 1650#define STRB2FAST 0x02
1943#define REQINIT 0x01 1651#define REQINIT 0x01
1944 1652
1945#define CLRSINT1 0x4c
1946#define CLRSELTIMEO 0x80
1947#define CLRATNO 0x40
1948#define CLRSCSIRSTI 0x20
1949#define CLRBUSFREE 0x08
1950#define CLRSCSIPERR 0x04
1951#define CLRSTRB2FAST 0x02
1952#define CLRREQINIT 0x01
1953
1954#define SSTAT2 0x4d 1653#define SSTAT2 0x4d
1955#define BUSFREETIME 0xc0 1654#define BUSFREETIME 0xc0
1956#define NONPACKREQ 0x20 1655#define NONPACKREQ 0x20
@@ -1998,14 +1697,6 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
1998#define LQIATNLQ 0x02 1697#define LQIATNLQ 0x02
1999#define LQIATNCMD 0x01 1698#define LQIATNCMD 0x01
2000 1699
2001#define LQIMODE0 0x50
2002#define ENLQIATNQASK 0x20
2003#define ENLQICRCT1 0x10
2004#define ENLQICRCT2 0x08
2005#define ENLQIBADLQT 0x04
2006#define ENLQIATNLQ 0x02
2007#define ENLQIATNCMD 0x01
2008
2009#define CLRLQIINT0 0x50 1700#define CLRLQIINT0 0x50
2010#define CLRLQIATNQAS 0x20 1701#define CLRLQIATNQAS 0x20
2011#define CLRLQICRCT1 0x10 1702#define CLRLQICRCT1 0x10
@@ -2014,6 +1705,14 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2014#define CLRLQIATNLQ 0x02 1705#define CLRLQIATNLQ 0x02
2015#define CLRLQIATNCMD 0x01 1706#define CLRLQIATNCMD 0x01
2016 1707
1708#define LQIMODE0 0x50
1709#define ENLQIATNQASK 0x20
1710#define ENLQICRCT1 0x10
1711#define ENLQICRCT2 0x08
1712#define ENLQIBADLQT 0x04
1713#define ENLQIATNLQ 0x02
1714#define ENLQIATNCMD 0x01
1715
2017#define LQIMODE1 0x51 1716#define LQIMODE1 0x51
2018#define ENLQIPHASE_LQ 0x80 1717#define ENLQIPHASE_LQ 0x80
2019#define ENLQIPHASE_NLQ 0x40 1718#define ENLQIPHASE_NLQ 0x40
@@ -2160,6 +1859,8 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2160#define CFG4ICMD 0x02 1859#define CFG4ICMD 0x02
2161#define CFG4TCMD 0x01 1860#define CFG4TCMD 0x01
2162 1861
1862#define CURRSCB 0x5c
1863
2163#define SEQIMODE 0x5c 1864#define SEQIMODE 0x5c
2164#define ENCTXTDONE 0x40 1865#define ENCTXTDONE 0x40
2165#define ENSAVEPTRS 0x20 1866#define ENSAVEPTRS 0x20
@@ -2169,8 +1870,6 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2169#define ENCFG4ICMD 0x02 1870#define ENCFG4ICMD 0x02
2170#define ENCFG4TCMD 0x01 1871#define ENCFG4TCMD 0x01
2171 1872
2172#define CURRSCB 0x5c
2173
2174#define MDFFSTAT 0x5d 1873#define MDFFSTAT 0x5d
2175#define SHCNTNEGATIVE 0x40 1874#define SHCNTNEGATIVE 0x40
2176#define SHCNTMINUS1 0x20 1875#define SHCNTMINUS1 0x20
@@ -2185,29 +1884,29 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2185 1884
2186#define DFFTAG 0x5e 1885#define DFFTAG 0x5e
2187 1886
1887#define LASTSCB 0x5e
1888
2188#define SCSITEST 0x5e 1889#define SCSITEST 0x5e
2189#define CNTRTEST 0x08 1890#define CNTRTEST 0x08
2190#define SEL_TXPLL_DEBUG 0x04 1891#define SEL_TXPLL_DEBUG 0x04
2191 1892
2192#define LASTSCB 0x5e
2193
2194#define IOPDNCTL 0x5f 1893#define IOPDNCTL 0x5f
2195#define DISABLE_OE 0x80 1894#define DISABLE_OE 0x80
2196#define PDN_IDIST 0x04 1895#define PDN_IDIST 0x04
2197#define PDN_DIFFSENSE 0x01 1896#define PDN_DIFFSENSE 0x01
2198 1897
2199#define DGRPCRCI 0x60
2200
2201#define SHADDR 0x60 1898#define SHADDR 0x60
2202 1899
2203#define NEGOADDR 0x60 1900#define NEGOADDR 0x60
2204 1901
2205#define NEGPERIOD 0x61 1902#define DGRPCRCI 0x60
2206 1903
2207#define NEGOFFSET 0x62 1904#define NEGPERIOD 0x61
2208 1905
2209#define PACKCRCI 0x62 1906#define PACKCRCI 0x62
2210 1907
1908#define NEGOFFSET 0x62
1909
2211#define NEGPPROPTS 0x63 1910#define NEGPPROPTS 0x63
2212#define PPROPT_PACE 0x08 1911#define PPROPT_PACE 0x08
2213#define PPROPT_QAS 0x04 1912#define PPROPT_QAS 0x04
@@ -2253,8 +1952,6 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2253 1952
2254#define SELOID 0x6b 1953#define SELOID 0x6b
2255 1954
2256#define FAIRNESS 0x6c
2257
2258#define PLL400CTL0 0x6c 1955#define PLL400CTL0 0x6c
2259#define PLL_VCOSEL 0x80 1956#define PLL_VCOSEL 0x80
2260#define PLL_PWDN 0x40 1957#define PLL_PWDN 0x40
@@ -2264,6 +1961,8 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2264#define PLL_DLPF 0x02 1961#define PLL_DLPF 0x02
2265#define PLL_ENFBM 0x01 1962#define PLL_ENFBM 0x01
2266 1963
1964#define FAIRNESS 0x6c
1965
2267#define PLL400CTL1 0x6d 1966#define PLL400CTL1 0x6d
2268#define PLL_CNTEN 0x80 1967#define PLL_CNTEN 0x80
2269#define PLL_CNTCLR 0x40 1968#define PLL_CNTCLR 0x40
@@ -2275,25 +1974,25 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2275 1974
2276#define HADDR 0x70 1975#define HADDR 0x70
2277 1976
2278#define HODMAADR 0x70
2279
2280#define PLLDELAY 0x70 1977#define PLLDELAY 0x70
2281#define SPLIT_DROP_REQ 0x80 1978#define SPLIT_DROP_REQ 0x80
2282 1979
2283#define HCNT 0x78 1980#define HODMAADR 0x70
2284 1981
2285#define HODMACNT 0x78 1982#define HODMACNT 0x78
2286 1983
2287#define HODMAEN 0x7a 1984#define HCNT 0x78
2288 1985
2289#define SGHADDR 0x7c 1986#define HODMAEN 0x7a
2290 1987
2291#define SCBHADDR 0x7c 1988#define SCBHADDR 0x7c
2292 1989
2293#define SGHCNT 0x84 1990#define SGHADDR 0x7c
2294 1991
2295#define SCBHCNT 0x84 1992#define SCBHCNT 0x84
2296 1993
1994#define SGHCNT 0x84
1995
2297#define DFF_THRSH 0x88 1996#define DFF_THRSH 0x88
2298#define WR_DFTHRSH 0x70 1997#define WR_DFTHRSH 0x70
2299#define RD_DFTHRSH 0x07 1998#define RD_DFTHRSH 0x07
@@ -2326,10 +2025,6 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2326 2025
2327#define CMCRXMSG0 0x90 2026#define CMCRXMSG0 0x90
2328 2027
2329#define OVLYRXMSG0 0x90
2330
2331#define DCHRXMSG0 0x90
2332
2333#define ROENABLE 0x90 2028#define ROENABLE 0x90
2334#define MSIROEN 0x20 2029#define MSIROEN 0x20
2335#define OVLYROEN 0x10 2030#define OVLYROEN 0x10
@@ -2338,11 +2033,11 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2338#define DCH1ROEN 0x02 2033#define DCH1ROEN 0x02
2339#define DCH0ROEN 0x01 2034#define DCH0ROEN 0x01
2340 2035
2341#define OVLYRXMSG1 0x91 2036#define OVLYRXMSG0 0x90
2342 2037
2343#define CMCRXMSG1 0x91 2038#define DCHRXMSG0 0x90
2344 2039
2345#define DCHRXMSG1 0x91 2040#define OVLYRXMSG1 0x91
2346 2041
2347#define NSENABLE 0x91 2042#define NSENABLE 0x91
2348#define MSINSEN 0x20 2043#define MSINSEN 0x20
@@ -2352,6 +2047,10 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2352#define DCH1NSEN 0x02 2047#define DCH1NSEN 0x02
2353#define DCH0NSEN 0x01 2048#define DCH0NSEN 0x01
2354 2049
2050#define CMCRXMSG1 0x91
2051
2052#define DCHRXMSG1 0x91
2053
2355#define DCHRXMSG2 0x92 2054#define DCHRXMSG2 0x92
2356 2055
2357#define CMCRXMSG2 0x92 2056#define CMCRXMSG2 0x92
@@ -2375,24 +2074,24 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2375#define TSCSERREN 0x02 2074#define TSCSERREN 0x02
2376#define CMPABCDIS 0x01 2075#define CMPABCDIS 0x01
2377 2076
2378#define CMCSEQBCNT 0x94
2379
2380#define OVLYSEQBCNT 0x94 2077#define OVLYSEQBCNT 0x94
2381 2078
2382#define DCHSEQBCNT 0x94 2079#define DCHSEQBCNT 0x94
2383 2080
2081#define CMCSEQBCNT 0x94
2082
2083#define CMCSPLTSTAT0 0x96
2084
2384#define DCHSPLTSTAT0 0x96 2085#define DCHSPLTSTAT0 0x96
2385 2086
2386#define OVLYSPLTSTAT0 0x96 2087#define OVLYSPLTSTAT0 0x96
2387 2088
2388#define CMCSPLTSTAT0 0x96 2089#define CMCSPLTSTAT1 0x97
2389 2090
2390#define OVLYSPLTSTAT1 0x97 2091#define OVLYSPLTSTAT1 0x97
2391 2092
2392#define DCHSPLTSTAT1 0x97 2093#define DCHSPLTSTAT1 0x97
2393 2094
2394#define CMCSPLTSTAT1 0x97
2395
2396#define SGRXMSG0 0x98 2095#define SGRXMSG0 0x98
2397#define CDNUM 0xf8 2096#define CDNUM 0xf8
2398#define CFNUM 0x07 2097#define CFNUM 0x07
@@ -2420,15 +2119,18 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2420#define TAG_NUM 0x1f 2119#define TAG_NUM 0x1f
2421#define RLXORD 0x10 2120#define RLXORD 0x10
2422 2121
2122#define SGSEQBCNT 0x9c
2123
2423#define SLVSPLTOUTATTR0 0x9c 2124#define SLVSPLTOUTATTR0 0x9c
2424#define LOWER_BCNT 0xff 2125#define LOWER_BCNT 0xff
2425 2126
2426#define SGSEQBCNT 0x9c
2427
2428#define SLVSPLTOUTATTR1 0x9d 2127#define SLVSPLTOUTATTR1 0x9d
2429#define CMPLT_DNUM 0xf8 2128#define CMPLT_DNUM 0xf8
2430#define CMPLT_FNUM 0x07 2129#define CMPLT_FNUM 0x07
2431 2130
2131#define SLVSPLTOUTATTR2 0x9e
2132#define CMPLT_BNUM 0xff
2133
2432#define SGSPLTSTAT0 0x9e 2134#define SGSPLTSTAT0 0x9e
2433#define STAETERM 0x80 2135#define STAETERM 0x80
2434#define SCBCERR 0x40 2136#define SCBCERR 0x40
@@ -2439,9 +2141,6 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2439#define RXSCEMSG 0x02 2141#define RXSCEMSG 0x02
2440#define RXSPLTRSP 0x01 2142#define RXSPLTRSP 0x01
2441 2143
2442#define SLVSPLTOUTATTR2 0x9e
2443#define CMPLT_BNUM 0xff
2444
2445#define SGSPLTSTAT1 0x9f 2144#define SGSPLTSTAT1 0x9f
2446#define RXDATABUCKET 0x01 2145#define RXDATABUCKET 0x01
2447 2146
@@ -2497,10 +2196,10 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2497 2196
2498#define CCSGADDR 0xac 2197#define CCSGADDR 0xac
2499 2198
2500#define CCSCBADDR 0xac
2501
2502#define CCSCBADR_BK 0xac 2199#define CCSCBADR_BK 0xac
2503 2200
2201#define CCSCBADDR 0xac
2202
2504#define CMC_RAMBIST 0xad 2203#define CMC_RAMBIST 0xad
2505#define SG_ELEMENT_SIZE 0x80 2204#define SG_ELEMENT_SIZE 0x80
2506#define SCBRAMBIST_FAIL 0x40 2205#define SCBRAMBIST_FAIL 0x40
@@ -2554,9 +2253,9 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2554#define SEEDAT 0xbc 2253#define SEEDAT 0xbc
2555 2254
2556#define SEECTL 0xbe 2255#define SEECTL 0xbe
2557#define SEEOP_EWDS 0x40
2558#define SEEOP_WALL 0x40 2256#define SEEOP_WALL 0x40
2559#define SEEOP_EWEN 0x40 2257#define SEEOP_EWEN 0x40
2258#define SEEOP_EWDS 0x40
2560#define SEEOPCODE 0x70 2259#define SEEOPCODE 0x70
2561#define SEERST 0x02 2260#define SEERST 0x02
2562#define SEESTART 0x01 2261#define SEESTART 0x01
@@ -2573,25 +2272,25 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2573 2272
2574#define SCBCNT 0xbf 2273#define SCBCNT 0xbf
2575 2274
2275#define DFWADDR 0xc0
2276
2576#define DSPFLTRCTL 0xc0 2277#define DSPFLTRCTL 0xc0
2577#define FLTRDISABLE 0x20 2278#define FLTRDISABLE 0x20
2578#define EDGESENSE 0x10 2279#define EDGESENSE 0x10
2579#define DSPFCNTSEL 0x0f 2280#define DSPFCNTSEL 0x0f
2580 2281
2581#define DFWADDR 0xc0
2582
2583#define DSPDATACTL 0xc1 2282#define DSPDATACTL 0xc1
2584#define BYPASSENAB 0x80 2283#define BYPASSENAB 0x80
2585#define DESQDIS 0x10 2284#define DESQDIS 0x10
2586#define RCVROFFSTDIS 0x04 2285#define RCVROFFSTDIS 0x04
2587#define XMITOFFSTDIS 0x02 2286#define XMITOFFSTDIS 0x02
2588 2287
2288#define DFRADDR 0xc2
2289
2589#define DSPREQCTL 0xc2 2290#define DSPREQCTL 0xc2
2590#define MANREQCTL 0xc0 2291#define MANREQCTL 0xc0
2591#define MANREQDLY 0x3f 2292#define MANREQDLY 0x3f
2592 2293
2593#define DFRADDR 0xc2
2594
2595#define DSPACKCTL 0xc3 2294#define DSPACKCTL 0xc3
2596#define MANACKCTL 0xc0 2295#define MANACKCTL 0xc0
2597#define MANACKDLY 0x3f 2296#define MANACKDLY 0x3f
@@ -2612,14 +2311,14 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2612 2311
2613#define WRTBIASCALC 0xc7 2312#define WRTBIASCALC 0xc7
2614 2313
2615#define DFPTRS 0xc8
2616
2617#define RCVRBIASCALC 0xc8 2314#define RCVRBIASCALC 0xc8
2618 2315
2619#define DFBKPTR 0xc9 2316#define DFPTRS 0xc8
2620 2317
2621#define SKEWCALC 0xc9 2318#define SKEWCALC 0xc9
2622 2319
2320#define DFBKPTR 0xc9
2321
2623#define DFDBCTL 0xcb 2322#define DFDBCTL 0xcb
2624#define DFF_CIO_WR_RDY 0x20 2323#define DFF_CIO_WR_RDY 0x20
2625#define DFF_CIO_RD_RDY 0x10 2324#define DFF_CIO_RD_RDY 0x10
@@ -2704,12 +2403,12 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2704 2403
2705#define ACCUM_SAVE 0xfa 2404#define ACCUM_SAVE 0xfa
2706 2405
2406#define WAITING_SCB_TAILS 0x100
2407
2707#define AHD_PCI_CONFIG_BASE 0x100 2408#define AHD_PCI_CONFIG_BASE 0x100
2708 2409
2709#define SRAM_BASE 0x100 2410#define SRAM_BASE 0x100
2710 2411
2711#define WAITING_SCB_TAILS 0x100
2712
2713#define WAITING_TID_HEAD 0x120 2412#define WAITING_TID_HEAD 0x120
2714 2413
2715#define WAITING_TID_TAIL 0x122 2414#define WAITING_TID_TAIL 0x122
@@ -2738,8 +2437,8 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2738#define PRELOADEN 0x80 2437#define PRELOADEN 0x80
2739#define WIDEODD 0x40 2438#define WIDEODD 0x40
2740#define SCSIEN 0x20 2439#define SCSIEN 0x20
2741#define SDMAENACK 0x10
2742#define SDMAEN 0x10 2440#define SDMAEN 0x10
2441#define SDMAENACK 0x10
2743#define HDMAEN 0x08 2442#define HDMAEN 0x08
2744#define HDMAENACK 0x08 2443#define HDMAENACK 0x08
2745#define DIRECTION 0x04 2444#define DIRECTION 0x04
@@ -2837,12 +2536,12 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2837 2536
2838#define MK_MESSAGE_SCSIID 0x162 2537#define MK_MESSAGE_SCSIID 0x162
2839 2538
2539#define SCB_BASE 0x180
2540
2840#define SCB_RESIDUAL_DATACNT 0x180 2541#define SCB_RESIDUAL_DATACNT 0x180
2841#define SCB_CDB_STORE 0x180 2542#define SCB_CDB_STORE 0x180
2842#define SCB_HOST_CDB_PTR 0x180 2543#define SCB_HOST_CDB_PTR 0x180
2843 2544
2844#define SCB_BASE 0x180
2845
2846#define SCB_RESIDUAL_SGPTR 0x184 2545#define SCB_RESIDUAL_SGPTR 0x184
2847#define SG_ADDR_MASK 0xf8 2546#define SG_ADDR_MASK 0xf8
2848#define SG_OVERRUN_RESID 0x02 2547#define SG_OVERRUN_RESID 0x02
@@ -2910,17 +2609,6 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2910#define SCB_DISCONNECTED_LISTS 0x1b8 2609#define SCB_DISCONNECTED_LISTS 0x1b8
2911 2610
2912 2611
2913#define CMD_GROUP_CODE_SHIFT 0x05
2914#define STIMESEL_MIN 0x18
2915#define STIMESEL_SHIFT 0x03
2916#define INVALID_ADDR 0x80
2917#define AHD_PRECOMP_MASK 0x07
2918#define TARGET_DATA_IN 0x01
2919#define CCSCBADDR_MAX 0x80
2920#define NUMDSPS 0x14
2921#define SEEOP_EWEN_ADDR 0xc0
2922#define AHD_ANNEXCOL_PER_DEV0 0x04
2923#define DST_MODE_SHIFT 0x04
2924#define AHD_TIMER_MAX_US 0x18ffe7 2612#define AHD_TIMER_MAX_US 0x18ffe7
2925#define AHD_TIMER_MAX_TICKS 0xffff 2613#define AHD_TIMER_MAX_TICKS 0xffff
2926#define AHD_SENSE_BUFSIZE 0x100 2614#define AHD_SENSE_BUFSIZE 0x100
@@ -2955,32 +2643,43 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2955#define LUNLEN_SINGLE_LEVEL_LUN 0x0f 2643#define LUNLEN_SINGLE_LEVEL_LUN 0x0f
2956#define NVRAM_SCB_OFFSET 0x2c 2644#define NVRAM_SCB_OFFSET 0x2c
2957#define STATUS_PKT_SENSE 0xff 2645#define STATUS_PKT_SENSE 0xff
2646#define CMD_GROUP_CODE_SHIFT 0x05
2958#define MAX_OFFSET_PACED_BUG 0x7f 2647#define MAX_OFFSET_PACED_BUG 0x7f
2959#define STIMESEL_BUG_ADJ 0x08 2648#define STIMESEL_BUG_ADJ 0x08
2649#define STIMESEL_MIN 0x18
2650#define STIMESEL_SHIFT 0x03
2960#define CCSGRAM_MAXSEGS 0x10 2651#define CCSGRAM_MAXSEGS 0x10
2652#define INVALID_ADDR 0x80
2961#define SEEOP_ERAL_ADDR 0x80 2653#define SEEOP_ERAL_ADDR 0x80
2962#define AHD_SLEWRATE_DEF_REVB 0x08 2654#define AHD_SLEWRATE_DEF_REVB 0x08
2963#define AHD_PRECOMP_CUTBACK_17 0x04 2655#define AHD_PRECOMP_CUTBACK_17 0x04
2656#define AHD_PRECOMP_MASK 0x07
2964#define SRC_MODE_SHIFT 0x00 2657#define SRC_MODE_SHIFT 0x00
2965#define PKT_OVERRUN_BUFSIZE 0x200 2658#define PKT_OVERRUN_BUFSIZE 0x200
2966#define SCB_TRANSFER_SIZE_1BYTE_LUN 0x30 2659#define SCB_TRANSFER_SIZE_1BYTE_LUN 0x30
2660#define TARGET_DATA_IN 0x01
2967#define HOST_MSG 0xff 2661#define HOST_MSG 0xff
2968#define MAX_OFFSET 0xfe 2662#define MAX_OFFSET 0xfe
2969#define BUS_16_BIT 0x01 2663#define BUS_16_BIT 0x01
2664#define CCSCBADDR_MAX 0x80
2665#define NUMDSPS 0x14
2666#define SEEOP_EWEN_ADDR 0xc0
2667#define AHD_ANNEXCOL_PER_DEV0 0x04
2668#define DST_MODE_SHIFT 0x04
2970 2669
2971 2670
2972/* Downloaded Constant Definitions */ 2671/* Downloaded Constant Definitions */
2973#define SG_SIZEOF 0x04
2974#define SG_PREFETCH_ALIGN_MASK 0x02
2975#define SG_PREFETCH_CNT_LIMIT 0x01
2976#define CACHELINE_MASK 0x07 2672#define CACHELINE_MASK 0x07
2977#define SCB_TRANSFER_SIZE 0x06 2673#define SCB_TRANSFER_SIZE 0x06
2978#define PKT_OVERRUN_BUFOFFSET 0x05 2674#define PKT_OVERRUN_BUFOFFSET 0x05
2675#define SG_SIZEOF 0x04
2979#define SG_PREFETCH_ADDR_MASK 0x03 2676#define SG_PREFETCH_ADDR_MASK 0x03
2677#define SG_PREFETCH_ALIGN_MASK 0x02
2678#define SG_PREFETCH_CNT_LIMIT 0x01
2980#define SG_PREFETCH_CNT 0x00 2679#define SG_PREFETCH_CNT 0x00
2981#define DOWNLOAD_CONST_COUNT 0x08 2680#define DOWNLOAD_CONST_COUNT 0x08
2982 2681
2983 2682
2984/* Exported Labels */ 2683/* Exported Labels */
2985#define LABEL_timer_isr 0x28b
2986#define LABEL_seq_isr 0x28f 2684#define LABEL_seq_isr 0x28f
2685#define LABEL_timer_isr 0x28b
diff --git a/drivers/scsi/aic7xxx/aic79xx_reg_print.c_shipped b/drivers/scsi/aic7xxx/aic79xx_reg_print.c_shipped
index c4c8a96bf5a3..f5ea715d6ac3 100644
--- a/drivers/scsi/aic7xxx/aic79xx_reg_print.c_shipped
+++ b/drivers/scsi/aic7xxx/aic79xx_reg_print.c_shipped
@@ -8,18 +8,6 @@
8 8
9#include "aic79xx_osm.h" 9#include "aic79xx_osm.h"
10 10
11static const ahd_reg_parse_entry_t MODE_PTR_parse_table[] = {
12 { "SRC_MODE", 0x07, 0x07 },
13 { "DST_MODE", 0x70, 0x70 }
14};
15
16int
17ahd_mode_ptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
18{
19 return (ahd_print_register(MODE_PTR_parse_table, 2, "MODE_PTR",
20 0x00, regvalue, cur_col, wrap));
21}
22
23static const ahd_reg_parse_entry_t INTSTAT_parse_table[] = { 11static const ahd_reg_parse_entry_t INTSTAT_parse_table[] = {
24 { "SPLTINT", 0x01, 0x01 }, 12 { "SPLTINT", 0x01, 0x01 },
25 { "CMDCMPLT", 0x02, 0x02 }, 13 { "CMDCMPLT", 0x02, 0x02 },
@@ -39,110 +27,6 @@ ahd_intstat_print(u_int regvalue, u_int *cur_col, u_int wrap)
39 0x01, regvalue, cur_col, wrap)); 27 0x01, regvalue, cur_col, wrap));
40} 28}
41 29
42static const ahd_reg_parse_entry_t SEQINTCODE_parse_table[] = {
43 { "NO_SEQINT", 0x00, 0xff },
44 { "BAD_PHASE", 0x01, 0xff },
45 { "SEND_REJECT", 0x02, 0xff },
46 { "PROTO_VIOLATION", 0x03, 0xff },
47 { "NO_MATCH", 0x04, 0xff },
48 { "IGN_WIDE_RES", 0x05, 0xff },
49 { "PDATA_REINIT", 0x06, 0xff },
50 { "HOST_MSG_LOOP", 0x07, 0xff },
51 { "BAD_STATUS", 0x08, 0xff },
52 { "DATA_OVERRUN", 0x09, 0xff },
53 { "MKMSG_FAILED", 0x0a, 0xff },
54 { "MISSED_BUSFREE", 0x0b, 0xff },
55 { "DUMP_CARD_STATE", 0x0c, 0xff },
56 { "ILLEGAL_PHASE", 0x0d, 0xff },
57 { "INVALID_SEQINT", 0x0e, 0xff },
58 { "CFG4ISTAT_INTR", 0x0f, 0xff },
59 { "STATUS_OVERRUN", 0x10, 0xff },
60 { "CFG4OVERRUN", 0x11, 0xff },
61 { "ENTERING_NONPACK", 0x12, 0xff },
62 { "TASKMGMT_FUNC_COMPLETE",0x13, 0xff },
63 { "TASKMGMT_CMD_CMPLT_OKAY",0x14, 0xff },
64 { "TRACEPOINT0", 0x15, 0xff },
65 { "TRACEPOINT1", 0x16, 0xff },
66 { "TRACEPOINT2", 0x17, 0xff },
67 { "TRACEPOINT3", 0x18, 0xff },
68 { "SAW_HWERR", 0x19, 0xff },
69 { "BAD_SCB_STATUS", 0x1a, 0xff }
70};
71
72int
73ahd_seqintcode_print(u_int regvalue, u_int *cur_col, u_int wrap)
74{
75 return (ahd_print_register(SEQINTCODE_parse_table, 27, "SEQINTCODE",
76 0x02, regvalue, cur_col, wrap));
77}
78
79static const ahd_reg_parse_entry_t CLRINT_parse_table[] = {
80 { "CLRSPLTINT", 0x01, 0x01 },
81 { "CLRCMDINT", 0x02, 0x02 },
82 { "CLRSEQINT", 0x04, 0x04 },
83 { "CLRSCSIINT", 0x08, 0x08 },
84 { "CLRPCIINT", 0x10, 0x10 },
85 { "CLRSWTMINT", 0x20, 0x20 },
86 { "CLRBRKADRINT", 0x40, 0x40 },
87 { "CLRHWERRINT", 0x80, 0x80 }
88};
89
90int
91ahd_clrint_print(u_int regvalue, u_int *cur_col, u_int wrap)
92{
93 return (ahd_print_register(CLRINT_parse_table, 8, "CLRINT",
94 0x03, regvalue, cur_col, wrap));
95}
96
97static const ahd_reg_parse_entry_t ERROR_parse_table[] = {
98 { "DSCTMOUT", 0x02, 0x02 },
99 { "ILLOPCODE", 0x04, 0x04 },
100 { "SQPARERR", 0x08, 0x08 },
101 { "DPARERR", 0x10, 0x10 },
102 { "MPARERR", 0x20, 0x20 },
103 { "CIOACCESFAIL", 0x40, 0x40 },
104 { "CIOPARERR", 0x80, 0x80 }
105};
106
107int
108ahd_error_print(u_int regvalue, u_int *cur_col, u_int wrap)
109{
110 return (ahd_print_register(ERROR_parse_table, 7, "ERROR",
111 0x04, regvalue, cur_col, wrap));
112}
113
114static const ahd_reg_parse_entry_t HCNTRL_parse_table[] = {
115 { "CHIPRST", 0x01, 0x01 },
116 { "CHIPRSTACK", 0x01, 0x01 },
117 { "INTEN", 0x02, 0x02 },
118 { "PAUSE", 0x04, 0x04 },
119 { "SWTIMER_START_B", 0x08, 0x08 },
120 { "SWINT", 0x10, 0x10 },
121 { "POWRDN", 0x40, 0x40 },
122 { "SEQ_RESET", 0x80, 0x80 }
123};
124
125int
126ahd_hcntrl_print(u_int regvalue, u_int *cur_col, u_int wrap)
127{
128 return (ahd_print_register(HCNTRL_parse_table, 8, "HCNTRL",
129 0x05, regvalue, cur_col, wrap));
130}
131
132int
133ahd_hnscb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap)
134{
135 return (ahd_print_register(NULL, 0, "HNSCB_QOFF",
136 0x06, regvalue, cur_col, wrap));
137}
138
139int
140ahd_hescb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap)
141{
142 return (ahd_print_register(NULL, 0, "HESCB_QOFF",
143 0x08, regvalue, cur_col, wrap));
144}
145
146static const ahd_reg_parse_entry_t HS_MAILBOX_parse_table[] = { 30static const ahd_reg_parse_entry_t HS_MAILBOX_parse_table[] = {
147 { "ENINT_COALESCE", 0x40, 0x40 }, 31 { "ENINT_COALESCE", 0x40, 0x40 },
148 { "HOST_TQINPOS", 0x80, 0x80 } 32 { "HOST_TQINPOS", 0x80, 0x80 }
@@ -170,77 +54,6 @@ ahd_seqintstat_print(u_int regvalue, u_int *cur_col, u_int wrap)
170 0x0c, regvalue, cur_col, wrap)); 54 0x0c, regvalue, cur_col, wrap));
171} 55}
172 56
173static const ahd_reg_parse_entry_t CLRSEQINTSTAT_parse_table[] = {
174 { "CLRSEQ_SPLTINT", 0x01, 0x01 },
175 { "CLRSEQ_PCIINT", 0x02, 0x02 },
176 { "CLRSEQ_SCSIINT", 0x04, 0x04 },
177 { "CLRSEQ_SEQINT", 0x08, 0x08 },
178 { "CLRSEQ_SWTMRTO", 0x10, 0x10 }
179};
180
181int
182ahd_clrseqintstat_print(u_int regvalue, u_int *cur_col, u_int wrap)
183{
184 return (ahd_print_register(CLRSEQINTSTAT_parse_table, 5, "CLRSEQINTSTAT",
185 0x0c, regvalue, cur_col, wrap));
186}
187
188int
189ahd_swtimer_print(u_int regvalue, u_int *cur_col, u_int wrap)
190{
191 return (ahd_print_register(NULL, 0, "SWTIMER",
192 0x0e, regvalue, cur_col, wrap));
193}
194
195int
196ahd_snscb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap)
197{
198 return (ahd_print_register(NULL, 0, "SNSCB_QOFF",
199 0x10, regvalue, cur_col, wrap));
200}
201
202int
203ahd_sescb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap)
204{
205 return (ahd_print_register(NULL, 0, "SESCB_QOFF",
206 0x12, regvalue, cur_col, wrap));
207}
208
209int
210ahd_sdscb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap)
211{
212 return (ahd_print_register(NULL, 0, "SDSCB_QOFF",
213 0x14, regvalue, cur_col, wrap));
214}
215
216static const ahd_reg_parse_entry_t QOFF_CTLSTA_parse_table[] = {
217 { "SCB_QSIZE_4", 0x00, 0x0f },
218 { "SCB_QSIZE_8", 0x01, 0x0f },
219 { "SCB_QSIZE_16", 0x02, 0x0f },
220 { "SCB_QSIZE_32", 0x03, 0x0f },
221 { "SCB_QSIZE_64", 0x04, 0x0f },
222 { "SCB_QSIZE_128", 0x05, 0x0f },
223 { "SCB_QSIZE_256", 0x06, 0x0f },
224 { "SCB_QSIZE_512", 0x07, 0x0f },
225 { "SCB_QSIZE_1024", 0x08, 0x0f },
226 { "SCB_QSIZE_2048", 0x09, 0x0f },
227 { "SCB_QSIZE_4096", 0x0a, 0x0f },
228 { "SCB_QSIZE_8192", 0x0b, 0x0f },
229 { "SCB_QSIZE_16384", 0x0c, 0x0f },
230 { "SCB_QSIZE", 0x0f, 0x0f },
231 { "HS_MAILBOX_ACT", 0x10, 0x10 },
232 { "SDSCB_ROLLOVR", 0x20, 0x20 },
233 { "NEW_SCB_AVAIL", 0x40, 0x40 },
234 { "EMPTY_SCB_AVAIL", 0x80, 0x80 }
235};
236
237int
238ahd_qoff_ctlsta_print(u_int regvalue, u_int *cur_col, u_int wrap)
239{
240 return (ahd_print_register(QOFF_CTLSTA_parse_table, 18, "QOFF_CTLSTA",
241 0x16, regvalue, cur_col, wrap));
242}
243
244static const ahd_reg_parse_entry_t INTCTL_parse_table[] = { 57static const ahd_reg_parse_entry_t INTCTL_parse_table[] = {
245 { "SPLTINTEN", 0x01, 0x01 }, 58 { "SPLTINTEN", 0x01, 0x01 },
246 { "SEQINTEN", 0x02, 0x02 }, 59 { "SEQINTEN", 0x02, 0x02 },
@@ -280,22 +93,6 @@ ahd_dfcntrl_print(u_int regvalue, u_int *cur_col, u_int wrap)
280 0x19, regvalue, cur_col, wrap)); 93 0x19, regvalue, cur_col, wrap));
281} 94}
282 95
283static const ahd_reg_parse_entry_t DSCOMMAND0_parse_table[] = {
284 { "CIOPARCKEN", 0x01, 0x01 },
285 { "DISABLE_TWATE", 0x02, 0x02 },
286 { "EXTREQLCK", 0x10, 0x10 },
287 { "MPARCKEN", 0x20, 0x20 },
288 { "DPARCKEN", 0x40, 0x40 },
289 { "CACHETHEN", 0x80, 0x80 }
290};
291
292int
293ahd_dscommand0_print(u_int regvalue, u_int *cur_col, u_int wrap)
294{
295 return (ahd_print_register(DSCOMMAND0_parse_table, 6, "DSCOMMAND0",
296 0x19, regvalue, cur_col, wrap));
297}
298
299static const ahd_reg_parse_entry_t DFSTATUS_parse_table[] = { 96static const ahd_reg_parse_entry_t DFSTATUS_parse_table[] = {
300 { "FIFOEMP", 0x01, 0x01 }, 97 { "FIFOEMP", 0x01, 0x01 },
301 { "FIFOFULL", 0x02, 0x02 }, 98 { "FIFOFULL", 0x02, 0x02 },
@@ -327,146 +124,6 @@ ahd_sg_cache_shadow_print(u_int regvalue, u_int *cur_col, u_int wrap)
327 0x1b, regvalue, cur_col, wrap)); 124 0x1b, regvalue, cur_col, wrap));
328} 125}
329 126
330static const ahd_reg_parse_entry_t SG_CACHE_PRE_parse_table[] = {
331 { "LAST_SEG", 0x02, 0x02 },
332 { "ODD_SEG", 0x04, 0x04 },
333 { "SG_ADDR_MASK", 0xf8, 0xf8 }
334};
335
336int
337ahd_sg_cache_pre_print(u_int regvalue, u_int *cur_col, u_int wrap)
338{
339 return (ahd_print_register(SG_CACHE_PRE_parse_table, 3, "SG_CACHE_PRE",
340 0x1b, regvalue, cur_col, wrap));
341}
342
343int
344ahd_lqin_print(u_int regvalue, u_int *cur_col, u_int wrap)
345{
346 return (ahd_print_register(NULL, 0, "LQIN",
347 0x20, regvalue, cur_col, wrap));
348}
349
350int
351ahd_lunptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
352{
353 return (ahd_print_register(NULL, 0, "LUNPTR",
354 0x22, regvalue, cur_col, wrap));
355}
356
357int
358ahd_cmdlenptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
359{
360 return (ahd_print_register(NULL, 0, "CMDLENPTR",
361 0x25, regvalue, cur_col, wrap));
362}
363
364int
365ahd_attrptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
366{
367 return (ahd_print_register(NULL, 0, "ATTRPTR",
368 0x26, regvalue, cur_col, wrap));
369}
370
371int
372ahd_flagptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
373{
374 return (ahd_print_register(NULL, 0, "FLAGPTR",
375 0x27, regvalue, cur_col, wrap));
376}
377
378int
379ahd_cmdptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
380{
381 return (ahd_print_register(NULL, 0, "CMDPTR",
382 0x28, regvalue, cur_col, wrap));
383}
384
385int
386ahd_qnextptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
387{
388 return (ahd_print_register(NULL, 0, "QNEXTPTR",
389 0x29, regvalue, cur_col, wrap));
390}
391
392int
393ahd_abrtbyteptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
394{
395 return (ahd_print_register(NULL, 0, "ABRTBYTEPTR",
396 0x2b, regvalue, cur_col, wrap));
397}
398
399int
400ahd_abrtbitptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
401{
402 return (ahd_print_register(NULL, 0, "ABRTBITPTR",
403 0x2c, regvalue, cur_col, wrap));
404}
405
406static const ahd_reg_parse_entry_t LUNLEN_parse_table[] = {
407 { "ILUNLEN", 0x0f, 0x0f },
408 { "TLUNLEN", 0xf0, 0xf0 }
409};
410
411int
412ahd_lunlen_print(u_int regvalue, u_int *cur_col, u_int wrap)
413{
414 return (ahd_print_register(LUNLEN_parse_table, 2, "LUNLEN",
415 0x30, regvalue, cur_col, wrap));
416}
417
418int
419ahd_cdblimit_print(u_int regvalue, u_int *cur_col, u_int wrap)
420{
421 return (ahd_print_register(NULL, 0, "CDBLIMIT",
422 0x31, regvalue, cur_col, wrap));
423}
424
425int
426ahd_maxcmd_print(u_int regvalue, u_int *cur_col, u_int wrap)
427{
428 return (ahd_print_register(NULL, 0, "MAXCMD",
429 0x32, regvalue, cur_col, wrap));
430}
431
432int
433ahd_maxcmdcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
434{
435 return (ahd_print_register(NULL, 0, "MAXCMDCNT",
436 0x33, regvalue, cur_col, wrap));
437}
438
439static const ahd_reg_parse_entry_t LQCTL1_parse_table[] = {
440 { "ABORTPENDING", 0x01, 0x01 },
441 { "SINGLECMD", 0x02, 0x02 },
442 { "PCI2PCI", 0x04, 0x04 }
443};
444
445int
446ahd_lqctl1_print(u_int regvalue, u_int *cur_col, u_int wrap)
447{
448 return (ahd_print_register(LQCTL1_parse_table, 3, "LQCTL1",
449 0x38, regvalue, cur_col, wrap));
450}
451
452static const ahd_reg_parse_entry_t LQCTL2_parse_table[] = {
453 { "LQOPAUSE", 0x01, 0x01 },
454 { "LQOTOIDLE", 0x02, 0x02 },
455 { "LQOCONTINUE", 0x04, 0x04 },
456 { "LQORETRY", 0x08, 0x08 },
457 { "LQIPAUSE", 0x10, 0x10 },
458 { "LQITOIDLE", 0x20, 0x20 },
459 { "LQICONTINUE", 0x40, 0x40 },
460 { "LQIRETRY", 0x80, 0x80 }
461};
462
463int
464ahd_lqctl2_print(u_int regvalue, u_int *cur_col, u_int wrap)
465{
466 return (ahd_print_register(LQCTL2_parse_table, 8, "LQCTL2",
467 0x39, regvalue, cur_col, wrap));
468}
469
470static const ahd_reg_parse_entry_t SCSISEQ0_parse_table[] = { 127static const ahd_reg_parse_entry_t SCSISEQ0_parse_table[] = {
471 { "SCSIRSTO", 0x01, 0x01 }, 128 { "SCSIRSTO", 0x01, 0x01 },
472 { "FORCEBUSFREE", 0x10, 0x10 }, 129 { "FORCEBUSFREE", 0x10, 0x10 },
@@ -498,37 +155,6 @@ ahd_scsiseq1_print(u_int regvalue, u_int *cur_col, u_int wrap)
498 0x3b, regvalue, cur_col, wrap)); 155 0x3b, regvalue, cur_col, wrap));
499} 156}
500 157
501static const ahd_reg_parse_entry_t SXFRCTL0_parse_table[] = {
502 { "SPIOEN", 0x08, 0x08 },
503 { "BIOSCANCELEN", 0x10, 0x10 },
504 { "DFPEXP", 0x40, 0x40 },
505 { "DFON", 0x80, 0x80 }
506};
507
508int
509ahd_sxfrctl0_print(u_int regvalue, u_int *cur_col, u_int wrap)
510{
511 return (ahd_print_register(SXFRCTL0_parse_table, 4, "SXFRCTL0",
512 0x3c, regvalue, cur_col, wrap));
513}
514
515static const ahd_reg_parse_entry_t SXFRCTL1_parse_table[] = {
516 { "STPWEN", 0x01, 0x01 },
517 { "ACTNEGEN", 0x02, 0x02 },
518 { "ENSTIMER", 0x04, 0x04 },
519 { "STIMESEL", 0x18, 0x18 },
520 { "ENSPCHK", 0x20, 0x20 },
521 { "ENSACHK", 0x40, 0x40 },
522 { "BITBUCKET", 0x80, 0x80 }
523};
524
525int
526ahd_sxfrctl1_print(u_int regvalue, u_int *cur_col, u_int wrap)
527{
528 return (ahd_print_register(SXFRCTL1_parse_table, 7, "SXFRCTL1",
529 0x3d, regvalue, cur_col, wrap));
530}
531
532static const ahd_reg_parse_entry_t DFFSTAT_parse_table[] = { 158static const ahd_reg_parse_entry_t DFFSTAT_parse_table[] = {
533 { "CURRFIFO_0", 0x00, 0x03 }, 159 { "CURRFIFO_0", 0x00, 0x03 },
534 { "CURRFIFO_1", 0x01, 0x03 }, 160 { "CURRFIFO_1", 0x01, 0x03 },
@@ -545,40 +171,6 @@ ahd_dffstat_print(u_int regvalue, u_int *cur_col, u_int wrap)
545 0x3f, regvalue, cur_col, wrap)); 171 0x3f, regvalue, cur_col, wrap));
546} 172}
547 173
548int
549ahd_multargid_print(u_int regvalue, u_int *cur_col, u_int wrap)
550{
551 return (ahd_print_register(NULL, 0, "MULTARGID",
552 0x40, regvalue, cur_col, wrap));
553}
554
555static const ahd_reg_parse_entry_t SCSISIGO_parse_table[] = {
556 { "P_DATAOUT", 0x00, 0xe0 },
557 { "P_DATAOUT_DT", 0x20, 0xe0 },
558 { "P_DATAIN", 0x40, 0xe0 },
559 { "P_DATAIN_DT", 0x60, 0xe0 },
560 { "P_COMMAND", 0x80, 0xe0 },
561 { "P_MESGOUT", 0xa0, 0xe0 },
562 { "P_STATUS", 0xc0, 0xe0 },
563 { "P_MESGIN", 0xe0, 0xe0 },
564 { "ACKO", 0x01, 0x01 },
565 { "REQO", 0x02, 0x02 },
566 { "BSYO", 0x04, 0x04 },
567 { "SELO", 0x08, 0x08 },
568 { "ATNO", 0x10, 0x10 },
569 { "MSGO", 0x20, 0x20 },
570 { "IOO", 0x40, 0x40 },
571 { "CDO", 0x80, 0x80 },
572 { "PHASE_MASK", 0xe0, 0xe0 }
573};
574
575int
576ahd_scsisigo_print(u_int regvalue, u_int *cur_col, u_int wrap)
577{
578 return (ahd_print_register(SCSISIGO_parse_table, 17, "SCSISIGO",
579 0x40, regvalue, cur_col, wrap));
580}
581
582static const ahd_reg_parse_entry_t SCSISIGI_parse_table[] = { 174static const ahd_reg_parse_entry_t SCSISIGI_parse_table[] = {
583 { "P_DATAOUT", 0x00, 0xe0 }, 175 { "P_DATAOUT", 0x00, 0xe0 },
584 { "P_DATAOUT_DT", 0x20, 0xe0 }, 176 { "P_DATAOUT_DT", 0x20, 0xe0 },
@@ -624,31 +216,12 @@ ahd_scsiphase_print(u_int regvalue, u_int *cur_col, u_int wrap)
624} 216}
625 217
626int 218int
627ahd_scsidat_print(u_int regvalue, u_int *cur_col, u_int wrap)
628{
629 return (ahd_print_register(NULL, 0, "SCSIDAT",
630 0x44, regvalue, cur_col, wrap));
631}
632
633int
634ahd_scsibus_print(u_int regvalue, u_int *cur_col, u_int wrap) 219ahd_scsibus_print(u_int regvalue, u_int *cur_col, u_int wrap)
635{ 220{
636 return (ahd_print_register(NULL, 0, "SCSIBUS", 221 return (ahd_print_register(NULL, 0, "SCSIBUS",
637 0x46, regvalue, cur_col, wrap)); 222 0x46, regvalue, cur_col, wrap));
638} 223}
639 224
640static const ahd_reg_parse_entry_t TARGIDIN_parse_table[] = {
641 { "TARGID", 0x0f, 0x0f },
642 { "CLKOUT", 0x80, 0x80 }
643};
644
645int
646ahd_targidin_print(u_int regvalue, u_int *cur_col, u_int wrap)
647{
648 return (ahd_print_register(TARGIDIN_parse_table, 2, "TARGIDIN",
649 0x48, regvalue, cur_col, wrap));
650}
651
652static const ahd_reg_parse_entry_t SELID_parse_table[] = { 225static const ahd_reg_parse_entry_t SELID_parse_table[] = {
653 { "ONEBIT", 0x08, 0x08 }, 226 { "ONEBIT", 0x08, 0x08 },
654 { "SELID_MASK", 0xf0, 0xf0 } 227 { "SELID_MASK", 0xf0, 0xf0 }
@@ -661,38 +234,6 @@ ahd_selid_print(u_int regvalue, u_int *cur_col, u_int wrap)
661 0x49, regvalue, cur_col, wrap)); 234 0x49, regvalue, cur_col, wrap));
662} 235}
663 236
664static const ahd_reg_parse_entry_t OPTIONMODE_parse_table[] = {
665 { "AUTO_MSGOUT_DE", 0x02, 0x02 },
666 { "ENDGFORMCHK", 0x04, 0x04 },
667 { "BUSFREEREV", 0x10, 0x10 },
668 { "BIASCANCTL", 0x20, 0x20 },
669 { "AUTOACKEN", 0x40, 0x40 },
670 { "BIOSCANCTL", 0x80, 0x80 },
671 { "OPTIONMODE_DEFAULTS",0x02, 0x02 }
672};
673
674int
675ahd_optionmode_print(u_int regvalue, u_int *cur_col, u_int wrap)
676{
677 return (ahd_print_register(OPTIONMODE_parse_table, 7, "OPTIONMODE",
678 0x4a, regvalue, cur_col, wrap));
679}
680
681static const ahd_reg_parse_entry_t SBLKCTL_parse_table[] = {
682 { "SELWIDE", 0x02, 0x02 },
683 { "ENAB20", 0x04, 0x04 },
684 { "ENAB40", 0x08, 0x08 },
685 { "DIAGLEDON", 0x40, 0x40 },
686 { "DIAGLEDEN", 0x80, 0x80 }
687};
688
689int
690ahd_sblkctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
691{
692 return (ahd_print_register(SBLKCTL_parse_table, 5, "SBLKCTL",
693 0x4a, regvalue, cur_col, wrap));
694}
695
696static const ahd_reg_parse_entry_t SSTAT0_parse_table[] = { 237static const ahd_reg_parse_entry_t SSTAT0_parse_table[] = {
697 { "ARBDO", 0x01, 0x01 }, 238 { "ARBDO", 0x01, 0x01 },
698 { "SPIORDY", 0x02, 0x02 }, 239 { "SPIORDY", 0x02, 0x02 },
@@ -728,23 +269,6 @@ ahd_simode0_print(u_int regvalue, u_int *cur_col, u_int wrap)
728 0x4b, regvalue, cur_col, wrap)); 269 0x4b, regvalue, cur_col, wrap));
729} 270}
730 271
731static const ahd_reg_parse_entry_t CLRSINT0_parse_table[] = {
732 { "CLRARBDO", 0x01, 0x01 },
733 { "CLRSPIORDY", 0x02, 0x02 },
734 { "CLROVERRUN", 0x04, 0x04 },
735 { "CLRIOERR", 0x08, 0x08 },
736 { "CLRSELINGO", 0x10, 0x10 },
737 { "CLRSELDI", 0x20, 0x20 },
738 { "CLRSELDO", 0x40, 0x40 }
739};
740
741int
742ahd_clrsint0_print(u_int regvalue, u_int *cur_col, u_int wrap)
743{
744 return (ahd_print_register(CLRSINT0_parse_table, 7, "CLRSINT0",
745 0x4b, regvalue, cur_col, wrap));
746}
747
748static const ahd_reg_parse_entry_t SSTAT1_parse_table[] = { 272static const ahd_reg_parse_entry_t SSTAT1_parse_table[] = {
749 { "REQINIT", 0x01, 0x01 }, 273 { "REQINIT", 0x01, 0x01 },
750 { "STRB2FAST", 0x02, 0x02 }, 274 { "STRB2FAST", 0x02, 0x02 },
@@ -763,23 +287,6 @@ ahd_sstat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
763 0x4c, regvalue, cur_col, wrap)); 287 0x4c, regvalue, cur_col, wrap));
764} 288}
765 289
766static const ahd_reg_parse_entry_t CLRSINT1_parse_table[] = {
767 { "CLRREQINIT", 0x01, 0x01 },
768 { "CLRSTRB2FAST", 0x02, 0x02 },
769 { "CLRSCSIPERR", 0x04, 0x04 },
770 { "CLRBUSFREE", 0x08, 0x08 },
771 { "CLRSCSIRSTI", 0x20, 0x20 },
772 { "CLRATNO", 0x40, 0x40 },
773 { "CLRSELTIMEO", 0x80, 0x80 }
774};
775
776int
777ahd_clrsint1_print(u_int regvalue, u_int *cur_col, u_int wrap)
778{
779 return (ahd_print_register(CLRSINT1_parse_table, 7, "CLRSINT1",
780 0x4c, regvalue, cur_col, wrap));
781}
782
783static const ahd_reg_parse_entry_t SSTAT2_parse_table[] = { 290static const ahd_reg_parse_entry_t SSTAT2_parse_table[] = {
784 { "BUSFREE_LQO", 0x40, 0xc0 }, 291 { "BUSFREE_LQO", 0x40, 0xc0 },
785 { "BUSFREE_DFF0", 0x80, 0xc0 }, 292 { "BUSFREE_DFF0", 0x80, 0xc0 },
@@ -800,20 +307,6 @@ ahd_sstat2_print(u_int regvalue, u_int *cur_col, u_int wrap)
800 0x4d, regvalue, cur_col, wrap)); 307 0x4d, regvalue, cur_col, wrap));
801} 308}
802 309
803static const ahd_reg_parse_entry_t CLRSINT2_parse_table[] = {
804 { "CLRDMADONE", 0x01, 0x01 },
805 { "CLRSDONE", 0x02, 0x02 },
806 { "CLRWIDE_RES", 0x04, 0x04 },
807 { "CLRNONPACKREQ", 0x20, 0x20 }
808};
809
810int
811ahd_clrsint2_print(u_int regvalue, u_int *cur_col, u_int wrap)
812{
813 return (ahd_print_register(CLRSINT2_parse_table, 4, "CLRSINT2",
814 0x4d, regvalue, cur_col, wrap));
815}
816
817static const ahd_reg_parse_entry_t PERRDIAG_parse_table[] = { 310static const ahd_reg_parse_entry_t PERRDIAG_parse_table[] = {
818 { "DTERR", 0x01, 0x01 }, 311 { "DTERR", 0x01, 0x01 },
819 { "DGFORMERR", 0x02, 0x02 }, 312 { "DGFORMERR", 0x02, 0x02 },
@@ -833,26 +326,12 @@ ahd_perrdiag_print(u_int regvalue, u_int *cur_col, u_int wrap)
833} 326}
834 327
835int 328int
836ahd_lqistate_print(u_int regvalue, u_int *cur_col, u_int wrap)
837{
838 return (ahd_print_register(NULL, 0, "LQISTATE",
839 0x4e, regvalue, cur_col, wrap));
840}
841
842int
843ahd_soffcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 329ahd_soffcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
844{ 330{
845 return (ahd_print_register(NULL, 0, "SOFFCNT", 331 return (ahd_print_register(NULL, 0, "SOFFCNT",
846 0x4f, regvalue, cur_col, wrap)); 332 0x4f, regvalue, cur_col, wrap));
847} 333}
848 334
849int
850ahd_lqostate_print(u_int regvalue, u_int *cur_col, u_int wrap)
851{
852 return (ahd_print_register(NULL, 0, "LQOSTATE",
853 0x4f, regvalue, cur_col, wrap));
854}
855
856static const ahd_reg_parse_entry_t LQISTAT0_parse_table[] = { 335static const ahd_reg_parse_entry_t LQISTAT0_parse_table[] = {
857 { "LQIATNCMD", 0x01, 0x01 }, 336 { "LQIATNCMD", 0x01, 0x01 },
858 { "LQIATNLQ", 0x02, 0x02 }, 337 { "LQIATNLQ", 0x02, 0x02 },
@@ -869,56 +348,6 @@ ahd_lqistat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
869 0x50, regvalue, cur_col, wrap)); 348 0x50, regvalue, cur_col, wrap));
870} 349}
871 350
872static const ahd_reg_parse_entry_t LQIMODE0_parse_table[] = {
873 { "ENLQIATNCMD", 0x01, 0x01 },
874 { "ENLQIATNLQ", 0x02, 0x02 },
875 { "ENLQIBADLQT", 0x04, 0x04 },
876 { "ENLQICRCT2", 0x08, 0x08 },
877 { "ENLQICRCT1", 0x10, 0x10 },
878 { "ENLQIATNQASK", 0x20, 0x20 }
879};
880
881int
882ahd_lqimode0_print(u_int regvalue, u_int *cur_col, u_int wrap)
883{
884 return (ahd_print_register(LQIMODE0_parse_table, 6, "LQIMODE0",
885 0x50, regvalue, cur_col, wrap));
886}
887
888static const ahd_reg_parse_entry_t CLRLQIINT0_parse_table[] = {
889 { "CLRLQIATNCMD", 0x01, 0x01 },
890 { "CLRLQIATNLQ", 0x02, 0x02 },
891 { "CLRLQIBADLQT", 0x04, 0x04 },
892 { "CLRLQICRCT2", 0x08, 0x08 },
893 { "CLRLQICRCT1", 0x10, 0x10 },
894 { "CLRLQIATNQAS", 0x20, 0x20 }
895};
896
897int
898ahd_clrlqiint0_print(u_int regvalue, u_int *cur_col, u_int wrap)
899{
900 return (ahd_print_register(CLRLQIINT0_parse_table, 6, "CLRLQIINT0",
901 0x50, regvalue, cur_col, wrap));
902}
903
904static const ahd_reg_parse_entry_t LQIMODE1_parse_table[] = {
905 { "ENLQIOVERI_NLQ", 0x01, 0x01 },
906 { "ENLQIOVERI_LQ", 0x02, 0x02 },
907 { "ENLQIBADLQI", 0x04, 0x04 },
908 { "ENLQICRCI_NLQ", 0x08, 0x08 },
909 { "ENLQICRCI_LQ", 0x10, 0x10 },
910 { "ENLIQABORT", 0x20, 0x20 },
911 { "ENLQIPHASE_NLQ", 0x40, 0x40 },
912 { "ENLQIPHASE_LQ", 0x80, 0x80 }
913};
914
915int
916ahd_lqimode1_print(u_int regvalue, u_int *cur_col, u_int wrap)
917{
918 return (ahd_print_register(LQIMODE1_parse_table, 8, "LQIMODE1",
919 0x51, regvalue, cur_col, wrap));
920}
921
922static const ahd_reg_parse_entry_t LQISTAT1_parse_table[] = { 351static const ahd_reg_parse_entry_t LQISTAT1_parse_table[] = {
923 { "LQIOVERI_NLQ", 0x01, 0x01 }, 352 { "LQIOVERI_NLQ", 0x01, 0x01 },
924 { "LQIOVERI_LQ", 0x02, 0x02 }, 353 { "LQIOVERI_LQ", 0x02, 0x02 },
@@ -937,24 +366,6 @@ ahd_lqistat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
937 0x51, regvalue, cur_col, wrap)); 366 0x51, regvalue, cur_col, wrap));
938} 367}
939 368
940static const ahd_reg_parse_entry_t CLRLQIINT1_parse_table[] = {
941 { "CLRLQIOVERI_NLQ", 0x01, 0x01 },
942 { "CLRLQIOVERI_LQ", 0x02, 0x02 },
943 { "CLRLQIBADLQI", 0x04, 0x04 },
944 { "CLRLQICRCI_NLQ", 0x08, 0x08 },
945 { "CLRLQICRCI_LQ", 0x10, 0x10 },
946 { "CLRLIQABORT", 0x20, 0x20 },
947 { "CLRLQIPHASE_NLQ", 0x40, 0x40 },
948 { "CLRLQIPHASE_LQ", 0x80, 0x80 }
949};
950
951int
952ahd_clrlqiint1_print(u_int regvalue, u_int *cur_col, u_int wrap)
953{
954 return (ahd_print_register(CLRLQIINT1_parse_table, 8, "CLRLQIINT1",
955 0x51, regvalue, cur_col, wrap));
956}
957
958static const ahd_reg_parse_entry_t LQISTAT2_parse_table[] = { 369static const ahd_reg_parse_entry_t LQISTAT2_parse_table[] = {
959 { "LQIGSAVAIL", 0x01, 0x01 }, 370 { "LQIGSAVAIL", 0x01, 0x01 },
960 { "LQISTOPCMD", 0x02, 0x02 }, 371 { "LQISTOPCMD", 0x02, 0x02 },
@@ -985,30 +396,6 @@ ahd_sstat3_print(u_int regvalue, u_int *cur_col, u_int wrap)
985 0x53, regvalue, cur_col, wrap)); 396 0x53, regvalue, cur_col, wrap));
986} 397}
987 398
988static const ahd_reg_parse_entry_t SIMODE3_parse_table[] = {
989 { "ENOSRAMPERR", 0x01, 0x01 },
990 { "ENNTRAMPERR", 0x02, 0x02 }
991};
992
993int
994ahd_simode3_print(u_int regvalue, u_int *cur_col, u_int wrap)
995{
996 return (ahd_print_register(SIMODE3_parse_table, 2, "SIMODE3",
997 0x53, regvalue, cur_col, wrap));
998}
999
1000static const ahd_reg_parse_entry_t CLRSINT3_parse_table[] = {
1001 { "CLROSRAMPERR", 0x01, 0x01 },
1002 { "CLRNTRAMPERR", 0x02, 0x02 }
1003};
1004
1005int
1006ahd_clrsint3_print(u_int regvalue, u_int *cur_col, u_int wrap)
1007{
1008 return (ahd_print_register(CLRSINT3_parse_table, 2, "CLRSINT3",
1009 0x53, regvalue, cur_col, wrap));
1010}
1011
1012static const ahd_reg_parse_entry_t LQOSTAT0_parse_table[] = { 399static const ahd_reg_parse_entry_t LQOSTAT0_parse_table[] = {
1013 { "LQOTCRC", 0x01, 0x01 }, 400 { "LQOTCRC", 0x01, 0x01 },
1014 { "LQOATNPKT", 0x02, 0x02 }, 401 { "LQOATNPKT", 0x02, 0x02 },
@@ -1024,51 +411,6 @@ ahd_lqostat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
1024 0x54, regvalue, cur_col, wrap)); 411 0x54, regvalue, cur_col, wrap));
1025} 412}
1026 413
1027static const ahd_reg_parse_entry_t CLRLQOINT0_parse_table[] = {
1028 { "CLRLQOTCRC", 0x01, 0x01 },
1029 { "CLRLQOATNPKT", 0x02, 0x02 },
1030 { "CLRLQOATNLQ", 0x04, 0x04 },
1031 { "CLRLQOSTOPT2", 0x08, 0x08 },
1032 { "CLRLQOTARGSCBPERR", 0x10, 0x10 }
1033};
1034
1035int
1036ahd_clrlqoint0_print(u_int regvalue, u_int *cur_col, u_int wrap)
1037{
1038 return (ahd_print_register(CLRLQOINT0_parse_table, 5, "CLRLQOINT0",
1039 0x54, regvalue, cur_col, wrap));
1040}
1041
1042static const ahd_reg_parse_entry_t LQOMODE0_parse_table[] = {
1043 { "ENLQOTCRC", 0x01, 0x01 },
1044 { "ENLQOATNPKT", 0x02, 0x02 },
1045 { "ENLQOATNLQ", 0x04, 0x04 },
1046 { "ENLQOSTOPT2", 0x08, 0x08 },
1047 { "ENLQOTARGSCBPERR", 0x10, 0x10 }
1048};
1049
1050int
1051ahd_lqomode0_print(u_int regvalue, u_int *cur_col, u_int wrap)
1052{
1053 return (ahd_print_register(LQOMODE0_parse_table, 5, "LQOMODE0",
1054 0x54, regvalue, cur_col, wrap));
1055}
1056
1057static const ahd_reg_parse_entry_t LQOMODE1_parse_table[] = {
1058 { "ENLQOPHACHGINPKT", 0x01, 0x01 },
1059 { "ENLQOBUSFREE", 0x02, 0x02 },
1060 { "ENLQOBADQAS", 0x04, 0x04 },
1061 { "ENLQOSTOPI2", 0x08, 0x08 },
1062 { "ENLQOINITSCBPERR", 0x10, 0x10 }
1063};
1064
1065int
1066ahd_lqomode1_print(u_int regvalue, u_int *cur_col, u_int wrap)
1067{
1068 return (ahd_print_register(LQOMODE1_parse_table, 5, "LQOMODE1",
1069 0x55, regvalue, cur_col, wrap));
1070}
1071
1072static const ahd_reg_parse_entry_t LQOSTAT1_parse_table[] = { 414static const ahd_reg_parse_entry_t LQOSTAT1_parse_table[] = {
1073 { "LQOPHACHGINPKT", 0x01, 0x01 }, 415 { "LQOPHACHGINPKT", 0x01, 0x01 },
1074 { "LQOBUSFREE", 0x02, 0x02 }, 416 { "LQOBUSFREE", 0x02, 0x02 },
@@ -1084,21 +426,6 @@ ahd_lqostat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
1084 0x55, regvalue, cur_col, wrap)); 426 0x55, regvalue, cur_col, wrap));
1085} 427}
1086 428
1087static const ahd_reg_parse_entry_t CLRLQOINT1_parse_table[] = {
1088 { "CLRLQOPHACHGINPKT", 0x01, 0x01 },
1089 { "CLRLQOBUSFREE", 0x02, 0x02 },
1090 { "CLRLQOBADQAS", 0x04, 0x04 },
1091 { "CLRLQOSTOPI2", 0x08, 0x08 },
1092 { "CLRLQOINITSCBPERR", 0x10, 0x10 }
1093};
1094
1095int
1096ahd_clrlqoint1_print(u_int regvalue, u_int *cur_col, u_int wrap)
1097{
1098 return (ahd_print_register(CLRLQOINT1_parse_table, 5, "CLRLQOINT1",
1099 0x55, regvalue, cur_col, wrap));
1100}
1101
1102static const ahd_reg_parse_entry_t LQOSTAT2_parse_table[] = { 429static const ahd_reg_parse_entry_t LQOSTAT2_parse_table[] = {
1103 { "LQOSTOP0", 0x01, 0x01 }, 430 { "LQOSTOP0", 0x01, 0x01 },
1104 { "LQOPHACHGOUTPKT", 0x02, 0x02 }, 431 { "LQOPHACHGOUTPKT", 0x02, 0x02 },
@@ -1113,13 +440,6 @@ ahd_lqostat2_print(u_int regvalue, u_int *cur_col, u_int wrap)
1113 0x56, regvalue, cur_col, wrap)); 440 0x56, regvalue, cur_col, wrap));
1114} 441}
1115 442
1116int
1117ahd_os_space_cnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
1118{
1119 return (ahd_print_register(NULL, 0, "OS_SPACE_CNT",
1120 0x56, regvalue, cur_col, wrap));
1121}
1122
1123static const ahd_reg_parse_entry_t SIMODE1_parse_table[] = { 443static const ahd_reg_parse_entry_t SIMODE1_parse_table[] = {
1124 { "ENREQINIT", 0x01, 0x01 }, 444 { "ENREQINIT", 0x01, 0x01 },
1125 { "ENSTRB2FAST", 0x02, 0x02 }, 445 { "ENSTRB2FAST", 0x02, 0x02 },
@@ -1138,13 +458,6 @@ ahd_simode1_print(u_int regvalue, u_int *cur_col, u_int wrap)
1138 0x57, regvalue, cur_col, wrap)); 458 0x57, regvalue, cur_col, wrap));
1139} 459}
1140 460
1141int
1142ahd_gsfifo_print(u_int regvalue, u_int *cur_col, u_int wrap)
1143{
1144 return (ahd_print_register(NULL, 0, "GSFIFO",
1145 0x58, regvalue, cur_col, wrap));
1146}
1147
1148static const ahd_reg_parse_entry_t DFFSXFRCTL_parse_table[] = { 461static const ahd_reg_parse_entry_t DFFSXFRCTL_parse_table[] = {
1149 { "RSTCHN", 0x01, 0x01 }, 462 { "RSTCHN", 0x01, 0x01 },
1150 { "CLRCHN", 0x02, 0x02 }, 463 { "CLRCHN", 0x02, 0x02 },
@@ -1159,44 +472,6 @@ ahd_dffsxfrctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
1159 0x5a, regvalue, cur_col, wrap)); 472 0x5a, regvalue, cur_col, wrap));
1160} 473}
1161 474
1162static const ahd_reg_parse_entry_t LQOSCSCTL_parse_table[] = {
1163 { "LQONOCHKOVER", 0x01, 0x01 },
1164 { "LQONOHOLDLACK", 0x02, 0x02 },
1165 { "LQOBUSETDLY", 0x40, 0x40 },
1166 { "LQOH2A_VERSION", 0x80, 0x80 }
1167};
1168
1169int
1170ahd_lqoscsctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
1171{
1172 return (ahd_print_register(LQOSCSCTL_parse_table, 4, "LQOSCSCTL",
1173 0x5a, regvalue, cur_col, wrap));
1174}
1175
1176int
1177ahd_nextscb_print(u_int regvalue, u_int *cur_col, u_int wrap)
1178{
1179 return (ahd_print_register(NULL, 0, "NEXTSCB",
1180 0x5a, regvalue, cur_col, wrap));
1181}
1182
1183static const ahd_reg_parse_entry_t CLRSEQINTSRC_parse_table[] = {
1184 { "CLRCFG4TCMD", 0x01, 0x01 },
1185 { "CLRCFG4ICMD", 0x02, 0x02 },
1186 { "CLRCFG4TSTAT", 0x04, 0x04 },
1187 { "CLRCFG4ISTAT", 0x08, 0x08 },
1188 { "CLRCFG4DATA", 0x10, 0x10 },
1189 { "CLRSAVEPTRS", 0x20, 0x20 },
1190 { "CLRCTXTDONE", 0x40, 0x40 }
1191};
1192
1193int
1194ahd_clrseqintsrc_print(u_int regvalue, u_int *cur_col, u_int wrap)
1195{
1196 return (ahd_print_register(CLRSEQINTSRC_parse_table, 7, "CLRSEQINTSRC",
1197 0x5b, regvalue, cur_col, wrap));
1198}
1199
1200static const ahd_reg_parse_entry_t SEQINTSRC_parse_table[] = { 475static const ahd_reg_parse_entry_t SEQINTSRC_parse_table[] = {
1201 { "CFG4TCMD", 0x01, 0x01 }, 476 { "CFG4TCMD", 0x01, 0x01 },
1202 { "CFG4ICMD", 0x02, 0x02 }, 477 { "CFG4ICMD", 0x02, 0x02 },
@@ -1231,13 +506,6 @@ ahd_seqimode_print(u_int regvalue, u_int *cur_col, u_int wrap)
1231 0x5c, regvalue, cur_col, wrap)); 506 0x5c, regvalue, cur_col, wrap));
1232} 507}
1233 508
1234int
1235ahd_currscb_print(u_int regvalue, u_int *cur_col, u_int wrap)
1236{
1237 return (ahd_print_register(NULL, 0, "CURRSCB",
1238 0x5c, regvalue, cur_col, wrap));
1239}
1240
1241static const ahd_reg_parse_entry_t MDFFSTAT_parse_table[] = { 509static const ahd_reg_parse_entry_t MDFFSTAT_parse_table[] = {
1242 { "FIFOFREE", 0x01, 0x01 }, 510 { "FIFOFREE", 0x01, 0x01 },
1243 { "DATAINFIFO", 0x02, 0x02 }, 511 { "DATAINFIFO", 0x02, 0x02 },
@@ -1256,308 +524,12 @@ ahd_mdffstat_print(u_int regvalue, u_int *cur_col, u_int wrap)
1256} 524}
1257 525
1258int 526int
1259ahd_lastscb_print(u_int regvalue, u_int *cur_col, u_int wrap)
1260{
1261 return (ahd_print_register(NULL, 0, "LASTSCB",
1262 0x5e, regvalue, cur_col, wrap));
1263}
1264
1265int
1266ahd_shaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1267{
1268 return (ahd_print_register(NULL, 0, "SHADDR",
1269 0x60, regvalue, cur_col, wrap));
1270}
1271
1272int
1273ahd_negoaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1274{
1275 return (ahd_print_register(NULL, 0, "NEGOADDR",
1276 0x60, regvalue, cur_col, wrap));
1277}
1278
1279int
1280ahd_negperiod_print(u_int regvalue, u_int *cur_col, u_int wrap)
1281{
1282 return (ahd_print_register(NULL, 0, "NEGPERIOD",
1283 0x61, regvalue, cur_col, wrap));
1284}
1285
1286int
1287ahd_negoffset_print(u_int regvalue, u_int *cur_col, u_int wrap)
1288{
1289 return (ahd_print_register(NULL, 0, "NEGOFFSET",
1290 0x62, regvalue, cur_col, wrap));
1291}
1292
1293static const ahd_reg_parse_entry_t NEGPPROPTS_parse_table[] = {
1294 { "PPROPT_IUT", 0x01, 0x01 },
1295 { "PPROPT_DT", 0x02, 0x02 },
1296 { "PPROPT_QAS", 0x04, 0x04 },
1297 { "PPROPT_PACE", 0x08, 0x08 }
1298};
1299
1300int
1301ahd_negppropts_print(u_int regvalue, u_int *cur_col, u_int wrap)
1302{
1303 return (ahd_print_register(NEGPPROPTS_parse_table, 4, "NEGPPROPTS",
1304 0x63, regvalue, cur_col, wrap));
1305}
1306
1307static const ahd_reg_parse_entry_t NEGCONOPTS_parse_table[] = {
1308 { "WIDEXFER", 0x01, 0x01 },
1309 { "ENAUTOATNO", 0x02, 0x02 },
1310 { "ENAUTOATNI", 0x04, 0x04 },
1311 { "ENSLOWCRC", 0x08, 0x08 },
1312 { "RTI_OVRDTRN", 0x10, 0x10 },
1313 { "RTI_WRTDIS", 0x20, 0x20 },
1314 { "ENSNAPSHOT", 0x40, 0x40 }
1315};
1316
1317int
1318ahd_negconopts_print(u_int regvalue, u_int *cur_col, u_int wrap)
1319{
1320 return (ahd_print_register(NEGCONOPTS_parse_table, 7, "NEGCONOPTS",
1321 0x64, regvalue, cur_col, wrap));
1322}
1323
1324int
1325ahd_annexcol_print(u_int regvalue, u_int *cur_col, u_int wrap)
1326{
1327 return (ahd_print_register(NULL, 0, "ANNEXCOL",
1328 0x65, regvalue, cur_col, wrap));
1329}
1330
1331int
1332ahd_annexdat_print(u_int regvalue, u_int *cur_col, u_int wrap)
1333{
1334 return (ahd_print_register(NULL, 0, "ANNEXDAT",
1335 0x66, regvalue, cur_col, wrap));
1336}
1337
1338static const ahd_reg_parse_entry_t SCSCHKN_parse_table[] = {
1339 { "LSTSGCLRDIS", 0x01, 0x01 },
1340 { "SHVALIDSTDIS", 0x02, 0x02 },
1341 { "DFFACTCLR", 0x04, 0x04 },
1342 { "SDONEMSKDIS", 0x08, 0x08 },
1343 { "WIDERESEN", 0x10, 0x10 },
1344 { "CURRFIFODEF", 0x20, 0x20 },
1345 { "STSELSKIDDIS", 0x40, 0x40 },
1346 { "BIDICHKDIS", 0x80, 0x80 }
1347};
1348
1349int
1350ahd_scschkn_print(u_int regvalue, u_int *cur_col, u_int wrap)
1351{
1352 return (ahd_print_register(SCSCHKN_parse_table, 8, "SCSCHKN",
1353 0x66, regvalue, cur_col, wrap));
1354}
1355
1356int
1357ahd_iownid_print(u_int regvalue, u_int *cur_col, u_int wrap)
1358{
1359 return (ahd_print_register(NULL, 0, "IOWNID",
1360 0x67, regvalue, cur_col, wrap));
1361}
1362
1363int
1364ahd_shcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
1365{
1366 return (ahd_print_register(NULL, 0, "SHCNT",
1367 0x68, regvalue, cur_col, wrap));
1368}
1369
1370int
1371ahd_townid_print(u_int regvalue, u_int *cur_col, u_int wrap)
1372{
1373 return (ahd_print_register(NULL, 0, "TOWNID",
1374 0x69, regvalue, cur_col, wrap));
1375}
1376
1377int
1378ahd_seloid_print(u_int regvalue, u_int *cur_col, u_int wrap) 527ahd_seloid_print(u_int regvalue, u_int *cur_col, u_int wrap)
1379{ 528{
1380 return (ahd_print_register(NULL, 0, "SELOID", 529 return (ahd_print_register(NULL, 0, "SELOID",
1381 0x6b, regvalue, cur_col, wrap)); 530 0x6b, regvalue, cur_col, wrap));
1382} 531}
1383 532
1384int
1385ahd_haddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1386{
1387 return (ahd_print_register(NULL, 0, "HADDR",
1388 0x70, regvalue, cur_col, wrap));
1389}
1390
1391int
1392ahd_hcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
1393{
1394 return (ahd_print_register(NULL, 0, "HCNT",
1395 0x78, regvalue, cur_col, wrap));
1396}
1397
1398int
1399ahd_sghaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1400{
1401 return (ahd_print_register(NULL, 0, "SGHADDR",
1402 0x7c, regvalue, cur_col, wrap));
1403}
1404
1405int
1406ahd_scbhaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1407{
1408 return (ahd_print_register(NULL, 0, "SCBHADDR",
1409 0x7c, regvalue, cur_col, wrap));
1410}
1411
1412int
1413ahd_sghcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
1414{
1415 return (ahd_print_register(NULL, 0, "SGHCNT",
1416 0x84, regvalue, cur_col, wrap));
1417}
1418
1419int
1420ahd_scbhcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
1421{
1422 return (ahd_print_register(NULL, 0, "SCBHCNT",
1423 0x84, regvalue, cur_col, wrap));
1424}
1425
1426static const ahd_reg_parse_entry_t DFF_THRSH_parse_table[] = {
1427 { "WR_DFTHRSH_MIN", 0x00, 0x70 },
1428 { "RD_DFTHRSH_MIN", 0x00, 0x07 },
1429 { "RD_DFTHRSH_25", 0x01, 0x07 },
1430 { "RD_DFTHRSH_50", 0x02, 0x07 },
1431 { "RD_DFTHRSH_63", 0x03, 0x07 },
1432 { "RD_DFTHRSH_75", 0x04, 0x07 },
1433 { "RD_DFTHRSH_85", 0x05, 0x07 },
1434 { "RD_DFTHRSH_90", 0x06, 0x07 },
1435 { "RD_DFTHRSH_MAX", 0x07, 0x07 },
1436 { "WR_DFTHRSH_25", 0x10, 0x70 },
1437 { "WR_DFTHRSH_50", 0x20, 0x70 },
1438 { "WR_DFTHRSH_63", 0x30, 0x70 },
1439 { "WR_DFTHRSH_75", 0x40, 0x70 },
1440 { "WR_DFTHRSH_85", 0x50, 0x70 },
1441 { "WR_DFTHRSH_90", 0x60, 0x70 },
1442 { "WR_DFTHRSH_MAX", 0x70, 0x70 },
1443 { "RD_DFTHRSH", 0x07, 0x07 },
1444 { "WR_DFTHRSH", 0x70, 0x70 }
1445};
1446
1447int
1448ahd_dff_thrsh_print(u_int regvalue, u_int *cur_col, u_int wrap)
1449{
1450 return (ahd_print_register(DFF_THRSH_parse_table, 18, "DFF_THRSH",
1451 0x88, regvalue, cur_col, wrap));
1452}
1453
1454static const ahd_reg_parse_entry_t PCIXCTL_parse_table[] = {
1455 { "CMPABCDIS", 0x01, 0x01 },
1456 { "TSCSERREN", 0x02, 0x02 },
1457 { "SRSPDPEEN", 0x04, 0x04 },
1458 { "SPLTSTADIS", 0x08, 0x08 },
1459 { "SPLTSMADIS", 0x10, 0x10 },
1460 { "UNEXPSCIEN", 0x20, 0x20 },
1461 { "SERRPULSE", 0x80, 0x80 }
1462};
1463
1464int
1465ahd_pcixctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
1466{
1467 return (ahd_print_register(PCIXCTL_parse_table, 7, "PCIXCTL",
1468 0x93, regvalue, cur_col, wrap));
1469}
1470
1471static const ahd_reg_parse_entry_t DCHSPLTSTAT0_parse_table[] = {
1472 { "RXSPLTRSP", 0x01, 0x01 },
1473 { "RXSCEMSG", 0x02, 0x02 },
1474 { "RXOVRUN", 0x04, 0x04 },
1475 { "CNTNOTCMPLT", 0x08, 0x08 },
1476 { "SCDATBUCKET", 0x10, 0x10 },
1477 { "SCADERR", 0x20, 0x20 },
1478 { "SCBCERR", 0x40, 0x40 },
1479 { "STAETERM", 0x80, 0x80 }
1480};
1481
1482int
1483ahd_dchspltstat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
1484{
1485 return (ahd_print_register(DCHSPLTSTAT0_parse_table, 8, "DCHSPLTSTAT0",
1486 0x96, regvalue, cur_col, wrap));
1487}
1488
1489static const ahd_reg_parse_entry_t DCHSPLTSTAT1_parse_table[] = {
1490 { "RXDATABUCKET", 0x01, 0x01 }
1491};
1492
1493int
1494ahd_dchspltstat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
1495{
1496 return (ahd_print_register(DCHSPLTSTAT1_parse_table, 1, "DCHSPLTSTAT1",
1497 0x97, regvalue, cur_col, wrap));
1498}
1499
1500static const ahd_reg_parse_entry_t SGSPLTSTAT0_parse_table[] = {
1501 { "RXSPLTRSP", 0x01, 0x01 },
1502 { "RXSCEMSG", 0x02, 0x02 },
1503 { "RXOVRUN", 0x04, 0x04 },
1504 { "CNTNOTCMPLT", 0x08, 0x08 },
1505 { "SCDATBUCKET", 0x10, 0x10 },
1506 { "SCADERR", 0x20, 0x20 },
1507 { "SCBCERR", 0x40, 0x40 },
1508 { "STAETERM", 0x80, 0x80 }
1509};
1510
1511int
1512ahd_sgspltstat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
1513{
1514 return (ahd_print_register(SGSPLTSTAT0_parse_table, 8, "SGSPLTSTAT0",
1515 0x9e, regvalue, cur_col, wrap));
1516}
1517
1518static const ahd_reg_parse_entry_t SGSPLTSTAT1_parse_table[] = {
1519 { "RXDATABUCKET", 0x01, 0x01 }
1520};
1521
1522int
1523ahd_sgspltstat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
1524{
1525 return (ahd_print_register(SGSPLTSTAT1_parse_table, 1, "SGSPLTSTAT1",
1526 0x9f, regvalue, cur_col, wrap));
1527}
1528
1529static const ahd_reg_parse_entry_t DF0PCISTAT_parse_table[] = {
1530 { "DPR", 0x01, 0x01 },
1531 { "TWATERR", 0x02, 0x02 },
1532 { "RDPERR", 0x04, 0x04 },
1533 { "SCAAPERR", 0x08, 0x08 },
1534 { "RTA", 0x10, 0x10 },
1535 { "RMA", 0x20, 0x20 },
1536 { "SSE", 0x40, 0x40 },
1537 { "DPE", 0x80, 0x80 }
1538};
1539
1540int
1541ahd_df0pcistat_print(u_int regvalue, u_int *cur_col, u_int wrap)
1542{
1543 return (ahd_print_register(DF0PCISTAT_parse_table, 8, "DF0PCISTAT",
1544 0xa0, regvalue, cur_col, wrap));
1545}
1546
1547int
1548ahd_reg0_print(u_int regvalue, u_int *cur_col, u_int wrap)
1549{
1550 return (ahd_print_register(NULL, 0, "REG0",
1551 0xa0, regvalue, cur_col, wrap));
1552}
1553
1554int
1555ahd_reg_isr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1556{
1557 return (ahd_print_register(NULL, 0, "REG_ISR",
1558 0xa4, regvalue, cur_col, wrap));
1559}
1560
1561static const ahd_reg_parse_entry_t SG_STATE_parse_table[] = { 533static const ahd_reg_parse_entry_t SG_STATE_parse_table[] = {
1562 { "SEGS_AVAIL", 0x01, 0x01 }, 534 { "SEGS_AVAIL", 0x01, 0x01 },
1563 { "LOADING_NEEDED", 0x02, 0x02 }, 535 { "LOADING_NEEDED", 0x02, 0x02 },
@@ -1571,54 +543,6 @@ ahd_sg_state_print(u_int regvalue, u_int *cur_col, u_int wrap)
1571 0xa6, regvalue, cur_col, wrap)); 543 0xa6, regvalue, cur_col, wrap));
1572} 544}
1573 545
1574static const ahd_reg_parse_entry_t TARGPCISTAT_parse_table[] = {
1575 { "TWATERR", 0x02, 0x02 },
1576 { "STA", 0x08, 0x08 },
1577 { "SSE", 0x40, 0x40 },
1578 { "DPE", 0x80, 0x80 }
1579};
1580
1581int
1582ahd_targpcistat_print(u_int regvalue, u_int *cur_col, u_int wrap)
1583{
1584 return (ahd_print_register(TARGPCISTAT_parse_table, 4, "TARGPCISTAT",
1585 0xa7, regvalue, cur_col, wrap));
1586}
1587
1588int
1589ahd_scbptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1590{
1591 return (ahd_print_register(NULL, 0, "SCBPTR",
1592 0xa8, regvalue, cur_col, wrap));
1593}
1594
1595static const ahd_reg_parse_entry_t SCBAUTOPTR_parse_table[] = {
1596 { "SCBPTR_OFF", 0x07, 0x07 },
1597 { "SCBPTR_ADDR", 0x38, 0x38 },
1598 { "AUSCBPTR_EN", 0x80, 0x80 }
1599};
1600
1601int
1602ahd_scbautoptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1603{
1604 return (ahd_print_register(SCBAUTOPTR_parse_table, 3, "SCBAUTOPTR",
1605 0xab, regvalue, cur_col, wrap));
1606}
1607
1608int
1609ahd_ccsgaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1610{
1611 return (ahd_print_register(NULL, 0, "CCSGADDR",
1612 0xac, regvalue, cur_col, wrap));
1613}
1614
1615int
1616ahd_ccscbaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1617{
1618 return (ahd_print_register(NULL, 0, "CCSCBADDR",
1619 0xac, regvalue, cur_col, wrap));
1620}
1621
1622static const ahd_reg_parse_entry_t CCSCBCTL_parse_table[] = { 546static const ahd_reg_parse_entry_t CCSCBCTL_parse_table[] = {
1623 { "CCSCBRESET", 0x01, 0x01 }, 547 { "CCSCBRESET", 0x01, 0x01 },
1624 { "CCSCBDIR", 0x04, 0x04 }, 548 { "CCSCBDIR", 0x04, 0x04 },
@@ -1651,138 +575,6 @@ ahd_ccsgctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
1651 0xad, regvalue, cur_col, wrap)); 575 0xad, regvalue, cur_col, wrap));
1652} 576}
1653 577
1654int
1655ahd_ccsgram_print(u_int regvalue, u_int *cur_col, u_int wrap)
1656{
1657 return (ahd_print_register(NULL, 0, "CCSGRAM",
1658 0xb0, regvalue, cur_col, wrap));
1659}
1660
1661int
1662ahd_ccscbram_print(u_int regvalue, u_int *cur_col, u_int wrap)
1663{
1664 return (ahd_print_register(NULL, 0, "CCSCBRAM",
1665 0xb0, regvalue, cur_col, wrap));
1666}
1667
1668int
1669ahd_brddat_print(u_int regvalue, u_int *cur_col, u_int wrap)
1670{
1671 return (ahd_print_register(NULL, 0, "BRDDAT",
1672 0xb8, regvalue, cur_col, wrap));
1673}
1674
1675static const ahd_reg_parse_entry_t BRDCTL_parse_table[] = {
1676 { "BRDSTB", 0x01, 0x01 },
1677 { "BRDRW", 0x02, 0x02 },
1678 { "BRDEN", 0x04, 0x04 },
1679 { "BRDADDR", 0x38, 0x38 },
1680 { "FLXARBREQ", 0x40, 0x40 },
1681 { "FLXARBACK", 0x80, 0x80 }
1682};
1683
1684int
1685ahd_brdctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
1686{
1687 return (ahd_print_register(BRDCTL_parse_table, 6, "BRDCTL",
1688 0xb9, regvalue, cur_col, wrap));
1689}
1690
1691int
1692ahd_seeadr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1693{
1694 return (ahd_print_register(NULL, 0, "SEEADR",
1695 0xba, regvalue, cur_col, wrap));
1696}
1697
1698int
1699ahd_seedat_print(u_int regvalue, u_int *cur_col, u_int wrap)
1700{
1701 return (ahd_print_register(NULL, 0, "SEEDAT",
1702 0xbc, regvalue, cur_col, wrap));
1703}
1704
1705static const ahd_reg_parse_entry_t SEECTL_parse_table[] = {
1706 { "SEEOP_ERAL", 0x40, 0x70 },
1707 { "SEEOP_WRITE", 0x50, 0x70 },
1708 { "SEEOP_READ", 0x60, 0x70 },
1709 { "SEEOP_ERASE", 0x70, 0x70 },
1710 { "SEESTART", 0x01, 0x01 },
1711 { "SEERST", 0x02, 0x02 },
1712 { "SEEOPCODE", 0x70, 0x70 },
1713 { "SEEOP_EWEN", 0x40, 0x40 },
1714 { "SEEOP_WALL", 0x40, 0x40 },
1715 { "SEEOP_EWDS", 0x40, 0x40 }
1716};
1717
1718int
1719ahd_seectl_print(u_int regvalue, u_int *cur_col, u_int wrap)
1720{
1721 return (ahd_print_register(SEECTL_parse_table, 10, "SEECTL",
1722 0xbe, regvalue, cur_col, wrap));
1723}
1724
1725static const ahd_reg_parse_entry_t SEESTAT_parse_table[] = {
1726 { "SEESTART", 0x01, 0x01 },
1727 { "SEEBUSY", 0x02, 0x02 },
1728 { "SEEARBACK", 0x04, 0x04 },
1729 { "LDALTID_L", 0x08, 0x08 },
1730 { "SEEOPCODE", 0x70, 0x70 },
1731 { "INIT_DONE", 0x80, 0x80 }
1732};
1733
1734int
1735ahd_seestat_print(u_int regvalue, u_int *cur_col, u_int wrap)
1736{
1737 return (ahd_print_register(SEESTAT_parse_table, 6, "SEESTAT",
1738 0xbe, regvalue, cur_col, wrap));
1739}
1740
1741static const ahd_reg_parse_entry_t DSPDATACTL_parse_table[] = {
1742 { "XMITOFFSTDIS", 0x02, 0x02 },
1743 { "RCVROFFSTDIS", 0x04, 0x04 },
1744 { "DESQDIS", 0x10, 0x10 },
1745 { "BYPASSENAB", 0x80, 0x80 }
1746};
1747
1748int
1749ahd_dspdatactl_print(u_int regvalue, u_int *cur_col, u_int wrap)
1750{
1751 return (ahd_print_register(DSPDATACTL_parse_table, 4, "DSPDATACTL",
1752 0xc1, regvalue, cur_col, wrap));
1753}
1754
1755int
1756ahd_dfdat_print(u_int regvalue, u_int *cur_col, u_int wrap)
1757{
1758 return (ahd_print_register(NULL, 0, "DFDAT",
1759 0xc4, regvalue, cur_col, wrap));
1760}
1761
1762static const ahd_reg_parse_entry_t DSPSELECT_parse_table[] = {
1763 { "DSPSEL", 0x1f, 0x1f },
1764 { "AUTOINCEN", 0x80, 0x80 }
1765};
1766
1767int
1768ahd_dspselect_print(u_int regvalue, u_int *cur_col, u_int wrap)
1769{
1770 return (ahd_print_register(DSPSELECT_parse_table, 2, "DSPSELECT",
1771 0xc4, regvalue, cur_col, wrap));
1772}
1773
1774static const ahd_reg_parse_entry_t WRTBIASCTL_parse_table[] = {
1775 { "XMITMANVAL", 0x3f, 0x3f },
1776 { "AUTOXBCDIS", 0x80, 0x80 }
1777};
1778
1779int
1780ahd_wrtbiasctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
1781{
1782 return (ahd_print_register(WRTBIASCTL_parse_table, 2, "WRTBIASCTL",
1783 0xc5, regvalue, cur_col, wrap));
1784}
1785
1786static const ahd_reg_parse_entry_t SEQCTL0_parse_table[] = { 578static const ahd_reg_parse_entry_t SEQCTL0_parse_table[] = {
1787 { "LOADRAM", 0x01, 0x01 }, 579 { "LOADRAM", 0x01, 0x01 },
1788 { "SEQRESET", 0x02, 0x02 }, 580 { "SEQRESET", 0x02, 0x02 },
@@ -1801,18 +593,6 @@ ahd_seqctl0_print(u_int regvalue, u_int *cur_col, u_int wrap)
1801 0xd6, regvalue, cur_col, wrap)); 593 0xd6, regvalue, cur_col, wrap));
1802} 594}
1803 595
1804static const ahd_reg_parse_entry_t FLAGS_parse_table[] = {
1805 { "CARRY", 0x01, 0x01 },
1806 { "ZERO", 0x02, 0x02 }
1807};
1808
1809int
1810ahd_flags_print(u_int regvalue, u_int *cur_col, u_int wrap)
1811{
1812 return (ahd_print_register(FLAGS_parse_table, 2, "FLAGS",
1813 0xd8, regvalue, cur_col, wrap));
1814}
1815
1816static const ahd_reg_parse_entry_t SEQINTCTL_parse_table[] = { 596static const ahd_reg_parse_entry_t SEQINTCTL_parse_table[] = {
1817 { "IRET", 0x01, 0x01 }, 597 { "IRET", 0x01, 0x01 },
1818 { "INTMASK1", 0x02, 0x02 }, 598 { "INTMASK1", 0x02, 0x02 },
@@ -1831,118 +611,6 @@ ahd_seqintctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
1831} 611}
1832 612
1833int 613int
1834ahd_seqram_print(u_int regvalue, u_int *cur_col, u_int wrap)
1835{
1836 return (ahd_print_register(NULL, 0, "SEQRAM",
1837 0xda, regvalue, cur_col, wrap));
1838}
1839
1840int
1841ahd_prgmcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
1842{
1843 return (ahd_print_register(NULL, 0, "PRGMCNT",
1844 0xde, regvalue, cur_col, wrap));
1845}
1846
1847int
1848ahd_accum_print(u_int regvalue, u_int *cur_col, u_int wrap)
1849{
1850 return (ahd_print_register(NULL, 0, "ACCUM",
1851 0xe0, regvalue, cur_col, wrap));
1852}
1853
1854int
1855ahd_sindex_print(u_int regvalue, u_int *cur_col, u_int wrap)
1856{
1857 return (ahd_print_register(NULL, 0, "SINDEX",
1858 0xe2, regvalue, cur_col, wrap));
1859}
1860
1861int
1862ahd_dindex_print(u_int regvalue, u_int *cur_col, u_int wrap)
1863{
1864 return (ahd_print_register(NULL, 0, "DINDEX",
1865 0xe4, regvalue, cur_col, wrap));
1866}
1867
1868int
1869ahd_allones_print(u_int regvalue, u_int *cur_col, u_int wrap)
1870{
1871 return (ahd_print_register(NULL, 0, "ALLONES",
1872 0xe8, regvalue, cur_col, wrap));
1873}
1874
1875int
1876ahd_allzeros_print(u_int regvalue, u_int *cur_col, u_int wrap)
1877{
1878 return (ahd_print_register(NULL, 0, "ALLZEROS",
1879 0xea, regvalue, cur_col, wrap));
1880}
1881
1882int
1883ahd_none_print(u_int regvalue, u_int *cur_col, u_int wrap)
1884{
1885 return (ahd_print_register(NULL, 0, "NONE",
1886 0xea, regvalue, cur_col, wrap));
1887}
1888
1889int
1890ahd_sindir_print(u_int regvalue, u_int *cur_col, u_int wrap)
1891{
1892 return (ahd_print_register(NULL, 0, "SINDIR",
1893 0xec, regvalue, cur_col, wrap));
1894}
1895
1896int
1897ahd_dindir_print(u_int regvalue, u_int *cur_col, u_int wrap)
1898{
1899 return (ahd_print_register(NULL, 0, "DINDIR",
1900 0xed, regvalue, cur_col, wrap));
1901}
1902
1903int
1904ahd_stack_print(u_int regvalue, u_int *cur_col, u_int wrap)
1905{
1906 return (ahd_print_register(NULL, 0, "STACK",
1907 0xf2, regvalue, cur_col, wrap));
1908}
1909
1910int
1911ahd_intvec1_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1912{
1913 return (ahd_print_register(NULL, 0, "INTVEC1_ADDR",
1914 0xf4, regvalue, cur_col, wrap));
1915}
1916
1917int
1918ahd_curaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1919{
1920 return (ahd_print_register(NULL, 0, "CURADDR",
1921 0xf4, regvalue, cur_col, wrap));
1922}
1923
1924int
1925ahd_intvec2_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1926{
1927 return (ahd_print_register(NULL, 0, "INTVEC2_ADDR",
1928 0xf6, regvalue, cur_col, wrap));
1929}
1930
1931int
1932ahd_longjmp_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1933{
1934 return (ahd_print_register(NULL, 0, "LONGJMP_ADDR",
1935 0xf8, regvalue, cur_col, wrap));
1936}
1937
1938int
1939ahd_accum_save_print(u_int regvalue, u_int *cur_col, u_int wrap)
1940{
1941 return (ahd_print_register(NULL, 0, "ACCUM_SAVE",
1942 0xfa, regvalue, cur_col, wrap));
1943}
1944
1945int
1946ahd_sram_base_print(u_int regvalue, u_int *cur_col, u_int wrap) 614ahd_sram_base_print(u_int regvalue, u_int *cur_col, u_int wrap)
1947{ 615{
1948 return (ahd_print_register(NULL, 0, "SRAM_BASE", 616 return (ahd_print_register(NULL, 0, "SRAM_BASE",
@@ -1950,69 +618,6 @@ ahd_sram_base_print(u_int regvalue, u_int *cur_col, u_int wrap)
1950} 618}
1951 619
1952int 620int
1953ahd_waiting_scb_tails_print(u_int regvalue, u_int *cur_col, u_int wrap)
1954{
1955 return (ahd_print_register(NULL, 0, "WAITING_SCB_TAILS",
1956 0x100, regvalue, cur_col, wrap));
1957}
1958
1959int
1960ahd_waiting_tid_head_print(u_int regvalue, u_int *cur_col, u_int wrap)
1961{
1962 return (ahd_print_register(NULL, 0, "WAITING_TID_HEAD",
1963 0x120, regvalue, cur_col, wrap));
1964}
1965
1966int
1967ahd_waiting_tid_tail_print(u_int regvalue, u_int *cur_col, u_int wrap)
1968{
1969 return (ahd_print_register(NULL, 0, "WAITING_TID_TAIL",
1970 0x122, regvalue, cur_col, wrap));
1971}
1972
1973int
1974ahd_next_queued_scb_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1975{
1976 return (ahd_print_register(NULL, 0, "NEXT_QUEUED_SCB_ADDR",
1977 0x124, regvalue, cur_col, wrap));
1978}
1979
1980int
1981ahd_complete_scb_head_print(u_int regvalue, u_int *cur_col, u_int wrap)
1982{
1983 return (ahd_print_register(NULL, 0, "COMPLETE_SCB_HEAD",
1984 0x128, regvalue, cur_col, wrap));
1985}
1986
1987int
1988ahd_complete_scb_dmainprog_head_print(u_int regvalue, u_int *cur_col, u_int wrap)
1989{
1990 return (ahd_print_register(NULL, 0, "COMPLETE_SCB_DMAINPROG_HEAD",
1991 0x12a, regvalue, cur_col, wrap));
1992}
1993
1994int
1995ahd_complete_dma_scb_head_print(u_int regvalue, u_int *cur_col, u_int wrap)
1996{
1997 return (ahd_print_register(NULL, 0, "COMPLETE_DMA_SCB_HEAD",
1998 0x12c, regvalue, cur_col, wrap));
1999}
2000
2001int
2002ahd_complete_dma_scb_tail_print(u_int regvalue, u_int *cur_col, u_int wrap)
2003{
2004 return (ahd_print_register(NULL, 0, "COMPLETE_DMA_SCB_TAIL",
2005 0x12e, regvalue, cur_col, wrap));
2006}
2007
2008int
2009ahd_complete_on_qfreeze_head_print(u_int regvalue, u_int *cur_col, u_int wrap)
2010{
2011 return (ahd_print_register(NULL, 0, "COMPLETE_ON_QFREEZE_HEAD",
2012 0x130, regvalue, cur_col, wrap));
2013}
2014
2015int
2016ahd_qfreeze_count_print(u_int regvalue, u_int *cur_col, u_int wrap) 621ahd_qfreeze_count_print(u_int regvalue, u_int *cur_col, u_int wrap)
2017{ 622{
2018 return (ahd_print_register(NULL, 0, "QFREEZE_COUNT", 623 return (ahd_print_register(NULL, 0, "QFREEZE_COUNT",
@@ -2033,33 +638,6 @@ ahd_saved_mode_print(u_int regvalue, u_int *cur_col, u_int wrap)
2033 0x136, regvalue, cur_col, wrap)); 638 0x136, regvalue, cur_col, wrap));
2034} 639}
2035 640
2036int
2037ahd_msg_out_print(u_int regvalue, u_int *cur_col, u_int wrap)
2038{
2039 return (ahd_print_register(NULL, 0, "MSG_OUT",
2040 0x137, regvalue, cur_col, wrap));
2041}
2042
2043static const ahd_reg_parse_entry_t DMAPARAMS_parse_table[] = {
2044 { "FIFORESET", 0x01, 0x01 },
2045 { "FIFOFLUSH", 0x02, 0x02 },
2046 { "DIRECTION", 0x04, 0x04 },
2047 { "HDMAEN", 0x08, 0x08 },
2048 { "HDMAENACK", 0x08, 0x08 },
2049 { "SDMAEN", 0x10, 0x10 },
2050 { "SDMAENACK", 0x10, 0x10 },
2051 { "SCSIEN", 0x20, 0x20 },
2052 { "WIDEODD", 0x40, 0x40 },
2053 { "PRELOADEN", 0x80, 0x80 }
2054};
2055
2056int
2057ahd_dmaparams_print(u_int regvalue, u_int *cur_col, u_int wrap)
2058{
2059 return (ahd_print_register(DMAPARAMS_parse_table, 10, "DMAPARAMS",
2060 0x138, regvalue, cur_col, wrap));
2061}
2062
2063static const ahd_reg_parse_entry_t SEQ_FLAGS_parse_table[] = { 641static const ahd_reg_parse_entry_t SEQ_FLAGS_parse_table[] = {
2064 { "NO_DISCONNECT", 0x01, 0x01 }, 642 { "NO_DISCONNECT", 0x01, 0x01 },
2065 { "SPHASE_PENDING", 0x02, 0x02 }, 643 { "SPHASE_PENDING", 0x02, 0x02 },
@@ -2079,20 +657,6 @@ ahd_seq_flags_print(u_int regvalue, u_int *cur_col, u_int wrap)
2079 0x139, regvalue, cur_col, wrap)); 657 0x139, regvalue, cur_col, wrap));
2080} 658}
2081 659
2082int
2083ahd_saved_scsiid_print(u_int regvalue, u_int *cur_col, u_int wrap)
2084{
2085 return (ahd_print_register(NULL, 0, "SAVED_SCSIID",
2086 0x13a, regvalue, cur_col, wrap));
2087}
2088
2089int
2090ahd_saved_lun_print(u_int regvalue, u_int *cur_col, u_int wrap)
2091{
2092 return (ahd_print_register(NULL, 0, "SAVED_LUN",
2093 0x13b, regvalue, cur_col, wrap));
2094}
2095
2096static const ahd_reg_parse_entry_t LASTPHASE_parse_table[] = { 660static const ahd_reg_parse_entry_t LASTPHASE_parse_table[] = {
2097 { "P_DATAOUT", 0x00, 0xe0 }, 661 { "P_DATAOUT", 0x00, 0xe0 },
2098 { "P_DATAOUT_DT", 0x20, 0xe0 }, 662 { "P_DATAOUT_DT", 0x20, 0xe0 },
@@ -2116,96 +680,6 @@ ahd_lastphase_print(u_int regvalue, u_int *cur_col, u_int wrap)
2116 0x13c, regvalue, cur_col, wrap)); 680 0x13c, regvalue, cur_col, wrap));
2117} 681}
2118 682
2119int
2120ahd_qoutfifo_entry_valid_tag_print(u_int regvalue, u_int *cur_col, u_int wrap)
2121{
2122 return (ahd_print_register(NULL, 0, "QOUTFIFO_ENTRY_VALID_TAG",
2123 0x13d, regvalue, cur_col, wrap));
2124}
2125
2126int
2127ahd_kernel_tqinpos_print(u_int regvalue, u_int *cur_col, u_int wrap)
2128{
2129 return (ahd_print_register(NULL, 0, "KERNEL_TQINPOS",
2130 0x13e, regvalue, cur_col, wrap));
2131}
2132
2133int
2134ahd_tqinpos_print(u_int regvalue, u_int *cur_col, u_int wrap)
2135{
2136 return (ahd_print_register(NULL, 0, "TQINPOS",
2137 0x13f, regvalue, cur_col, wrap));
2138}
2139
2140int
2141ahd_shared_data_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
2142{
2143 return (ahd_print_register(NULL, 0, "SHARED_DATA_ADDR",
2144 0x140, regvalue, cur_col, wrap));
2145}
2146
2147int
2148ahd_qoutfifo_next_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
2149{
2150 return (ahd_print_register(NULL, 0, "QOUTFIFO_NEXT_ADDR",
2151 0x144, regvalue, cur_col, wrap));
2152}
2153
2154static const ahd_reg_parse_entry_t ARG_1_parse_table[] = {
2155 { "CONT_MSG_LOOP_TARG", 0x02, 0x02 },
2156 { "CONT_MSG_LOOP_READ", 0x03, 0x03 },
2157 { "CONT_MSG_LOOP_WRITE",0x04, 0x04 },
2158 { "EXIT_MSG_LOOP", 0x08, 0x08 },
2159 { "MSGOUT_PHASEMIS", 0x10, 0x10 },
2160 { "SEND_REJ", 0x20, 0x20 },
2161 { "SEND_SENSE", 0x40, 0x40 },
2162 { "SEND_MSG", 0x80, 0x80 }
2163};
2164
2165int
2166ahd_arg_1_print(u_int regvalue, u_int *cur_col, u_int wrap)
2167{
2168 return (ahd_print_register(ARG_1_parse_table, 8, "ARG_1",
2169 0x148, regvalue, cur_col, wrap));
2170}
2171
2172int
2173ahd_arg_2_print(u_int regvalue, u_int *cur_col, u_int wrap)
2174{
2175 return (ahd_print_register(NULL, 0, "ARG_2",
2176 0x149, regvalue, cur_col, wrap));
2177}
2178
2179int
2180ahd_last_msg_print(u_int regvalue, u_int *cur_col, u_int wrap)
2181{
2182 return (ahd_print_register(NULL, 0, "LAST_MSG",
2183 0x14a, regvalue, cur_col, wrap));
2184}
2185
2186static const ahd_reg_parse_entry_t SCSISEQ_TEMPLATE_parse_table[] = {
2187 { "ALTSTIM", 0x01, 0x01 },
2188 { "ENAUTOATNP", 0x02, 0x02 },
2189 { "MANUALP", 0x0c, 0x0c },
2190 { "ENRSELI", 0x10, 0x10 },
2191 { "ENSELI", 0x20, 0x20 },
2192 { "MANUALCTL", 0x40, 0x40 }
2193};
2194
2195int
2196ahd_scsiseq_template_print(u_int regvalue, u_int *cur_col, u_int wrap)
2197{
2198 return (ahd_print_register(SCSISEQ_TEMPLATE_parse_table, 6, "SCSISEQ_TEMPLATE",
2199 0x14b, regvalue, cur_col, wrap));
2200}
2201
2202int
2203ahd_initiator_tag_print(u_int regvalue, u_int *cur_col, u_int wrap)
2204{
2205 return (ahd_print_register(NULL, 0, "INITIATOR_TAG",
2206 0x14c, regvalue, cur_col, wrap));
2207}
2208
2209static const ahd_reg_parse_entry_t SEQ_FLAGS2_parse_table[] = { 683static const ahd_reg_parse_entry_t SEQ_FLAGS2_parse_table[] = {
2210 { "PENDING_MK_MESSAGE", 0x01, 0x01 }, 684 { "PENDING_MK_MESSAGE", 0x01, 0x01 },
2211 { "TARGET_MSG_PENDING", 0x02, 0x02 }, 685 { "TARGET_MSG_PENDING", 0x02, 0x02 },
@@ -2220,62 +694,6 @@ ahd_seq_flags2_print(u_int regvalue, u_int *cur_col, u_int wrap)
2220} 694}
2221 695
2222int 696int
2223ahd_allocfifo_scbptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
2224{
2225 return (ahd_print_register(NULL, 0, "ALLOCFIFO_SCBPTR",
2226 0x14e, regvalue, cur_col, wrap));
2227}
2228
2229int
2230ahd_int_coalescing_timer_print(u_int regvalue, u_int *cur_col, u_int wrap)
2231{
2232 return (ahd_print_register(NULL, 0, "INT_COALESCING_TIMER",
2233 0x150, regvalue, cur_col, wrap));
2234}
2235
2236int
2237ahd_int_coalescing_maxcmds_print(u_int regvalue, u_int *cur_col, u_int wrap)
2238{
2239 return (ahd_print_register(NULL, 0, "INT_COALESCING_MAXCMDS",
2240 0x152, regvalue, cur_col, wrap));
2241}
2242
2243int
2244ahd_int_coalescing_mincmds_print(u_int regvalue, u_int *cur_col, u_int wrap)
2245{
2246 return (ahd_print_register(NULL, 0, "INT_COALESCING_MINCMDS",
2247 0x153, regvalue, cur_col, wrap));
2248}
2249
2250int
2251ahd_cmds_pending_print(u_int regvalue, u_int *cur_col, u_int wrap)
2252{
2253 return (ahd_print_register(NULL, 0, "CMDS_PENDING",
2254 0x154, regvalue, cur_col, wrap));
2255}
2256
2257int
2258ahd_int_coalescing_cmdcount_print(u_int regvalue, u_int *cur_col, u_int wrap)
2259{
2260 return (ahd_print_register(NULL, 0, "INT_COALESCING_CMDCOUNT",
2261 0x156, regvalue, cur_col, wrap));
2262}
2263
2264int
2265ahd_local_hs_mailbox_print(u_int regvalue, u_int *cur_col, u_int wrap)
2266{
2267 return (ahd_print_register(NULL, 0, "LOCAL_HS_MAILBOX",
2268 0x157, regvalue, cur_col, wrap));
2269}
2270
2271int
2272ahd_cmdsize_table_print(u_int regvalue, u_int *cur_col, u_int wrap)
2273{
2274 return (ahd_print_register(NULL, 0, "CMDSIZE_TABLE",
2275 0x158, regvalue, cur_col, wrap));
2276}
2277
2278int
2279ahd_mk_message_scb_print(u_int regvalue, u_int *cur_col, u_int wrap) 697ahd_mk_message_scb_print(u_int regvalue, u_int *cur_col, u_int wrap)
2280{ 698{
2281 return (ahd_print_register(NULL, 0, "MK_MESSAGE_SCB", 699 return (ahd_print_register(NULL, 0, "MK_MESSAGE_SCB",
@@ -2290,53 +708,12 @@ ahd_mk_message_scsiid_print(u_int regvalue, u_int *cur_col, u_int wrap)
2290} 708}
2291 709
2292int 710int
2293ahd_scb_residual_datacnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
2294{
2295 return (ahd_print_register(NULL, 0, "SCB_RESIDUAL_DATACNT",
2296 0x180, regvalue, cur_col, wrap));
2297}
2298
2299int
2300ahd_scb_base_print(u_int regvalue, u_int *cur_col, u_int wrap) 711ahd_scb_base_print(u_int regvalue, u_int *cur_col, u_int wrap)
2301{ 712{
2302 return (ahd_print_register(NULL, 0, "SCB_BASE", 713 return (ahd_print_register(NULL, 0, "SCB_BASE",
2303 0x180, regvalue, cur_col, wrap)); 714 0x180, regvalue, cur_col, wrap));
2304} 715}
2305 716
2306static const ahd_reg_parse_entry_t SCB_RESIDUAL_SGPTR_parse_table[] = {
2307 { "SG_LIST_NULL", 0x01, 0x01 },
2308 { "SG_OVERRUN_RESID", 0x02, 0x02 },
2309 { "SG_ADDR_MASK", 0xf8, 0xf8 }
2310};
2311
2312int
2313ahd_scb_residual_sgptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
2314{
2315 return (ahd_print_register(SCB_RESIDUAL_SGPTR_parse_table, 3, "SCB_RESIDUAL_SGPTR",
2316 0x184, regvalue, cur_col, wrap));
2317}
2318
2319int
2320ahd_scb_scsi_status_print(u_int regvalue, u_int *cur_col, u_int wrap)
2321{
2322 return (ahd_print_register(NULL, 0, "SCB_SCSI_STATUS",
2323 0x188, regvalue, cur_col, wrap));
2324}
2325
2326int
2327ahd_scb_sense_busaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
2328{
2329 return (ahd_print_register(NULL, 0, "SCB_SENSE_BUSADDR",
2330 0x18c, regvalue, cur_col, wrap));
2331}
2332
2333int
2334ahd_scb_tag_print(u_int regvalue, u_int *cur_col, u_int wrap)
2335{
2336 return (ahd_print_register(NULL, 0, "SCB_TAG",
2337 0x190, regvalue, cur_col, wrap));
2338}
2339
2340static const ahd_reg_parse_entry_t SCB_CONTROL_parse_table[] = { 717static const ahd_reg_parse_entry_t SCB_CONTROL_parse_table[] = {
2341 { "SCB_TAG_TYPE", 0x03, 0x03 }, 718 { "SCB_TAG_TYPE", 0x03, 0x03 },
2342 { "DISCONNECTED", 0x04, 0x04 }, 719 { "DISCONNECTED", 0x04, 0x04 },
@@ -2366,103 +743,3 @@ ahd_scb_scsiid_print(u_int regvalue, u_int *cur_col, u_int wrap)
2366 0x193, regvalue, cur_col, wrap)); 743 0x193, regvalue, cur_col, wrap));
2367} 744}
2368 745
2369static const ahd_reg_parse_entry_t SCB_LUN_parse_table[] = {
2370 { "LID", 0xff, 0xff }
2371};
2372
2373int
2374ahd_scb_lun_print(u_int regvalue, u_int *cur_col, u_int wrap)
2375{
2376 return (ahd_print_register(SCB_LUN_parse_table, 1, "SCB_LUN",
2377 0x194, regvalue, cur_col, wrap));
2378}
2379
2380static const ahd_reg_parse_entry_t SCB_TASK_ATTRIBUTE_parse_table[] = {
2381 { "SCB_XFERLEN_ODD", 0x01, 0x01 }
2382};
2383
2384int
2385ahd_scb_task_attribute_print(u_int regvalue, u_int *cur_col, u_int wrap)
2386{
2387 return (ahd_print_register(SCB_TASK_ATTRIBUTE_parse_table, 1, "SCB_TASK_ATTRIBUTE",
2388 0x195, regvalue, cur_col, wrap));
2389}
2390
2391static const ahd_reg_parse_entry_t SCB_CDB_LEN_parse_table[] = {
2392 { "SCB_CDB_LEN_PTR", 0x80, 0x80 }
2393};
2394
2395int
2396ahd_scb_cdb_len_print(u_int regvalue, u_int *cur_col, u_int wrap)
2397{
2398 return (ahd_print_register(SCB_CDB_LEN_parse_table, 1, "SCB_CDB_LEN",
2399 0x196, regvalue, cur_col, wrap));
2400}
2401
2402int
2403ahd_scb_task_management_print(u_int regvalue, u_int *cur_col, u_int wrap)
2404{
2405 return (ahd_print_register(NULL, 0, "SCB_TASK_MANAGEMENT",
2406 0x197, regvalue, cur_col, wrap));
2407}
2408
2409int
2410ahd_scb_dataptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
2411{
2412 return (ahd_print_register(NULL, 0, "SCB_DATAPTR",
2413 0x198, regvalue, cur_col, wrap));
2414}
2415
2416static const ahd_reg_parse_entry_t SCB_DATACNT_parse_table[] = {
2417 { "SG_HIGH_ADDR_BITS", 0x7f, 0x7f },
2418 { "SG_LAST_SEG", 0x80, 0x80 }
2419};
2420
2421int
2422ahd_scb_datacnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
2423{
2424 return (ahd_print_register(SCB_DATACNT_parse_table, 2, "SCB_DATACNT",
2425 0x1a0, regvalue, cur_col, wrap));
2426}
2427
2428static const ahd_reg_parse_entry_t SCB_SGPTR_parse_table[] = {
2429 { "SG_LIST_NULL", 0x01, 0x01 },
2430 { "SG_FULL_RESID", 0x02, 0x02 },
2431 { "SG_STATUS_VALID", 0x04, 0x04 }
2432};
2433
2434int
2435ahd_scb_sgptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
2436{
2437 return (ahd_print_register(SCB_SGPTR_parse_table, 3, "SCB_SGPTR",
2438 0x1a4, regvalue, cur_col, wrap));
2439}
2440
2441int
2442ahd_scb_busaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
2443{
2444 return (ahd_print_register(NULL, 0, "SCB_BUSADDR",
2445 0x1a8, regvalue, cur_col, wrap));
2446}
2447
2448int
2449ahd_scb_next_print(u_int regvalue, u_int *cur_col, u_int wrap)
2450{
2451 return (ahd_print_register(NULL, 0, "SCB_NEXT",
2452 0x1ac, regvalue, cur_col, wrap));
2453}
2454
2455int
2456ahd_scb_next2_print(u_int regvalue, u_int *cur_col, u_int wrap)
2457{
2458 return (ahd_print_register(NULL, 0, "SCB_NEXT2",
2459 0x1ae, regvalue, cur_col, wrap));
2460}
2461
2462int
2463ahd_scb_disconnected_lists_print(u_int regvalue, u_int *cur_col, u_int wrap)
2464{
2465 return (ahd_print_register(NULL, 0, "SCB_DISCONNECTED_LISTS",
2466 0x1b8, regvalue, cur_col, wrap));
2467}
2468
diff --git a/drivers/scsi/aic7xxx/aic7xxx_reg.h_shipped b/drivers/scsi/aic7xxx/aic7xxx_reg.h_shipped
index 2ce1febca207..e821082a4f47 100644
--- a/drivers/scsi/aic7xxx/aic7xxx_reg.h_shipped
+++ b/drivers/scsi/aic7xxx/aic7xxx_reg.h_shipped
@@ -27,20 +27,6 @@ ahc_reg_print_t ahc_sxfrctl0_print;
27#endif 27#endif
28 28
29#if AIC_DEBUG_REGISTERS 29#if AIC_DEBUG_REGISTERS
30ahc_reg_print_t ahc_sxfrctl1_print;
31#else
32#define ahc_sxfrctl1_print(regvalue, cur_col, wrap) \
33 ahc_print_register(NULL, 0, "SXFRCTL1", 0x02, regvalue, cur_col, wrap)
34#endif
35
36#if AIC_DEBUG_REGISTERS
37ahc_reg_print_t ahc_scsisigo_print;
38#else
39#define ahc_scsisigo_print(regvalue, cur_col, wrap) \
40 ahc_print_register(NULL, 0, "SCSISIGO", 0x03, regvalue, cur_col, wrap)
41#endif
42
43#if AIC_DEBUG_REGISTERS
44ahc_reg_print_t ahc_scsisigi_print; 30ahc_reg_print_t ahc_scsisigi_print;
45#else 31#else
46#define ahc_scsisigi_print(regvalue, cur_col, wrap) \ 32#define ahc_scsisigi_print(regvalue, cur_col, wrap) \
@@ -55,55 +41,6 @@ ahc_reg_print_t ahc_scsirate_print;
55#endif 41#endif
56 42
57#if AIC_DEBUG_REGISTERS 43#if AIC_DEBUG_REGISTERS
58ahc_reg_print_t ahc_scsiid_print;
59#else
60#define ahc_scsiid_print(regvalue, cur_col, wrap) \
61 ahc_print_register(NULL, 0, "SCSIID", 0x05, regvalue, cur_col, wrap)
62#endif
63
64#if AIC_DEBUG_REGISTERS
65ahc_reg_print_t ahc_scsidatl_print;
66#else
67#define ahc_scsidatl_print(regvalue, cur_col, wrap) \
68 ahc_print_register(NULL, 0, "SCSIDATL", 0x06, regvalue, cur_col, wrap)
69#endif
70
71#if AIC_DEBUG_REGISTERS
72ahc_reg_print_t ahc_scsidath_print;
73#else
74#define ahc_scsidath_print(regvalue, cur_col, wrap) \
75 ahc_print_register(NULL, 0, "SCSIDATH", 0x07, regvalue, cur_col, wrap)
76#endif
77
78#if AIC_DEBUG_REGISTERS
79ahc_reg_print_t ahc_stcnt_print;
80#else
81#define ahc_stcnt_print(regvalue, cur_col, wrap) \
82 ahc_print_register(NULL, 0, "STCNT", 0x08, regvalue, cur_col, wrap)
83#endif
84
85#if AIC_DEBUG_REGISTERS
86ahc_reg_print_t ahc_optionmode_print;
87#else
88#define ahc_optionmode_print(regvalue, cur_col, wrap) \
89 ahc_print_register(NULL, 0, "OPTIONMODE", 0x08, regvalue, cur_col, wrap)
90#endif
91
92#if AIC_DEBUG_REGISTERS
93ahc_reg_print_t ahc_targcrccnt_print;
94#else
95#define ahc_targcrccnt_print(regvalue, cur_col, wrap) \
96 ahc_print_register(NULL, 0, "TARGCRCCNT", 0x0a, regvalue, cur_col, wrap)
97#endif
98
99#if AIC_DEBUG_REGISTERS
100ahc_reg_print_t ahc_clrsint0_print;
101#else
102#define ahc_clrsint0_print(regvalue, cur_col, wrap) \
103 ahc_print_register(NULL, 0, "CLRSINT0", 0x0b, regvalue, cur_col, wrap)
104#endif
105
106#if AIC_DEBUG_REGISTERS
107ahc_reg_print_t ahc_sstat0_print; 44ahc_reg_print_t ahc_sstat0_print;
108#else 45#else
109#define ahc_sstat0_print(regvalue, cur_col, wrap) \ 46#define ahc_sstat0_print(regvalue, cur_col, wrap) \
@@ -111,13 +48,6 @@ ahc_reg_print_t ahc_sstat0_print;
111#endif 48#endif
112 49
113#if AIC_DEBUG_REGISTERS 50#if AIC_DEBUG_REGISTERS
114ahc_reg_print_t ahc_clrsint1_print;
115#else
116#define ahc_clrsint1_print(regvalue, cur_col, wrap) \
117 ahc_print_register(NULL, 0, "CLRSINT1", 0x0c, regvalue, cur_col, wrap)
118#endif
119
120#if AIC_DEBUG_REGISTERS
121ahc_reg_print_t ahc_sstat1_print; 51ahc_reg_print_t ahc_sstat1_print;
122#else 52#else
123#define ahc_sstat1_print(regvalue, cur_col, wrap) \ 53#define ahc_sstat1_print(regvalue, cur_col, wrap) \
@@ -139,13 +69,6 @@ ahc_reg_print_t ahc_sstat3_print;
139#endif 69#endif
140 70
141#if AIC_DEBUG_REGISTERS 71#if AIC_DEBUG_REGISTERS
142ahc_reg_print_t ahc_scsiid_ultra2_print;
143#else
144#define ahc_scsiid_ultra2_print(regvalue, cur_col, wrap) \
145 ahc_print_register(NULL, 0, "SCSIID_ULTRA2", 0x0f, regvalue, cur_col, wrap)
146#endif
147
148#if AIC_DEBUG_REGISTERS
149ahc_reg_print_t ahc_simode0_print; 72ahc_reg_print_t ahc_simode0_print;
150#else 73#else
151#define ahc_simode0_print(regvalue, cur_col, wrap) \ 74#define ahc_simode0_print(regvalue, cur_col, wrap) \
@@ -167,76 +90,6 @@ ahc_reg_print_t ahc_scsibusl_print;
167#endif 90#endif
168 91
169#if AIC_DEBUG_REGISTERS 92#if AIC_DEBUG_REGISTERS
170ahc_reg_print_t ahc_scsibush_print;
171#else
172#define ahc_scsibush_print(regvalue, cur_col, wrap) \
173 ahc_print_register(NULL, 0, "SCSIBUSH", 0x13, regvalue, cur_col, wrap)
174#endif
175
176#if AIC_DEBUG_REGISTERS
177ahc_reg_print_t ahc_sxfrctl2_print;
178#else
179#define ahc_sxfrctl2_print(regvalue, cur_col, wrap) \
180 ahc_print_register(NULL, 0, "SXFRCTL2", 0x13, regvalue, cur_col, wrap)
181#endif
182
183#if AIC_DEBUG_REGISTERS
184ahc_reg_print_t ahc_shaddr_print;
185#else
186#define ahc_shaddr_print(regvalue, cur_col, wrap) \
187 ahc_print_register(NULL, 0, "SHADDR", 0x14, regvalue, cur_col, wrap)
188#endif
189
190#if AIC_DEBUG_REGISTERS
191ahc_reg_print_t ahc_seltimer_print;
192#else
193#define ahc_seltimer_print(regvalue, cur_col, wrap) \
194 ahc_print_register(NULL, 0, "SELTIMER", 0x18, regvalue, cur_col, wrap)
195#endif
196
197#if AIC_DEBUG_REGISTERS
198ahc_reg_print_t ahc_selid_print;
199#else
200#define ahc_selid_print(regvalue, cur_col, wrap) \
201 ahc_print_register(NULL, 0, "SELID", 0x19, regvalue, cur_col, wrap)
202#endif
203
204#if AIC_DEBUG_REGISTERS
205ahc_reg_print_t ahc_scamctl_print;
206#else
207#define ahc_scamctl_print(regvalue, cur_col, wrap) \
208 ahc_print_register(NULL, 0, "SCAMCTL", 0x1a, regvalue, cur_col, wrap)
209#endif
210
211#if AIC_DEBUG_REGISTERS
212ahc_reg_print_t ahc_targid_print;
213#else
214#define ahc_targid_print(regvalue, cur_col, wrap) \
215 ahc_print_register(NULL, 0, "TARGID", 0x1b, regvalue, cur_col, wrap)
216#endif
217
218#if AIC_DEBUG_REGISTERS
219ahc_reg_print_t ahc_spiocap_print;
220#else
221#define ahc_spiocap_print(regvalue, cur_col, wrap) \
222 ahc_print_register(NULL, 0, "SPIOCAP", 0x1b, regvalue, cur_col, wrap)
223#endif
224
225#if AIC_DEBUG_REGISTERS
226ahc_reg_print_t ahc_brdctl_print;
227#else
228#define ahc_brdctl_print(regvalue, cur_col, wrap) \
229 ahc_print_register(NULL, 0, "BRDCTL", 0x1d, regvalue, cur_col, wrap)
230#endif
231
232#if AIC_DEBUG_REGISTERS
233ahc_reg_print_t ahc_seectl_print;
234#else
235#define ahc_seectl_print(regvalue, cur_col, wrap) \
236 ahc_print_register(NULL, 0, "SEECTL", 0x1e, regvalue, cur_col, wrap)
237#endif
238
239#if AIC_DEBUG_REGISTERS
240ahc_reg_print_t ahc_sblkctl_print; 93ahc_reg_print_t ahc_sblkctl_print;
241#else 94#else
242#define ahc_sblkctl_print(regvalue, cur_col, wrap) \ 95#define ahc_sblkctl_print(regvalue, cur_col, wrap) \
@@ -244,62 +97,6 @@ ahc_reg_print_t ahc_sblkctl_print;
244#endif 97#endif
245 98
246#if AIC_DEBUG_REGISTERS 99#if AIC_DEBUG_REGISTERS
247ahc_reg_print_t ahc_busy_targets_print;
248#else
249#define ahc_busy_targets_print(regvalue, cur_col, wrap) \
250 ahc_print_register(NULL, 0, "BUSY_TARGETS", 0x20, regvalue, cur_col, wrap)
251#endif
252
253#if AIC_DEBUG_REGISTERS
254ahc_reg_print_t ahc_ultra_enb_print;
255#else
256#define ahc_ultra_enb_print(regvalue, cur_col, wrap) \
257 ahc_print_register(NULL, 0, "ULTRA_ENB", 0x30, regvalue, cur_col, wrap)
258#endif
259
260#if AIC_DEBUG_REGISTERS
261ahc_reg_print_t ahc_disc_dsb_print;
262#else
263#define ahc_disc_dsb_print(regvalue, cur_col, wrap) \
264 ahc_print_register(NULL, 0, "DISC_DSB", 0x32, regvalue, cur_col, wrap)
265#endif
266
267#if AIC_DEBUG_REGISTERS
268ahc_reg_print_t ahc_cmdsize_table_tail_print;
269#else
270#define ahc_cmdsize_table_tail_print(regvalue, cur_col, wrap) \
271 ahc_print_register(NULL, 0, "CMDSIZE_TABLE_TAIL", 0x34, regvalue, cur_col, wrap)
272#endif
273
274#if AIC_DEBUG_REGISTERS
275ahc_reg_print_t ahc_mwi_residual_print;
276#else
277#define ahc_mwi_residual_print(regvalue, cur_col, wrap) \
278 ahc_print_register(NULL, 0, "MWI_RESIDUAL", 0x38, regvalue, cur_col, wrap)
279#endif
280
281#if AIC_DEBUG_REGISTERS
282ahc_reg_print_t ahc_next_queued_scb_print;
283#else
284#define ahc_next_queued_scb_print(regvalue, cur_col, wrap) \
285 ahc_print_register(NULL, 0, "NEXT_QUEUED_SCB", 0x39, regvalue, cur_col, wrap)
286#endif
287
288#if AIC_DEBUG_REGISTERS
289ahc_reg_print_t ahc_msg_out_print;
290#else
291#define ahc_msg_out_print(regvalue, cur_col, wrap) \
292 ahc_print_register(NULL, 0, "MSG_OUT", 0x3a, regvalue, cur_col, wrap)
293#endif
294
295#if AIC_DEBUG_REGISTERS
296ahc_reg_print_t ahc_dmaparams_print;
297#else
298#define ahc_dmaparams_print(regvalue, cur_col, wrap) \
299 ahc_print_register(NULL, 0, "DMAPARAMS", 0x3b, regvalue, cur_col, wrap)
300#endif
301
302#if AIC_DEBUG_REGISTERS
303ahc_reg_print_t ahc_seq_flags_print; 100ahc_reg_print_t ahc_seq_flags_print;
304#else 101#else
305#define ahc_seq_flags_print(regvalue, cur_col, wrap) \ 102#define ahc_seq_flags_print(regvalue, cur_col, wrap) \
@@ -307,20 +104,6 @@ ahc_reg_print_t ahc_seq_flags_print;
307#endif 104#endif
308 105
309#if AIC_DEBUG_REGISTERS 106#if AIC_DEBUG_REGISTERS
310ahc_reg_print_t ahc_saved_scsiid_print;
311#else
312#define ahc_saved_scsiid_print(regvalue, cur_col, wrap) \
313 ahc_print_register(NULL, 0, "SAVED_SCSIID", 0x3d, regvalue, cur_col, wrap)
314#endif
315
316#if AIC_DEBUG_REGISTERS
317ahc_reg_print_t ahc_saved_lun_print;
318#else
319#define ahc_saved_lun_print(regvalue, cur_col, wrap) \
320 ahc_print_register(NULL, 0, "SAVED_LUN", 0x3e, regvalue, cur_col, wrap)
321#endif
322
323#if AIC_DEBUG_REGISTERS
324ahc_reg_print_t ahc_lastphase_print; 107ahc_reg_print_t ahc_lastphase_print;
325#else 108#else
326#define ahc_lastphase_print(regvalue, cur_col, wrap) \ 109#define ahc_lastphase_print(regvalue, cur_col, wrap) \
@@ -328,153 +111,6 @@ ahc_reg_print_t ahc_lastphase_print;
328#endif 111#endif
329 112
330#if AIC_DEBUG_REGISTERS 113#if AIC_DEBUG_REGISTERS
331ahc_reg_print_t ahc_waiting_scbh_print;
332#else
333#define ahc_waiting_scbh_print(regvalue, cur_col, wrap) \
334 ahc_print_register(NULL, 0, "WAITING_SCBH", 0x40, regvalue, cur_col, wrap)
335#endif
336
337#if AIC_DEBUG_REGISTERS
338ahc_reg_print_t ahc_disconnected_scbh_print;
339#else
340#define ahc_disconnected_scbh_print(regvalue, cur_col, wrap) \
341 ahc_print_register(NULL, 0, "DISCONNECTED_SCBH", 0x41, regvalue, cur_col, wrap)
342#endif
343
344#if AIC_DEBUG_REGISTERS
345ahc_reg_print_t ahc_free_scbh_print;
346#else
347#define ahc_free_scbh_print(regvalue, cur_col, wrap) \
348 ahc_print_register(NULL, 0, "FREE_SCBH", 0x42, regvalue, cur_col, wrap)
349#endif
350
351#if AIC_DEBUG_REGISTERS
352ahc_reg_print_t ahc_complete_scbh_print;
353#else
354#define ahc_complete_scbh_print(regvalue, cur_col, wrap) \
355 ahc_print_register(NULL, 0, "COMPLETE_SCBH", 0x43, regvalue, cur_col, wrap)
356#endif
357
358#if AIC_DEBUG_REGISTERS
359ahc_reg_print_t ahc_hscb_addr_print;
360#else
361#define ahc_hscb_addr_print(regvalue, cur_col, wrap) \
362 ahc_print_register(NULL, 0, "HSCB_ADDR", 0x44, regvalue, cur_col, wrap)
363#endif
364
365#if AIC_DEBUG_REGISTERS
366ahc_reg_print_t ahc_shared_data_addr_print;
367#else
368#define ahc_shared_data_addr_print(regvalue, cur_col, wrap) \
369 ahc_print_register(NULL, 0, "SHARED_DATA_ADDR", 0x48, regvalue, cur_col, wrap)
370#endif
371
372#if AIC_DEBUG_REGISTERS
373ahc_reg_print_t ahc_kernel_qinpos_print;
374#else
375#define ahc_kernel_qinpos_print(regvalue, cur_col, wrap) \
376 ahc_print_register(NULL, 0, "KERNEL_QINPOS", 0x4c, regvalue, cur_col, wrap)
377#endif
378
379#if AIC_DEBUG_REGISTERS
380ahc_reg_print_t ahc_qinpos_print;
381#else
382#define ahc_qinpos_print(regvalue, cur_col, wrap) \
383 ahc_print_register(NULL, 0, "QINPOS", 0x4d, regvalue, cur_col, wrap)
384#endif
385
386#if AIC_DEBUG_REGISTERS
387ahc_reg_print_t ahc_qoutpos_print;
388#else
389#define ahc_qoutpos_print(regvalue, cur_col, wrap) \
390 ahc_print_register(NULL, 0, "QOUTPOS", 0x4e, regvalue, cur_col, wrap)
391#endif
392
393#if AIC_DEBUG_REGISTERS
394ahc_reg_print_t ahc_kernel_tqinpos_print;
395#else
396#define ahc_kernel_tqinpos_print(regvalue, cur_col, wrap) \
397 ahc_print_register(NULL, 0, "KERNEL_TQINPOS", 0x4f, regvalue, cur_col, wrap)
398#endif
399
400#if AIC_DEBUG_REGISTERS
401ahc_reg_print_t ahc_tqinpos_print;
402#else
403#define ahc_tqinpos_print(regvalue, cur_col, wrap) \
404 ahc_print_register(NULL, 0, "TQINPOS", 0x50, regvalue, cur_col, wrap)
405#endif
406
407#if AIC_DEBUG_REGISTERS
408ahc_reg_print_t ahc_arg_1_print;
409#else
410#define ahc_arg_1_print(regvalue, cur_col, wrap) \
411 ahc_print_register(NULL, 0, "ARG_1", 0x51, regvalue, cur_col, wrap)
412#endif
413
414#if AIC_DEBUG_REGISTERS
415ahc_reg_print_t ahc_arg_2_print;
416#else
417#define ahc_arg_2_print(regvalue, cur_col, wrap) \
418 ahc_print_register(NULL, 0, "ARG_2", 0x52, regvalue, cur_col, wrap)
419#endif
420
421#if AIC_DEBUG_REGISTERS
422ahc_reg_print_t ahc_last_msg_print;
423#else
424#define ahc_last_msg_print(regvalue, cur_col, wrap) \
425 ahc_print_register(NULL, 0, "LAST_MSG", 0x53, regvalue, cur_col, wrap)
426#endif
427
428#if AIC_DEBUG_REGISTERS
429ahc_reg_print_t ahc_scsiseq_template_print;
430#else
431#define ahc_scsiseq_template_print(regvalue, cur_col, wrap) \
432 ahc_print_register(NULL, 0, "SCSISEQ_TEMPLATE", 0x54, regvalue, cur_col, wrap)
433#endif
434
435#if AIC_DEBUG_REGISTERS
436ahc_reg_print_t ahc_ha_274_biosglobal_print;
437#else
438#define ahc_ha_274_biosglobal_print(regvalue, cur_col, wrap) \
439 ahc_print_register(NULL, 0, "HA_274_BIOSGLOBAL", 0x56, regvalue, cur_col, wrap)
440#endif
441
442#if AIC_DEBUG_REGISTERS
443ahc_reg_print_t ahc_seq_flags2_print;
444#else
445#define ahc_seq_flags2_print(regvalue, cur_col, wrap) \
446 ahc_print_register(NULL, 0, "SEQ_FLAGS2", 0x57, regvalue, cur_col, wrap)
447#endif
448
449#if AIC_DEBUG_REGISTERS
450ahc_reg_print_t ahc_scsiconf_print;
451#else
452#define ahc_scsiconf_print(regvalue, cur_col, wrap) \
453 ahc_print_register(NULL, 0, "SCSICONF", 0x5a, regvalue, cur_col, wrap)
454#endif
455
456#if AIC_DEBUG_REGISTERS
457ahc_reg_print_t ahc_intdef_print;
458#else
459#define ahc_intdef_print(regvalue, cur_col, wrap) \
460 ahc_print_register(NULL, 0, "INTDEF", 0x5c, regvalue, cur_col, wrap)
461#endif
462
463#if AIC_DEBUG_REGISTERS
464ahc_reg_print_t ahc_hostconf_print;
465#else
466#define ahc_hostconf_print(regvalue, cur_col, wrap) \
467 ahc_print_register(NULL, 0, "HOSTCONF", 0x5d, regvalue, cur_col, wrap)
468#endif
469
470#if AIC_DEBUG_REGISTERS
471ahc_reg_print_t ahc_ha_274_biosctrl_print;
472#else
473#define ahc_ha_274_biosctrl_print(regvalue, cur_col, wrap) \
474 ahc_print_register(NULL, 0, "HA_274_BIOSCTRL", 0x5f, regvalue, cur_col, wrap)
475#endif
476
477#if AIC_DEBUG_REGISTERS
478ahc_reg_print_t ahc_seqctl_print; 114ahc_reg_print_t ahc_seqctl_print;
479#else 115#else
480#define ahc_seqctl_print(regvalue, cur_col, wrap) \ 116#define ahc_seqctl_print(regvalue, cur_col, wrap) \
@@ -482,111 +118,6 @@ ahc_reg_print_t ahc_seqctl_print;
482#endif 118#endif
483 119
484#if AIC_DEBUG_REGISTERS 120#if AIC_DEBUG_REGISTERS
485ahc_reg_print_t ahc_seqram_print;
486#else
487#define ahc_seqram_print(regvalue, cur_col, wrap) \
488 ahc_print_register(NULL, 0, "SEQRAM", 0x61, regvalue, cur_col, wrap)
489#endif
490
491#if AIC_DEBUG_REGISTERS
492ahc_reg_print_t ahc_seqaddr0_print;
493#else
494#define ahc_seqaddr0_print(regvalue, cur_col, wrap) \
495 ahc_print_register(NULL, 0, "SEQADDR0", 0x62, regvalue, cur_col, wrap)
496#endif
497
498#if AIC_DEBUG_REGISTERS
499ahc_reg_print_t ahc_seqaddr1_print;
500#else
501#define ahc_seqaddr1_print(regvalue, cur_col, wrap) \
502 ahc_print_register(NULL, 0, "SEQADDR1", 0x63, regvalue, cur_col, wrap)
503#endif
504
505#if AIC_DEBUG_REGISTERS
506ahc_reg_print_t ahc_accum_print;
507#else
508#define ahc_accum_print(regvalue, cur_col, wrap) \
509 ahc_print_register(NULL, 0, "ACCUM", 0x64, regvalue, cur_col, wrap)
510#endif
511
512#if AIC_DEBUG_REGISTERS
513ahc_reg_print_t ahc_sindex_print;
514#else
515#define ahc_sindex_print(regvalue, cur_col, wrap) \
516 ahc_print_register(NULL, 0, "SINDEX", 0x65, regvalue, cur_col, wrap)
517#endif
518
519#if AIC_DEBUG_REGISTERS
520ahc_reg_print_t ahc_dindex_print;
521#else
522#define ahc_dindex_print(regvalue, cur_col, wrap) \
523 ahc_print_register(NULL, 0, "DINDEX", 0x66, regvalue, cur_col, wrap)
524#endif
525
526#if AIC_DEBUG_REGISTERS
527ahc_reg_print_t ahc_allones_print;
528#else
529#define ahc_allones_print(regvalue, cur_col, wrap) \
530 ahc_print_register(NULL, 0, "ALLONES", 0x69, regvalue, cur_col, wrap)
531#endif
532
533#if AIC_DEBUG_REGISTERS
534ahc_reg_print_t ahc_allzeros_print;
535#else
536#define ahc_allzeros_print(regvalue, cur_col, wrap) \
537 ahc_print_register(NULL, 0, "ALLZEROS", 0x6a, regvalue, cur_col, wrap)
538#endif
539
540#if AIC_DEBUG_REGISTERS
541ahc_reg_print_t ahc_none_print;
542#else
543#define ahc_none_print(regvalue, cur_col, wrap) \
544 ahc_print_register(NULL, 0, "NONE", 0x6a, regvalue, cur_col, wrap)
545#endif
546
547#if AIC_DEBUG_REGISTERS
548ahc_reg_print_t ahc_flags_print;
549#else
550#define ahc_flags_print(regvalue, cur_col, wrap) \
551 ahc_print_register(NULL, 0, "FLAGS", 0x6b, regvalue, cur_col, wrap)
552#endif
553
554#if AIC_DEBUG_REGISTERS
555ahc_reg_print_t ahc_sindir_print;
556#else
557#define ahc_sindir_print(regvalue, cur_col, wrap) \
558 ahc_print_register(NULL, 0, "SINDIR", 0x6c, regvalue, cur_col, wrap)
559#endif
560
561#if AIC_DEBUG_REGISTERS
562ahc_reg_print_t ahc_dindir_print;
563#else
564#define ahc_dindir_print(regvalue, cur_col, wrap) \
565 ahc_print_register(NULL, 0, "DINDIR", 0x6d, regvalue, cur_col, wrap)
566#endif
567
568#if AIC_DEBUG_REGISTERS
569ahc_reg_print_t ahc_function1_print;
570#else
571#define ahc_function1_print(regvalue, cur_col, wrap) \
572 ahc_print_register(NULL, 0, "FUNCTION1", 0x6e, regvalue, cur_col, wrap)
573#endif
574
575#if AIC_DEBUG_REGISTERS
576ahc_reg_print_t ahc_stack_print;
577#else
578#define ahc_stack_print(regvalue, cur_col, wrap) \
579 ahc_print_register(NULL, 0, "STACK", 0x6f, regvalue, cur_col, wrap)
580#endif
581
582#if AIC_DEBUG_REGISTERS
583ahc_reg_print_t ahc_targ_offset_print;
584#else
585#define ahc_targ_offset_print(regvalue, cur_col, wrap) \
586 ahc_print_register(NULL, 0, "TARG_OFFSET", 0x70, regvalue, cur_col, wrap)
587#endif
588
589#if AIC_DEBUG_REGISTERS
590ahc_reg_print_t ahc_sram_base_print; 121ahc_reg_print_t ahc_sram_base_print;
591#else 122#else
592#define ahc_sram_base_print(regvalue, cur_col, wrap) \ 123#define ahc_sram_base_print(regvalue, cur_col, wrap) \
@@ -594,97 +125,6 @@ ahc_reg_print_t ahc_sram_base_print;
594#endif 125#endif
595 126
596#if AIC_DEBUG_REGISTERS 127#if AIC_DEBUG_REGISTERS
597ahc_reg_print_t ahc_bctl_print;
598#else
599#define ahc_bctl_print(regvalue, cur_col, wrap) \
600 ahc_print_register(NULL, 0, "BCTL", 0x84, regvalue, cur_col, wrap)
601#endif
602
603#if AIC_DEBUG_REGISTERS
604ahc_reg_print_t ahc_dscommand0_print;
605#else
606#define ahc_dscommand0_print(regvalue, cur_col, wrap) \
607 ahc_print_register(NULL, 0, "DSCOMMAND0", 0x84, regvalue, cur_col, wrap)
608#endif
609
610#if AIC_DEBUG_REGISTERS
611ahc_reg_print_t ahc_bustime_print;
612#else
613#define ahc_bustime_print(regvalue, cur_col, wrap) \
614 ahc_print_register(NULL, 0, "BUSTIME", 0x85, regvalue, cur_col, wrap)
615#endif
616
617#if AIC_DEBUG_REGISTERS
618ahc_reg_print_t ahc_dscommand1_print;
619#else
620#define ahc_dscommand1_print(regvalue, cur_col, wrap) \
621 ahc_print_register(NULL, 0, "DSCOMMAND1", 0x85, regvalue, cur_col, wrap)
622#endif
623
624#if AIC_DEBUG_REGISTERS
625ahc_reg_print_t ahc_busspd_print;
626#else
627#define ahc_busspd_print(regvalue, cur_col, wrap) \
628 ahc_print_register(NULL, 0, "BUSSPD", 0x86, regvalue, cur_col, wrap)
629#endif
630
631#if AIC_DEBUG_REGISTERS
632ahc_reg_print_t ahc_hs_mailbox_print;
633#else
634#define ahc_hs_mailbox_print(regvalue, cur_col, wrap) \
635 ahc_print_register(NULL, 0, "HS_MAILBOX", 0x86, regvalue, cur_col, wrap)
636#endif
637
638#if AIC_DEBUG_REGISTERS
639ahc_reg_print_t ahc_dspcistatus_print;
640#else
641#define ahc_dspcistatus_print(regvalue, cur_col, wrap) \
642 ahc_print_register(NULL, 0, "DSPCISTATUS", 0x86, regvalue, cur_col, wrap)
643#endif
644
645#if AIC_DEBUG_REGISTERS
646ahc_reg_print_t ahc_hcntrl_print;
647#else
648#define ahc_hcntrl_print(regvalue, cur_col, wrap) \
649 ahc_print_register(NULL, 0, "HCNTRL", 0x87, regvalue, cur_col, wrap)
650#endif
651
652#if AIC_DEBUG_REGISTERS
653ahc_reg_print_t ahc_haddr_print;
654#else
655#define ahc_haddr_print(regvalue, cur_col, wrap) \
656 ahc_print_register(NULL, 0, "HADDR", 0x88, regvalue, cur_col, wrap)
657#endif
658
659#if AIC_DEBUG_REGISTERS
660ahc_reg_print_t ahc_hcnt_print;
661#else
662#define ahc_hcnt_print(regvalue, cur_col, wrap) \
663 ahc_print_register(NULL, 0, "HCNT", 0x8c, regvalue, cur_col, wrap)
664#endif
665
666#if AIC_DEBUG_REGISTERS
667ahc_reg_print_t ahc_scbptr_print;
668#else
669#define ahc_scbptr_print(regvalue, cur_col, wrap) \
670 ahc_print_register(NULL, 0, "SCBPTR", 0x90, regvalue, cur_col, wrap)
671#endif
672
673#if AIC_DEBUG_REGISTERS
674ahc_reg_print_t ahc_intstat_print;
675#else
676#define ahc_intstat_print(regvalue, cur_col, wrap) \
677 ahc_print_register(NULL, 0, "INTSTAT", 0x91, regvalue, cur_col, wrap)
678#endif
679
680#if AIC_DEBUG_REGISTERS
681ahc_reg_print_t ahc_clrint_print;
682#else
683#define ahc_clrint_print(regvalue, cur_col, wrap) \
684 ahc_print_register(NULL, 0, "CLRINT", 0x92, regvalue, cur_col, wrap)
685#endif
686
687#if AIC_DEBUG_REGISTERS
688ahc_reg_print_t ahc_error_print; 128ahc_reg_print_t ahc_error_print;
689#else 129#else
690#define ahc_error_print(regvalue, cur_col, wrap) \ 130#define ahc_error_print(regvalue, cur_col, wrap) \
@@ -706,69 +146,6 @@ ahc_reg_print_t ahc_dfstatus_print;
706#endif 146#endif
707 147
708#if AIC_DEBUG_REGISTERS 148#if AIC_DEBUG_REGISTERS
709ahc_reg_print_t ahc_dfwaddr_print;
710#else
711#define ahc_dfwaddr_print(regvalue, cur_col, wrap) \
712 ahc_print_register(NULL, 0, "DFWADDR", 0x95, regvalue, cur_col, wrap)
713#endif
714
715#if AIC_DEBUG_REGISTERS
716ahc_reg_print_t ahc_dfraddr_print;
717#else
718#define ahc_dfraddr_print(regvalue, cur_col, wrap) \
719 ahc_print_register(NULL, 0, "DFRADDR", 0x97, regvalue, cur_col, wrap)
720#endif
721
722#if AIC_DEBUG_REGISTERS
723ahc_reg_print_t ahc_dfdat_print;
724#else
725#define ahc_dfdat_print(regvalue, cur_col, wrap) \
726 ahc_print_register(NULL, 0, "DFDAT", 0x99, regvalue, cur_col, wrap)
727#endif
728
729#if AIC_DEBUG_REGISTERS
730ahc_reg_print_t ahc_scbcnt_print;
731#else
732#define ahc_scbcnt_print(regvalue, cur_col, wrap) \
733 ahc_print_register(NULL, 0, "SCBCNT", 0x9a, regvalue, cur_col, wrap)
734#endif
735
736#if AIC_DEBUG_REGISTERS
737ahc_reg_print_t ahc_qinfifo_print;
738#else
739#define ahc_qinfifo_print(regvalue, cur_col, wrap) \
740 ahc_print_register(NULL, 0, "QINFIFO", 0x9b, regvalue, cur_col, wrap)
741#endif
742
743#if AIC_DEBUG_REGISTERS
744ahc_reg_print_t ahc_qincnt_print;
745#else
746#define ahc_qincnt_print(regvalue, cur_col, wrap) \
747 ahc_print_register(NULL, 0, "QINCNT", 0x9c, regvalue, cur_col, wrap)
748#endif
749
750#if AIC_DEBUG_REGISTERS
751ahc_reg_print_t ahc_qoutfifo_print;
752#else
753#define ahc_qoutfifo_print(regvalue, cur_col, wrap) \
754 ahc_print_register(NULL, 0, "QOUTFIFO", 0x9d, regvalue, cur_col, wrap)
755#endif
756
757#if AIC_DEBUG_REGISTERS
758ahc_reg_print_t ahc_crccontrol1_print;
759#else
760#define ahc_crccontrol1_print(regvalue, cur_col, wrap) \
761 ahc_print_register(NULL, 0, "CRCCONTROL1", 0x9d, regvalue, cur_col, wrap)
762#endif
763
764#if AIC_DEBUG_REGISTERS
765ahc_reg_print_t ahc_qoutcnt_print;
766#else
767#define ahc_qoutcnt_print(regvalue, cur_col, wrap) \
768 ahc_print_register(NULL, 0, "QOUTCNT", 0x9e, regvalue, cur_col, wrap)
769#endif
770
771#if AIC_DEBUG_REGISTERS
772ahc_reg_print_t ahc_scsiphase_print; 149ahc_reg_print_t ahc_scsiphase_print;
773#else 150#else
774#define ahc_scsiphase_print(regvalue, cur_col, wrap) \ 151#define ahc_scsiphase_print(regvalue, cur_col, wrap) \
@@ -776,13 +153,6 @@ ahc_reg_print_t ahc_scsiphase_print;
776#endif 153#endif
777 154
778#if AIC_DEBUG_REGISTERS 155#if AIC_DEBUG_REGISTERS
779ahc_reg_print_t ahc_sfunct_print;
780#else
781#define ahc_sfunct_print(regvalue, cur_col, wrap) \
782 ahc_print_register(NULL, 0, "SFUNCT", 0x9f, regvalue, cur_col, wrap)
783#endif
784
785#if AIC_DEBUG_REGISTERS
786ahc_reg_print_t ahc_scb_base_print; 156ahc_reg_print_t ahc_scb_base_print;
787#else 157#else
788#define ahc_scb_base_print(regvalue, cur_col, wrap) \ 158#define ahc_scb_base_print(regvalue, cur_col, wrap) \
@@ -790,69 +160,6 @@ ahc_reg_print_t ahc_scb_base_print;
790#endif 160#endif
791 161
792#if AIC_DEBUG_REGISTERS 162#if AIC_DEBUG_REGISTERS
793ahc_reg_print_t ahc_scb_cdb_ptr_print;
794#else
795#define ahc_scb_cdb_ptr_print(regvalue, cur_col, wrap) \
796 ahc_print_register(NULL, 0, "SCB_CDB_PTR", 0xa0, regvalue, cur_col, wrap)
797#endif
798
799#if AIC_DEBUG_REGISTERS
800ahc_reg_print_t ahc_scb_residual_sgptr_print;
801#else
802#define ahc_scb_residual_sgptr_print(regvalue, cur_col, wrap) \
803 ahc_print_register(NULL, 0, "SCB_RESIDUAL_SGPTR", 0xa4, regvalue, cur_col, wrap)
804#endif
805
806#if AIC_DEBUG_REGISTERS
807ahc_reg_print_t ahc_scb_scsi_status_print;
808#else
809#define ahc_scb_scsi_status_print(regvalue, cur_col, wrap) \
810 ahc_print_register(NULL, 0, "SCB_SCSI_STATUS", 0xa8, regvalue, cur_col, wrap)
811#endif
812
813#if AIC_DEBUG_REGISTERS
814ahc_reg_print_t ahc_scb_target_phases_print;
815#else
816#define ahc_scb_target_phases_print(regvalue, cur_col, wrap) \
817 ahc_print_register(NULL, 0, "SCB_TARGET_PHASES", 0xa9, regvalue, cur_col, wrap)
818#endif
819
820#if AIC_DEBUG_REGISTERS
821ahc_reg_print_t ahc_scb_target_data_dir_print;
822#else
823#define ahc_scb_target_data_dir_print(regvalue, cur_col, wrap) \
824 ahc_print_register(NULL, 0, "SCB_TARGET_DATA_DIR", 0xaa, regvalue, cur_col, wrap)
825#endif
826
827#if AIC_DEBUG_REGISTERS
828ahc_reg_print_t ahc_scb_target_itag_print;
829#else
830#define ahc_scb_target_itag_print(regvalue, cur_col, wrap) \
831 ahc_print_register(NULL, 0, "SCB_TARGET_ITAG", 0xab, regvalue, cur_col, wrap)
832#endif
833
834#if AIC_DEBUG_REGISTERS
835ahc_reg_print_t ahc_scb_dataptr_print;
836#else
837#define ahc_scb_dataptr_print(regvalue, cur_col, wrap) \
838 ahc_print_register(NULL, 0, "SCB_DATAPTR", 0xac, regvalue, cur_col, wrap)
839#endif
840
841#if AIC_DEBUG_REGISTERS
842ahc_reg_print_t ahc_scb_datacnt_print;
843#else
844#define ahc_scb_datacnt_print(regvalue, cur_col, wrap) \
845 ahc_print_register(NULL, 0, "SCB_DATACNT", 0xb0, regvalue, cur_col, wrap)
846#endif
847
848#if AIC_DEBUG_REGISTERS
849ahc_reg_print_t ahc_scb_sgptr_print;
850#else
851#define ahc_scb_sgptr_print(regvalue, cur_col, wrap) \
852 ahc_print_register(NULL, 0, "SCB_SGPTR", 0xb4, regvalue, cur_col, wrap)
853#endif
854
855#if AIC_DEBUG_REGISTERS
856ahc_reg_print_t ahc_scb_control_print; 163ahc_reg_print_t ahc_scb_control_print;
857#else 164#else
858#define ahc_scb_control_print(regvalue, cur_col, wrap) \ 165#define ahc_scb_control_print(regvalue, cur_col, wrap) \
@@ -880,188 +187,6 @@ ahc_reg_print_t ahc_scb_tag_print;
880 ahc_print_register(NULL, 0, "SCB_TAG", 0xbb, regvalue, cur_col, wrap) 187 ahc_print_register(NULL, 0, "SCB_TAG", 0xbb, regvalue, cur_col, wrap)
881#endif 188#endif
882 189
883#if AIC_DEBUG_REGISTERS
884ahc_reg_print_t ahc_scb_cdb_len_print;
885#else
886#define ahc_scb_cdb_len_print(regvalue, cur_col, wrap) \
887 ahc_print_register(NULL, 0, "SCB_CDB_LEN", 0xbc, regvalue, cur_col, wrap)
888#endif
889
890#if AIC_DEBUG_REGISTERS
891ahc_reg_print_t ahc_scb_scsirate_print;
892#else
893#define ahc_scb_scsirate_print(regvalue, cur_col, wrap) \
894 ahc_print_register(NULL, 0, "SCB_SCSIRATE", 0xbd, regvalue, cur_col, wrap)
895#endif
896
897#if AIC_DEBUG_REGISTERS
898ahc_reg_print_t ahc_scb_scsioffset_print;
899#else
900#define ahc_scb_scsioffset_print(regvalue, cur_col, wrap) \
901 ahc_print_register(NULL, 0, "SCB_SCSIOFFSET", 0xbe, regvalue, cur_col, wrap)
902#endif
903
904#if AIC_DEBUG_REGISTERS
905ahc_reg_print_t ahc_scb_next_print;
906#else
907#define ahc_scb_next_print(regvalue, cur_col, wrap) \
908 ahc_print_register(NULL, 0, "SCB_NEXT", 0xbf, regvalue, cur_col, wrap)
909#endif
910
911#if AIC_DEBUG_REGISTERS
912ahc_reg_print_t ahc_scb_64_spare_print;
913#else
914#define ahc_scb_64_spare_print(regvalue, cur_col, wrap) \
915 ahc_print_register(NULL, 0, "SCB_64_SPARE", 0xc0, regvalue, cur_col, wrap)
916#endif
917
918#if AIC_DEBUG_REGISTERS
919ahc_reg_print_t ahc_seectl_2840_print;
920#else
921#define ahc_seectl_2840_print(regvalue, cur_col, wrap) \
922 ahc_print_register(NULL, 0, "SEECTL_2840", 0xc0, regvalue, cur_col, wrap)
923#endif
924
925#if AIC_DEBUG_REGISTERS
926ahc_reg_print_t ahc_status_2840_print;
927#else
928#define ahc_status_2840_print(regvalue, cur_col, wrap) \
929 ahc_print_register(NULL, 0, "STATUS_2840", 0xc1, regvalue, cur_col, wrap)
930#endif
931
932#if AIC_DEBUG_REGISTERS
933ahc_reg_print_t ahc_scb_64_btt_print;
934#else
935#define ahc_scb_64_btt_print(regvalue, cur_col, wrap) \
936 ahc_print_register(NULL, 0, "SCB_64_BTT", 0xd0, regvalue, cur_col, wrap)
937#endif
938
939#if AIC_DEBUG_REGISTERS
940ahc_reg_print_t ahc_cchaddr_print;
941#else
942#define ahc_cchaddr_print(regvalue, cur_col, wrap) \
943 ahc_print_register(NULL, 0, "CCHADDR", 0xe0, regvalue, cur_col, wrap)
944#endif
945
946#if AIC_DEBUG_REGISTERS
947ahc_reg_print_t ahc_cchcnt_print;
948#else
949#define ahc_cchcnt_print(regvalue, cur_col, wrap) \
950 ahc_print_register(NULL, 0, "CCHCNT", 0xe8, regvalue, cur_col, wrap)
951#endif
952
953#if AIC_DEBUG_REGISTERS
954ahc_reg_print_t ahc_ccsgram_print;
955#else
956#define ahc_ccsgram_print(regvalue, cur_col, wrap) \
957 ahc_print_register(NULL, 0, "CCSGRAM", 0xe9, regvalue, cur_col, wrap)
958#endif
959
960#if AIC_DEBUG_REGISTERS
961ahc_reg_print_t ahc_ccsgaddr_print;
962#else
963#define ahc_ccsgaddr_print(regvalue, cur_col, wrap) \
964 ahc_print_register(NULL, 0, "CCSGADDR", 0xea, regvalue, cur_col, wrap)
965#endif
966
967#if AIC_DEBUG_REGISTERS
968ahc_reg_print_t ahc_ccsgctl_print;
969#else
970#define ahc_ccsgctl_print(regvalue, cur_col, wrap) \
971 ahc_print_register(NULL, 0, "CCSGCTL", 0xeb, regvalue, cur_col, wrap)
972#endif
973
974#if AIC_DEBUG_REGISTERS
975ahc_reg_print_t ahc_ccscbram_print;
976#else
977#define ahc_ccscbram_print(regvalue, cur_col, wrap) \
978 ahc_print_register(NULL, 0, "CCSCBRAM", 0xec, regvalue, cur_col, wrap)
979#endif
980
981#if AIC_DEBUG_REGISTERS
982ahc_reg_print_t ahc_ccscbaddr_print;
983#else
984#define ahc_ccscbaddr_print(regvalue, cur_col, wrap) \
985 ahc_print_register(NULL, 0, "CCSCBADDR", 0xed, regvalue, cur_col, wrap)
986#endif
987
988#if AIC_DEBUG_REGISTERS
989ahc_reg_print_t ahc_ccscbctl_print;
990#else
991#define ahc_ccscbctl_print(regvalue, cur_col, wrap) \
992 ahc_print_register(NULL, 0, "CCSCBCTL", 0xee, regvalue, cur_col, wrap)
993#endif
994
995#if AIC_DEBUG_REGISTERS
996ahc_reg_print_t ahc_ccscbcnt_print;
997#else
998#define ahc_ccscbcnt_print(regvalue, cur_col, wrap) \
999 ahc_print_register(NULL, 0, "CCSCBCNT", 0xef, regvalue, cur_col, wrap)
1000#endif
1001
1002#if AIC_DEBUG_REGISTERS
1003ahc_reg_print_t ahc_scbbaddr_print;
1004#else
1005#define ahc_scbbaddr_print(regvalue, cur_col, wrap) \
1006 ahc_print_register(NULL, 0, "SCBBADDR", 0xf0, regvalue, cur_col, wrap)
1007#endif
1008
1009#if AIC_DEBUG_REGISTERS
1010ahc_reg_print_t ahc_ccscbptr_print;
1011#else
1012#define ahc_ccscbptr_print(regvalue, cur_col, wrap) \
1013 ahc_print_register(NULL, 0, "CCSCBPTR", 0xf1, regvalue, cur_col, wrap)
1014#endif
1015
1016#if AIC_DEBUG_REGISTERS
1017ahc_reg_print_t ahc_hnscb_qoff_print;
1018#else
1019#define ahc_hnscb_qoff_print(regvalue, cur_col, wrap) \
1020 ahc_print_register(NULL, 0, "HNSCB_QOFF", 0xf4, regvalue, cur_col, wrap)
1021#endif
1022
1023#if AIC_DEBUG_REGISTERS
1024ahc_reg_print_t ahc_snscb_qoff_print;
1025#else
1026#define ahc_snscb_qoff_print(regvalue, cur_col, wrap) \
1027 ahc_print_register(NULL, 0, "SNSCB_QOFF", 0xf6, regvalue, cur_col, wrap)
1028#endif
1029
1030#if AIC_DEBUG_REGISTERS
1031ahc_reg_print_t ahc_sdscb_qoff_print;
1032#else
1033#define ahc_sdscb_qoff_print(regvalue, cur_col, wrap) \
1034 ahc_print_register(NULL, 0, "SDSCB_QOFF", 0xf8, regvalue, cur_col, wrap)
1035#endif
1036
1037#if AIC_DEBUG_REGISTERS
1038ahc_reg_print_t ahc_qoff_ctlsta_print;
1039#else
1040#define ahc_qoff_ctlsta_print(regvalue, cur_col, wrap) \
1041 ahc_print_register(NULL, 0, "QOFF_CTLSTA", 0xfa, regvalue, cur_col, wrap)
1042#endif
1043
1044#if AIC_DEBUG_REGISTERS
1045ahc_reg_print_t ahc_dff_thrsh_print;
1046#else
1047#define ahc_dff_thrsh_print(regvalue, cur_col, wrap) \
1048 ahc_print_register(NULL, 0, "DFF_THRSH", 0xfb, regvalue, cur_col, wrap)
1049#endif
1050
1051#if AIC_DEBUG_REGISTERS
1052ahc_reg_print_t ahc_sg_cache_shadow_print;
1053#else
1054#define ahc_sg_cache_shadow_print(regvalue, cur_col, wrap) \
1055 ahc_print_register(NULL, 0, "SG_CACHE_SHADOW", 0xfc, regvalue, cur_col, wrap)
1056#endif
1057
1058#if AIC_DEBUG_REGISTERS
1059ahc_reg_print_t ahc_sg_cache_pre_print;
1060#else
1061#define ahc_sg_cache_pre_print(regvalue, cur_col, wrap) \
1062 ahc_print_register(NULL, 0, "SG_CACHE_PRE", 0xfc, regvalue, cur_col, wrap)
1063#endif
1064
1065 190
1066#define SCSISEQ 0x00 191#define SCSISEQ 0x00
1067#define TEMODE 0x80 192#define TEMODE 0x80
diff --git a/drivers/scsi/aic7xxx/aic7xxx_reg_print.c_shipped b/drivers/scsi/aic7xxx/aic7xxx_reg_print.c_shipped
index 309a562b009e..9f9b88047d0c 100644
--- a/drivers/scsi/aic7xxx/aic7xxx_reg_print.c_shipped
+++ b/drivers/scsi/aic7xxx/aic7xxx_reg_print.c_shipped
@@ -43,48 +43,6 @@ ahc_sxfrctl0_print(u_int regvalue, u_int *cur_col, u_int wrap)
43 0x01, regvalue, cur_col, wrap)); 43 0x01, regvalue, cur_col, wrap));
44} 44}
45 45
46static const ahc_reg_parse_entry_t SXFRCTL1_parse_table[] = {
47 { "STPWEN", 0x01, 0x01 },
48 { "ACTNEGEN", 0x02, 0x02 },
49 { "ENSTIMER", 0x04, 0x04 },
50 { "ENSPCHK", 0x20, 0x20 },
51 { "SWRAPEN", 0x40, 0x40 },
52 { "BITBUCKET", 0x80, 0x80 },
53 { "STIMESEL", 0x18, 0x18 }
54};
55
56int
57ahc_sxfrctl1_print(u_int regvalue, u_int *cur_col, u_int wrap)
58{
59 return (ahc_print_register(SXFRCTL1_parse_table, 7, "SXFRCTL1",
60 0x02, regvalue, cur_col, wrap));
61}
62
63static const ahc_reg_parse_entry_t SCSISIGO_parse_table[] = {
64 { "ACKO", 0x01, 0x01 },
65 { "REQO", 0x02, 0x02 },
66 { "BSYO", 0x04, 0x04 },
67 { "SELO", 0x08, 0x08 },
68 { "ATNO", 0x10, 0x10 },
69 { "MSGO", 0x20, 0x20 },
70 { "IOO", 0x40, 0x40 },
71 { "CDO", 0x80, 0x80 },
72 { "P_DATAOUT", 0x00, 0x00 },
73 { "P_DATAIN", 0x40, 0x40 },
74 { "P_COMMAND", 0x80, 0x80 },
75 { "P_MESGOUT", 0xa0, 0xa0 },
76 { "P_STATUS", 0xc0, 0xc0 },
77 { "PHASE_MASK", 0xe0, 0xe0 },
78 { "P_MESGIN", 0xe0, 0xe0 }
79};
80
81int
82ahc_scsisigo_print(u_int regvalue, u_int *cur_col, u_int wrap)
83{
84 return (ahc_print_register(SCSISIGO_parse_table, 15, "SCSISIGO",
85 0x03, regvalue, cur_col, wrap));
86}
87
88static const ahc_reg_parse_entry_t SCSISIGI_parse_table[] = { 46static const ahc_reg_parse_entry_t SCSISIGI_parse_table[] = {
89 { "ACKI", 0x01, 0x01 }, 47 { "ACKI", 0x01, 0x01 },
90 { "REQI", 0x02, 0x02 }, 48 { "REQI", 0x02, 0x02 },
@@ -128,77 +86,6 @@ ahc_scsirate_print(u_int regvalue, u_int *cur_col, u_int wrap)
128 0x04, regvalue, cur_col, wrap)); 86 0x04, regvalue, cur_col, wrap));
129} 87}
130 88
131static const ahc_reg_parse_entry_t SCSIID_parse_table[] = {
132 { "TWIN_CHNLB", 0x80, 0x80 },
133 { "OID", 0x0f, 0x0f },
134 { "TWIN_TID", 0x70, 0x70 },
135 { "SOFS_ULTRA2", 0x7f, 0x7f },
136 { "TID", 0xf0, 0xf0 }
137};
138
139int
140ahc_scsiid_print(u_int regvalue, u_int *cur_col, u_int wrap)
141{
142 return (ahc_print_register(SCSIID_parse_table, 5, "SCSIID",
143 0x05, regvalue, cur_col, wrap));
144}
145
146int
147ahc_scsidatl_print(u_int regvalue, u_int *cur_col, u_int wrap)
148{
149 return (ahc_print_register(NULL, 0, "SCSIDATL",
150 0x06, regvalue, cur_col, wrap));
151}
152
153int
154ahc_stcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
155{
156 return (ahc_print_register(NULL, 0, "STCNT",
157 0x08, regvalue, cur_col, wrap));
158}
159
160static const ahc_reg_parse_entry_t OPTIONMODE_parse_table[] = {
161 { "DIS_MSGIN_DUALEDGE", 0x01, 0x01 },
162 { "AUTO_MSGOUT_DE", 0x02, 0x02 },
163 { "SCSIDATL_IMGEN", 0x04, 0x04 },
164 { "EXPPHASEDIS", 0x08, 0x08 },
165 { "BUSFREEREV", 0x10, 0x10 },
166 { "ATNMGMNTEN", 0x20, 0x20 },
167 { "AUTOACKEN", 0x40, 0x40 },
168 { "AUTORATEEN", 0x80, 0x80 },
169 { "OPTIONMODE_DEFAULTS",0x03, 0x03 }
170};
171
172int
173ahc_optionmode_print(u_int regvalue, u_int *cur_col, u_int wrap)
174{
175 return (ahc_print_register(OPTIONMODE_parse_table, 9, "OPTIONMODE",
176 0x08, regvalue, cur_col, wrap));
177}
178
179int
180ahc_targcrccnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
181{
182 return (ahc_print_register(NULL, 0, "TARGCRCCNT",
183 0x0a, regvalue, cur_col, wrap));
184}
185
186static const ahc_reg_parse_entry_t CLRSINT0_parse_table[] = {
187 { "CLRSPIORDY", 0x02, 0x02 },
188 { "CLRSWRAP", 0x08, 0x08 },
189 { "CLRIOERR", 0x08, 0x08 },
190 { "CLRSELINGO", 0x10, 0x10 },
191 { "CLRSELDI", 0x20, 0x20 },
192 { "CLRSELDO", 0x40, 0x40 }
193};
194
195int
196ahc_clrsint0_print(u_int regvalue, u_int *cur_col, u_int wrap)
197{
198 return (ahc_print_register(CLRSINT0_parse_table, 6, "CLRSINT0",
199 0x0b, regvalue, cur_col, wrap));
200}
201
202static const ahc_reg_parse_entry_t SSTAT0_parse_table[] = { 89static const ahc_reg_parse_entry_t SSTAT0_parse_table[] = {
203 { "DMADONE", 0x01, 0x01 }, 90 { "DMADONE", 0x01, 0x01 },
204 { "SPIORDY", 0x02, 0x02 }, 91 { "SPIORDY", 0x02, 0x02 },
@@ -218,23 +105,6 @@ ahc_sstat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
218 0x0b, regvalue, cur_col, wrap)); 105 0x0b, regvalue, cur_col, wrap));
219} 106}
220 107
221static const ahc_reg_parse_entry_t CLRSINT1_parse_table[] = {
222 { "CLRREQINIT", 0x01, 0x01 },
223 { "CLRPHASECHG", 0x02, 0x02 },
224 { "CLRSCSIPERR", 0x04, 0x04 },
225 { "CLRBUSFREE", 0x08, 0x08 },
226 { "CLRSCSIRSTI", 0x20, 0x20 },
227 { "CLRATNO", 0x40, 0x40 },
228 { "CLRSELTIMEO", 0x80, 0x80 }
229};
230
231int
232ahc_clrsint1_print(u_int regvalue, u_int *cur_col, u_int wrap)
233{
234 return (ahc_print_register(CLRSINT1_parse_table, 7, "CLRSINT1",
235 0x0c, regvalue, cur_col, wrap));
236}
237
238static const ahc_reg_parse_entry_t SSTAT1_parse_table[] = { 108static const ahc_reg_parse_entry_t SSTAT1_parse_table[] = {
239 { "REQINIT", 0x01, 0x01 }, 109 { "REQINIT", 0x01, 0x01 },
240 { "PHASECHG", 0x02, 0x02 }, 110 { "PHASECHG", 0x02, 0x02 },
@@ -284,18 +154,6 @@ ahc_sstat3_print(u_int regvalue, u_int *cur_col, u_int wrap)
284 0x0e, regvalue, cur_col, wrap)); 154 0x0e, regvalue, cur_col, wrap));
285} 155}
286 156
287static const ahc_reg_parse_entry_t SCSIID_ULTRA2_parse_table[] = {
288 { "OID", 0x0f, 0x0f },
289 { "TID", 0xf0, 0xf0 }
290};
291
292int
293ahc_scsiid_ultra2_print(u_int regvalue, u_int *cur_col, u_int wrap)
294{
295 return (ahc_print_register(SCSIID_ULTRA2_parse_table, 2, "SCSIID_ULTRA2",
296 0x0f, regvalue, cur_col, wrap));
297}
298
299static const ahc_reg_parse_entry_t SIMODE0_parse_table[] = { 157static const ahc_reg_parse_entry_t SIMODE0_parse_table[] = {
300 { "ENDMADONE", 0x01, 0x01 }, 158 { "ENDMADONE", 0x01, 0x01 },
301 { "ENSPIORDY", 0x02, 0x02 }, 159 { "ENSPIORDY", 0x02, 0x02 },
@@ -339,107 +197,6 @@ ahc_scsibusl_print(u_int regvalue, u_int *cur_col, u_int wrap)
339 0x12, regvalue, cur_col, wrap)); 197 0x12, regvalue, cur_col, wrap));
340} 198}
341 199
342int
343ahc_shaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
344{
345 return (ahc_print_register(NULL, 0, "SHADDR",
346 0x14, regvalue, cur_col, wrap));
347}
348
349static const ahc_reg_parse_entry_t SELTIMER_parse_table[] = {
350 { "STAGE1", 0x01, 0x01 },
351 { "STAGE2", 0x02, 0x02 },
352 { "STAGE3", 0x04, 0x04 },
353 { "STAGE4", 0x08, 0x08 },
354 { "STAGE5", 0x10, 0x10 },
355 { "STAGE6", 0x20, 0x20 }
356};
357
358int
359ahc_seltimer_print(u_int regvalue, u_int *cur_col, u_int wrap)
360{
361 return (ahc_print_register(SELTIMER_parse_table, 6, "SELTIMER",
362 0x18, regvalue, cur_col, wrap));
363}
364
365static const ahc_reg_parse_entry_t SELID_parse_table[] = {
366 { "ONEBIT", 0x08, 0x08 },
367 { "SELID_MASK", 0xf0, 0xf0 }
368};
369
370int
371ahc_selid_print(u_int regvalue, u_int *cur_col, u_int wrap)
372{
373 return (ahc_print_register(SELID_parse_table, 2, "SELID",
374 0x19, regvalue, cur_col, wrap));
375}
376
377int
378ahc_targid_print(u_int regvalue, u_int *cur_col, u_int wrap)
379{
380 return (ahc_print_register(NULL, 0, "TARGID",
381 0x1b, regvalue, cur_col, wrap));
382}
383
384static const ahc_reg_parse_entry_t SPIOCAP_parse_table[] = {
385 { "SSPIOCPS", 0x01, 0x01 },
386 { "ROM", 0x02, 0x02 },
387 { "EEPROM", 0x04, 0x04 },
388 { "SEEPROM", 0x08, 0x08 },
389 { "EXT_BRDCTL", 0x10, 0x10 },
390 { "SOFTCMDEN", 0x20, 0x20 },
391 { "SOFT0", 0x40, 0x40 },
392 { "SOFT1", 0x80, 0x80 }
393};
394
395int
396ahc_spiocap_print(u_int regvalue, u_int *cur_col, u_int wrap)
397{
398 return (ahc_print_register(SPIOCAP_parse_table, 8, "SPIOCAP",
399 0x1b, regvalue, cur_col, wrap));
400}
401
402static const ahc_reg_parse_entry_t BRDCTL_parse_table[] = {
403 { "BRDCTL0", 0x01, 0x01 },
404 { "BRDSTB_ULTRA2", 0x01, 0x01 },
405 { "BRDCTL1", 0x02, 0x02 },
406 { "BRDRW_ULTRA2", 0x02, 0x02 },
407 { "BRDRW", 0x04, 0x04 },
408 { "BRDDAT2", 0x04, 0x04 },
409 { "BRDCS", 0x08, 0x08 },
410 { "BRDDAT3", 0x08, 0x08 },
411 { "BRDSTB", 0x10, 0x10 },
412 { "BRDDAT4", 0x10, 0x10 },
413 { "BRDDAT5", 0x20, 0x20 },
414 { "BRDDAT6", 0x40, 0x40 },
415 { "BRDDAT7", 0x80, 0x80 }
416};
417
418int
419ahc_brdctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
420{
421 return (ahc_print_register(BRDCTL_parse_table, 13, "BRDCTL",
422 0x1d, regvalue, cur_col, wrap));
423}
424
425static const ahc_reg_parse_entry_t SEECTL_parse_table[] = {
426 { "SEEDI", 0x01, 0x01 },
427 { "SEEDO", 0x02, 0x02 },
428 { "SEECK", 0x04, 0x04 },
429 { "SEECS", 0x08, 0x08 },
430 { "SEERDY", 0x10, 0x10 },
431 { "SEEMS", 0x20, 0x20 },
432 { "EXTARBREQ", 0x40, 0x40 },
433 { "EXTARBACK", 0x80, 0x80 }
434};
435
436int
437ahc_seectl_print(u_int regvalue, u_int *cur_col, u_int wrap)
438{
439 return (ahc_print_register(SEECTL_parse_table, 8, "SEECTL",
440 0x1e, regvalue, cur_col, wrap));
441}
442
443static const ahc_reg_parse_entry_t SBLKCTL_parse_table[] = { 200static const ahc_reg_parse_entry_t SBLKCTL_parse_table[] = {
444 { "XCVR", 0x01, 0x01 }, 201 { "XCVR", 0x01, 0x01 },
445 { "SELWIDE", 0x02, 0x02 }, 202 { "SELWIDE", 0x02, 0x02 },
@@ -458,68 +215,6 @@ ahc_sblkctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
458 0x1f, regvalue, cur_col, wrap)); 215 0x1f, regvalue, cur_col, wrap));
459} 216}
460 217
461int
462ahc_busy_targets_print(u_int regvalue, u_int *cur_col, u_int wrap)
463{
464 return (ahc_print_register(NULL, 0, "BUSY_TARGETS",
465 0x20, regvalue, cur_col, wrap));
466}
467
468int
469ahc_ultra_enb_print(u_int regvalue, u_int *cur_col, u_int wrap)
470{
471 return (ahc_print_register(NULL, 0, "ULTRA_ENB",
472 0x30, regvalue, cur_col, wrap));
473}
474
475int
476ahc_disc_dsb_print(u_int regvalue, u_int *cur_col, u_int wrap)
477{
478 return (ahc_print_register(NULL, 0, "DISC_DSB",
479 0x32, regvalue, cur_col, wrap));
480}
481
482int
483ahc_mwi_residual_print(u_int regvalue, u_int *cur_col, u_int wrap)
484{
485 return (ahc_print_register(NULL, 0, "MWI_RESIDUAL",
486 0x38, regvalue, cur_col, wrap));
487}
488
489int
490ahc_next_queued_scb_print(u_int regvalue, u_int *cur_col, u_int wrap)
491{
492 return (ahc_print_register(NULL, 0, "NEXT_QUEUED_SCB",
493 0x39, regvalue, cur_col, wrap));
494}
495
496int
497ahc_msg_out_print(u_int regvalue, u_int *cur_col, u_int wrap)
498{
499 return (ahc_print_register(NULL, 0, "MSG_OUT",
500 0x3a, regvalue, cur_col, wrap));
501}
502
503static const ahc_reg_parse_entry_t DMAPARAMS_parse_table[] = {
504 { "FIFORESET", 0x01, 0x01 },
505 { "FIFOFLUSH", 0x02, 0x02 },
506 { "DIRECTION", 0x04, 0x04 },
507 { "HDMAEN", 0x08, 0x08 },
508 { "HDMAENACK", 0x08, 0x08 },
509 { "SDMAEN", 0x10, 0x10 },
510 { "SDMAENACK", 0x10, 0x10 },
511 { "SCSIEN", 0x20, 0x20 },
512 { "WIDEODD", 0x40, 0x40 },
513 { "PRELOADEN", 0x80, 0x80 }
514};
515
516int
517ahc_dmaparams_print(u_int regvalue, u_int *cur_col, u_int wrap)
518{
519 return (ahc_print_register(DMAPARAMS_parse_table, 10, "DMAPARAMS",
520 0x3b, regvalue, cur_col, wrap));
521}
522
523static const ahc_reg_parse_entry_t SEQ_FLAGS_parse_table[] = { 218static const ahc_reg_parse_entry_t SEQ_FLAGS_parse_table[] = {
524 { "NO_DISCONNECT", 0x01, 0x01 }, 219 { "NO_DISCONNECT", 0x01, 0x01 },
525 { "SPHASE_PENDING", 0x02, 0x02 }, 220 { "SPHASE_PENDING", 0x02, 0x02 },
@@ -539,20 +234,6 @@ ahc_seq_flags_print(u_int regvalue, u_int *cur_col, u_int wrap)
539 0x3c, regvalue, cur_col, wrap)); 234 0x3c, regvalue, cur_col, wrap));
540} 235}
541 236
542int
543ahc_saved_scsiid_print(u_int regvalue, u_int *cur_col, u_int wrap)
544{
545 return (ahc_print_register(NULL, 0, "SAVED_SCSIID",
546 0x3d, regvalue, cur_col, wrap));
547}
548
549int
550ahc_saved_lun_print(u_int regvalue, u_int *cur_col, u_int wrap)
551{
552 return (ahc_print_register(NULL, 0, "SAVED_LUN",
553 0x3e, regvalue, cur_col, wrap));
554}
555
556static const ahc_reg_parse_entry_t LASTPHASE_parse_table[] = { 237static const ahc_reg_parse_entry_t LASTPHASE_parse_table[] = {
557 { "MSGI", 0x20, 0x20 }, 238 { "MSGI", 0x20, 0x20 },
558 { "IOI", 0x40, 0x40 }, 239 { "IOI", 0x40, 0x40 },
@@ -574,193 +255,6 @@ ahc_lastphase_print(u_int regvalue, u_int *cur_col, u_int wrap)
574 0x3f, regvalue, cur_col, wrap)); 255 0x3f, regvalue, cur_col, wrap));
575} 256}
576 257
577int
578ahc_waiting_scbh_print(u_int regvalue, u_int *cur_col, u_int wrap)
579{
580 return (ahc_print_register(NULL, 0, "WAITING_SCBH",
581 0x40, regvalue, cur_col, wrap));
582}
583
584int
585ahc_disconnected_scbh_print(u_int regvalue, u_int *cur_col, u_int wrap)
586{
587 return (ahc_print_register(NULL, 0, "DISCONNECTED_SCBH",
588 0x41, regvalue, cur_col, wrap));
589}
590
591int
592ahc_free_scbh_print(u_int regvalue, u_int *cur_col, u_int wrap)
593{
594 return (ahc_print_register(NULL, 0, "FREE_SCBH",
595 0x42, regvalue, cur_col, wrap));
596}
597
598int
599ahc_hscb_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
600{
601 return (ahc_print_register(NULL, 0, "HSCB_ADDR",
602 0x44, regvalue, cur_col, wrap));
603}
604
605int
606ahc_shared_data_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
607{
608 return (ahc_print_register(NULL, 0, "SHARED_DATA_ADDR",
609 0x48, regvalue, cur_col, wrap));
610}
611
612int
613ahc_kernel_qinpos_print(u_int regvalue, u_int *cur_col, u_int wrap)
614{
615 return (ahc_print_register(NULL, 0, "KERNEL_QINPOS",
616 0x4c, regvalue, cur_col, wrap));
617}
618
619int
620ahc_qinpos_print(u_int regvalue, u_int *cur_col, u_int wrap)
621{
622 return (ahc_print_register(NULL, 0, "QINPOS",
623 0x4d, regvalue, cur_col, wrap));
624}
625
626int
627ahc_qoutpos_print(u_int regvalue, u_int *cur_col, u_int wrap)
628{
629 return (ahc_print_register(NULL, 0, "QOUTPOS",
630 0x4e, regvalue, cur_col, wrap));
631}
632
633int
634ahc_kernel_tqinpos_print(u_int regvalue, u_int *cur_col, u_int wrap)
635{
636 return (ahc_print_register(NULL, 0, "KERNEL_TQINPOS",
637 0x4f, regvalue, cur_col, wrap));
638}
639
640int
641ahc_tqinpos_print(u_int regvalue, u_int *cur_col, u_int wrap)
642{
643 return (ahc_print_register(NULL, 0, "TQINPOS",
644 0x50, regvalue, cur_col, wrap));
645}
646
647static const ahc_reg_parse_entry_t ARG_1_parse_table[] = {
648 { "CONT_TARG_SESSION", 0x02, 0x02 },
649 { "CONT_MSG_LOOP", 0x04, 0x04 },
650 { "EXIT_MSG_LOOP", 0x08, 0x08 },
651 { "MSGOUT_PHASEMIS", 0x10, 0x10 },
652 { "SEND_REJ", 0x20, 0x20 },
653 { "SEND_SENSE", 0x40, 0x40 },
654 { "SEND_MSG", 0x80, 0x80 }
655};
656
657int
658ahc_arg_1_print(u_int regvalue, u_int *cur_col, u_int wrap)
659{
660 return (ahc_print_register(ARG_1_parse_table, 7, "ARG_1",
661 0x51, regvalue, cur_col, wrap));
662}
663
664int
665ahc_arg_2_print(u_int regvalue, u_int *cur_col, u_int wrap)
666{
667 return (ahc_print_register(NULL, 0, "ARG_2",
668 0x52, regvalue, cur_col, wrap));
669}
670
671int
672ahc_last_msg_print(u_int regvalue, u_int *cur_col, u_int wrap)
673{
674 return (ahc_print_register(NULL, 0, "LAST_MSG",
675 0x53, regvalue, cur_col, wrap));
676}
677
678static const ahc_reg_parse_entry_t SCSISEQ_TEMPLATE_parse_table[] = {
679 { "ENAUTOATNP", 0x02, 0x02 },
680 { "ENAUTOATNI", 0x04, 0x04 },
681 { "ENAUTOATNO", 0x08, 0x08 },
682 { "ENRSELI", 0x10, 0x10 },
683 { "ENSELI", 0x20, 0x20 },
684 { "ENSELO", 0x40, 0x40 }
685};
686
687int
688ahc_scsiseq_template_print(u_int regvalue, u_int *cur_col, u_int wrap)
689{
690 return (ahc_print_register(SCSISEQ_TEMPLATE_parse_table, 6, "SCSISEQ_TEMPLATE",
691 0x54, regvalue, cur_col, wrap));
692}
693
694static const ahc_reg_parse_entry_t HA_274_BIOSGLOBAL_parse_table[] = {
695 { "HA_274_EXTENDED_TRANS",0x01, 0x01 }
696};
697
698int
699ahc_ha_274_biosglobal_print(u_int regvalue, u_int *cur_col, u_int wrap)
700{
701 return (ahc_print_register(HA_274_BIOSGLOBAL_parse_table, 1, "HA_274_BIOSGLOBAL",
702 0x56, regvalue, cur_col, wrap));
703}
704
705static const ahc_reg_parse_entry_t SEQ_FLAGS2_parse_table[] = {
706 { "SCB_DMA", 0x01, 0x01 },
707 { "TARGET_MSG_PENDING", 0x02, 0x02 }
708};
709
710int
711ahc_seq_flags2_print(u_int regvalue, u_int *cur_col, u_int wrap)
712{
713 return (ahc_print_register(SEQ_FLAGS2_parse_table, 2, "SEQ_FLAGS2",
714 0x57, regvalue, cur_col, wrap));
715}
716
717static const ahc_reg_parse_entry_t SCSICONF_parse_table[] = {
718 { "ENSPCHK", 0x20, 0x20 },
719 { "RESET_SCSI", 0x40, 0x40 },
720 { "TERM_ENB", 0x80, 0x80 },
721 { "HSCSIID", 0x07, 0x07 },
722 { "HWSCSIID", 0x0f, 0x0f }
723};
724
725int
726ahc_scsiconf_print(u_int regvalue, u_int *cur_col, u_int wrap)
727{
728 return (ahc_print_register(SCSICONF_parse_table, 5, "SCSICONF",
729 0x5a, regvalue, cur_col, wrap));
730}
731
732static const ahc_reg_parse_entry_t INTDEF_parse_table[] = {
733 { "EDGE_TRIG", 0x80, 0x80 },
734 { "VECTOR", 0x0f, 0x0f }
735};
736
737int
738ahc_intdef_print(u_int regvalue, u_int *cur_col, u_int wrap)
739{
740 return (ahc_print_register(INTDEF_parse_table, 2, "INTDEF",
741 0x5c, regvalue, cur_col, wrap));
742}
743
744int
745ahc_hostconf_print(u_int regvalue, u_int *cur_col, u_int wrap)
746{
747 return (ahc_print_register(NULL, 0, "HOSTCONF",
748 0x5d, regvalue, cur_col, wrap));
749}
750
751static const ahc_reg_parse_entry_t HA_274_BIOSCTRL_parse_table[] = {
752 { "CHANNEL_B_PRIMARY", 0x08, 0x08 },
753 { "BIOSMODE", 0x30, 0x30 },
754 { "BIOSDISABLED", 0x30, 0x30 }
755};
756
757int
758ahc_ha_274_biosctrl_print(u_int regvalue, u_int *cur_col, u_int wrap)
759{
760 return (ahc_print_register(HA_274_BIOSCTRL_parse_table, 3, "HA_274_BIOSCTRL",
761 0x5f, regvalue, cur_col, wrap));
762}
763
764static const ahc_reg_parse_entry_t SEQCTL_parse_table[] = { 258static const ahc_reg_parse_entry_t SEQCTL_parse_table[] = {
765 { "LOADRAM", 0x01, 0x01 }, 259 { "LOADRAM", 0x01, 0x01 },
766 { "SEQRESET", 0x02, 0x02 }, 260 { "SEQRESET", 0x02, 0x02 },
@@ -780,285 +274,12 @@ ahc_seqctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
780} 274}
781 275
782int 276int
783ahc_seqram_print(u_int regvalue, u_int *cur_col, u_int wrap)
784{
785 return (ahc_print_register(NULL, 0, "SEQRAM",
786 0x61, regvalue, cur_col, wrap));
787}
788
789int
790ahc_seqaddr0_print(u_int regvalue, u_int *cur_col, u_int wrap)
791{
792 return (ahc_print_register(NULL, 0, "SEQADDR0",
793 0x62, regvalue, cur_col, wrap));
794}
795
796static const ahc_reg_parse_entry_t SEQADDR1_parse_table[] = {
797 { "SEQADDR1_MASK", 0x01, 0x01 }
798};
799
800int
801ahc_seqaddr1_print(u_int regvalue, u_int *cur_col, u_int wrap)
802{
803 return (ahc_print_register(SEQADDR1_parse_table, 1, "SEQADDR1",
804 0x63, regvalue, cur_col, wrap));
805}
806
807int
808ahc_accum_print(u_int regvalue, u_int *cur_col, u_int wrap)
809{
810 return (ahc_print_register(NULL, 0, "ACCUM",
811 0x64, regvalue, cur_col, wrap));
812}
813
814int
815ahc_sindex_print(u_int regvalue, u_int *cur_col, u_int wrap)
816{
817 return (ahc_print_register(NULL, 0, "SINDEX",
818 0x65, regvalue, cur_col, wrap));
819}
820
821int
822ahc_dindex_print(u_int regvalue, u_int *cur_col, u_int wrap)
823{
824 return (ahc_print_register(NULL, 0, "DINDEX",
825 0x66, regvalue, cur_col, wrap));
826}
827
828int
829ahc_allones_print(u_int regvalue, u_int *cur_col, u_int wrap)
830{
831 return (ahc_print_register(NULL, 0, "ALLONES",
832 0x69, regvalue, cur_col, wrap));
833}
834
835int
836ahc_allzeros_print(u_int regvalue, u_int *cur_col, u_int wrap)
837{
838 return (ahc_print_register(NULL, 0, "ALLZEROS",
839 0x6a, regvalue, cur_col, wrap));
840}
841
842int
843ahc_none_print(u_int regvalue, u_int *cur_col, u_int wrap)
844{
845 return (ahc_print_register(NULL, 0, "NONE",
846 0x6a, regvalue, cur_col, wrap));
847}
848
849static const ahc_reg_parse_entry_t FLAGS_parse_table[] = {
850 { "CARRY", 0x01, 0x01 },
851 { "ZERO", 0x02, 0x02 }
852};
853
854int
855ahc_flags_print(u_int regvalue, u_int *cur_col, u_int wrap)
856{
857 return (ahc_print_register(FLAGS_parse_table, 2, "FLAGS",
858 0x6b, regvalue, cur_col, wrap));
859}
860
861int
862ahc_sindir_print(u_int regvalue, u_int *cur_col, u_int wrap)
863{
864 return (ahc_print_register(NULL, 0, "SINDIR",
865 0x6c, regvalue, cur_col, wrap));
866}
867
868int
869ahc_dindir_print(u_int regvalue, u_int *cur_col, u_int wrap)
870{
871 return (ahc_print_register(NULL, 0, "DINDIR",
872 0x6d, regvalue, cur_col, wrap));
873}
874
875int
876ahc_stack_print(u_int regvalue, u_int *cur_col, u_int wrap)
877{
878 return (ahc_print_register(NULL, 0, "STACK",
879 0x6f, regvalue, cur_col, wrap));
880}
881
882int
883ahc_targ_offset_print(u_int regvalue, u_int *cur_col, u_int wrap)
884{
885 return (ahc_print_register(NULL, 0, "TARG_OFFSET",
886 0x70, regvalue, cur_col, wrap));
887}
888
889int
890ahc_sram_base_print(u_int regvalue, u_int *cur_col, u_int wrap) 277ahc_sram_base_print(u_int regvalue, u_int *cur_col, u_int wrap)
891{ 278{
892 return (ahc_print_register(NULL, 0, "SRAM_BASE", 279 return (ahc_print_register(NULL, 0, "SRAM_BASE",
893 0x70, regvalue, cur_col, wrap)); 280 0x70, regvalue, cur_col, wrap));
894} 281}
895 282
896static const ahc_reg_parse_entry_t DSCOMMAND0_parse_table[] = {
897 { "CIOPARCKEN", 0x01, 0x01 },
898 { "USCBSIZE32", 0x02, 0x02 },
899 { "RAMPS", 0x04, 0x04 },
900 { "INTSCBRAMSEL", 0x08, 0x08 },
901 { "EXTREQLCK", 0x10, 0x10 },
902 { "MPARCKEN", 0x20, 0x20 },
903 { "DPARCKEN", 0x40, 0x40 },
904 { "CACHETHEN", 0x80, 0x80 }
905};
906
907int
908ahc_dscommand0_print(u_int regvalue, u_int *cur_col, u_int wrap)
909{
910 return (ahc_print_register(DSCOMMAND0_parse_table, 8, "DSCOMMAND0",
911 0x84, regvalue, cur_col, wrap));
912}
913
914static const ahc_reg_parse_entry_t BUSTIME_parse_table[] = {
915 { "BON", 0x0f, 0x0f },
916 { "BOFF", 0xf0, 0xf0 }
917};
918
919int
920ahc_bustime_print(u_int regvalue, u_int *cur_col, u_int wrap)
921{
922 return (ahc_print_register(BUSTIME_parse_table, 2, "BUSTIME",
923 0x85, regvalue, cur_col, wrap));
924}
925
926static const ahc_reg_parse_entry_t DSCOMMAND1_parse_table[] = {
927 { "HADDLDSEL0", 0x01, 0x01 },
928 { "HADDLDSEL1", 0x02, 0x02 },
929 { "DSLATT", 0xfc, 0xfc }
930};
931
932int
933ahc_dscommand1_print(u_int regvalue, u_int *cur_col, u_int wrap)
934{
935 return (ahc_print_register(DSCOMMAND1_parse_table, 3, "DSCOMMAND1",
936 0x85, regvalue, cur_col, wrap));
937}
938
939static const ahc_reg_parse_entry_t BUSSPD_parse_table[] = {
940 { "STBON", 0x07, 0x07 },
941 { "STBOFF", 0x38, 0x38 },
942 { "DFTHRSH_75", 0x80, 0x80 },
943 { "DFTHRSH", 0xc0, 0xc0 },
944 { "DFTHRSH_100", 0xc0, 0xc0 }
945};
946
947int
948ahc_busspd_print(u_int regvalue, u_int *cur_col, u_int wrap)
949{
950 return (ahc_print_register(BUSSPD_parse_table, 5, "BUSSPD",
951 0x86, regvalue, cur_col, wrap));
952}
953
954static const ahc_reg_parse_entry_t HS_MAILBOX_parse_table[] = {
955 { "SEQ_MAILBOX", 0x0f, 0x0f },
956 { "HOST_TQINPOS", 0x80, 0x80 },
957 { "HOST_MAILBOX", 0xf0, 0xf0 }
958};
959
960int
961ahc_hs_mailbox_print(u_int regvalue, u_int *cur_col, u_int wrap)
962{
963 return (ahc_print_register(HS_MAILBOX_parse_table, 3, "HS_MAILBOX",
964 0x86, regvalue, cur_col, wrap));
965}
966
967static const ahc_reg_parse_entry_t DSPCISTATUS_parse_table[] = {
968 { "DFTHRSH_100", 0xc0, 0xc0 }
969};
970
971int
972ahc_dspcistatus_print(u_int regvalue, u_int *cur_col, u_int wrap)
973{
974 return (ahc_print_register(DSPCISTATUS_parse_table, 1, "DSPCISTATUS",
975 0x86, regvalue, cur_col, wrap));
976}
977
978static const ahc_reg_parse_entry_t HCNTRL_parse_table[] = {
979 { "CHIPRST", 0x01, 0x01 },
980 { "CHIPRSTACK", 0x01, 0x01 },
981 { "INTEN", 0x02, 0x02 },
982 { "PAUSE", 0x04, 0x04 },
983 { "IRQMS", 0x08, 0x08 },
984 { "SWINT", 0x10, 0x10 },
985 { "POWRDN", 0x40, 0x40 }
986};
987
988int
989ahc_hcntrl_print(u_int regvalue, u_int *cur_col, u_int wrap)
990{
991 return (ahc_print_register(HCNTRL_parse_table, 7, "HCNTRL",
992 0x87, regvalue, cur_col, wrap));
993}
994
995int
996ahc_haddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
997{
998 return (ahc_print_register(NULL, 0, "HADDR",
999 0x88, regvalue, cur_col, wrap));
1000}
1001
1002int
1003ahc_hcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
1004{
1005 return (ahc_print_register(NULL, 0, "HCNT",
1006 0x8c, regvalue, cur_col, wrap));
1007}
1008
1009int
1010ahc_scbptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1011{
1012 return (ahc_print_register(NULL, 0, "SCBPTR",
1013 0x90, regvalue, cur_col, wrap));
1014}
1015
1016static const ahc_reg_parse_entry_t INTSTAT_parse_table[] = {
1017 { "SEQINT", 0x01, 0x01 },
1018 { "CMDCMPLT", 0x02, 0x02 },
1019 { "SCSIINT", 0x04, 0x04 },
1020 { "BRKADRINT", 0x08, 0x08 },
1021 { "BAD_PHASE", 0x01, 0x01 },
1022 { "INT_PEND", 0x0f, 0x0f },
1023 { "SEND_REJECT", 0x11, 0x11 },
1024 { "PROTO_VIOLATION", 0x21, 0x21 },
1025 { "NO_MATCH", 0x31, 0x31 },
1026 { "IGN_WIDE_RES", 0x41, 0x41 },
1027 { "PDATA_REINIT", 0x51, 0x51 },
1028 { "HOST_MSG_LOOP", 0x61, 0x61 },
1029 { "BAD_STATUS", 0x71, 0x71 },
1030 { "PERR_DETECTED", 0x81, 0x81 },
1031 { "DATA_OVERRUN", 0x91, 0x91 },
1032 { "MKMSG_FAILED", 0xa1, 0xa1 },
1033 { "MISSED_BUSFREE", 0xb1, 0xb1 },
1034 { "SCB_MISMATCH", 0xc1, 0xc1 },
1035 { "NO_FREE_SCB", 0xd1, 0xd1 },
1036 { "OUT_OF_RANGE", 0xe1, 0xe1 },
1037 { "SEQINT_MASK", 0xf1, 0xf1 }
1038};
1039
1040int
1041ahc_intstat_print(u_int regvalue, u_int *cur_col, u_int wrap)
1042{
1043 return (ahc_print_register(INTSTAT_parse_table, 21, "INTSTAT",
1044 0x91, regvalue, cur_col, wrap));
1045}
1046
1047static const ahc_reg_parse_entry_t CLRINT_parse_table[] = {
1048 { "CLRSEQINT", 0x01, 0x01 },
1049 { "CLRCMDINT", 0x02, 0x02 },
1050 { "CLRSCSIINT", 0x04, 0x04 },
1051 { "CLRBRKADRINT", 0x08, 0x08 },
1052 { "CLRPARERR", 0x10, 0x10 }
1053};
1054
1055int
1056ahc_clrint_print(u_int regvalue, u_int *cur_col, u_int wrap)
1057{
1058 return (ahc_print_register(CLRINT_parse_table, 5, "CLRINT",
1059 0x92, regvalue, cur_col, wrap));
1060}
1061
1062static const ahc_reg_parse_entry_t ERROR_parse_table[] = { 283static const ahc_reg_parse_entry_t ERROR_parse_table[] = {
1063 { "ILLHADDR", 0x01, 0x01 }, 284 { "ILLHADDR", 0x01, 0x01 },
1064 { "ILLSADDR", 0x02, 0x02 }, 285 { "ILLSADDR", 0x02, 0x02 },
@@ -1115,62 +336,6 @@ ahc_dfstatus_print(u_int regvalue, u_int *cur_col, u_int wrap)
1115 0x94, regvalue, cur_col, wrap)); 336 0x94, regvalue, cur_col, wrap));
1116} 337}
1117 338
1118int
1119ahc_dfwaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1120{
1121 return (ahc_print_register(NULL, 0, "DFWADDR",
1122 0x95, regvalue, cur_col, wrap));
1123}
1124
1125int
1126ahc_dfdat_print(u_int regvalue, u_int *cur_col, u_int wrap)
1127{
1128 return (ahc_print_register(NULL, 0, "DFDAT",
1129 0x99, regvalue, cur_col, wrap));
1130}
1131
1132static const ahc_reg_parse_entry_t SCBCNT_parse_table[] = {
1133 { "SCBAUTO", 0x80, 0x80 },
1134 { "SCBCNT_MASK", 0x1f, 0x1f }
1135};
1136
1137int
1138ahc_scbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
1139{
1140 return (ahc_print_register(SCBCNT_parse_table, 2, "SCBCNT",
1141 0x9a, regvalue, cur_col, wrap));
1142}
1143
1144int
1145ahc_qinfifo_print(u_int regvalue, u_int *cur_col, u_int wrap)
1146{
1147 return (ahc_print_register(NULL, 0, "QINFIFO",
1148 0x9b, regvalue, cur_col, wrap));
1149}
1150
1151int
1152ahc_qoutfifo_print(u_int regvalue, u_int *cur_col, u_int wrap)
1153{
1154 return (ahc_print_register(NULL, 0, "QOUTFIFO",
1155 0x9d, regvalue, cur_col, wrap));
1156}
1157
1158static const ahc_reg_parse_entry_t CRCCONTROL1_parse_table[] = {
1159 { "TARGCRCCNTEN", 0x04, 0x04 },
1160 { "TARGCRCENDEN", 0x08, 0x08 },
1161 { "CRCREQCHKEN", 0x10, 0x10 },
1162 { "CRCENDCHKEN", 0x20, 0x20 },
1163 { "CRCVALCHKEN", 0x40, 0x40 },
1164 { "CRCONSEEN", 0x80, 0x80 }
1165};
1166
1167int
1168ahc_crccontrol1_print(u_int regvalue, u_int *cur_col, u_int wrap)
1169{
1170 return (ahc_print_register(CRCCONTROL1_parse_table, 6, "CRCCONTROL1",
1171 0x9d, regvalue, cur_col, wrap));
1172}
1173
1174static const ahc_reg_parse_entry_t SCSIPHASE_parse_table[] = { 339static const ahc_reg_parse_entry_t SCSIPHASE_parse_table[] = {
1175 { "DATA_OUT_PHASE", 0x01, 0x01 }, 340 { "DATA_OUT_PHASE", 0x01, 0x01 },
1176 { "DATA_IN_PHASE", 0x02, 0x02 }, 341 { "DATA_IN_PHASE", 0x02, 0x02 },
@@ -1188,17 +353,6 @@ ahc_scsiphase_print(u_int regvalue, u_int *cur_col, u_int wrap)
1188 0x9e, regvalue, cur_col, wrap)); 353 0x9e, regvalue, cur_col, wrap));
1189} 354}
1190 355
1191static const ahc_reg_parse_entry_t SFUNCT_parse_table[] = {
1192 { "ALT_MODE", 0x80, 0x80 }
1193};
1194
1195int
1196ahc_sfunct_print(u_int regvalue, u_int *cur_col, u_int wrap)
1197{
1198 return (ahc_print_register(SFUNCT_parse_table, 1, "SFUNCT",
1199 0x9f, regvalue, cur_col, wrap));
1200}
1201
1202int 356int
1203ahc_scb_base_print(u_int regvalue, u_int *cur_col, u_int wrap) 357ahc_scb_base_print(u_int regvalue, u_int *cur_col, u_int wrap)
1204{ 358{
@@ -1206,80 +360,6 @@ ahc_scb_base_print(u_int regvalue, u_int *cur_col, u_int wrap)
1206 0xa0, regvalue, cur_col, wrap)); 360 0xa0, regvalue, cur_col, wrap));
1207} 361}
1208 362
1209int
1210ahc_scb_cdb_ptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1211{
1212 return (ahc_print_register(NULL, 0, "SCB_CDB_PTR",
1213 0xa0, regvalue, cur_col, wrap));
1214}
1215
1216int
1217ahc_scb_residual_sgptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1218{
1219 return (ahc_print_register(NULL, 0, "SCB_RESIDUAL_SGPTR",
1220 0xa4, regvalue, cur_col, wrap));
1221}
1222
1223int
1224ahc_scb_scsi_status_print(u_int regvalue, u_int *cur_col, u_int wrap)
1225{
1226 return (ahc_print_register(NULL, 0, "SCB_SCSI_STATUS",
1227 0xa8, regvalue, cur_col, wrap));
1228}
1229
1230int
1231ahc_scb_target_phases_print(u_int regvalue, u_int *cur_col, u_int wrap)
1232{
1233 return (ahc_print_register(NULL, 0, "SCB_TARGET_PHASES",
1234 0xa9, regvalue, cur_col, wrap));
1235}
1236
1237int
1238ahc_scb_target_data_dir_print(u_int regvalue, u_int *cur_col, u_int wrap)
1239{
1240 return (ahc_print_register(NULL, 0, "SCB_TARGET_DATA_DIR",
1241 0xaa, regvalue, cur_col, wrap));
1242}
1243
1244int
1245ahc_scb_target_itag_print(u_int regvalue, u_int *cur_col, u_int wrap)
1246{
1247 return (ahc_print_register(NULL, 0, "SCB_TARGET_ITAG",
1248 0xab, regvalue, cur_col, wrap));
1249}
1250
1251int
1252ahc_scb_dataptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1253{
1254 return (ahc_print_register(NULL, 0, "SCB_DATAPTR",
1255 0xac, regvalue, cur_col, wrap));
1256}
1257
1258static const ahc_reg_parse_entry_t SCB_DATACNT_parse_table[] = {
1259 { "SG_LAST_SEG", 0x80, 0x80 },
1260 { "SG_HIGH_ADDR_BITS", 0x7f, 0x7f }
1261};
1262
1263int
1264ahc_scb_datacnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
1265{
1266 return (ahc_print_register(SCB_DATACNT_parse_table, 2, "SCB_DATACNT",
1267 0xb0, regvalue, cur_col, wrap));
1268}
1269
1270static const ahc_reg_parse_entry_t SCB_SGPTR_parse_table[] = {
1271 { "SG_LIST_NULL", 0x01, 0x01 },
1272 { "SG_FULL_RESID", 0x02, 0x02 },
1273 { "SG_RESID_VALID", 0x04, 0x04 }
1274};
1275
1276int
1277ahc_scb_sgptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1278{
1279 return (ahc_print_register(SCB_SGPTR_parse_table, 3, "SCB_SGPTR",
1280 0xb4, regvalue, cur_col, wrap));
1281}
1282
1283static const ahc_reg_parse_entry_t SCB_CONTROL_parse_table[] = { 363static const ahc_reg_parse_entry_t SCB_CONTROL_parse_table[] = {
1284 { "DISCONNECTED", 0x04, 0x04 }, 364 { "DISCONNECTED", 0x04, 0x04 },
1285 { "ULTRAENB", 0x08, 0x08 }, 365 { "ULTRAENB", 0x08, 0x08 },
@@ -1331,248 +411,3 @@ ahc_scb_tag_print(u_int regvalue, u_int *cur_col, u_int wrap)
1331 0xbb, regvalue, cur_col, wrap)); 411 0xbb, regvalue, cur_col, wrap));
1332} 412}
1333 413
1334int
1335ahc_scb_cdb_len_print(u_int regvalue, u_int *cur_col, u_int wrap)
1336{
1337 return (ahc_print_register(NULL, 0, "SCB_CDB_LEN",
1338 0xbc, regvalue, cur_col, wrap));
1339}
1340
1341int
1342ahc_scb_scsirate_print(u_int regvalue, u_int *cur_col, u_int wrap)
1343{
1344 return (ahc_print_register(NULL, 0, "SCB_SCSIRATE",
1345 0xbd, regvalue, cur_col, wrap));
1346}
1347
1348int
1349ahc_scb_scsioffset_print(u_int regvalue, u_int *cur_col, u_int wrap)
1350{
1351 return (ahc_print_register(NULL, 0, "SCB_SCSIOFFSET",
1352 0xbe, regvalue, cur_col, wrap));
1353}
1354
1355int
1356ahc_scb_next_print(u_int regvalue, u_int *cur_col, u_int wrap)
1357{
1358 return (ahc_print_register(NULL, 0, "SCB_NEXT",
1359 0xbf, regvalue, cur_col, wrap));
1360}
1361
1362static const ahc_reg_parse_entry_t SEECTL_2840_parse_table[] = {
1363 { "DO_2840", 0x01, 0x01 },
1364 { "CK_2840", 0x02, 0x02 },
1365 { "CS_2840", 0x04, 0x04 }
1366};
1367
1368int
1369ahc_seectl_2840_print(u_int regvalue, u_int *cur_col, u_int wrap)
1370{
1371 return (ahc_print_register(SEECTL_2840_parse_table, 3, "SEECTL_2840",
1372 0xc0, regvalue, cur_col, wrap));
1373}
1374
1375static const ahc_reg_parse_entry_t STATUS_2840_parse_table[] = {
1376 { "DI_2840", 0x01, 0x01 },
1377 { "EEPROM_TF", 0x80, 0x80 },
1378 { "ADSEL", 0x1e, 0x1e },
1379 { "BIOS_SEL", 0x60, 0x60 }
1380};
1381
1382int
1383ahc_status_2840_print(u_int regvalue, u_int *cur_col, u_int wrap)
1384{
1385 return (ahc_print_register(STATUS_2840_parse_table, 4, "STATUS_2840",
1386 0xc1, regvalue, cur_col, wrap));
1387}
1388
1389int
1390ahc_scb_64_btt_print(u_int regvalue, u_int *cur_col, u_int wrap)
1391{
1392 return (ahc_print_register(NULL, 0, "SCB_64_BTT",
1393 0xd0, regvalue, cur_col, wrap));
1394}
1395
1396int
1397ahc_cchaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1398{
1399 return (ahc_print_register(NULL, 0, "CCHADDR",
1400 0xe0, regvalue, cur_col, wrap));
1401}
1402
1403int
1404ahc_cchcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
1405{
1406 return (ahc_print_register(NULL, 0, "CCHCNT",
1407 0xe8, regvalue, cur_col, wrap));
1408}
1409
1410int
1411ahc_ccsgram_print(u_int regvalue, u_int *cur_col, u_int wrap)
1412{
1413 return (ahc_print_register(NULL, 0, "CCSGRAM",
1414 0xe9, regvalue, cur_col, wrap));
1415}
1416
1417int
1418ahc_ccsgaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1419{
1420 return (ahc_print_register(NULL, 0, "CCSGADDR",
1421 0xea, regvalue, cur_col, wrap));
1422}
1423
1424static const ahc_reg_parse_entry_t CCSGCTL_parse_table[] = {
1425 { "CCSGRESET", 0x01, 0x01 },
1426 { "SG_FETCH_NEEDED", 0x02, 0x02 },
1427 { "CCSGEN", 0x08, 0x08 },
1428 { "CCSGDONE", 0x80, 0x80 }
1429};
1430
1431int
1432ahc_ccsgctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
1433{
1434 return (ahc_print_register(CCSGCTL_parse_table, 4, "CCSGCTL",
1435 0xeb, regvalue, cur_col, wrap));
1436}
1437
1438int
1439ahc_ccscbram_print(u_int regvalue, u_int *cur_col, u_int wrap)
1440{
1441 return (ahc_print_register(NULL, 0, "CCSCBRAM",
1442 0xec, regvalue, cur_col, wrap));
1443}
1444
1445int
1446ahc_ccscbaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1447{
1448 return (ahc_print_register(NULL, 0, "CCSCBADDR",
1449 0xed, regvalue, cur_col, wrap));
1450}
1451
1452static const ahc_reg_parse_entry_t CCSCBCTL_parse_table[] = {
1453 { "CCSCBRESET", 0x01, 0x01 },
1454 { "CCSCBDIR", 0x04, 0x04 },
1455 { "CCSCBEN", 0x08, 0x08 },
1456 { "CCARREN", 0x10, 0x10 },
1457 { "ARRDONE", 0x40, 0x40 },
1458 { "CCSCBDONE", 0x80, 0x80 }
1459};
1460
1461int
1462ahc_ccscbctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
1463{
1464 return (ahc_print_register(CCSCBCTL_parse_table, 6, "CCSCBCTL",
1465 0xee, regvalue, cur_col, wrap));
1466}
1467
1468int
1469ahc_ccscbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
1470{
1471 return (ahc_print_register(NULL, 0, "CCSCBCNT",
1472 0xef, regvalue, cur_col, wrap));
1473}
1474
1475int
1476ahc_scbbaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1477{
1478 return (ahc_print_register(NULL, 0, "SCBBADDR",
1479 0xf0, regvalue, cur_col, wrap));
1480}
1481
1482int
1483ahc_ccscbptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1484{
1485 return (ahc_print_register(NULL, 0, "CCSCBPTR",
1486 0xf1, regvalue, cur_col, wrap));
1487}
1488
1489int
1490ahc_hnscb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap)
1491{
1492 return (ahc_print_register(NULL, 0, "HNSCB_QOFF",
1493 0xf4, regvalue, cur_col, wrap));
1494}
1495
1496int
1497ahc_snscb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap)
1498{
1499 return (ahc_print_register(NULL, 0, "SNSCB_QOFF",
1500 0xf6, regvalue, cur_col, wrap));
1501}
1502
1503int
1504ahc_sdscb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap)
1505{
1506 return (ahc_print_register(NULL, 0, "SDSCB_QOFF",
1507 0xf8, regvalue, cur_col, wrap));
1508}
1509
1510static const ahc_reg_parse_entry_t QOFF_CTLSTA_parse_table[] = {
1511 { "SDSCB_ROLLOVER", 0x10, 0x10 },
1512 { "SNSCB_ROLLOVER", 0x20, 0x20 },
1513 { "SCB_AVAIL", 0x40, 0x40 },
1514 { "SCB_QSIZE_256", 0x06, 0x06 },
1515 { "SCB_QSIZE", 0x07, 0x07 }
1516};
1517
1518int
1519ahc_qoff_ctlsta_print(u_int regvalue, u_int *cur_col, u_int wrap)
1520{
1521 return (ahc_print_register(QOFF_CTLSTA_parse_table, 5, "QOFF_CTLSTA",
1522 0xfa, regvalue, cur_col, wrap));
1523}
1524
1525static const ahc_reg_parse_entry_t DFF_THRSH_parse_table[] = {
1526 { "RD_DFTHRSH_MIN", 0x00, 0x00 },
1527 { "WR_DFTHRSH_MIN", 0x00, 0x00 },
1528 { "RD_DFTHRSH_25", 0x01, 0x01 },
1529 { "RD_DFTHRSH_50", 0x02, 0x02 },
1530 { "RD_DFTHRSH_63", 0x03, 0x03 },
1531 { "RD_DFTHRSH_75", 0x04, 0x04 },
1532 { "RD_DFTHRSH_85", 0x05, 0x05 },
1533 { "RD_DFTHRSH_90", 0x06, 0x06 },
1534 { "RD_DFTHRSH", 0x07, 0x07 },
1535 { "RD_DFTHRSH_MAX", 0x07, 0x07 },
1536 { "WR_DFTHRSH_25", 0x10, 0x10 },
1537 { "WR_DFTHRSH_50", 0x20, 0x20 },
1538 { "WR_DFTHRSH_63", 0x30, 0x30 },
1539 { "WR_DFTHRSH_75", 0x40, 0x40 },
1540 { "WR_DFTHRSH_85", 0x50, 0x50 },
1541 { "WR_DFTHRSH_90", 0x60, 0x60 },
1542 { "WR_DFTHRSH", 0x70, 0x70 },
1543 { "WR_DFTHRSH_MAX", 0x70, 0x70 }
1544};
1545
1546int
1547ahc_dff_thrsh_print(u_int regvalue, u_int *cur_col, u_int wrap)
1548{
1549 return (ahc_print_register(DFF_THRSH_parse_table, 18, "DFF_THRSH",
1550 0xfb, regvalue, cur_col, wrap));
1551}
1552
1553static const ahc_reg_parse_entry_t SG_CACHE_SHADOW_parse_table[] = {
1554 { "LAST_SEG_DONE", 0x01, 0x01 },
1555 { "LAST_SEG", 0x02, 0x02 },
1556 { "SG_ADDR_MASK", 0xf8, 0xf8 }
1557};
1558
1559int
1560ahc_sg_cache_shadow_print(u_int regvalue, u_int *cur_col, u_int wrap)
1561{
1562 return (ahc_print_register(SG_CACHE_SHADOW_parse_table, 3, "SG_CACHE_SHADOW",
1563 0xfc, regvalue, cur_col, wrap));
1564}
1565
1566static const ahc_reg_parse_entry_t SG_CACHE_PRE_parse_table[] = {
1567 { "LAST_SEG_DONE", 0x01, 0x01 },
1568 { "LAST_SEG", 0x02, 0x02 },
1569 { "SG_ADDR_MASK", 0xf8, 0xf8 }
1570};
1571
1572int
1573ahc_sg_cache_pre_print(u_int regvalue, u_int *cur_col, u_int wrap)
1574{
1575 return (ahc_print_register(SG_CACHE_PRE_parse_table, 3, "SG_CACHE_PRE",
1576 0xfc, regvalue, cur_col, wrap));
1577}
1578
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-22 17:02:27 -0500