[PATCH] i386: i386 make NMI use PERFCTR1 for architectural perfmon (take 2)

Hello,

This patch against 2.6.20-git14 makes the NMI watchdog use PERFSEL1/PERFCTR1
instead of PERFSEL0/PERFCTR0 on processors supporting Intel architectural
perfmon, such as Intel Core 2. Although all PMU events can work on
both counters, the Precise Event-Based Sampling (PEBS) requires that the
event be in PERFCTR0 to work correctly (see section 18.14.4.1 in the
IA32 SDM Vol 3b).

A similar patch for x86-64 is to follow.

Changelog:
        - make the i386 NMI watchdog use PERFSEL1/PERFCTR1 instead of PERFSEL0/PERFCTR0
          on processors supporting the Intel architectural perfmon (e.g. Core 2 Duo).
          This allows PEBS to work when the NMI watchdog is active.

signed-off-by: stephane eranian <eranian@hpl.hp.com>

Signed-off-by: Andi Kleen <ak@suse.de>

1 files changed, 4 insertions, 4 deletions

diff --git a/arch/i386/kernel/nmi.c b/arch/i386/kernel/nmi.c
index 84c3497efb60..aef22c881a0d 100644
--- a/arch/i386/kernel/nmi.c
+++ b/arch/i386/kernel/nmi.c
@@ -365,7 +365,7 @@ static int __init check_nmi_watchdog(void)
                 nmi_hz = 1;
 
                 if (wd->perfctr_msr == MSR_P6_PERFCTR0 ||
-                    wd->perfctr_msr == MSR_ARCH_PERFMON_PERFCTR0) {
+                    wd->perfctr_msr == MSR_ARCH_PERFMON_PERFCTR1) {
                         nmi_hz = adjust_for_32bit_ctr(nmi_hz);
                 }
         }
@@ -799,8 +799,8 @@ static int setup_intel_arch_watchdog(void)
             (ebx & ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT))
                 goto fail;
 
-        perfctr_msr = MSR_ARCH_PERFMON_PERFCTR0;
-        evntsel_msr = MSR_ARCH_PERFMON_EVENTSEL0;
+        perfctr_msr = MSR_ARCH_PERFMON_PERFCTR1;
+        evntsel_msr = MSR_ARCH_PERFMON_EVENTSEL1;
 
         if (!__reserve_perfctr_nmi(-1, perfctr_msr))
                 goto fail;
@@ -1080,7 +1080,7 @@ __kprobes int nmi_watchdog_tick(struct pt_regs * regs, unsigned reason)
                                 write_watchdog_counter(wd->perfctr_msr, NULL);
                         }
                         else if (wd->perfctr_msr == MSR_P6_PERFCTR0 ||
-                                 wd->perfctr_msr == MSR_ARCH_PERFMON_PERFCTR0) {
+                                 wd->perfctr_msr == MSR_ARCH_PERFMON_PERFCTR1) {
                                 /* P6 based Pentium M need to re-unmask
                                  * the apic vector but it doesn't hurt
                                  * other P6 variant.