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authorStephen Hemminger <shemminger@osdl.org>2006-12-01 19:36:16 -0500
committerJeff Garzik <jeff@garzik.org>2006-12-02 00:24:49 -0500
commitf1d3d38af75789f1b82969b83b69cab540609789 (patch)
tree47d31e8a55fb65cf33797197b92a332630cfc3ef
parent415294ecbb32ddbd0a7a2b7bae0b60fedfa09cc4 (diff)
[PATCH] chelsio: add support for other 10G boards
Add support for other versions of the 10G Chelsio boards. This is basically a port of the vendor driver with the TOE features removed. Signed-off-by: Stephen Hemminger <shemminger@osdl.org> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat
-rw-r--r--drivers/net/Kconfig6
-rw-r--r--drivers/net/chelsio/Makefile7
-rw-r--r--drivers/net/chelsio/common.h101
-rw-r--r--drivers/net/chelsio/cphy.h24
-rw-r--r--drivers/net/chelsio/cpl5_cmd.h510
-rw-r--r--drivers/net/chelsio/cxgb2.c238
-rw-r--r--drivers/net/chelsio/elmer0.h7
-rw-r--r--drivers/net/chelsio/espi.c203
-rw-r--r--drivers/net/chelsio/espi.h1
-rw-r--r--drivers/net/chelsio/fpga_defs.h232
-rw-r--r--drivers/net/chelsio/gmac.h5
-rw-r--r--drivers/net/chelsio/mv88e1xxx.h127
-rw-r--r--drivers/net/chelsio/mv88x201x.c32
-rw-r--r--drivers/net/chelsio/my3126.c204
-rw-r--r--drivers/net/chelsio/pm3393.c24
-rw-r--r--drivers/net/chelsio/regs.h1718
-rw-r--r--drivers/net/chelsio/sge.c770
-rw-r--r--drivers/net/chelsio/sge.h4
-rw-r--r--drivers/net/chelsio/subr.c265
-rw-r--r--drivers/net/chelsio/suni1x10gexp_regs.h1430
-rw-r--r--drivers/net/chelsio/tp.c145
-rw-r--r--drivers/net/chelsio/tp.h73
-rw-r--r--drivers/net/chelsio/vsc7326_reg.h286
23 files changed, 6041 insertions, 371 deletions
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 460517a19a63..2f10dd554e33 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -2361,9 +2361,9 @@ config CHELSIO_T1
2361 tristate "Chelsio 10Gb Ethernet support" 2361 tristate "Chelsio 10Gb Ethernet support"
2362 depends on PCI 2362 depends on PCI
2363 help 2363 help
2364 This driver supports Chelsio N110 and N210 models 10Gb Ethernet 2364 This driver supports Chelsio gigabit and 10-gigabit
2365 cards. More information about adapter features and performance 2365 Ethernet cards. More information about adapter features and
2366 tuning is in <file:Documentation/networking/cxgb.txt>. 2366 performance tuning is in <file:Documentation/networking/cxgb.txt>.
2367 2367
2368 For general information about Chelsio and our products, visit 2368 For general information about Chelsio and our products, visit
2369 our website at <http://www.chelsio.com>. 2369 our website at <http://www.chelsio.com>.
diff --git a/drivers/net/chelsio/Makefile b/drivers/net/chelsio/Makefile
index 54c78d94f48b..6d87316e58cb 100644
--- a/drivers/net/chelsio/Makefile
+++ b/drivers/net/chelsio/Makefile
@@ -1,11 +1,10 @@
1# 1#
2# Chelsio 10Gb NIC driver for Linux. 2# Chelsio T1 driver
3# 3#
4 4
5obj-$(CONFIG_CHELSIO_T1) += cxgb.o 5obj-$(CONFIG_CHELSIO_T1) += cxgb.o
6 6
7EXTRA_CFLAGS += -Idrivers/net/chelsio $(DEBUG_FLAGS) 7cxgb-objs := cxgb2.o espi.o tp.o pm3393.o sge.o subr.o \
8 mv88x201x.o my3126.o $(cxgb-y)
8 9
9 10
10cxgb-objs := cxgb2.o espi.o pm3393.o sge.o subr.o mv88x201x.o
11
diff --git a/drivers/net/chelsio/common.h b/drivers/net/chelsio/common.h
index efe1f6685285..e4e59d2d410e 100644
--- a/drivers/net/chelsio/common.h
+++ b/drivers/net/chelsio/common.h
@@ -45,6 +45,7 @@
45#include <linux/delay.h> 45#include <linux/delay.h>
46#include <linux/pci.h> 46#include <linux/pci.h>
47#include <linux/ethtool.h> 47#include <linux/ethtool.h>
48#include <linux/if_vlan.h>
48#include <linux/mii.h> 49#include <linux/mii.h>
49#include <linux/crc32.h> 50#include <linux/crc32.h>
50#include <linux/init.h> 51#include <linux/init.h>
@@ -53,13 +54,30 @@
53 54
54#define DRV_DESCRIPTION "Chelsio 10Gb Ethernet Driver" 55#define DRV_DESCRIPTION "Chelsio 10Gb Ethernet Driver"
55#define DRV_NAME "cxgb" 56#define DRV_NAME "cxgb"
56#define DRV_VERSION "2.1.1" 57#define DRV_VERSION "2.2"
57#define PFX DRV_NAME ": " 58#define PFX DRV_NAME ": "
58 59
59#define CH_ERR(fmt, ...) printk(KERN_ERR PFX fmt, ## __VA_ARGS__) 60#define CH_ERR(fmt, ...) printk(KERN_ERR PFX fmt, ## __VA_ARGS__)
60#define CH_WARN(fmt, ...) printk(KERN_WARNING PFX fmt, ## __VA_ARGS__) 61#define CH_WARN(fmt, ...) printk(KERN_WARNING PFX fmt, ## __VA_ARGS__)
61#define CH_ALERT(fmt, ...) printk(KERN_ALERT PFX fmt, ## __VA_ARGS__) 62#define CH_ALERT(fmt, ...) printk(KERN_ALERT PFX fmt, ## __VA_ARGS__)
62 63
64/*
65 * More powerful macro that selectively prints messages based on msg_enable.
66 * For info and debugging messages.
67 */
68#define CH_MSG(adapter, level, category, fmt, ...) do { \
69 if ((adapter)->msg_enable & NETIF_MSG_##category) \
70 printk(KERN_##level PFX "%s: " fmt, (adapter)->name, \
71 ## __VA_ARGS__); \
72} while (0)
73
74#ifdef DEBUG
75# define CH_DBG(adapter, category, fmt, ...) \
76 CH_MSG(adapter, DEBUG, category, fmt, ## __VA_ARGS__)
77#else
78# define CH_DBG(fmt, ...)
79#endif
80
63#define CH_DEVICE(devid, ssid, idx) \ 81#define CH_DEVICE(devid, ssid, idx) \
64 { PCI_VENDOR_ID_CHELSIO, devid, PCI_ANY_ID, ssid, 0, 0, idx } 82 { PCI_VENDOR_ID_CHELSIO, devid, PCI_ANY_ID, ssid, 0, 0, idx }
65 83
@@ -71,10 +89,6 @@
71 89
72typedef struct adapter adapter_t; 90typedef struct adapter adapter_t;
73 91
74void t1_elmer0_ext_intr(adapter_t *adapter);
75void t1_link_changed(adapter_t *adapter, int port_id, int link_status,
76 int speed, int duplex, int fc);
77
78struct t1_rx_mode { 92struct t1_rx_mode {
79 struct net_device *dev; 93 struct net_device *dev;
80 u32 idx; 94 u32 idx;
@@ -97,26 +111,53 @@ static inline u8 *t1_get_next_mcaddr(struct t1_rx_mode *rm)
97} 111}
98 112
99#define MAX_NPORTS 4 113#define MAX_NPORTS 4
114#define PORT_MASK ((1 << MAX_NPORTS) - 1)
115#define NMTUS 8
116#define TCB_SIZE 128
100 117
101#define SPEED_INVALID 0xffff 118#define SPEED_INVALID 0xffff
102#define DUPLEX_INVALID 0xff 119#define DUPLEX_INVALID 0xff
103 120
104enum { 121enum {
105 CHBT_BOARD_N110, 122 CHBT_BOARD_N110,
106 CHBT_BOARD_N210 123 CHBT_BOARD_N210,
124 CHBT_BOARD_7500,
125 CHBT_BOARD_8000,
126 CHBT_BOARD_CHT101,
127 CHBT_BOARD_CHT110,
128 CHBT_BOARD_CHT210,
129 CHBT_BOARD_CHT204,
130 CHBT_BOARD_CHT204V,
131 CHBT_BOARD_CHT204E,
132 CHBT_BOARD_CHN204,
133 CHBT_BOARD_COUGAR,
134 CHBT_BOARD_6800,
135 CHBT_BOARD_SIMUL,
107}; 136};
108 137
109enum { 138enum {
139 CHBT_TERM_FPGA,
110 CHBT_TERM_T1, 140 CHBT_TERM_T1,
111 CHBT_TERM_T2 141 CHBT_TERM_T2,
142 CHBT_TERM_T3
112}; 143};
113 144
114enum { 145enum {
146 CHBT_MAC_CHELSIO_A,
147 CHBT_MAC_IXF1010,
115 CHBT_MAC_PM3393, 148 CHBT_MAC_PM3393,
149 CHBT_MAC_VSC7321,
150 CHBT_MAC_DUMMY
116}; 151};
117 152
118enum { 153enum {
154 CHBT_PHY_88E1041,
155 CHBT_PHY_88E1111,
119 CHBT_PHY_88X2010, 156 CHBT_PHY_88X2010,
157 CHBT_PHY_XPAK,
158 CHBT_PHY_MY3126,
159 CHBT_PHY_8244,
160 CHBT_PHY_DUMMY
120}; 161};
121 162
122enum { 163enum {
@@ -150,16 +191,43 @@ struct chelsio_pci_params {
150 unsigned char is_pcix; 191 unsigned char is_pcix;
151}; 192};
152 193
194struct tp_params {
195 unsigned int pm_size;
196 unsigned int cm_size;
197 unsigned int pm_rx_base;
198 unsigned int pm_tx_base;
199 unsigned int pm_rx_pg_size;
200 unsigned int pm_tx_pg_size;
201 unsigned int pm_rx_num_pgs;
202 unsigned int pm_tx_num_pgs;
203 unsigned int rx_coalescing_size;
204 unsigned int use_5tuple_mode;
205};
206
207struct mc5_params {
208 unsigned int mode; /* selects MC5 width */
209 unsigned int nservers; /* size of server region */
210 unsigned int nroutes; /* size of routing region */
211};
212
213/* Default MC5 region sizes */
214#define DEFAULT_SERVER_REGION_LEN 256
215#define DEFAULT_RT_REGION_LEN 1024
216
153struct adapter_params { 217struct adapter_params {
154 struct sge_params sge; 218 struct sge_params sge;
219 struct mc5_params mc5;
220 struct tp_params tp;
155 struct chelsio_pci_params pci; 221 struct chelsio_pci_params pci;
156 222
157 const struct board_info *brd_info; 223 const struct board_info *brd_info;
158 224
225 unsigned short mtus[NMTUS];
159 unsigned int nports; /* # of ethernet ports */ 226 unsigned int nports; /* # of ethernet ports */
160 unsigned int stats_update_period; 227 unsigned int stats_update_period;
161 unsigned short chip_revision; 228 unsigned short chip_revision;
162 unsigned char chip_version; 229 unsigned char chip_version;
230 unsigned char is_asic;
163}; 231};
164 232
165struct link_config { 233struct link_config {
@@ -207,6 +275,7 @@ struct adapter {
207 /* Terminator modules. */ 275 /* Terminator modules. */
208 struct sge *sge; 276 struct sge *sge;
209 struct peespi *espi; 277 struct peespi *espi;
278 struct petp *tp;
210 279
211 struct port_info port[MAX_NPORTS]; 280 struct port_info port[MAX_NPORTS];
212 struct work_struct stats_update_task; 281 struct work_struct stats_update_task;
@@ -217,6 +286,7 @@ struct adapter {
217 /* guards async operations */ 286 /* guards async operations */
218 spinlock_t async_lock ____cacheline_aligned; 287 spinlock_t async_lock ____cacheline_aligned;
219 u32 slow_intr_mask; 288 u32 slow_intr_mask;
289 int t1powersave;
220}; 290};
221 291
222enum { /* adapter flags */ 292enum { /* adapter flags */
@@ -255,6 +325,11 @@ struct board_info {
255 const char *desc; 325 const char *desc;
256}; 326};
257 327
328static inline int t1_is_asic(const adapter_t *adapter)
329{
330 return adapter->params.is_asic;
331}
332
258extern struct pci_device_id t1_pci_tbl[]; 333extern struct pci_device_id t1_pci_tbl[];
259 334
260static inline int adapter_matches_type(const adapter_t *adapter, 335static inline int adapter_matches_type(const adapter_t *adapter,
@@ -284,13 +359,15 @@ static inline unsigned int core_ticks_per_usec(const adapter_t *adap)
284 return board_info(adap)->clock_core / 1000000; 359 return board_info(adap)->clock_core / 1000000;
285} 360}
286 361
362extern int __t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp);
363extern int __t1_tpi_write(adapter_t *adapter, u32 addr, u32 value);
287extern int t1_tpi_write(adapter_t *adapter, u32 addr, u32 value); 364extern int t1_tpi_write(adapter_t *adapter, u32 addr, u32 value);
288extern int t1_tpi_read(adapter_t *adapter, u32 addr, u32 *value); 365extern int t1_tpi_read(adapter_t *adapter, u32 addr, u32 *value);
289 366
290extern void t1_interrupts_enable(adapter_t *adapter); 367extern void t1_interrupts_enable(adapter_t *adapter);
291extern void t1_interrupts_disable(adapter_t *adapter); 368extern void t1_interrupts_disable(adapter_t *adapter);
292extern void t1_interrupts_clear(adapter_t *adapter); 369extern void t1_interrupts_clear(adapter_t *adapter);
293extern int elmer0_ext_intr_handler(adapter_t *adapter); 370extern int t1_elmer0_ext_intr_handler(adapter_t *adapter);
294extern int t1_slow_intr_handler(adapter_t *adapter); 371extern int t1_slow_intr_handler(adapter_t *adapter);
295 372
296extern int t1_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc); 373extern int t1_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc);
@@ -304,9 +381,7 @@ extern int t1_init_hw_modules(adapter_t *adapter);
304extern int t1_init_sw_modules(adapter_t *adapter, const struct board_info *bi); 381extern int t1_init_sw_modules(adapter_t *adapter, const struct board_info *bi);
305extern void t1_free_sw_modules(adapter_t *adapter); 382extern void t1_free_sw_modules(adapter_t *adapter);
306extern void t1_fatal_err(adapter_t *adapter); 383extern void t1_fatal_err(adapter_t *adapter);
307 384extern void t1_link_changed(adapter_t *adapter, int port_id);
308extern void t1_tp_set_udp_checksum_offload(adapter_t *adapter, int enable); 385extern void t1_link_negotiated(adapter_t *adapter, int port_id, int link_stat,
309extern void t1_tp_set_tcp_checksum_offload(adapter_t *adapter, int enable); 386 int speed, int duplex, int pause);
310extern void t1_tp_set_ip_checksum_offload(adapter_t *adapter, int enable);
311
312#endif /* _CXGB_COMMON_H_ */ 387#endif /* _CXGB_COMMON_H_ */
diff --git a/drivers/net/chelsio/cphy.h b/drivers/net/chelsio/cphy.h
index 3412342f7345..60901f25014e 100644
--- a/drivers/net/chelsio/cphy.h
+++ b/drivers/net/chelsio/cphy.h
@@ -52,7 +52,14 @@ struct mdio_ops {
52/* PHY interrupt types */ 52/* PHY interrupt types */
53enum { 53enum {
54 cphy_cause_link_change = 0x1, 54 cphy_cause_link_change = 0x1,
55 cphy_cause_error = 0x2 55 cphy_cause_error = 0x2,
56 cphy_cause_fifo_error = 0x3
57};
58
59enum {
60 PHY_LINK_UP = 0x1,
61 PHY_AUTONEG_RDY = 0x2,
62 PHY_AUTONEG_EN = 0x4
56}; 63};
57 64
58struct cphy; 65struct cphy;
@@ -81,7 +88,18 @@ struct cphy_ops {
81/* A PHY instance */ 88/* A PHY instance */
82struct cphy { 89struct cphy {
83 int addr; /* PHY address */ 90 int addr; /* PHY address */
91 int state; /* Link status state machine */
84 adapter_t *adapter; /* associated adapter */ 92 adapter_t *adapter; /* associated adapter */
93
94 struct work_struct phy_update;
95
96 u16 bmsr;
97 int count;
98 int act_count;
99 int act_on;
100
101 u32 elmer_gpo;
102
85 struct cphy_ops *ops; /* PHY operations */ 103 struct cphy_ops *ops; /* PHY operations */
86 int (*mdio_read)(adapter_t *adapter, int phy_addr, int mmd_addr, 104 int (*mdio_read)(adapter_t *adapter, int phy_addr, int mmd_addr,
87 int reg_addr, unsigned int *val); 105 int reg_addr, unsigned int *val);
@@ -142,6 +160,10 @@ struct gphy {
142 int (*reset)(adapter_t *adapter); 160 int (*reset)(adapter_t *adapter);
143}; 161};
144 162
163extern struct gphy t1_my3126_ops;
164extern struct gphy t1_mv88e1xxx_ops;
165extern struct gphy t1_vsc8244_ops;
166extern struct gphy t1_xpak_ops;
145extern struct gphy t1_mv88x201x_ops; 167extern struct gphy t1_mv88x201x_ops;
146extern struct gphy t1_dummy_phy_ops; 168extern struct gphy t1_dummy_phy_ops;
147 169
diff --git a/drivers/net/chelsio/cpl5_cmd.h b/drivers/net/chelsio/cpl5_cmd.h
index 5b357d9e88d6..35f565be4fd3 100644
--- a/drivers/net/chelsio/cpl5_cmd.h
+++ b/drivers/net/chelsio/cpl5_cmd.h
@@ -46,24 +46,385 @@
46#endif 46#endif
47 47
48enum CPL_opcode { 48enum CPL_opcode {
49 CPL_PASS_OPEN_REQ = 0x1,
50 CPL_PASS_OPEN_RPL = 0x2,
51 CPL_PASS_ESTABLISH = 0x3,
52 CPL_PASS_ACCEPT_REQ = 0xE,
53 CPL_PASS_ACCEPT_RPL = 0x4,
54 CPL_ACT_OPEN_REQ = 0x5,
55 CPL_ACT_OPEN_RPL = 0x6,
56 CPL_CLOSE_CON_REQ = 0x7,
57 CPL_CLOSE_CON_RPL = 0x8,
58 CPL_CLOSE_LISTSRV_REQ = 0x9,
59 CPL_CLOSE_LISTSRV_RPL = 0xA,
60 CPL_ABORT_REQ = 0xB,
61 CPL_ABORT_RPL = 0xC,
62 CPL_PEER_CLOSE = 0xD,
63 CPL_ACT_ESTABLISH = 0x17,
64
65 CPL_GET_TCB = 0x24,
66 CPL_GET_TCB_RPL = 0x25,
67 CPL_SET_TCB = 0x26,
68 CPL_SET_TCB_FIELD = 0x27,
69 CPL_SET_TCB_RPL = 0x28,
70 CPL_PCMD = 0x29,
71
72 CPL_PCMD_READ = 0x31,
73 CPL_PCMD_READ_RPL = 0x32,
74
75
76 CPL_RX_DATA = 0xA0,
77 CPL_RX_DATA_DDP = 0xA1,
78 CPL_RX_DATA_ACK = 0xA3,
49 CPL_RX_PKT = 0xAD, 79 CPL_RX_PKT = 0xAD,
80 CPL_RX_ISCSI_HDR = 0xAF,
81 CPL_TX_DATA_ACK = 0xB0,
82 CPL_TX_DATA = 0xB1,
50 CPL_TX_PKT = 0xB2, 83 CPL_TX_PKT = 0xB2,
51 CPL_TX_PKT_LSO = 0xB6, 84 CPL_TX_PKT_LSO = 0xB6,
85
86 CPL_RTE_DELETE_REQ = 0xC0,
87 CPL_RTE_DELETE_RPL = 0xC1,
88 CPL_RTE_WRITE_REQ = 0xC2,
89 CPL_RTE_WRITE_RPL = 0xD3,
90 CPL_RTE_READ_REQ = 0xC3,
91 CPL_RTE_READ_RPL = 0xC4,
92 CPL_L2T_WRITE_REQ = 0xC5,
93 CPL_L2T_WRITE_RPL = 0xD4,
94 CPL_L2T_READ_REQ = 0xC6,
95 CPL_L2T_READ_RPL = 0xC7,
96 CPL_SMT_WRITE_REQ = 0xC8,
97 CPL_SMT_WRITE_RPL = 0xD5,
98 CPL_SMT_READ_REQ = 0xC9,
99 CPL_SMT_READ_RPL = 0xCA,
100 CPL_ARP_MISS_REQ = 0xCD,
101 CPL_ARP_MISS_RPL = 0xCE,
102 CPL_MIGRATE_C2T_REQ = 0xDC,
103 CPL_MIGRATE_C2T_RPL = 0xDD,
104 CPL_ERROR = 0xD7,
105
106 /* internal: driver -> TOM */
107 CPL_MSS_CHANGE = 0xE1
52}; 108};
53 109
54enum { /* TX_PKT_LSO ethernet types */ 110#define NUM_CPL_CMDS 256
111
112enum CPL_error {
113 CPL_ERR_NONE = 0,
114 CPL_ERR_TCAM_PARITY = 1,
115 CPL_ERR_TCAM_FULL = 3,
116 CPL_ERR_CONN_RESET = 20,
117 CPL_ERR_CONN_EXIST = 22,
118 CPL_ERR_ARP_MISS = 23,
119 CPL_ERR_BAD_SYN = 24,
120 CPL_ERR_CONN_TIMEDOUT = 30,
121 CPL_ERR_XMIT_TIMEDOUT = 31,
122 CPL_ERR_PERSIST_TIMEDOUT = 32,
123 CPL_ERR_FINWAIT2_TIMEDOUT = 33,
124 CPL_ERR_KEEPALIVE_TIMEDOUT = 34,
125 CPL_ERR_ABORT_FAILED = 42,
126 CPL_ERR_GENERAL = 99
127};
128
129enum {
130 CPL_CONN_POLICY_AUTO = 0,
131 CPL_CONN_POLICY_ASK = 1,
132 CPL_CONN_POLICY_DENY = 3
133};
134
135enum {
136 ULP_MODE_NONE = 0,
137 ULP_MODE_TCPDDP = 1,
138 ULP_MODE_ISCSI = 2,
139 ULP_MODE_IWARP = 3,
140 ULP_MODE_SSL = 4
141};
142
143enum {
144 CPL_PASS_OPEN_ACCEPT,
145 CPL_PASS_OPEN_REJECT
146};
147
148enum {
149 CPL_ABORT_SEND_RST = 0,
150 CPL_ABORT_NO_RST,
151 CPL_ABORT_POST_CLOSE_REQ = 2
152};
153
154enum { // TX_PKT_LSO ethernet types
55 CPL_ETH_II, 155 CPL_ETH_II,
56 CPL_ETH_II_VLAN, 156 CPL_ETH_II_VLAN,
57 CPL_ETH_802_3, 157 CPL_ETH_802_3,
58 CPL_ETH_802_3_VLAN 158 CPL_ETH_802_3_VLAN
59}; 159};
60 160
61struct cpl_rx_data { 161union opcode_tid {
162 u32 opcode_tid;
163 u8 opcode;
164};
165
166#define S_OPCODE 24
167#define V_OPCODE(x) ((x) << S_OPCODE)
168#define G_OPCODE(x) (((x) >> S_OPCODE) & 0xFF)
169#define G_TID(x) ((x) & 0xFFFFFF)
170
171/* tid is assumed to be 24-bits */
172#define MK_OPCODE_TID(opcode, tid) (V_OPCODE(opcode) | (tid))
173
174#define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)
175
176/* extract the TID from a CPL command */
177#define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd))))
178
179struct tcp_options {
180 u16 mss;
181 u8 wsf;
182#if defined(__LITTLE_ENDIAN_BITFIELD)
183 u8 rsvd:4;
184 u8 ecn:1;
185 u8 sack:1;
186 u8 tstamp:1;
187#else
188 u8 tstamp:1;
189 u8 sack:1;
190 u8 ecn:1;
191 u8 rsvd:4;
192#endif
193};
194
195struct cpl_pass_open_req {
196 union opcode_tid ot;
197 u16 local_port;
198 u16 peer_port;
199 u32 local_ip;
200 u32 peer_ip;
201 u32 opt0h;
202 u32 opt0l;
203 u32 peer_netmask;
204 u32 opt1;
205};
206
207struct cpl_pass_open_rpl {
208 union opcode_tid ot;
209 u16 local_port;
210 u16 peer_port;
211 u32 local_ip;
212 u32 peer_ip;
213 u8 resvd[7];
214 u8 status;
215};
216
217struct cpl_pass_establish {
218 union opcode_tid ot;
219 u16 local_port;
220 u16 peer_port;
221 u32 local_ip;
222 u32 peer_ip;
223 u32 tos_tid;
224 u8 l2t_idx;
225 u8 rsvd[3];
226 u32 snd_isn;
227 u32 rcv_isn;
228};
229
230struct cpl_pass_accept_req {
231 union opcode_tid ot;
232 u16 local_port;
233 u16 peer_port;
234 u32 local_ip;
235 u32 peer_ip;
236 u32 tos_tid;
237 struct tcp_options tcp_options;
238 u8 dst_mac[6];
239 u16 vlan_tag;
240 u8 src_mac[6];
241 u8 rsvd[2];
242 u32 rcv_isn;
243 u32 unknown_tcp_options;
244};
245
246struct cpl_pass_accept_rpl {
247 union opcode_tid ot;
248 u32 rsvd0;
249 u32 rsvd1;
250 u32 peer_ip;
251 u32 opt0h;
252 union {
253 u32 opt0l;
254 struct {
255 u8 rsvd[3];
256 u8 status;
257 };
258 };
259};
260
261struct cpl_act_open_req {
262 union opcode_tid ot;
263 u16 local_port;
264 u16 peer_port;
265 u32 local_ip;
266 u32 peer_ip;
267 u32 opt0h;
268 u32 opt0l;
269 u32 iff_vlantag;
270 u32 rsvd;
271};
272
273struct cpl_act_open_rpl {
274 union opcode_tid ot;
275 u16 local_port;
276 u16 peer_port;
277 u32 local_ip;
278 u32 peer_ip;
279 u32 new_tid;
280 u8 rsvd[3];
281 u8 status;
282};
283
284struct cpl_act_establish {
285 union opcode_tid ot;
286 u16 local_port;
287 u16 peer_port;
288 u32 local_ip;
289 u32 peer_ip;
290 u32 tos_tid;
291 u32 rsvd;
292 u32 snd_isn;
293 u32 rcv_isn;
294};
295
296struct cpl_get_tcb {
297 union opcode_tid ot;
298 u32 rsvd;
299};
300
301struct cpl_get_tcb_rpl {
302 union opcode_tid ot;
303 u16 len;
304 u8 rsvd;
305 u8 status;
306};
307
308struct cpl_set_tcb {
309 union opcode_tid ot;
310 u16 len;
311 u16 rsvd;
312};
313
314struct cpl_set_tcb_field {
315 union opcode_tid ot;
316 u8 rsvd[3];
317 u8 offset;
318 u32 mask;
319 u32 val;
320};
321
322struct cpl_set_tcb_rpl {
323 union opcode_tid ot;
324 u8 rsvd[3];
325 u8 status;
326};
327
328struct cpl_pcmd {
329 union opcode_tid ot;
330 u16 dlen_in;
331 u16 dlen_out;
332 u32 pcmd_parm[2];
333};
334
335struct cpl_pcmd_read {
336 union opcode_tid ot;
337 u32 rsvd1;
338 u16 rsvd2;
339 u32 addr;
340 u16 len;
341};
342
343struct cpl_pcmd_read_rpl {
344 union opcode_tid ot;
345 u16 len;
346};
347
348struct cpl_close_con_req {
349 union opcode_tid ot;
350 u32 rsvd;
351};
352
353struct cpl_close_con_rpl {
354 union opcode_tid ot;
355 u8 rsvd[3];
356 u8 status;
357 u32 snd_nxt;
358 u32 rcv_nxt;
359};
360
361struct cpl_close_listserv_req {
362 union opcode_tid ot;
363 u32 rsvd;
364};
365
366struct cpl_close_listserv_rpl {
367 union opcode_tid ot;
368 u8 rsvd[3];
369 u8 status;
370};
371
372struct cpl_abort_req {
373 union opcode_tid ot;
62 u32 rsvd0; 374 u32 rsvd0;
375 u8 rsvd1;
376 u8 cmd;
377 u8 rsvd2[6];
378};
379
380struct cpl_abort_rpl {
381 union opcode_tid ot;
382 u32 rsvd0;
383 u8 rsvd1;
384 u8 status;
385 u8 rsvd2[6];
386};
387
388struct cpl_peer_close {
389 union opcode_tid ot;
390 u32 rsvd;
391};
392
393struct cpl_tx_data {
394 union opcode_tid ot;
395 u32 len;
396 u32 rsvd0;
397 u16 urg;
398 u16 flags;
399};
400
401struct cpl_tx_data_ack {
402 union opcode_tid ot;
403 u32 ack_seq;
404};
405
406struct cpl_rx_data {
407 union opcode_tid ot;
63 u32 len; 408 u32 len;
64 u32 seq; 409 u32 seq;
65 u16 urg; 410 u16 urg;
66 u8 rsvd1; 411 u8 rsvd;
412 u8 status;
413};
414
415struct cpl_rx_data_ack {
416 union opcode_tid ot;
417 u32 credit;
418};
419
420struct cpl_rx_data_ddp {
421 union opcode_tid ot;
422 u32 len;
423 u32 seq;
424 u32 nxt_seq;
425 u32 ulp_crc;
426 u16 ddp_status;
427 u8 rsvd;
67 u8 status; 428 u8 status;
68}; 429};
69 430
@@ -99,9 +460,9 @@ struct cpl_tx_pkt_lso {
99 u8 ip_csum_dis:1; 460 u8 ip_csum_dis:1;
100 u8 l4_csum_dis:1; 461 u8 l4_csum_dis:1;
101 u8 vlan_valid:1; 462 u8 vlan_valid:1;
102 u8 rsvd:1; 463 u8 :1;
103#else 464#else
104 u8 rsvd:1; 465 u8 :1;
105 u8 vlan_valid:1; 466 u8 vlan_valid:1;
106 u8 l4_csum_dis:1; 467 u8 l4_csum_dis:1;
107 u8 ip_csum_dis:1; 468 u8 ip_csum_dis:1;
@@ -110,8 +471,7 @@ struct cpl_tx_pkt_lso {
110 u16 vlan; 471 u16 vlan;
111 __be32 len; 472 __be32 len;
112 473
113 u32 rsvd2; 474 u8 rsvd[5];
114 u8 rsvd3;
115#if defined(__LITTLE_ENDIAN_BITFIELD) 475#if defined(__LITTLE_ENDIAN_BITFIELD)
116 u8 tcp_hdr_words:4; 476 u8 tcp_hdr_words:4;
117 u8 ip_hdr_words:4; 477 u8 ip_hdr_words:4;
@@ -138,8 +498,142 @@ struct cpl_rx_pkt {
138 u8 iff:4; 498 u8 iff:4;
139#endif 499#endif
140 u16 csum; 500 u16 csum;
141 __be16 vlan; 501 u16 vlan;
142 u16 len; 502 u16 len;
143}; 503};
144 504
505struct cpl_l2t_write_req {
506 union opcode_tid ot;
507 u32 params;
508 u8 rsvd1[2];
509 u8 dst_mac[6];
510};
511
512struct cpl_l2t_write_rpl {
513 union opcode_tid ot;
514 u8 status;
515 u8 rsvd[3];
516};
517
518struct cpl_l2t_read_req {
519 union opcode_tid ot;
520 u8 rsvd[3];
521 u8 l2t_idx;
522};
523
524struct cpl_l2t_read_rpl {
525 union opcode_tid ot;
526 u32 params;
527 u8 rsvd1[2];
528 u8 dst_mac[6];
529};
530
531struct cpl_smt_write_req {
532 union opcode_tid ot;
533 u8 rsvd0;
534#if defined(__LITTLE_ENDIAN_BITFIELD)
535 u8 rsvd1:1;
536 u8 mtu_idx:3;
537 u8 iff:4;
538#else
539 u8 iff:4;
540 u8 mtu_idx:3;
541 u8 rsvd1:1;
542#endif
543 u16 rsvd2;
544 u16 rsvd3;
545 u8 src_mac1[6];
546 u16 rsvd4;
547 u8 src_mac0[6];
548};
549
550struct cpl_smt_write_rpl {
551 union opcode_tid ot;
552 u8 status;
553 u8 rsvd[3];
554};
555
556struct cpl_smt_read_req {
557 union opcode_tid ot;
558 u8 rsvd0;
559#if defined(__LITTLE_ENDIAN_BITFIELD)
560 u8 rsvd1:4;
561 u8 iff:4;
562#else
563 u8 iff:4;
564 u8 rsvd1:4;
565#endif
566 u16 rsvd2;
567};
568
569struct cpl_smt_read_rpl {
570 union opcode_tid ot;
571 u8 status;
572#if defined(__LITTLE_ENDIAN_BITFIELD)
573 u8 rsvd1:1;
574 u8 mtu_idx:3;
575 u8 rsvd0:4;
576#else
577 u8 rsvd0:4;
578 u8 mtu_idx:3;
579 u8 rsvd1:1;
580#endif
581 u16 rsvd2;
582 u16 rsvd3;
583 u8 src_mac1[6];
584 u16 rsvd4;
585 u8 src_mac0[6];
586};
587
588struct cpl_rte_delete_req {
589 union opcode_tid ot;
590 u32 params;
591};
592
593struct cpl_rte_delete_rpl {
594 union opcode_tid ot;
595 u8 status;
596 u8 rsvd[3];
597};
598
599struct cpl_rte_write_req {
600 union opcode_tid ot;
601 u32 params;
602 u32 netmask;
603 u32 faddr;
604};
605
606struct cpl_rte_write_rpl {
607 union opcode_tid ot;
608 u8 status;
609 u8 rsvd[3];
610};
611
612struct cpl_rte_read_req {
613 union opcode_tid ot;
614 u32 params;
615};
616
617struct cpl_rte_read_rpl {
618 union opcode_tid ot;
619 u8 status;
620 u8 rsvd0[2];
621 u8 l2t_idx;
622#if defined(__LITTLE_ENDIAN_BITFIELD)
623 u8 rsvd1:7;
624 u8 select:1;
625#else
626 u8 select:1;
627 u8 rsvd1:7;
628#endif
629 u8 rsvd2[3];
630 u32 addr;
631};
632
633struct cpl_mss_change {
634 union opcode_tid ot;
635 u32 mss;
636};
637
145#endif /* _CXGB_CPL5_CMD_H_ */ 638#endif /* _CXGB_CPL5_CMD_H_ */
639
diff --git a/drivers/net/chelsio/cxgb2.c b/drivers/net/chelsio/cxgb2.c
index 42ad9cfd670a..a8c873b0af54 100644
--- a/drivers/net/chelsio/cxgb2.c
+++ b/drivers/net/chelsio/cxgb2.c
@@ -53,7 +53,9 @@
53#include "gmac.h" 53#include "gmac.h"
54#include "cphy.h" 54#include "cphy.h"
55#include "sge.h" 55#include "sge.h"
56#include "tp.h"
56#include "espi.h" 57#include "espi.h"
58#include "elmer0.h"
57 59
58#include <linux/workqueue.h> 60#include <linux/workqueue.h>
59 61
@@ -73,10 +75,9 @@ static inline void cancel_mac_stats_update(struct adapter *ap)
73#define MAX_RX_JUMBO_BUFFERS 16384 75#define MAX_RX_JUMBO_BUFFERS 16384
74#define MAX_TX_BUFFERS_HIGH 16384U 76#define MAX_TX_BUFFERS_HIGH 16384U
75#define MAX_TX_BUFFERS_LOW 1536U 77#define MAX_TX_BUFFERS_LOW 1536U
78#define MAX_TX_BUFFERS 1460U
76#define MIN_FL_ENTRIES 32 79#define MIN_FL_ENTRIES 32
77 80
78#define PORT_MASK ((1 << MAX_NPORTS) - 1)
79
80#define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \ 81#define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
81 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\ 82 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
82 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR) 83 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
@@ -94,8 +95,17 @@ MODULE_LICENSE("GPL");
94static int dflt_msg_enable = DFLT_MSG_ENABLE; 95static int dflt_msg_enable = DFLT_MSG_ENABLE;
95 96
96module_param(dflt_msg_enable, int, 0); 97module_param(dflt_msg_enable, int, 0);
97MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T1 message enable bitmap"); 98MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T1 default message enable bitmap");
99
100#define HCLOCK 0x0
101#define LCLOCK 0x1
102
103/* T1 cards powersave mode */
104static int t1_clock(struct adapter *adapter, int mode);
105static int t1powersave = 1; /* HW default is powersave mode. */
98 106
107module_param(t1powersave, int, 0);
108MODULE_PARM_DESC(t1powersave, "Enable/Disable T1 powersaving mode");
99 109
100static const char pci_speed[][4] = { 110static const char pci_speed[][4] = {
101 "33", "66", "100", "133" 111 "33", "66", "100", "133"
@@ -135,7 +145,7 @@ static void link_report(struct port_info *p)
135 } 145 }
136} 146}
137 147
138void t1_link_changed(struct adapter *adapter, int port_id, int link_stat, 148void t1_link_negotiated(struct adapter *adapter, int port_id, int link_stat,
139 int speed, int duplex, int pause) 149 int speed, int duplex, int pause)
140{ 150{
141 struct port_info *p = &adapter->port[port_id]; 151 struct port_info *p = &adapter->port[port_id];
@@ -147,6 +157,22 @@ void t1_link_changed(struct adapter *adapter, int port_id, int link_stat,
147 netif_carrier_off(p->dev); 157 netif_carrier_off(p->dev);
148 link_report(p); 158 link_report(p);
149 159
160 /* multi-ports: inform toe */
161 if ((speed > 0) && (adapter->params.nports > 1)) {
162 unsigned int sched_speed = 10;
163 switch (speed) {
164 case SPEED_1000:
165 sched_speed = 1000;
166 break;
167 case SPEED_100:
168 sched_speed = 100;
169 break;
170 case SPEED_10:
171 sched_speed = 10;
172 break;
173 }
174 t1_sched_update_parms(adapter->sge, port_id, 0, sched_speed);
175 }
150 } 176 }
151} 177}
152 178
@@ -165,8 +191,10 @@ static void link_start(struct port_info *p)
165static void enable_hw_csum(struct adapter *adapter) 191static void enable_hw_csum(struct adapter *adapter)
166{ 192{
167 if (adapter->flags & TSO_CAPABLE) 193 if (adapter->flags & TSO_CAPABLE)
168 t1_tp_set_ip_checksum_offload(adapter, 1); /* for TSO only */ 194 t1_tp_set_ip_checksum_offload(adapter->tp, 1); /* for TSO only */
169 t1_tp_set_tcp_checksum_offload(adapter, 1); 195 if (adapter->flags & UDP_CSUM_CAPABLE)
196 t1_tp_set_udp_checksum_offload(adapter->tp, 1);
197 t1_tp_set_tcp_checksum_offload(adapter->tp, 1);
170} 198}
171 199
172/* 200/*
@@ -468,6 +496,18 @@ static void get_stats(struct net_device *dev, struct ethtool_stats *stats,
468 *data++ = (u64)t->tx_reg_pkts; 496 *data++ = (u64)t->tx_reg_pkts;
469 *data++ = (u64)t->tx_lso_pkts; 497 *data++ = (u64)t->tx_lso_pkts;
470 *data++ = (u64)t->tx_do_cksum; 498 *data++ = (u64)t->tx_do_cksum;
499
500 if (adapter->espi) {
501 const struct espi_intr_counts *e;
502
503 e = t1_espi_get_intr_counts(adapter->espi);
504 *data++ = (u64) e->DIP2_parity_err;
505 *data++ = (u64) e->DIP4_err;
506 *data++ = (u64) e->rx_drops;
507 *data++ = (u64) e->tx_drops;
508 *data++ = (u64) e->rx_ovflw;
509 *data++ = (u64) e->parity_err;
510 }
471} 511}
472 512
473static inline void reg_block_dump(struct adapter *ap, void *buf, 513static inline void reg_block_dump(struct adapter *ap, void *buf,
@@ -491,6 +531,15 @@ static void get_regs(struct net_device *dev, struct ethtool_regs *regs,
491 531
492 memset(buf, 0, T2_REGMAP_SIZE); 532 memset(buf, 0, T2_REGMAP_SIZE);
493 reg_block_dump(ap, buf, 0, A_SG_RESPACCUTIMER); 533 reg_block_dump(ap, buf, 0, A_SG_RESPACCUTIMER);
534 reg_block_dump(ap, buf, A_MC3_CFG, A_MC4_INT_CAUSE);
535 reg_block_dump(ap, buf, A_TPI_ADDR, A_TPI_PAR);
536 reg_block_dump(ap, buf, A_TP_IN_CONFIG, A_TP_TX_DROP_COUNT);
537 reg_block_dump(ap, buf, A_RAT_ROUTE_CONTROL, A_RAT_INTR_CAUSE);
538 reg_block_dump(ap, buf, A_CSPI_RX_AE_WM, A_CSPI_INTR_ENABLE);
539 reg_block_dump(ap, buf, A_ESPI_SCH_TOKEN0, A_ESPI_GOSTAT);
540 reg_block_dump(ap, buf, A_ULP_ULIMIT, A_ULP_PIO_CTRL);
541 reg_block_dump(ap, buf, A_PL_ENABLE, A_PL_CAUSE);
542 reg_block_dump(ap, buf, A_MC5_CONFIG, A_MC5_MASK_WRITE_CMD);
494} 543}
495 544
496static int get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 545static int get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
@@ -729,7 +778,9 @@ static int get_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
729 778
730static int get_eeprom_len(struct net_device *dev) 779static int get_eeprom_len(struct net_device *dev)
731{ 780{
732 return EEPROM_SIZE; 781 struct adapter *adapter = dev->priv;
782
783 return t1_is_asic(adapter) ? EEPROM_SIZE : 0;
733} 784}
734 785
735#define EEPROM_MAGIC(ap) \ 786#define EEPROM_MAGIC(ap) \
@@ -914,7 +965,7 @@ static void ext_intr_task(void *data)
914{ 965{
915 struct adapter *adapter = data; 966 struct adapter *adapter = data;
916 967
917 elmer0_ext_intr_handler(adapter); 968 t1_elmer0_ext_intr_handler(adapter);
918 969
919 /* Now reenable external interrupts */ 970 /* Now reenable external interrupts */
920 spin_lock_irq(&adapter->async_lock); 971 spin_lock_irq(&adapter->async_lock);
@@ -1074,16 +1125,19 @@ static int __devinit init_one(struct pci_dev *pdev,
1074 netdev->vlan_rx_register = vlan_rx_register; 1125 netdev->vlan_rx_register = vlan_rx_register;
1075 netdev->vlan_rx_kill_vid = vlan_rx_kill_vid; 1126 netdev->vlan_rx_kill_vid = vlan_rx_kill_vid;
1076#endif 1127#endif
1077 adapter->flags |= TSO_CAPABLE; 1128
1078 netdev->features |= NETIF_F_TSO; 1129 /* T204: disable TSO */
1130 if (!(is_T2(adapter)) || bi->port_number != 4) {
1131 adapter->flags |= TSO_CAPABLE;
1132 netdev->features |= NETIF_F_TSO;
1133 }
1079 } 1134 }
1080 1135
1081 netdev->open = cxgb_open; 1136 netdev->open = cxgb_open;
1082 netdev->stop = cxgb_close; 1137 netdev->stop = cxgb_close;
1083 netdev->hard_start_xmit = t1_start_xmit; 1138 netdev->hard_start_xmit = t1_start_xmit;
1084 netdev->hard_header_len += (adapter->flags & TSO_CAPABLE) ? 1139 netdev->hard_header_len += (adapter->flags & TSO_CAPABLE) ?
1085 sizeof(struct cpl_tx_pkt_lso) : 1140 sizeof(struct cpl_tx_pkt_lso) : sizeof(struct cpl_tx_pkt);
1086 sizeof(struct cpl_tx_pkt);
1087 netdev->get_stats = t1_get_stats; 1141 netdev->get_stats = t1_get_stats;
1088 netdev->set_multicast_list = t1_set_rxmode; 1142 netdev->set_multicast_list = t1_set_rxmode;
1089 netdev->do_ioctl = t1_ioctl; 1143 netdev->do_ioctl = t1_ioctl;
@@ -1134,6 +1188,17 @@ static int __devinit init_one(struct pci_dev *pdev,
1134 bi->desc, adapter->params.chip_revision, 1188 bi->desc, adapter->params.chip_revision,
1135 adapter->params.pci.is_pcix ? "PCIX" : "PCI", 1189 adapter->params.pci.is_pcix ? "PCIX" : "PCI",
1136 adapter->params.pci.speed, adapter->params.pci.width); 1190 adapter->params.pci.speed, adapter->params.pci.width);
1191
1192 /*
1193 * Set the T1B ASIC and memory clocks.
1194 */
1195 if (t1powersave)
1196 adapter->t1powersave = LCLOCK; /* HW default is powersave mode. */
1197 else
1198 adapter->t1powersave = HCLOCK;
1199 if (t1_is_T1B(adapter))
1200 t1_clock(adapter, t1powersave);
1201
1137 return 0; 1202 return 0;
1138 1203
1139 out_release_adapter_res: 1204 out_release_adapter_res:
@@ -1153,6 +1218,155 @@ static int __devinit init_one(struct pci_dev *pdev,
1153 return err; 1218 return err;
1154} 1219}
1155 1220
1221static void bit_bang(struct adapter *adapter, int bitdata, int nbits)
1222{
1223 int data;
1224 int i;
1225 u32 val;
1226
1227 enum {
1228 S_CLOCK = 1 << 3,
1229 S_DATA = 1 << 4
1230 };
1231
1232 for (i = (nbits - 1); i > -1; i--) {
1233
1234 udelay(50);
1235
1236 data = ((bitdata >> i) & 0x1);
1237 __t1_tpi_read(adapter, A_ELMER0_GPO, &val);
1238
1239 if (data)
1240 val |= S_DATA;
1241 else
1242 val &= ~S_DATA;
1243
1244 udelay(50);
1245
1246 /* Set SCLOCK low */
1247 val &= ~S_CLOCK;
1248 __t1_tpi_write(adapter, A_ELMER0_GPO, val);
1249
1250 udelay(50);
1251
1252 /* Write SCLOCK high */
1253 val |= S_CLOCK;
1254 __t1_tpi_write(adapter, A_ELMER0_GPO, val);
1255
1256 }
1257}
1258
1259static int t1_clock(struct adapter *adapter, int mode)
1260{
1261 u32 val;
1262 int M_CORE_VAL;
1263 int M_MEM_VAL;
1264
1265 enum {
1266 M_CORE_BITS = 9,
1267 T_CORE_VAL = 0,
1268 T_CORE_BITS = 2,
1269 N_CORE_VAL = 0,
1270 N_CORE_BITS = 2,
1271 M_MEM_BITS = 9,
1272 T_MEM_VAL = 0,
1273 T_MEM_BITS = 2,
1274 N_MEM_VAL = 0,
1275 N_MEM_BITS = 2,
1276 NP_LOAD = 1 << 17,
1277 S_LOAD_MEM = 1 << 5,
1278 S_LOAD_CORE = 1 << 6,
1279 S_CLOCK = 1 << 3
1280 };
1281
1282 if (!t1_is_T1B(adapter))
1283 return -ENODEV; /* Can't re-clock this chip. */
1284
1285 if (mode & 2) {
1286 return 0; /* show current mode. */
1287 }
1288
1289 if ((adapter->t1powersave & 1) == (mode & 1))
1290 return -EALREADY; /* ASIC already running in mode. */
1291
1292 if ((mode & 1) == HCLOCK) {
1293 M_CORE_VAL = 0x14;
1294 M_MEM_VAL = 0x18;
1295 adapter->t1powersave = HCLOCK; /* overclock */
1296 } else {
1297 M_CORE_VAL = 0xe;
1298 M_MEM_VAL = 0x10;
1299 adapter->t1powersave = LCLOCK; /* underclock */
1300 }
1301
1302 /* Don't interrupt this serial stream! */
1303 spin_lock(&adapter->tpi_lock);
1304
1305 /* Initialize for ASIC core */
1306 __t1_tpi_read(adapter, A_ELMER0_GPO, &val);
1307 val |= NP_LOAD;
1308 udelay(50);
1309 __t1_tpi_write(adapter, A_ELMER0_GPO, val);
1310 udelay(50);
1311 __t1_tpi_read(adapter, A_ELMER0_GPO, &val);
1312 val &= ~S_LOAD_CORE;
1313 val &= ~S_CLOCK;
1314 __t1_tpi_write(adapter, A_ELMER0_GPO, val);
1315 udelay(50);
1316
1317 /* Serial program the ASIC clock synthesizer */
1318 bit_bang(adapter, T_CORE_VAL, T_CORE_BITS);
1319 bit_bang(adapter, N_CORE_VAL, N_CORE_BITS);
1320 bit_bang(adapter, M_CORE_VAL, M_CORE_BITS);
1321 udelay(50);
1322
1323 /* Finish ASIC core */
1324 __t1_tpi_read(adapter, A_ELMER0_GPO, &val);
1325 val |= S_LOAD_CORE;
1326 udelay(50);
1327 __t1_tpi_write(adapter, A_ELMER0_GPO, val);
1328 udelay(50);
1329 __t1_tpi_read(adapter, A_ELMER0_GPO, &val);
1330 val &= ~S_LOAD_CORE;
1331 udelay(50);
1332 __t1_tpi_write(adapter, A_ELMER0_GPO, val);
1333 udelay(50);
1334
1335 /* Initialize for memory */
1336 __t1_tpi_read(adapter, A_ELMER0_GPO, &val);
1337 val |= NP_LOAD;
1338 udelay(50);
1339 __t1_tpi_write(adapter, A_ELMER0_GPO, val);
1340 udelay(50);
1341 __t1_tpi_read(adapter, A_ELMER0_GPO, &val);
1342 val &= ~S_LOAD_MEM;
1343 val &= ~S_CLOCK;
1344 udelay(50);
1345 __t1_tpi_write(adapter, A_ELMER0_GPO, val);
1346 udelay(50);
1347
1348 /* Serial program the memory clock synthesizer */
1349 bit_bang(adapter, T_MEM_VAL, T_MEM_BITS);
1350 bit_bang(adapter, N_MEM_VAL, N_MEM_BITS);
1351 bit_bang(adapter, M_MEM_VAL, M_MEM_BITS);
1352 udelay(50);
1353
1354 /* Finish memory */
1355 __t1_tpi_read(adapter, A_ELMER0_GPO, &val);
1356 val |= S_LOAD_MEM;
1357 udelay(50);
1358 __t1_tpi_write(adapter, A_ELMER0_GPO, val);
1359 udelay(50);
1360 __t1_tpi_read(adapter, A_ELMER0_GPO, &val);
1361 val &= ~S_LOAD_MEM;
1362 udelay(50);
1363 __t1_tpi_write(adapter, A_ELMER0_GPO, val);
1364
1365 spin_unlock(&adapter->tpi_lock);
1366
1367 return 0;
1368}
1369
1156static inline void t1_sw_reset(struct pci_dev *pdev) 1370static inline void t1_sw_reset(struct pci_dev *pdev)
1157{ 1371{
1158 pci_write_config_dword(pdev, A_PCICFG_PM_CSR, 3); 1372 pci_write_config_dword(pdev, A_PCICFG_PM_CSR, 3);
diff --git a/drivers/net/chelsio/elmer0.h b/drivers/net/chelsio/elmer0.h
index 5590cb2dac19..9ebecaa97d31 100644
--- a/drivers/net/chelsio/elmer0.h
+++ b/drivers/net/chelsio/elmer0.h
@@ -39,6 +39,12 @@
39#ifndef _CXGB_ELMER0_H_ 39#ifndef _CXGB_ELMER0_H_
40#define _CXGB_ELMER0_H_ 40#define _CXGB_ELMER0_H_
41 41
42/* ELMER0 flavors */
43enum {
44 ELMER0_XC2S300E_6FT256_C,
45 ELMER0_XC2S100E_6TQ144_C
46};
47
42/* ELMER0 registers */ 48/* ELMER0 registers */
43#define A_ELMER0_VERSION 0x100000 49#define A_ELMER0_VERSION 0x100000
44#define A_ELMER0_PHY_CFG 0x100004 50#define A_ELMER0_PHY_CFG 0x100004
@@ -149,3 +155,4 @@
149#define MI1_OP_INDIRECT_READ 3 155#define MI1_OP_INDIRECT_READ 3
150 156
151#endif /* _CXGB_ELMER0_H_ */ 157#endif /* _CXGB_ELMER0_H_ */
158
diff --git a/drivers/net/chelsio/espi.c b/drivers/net/chelsio/espi.c
index 40af47b795e6..4192f0f5b3ee 100644
--- a/drivers/net/chelsio/espi.c
+++ b/drivers/net/chelsio/espi.c
@@ -81,46 +81,36 @@ static int tricn_write(adapter_t *adapter, int bundle_addr, int module_addr,
81 return busy; 81 return busy;
82} 82}
83 83
84/* 1. Deassert rx_reset_core. */
85/* 2. Program TRICN_CNFG registers. */
86/* 3. Deassert rx_reset_link */
87static int tricn_init(adapter_t *adapter) 84static int tricn_init(adapter_t *adapter)
88{ 85{
89 int i = 0; 86 int i, sme = 1;
90 int stat = 0;
91 int timeout = 0;
92 int is_ready = 0;
93 87
94 /* 1 */ 88 if (!(readl(adapter->regs + A_ESPI_RX_RESET) & F_RX_CLK_STATUS)) {
95 timeout=1000; 89 CH_ERR("%s: ESPI clock not ready\n", adapter->name);
96 do { 90 return -1;
97 stat = readl(adapter->regs + A_ESPI_RX_RESET);
98 is_ready = (stat & 0x4);
99 timeout--;
100 udelay(5);
101 } while (!is_ready || (timeout==0));
102 writel(0x2, adapter->regs + A_ESPI_RX_RESET);
103 if (timeout==0)
104 {
105 CH_ERR("ESPI : ERROR : Timeout tricn_init() \n");
106 t1_fatal_err(adapter);
107 } 91 }
108 92
109 /* 2 */ 93 writel(F_ESPI_RX_CORE_RST, adapter->regs + A_ESPI_RX_RESET);
110 tricn_write(adapter, 0, 0, 0, TRICN_CNFG, 0x81); 94
111 tricn_write(adapter, 0, 1, 0, TRICN_CNFG, 0x81); 95 if (sme) {
112 tricn_write(adapter, 0, 2, 0, TRICN_CNFG, 0x81); 96 tricn_write(adapter, 0, 0, 0, TRICN_CNFG, 0x81);
113 for (i=1; i<= 8; i++) tricn_write(adapter, 0, 0, i, TRICN_CNFG, 0xf1); 97 tricn_write(adapter, 0, 1, 0, TRICN_CNFG, 0x81);
114 for (i=1; i<= 2; i++) tricn_write(adapter, 0, 1, i, TRICN_CNFG, 0xf1); 98 tricn_write(adapter, 0, 2, 0, TRICN_CNFG, 0x81);
115 for (i=1; i<= 3; i++) tricn_write(adapter, 0, 2, i, TRICN_CNFG, 0xe1); 99 }
116 for (i=4; i<= 4; i++) tricn_write(adapter, 0, 2, i, TRICN_CNFG, 0xf1); 100 for (i = 1; i <= 8; i++)
117 for (i=5; i<= 5; i++) tricn_write(adapter, 0, 2, i, TRICN_CNFG, 0xe1); 101 tricn_write(adapter, 0, 0, i, TRICN_CNFG, 0xf1);
118 for (i=6; i<= 6; i++) tricn_write(adapter, 0, 2, i, TRICN_CNFG, 0xf1); 102 for (i = 1; i <= 2; i++)
119 for (i=7; i<= 7; i++) tricn_write(adapter, 0, 2, i, TRICN_CNFG, 0x80); 103 tricn_write(adapter, 0, 1, i, TRICN_CNFG, 0xf1);
120 for (i=8; i<= 8; i++) tricn_write(adapter, 0, 2, i, TRICN_CNFG, 0xf1); 104 for (i = 1; i <= 3; i++)
121 105 tricn_write(adapter, 0, 2, i, TRICN_CNFG, 0xe1);
122 /* 3 */ 106 tricn_write(adapter, 0, 2, 4, TRICN_CNFG, 0xf1);
123 writel(0x3, adapter->regs + A_ESPI_RX_RESET); 107 tricn_write(adapter, 0, 2, 5, TRICN_CNFG, 0xe1);
108 tricn_write(adapter, 0, 2, 6, TRICN_CNFG, 0xf1);
109 tricn_write(adapter, 0, 2, 7, TRICN_CNFG, 0x80);
110 tricn_write(adapter, 0, 2, 8, TRICN_CNFG, 0xf1);
111
112 writel(F_ESPI_RX_CORE_RST | F_ESPI_RX_LNK_RST,
113 adapter->regs + A_ESPI_RX_RESET);
124 114
125 return 0; 115 return 0;
126} 116}
@@ -143,6 +133,7 @@ void t1_espi_intr_enable(struct peespi *espi)
143 133
144void t1_espi_intr_clear(struct peespi *espi) 134void t1_espi_intr_clear(struct peespi *espi)
145{ 135{
136 readl(espi->adapter->regs + A_ESPI_DIP2_ERR_COUNT);
146 writel(0xffffffff, espi->adapter->regs + A_ESPI_INTR_STATUS); 137 writel(0xffffffff, espi->adapter->regs + A_ESPI_INTR_STATUS);
147 writel(F_PL_INTR_ESPI, espi->adapter->regs + A_PL_CAUSE); 138 writel(F_PL_INTR_ESPI, espi->adapter->regs + A_PL_CAUSE);
148} 139}
@@ -157,7 +148,6 @@ void t1_espi_intr_disable(struct peespi *espi)
157 148
158int t1_espi_intr_handler(struct peespi *espi) 149int t1_espi_intr_handler(struct peespi *espi)
159{ 150{
160 u32 cnt;
161 u32 status = readl(espi->adapter->regs + A_ESPI_INTR_STATUS); 151 u32 status = readl(espi->adapter->regs + A_ESPI_INTR_STATUS);
162 152
163 if (status & F_DIP4ERR) 153 if (status & F_DIP4ERR)
@@ -177,7 +167,7 @@ int t1_espi_intr_handler(struct peespi *espi)
177 * Must read the error count to clear the interrupt 167 * Must read the error count to clear the interrupt
178 * that it causes. 168 * that it causes.
179 */ 169 */
180 cnt = readl(espi->adapter->regs + A_ESPI_DIP2_ERR_COUNT); 170 readl(espi->adapter->regs + A_ESPI_DIP2_ERR_COUNT);
181 } 171 }
182 172
183 /* 173 /*
@@ -210,17 +200,45 @@ static void espi_setup_for_pm3393(adapter_t *adapter)
210 writel(V_RX_NPORTS(1) | V_TX_NPORTS(1), adapter->regs + A_PORT_CONFIG); 200 writel(V_RX_NPORTS(1) | V_TX_NPORTS(1), adapter->regs + A_PORT_CONFIG);
211} 201}
212 202
213/* T2 Init part -- */ 203static void espi_setup_for_vsc7321(adapter_t *adapter)
214/* 1. Set T_ESPI_MISCCTRL_ADDR */ 204{
215/* 2. Init ESPI registers. */ 205 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN0);
216/* 3. Init TriCN Hard Macro */ 206 writel(0x1f401f4, adapter->regs + A_ESPI_SCH_TOKEN1);
217int t1_espi_init(struct peespi *espi, int mac_type, int nports) 207 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN2);
208 writel(0xa00, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK);
209 writel(0x1ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK);
210 writel(1, adapter->regs + A_ESPI_CALENDAR_LENGTH);
211 writel(V_RX_NPORTS(4) | V_TX_NPORTS(4), adapter->regs + A_PORT_CONFIG);
212
213 writel(0x08000008, adapter->regs + A_ESPI_TRAIN);
214}
215
216/*
217 * Note that T1B requires at least 2 ports for IXF1010 due to a HW bug.
218 */
219static void espi_setup_for_ixf1010(adapter_t *adapter, int nports)
218{ 220{
219 u32 cnt; 221 writel(1, adapter->regs + A_ESPI_CALENDAR_LENGTH);
222 if (nports == 4) {
223 if (is_T2(adapter)) {
224 writel(0xf00, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK);
225 writel(0x3c0, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK);
226 } else {
227 writel(0x7ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK);
228 writel(0x1ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK);
229 }
230 } else {
231 writel(0x1fff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK);
232 writel(0x7ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK);
233 }
234 writel(V_RX_NPORTS(nports) | V_TX_NPORTS(nports), adapter->regs + A_PORT_CONFIG);
220 235
236}
237
238int t1_espi_init(struct peespi *espi, int mac_type, int nports)
239{
221 u32 status_enable_extra = 0; 240 u32 status_enable_extra = 0;
222 adapter_t *adapter = espi->adapter; 241 adapter_t *adapter = espi->adapter;
223 u32 status, burstval = 0x800100;
224 242
225 /* Disable ESPI training. MACs that can handle it enable it below. */ 243 /* Disable ESPI training. MACs that can handle it enable it below. */
226 writel(0, adapter->regs + A_ESPI_TRAIN); 244 writel(0, adapter->regs + A_ESPI_TRAIN);
@@ -229,38 +247,20 @@ int t1_espi_init(struct peespi *espi, int mac_type, int nports)
229 writel(V_OUT_OF_SYNC_COUNT(4) | 247 writel(V_OUT_OF_SYNC_COUNT(4) |
230 V_DIP2_PARITY_ERR_THRES(3) | 248 V_DIP2_PARITY_ERR_THRES(3) |
231 V_DIP4_THRES(1), adapter->regs + A_ESPI_MISC_CONTROL); 249 V_DIP4_THRES(1), adapter->regs + A_ESPI_MISC_CONTROL);
232 if (nports == 4) { 250 writel(nports == 4 ? 0x200040 : 0x1000080,
233 /* T204: maxburst1 = 0x40, maxburst2 = 0x20 */ 251 adapter->regs + A_ESPI_MAXBURST1_MAXBURST2);
234 burstval = 0x200040; 252 } else
235 } 253 writel(0x800100, adapter->regs + A_ESPI_MAXBURST1_MAXBURST2);
236 }
237 writel(burstval, adapter->regs + A_ESPI_MAXBURST1_MAXBURST2);
238 254
239 switch (mac_type) { 255 if (mac_type == CHBT_MAC_PM3393)
240 case CHBT_MAC_PM3393:
241 espi_setup_for_pm3393(adapter); 256 espi_setup_for_pm3393(adapter);
242 break; 257 else if (mac_type == CHBT_MAC_VSC7321)
243 default: 258 espi_setup_for_vsc7321(adapter);
259 else if (mac_type == CHBT_MAC_IXF1010) {
260 status_enable_extra = F_INTEL1010MODE;
261 espi_setup_for_ixf1010(adapter, nports);
262 } else
244 return -1; 263 return -1;
245 }
246
247 /*
248 * Make sure any pending interrupts from the SPI are
249 * Cleared before enabling the interrupt.
250 */
251 writel(ESPI_INTR_MASK, espi->adapter->regs + A_ESPI_INTR_ENABLE);
252 status = readl(espi->adapter->regs + A_ESPI_INTR_STATUS);
253 if (status & F_DIP2PARITYERR) {
254 cnt = readl(espi->adapter->regs + A_ESPI_DIP2_ERR_COUNT);
255 }
256
257 /*
258 * For T1B we need to write 1 to clear ESPI interrupts. For T2+ we
259 * write the status as is.
260 */
261 if (status && t1_is_T1B(espi->adapter))
262 status = 1;
263 writel(status, espi->adapter->regs + A_ESPI_INTR_STATUS);
264 264
265 writel(status_enable_extra | F_RXSTATUSENABLE, 265 writel(status_enable_extra | F_RXSTATUSENABLE,
266 adapter->regs + A_ESPI_FIFO_STATUS_ENABLE); 266 adapter->regs + A_ESPI_FIFO_STATUS_ENABLE);
@@ -271,9 +271,11 @@ int t1_espi_init(struct peespi *espi, int mac_type, int nports)
271 * Always position the control at the 1st port egress IN 271 * Always position the control at the 1st port egress IN
272 * (sop,eop) counter to reduce PIOs for T/N210 workaround. 272 * (sop,eop) counter to reduce PIOs for T/N210 workaround.
273 */ 273 */
274 espi->misc_ctrl = (readl(adapter->regs + A_ESPI_MISC_CONTROL) 274 espi->misc_ctrl = readl(adapter->regs + A_ESPI_MISC_CONTROL);
275 & ~MON_MASK) | (F_MONITORED_DIRECTION 275 espi->misc_ctrl &= ~MON_MASK;
276 | F_MONITORED_INTERFACE); 276 espi->misc_ctrl |= F_MONITORED_DIRECTION;
277 if (adapter->params.nports == 1)
278 espi->misc_ctrl |= F_MONITORED_INTERFACE;
277 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL); 279 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL);
278 spin_lock_init(&espi->lock); 280 spin_lock_init(&espi->lock);
279 } 281 }
@@ -299,8 +301,7 @@ void t1_espi_set_misc_ctrl(adapter_t *adapter, u32 val)
299{ 301{
300 struct peespi *espi = adapter->espi; 302 struct peespi *espi = adapter->espi;
301 303
302 if (!is_T2(adapter)) 304 if (!is_T2(adapter)) return;
303 return;
304 spin_lock(&espi->lock); 305 spin_lock(&espi->lock);
305 espi->misc_ctrl = (val & ~MON_MASK) | 306 espi->misc_ctrl = (val & ~MON_MASK) |
306 (espi->misc_ctrl & MON_MASK); 307 (espi->misc_ctrl & MON_MASK);
@@ -310,27 +311,61 @@ void t1_espi_set_misc_ctrl(adapter_t *adapter, u32 val)
310 311
311u32 t1_espi_get_mon(adapter_t *adapter, u32 addr, u8 wait) 312u32 t1_espi_get_mon(adapter_t *adapter, u32 addr, u8 wait)
312{ 313{
313 u32 sel;
314
315 struct peespi *espi = adapter->espi; 314 struct peespi *espi = adapter->espi;
315 u32 sel;
316 316
317 if (!is_T2(adapter)) 317 if (!is_T2(adapter))
318 return 0; 318 return 0;
319
319 sel = V_MONITORED_PORT_NUM((addr & 0x3c) >> 2); 320 sel = V_MONITORED_PORT_NUM((addr & 0x3c) >> 2);
320 if (!wait) { 321 if (!wait) {
321 if (!spin_trylock(&espi->lock)) 322 if (!spin_trylock(&espi->lock))
322 return 0; 323 return 0;
323 } 324 } else
324 else
325 spin_lock(&espi->lock); 325 spin_lock(&espi->lock);
326
326 if ((sel != (espi->misc_ctrl & MON_MASK))) { 327 if ((sel != (espi->misc_ctrl & MON_MASK))) {
327 writel(((espi->misc_ctrl & ~MON_MASK) | sel), 328 writel(((espi->misc_ctrl & ~MON_MASK) | sel),
328 adapter->regs + A_ESPI_MISC_CONTROL); 329 adapter->regs + A_ESPI_MISC_CONTROL);
329 sel = readl(adapter->regs + A_ESPI_SCH_TOKEN3); 330 sel = readl(adapter->regs + A_ESPI_SCH_TOKEN3);
330 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL); 331 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL);
331 } 332 } else
332 else
333 sel = readl(adapter->regs + A_ESPI_SCH_TOKEN3); 333 sel = readl(adapter->regs + A_ESPI_SCH_TOKEN3);
334 spin_unlock(&espi->lock); 334 spin_unlock(&espi->lock);
335 return sel; 335 return sel;
336} 336}
337
338/*
339 * This function is for T204 only.
340 * compare with t1_espi_get_mon(), it reads espiInTxSop[0 ~ 3] in
341 * one shot, since there is no per port counter on the out side.
342 */
343int
344t1_espi_get_mon_t204(adapter_t *adapter, u32 *valp, u8 wait)
345{
346 struct peespi *espi = adapter->espi;
347 u8 i, nport = (u8)adapter->params.nports;
348
349 if (!wait) {
350 if (!spin_trylock(&espi->lock))
351 return -1;
352 } else
353 spin_lock(&espi->lock);
354
355 if ( (espi->misc_ctrl & MON_MASK) != F_MONITORED_DIRECTION ) {
356 espi->misc_ctrl = (espi->misc_ctrl & ~MON_MASK) |
357 F_MONITORED_DIRECTION;
358 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL);
359 }
360 for (i = 0 ; i < nport; i++, valp++) {
361 if (i) {
362 writel(espi->misc_ctrl | V_MONITORED_PORT_NUM(i),
363 adapter->regs + A_ESPI_MISC_CONTROL);
364 }
365 *valp = readl(adapter->regs + A_ESPI_SCH_TOKEN3);
366 }
367
368 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL);
369 spin_unlock(&espi->lock);
370 return 0;
371}
diff --git a/drivers/net/chelsio/espi.h b/drivers/net/chelsio/espi.h
index c90e37f8457c..84f2c98bc4cc 100644
--- a/drivers/net/chelsio/espi.h
+++ b/drivers/net/chelsio/espi.h
@@ -64,5 +64,6 @@ const struct espi_intr_counts *t1_espi_get_intr_counts(struct peespi *espi);
64 64
65void t1_espi_set_misc_ctrl(adapter_t *adapter, u32 val); 65void t1_espi_set_misc_ctrl(adapter_t *adapter, u32 val);
66u32 t1_espi_get_mon(adapter_t *adapter, u32 addr, u8 wait); 66u32 t1_espi_get_mon(adapter_t *adapter, u32 addr, u8 wait);
67int t1_espi_get_mon_t204(adapter_t *, u32 *, u8);
67 68
68#endif /* _CXGB_ESPI_H_ */ 69#endif /* _CXGB_ESPI_H_ */
diff --git a/drivers/net/chelsio/fpga_defs.h b/drivers/net/chelsio/fpga_defs.h
new file mode 100644
index 000000000000..17a3c2ba36a3
--- /dev/null
+++ b/drivers/net/chelsio/fpga_defs.h
@@ -0,0 +1,232 @@
1/* $Date: 2005/03/07 23:59:05 $ $RCSfile: fpga_defs.h,v $ $Revision: 1.4 $ */
2
3/*
4 * FPGA specific definitions
5 */
6
7#ifndef __CHELSIO_FPGA_DEFS_H__
8#define __CHELSIO_FPGA_DEFS_H__
9
10#define FPGA_PCIX_ADDR_VERSION 0xA08
11#define FPGA_PCIX_ADDR_STAT 0xA0C
12
13/* FPGA master interrupt Cause/Enable bits */
14#define FPGA_PCIX_INTERRUPT_SGE_ERROR 0x1
15#define FPGA_PCIX_INTERRUPT_SGE_DATA 0x2
16#define FPGA_PCIX_INTERRUPT_TP 0x4
17#define FPGA_PCIX_INTERRUPT_MC3 0x8
18#define FPGA_PCIX_INTERRUPT_GMAC 0x10
19#define FPGA_PCIX_INTERRUPT_PCIX 0x20
20
21/* TP interrupt register addresses */
22#define FPGA_TP_ADDR_INTERRUPT_ENABLE 0xA10
23#define FPGA_TP_ADDR_INTERRUPT_CAUSE 0xA14
24#define FPGA_TP_ADDR_VERSION 0xA18
25
26/* TP interrupt Cause/Enable bits */
27#define FPGA_TP_INTERRUPT_MC4 0x1
28#define FPGA_TP_INTERRUPT_MC5 0x2
29
30/*
31 * PM interrupt register addresses
32 */
33#define FPGA_MC3_REG_INTRENABLE 0xA20
34#define FPGA_MC3_REG_INTRCAUSE 0xA24
35#define FPGA_MC3_REG_VERSION 0xA28
36
37/*
38 * GMAC interrupt register addresses
39 */
40#define FPGA_GMAC_ADDR_INTERRUPT_ENABLE 0xA30
41#define FPGA_GMAC_ADDR_INTERRUPT_CAUSE 0xA34
42#define FPGA_GMAC_ADDR_VERSION 0xA38
43
44/* GMAC Cause/Enable bits */
45#define FPGA_GMAC_INTERRUPT_PORT0 0x1
46#define FPGA_GMAC_INTERRUPT_PORT1 0x2
47#define FPGA_GMAC_INTERRUPT_PORT2 0x4
48#define FPGA_GMAC_INTERRUPT_PORT3 0x8
49
50/* MI0 registers */
51#define A_MI0_CLK 0xb00
52
53#define S_MI0_CLK_DIV 0
54#define M_MI0_CLK_DIV 0xff
55#define V_MI0_CLK_DIV(x) ((x) << S_MI0_CLK_DIV)
56#define G_MI0_CLK_DIV(x) (((x) >> S_MI0_CLK_DIV) & M_MI0_CLK_DIV)
57
58#define S_MI0_CLK_CNT 8
59#define M_MI0_CLK_CNT 0xff
60#define V_MI0_CLK_CNT(x) ((x) << S_MI0_CLK_CNT)
61#define G_MI0_CLK_CNT(x) (((x) >> S_MI0_CLK_CNT) & M_MI0_CLK_CNT)
62
63#define A_MI0_CSR 0xb04
64
65#define S_MI0_CSR_POLL 0
66#define V_MI0_CSR_POLL(x) ((x) << S_MI0_CSR_POLL)
67#define F_MI0_CSR_POLL V_MI0_CSR_POLL(1U)
68
69#define S_MI0_PREAMBLE 1
70#define V_MI0_PREAMBLE(x) ((x) << S_MI0_PREAMBLE)
71#define F_MI0_PREAMBLE V_MI0_PREAMBLE(1U)
72
73#define S_MI0_INTR_ENABLE 2
74#define V_MI0_INTR_ENABLE(x) ((x) << S_MI0_INTR_ENABLE)
75#define F_MI0_INTR_ENABLE V_MI0_INTR_ENABLE(1U)
76
77#define S_MI0_BUSY 3
78#define V_MI0_BUSY(x) ((x) << S_MI0_BUSY)
79#define F_MI0_BUSY V_MI0_BUSY(1U)
80
81#define S_MI0_MDIO 4
82#define V_MI0_MDIO(x) ((x) << S_MI0_MDIO)
83#define F_MI0_MDIO V_MI0_MDIO(1U)
84
85#define A_MI0_ADDR 0xb08
86
87#define S_MI0_PHY_REG_ADDR 0
88#define M_MI0_PHY_REG_ADDR 0x1f
89#define V_MI0_PHY_REG_ADDR(x) ((x) << S_MI0_PHY_REG_ADDR)
90#define G_MI0_PHY_REG_ADDR(x) (((x) >> S_MI0_PHY_REG_ADDR) & M_MI0_PHY_REG_ADDR)
91
92#define S_MI0_PHY_ADDR 5
93#define M_MI0_PHY_ADDR 0x1f
94#define V_MI0_PHY_ADDR(x) ((x) << S_MI0_PHY_ADDR)
95#define G_MI0_PHY_ADDR(x) (((x) >> S_MI0_PHY_ADDR) & M_MI0_PHY_ADDR)
96
97#define A_MI0_DATA_EXT 0xb0c
98#define A_MI0_DATA_INT 0xb10
99
100/* GMAC registers */
101#define A_GMAC_MACID_LO 0x28
102#define A_GMAC_MACID_HI 0x2c
103#define A_GMAC_CSR 0x30
104
105#define S_INTERFACE 0
106#define M_INTERFACE 0x3
107#define V_INTERFACE(x) ((x) << S_INTERFACE)
108#define G_INTERFACE(x) (((x) >> S_INTERFACE) & M_INTERFACE)
109
110#define S_MAC_TX_ENABLE 2
111#define V_MAC_TX_ENABLE(x) ((x) << S_MAC_TX_ENABLE)
112#define F_MAC_TX_ENABLE V_MAC_TX_ENABLE(1U)
113
114#define S_MAC_RX_ENABLE 3
115#define V_MAC_RX_ENABLE(x) ((x) << S_MAC_RX_ENABLE)
116#define F_MAC_RX_ENABLE V_MAC_RX_ENABLE(1U)
117
118#define S_MAC_LB_ENABLE 4
119#define V_MAC_LB_ENABLE(x) ((x) << S_MAC_LB_ENABLE)
120#define F_MAC_LB_ENABLE V_MAC_LB_ENABLE(1U)
121
122#define S_MAC_SPEED 5
123#define M_MAC_SPEED 0x3
124#define V_MAC_SPEED(x) ((x) << S_MAC_SPEED)
125#define G_MAC_SPEED(x) (((x) >> S_MAC_SPEED) & M_MAC_SPEED)
126
127#define S_MAC_HD_FC_ENABLE 7
128#define V_MAC_HD_FC_ENABLE(x) ((x) << S_MAC_HD_FC_ENABLE)
129#define F_MAC_HD_FC_ENABLE V_MAC_HD_FC_ENABLE(1U)
130
131#define S_MAC_HALF_DUPLEX 8
132#define V_MAC_HALF_DUPLEX(x) ((x) << S_MAC_HALF_DUPLEX)
133#define F_MAC_HALF_DUPLEX V_MAC_HALF_DUPLEX(1U)
134
135#define S_MAC_PROMISC 9
136#define V_MAC_PROMISC(x) ((x) << S_MAC_PROMISC)
137#define F_MAC_PROMISC V_MAC_PROMISC(1U)
138
139#define S_MAC_MC_ENABLE 10
140#define V_MAC_MC_ENABLE(x) ((x) << S_MAC_MC_ENABLE)
141#define F_MAC_MC_ENABLE V_MAC_MC_ENABLE(1U)
142
143#define S_MAC_RESET 11
144#define V_MAC_RESET(x) ((x) << S_MAC_RESET)
145#define F_MAC_RESET V_MAC_RESET(1U)
146
147#define S_MAC_RX_PAUSE_ENABLE 12
148#define V_MAC_RX_PAUSE_ENABLE(x) ((x) << S_MAC_RX_PAUSE_ENABLE)
149#define F_MAC_RX_PAUSE_ENABLE V_MAC_RX_PAUSE_ENABLE(1U)
150
151#define S_MAC_TX_PAUSE_ENABLE 13
152#define V_MAC_TX_PAUSE_ENABLE(x) ((x) << S_MAC_TX_PAUSE_ENABLE)
153#define F_MAC_TX_PAUSE_ENABLE V_MAC_TX_PAUSE_ENABLE(1U)
154
155#define S_MAC_LWM_ENABLE 14
156#define V_MAC_LWM_ENABLE(x) ((x) << S_MAC_LWM_ENABLE)
157#define F_MAC_LWM_ENABLE V_MAC_LWM_ENABLE(1U)
158
159#define S_MAC_MAGIC_PKT_ENABLE 15
160#define V_MAC_MAGIC_PKT_ENABLE(x) ((x) << S_MAC_MAGIC_PKT_ENABLE)
161#define F_MAC_MAGIC_PKT_ENABLE V_MAC_MAGIC_PKT_ENABLE(1U)
162
163#define S_MAC_ISL_ENABLE 16
164#define V_MAC_ISL_ENABLE(x) ((x) << S_MAC_ISL_ENABLE)
165#define F_MAC_ISL_ENABLE V_MAC_ISL_ENABLE(1U)
166
167#define S_MAC_JUMBO_ENABLE 17
168#define V_MAC_JUMBO_ENABLE(x) ((x) << S_MAC_JUMBO_ENABLE)
169#define F_MAC_JUMBO_ENABLE V_MAC_JUMBO_ENABLE(1U)
170
171#define S_MAC_RX_PAD_ENABLE 18
172#define V_MAC_RX_PAD_ENABLE(x) ((x) << S_MAC_RX_PAD_ENABLE)
173#define F_MAC_RX_PAD_ENABLE V_MAC_RX_PAD_ENABLE(1U)
174
175#define S_MAC_RX_CRC_ENABLE 19
176#define V_MAC_RX_CRC_ENABLE(x) ((x) << S_MAC_RX_CRC_ENABLE)
177#define F_MAC_RX_CRC_ENABLE V_MAC_RX_CRC_ENABLE(1U)
178
179#define A_GMAC_IFS 0x34
180
181#define S_MAC_IFS2 0
182#define M_MAC_IFS2 0x3f
183#define V_MAC_IFS2(x) ((x) << S_MAC_IFS2)
184#define G_MAC_IFS2(x) (((x) >> S_MAC_IFS2) & M_MAC_IFS2)
185
186#define S_MAC_IFS1 8
187#define M_MAC_IFS1 0x7f
188#define V_MAC_IFS1(x) ((x) << S_MAC_IFS1)
189#define G_MAC_IFS1(x) (((x) >> S_MAC_IFS1) & M_MAC_IFS1)
190
191#define A_GMAC_JUMBO_FRAME_LEN 0x38
192#define A_GMAC_LNK_DLY 0x3c
193#define A_GMAC_PAUSETIME 0x40
194#define A_GMAC_MCAST_LO 0x44
195#define A_GMAC_MCAST_HI 0x48
196#define A_GMAC_MCAST_MASK_LO 0x4c
197#define A_GMAC_MCAST_MASK_HI 0x50
198#define A_GMAC_RMT_CNT 0x54
199#define A_GMAC_RMT_DATA 0x58
200#define A_GMAC_BACKOFF_SEED 0x5c
201#define A_GMAC_TXF_THRES 0x60
202
203#define S_TXF_READ_THRESHOLD 0
204#define M_TXF_READ_THRESHOLD 0xff
205#define V_TXF_READ_THRESHOLD(x) ((x) << S_TXF_READ_THRESHOLD)
206#define G_TXF_READ_THRESHOLD(x) (((x) >> S_TXF_READ_THRESHOLD) & M_TXF_READ_THRESHOLD)
207
208#define S_TXF_WRITE_THRESHOLD 16
209#define M_TXF_WRITE_THRESHOLD 0xff
210#define V_TXF_WRITE_THRESHOLD(x) ((x) << S_TXF_WRITE_THRESHOLD)
211#define G_TXF_WRITE_THRESHOLD(x) (((x) >> S_TXF_WRITE_THRESHOLD) & M_TXF_WRITE_THRESHOLD)
212
213#define MAC_REG_BASE 0x600
214#define MAC_REG_ADDR(idx, reg) (MAC_REG_BASE + (idx) * 128 + (reg))
215
216#define MAC_REG_IDLO(idx) MAC_REG_ADDR(idx, A_GMAC_MACID_LO)
217#define MAC_REG_IDHI(idx) MAC_REG_ADDR(idx, A_GMAC_MACID_HI)
218#define MAC_REG_CSR(idx) MAC_REG_ADDR(idx, A_GMAC_CSR)
219#define MAC_REG_IFS(idx) MAC_REG_ADDR(idx, A_GMAC_IFS)
220#define MAC_REG_LARGEFRAMELENGTH(idx) MAC_REG_ADDR(idx, A_GMAC_JUMBO_FRAME_LEN)
221#define MAC_REG_LINKDLY(idx) MAC_REG_ADDR(idx, A_GMAC_LNK_DLY)
222#define MAC_REG_PAUSETIME(idx) MAC_REG_ADDR(idx, A_GMAC_PAUSETIME)
223#define MAC_REG_CASTLO(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_LO)
224#define MAC_REG_MCASTHI(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_HI)
225#define MAC_REG_CASTMASKLO(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_MASK_LO)
226#define MAC_REG_MCASTMASKHI(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_MASK_HI)
227#define MAC_REG_RMCNT(idx) MAC_REG_ADDR(idx, A_GMAC_RMT_CNT)
228#define MAC_REG_RMDATA(idx) MAC_REG_ADDR(idx, A_GMAC_RMT_DATA)
229#define MAC_REG_GMRANDBACKOFFSEED(idx) MAC_REG_ADDR(idx, A_GMAC_BACKOFF_SEED)
230#define MAC_REG_TXFTHRESHOLDS(idx) MAC_REG_ADDR(idx, A_GMAC_TXF_THRES)
231
232#endif
diff --git a/drivers/net/chelsio/gmac.h b/drivers/net/chelsio/gmac.h
index 746b0eeea964..a2b8ad9b5535 100644
--- a/drivers/net/chelsio/gmac.h
+++ b/drivers/net/chelsio/gmac.h
@@ -62,6 +62,8 @@ struct cmac_statistics {
62 u64 TxInternalMACXmitError; 62 u64 TxInternalMACXmitError;
63 u64 TxFramesWithExcessiveDeferral; 63 u64 TxFramesWithExcessiveDeferral;
64 u64 TxFCSErrors; 64 u64 TxFCSErrors;
65 u64 TxJumboFramesOK;
66 u64 TxJumboOctetsOK;
65 67
66 /* Receive */ 68 /* Receive */
67 u64 RxOctetsOK; 69 u64 RxOctetsOK;
@@ -81,6 +83,8 @@ struct cmac_statistics {
81 u64 RxInRangeLengthErrors; 83 u64 RxInRangeLengthErrors;
82 u64 RxOutOfRangeLengthField; 84 u64 RxOutOfRangeLengthField;
83 u64 RxFrameTooLongErrors; 85 u64 RxFrameTooLongErrors;
86 u64 RxJumboFramesOK;
87 u64 RxJumboOctetsOK;
84}; 88};
85 89
86struct cmac_ops { 90struct cmac_ops {
@@ -128,6 +132,7 @@ struct gmac {
128extern struct gmac t1_pm3393_ops; 132extern struct gmac t1_pm3393_ops;
129extern struct gmac t1_chelsio_mac_ops; 133extern struct gmac t1_chelsio_mac_ops;
130extern struct gmac t1_vsc7321_ops; 134extern struct gmac t1_vsc7321_ops;
135extern struct gmac t1_vsc7326_ops;
131extern struct gmac t1_ixf1010_ops; 136extern struct gmac t1_ixf1010_ops;
132extern struct gmac t1_dummy_mac_ops; 137extern struct gmac t1_dummy_mac_ops;
133 138
diff --git a/drivers/net/chelsio/mv88e1xxx.h b/drivers/net/chelsio/mv88e1xxx.h
new file mode 100644
index 000000000000..967cc4286359
--- /dev/null
+++ b/drivers/net/chelsio/mv88e1xxx.h
@@ -0,0 +1,127 @@
1/* $Date: 2005/03/07 23:59:05 $ $RCSfile: mv88e1xxx.h,v $ $Revision: 1.13 $ */
2#ifndef CHELSIO_MV8E1XXX_H
3#define CHELSIO_MV8E1XXX_H
4
5#ifndef BMCR_SPEED1000
6# define BMCR_SPEED1000 0x40
7#endif
8
9#ifndef ADVERTISE_PAUSE
10# define ADVERTISE_PAUSE 0x400
11#endif
12#ifndef ADVERTISE_PAUSE_ASYM
13# define ADVERTISE_PAUSE_ASYM 0x800
14#endif
15
16/* Gigabit MII registers */
17#define MII_GBCR 9 /* 1000Base-T control register */
18#define MII_GBSR 10 /* 1000Base-T status register */
19
20/* 1000Base-T control register fields */
21#define GBCR_ADV_1000HALF 0x100
22#define GBCR_ADV_1000FULL 0x200
23#define GBCR_PREFER_MASTER 0x400
24#define GBCR_MANUAL_AS_MASTER 0x800
25#define GBCR_MANUAL_CONFIG_ENABLE 0x1000
26
27/* 1000Base-T status register fields */
28#define GBSR_LP_1000HALF 0x400
29#define GBSR_LP_1000FULL 0x800
30#define GBSR_REMOTE_OK 0x1000
31#define GBSR_LOCAL_OK 0x2000
32#define GBSR_LOCAL_MASTER 0x4000
33#define GBSR_MASTER_FAULT 0x8000
34
35/* Marvell PHY interrupt status bits. */
36#define MV88E1XXX_INTR_JABBER 0x0001
37#define MV88E1XXX_INTR_POLARITY_CHNG 0x0002
38#define MV88E1XXX_INTR_ENG_DETECT_CHNG 0x0010
39#define MV88E1XXX_INTR_DOWNSHIFT 0x0020
40#define MV88E1XXX_INTR_MDI_XOVER_CHNG 0x0040
41#define MV88E1XXX_INTR_FIFO_OVER_UNDER 0x0080
42#define MV88E1XXX_INTR_FALSE_CARRIER 0x0100
43#define MV88E1XXX_INTR_SYMBOL_ERROR 0x0200
44#define MV88E1XXX_INTR_LINK_CHNG 0x0400
45#define MV88E1XXX_INTR_AUTONEG_DONE 0x0800
46#define MV88E1XXX_INTR_PAGE_RECV 0x1000
47#define MV88E1XXX_INTR_DUPLEX_CHNG 0x2000
48#define MV88E1XXX_INTR_SPEED_CHNG 0x4000
49#define MV88E1XXX_INTR_AUTONEG_ERR 0x8000
50
51/* Marvell PHY specific registers. */
52#define MV88E1XXX_SPECIFIC_CNTRL_REGISTER 16
53#define MV88E1XXX_SPECIFIC_STATUS_REGISTER 17
54#define MV88E1XXX_INTERRUPT_ENABLE_REGISTER 18
55#define MV88E1XXX_INTERRUPT_STATUS_REGISTER 19
56#define MV88E1XXX_EXT_PHY_SPECIFIC_CNTRL_REGISTER 20
57#define MV88E1XXX_RECV_ERR_CNTR_REGISTER 21
58#define MV88E1XXX_RES_REGISTER 22
59#define MV88E1XXX_GLOBAL_STATUS_REGISTER 23
60#define MV88E1XXX_LED_CONTROL_REGISTER 24
61#define MV88E1XXX_MANUAL_LED_OVERRIDE_REGISTER 25
62#define MV88E1XXX_EXT_PHY_SPECIFIC_CNTRL_2_REGISTER 26
63#define MV88E1XXX_EXT_PHY_SPECIFIC_STATUS_REGISTER 27
64#define MV88E1XXX_VIRTUAL_CABLE_TESTER_REGISTER 28
65#define MV88E1XXX_EXTENDED_ADDR_REGISTER 29
66#define MV88E1XXX_EXTENDED_REGISTER 30
67
68/* PHY specific control register fields */
69#define S_PSCR_MDI_XOVER_MODE 5
70#define M_PSCR_MDI_XOVER_MODE 0x3
71#define V_PSCR_MDI_XOVER_MODE(x) ((x) << S_PSCR_MDI_XOVER_MODE)
72#define G_PSCR_MDI_XOVER_MODE(x) (((x) >> S_PSCR_MDI_XOVER_MODE) & M_PSCR_MDI_XOVER_MODE)
73
74/* Extended PHY specific control register fields */
75#define S_DOWNSHIFT_ENABLE 8
76#define V_DOWNSHIFT_ENABLE (1 << S_DOWNSHIFT_ENABLE)
77
78#define S_DOWNSHIFT_CNT 9
79#define M_DOWNSHIFT_CNT 0x7
80#define V_DOWNSHIFT_CNT(x) ((x) << S_DOWNSHIFT_CNT)
81#define G_DOWNSHIFT_CNT(x) (((x) >> S_DOWNSHIFT_CNT) & M_DOWNSHIFT_CNT)
82
83/* PHY specific status register fields */
84#define S_PSSR_JABBER 0
85#define V_PSSR_JABBER (1 << S_PSSR_JABBER)
86
87#define S_PSSR_POLARITY 1
88#define V_PSSR_POLARITY (1 << S_PSSR_POLARITY)
89
90#define S_PSSR_RX_PAUSE 2
91#define V_PSSR_RX_PAUSE (1 << S_PSSR_RX_PAUSE)
92
93#define S_PSSR_TX_PAUSE 3
94#define V_PSSR_TX_PAUSE (1 << S_PSSR_TX_PAUSE)
95
96#define S_PSSR_ENERGY_DETECT 4
97#define V_PSSR_ENERGY_DETECT (1 << S_PSSR_ENERGY_DETECT)
98
99#define S_PSSR_DOWNSHIFT_STATUS 5
100#define V_PSSR_DOWNSHIFT_STATUS (1 << S_PSSR_DOWNSHIFT_STATUS)
101
102#define S_PSSR_MDI 6
103#define V_PSSR_MDI (1 << S_PSSR_MDI)
104
105#define S_PSSR_CABLE_LEN 7
106#define M_PSSR_CABLE_LEN 0x7
107#define V_PSSR_CABLE_LEN(x) ((x) << S_PSSR_CABLE_LEN)
108#define G_PSSR_CABLE_LEN(x) (((x) >> S_PSSR_CABLE_LEN) & M_PSSR_CABLE_LEN)
109
110#define S_PSSR_LINK 10
111#define V_PSSR_LINK (1 << S_PSSR_LINK)
112
113#define S_PSSR_STATUS_RESOLVED 11
114#define V_PSSR_STATUS_RESOLVED (1 << S_PSSR_STATUS_RESOLVED)
115
116#define S_PSSR_PAGE_RECEIVED 12
117#define V_PSSR_PAGE_RECEIVED (1 << S_PSSR_PAGE_RECEIVED)
118
119#define S_PSSR_DUPLEX 13
120#define V_PSSR_DUPLEX (1 << S_PSSR_DUPLEX)
121
122#define S_PSSR_SPEED 14
123#define M_PSSR_SPEED 0x3
124#define V_PSSR_SPEED(x) ((x) << S_PSSR_SPEED)
125#define G_PSSR_SPEED(x) (((x) >> S_PSSR_SPEED) & M_PSSR_SPEED)
126
127#endif
diff --git a/drivers/net/chelsio/mv88x201x.c b/drivers/net/chelsio/mv88x201x.c
index bf7d8538885d..c8e89480d906 100644
--- a/drivers/net/chelsio/mv88x201x.c
+++ b/drivers/net/chelsio/mv88x201x.c
@@ -85,29 +85,33 @@ static int mv88x201x_reset(struct cphy *cphy, int wait)
85 85
86static int mv88x201x_interrupt_enable(struct cphy *cphy) 86static int mv88x201x_interrupt_enable(struct cphy *cphy)
87{ 87{
88 u32 elmer;
89
90 /* Enable PHY LASI interrupts. */ 88 /* Enable PHY LASI interrupts. */
91 mdio_write(cphy, 0x1, 0x9002, 0x1); 89 mdio_write(cphy, 0x1, 0x9002, 0x1);
92 90
93 /* Enable Marvell interrupts through Elmer0. */ 91 /* Enable Marvell interrupts through Elmer0. */
94 t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer); 92 if (t1_is_asic(cphy->adapter)) {
95 elmer |= ELMER0_GP_BIT6; 93 u32 elmer;
96 t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer); 94
95 t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer);
96 elmer |= ELMER0_GP_BIT6;
97 t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer);
98 }
97 return 0; 99 return 0;
98} 100}
99 101
100static int mv88x201x_interrupt_disable(struct cphy *cphy) 102static int mv88x201x_interrupt_disable(struct cphy *cphy)
101{ 103{
102 u32 elmer;
103
104 /* Disable PHY LASI interrupts. */ 104 /* Disable PHY LASI interrupts. */
105 mdio_write(cphy, 0x1, 0x9002, 0x0); 105 mdio_write(cphy, 0x1, 0x9002, 0x0);
106 106
107 /* Disable Marvell interrupts through Elmer0. */ 107 /* Disable Marvell interrupts through Elmer0. */
108 t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer); 108 if (t1_is_asic(cphy->adapter)) {
109 elmer &= ~ELMER0_GP_BIT6; 109 u32 elmer;
110 t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer); 110
111 t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer);
112 elmer &= ~ELMER0_GP_BIT6;
113 t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer);
114 }
111 return 0; 115 return 0;
112} 116}
113 117
@@ -140,9 +144,11 @@ static int mv88x201x_interrupt_clear(struct cphy *cphy)
140#endif 144#endif
141 145
142 /* Clear Marvell interrupts through Elmer0. */ 146 /* Clear Marvell interrupts through Elmer0. */
143 t1_tpi_read(cphy->adapter, A_ELMER0_INT_CAUSE, &elmer); 147 if (t1_is_asic(cphy->adapter)) {
144 elmer |= ELMER0_GP_BIT6; 148 t1_tpi_read(cphy->adapter, A_ELMER0_INT_CAUSE, &elmer);
145 t1_tpi_write(cphy->adapter, A_ELMER0_INT_CAUSE, elmer); 149 elmer |= ELMER0_GP_BIT6;
150 t1_tpi_write(cphy->adapter, A_ELMER0_INT_CAUSE, elmer);
151 }
146 return 0; 152 return 0;
147} 153}
148 154
diff --git a/drivers/net/chelsio/my3126.c b/drivers/net/chelsio/my3126.c
new file mode 100644
index 000000000000..0b90014d5b3e
--- /dev/null
+++ b/drivers/net/chelsio/my3126.c
@@ -0,0 +1,204 @@
1/* $Date: 2005/11/12 02:13:49 $ $RCSfile: my3126.c,v $ $Revision: 1.15 $ */
2#include "cphy.h"
3#include "elmer0.h"
4#include "suni1x10gexp_regs.h"
5
6/* Port Reset */
7static int my3126_reset(struct cphy *cphy, int wait)
8{
9 /*
10 * This can be done through registers. It is not required since
11 * a full chip reset is used.
12 */
13 return (0);
14}
15
16static int my3126_interrupt_enable(struct cphy *cphy)
17{
18 schedule_delayed_work(&cphy->phy_update, HZ/30);
19 t1_tpi_read(cphy->adapter, A_ELMER0_GPO, &cphy->elmer_gpo);
20 return (0);
21}
22
23static int my3126_interrupt_disable(struct cphy *cphy)
24{
25 cancel_rearming_delayed_work(&cphy->phy_update);
26 return (0);
27}
28
29static int my3126_interrupt_clear(struct cphy *cphy)
30{
31 return (0);
32}
33
34#define OFFSET(REG_ADDR) (REG_ADDR << 2)
35
36static int my3126_interrupt_handler(struct cphy *cphy)
37{
38 u32 val;
39 u16 val16;
40 u16 status;
41 u32 act_count;
42 adapter_t *adapter;
43 adapter = cphy->adapter;
44
45 if (cphy->count == 50) {
46 mdio_read(cphy, 0x1, 0x1, &val);
47 val16 = (u16) val;
48 status = cphy->bmsr ^ val16;
49
50 if (status & BMSR_LSTATUS)
51 t1_link_changed(adapter, 0);
52 cphy->bmsr = val16;
53
54 /* We have only enabled link change interrupts so it
55 must be that
56 */
57 cphy->count = 0;
58 }
59
60 t1_tpi_write(adapter, OFFSET(SUNI1x10GEXP_REG_MSTAT_CONTROL),
61 SUNI1x10GEXP_BITMSK_MSTAT_SNAP);
62 t1_tpi_read(adapter,
63 OFFSET(SUNI1x10GEXP_REG_MSTAT_COUNTER_1_LOW), &act_count);
64 t1_tpi_read(adapter,
65 OFFSET(SUNI1x10GEXP_REG_MSTAT_COUNTER_33_LOW), &val);
66 act_count += val;
67
68 /* Populate elmer_gpo with the register value */
69 t1_tpi_read(adapter, A_ELMER0_GPO, &val);
70 cphy->elmer_gpo = val;
71
72 if ( (val & (1 << 8)) || (val & (1 << 19)) ||
73 (cphy->act_count == act_count) || cphy->act_on ) {
74 if (is_T2(adapter))
75 val |= (1 << 9);
76 else if (t1_is_T1B(adapter))
77 val |= (1 << 20);
78 cphy->act_on = 0;
79 } else {
80 if (is_T2(adapter))
81 val &= ~(1 << 9);
82 else if (t1_is_T1B(adapter))
83 val &= ~(1 << 20);
84 cphy->act_on = 1;
85 }
86
87 t1_tpi_write(adapter, A_ELMER0_GPO, val);
88
89 cphy->elmer_gpo = val;
90 cphy->act_count = act_count;
91 cphy->count++;
92
93 return cphy_cause_link_change;
94}
95
96static void my3216_poll(void *arg)
97{
98 my3126_interrupt_handler(arg);
99}
100
101static int my3126_set_loopback(struct cphy *cphy, int on)
102{
103 return (0);
104}
105
106/* To check the activity LED */
107static int my3126_get_link_status(struct cphy *cphy,
108 int *link_ok, int *speed, int *duplex, int *fc)
109{
110 u32 val;
111 u16 val16;
112 adapter_t *adapter;
113
114 adapter = cphy->adapter;
115 mdio_read(cphy, 0x1, 0x1, &val);
116 val16 = (u16) val;
117
118 /* Populate elmer_gpo with the register value */
119 t1_tpi_read(adapter, A_ELMER0_GPO, &val);
120 cphy->elmer_gpo = val;
121
122 *link_ok = (val16 & BMSR_LSTATUS);
123
124 if (*link_ok) {
125 /* Turn on the LED. */
126 if (is_T2(adapter))
127 val &= ~(1 << 8);
128 else if (t1_is_T1B(adapter))
129 val &= ~(1 << 19);
130 } else {
131 /* Turn off the LED. */
132 if (is_T2(adapter))
133 val |= (1 << 8);
134 else if (t1_is_T1B(adapter))
135 val |= (1 << 19);
136 }
137
138 t1_tpi_write(adapter, A_ELMER0_GPO, val);
139 cphy->elmer_gpo = val;
140 *speed = SPEED_10000;
141 *duplex = DUPLEX_FULL;
142
143 /* need to add flow control */
144 if (fc)
145 *fc = PAUSE_RX | PAUSE_TX;
146
147 return (0);
148}
149
150static void my3126_destroy(struct cphy *cphy)
151{
152 kfree(cphy);
153}
154
155static struct cphy_ops my3126_ops = {
156 .destroy = my3126_destroy,
157 .reset = my3126_reset,
158 .interrupt_enable = my3126_interrupt_enable,
159 .interrupt_disable = my3126_interrupt_disable,
160 .interrupt_clear = my3126_interrupt_clear,
161 .interrupt_handler = my3126_interrupt_handler,
162 .get_link_status = my3126_get_link_status,
163 .set_loopback = my3126_set_loopback,
164};
165
166static struct cphy *my3126_phy_create(adapter_t *adapter,
167 int phy_addr, struct mdio_ops *mdio_ops)
168{
169 struct cphy *cphy = kzalloc(sizeof (*cphy), GFP_KERNEL);
170
171 if (cphy)
172 cphy_init(cphy, adapter, phy_addr, &my3126_ops, mdio_ops);
173
174 INIT_WORK(&cphy->phy_update, my3216_poll, cphy);
175 cphy->bmsr = 0;
176
177 return (cphy);
178}
179
180/* Chip Reset */
181static int my3126_phy_reset(adapter_t * adapter)
182{
183 u32 val;
184
185 t1_tpi_read(adapter, A_ELMER0_GPO, &val);
186 val &= ~4;
187 t1_tpi_write(adapter, A_ELMER0_GPO, val);
188 msleep(100);
189
190 t1_tpi_write(adapter, A_ELMER0_GPO, val | 4);
191 msleep(1000);
192
193 /* Now lets enable the Laser. Delay 100us */
194 t1_tpi_read(adapter, A_ELMER0_GPO, &val);
195 val |= 0x8000;
196 t1_tpi_write(adapter, A_ELMER0_GPO, val);
197 udelay(100);
198 return (0);
199}
200
201struct gphy t1_my3126_ops = {
202 my3126_phy_create,
203 my3126_phy_reset
204};
diff --git a/drivers/net/chelsio/pm3393.c b/drivers/net/chelsio/pm3393.c
index 50983f9ce4bc..b943f5ddd8fd 100644
--- a/drivers/net/chelsio/pm3393.c
+++ b/drivers/net/chelsio/pm3393.c
@@ -88,6 +88,8 @@ enum { /* RMON registers */
88 RxJabbers = SUNI1x10GEXP_REG_MSTAT_COUNTER_16_LOW, 88 RxJabbers = SUNI1x10GEXP_REG_MSTAT_COUNTER_16_LOW,
89 RxFragments = SUNI1x10GEXP_REG_MSTAT_COUNTER_17_LOW, 89 RxFragments = SUNI1x10GEXP_REG_MSTAT_COUNTER_17_LOW,
90 RxUndersizedFrames = SUNI1x10GEXP_REG_MSTAT_COUNTER_18_LOW, 90 RxUndersizedFrames = SUNI1x10GEXP_REG_MSTAT_COUNTER_18_LOW,
91 RxJumboFramesReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_25_LOW,
92 RxJumboOctetsReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_26_LOW,
91 93
92 TxOctetsTransmittedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_33_LOW, 94 TxOctetsTransmittedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_33_LOW,
93 TxFramesLostDueToInternalMACTransmissionError = SUNI1x10GEXP_REG_MSTAT_COUNTER_35_LOW, 95 TxFramesLostDueToInternalMACTransmissionError = SUNI1x10GEXP_REG_MSTAT_COUNTER_35_LOW,
@@ -95,7 +97,9 @@ enum { /* RMON registers */
95 TxUnicastFramesTransmittedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_38_LOW, 97 TxUnicastFramesTransmittedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_38_LOW,
96 TxMulticastFramesTransmittedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_40_LOW, 98 TxMulticastFramesTransmittedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_40_LOW,
97 TxBroadcastFramesTransmittedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_42_LOW, 99 TxBroadcastFramesTransmittedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_42_LOW,
98 TxPAUSEMACCtrlFramesTransmitted = SUNI1x10GEXP_REG_MSTAT_COUNTER_43_LOW 100 TxPAUSEMACCtrlFramesTransmitted = SUNI1x10GEXP_REG_MSTAT_COUNTER_43_LOW,
101 TxJumboFramesReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_51_LOW,
102 TxJumboOctetsReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_52_LOW
99}; 103};
100 104
101struct _cmac_instance { 105struct _cmac_instance {
@@ -265,6 +269,8 @@ static int pm3393_interrupt_handler(struct cmac *cmac)
265 /* Read the master interrupt status register. */ 269 /* Read the master interrupt status register. */
266 pmread(cmac, SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS, 270 pmread(cmac, SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS,
267 &master_intr_status); 271 &master_intr_status);
272 CH_DBG(cmac->adapter, INTR, "PM3393 intr cause 0x%x\n",
273 master_intr_status);
268 274
269 /* TBD XXX Lets just clear everything for now */ 275 /* TBD XXX Lets just clear everything for now */
270 pm3393_interrupt_clear(cmac); 276 pm3393_interrupt_clear(cmac);
@@ -307,11 +313,7 @@ static int pm3393_enable_port(struct cmac *cmac, int which)
307 * The PHY doesn't give us link status indication on its own so have 313 * The PHY doesn't give us link status indication on its own so have
308 * the link management code query it instead. 314 * the link management code query it instead.
309 */ 315 */
310 { 316 t1_link_changed(cmac->adapter, 0);
311 extern void link_changed(adapter_t *adapter, int port_id);
312
313 link_changed(cmac->adapter, 0);
314 }
315 return 0; 317 return 0;
316} 318}
317 319
@@ -519,6 +521,8 @@ static const struct cmac_statistics *pm3393_update_statistics(struct cmac *mac,
519 RMON_UPDATE(mac, RxJabbers, RxJabberErrors); 521 RMON_UPDATE(mac, RxJabbers, RxJabberErrors);
520 RMON_UPDATE(mac, RxFragments, RxRuntErrors); 522 RMON_UPDATE(mac, RxFragments, RxRuntErrors);
521 RMON_UPDATE(mac, RxUndersizedFrames, RxRuntErrors); 523 RMON_UPDATE(mac, RxUndersizedFrames, RxRuntErrors);
524 RMON_UPDATE(mac, RxJumboFramesReceivedOK, RxJumboFramesOK);
525 RMON_UPDATE(mac, RxJumboOctetsReceivedOK, RxJumboOctetsOK);
522 526
523 /* Tx stats */ 527 /* Tx stats */
524 RMON_UPDATE(mac, TxOctetsTransmittedOK, TxOctetsOK); 528 RMON_UPDATE(mac, TxOctetsTransmittedOK, TxOctetsOK);
@@ -529,6 +533,8 @@ static const struct cmac_statistics *pm3393_update_statistics(struct cmac *mac,
529 RMON_UPDATE(mac, TxMulticastFramesTransmittedOK, TxMulticastFramesOK); 533 RMON_UPDATE(mac, TxMulticastFramesTransmittedOK, TxMulticastFramesOK);
530 RMON_UPDATE(mac, TxBroadcastFramesTransmittedOK, TxBroadcastFramesOK); 534 RMON_UPDATE(mac, TxBroadcastFramesTransmittedOK, TxBroadcastFramesOK);
531 RMON_UPDATE(mac, TxPAUSEMACCtrlFramesTransmitted, TxPauseFrames); 535 RMON_UPDATE(mac, TxPAUSEMACCtrlFramesTransmitted, TxPauseFrames);
536 RMON_UPDATE(mac, TxJumboFramesReceivedOK, TxJumboFramesOK);
537 RMON_UPDATE(mac, TxJumboOctetsReceivedOK, TxJumboOctetsOK);
532 538
533 return &mac->stats; 539 return &mac->stats;
534} 540}
@@ -814,6 +820,12 @@ static int pm3393_mac_reset(adapter_t * adapter)
814 820
815 successful_reset = (is_pl4_reset_finished && !is_pl4_outof_lock 821 successful_reset = (is_pl4_reset_finished && !is_pl4_outof_lock
816 && is_xaui_mabc_pll_locked); 822 && is_xaui_mabc_pll_locked);
823
824 CH_DBG(adapter, HW,
825 "PM3393 HW reset %d: pl4_reset 0x%x, val 0x%x, "
826 "is_pl4_outof_lock 0x%x, xaui_locked 0x%x\n",
827 i, is_pl4_reset_finished, val, is_pl4_outof_lock,
828 is_xaui_mabc_pll_locked);
817 } 829 }
818 return successful_reset ? 0 : 1; 830 return successful_reset ? 0 : 1;
819} 831}
diff --git a/drivers/net/chelsio/regs.h b/drivers/net/chelsio/regs.h
index b90e11f40d1f..c80bf4d6d0a6 100644
--- a/drivers/net/chelsio/regs.h
+++ b/drivers/net/chelsio/regs.h
@@ -71,6 +71,10 @@
71#define V_CMDQ_PRIORITY(x) ((x) << S_CMDQ_PRIORITY) 71#define V_CMDQ_PRIORITY(x) ((x) << S_CMDQ_PRIORITY)
72#define G_CMDQ_PRIORITY(x) (((x) >> S_CMDQ_PRIORITY) & M_CMDQ_PRIORITY) 72#define G_CMDQ_PRIORITY(x) (((x) >> S_CMDQ_PRIORITY) & M_CMDQ_PRIORITY)
73 73
74#define S_DISABLE_CMDQ0_GTS 8
75#define V_DISABLE_CMDQ0_GTS(x) ((x) << S_DISABLE_CMDQ0_GTS)
76#define F_DISABLE_CMDQ0_GTS V_DISABLE_CMDQ0_GTS(1U)
77
74#define S_DISABLE_CMDQ1_GTS 9 78#define S_DISABLE_CMDQ1_GTS 9
75#define V_DISABLE_CMDQ1_GTS(x) ((x) << S_DISABLE_CMDQ1_GTS) 79#define V_DISABLE_CMDQ1_GTS(x) ((x) << S_DISABLE_CMDQ1_GTS)
76#define F_DISABLE_CMDQ1_GTS V_DISABLE_CMDQ1_GTS(1U) 80#define F_DISABLE_CMDQ1_GTS V_DISABLE_CMDQ1_GTS(1U)
@@ -87,12 +91,18 @@
87#define V_ENABLE_BIG_ENDIAN(x) ((x) << S_ENABLE_BIG_ENDIAN) 91#define V_ENABLE_BIG_ENDIAN(x) ((x) << S_ENABLE_BIG_ENDIAN)
88#define F_ENABLE_BIG_ENDIAN V_ENABLE_BIG_ENDIAN(1U) 92#define F_ENABLE_BIG_ENDIAN V_ENABLE_BIG_ENDIAN(1U)
89 93
94#define S_FL_SELECTION_CRITERIA 13
95#define V_FL_SELECTION_CRITERIA(x) ((x) << S_FL_SELECTION_CRITERIA)
96#define F_FL_SELECTION_CRITERIA V_FL_SELECTION_CRITERIA(1U)
97
90#define S_ISCSI_COALESCE 14 98#define S_ISCSI_COALESCE 14
91#define V_ISCSI_COALESCE(x) ((x) << S_ISCSI_COALESCE) 99#define V_ISCSI_COALESCE(x) ((x) << S_ISCSI_COALESCE)
92#define F_ISCSI_COALESCE V_ISCSI_COALESCE(1U) 100#define F_ISCSI_COALESCE V_ISCSI_COALESCE(1U)
93 101
94#define S_RX_PKT_OFFSET 15 102#define S_RX_PKT_OFFSET 15
103#define M_RX_PKT_OFFSET 0x7
95#define V_RX_PKT_OFFSET(x) ((x) << S_RX_PKT_OFFSET) 104#define V_RX_PKT_OFFSET(x) ((x) << S_RX_PKT_OFFSET)
105#define G_RX_PKT_OFFSET(x) (((x) >> S_RX_PKT_OFFSET) & M_RX_PKT_OFFSET)
96 106
97#define S_VLAN_XTRACT 18 107#define S_VLAN_XTRACT 18
98#define V_VLAN_XTRACT(x) ((x) << S_VLAN_XTRACT) 108#define V_VLAN_XTRACT(x) ((x) << S_VLAN_XTRACT)
@@ -108,16 +118,114 @@
108#define A_SG_FL1BASELWR 0x20 118#define A_SG_FL1BASELWR 0x20
109#define A_SG_FL1BASEUPR 0x24 119#define A_SG_FL1BASEUPR 0x24
110#define A_SG_CMD0SIZE 0x28 120#define A_SG_CMD0SIZE 0x28
121
122#define S_CMDQ0_SIZE 0
123#define M_CMDQ0_SIZE 0x1ffff
124#define V_CMDQ0_SIZE(x) ((x) << S_CMDQ0_SIZE)
125#define G_CMDQ0_SIZE(x) (((x) >> S_CMDQ0_SIZE) & M_CMDQ0_SIZE)
126
111#define A_SG_FL0SIZE 0x2c 127#define A_SG_FL0SIZE 0x2c
128
129#define S_FL0_SIZE 0
130#define M_FL0_SIZE 0x1ffff
131#define V_FL0_SIZE(x) ((x) << S_FL0_SIZE)
132#define G_FL0_SIZE(x) (((x) >> S_FL0_SIZE) & M_FL0_SIZE)
133
112#define A_SG_RSPSIZE 0x30 134#define A_SG_RSPSIZE 0x30
135
136#define S_RESPQ_SIZE 0
137#define M_RESPQ_SIZE 0x1ffff
138#define V_RESPQ_SIZE(x) ((x) << S_RESPQ_SIZE)
139#define G_RESPQ_SIZE(x) (((x) >> S_RESPQ_SIZE) & M_RESPQ_SIZE)
140
113#define A_SG_RSPBASELWR 0x34 141#define A_SG_RSPBASELWR 0x34
114#define A_SG_RSPBASEUPR 0x38 142#define A_SG_RSPBASEUPR 0x38
115#define A_SG_FLTHRESHOLD 0x3c 143#define A_SG_FLTHRESHOLD 0x3c
144
145#define S_FL_THRESHOLD 0
146#define M_FL_THRESHOLD 0xffff
147#define V_FL_THRESHOLD(x) ((x) << S_FL_THRESHOLD)
148#define G_FL_THRESHOLD(x) (((x) >> S_FL_THRESHOLD) & M_FL_THRESHOLD)
149
116#define A_SG_RSPQUEUECREDIT 0x40 150#define A_SG_RSPQUEUECREDIT 0x40
151
152#define S_RESPQ_CREDIT 0
153#define M_RESPQ_CREDIT 0x1ffff
154#define V_RESPQ_CREDIT(x) ((x) << S_RESPQ_CREDIT)
155#define G_RESPQ_CREDIT(x) (((x) >> S_RESPQ_CREDIT) & M_RESPQ_CREDIT)
156
117#define A_SG_SLEEPING 0x48 157#define A_SG_SLEEPING 0x48
158
159#define S_SLEEPING 0
160#define M_SLEEPING 0xffff
161#define V_SLEEPING(x) ((x) << S_SLEEPING)
162#define G_SLEEPING(x) (((x) >> S_SLEEPING) & M_SLEEPING)
163
118#define A_SG_INTRTIMER 0x4c 164#define A_SG_INTRTIMER 0x4c
165
166#define S_INTERRUPT_TIMER_COUNT 0
167#define M_INTERRUPT_TIMER_COUNT 0xffffff
168#define V_INTERRUPT_TIMER_COUNT(x) ((x) << S_INTERRUPT_TIMER_COUNT)
169#define G_INTERRUPT_TIMER_COUNT(x) (((x) >> S_INTERRUPT_TIMER_COUNT) & M_INTERRUPT_TIMER_COUNT)
170
171#define A_SG_CMD0PTR 0x50
172
173#define S_CMDQ0_POINTER 0
174#define M_CMDQ0_POINTER 0xffff
175#define V_CMDQ0_POINTER(x) ((x) << S_CMDQ0_POINTER)
176#define G_CMDQ0_POINTER(x) (((x) >> S_CMDQ0_POINTER) & M_CMDQ0_POINTER)
177
178#define S_CURRENT_GENERATION_BIT 16
179#define V_CURRENT_GENERATION_BIT(x) ((x) << S_CURRENT_GENERATION_BIT)
180#define F_CURRENT_GENERATION_BIT V_CURRENT_GENERATION_BIT(1U)
181
182#define A_SG_CMD1PTR 0x54
183
184#define S_CMDQ1_POINTER 0
185#define M_CMDQ1_POINTER 0xffff
186#define V_CMDQ1_POINTER(x) ((x) << S_CMDQ1_POINTER)
187#define G_CMDQ1_POINTER(x) (((x) >> S_CMDQ1_POINTER) & M_CMDQ1_POINTER)
188
189#define A_SG_FL0PTR 0x58
190
191#define S_FL0_POINTER 0
192#define M_FL0_POINTER 0xffff
193#define V_FL0_POINTER(x) ((x) << S_FL0_POINTER)
194#define G_FL0_POINTER(x) (((x) >> S_FL0_POINTER) & M_FL0_POINTER)
195
196#define A_SG_FL1PTR 0x5c
197
198#define S_FL1_POINTER 0
199#define M_FL1_POINTER 0xffff
200#define V_FL1_POINTER(x) ((x) << S_FL1_POINTER)
201#define G_FL1_POINTER(x) (((x) >> S_FL1_POINTER) & M_FL1_POINTER)
202
203#define A_SG_VERSION 0x6c
204
205#define S_DAY 0
206#define M_DAY 0x1f
207#define V_DAY(x) ((x) << S_DAY)
208#define G_DAY(x) (((x) >> S_DAY) & M_DAY)
209
210#define S_MONTH 5
211#define M_MONTH 0xf
212#define V_MONTH(x) ((x) << S_MONTH)
213#define G_MONTH(x) (((x) >> S_MONTH) & M_MONTH)
214
119#define A_SG_CMD1SIZE 0xb0 215#define A_SG_CMD1SIZE 0xb0
216
217#define S_CMDQ1_SIZE 0
218#define M_CMDQ1_SIZE 0x1ffff
219#define V_CMDQ1_SIZE(x) ((x) << S_CMDQ1_SIZE)
220#define G_CMDQ1_SIZE(x) (((x) >> S_CMDQ1_SIZE) & M_CMDQ1_SIZE)
221
120#define A_SG_FL1SIZE 0xb4 222#define A_SG_FL1SIZE 0xb4
223
224#define S_FL1_SIZE 0
225#define M_FL1_SIZE 0x1ffff
226#define V_FL1_SIZE(x) ((x) << S_FL1_SIZE)
227#define G_FL1_SIZE(x) (((x) >> S_FL1_SIZE) & M_FL1_SIZE)
228
121#define A_SG_INT_ENABLE 0xb8 229#define A_SG_INT_ENABLE 0xb8
122 230
123#define S_RESPQ_EXHAUSTED 0 231#define S_RESPQ_EXHAUSTED 0
@@ -144,21 +252,369 @@
144#define A_SG_RESPACCUTIMER 0xc0 252#define A_SG_RESPACCUTIMER 0xc0
145 253
146/* MC3 registers */ 254/* MC3 registers */
255#define A_MC3_CFG 0x100
256
257#define S_CLK_ENABLE 0
258#define V_CLK_ENABLE(x) ((x) << S_CLK_ENABLE)
259#define F_CLK_ENABLE V_CLK_ENABLE(1U)
147 260
148#define S_READY 1 261#define S_READY 1
149#define V_READY(x) ((x) << S_READY) 262#define V_READY(x) ((x) << S_READY)
150#define F_READY V_READY(1U) 263#define F_READY V_READY(1U)
151 264
152/* MC4 registers */ 265#define S_READ_TO_WRITE_DELAY 2
266#define M_READ_TO_WRITE_DELAY 0x7
267#define V_READ_TO_WRITE_DELAY(x) ((x) << S_READ_TO_WRITE_DELAY)
268#define G_READ_TO_WRITE_DELAY(x) (((x) >> S_READ_TO_WRITE_DELAY) & M_READ_TO_WRITE_DELAY)
269
270#define S_WRITE_TO_READ_DELAY 5
271#define M_WRITE_TO_READ_DELAY 0x7
272#define V_WRITE_TO_READ_DELAY(x) ((x) << S_WRITE_TO_READ_DELAY)
273#define G_WRITE_TO_READ_DELAY(x) (((x) >> S_WRITE_TO_READ_DELAY) & M_WRITE_TO_READ_DELAY)
153 274
275#define S_MC3_BANK_CYCLE 8
276#define M_MC3_BANK_CYCLE 0xf
277#define V_MC3_BANK_CYCLE(x) ((x) << S_MC3_BANK_CYCLE)
278#define G_MC3_BANK_CYCLE(x) (((x) >> S_MC3_BANK_CYCLE) & M_MC3_BANK_CYCLE)
279
280#define S_REFRESH_CYCLE 12
281#define M_REFRESH_CYCLE 0xf
282#define V_REFRESH_CYCLE(x) ((x) << S_REFRESH_CYCLE)
283#define G_REFRESH_CYCLE(x) (((x) >> S_REFRESH_CYCLE) & M_REFRESH_CYCLE)
284
285#define S_PRECHARGE_CYCLE 16
286#define M_PRECHARGE_CYCLE 0x3
287#define V_PRECHARGE_CYCLE(x) ((x) << S_PRECHARGE_CYCLE)
288#define G_PRECHARGE_CYCLE(x) (((x) >> S_PRECHARGE_CYCLE) & M_PRECHARGE_CYCLE)
289
290#define S_ACTIVE_TO_READ_WRITE_DELAY 18
291#define V_ACTIVE_TO_READ_WRITE_DELAY(x) ((x) << S_ACTIVE_TO_READ_WRITE_DELAY)
292#define F_ACTIVE_TO_READ_WRITE_DELAY V_ACTIVE_TO_READ_WRITE_DELAY(1U)
293
294#define S_ACTIVE_TO_PRECHARGE_DELAY 19
295#define M_ACTIVE_TO_PRECHARGE_DELAY 0x7
296#define V_ACTIVE_TO_PRECHARGE_DELAY(x) ((x) << S_ACTIVE_TO_PRECHARGE_DELAY)
297#define G_ACTIVE_TO_PRECHARGE_DELAY(x) (((x) >> S_ACTIVE_TO_PRECHARGE_DELAY) & M_ACTIVE_TO_PRECHARGE_DELAY)
298
299#define S_WRITE_RECOVERY_DELAY 22
300#define M_WRITE_RECOVERY_DELAY 0x3
301#define V_WRITE_RECOVERY_DELAY(x) ((x) << S_WRITE_RECOVERY_DELAY)
302#define G_WRITE_RECOVERY_DELAY(x) (((x) >> S_WRITE_RECOVERY_DELAY) & M_WRITE_RECOVERY_DELAY)
303
304#define S_DENSITY 24
305#define M_DENSITY 0x3
306#define V_DENSITY(x) ((x) << S_DENSITY)
307#define G_DENSITY(x) (((x) >> S_DENSITY) & M_DENSITY)
308
309#define S_ORGANIZATION 26
310#define V_ORGANIZATION(x) ((x) << S_ORGANIZATION)
311#define F_ORGANIZATION V_ORGANIZATION(1U)
312
313#define S_BANKS 27
314#define V_BANKS(x) ((x) << S_BANKS)
315#define F_BANKS V_BANKS(1U)
316
317#define S_UNREGISTERED 28
318#define V_UNREGISTERED(x) ((x) << S_UNREGISTERED)
319#define F_UNREGISTERED V_UNREGISTERED(1U)
320
321#define S_MC3_WIDTH 29
322#define M_MC3_WIDTH 0x3
323#define V_MC3_WIDTH(x) ((x) << S_MC3_WIDTH)
324#define G_MC3_WIDTH(x) (((x) >> S_MC3_WIDTH) & M_MC3_WIDTH)
325
326#define S_MC3_SLOW 31
327#define V_MC3_SLOW(x) ((x) << S_MC3_SLOW)
328#define F_MC3_SLOW V_MC3_SLOW(1U)
329
330#define A_MC3_MODE 0x104
331
332#define S_MC3_MODE 0
333#define M_MC3_MODE 0x3fff
334#define V_MC3_MODE(x) ((x) << S_MC3_MODE)
335#define G_MC3_MODE(x) (((x) >> S_MC3_MODE) & M_MC3_MODE)
336
337#define S_BUSY 31
338#define V_BUSY(x) ((x) << S_BUSY)
339#define F_BUSY V_BUSY(1U)
340
341#define A_MC3_EXT_MODE 0x108
342
343#define S_MC3_EXTENDED_MODE 0
344#define M_MC3_EXTENDED_MODE 0x3fff
345#define V_MC3_EXTENDED_MODE(x) ((x) << S_MC3_EXTENDED_MODE)
346#define G_MC3_EXTENDED_MODE(x) (((x) >> S_MC3_EXTENDED_MODE) & M_MC3_EXTENDED_MODE)
347
348#define A_MC3_PRECHARG 0x10c
349#define A_MC3_REFRESH 0x110
350
351#define S_REFRESH_ENABLE 0
352#define V_REFRESH_ENABLE(x) ((x) << S_REFRESH_ENABLE)
353#define F_REFRESH_ENABLE V_REFRESH_ENABLE(1U)
354
355#define S_REFRESH_DIVISOR 1
356#define M_REFRESH_DIVISOR 0x3fff
357#define V_REFRESH_DIVISOR(x) ((x) << S_REFRESH_DIVISOR)
358#define G_REFRESH_DIVISOR(x) (((x) >> S_REFRESH_DIVISOR) & M_REFRESH_DIVISOR)
359
360#define A_MC3_STROBE 0x114
361
362#define S_MASTER_DLL_RESET 0
363#define V_MASTER_DLL_RESET(x) ((x) << S_MASTER_DLL_RESET)
364#define F_MASTER_DLL_RESET V_MASTER_DLL_RESET(1U)
365
366#define S_MASTER_DLL_TAP_COUNT 1
367#define M_MASTER_DLL_TAP_COUNT 0xff
368#define V_MASTER_DLL_TAP_COUNT(x) ((x) << S_MASTER_DLL_TAP_COUNT)
369#define G_MASTER_DLL_TAP_COUNT(x) (((x) >> S_MASTER_DLL_TAP_COUNT) & M_MASTER_DLL_TAP_COUNT)
370
371#define S_MASTER_DLL_LOCKED 9
372#define V_MASTER_DLL_LOCKED(x) ((x) << S_MASTER_DLL_LOCKED)
373#define F_MASTER_DLL_LOCKED V_MASTER_DLL_LOCKED(1U)
374
375#define S_MASTER_DLL_MAX_TAP_COUNT 10
376#define V_MASTER_DLL_MAX_TAP_COUNT(x) ((x) << S_MASTER_DLL_MAX_TAP_COUNT)
377#define F_MASTER_DLL_MAX_TAP_COUNT V_MASTER_DLL_MAX_TAP_COUNT(1U)
378
379#define S_MASTER_DLL_TAP_COUNT_OFFSET 11
380#define M_MASTER_DLL_TAP_COUNT_OFFSET 0x3f
381#define V_MASTER_DLL_TAP_COUNT_OFFSET(x) ((x) << S_MASTER_DLL_TAP_COUNT_OFFSET)
382#define G_MASTER_DLL_TAP_COUNT_OFFSET(x) (((x) >> S_MASTER_DLL_TAP_COUNT_OFFSET) & M_MASTER_DLL_TAP_COUNT_OFFSET)
383
384#define S_SLAVE_DLL_RESET 11
385#define V_SLAVE_DLL_RESET(x) ((x) << S_SLAVE_DLL_RESET)
386#define F_SLAVE_DLL_RESET V_SLAVE_DLL_RESET(1U)
387
388#define S_SLAVE_DLL_DELTA 12
389#define M_SLAVE_DLL_DELTA 0xf
390#define V_SLAVE_DLL_DELTA(x) ((x) << S_SLAVE_DLL_DELTA)
391#define G_SLAVE_DLL_DELTA(x) (((x) >> S_SLAVE_DLL_DELTA) & M_SLAVE_DLL_DELTA)
392
393#define S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT 17
394#define M_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT 0x3f
395#define V_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT(x) ((x) << S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT)
396#define G_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT(x) (((x) >> S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT) & M_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT)
397
398#define S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE 23
399#define V_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE(x) ((x) << S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE)
400#define F_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE V_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE(1U)
401
402#define S_SLAVE_DELAY_LINE_TAP_COUNT 24
403#define M_SLAVE_DELAY_LINE_TAP_COUNT 0x3f
404#define V_SLAVE_DELAY_LINE_TAP_COUNT(x) ((x) << S_SLAVE_DELAY_LINE_TAP_COUNT)
405#define G_SLAVE_DELAY_LINE_TAP_COUNT(x) (((x) >> S_SLAVE_DELAY_LINE_TAP_COUNT) & M_SLAVE_DELAY_LINE_TAP_COUNT)
406
407#define A_MC3_ECC_CNTL 0x118
408
409#define S_ECC_GENERATION_ENABLE 0
410#define V_ECC_GENERATION_ENABLE(x) ((x) << S_ECC_GENERATION_ENABLE)
411#define F_ECC_GENERATION_ENABLE V_ECC_GENERATION_ENABLE(1U)
412
413#define S_ECC_CHECK_ENABLE 1
414#define V_ECC_CHECK_ENABLE(x) ((x) << S_ECC_CHECK_ENABLE)
415#define F_ECC_CHECK_ENABLE V_ECC_CHECK_ENABLE(1U)
416
417#define S_CORRECTABLE_ERROR_COUNT 2
418#define M_CORRECTABLE_ERROR_COUNT 0xff
419#define V_CORRECTABLE_ERROR_COUNT(x) ((x) << S_CORRECTABLE_ERROR_COUNT)
420#define G_CORRECTABLE_ERROR_COUNT(x) (((x) >> S_CORRECTABLE_ERROR_COUNT) & M_CORRECTABLE_ERROR_COUNT)
421
422#define S_UNCORRECTABLE_ERROR_COUNT 10
423#define M_UNCORRECTABLE_ERROR_COUNT 0xff
424#define V_UNCORRECTABLE_ERROR_COUNT(x) ((x) << S_UNCORRECTABLE_ERROR_COUNT)
425#define G_UNCORRECTABLE_ERROR_COUNT(x) (((x) >> S_UNCORRECTABLE_ERROR_COUNT) & M_UNCORRECTABLE_ERROR_COUNT)
426
427#define A_MC3_CE_ADDR 0x11c
428
429#define S_MC3_CE_ADDR 4
430#define M_MC3_CE_ADDR 0xfffffff
431#define V_MC3_CE_ADDR(x) ((x) << S_MC3_CE_ADDR)
432#define G_MC3_CE_ADDR(x) (((x) >> S_MC3_CE_ADDR) & M_MC3_CE_ADDR)
433
434#define A_MC3_CE_DATA0 0x120
435#define A_MC3_CE_DATA1 0x124
436#define A_MC3_CE_DATA2 0x128
437#define A_MC3_CE_DATA3 0x12c
438#define A_MC3_CE_DATA4 0x130
439#define A_MC3_UE_ADDR 0x134
440
441#define S_MC3_UE_ADDR 4
442#define M_MC3_UE_ADDR 0xfffffff
443#define V_MC3_UE_ADDR(x) ((x) << S_MC3_UE_ADDR)
444#define G_MC3_UE_ADDR(x) (((x) >> S_MC3_UE_ADDR) & M_MC3_UE_ADDR)
445
446#define A_MC3_UE_DATA0 0x138
447#define A_MC3_UE_DATA1 0x13c
448#define A_MC3_UE_DATA2 0x140
449#define A_MC3_UE_DATA3 0x144
450#define A_MC3_UE_DATA4 0x148
451#define A_MC3_BD_ADDR 0x14c
452#define A_MC3_BD_DATA0 0x150
453#define A_MC3_BD_DATA1 0x154
454#define A_MC3_BD_DATA2 0x158
455#define A_MC3_BD_DATA3 0x15c
456#define A_MC3_BD_DATA4 0x160
457#define A_MC3_BD_OP 0x164
458
459#define S_BACK_DOOR_OPERATION 0
460#define V_BACK_DOOR_OPERATION(x) ((x) << S_BACK_DOOR_OPERATION)
461#define F_BACK_DOOR_OPERATION V_BACK_DOOR_OPERATION(1U)
462
463#define A_MC3_BIST_ADDR_BEG 0x168
464#define A_MC3_BIST_ADDR_END 0x16c
465#define A_MC3_BIST_DATA 0x170
466#define A_MC3_BIST_OP 0x174
467
468#define S_OP 0
469#define V_OP(x) ((x) << S_OP)
470#define F_OP V_OP(1U)
471
472#define S_DATA_PATTERN 1
473#define M_DATA_PATTERN 0x3
474#define V_DATA_PATTERN(x) ((x) << S_DATA_PATTERN)
475#define G_DATA_PATTERN(x) (((x) >> S_DATA_PATTERN) & M_DATA_PATTERN)
476
477#define S_CONTINUOUS 3
478#define V_CONTINUOUS(x) ((x) << S_CONTINUOUS)
479#define F_CONTINUOUS V_CONTINUOUS(1U)
480
481#define A_MC3_INT_ENABLE 0x178
482
483#define S_MC3_CORR_ERR 0
484#define V_MC3_CORR_ERR(x) ((x) << S_MC3_CORR_ERR)
485#define F_MC3_CORR_ERR V_MC3_CORR_ERR(1U)
486
487#define S_MC3_UNCORR_ERR 1
488#define V_MC3_UNCORR_ERR(x) ((x) << S_MC3_UNCORR_ERR)
489#define F_MC3_UNCORR_ERR V_MC3_UNCORR_ERR(1U)
490
491#define S_MC3_PARITY_ERR 2
492#define M_MC3_PARITY_ERR 0xff
493#define V_MC3_PARITY_ERR(x) ((x) << S_MC3_PARITY_ERR)
494#define G_MC3_PARITY_ERR(x) (((x) >> S_MC3_PARITY_ERR) & M_MC3_PARITY_ERR)
495
496#define S_MC3_ADDR_ERR 10
497#define V_MC3_ADDR_ERR(x) ((x) << S_MC3_ADDR_ERR)
498#define F_MC3_ADDR_ERR V_MC3_ADDR_ERR(1U)
499
500#define A_MC3_INT_CAUSE 0x17c
501
502/* MC4 registers */
154#define A_MC4_CFG 0x180 503#define A_MC4_CFG 0x180
504
505#define S_POWER_UP 0
506#define V_POWER_UP(x) ((x) << S_POWER_UP)
507#define F_POWER_UP V_POWER_UP(1U)
508
509#define S_MC4_BANK_CYCLE 8
510#define M_MC4_BANK_CYCLE 0x7
511#define V_MC4_BANK_CYCLE(x) ((x) << S_MC4_BANK_CYCLE)
512#define G_MC4_BANK_CYCLE(x) (((x) >> S_MC4_BANK_CYCLE) & M_MC4_BANK_CYCLE)
513
514#define S_MC4_NARROW 24
515#define V_MC4_NARROW(x) ((x) << S_MC4_NARROW)
516#define F_MC4_NARROW V_MC4_NARROW(1U)
517
155#define S_MC4_SLOW 25 518#define S_MC4_SLOW 25
156#define V_MC4_SLOW(x) ((x) << S_MC4_SLOW) 519#define V_MC4_SLOW(x) ((x) << S_MC4_SLOW)
157#define F_MC4_SLOW V_MC4_SLOW(1U) 520#define F_MC4_SLOW V_MC4_SLOW(1U)
158 521
159/* TPI registers */ 522#define S_MC4A_WIDTH 24
523#define M_MC4A_WIDTH 0x3
524#define V_MC4A_WIDTH(x) ((x) << S_MC4A_WIDTH)
525#define G_MC4A_WIDTH(x) (((x) >> S_MC4A_WIDTH) & M_MC4A_WIDTH)
526
527#define S_MC4A_SLOW 26
528#define V_MC4A_SLOW(x) ((x) << S_MC4A_SLOW)
529#define F_MC4A_SLOW V_MC4A_SLOW(1U)
530
531#define A_MC4_MODE 0x184
532
533#define S_MC4_MODE 0
534#define M_MC4_MODE 0x7fff
535#define V_MC4_MODE(x) ((x) << S_MC4_MODE)
536#define G_MC4_MODE(x) (((x) >> S_MC4_MODE) & M_MC4_MODE)
537
538#define A_MC4_EXT_MODE 0x188
539
540#define S_MC4_EXTENDED_MODE 0
541#define M_MC4_EXTENDED_MODE 0x7fff
542#define V_MC4_EXTENDED_MODE(x) ((x) << S_MC4_EXTENDED_MODE)
543#define G_MC4_EXTENDED_MODE(x) (((x) >> S_MC4_EXTENDED_MODE) & M_MC4_EXTENDED_MODE)
544
545#define A_MC4_REFRESH 0x190
546#define A_MC4_STROBE 0x194
547#define A_MC4_ECC_CNTL 0x198
548#define A_MC4_CE_ADDR 0x19c
549
550#define S_MC4_CE_ADDR 4
551#define M_MC4_CE_ADDR 0xffffff
552#define V_MC4_CE_ADDR(x) ((x) << S_MC4_CE_ADDR)
553#define G_MC4_CE_ADDR(x) (((x) >> S_MC4_CE_ADDR) & M_MC4_CE_ADDR)
554
555#define A_MC4_CE_DATA0 0x1a0
556#define A_MC4_CE_DATA1 0x1a4
557#define A_MC4_CE_DATA2 0x1a8
558#define A_MC4_CE_DATA3 0x1ac
559#define A_MC4_CE_DATA4 0x1b0
560#define A_MC4_UE_ADDR 0x1b4
561
562#define S_MC4_UE_ADDR 4
563#define M_MC4_UE_ADDR 0xffffff
564#define V_MC4_UE_ADDR(x) ((x) << S_MC4_UE_ADDR)
565#define G_MC4_UE_ADDR(x) (((x) >> S_MC4_UE_ADDR) & M_MC4_UE_ADDR)
566
567#define A_MC4_UE_DATA0 0x1b8
568#define A_MC4_UE_DATA1 0x1bc
569#define A_MC4_UE_DATA2 0x1c0
570#define A_MC4_UE_DATA3 0x1c4
571#define A_MC4_UE_DATA4 0x1c8
572#define A_MC4_BD_ADDR 0x1cc
573
574#define S_MC4_BACK_DOOR_ADDR 0
575#define M_MC4_BACK_DOOR_ADDR 0xfffffff
576#define V_MC4_BACK_DOOR_ADDR(x) ((x) << S_MC4_BACK_DOOR_ADDR)
577#define G_MC4_BACK_DOOR_ADDR(x) (((x) >> S_MC4_BACK_DOOR_ADDR) & M_MC4_BACK_DOOR_ADDR)
578
579#define A_MC4_BD_DATA0 0x1d0
580#define A_MC4_BD_DATA1 0x1d4
581#define A_MC4_BD_DATA2 0x1d8
582#define A_MC4_BD_DATA3 0x1dc
583#define A_MC4_BD_DATA4 0x1e0
584#define A_MC4_BD_OP 0x1e4
585
586#define S_OPERATION 0
587#define V_OPERATION(x) ((x) << S_OPERATION)
588#define F_OPERATION V_OPERATION(1U)
589
590#define A_MC4_BIST_ADDR_BEG 0x1e8
591#define A_MC4_BIST_ADDR_END 0x1ec
592#define A_MC4_BIST_DATA 0x1f0
593#define A_MC4_BIST_OP 0x1f4
594#define A_MC4_INT_ENABLE 0x1f8
595
596#define S_MC4_CORR_ERR 0
597#define V_MC4_CORR_ERR(x) ((x) << S_MC4_CORR_ERR)
598#define F_MC4_CORR_ERR V_MC4_CORR_ERR(1U)
599
600#define S_MC4_UNCORR_ERR 1
601#define V_MC4_UNCORR_ERR(x) ((x) << S_MC4_UNCORR_ERR)
602#define F_MC4_UNCORR_ERR V_MC4_UNCORR_ERR(1U)
603
604#define S_MC4_ADDR_ERR 2
605#define V_MC4_ADDR_ERR(x) ((x) << S_MC4_ADDR_ERR)
606#define F_MC4_ADDR_ERR V_MC4_ADDR_ERR(1U)
607
608#define A_MC4_INT_CAUSE 0x1fc
160 609
610/* TPI registers */
161#define A_TPI_ADDR 0x280 611#define A_TPI_ADDR 0x280
612
613#define S_TPI_ADDRESS 0
614#define M_TPI_ADDRESS 0xffffff
615#define V_TPI_ADDRESS(x) ((x) << S_TPI_ADDRESS)
616#define G_TPI_ADDRESS(x) (((x) >> S_TPI_ADDRESS) & M_TPI_ADDRESS)
617
162#define A_TPI_WR_DATA 0x284 618#define A_TPI_WR_DATA 0x284
163#define A_TPI_RD_DATA 0x288 619#define A_TPI_RD_DATA 0x288
164#define A_TPI_CSR 0x28c 620#define A_TPI_CSR 0x28c
@@ -171,6 +627,10 @@
171#define V_TPIRDY(x) ((x) << S_TPIRDY) 627#define V_TPIRDY(x) ((x) << S_TPIRDY)
172#define F_TPIRDY V_TPIRDY(1U) 628#define F_TPIRDY V_TPIRDY(1U)
173 629
630#define S_INT_DIR 31
631#define V_INT_DIR(x) ((x) << S_INT_DIR)
632#define F_INT_DIR V_INT_DIR(1U)
633
174#define A_TPI_PAR 0x29c 634#define A_TPI_PAR 0x29c
175 635
176#define S_TPIPAR 0 636#define S_TPIPAR 0
@@ -178,14 +638,26 @@
178#define V_TPIPAR(x) ((x) << S_TPIPAR) 638#define V_TPIPAR(x) ((x) << S_TPIPAR)
179#define G_TPIPAR(x) (((x) >> S_TPIPAR) & M_TPIPAR) 639#define G_TPIPAR(x) (((x) >> S_TPIPAR) & M_TPIPAR)
180 640
181/* TP registers */
182 641
642/* TP registers */
183#define A_TP_IN_CONFIG 0x300 643#define A_TP_IN_CONFIG 0x300
184 644
645#define S_TP_IN_CSPI_TUNNEL 0
646#define V_TP_IN_CSPI_TUNNEL(x) ((x) << S_TP_IN_CSPI_TUNNEL)
647#define F_TP_IN_CSPI_TUNNEL V_TP_IN_CSPI_TUNNEL(1U)
648
649#define S_TP_IN_CSPI_ETHERNET 1
650#define V_TP_IN_CSPI_ETHERNET(x) ((x) << S_TP_IN_CSPI_ETHERNET)
651#define F_TP_IN_CSPI_ETHERNET V_TP_IN_CSPI_ETHERNET(1U)
652
185#define S_TP_IN_CSPI_CPL 3 653#define S_TP_IN_CSPI_CPL 3
186#define V_TP_IN_CSPI_CPL(x) ((x) << S_TP_IN_CSPI_CPL) 654#define V_TP_IN_CSPI_CPL(x) ((x) << S_TP_IN_CSPI_CPL)
187#define F_TP_IN_CSPI_CPL V_TP_IN_CSPI_CPL(1U) 655#define F_TP_IN_CSPI_CPL V_TP_IN_CSPI_CPL(1U)
188 656
657#define S_TP_IN_CSPI_POS 4
658#define V_TP_IN_CSPI_POS(x) ((x) << S_TP_IN_CSPI_POS)
659#define F_TP_IN_CSPI_POS V_TP_IN_CSPI_POS(1U)
660
189#define S_TP_IN_CSPI_CHECK_IP_CSUM 5 661#define S_TP_IN_CSPI_CHECK_IP_CSUM 5
190#define V_TP_IN_CSPI_CHECK_IP_CSUM(x) ((x) << S_TP_IN_CSPI_CHECK_IP_CSUM) 662#define V_TP_IN_CSPI_CHECK_IP_CSUM(x) ((x) << S_TP_IN_CSPI_CHECK_IP_CSUM)
191#define F_TP_IN_CSPI_CHECK_IP_CSUM V_TP_IN_CSPI_CHECK_IP_CSUM(1U) 663#define F_TP_IN_CSPI_CHECK_IP_CSUM V_TP_IN_CSPI_CHECK_IP_CSUM(1U)
@@ -194,10 +666,22 @@
194#define V_TP_IN_CSPI_CHECK_TCP_CSUM(x) ((x) << S_TP_IN_CSPI_CHECK_TCP_CSUM) 666#define V_TP_IN_CSPI_CHECK_TCP_CSUM(x) ((x) << S_TP_IN_CSPI_CHECK_TCP_CSUM)
195#define F_TP_IN_CSPI_CHECK_TCP_CSUM V_TP_IN_CSPI_CHECK_TCP_CSUM(1U) 667#define F_TP_IN_CSPI_CHECK_TCP_CSUM V_TP_IN_CSPI_CHECK_TCP_CSUM(1U)
196 668
669#define S_TP_IN_ESPI_TUNNEL 7
670#define V_TP_IN_ESPI_TUNNEL(x) ((x) << S_TP_IN_ESPI_TUNNEL)
671#define F_TP_IN_ESPI_TUNNEL V_TP_IN_ESPI_TUNNEL(1U)
672
197#define S_TP_IN_ESPI_ETHERNET 8 673#define S_TP_IN_ESPI_ETHERNET 8
198#define V_TP_IN_ESPI_ETHERNET(x) ((x) << S_TP_IN_ESPI_ETHERNET) 674#define V_TP_IN_ESPI_ETHERNET(x) ((x) << S_TP_IN_ESPI_ETHERNET)
199#define F_TP_IN_ESPI_ETHERNET V_TP_IN_ESPI_ETHERNET(1U) 675#define F_TP_IN_ESPI_ETHERNET V_TP_IN_ESPI_ETHERNET(1U)
200 676
677#define S_TP_IN_ESPI_CPL 10
678#define V_TP_IN_ESPI_CPL(x) ((x) << S_TP_IN_ESPI_CPL)
679#define F_TP_IN_ESPI_CPL V_TP_IN_ESPI_CPL(1U)
680
681#define S_TP_IN_ESPI_POS 11
682#define V_TP_IN_ESPI_POS(x) ((x) << S_TP_IN_ESPI_POS)
683#define F_TP_IN_ESPI_POS V_TP_IN_ESPI_POS(1U)
684
201#define S_TP_IN_ESPI_CHECK_IP_CSUM 12 685#define S_TP_IN_ESPI_CHECK_IP_CSUM 12
202#define V_TP_IN_ESPI_CHECK_IP_CSUM(x) ((x) << S_TP_IN_ESPI_CHECK_IP_CSUM) 686#define V_TP_IN_ESPI_CHECK_IP_CSUM(x) ((x) << S_TP_IN_ESPI_CHECK_IP_CSUM)
203#define F_TP_IN_ESPI_CHECK_IP_CSUM V_TP_IN_ESPI_CHECK_IP_CSUM(1U) 687#define F_TP_IN_ESPI_CHECK_IP_CSUM V_TP_IN_ESPI_CHECK_IP_CSUM(1U)
@@ -212,14 +696,42 @@
212 696
213#define A_TP_OUT_CONFIG 0x304 697#define A_TP_OUT_CONFIG 0x304
214 698
699#define S_TP_OUT_C_ETH 0
700#define V_TP_OUT_C_ETH(x) ((x) << S_TP_OUT_C_ETH)
701#define F_TP_OUT_C_ETH V_TP_OUT_C_ETH(1U)
702
215#define S_TP_OUT_CSPI_CPL 2 703#define S_TP_OUT_CSPI_CPL 2
216#define V_TP_OUT_CSPI_CPL(x) ((x) << S_TP_OUT_CSPI_CPL) 704#define V_TP_OUT_CSPI_CPL(x) ((x) << S_TP_OUT_CSPI_CPL)
217#define F_TP_OUT_CSPI_CPL V_TP_OUT_CSPI_CPL(1U) 705#define F_TP_OUT_CSPI_CPL V_TP_OUT_CSPI_CPL(1U)
218 706
707#define S_TP_OUT_CSPI_POS 3
708#define V_TP_OUT_CSPI_POS(x) ((x) << S_TP_OUT_CSPI_POS)
709#define F_TP_OUT_CSPI_POS V_TP_OUT_CSPI_POS(1U)
710
711#define S_TP_OUT_CSPI_GENERATE_IP_CSUM 4
712#define V_TP_OUT_CSPI_GENERATE_IP_CSUM(x) ((x) << S_TP_OUT_CSPI_GENERATE_IP_CSUM)
713#define F_TP_OUT_CSPI_GENERATE_IP_CSUM V_TP_OUT_CSPI_GENERATE_IP_CSUM(1U)
714
715#define S_TP_OUT_CSPI_GENERATE_TCP_CSUM 5
716#define V_TP_OUT_CSPI_GENERATE_TCP_CSUM(x) ((x) << S_TP_OUT_CSPI_GENERATE_TCP_CSUM)
717#define F_TP_OUT_CSPI_GENERATE_TCP_CSUM V_TP_OUT_CSPI_GENERATE_TCP_CSUM(1U)
718
219#define S_TP_OUT_ESPI_ETHERNET 6 719#define S_TP_OUT_ESPI_ETHERNET 6
220#define V_TP_OUT_ESPI_ETHERNET(x) ((x) << S_TP_OUT_ESPI_ETHERNET) 720#define V_TP_OUT_ESPI_ETHERNET(x) ((x) << S_TP_OUT_ESPI_ETHERNET)
221#define F_TP_OUT_ESPI_ETHERNET V_TP_OUT_ESPI_ETHERNET(1U) 721#define F_TP_OUT_ESPI_ETHERNET V_TP_OUT_ESPI_ETHERNET(1U)
222 722
723#define S_TP_OUT_ESPI_TAG_ETHERNET 7
724#define V_TP_OUT_ESPI_TAG_ETHERNET(x) ((x) << S_TP_OUT_ESPI_TAG_ETHERNET)
725#define F_TP_OUT_ESPI_TAG_ETHERNET V_TP_OUT_ESPI_TAG_ETHERNET(1U)
726
727#define S_TP_OUT_ESPI_CPL 8
728#define V_TP_OUT_ESPI_CPL(x) ((x) << S_TP_OUT_ESPI_CPL)
729#define F_TP_OUT_ESPI_CPL V_TP_OUT_ESPI_CPL(1U)
730
731#define S_TP_OUT_ESPI_POS 9
732#define V_TP_OUT_ESPI_POS(x) ((x) << S_TP_OUT_ESPI_POS)
733#define F_TP_OUT_ESPI_POS V_TP_OUT_ESPI_POS(1U)
734
223#define S_TP_OUT_ESPI_GENERATE_IP_CSUM 10 735#define S_TP_OUT_ESPI_GENERATE_IP_CSUM 10
224#define V_TP_OUT_ESPI_GENERATE_IP_CSUM(x) ((x) << S_TP_OUT_ESPI_GENERATE_IP_CSUM) 736#define V_TP_OUT_ESPI_GENERATE_IP_CSUM(x) ((x) << S_TP_OUT_ESPI_GENERATE_IP_CSUM)
225#define F_TP_OUT_ESPI_GENERATE_IP_CSUM V_TP_OUT_ESPI_GENERATE_IP_CSUM(1U) 737#define F_TP_OUT_ESPI_GENERATE_IP_CSUM V_TP_OUT_ESPI_GENERATE_IP_CSUM(1U)
@@ -233,6 +745,16 @@
233#define S_IP_TTL 0 745#define S_IP_TTL 0
234#define M_IP_TTL 0xff 746#define M_IP_TTL 0xff
235#define V_IP_TTL(x) ((x) << S_IP_TTL) 747#define V_IP_TTL(x) ((x) << S_IP_TTL)
748#define G_IP_TTL(x) (((x) >> S_IP_TTL) & M_IP_TTL)
749
750#define S_TCAM_SERVER_REGION_USAGE 8
751#define M_TCAM_SERVER_REGION_USAGE 0x3
752#define V_TCAM_SERVER_REGION_USAGE(x) ((x) << S_TCAM_SERVER_REGION_USAGE)
753#define G_TCAM_SERVER_REGION_USAGE(x) (((x) >> S_TCAM_SERVER_REGION_USAGE) & M_TCAM_SERVER_REGION_USAGE)
754
755#define S_QOS_MAPPING 10
756#define V_QOS_MAPPING(x) ((x) << S_QOS_MAPPING)
757#define F_QOS_MAPPING V_QOS_MAPPING(1U)
236 758
237#define S_TCP_CSUM 11 759#define S_TCP_CSUM 11
238#define V_TCP_CSUM(x) ((x) << S_TCP_CSUM) 760#define V_TCP_CSUM(x) ((x) << S_TCP_CSUM)
@@ -246,31 +768,476 @@
246#define V_IP_CSUM(x) ((x) << S_IP_CSUM) 768#define V_IP_CSUM(x) ((x) << S_IP_CSUM)
247#define F_IP_CSUM V_IP_CSUM(1U) 769#define F_IP_CSUM V_IP_CSUM(1U)
248 770
771#define S_IP_ID_SPLIT 14
772#define V_IP_ID_SPLIT(x) ((x) << S_IP_ID_SPLIT)
773#define F_IP_ID_SPLIT V_IP_ID_SPLIT(1U)
774
249#define S_PATH_MTU 15 775#define S_PATH_MTU 15
250#define V_PATH_MTU(x) ((x) << S_PATH_MTU) 776#define V_PATH_MTU(x) ((x) << S_PATH_MTU)
251#define F_PATH_MTU V_PATH_MTU(1U) 777#define F_PATH_MTU V_PATH_MTU(1U)
252 778
253#define S_5TUPLE_LOOKUP 17 779#define S_5TUPLE_LOOKUP 17
780#define M_5TUPLE_LOOKUP 0x3
254#define V_5TUPLE_LOOKUP(x) ((x) << S_5TUPLE_LOOKUP) 781#define V_5TUPLE_LOOKUP(x) ((x) << S_5TUPLE_LOOKUP)
782#define G_5TUPLE_LOOKUP(x) (((x) >> S_5TUPLE_LOOKUP) & M_5TUPLE_LOOKUP)
783
784#define S_IP_FRAGMENT_DROP 19
785#define V_IP_FRAGMENT_DROP(x) ((x) << S_IP_FRAGMENT_DROP)
786#define F_IP_FRAGMENT_DROP V_IP_FRAGMENT_DROP(1U)
787
788#define S_PING_DROP 20
789#define V_PING_DROP(x) ((x) << S_PING_DROP)
790#define F_PING_DROP V_PING_DROP(1U)
791
792#define S_PROTECT_MODE 21
793#define V_PROTECT_MODE(x) ((x) << S_PROTECT_MODE)
794#define F_PROTECT_MODE V_PROTECT_MODE(1U)
795
796#define S_SYN_COOKIE_ALGORITHM 22
797#define V_SYN_COOKIE_ALGORITHM(x) ((x) << S_SYN_COOKIE_ALGORITHM)
798#define F_SYN_COOKIE_ALGORITHM V_SYN_COOKIE_ALGORITHM(1U)
799
800#define S_ATTACK_FILTER 23
801#define V_ATTACK_FILTER(x) ((x) << S_ATTACK_FILTER)
802#define F_ATTACK_FILTER V_ATTACK_FILTER(1U)
803
804#define S_INTERFACE_TYPE 24
805#define V_INTERFACE_TYPE(x) ((x) << S_INTERFACE_TYPE)
806#define F_INTERFACE_TYPE V_INTERFACE_TYPE(1U)
807
808#define S_DISABLE_RX_FLOW_CONTROL 25
809#define V_DISABLE_RX_FLOW_CONTROL(x) ((x) << S_DISABLE_RX_FLOW_CONTROL)
810#define F_DISABLE_RX_FLOW_CONTROL V_DISABLE_RX_FLOW_CONTROL(1U)
255 811
256#define S_SYN_COOKIE_PARAMETER 26 812#define S_SYN_COOKIE_PARAMETER 26
813#define M_SYN_COOKIE_PARAMETER 0x3f
257#define V_SYN_COOKIE_PARAMETER(x) ((x) << S_SYN_COOKIE_PARAMETER) 814#define V_SYN_COOKIE_PARAMETER(x) ((x) << S_SYN_COOKIE_PARAMETER)
815#define G_SYN_COOKIE_PARAMETER(x) (((x) >> S_SYN_COOKIE_PARAMETER) & M_SYN_COOKIE_PARAMETER)
816
817#define A_TP_GLOBAL_RX_CREDITS 0x30c
818#define A_TP_CM_SIZE 0x310
819#define A_TP_CM_MM_BASE 0x314
820
821#define S_CM_MEMMGR_BASE 0
822#define M_CM_MEMMGR_BASE 0xfffffff
823#define V_CM_MEMMGR_BASE(x) ((x) << S_CM_MEMMGR_BASE)
824#define G_CM_MEMMGR_BASE(x) (((x) >> S_CM_MEMMGR_BASE) & M_CM_MEMMGR_BASE)
825
826#define A_TP_CM_TIMER_BASE 0x318
827
828#define S_CM_TIMER_BASE 0
829#define M_CM_TIMER_BASE 0xfffffff
830#define V_CM_TIMER_BASE(x) ((x) << S_CM_TIMER_BASE)
831#define G_CM_TIMER_BASE(x) (((x) >> S_CM_TIMER_BASE) & M_CM_TIMER_BASE)
832
833#define A_TP_PM_SIZE 0x31c
834#define A_TP_PM_TX_BASE 0x320
835#define A_TP_PM_DEFRAG_BASE 0x324
836#define A_TP_PM_RX_BASE 0x328
837#define A_TP_PM_RX_PG_SIZE 0x32c
838#define A_TP_PM_RX_MAX_PGS 0x330
839#define A_TP_PM_TX_PG_SIZE 0x334
840#define A_TP_PM_TX_MAX_PGS 0x338
841#define A_TP_TCP_OPTIONS 0x340
842
843#define S_TIMESTAMP 0
844#define M_TIMESTAMP 0x3
845#define V_TIMESTAMP(x) ((x) << S_TIMESTAMP)
846#define G_TIMESTAMP(x) (((x) >> S_TIMESTAMP) & M_TIMESTAMP)
847
848#define S_WINDOW_SCALE 2
849#define M_WINDOW_SCALE 0x3
850#define V_WINDOW_SCALE(x) ((x) << S_WINDOW_SCALE)
851#define G_WINDOW_SCALE(x) (((x) >> S_WINDOW_SCALE) & M_WINDOW_SCALE)
852
853#define S_SACK 4
854#define M_SACK 0x3
855#define V_SACK(x) ((x) << S_SACK)
856#define G_SACK(x) (((x) >> S_SACK) & M_SACK)
857
858#define S_ECN 6
859#define M_ECN 0x3
860#define V_ECN(x) ((x) << S_ECN)
861#define G_ECN(x) (((x) >> S_ECN) & M_ECN)
862
863#define S_SACK_ALGORITHM 8
864#define M_SACK_ALGORITHM 0x3
865#define V_SACK_ALGORITHM(x) ((x) << S_SACK_ALGORITHM)
866#define G_SACK_ALGORITHM(x) (((x) >> S_SACK_ALGORITHM) & M_SACK_ALGORITHM)
867
868#define S_MSS 10
869#define V_MSS(x) ((x) << S_MSS)
870#define F_MSS V_MSS(1U)
871
872#define S_DEFAULT_PEER_MSS 16
873#define M_DEFAULT_PEER_MSS 0xffff
874#define V_DEFAULT_PEER_MSS(x) ((x) << S_DEFAULT_PEER_MSS)
875#define G_DEFAULT_PEER_MSS(x) (((x) >> S_DEFAULT_PEER_MSS) & M_DEFAULT_PEER_MSS)
876
877#define A_TP_DACK_CONFIG 0x344
878
879#define S_DACK_MODE 0
880#define V_DACK_MODE(x) ((x) << S_DACK_MODE)
881#define F_DACK_MODE V_DACK_MODE(1U)
882
883#define S_DACK_AUTO_MGMT 1
884#define V_DACK_AUTO_MGMT(x) ((x) << S_DACK_AUTO_MGMT)
885#define F_DACK_AUTO_MGMT V_DACK_AUTO_MGMT(1U)
886
887#define S_DACK_AUTO_CAREFUL 2
888#define V_DACK_AUTO_CAREFUL(x) ((x) << S_DACK_AUTO_CAREFUL)
889#define F_DACK_AUTO_CAREFUL V_DACK_AUTO_CAREFUL(1U)
890
891#define S_DACK_MSS_SELECTOR 3
892#define M_DACK_MSS_SELECTOR 0x3
893#define V_DACK_MSS_SELECTOR(x) ((x) << S_DACK_MSS_SELECTOR)
894#define G_DACK_MSS_SELECTOR(x) (((x) >> S_DACK_MSS_SELECTOR) & M_DACK_MSS_SELECTOR)
895
896#define S_DACK_BYTE_THRESHOLD 5
897#define M_DACK_BYTE_THRESHOLD 0xfffff
898#define V_DACK_BYTE_THRESHOLD(x) ((x) << S_DACK_BYTE_THRESHOLD)
899#define G_DACK_BYTE_THRESHOLD(x) (((x) >> S_DACK_BYTE_THRESHOLD) & M_DACK_BYTE_THRESHOLD)
258 900
259#define A_TP_PC_CONFIG 0x348 901#define A_TP_PC_CONFIG 0x348
902
903#define S_TP_ACCESS_LATENCY 0
904#define M_TP_ACCESS_LATENCY 0xf
905#define V_TP_ACCESS_LATENCY(x) ((x) << S_TP_ACCESS_LATENCY)
906#define G_TP_ACCESS_LATENCY(x) (((x) >> S_TP_ACCESS_LATENCY) & M_TP_ACCESS_LATENCY)
907
908#define S_HELD_FIN_DISABLE 4
909#define V_HELD_FIN_DISABLE(x) ((x) << S_HELD_FIN_DISABLE)
910#define F_HELD_FIN_DISABLE V_HELD_FIN_DISABLE(1U)
911
912#define S_DDP_FC_ENABLE 5
913#define V_DDP_FC_ENABLE(x) ((x) << S_DDP_FC_ENABLE)
914#define F_DDP_FC_ENABLE V_DDP_FC_ENABLE(1U)
915
916#define S_RDMA_ERR_ENABLE 6
917#define V_RDMA_ERR_ENABLE(x) ((x) << S_RDMA_ERR_ENABLE)
918#define F_RDMA_ERR_ENABLE V_RDMA_ERR_ENABLE(1U)
919
920#define S_FAST_PDU_DELIVERY 7
921#define V_FAST_PDU_DELIVERY(x) ((x) << S_FAST_PDU_DELIVERY)
922#define F_FAST_PDU_DELIVERY V_FAST_PDU_DELIVERY(1U)
923
924#define S_CLEAR_FIN 8
925#define V_CLEAR_FIN(x) ((x) << S_CLEAR_FIN)
926#define F_CLEAR_FIN V_CLEAR_FIN(1U)
927
260#define S_DIS_TX_FILL_WIN_PUSH 12 928#define S_DIS_TX_FILL_WIN_PUSH 12
261#define V_DIS_TX_FILL_WIN_PUSH(x) ((x) << S_DIS_TX_FILL_WIN_PUSH) 929#define V_DIS_TX_FILL_WIN_PUSH(x) ((x) << S_DIS_TX_FILL_WIN_PUSH)
262#define F_DIS_TX_FILL_WIN_PUSH V_DIS_TX_FILL_WIN_PUSH(1U) 930#define F_DIS_TX_FILL_WIN_PUSH V_DIS_TX_FILL_WIN_PUSH(1U)
263 931
264#define S_TP_PC_REV 30 932#define S_TP_PC_REV 30
265#define M_TP_PC_REV 0x3 933#define M_TP_PC_REV 0x3
934#define V_TP_PC_REV(x) ((x) << S_TP_PC_REV)
266#define G_TP_PC_REV(x) (((x) >> S_TP_PC_REV) & M_TP_PC_REV) 935#define G_TP_PC_REV(x) (((x) >> S_TP_PC_REV) & M_TP_PC_REV)
936
937#define A_TP_BACKOFF0 0x350
938
939#define S_ELEMENT0 0
940#define M_ELEMENT0 0xff
941#define V_ELEMENT0(x) ((x) << S_ELEMENT0)
942#define G_ELEMENT0(x) (((x) >> S_ELEMENT0) & M_ELEMENT0)
943
944#define S_ELEMENT1 8
945#define M_ELEMENT1 0xff
946#define V_ELEMENT1(x) ((x) << S_ELEMENT1)
947#define G_ELEMENT1(x) (((x) >> S_ELEMENT1) & M_ELEMENT1)
948
949#define S_ELEMENT2 16
950#define M_ELEMENT2 0xff
951#define V_ELEMENT2(x) ((x) << S_ELEMENT2)
952#define G_ELEMENT2(x) (((x) >> S_ELEMENT2) & M_ELEMENT2)
953
954#define S_ELEMENT3 24
955#define M_ELEMENT3 0xff
956#define V_ELEMENT3(x) ((x) << S_ELEMENT3)
957#define G_ELEMENT3(x) (((x) >> S_ELEMENT3) & M_ELEMENT3)
958
959#define A_TP_BACKOFF1 0x354
960#define A_TP_BACKOFF2 0x358
961#define A_TP_BACKOFF3 0x35c
962#define A_TP_PARA_REG0 0x360
963
964#define S_VAR_MULT 0
965#define M_VAR_MULT 0xf
966#define V_VAR_MULT(x) ((x) << S_VAR_MULT)
967#define G_VAR_MULT(x) (((x) >> S_VAR_MULT) & M_VAR_MULT)
968
969#define S_VAR_GAIN 4
970#define M_VAR_GAIN 0xf
971#define V_VAR_GAIN(x) ((x) << S_VAR_GAIN)
972#define G_VAR_GAIN(x) (((x) >> S_VAR_GAIN) & M_VAR_GAIN)
973
974#define S_SRTT_GAIN 8
975#define M_SRTT_GAIN 0xf
976#define V_SRTT_GAIN(x) ((x) << S_SRTT_GAIN)
977#define G_SRTT_GAIN(x) (((x) >> S_SRTT_GAIN) & M_SRTT_GAIN)
978
979#define S_RTTVAR_INIT 12
980#define M_RTTVAR_INIT 0xf
981#define V_RTTVAR_INIT(x) ((x) << S_RTTVAR_INIT)
982#define G_RTTVAR_INIT(x) (((x) >> S_RTTVAR_INIT) & M_RTTVAR_INIT)
983
984#define S_DUP_THRESH 20
985#define M_DUP_THRESH 0xf
986#define V_DUP_THRESH(x) ((x) << S_DUP_THRESH)
987#define G_DUP_THRESH(x) (((x) >> S_DUP_THRESH) & M_DUP_THRESH)
988
989#define S_INIT_CONG_WIN 24
990#define M_INIT_CONG_WIN 0x7
991#define V_INIT_CONG_WIN(x) ((x) << S_INIT_CONG_WIN)
992#define G_INIT_CONG_WIN(x) (((x) >> S_INIT_CONG_WIN) & M_INIT_CONG_WIN)
993
994#define A_TP_PARA_REG1 0x364
995
996#define S_INITIAL_SLOW_START_THRESHOLD 0
997#define M_INITIAL_SLOW_START_THRESHOLD 0xffff
998#define V_INITIAL_SLOW_START_THRESHOLD(x) ((x) << S_INITIAL_SLOW_START_THRESHOLD)
999#define G_INITIAL_SLOW_START_THRESHOLD(x) (((x) >> S_INITIAL_SLOW_START_THRESHOLD) & M_INITIAL_SLOW_START_THRESHOLD)
1000
1001#define S_RECEIVE_BUFFER_SIZE 16
1002#define M_RECEIVE_BUFFER_SIZE 0xffff
1003#define V_RECEIVE_BUFFER_SIZE(x) ((x) << S_RECEIVE_BUFFER_SIZE)
1004#define G_RECEIVE_BUFFER_SIZE(x) (((x) >> S_RECEIVE_BUFFER_SIZE) & M_RECEIVE_BUFFER_SIZE)
1005
1006#define A_TP_PARA_REG2 0x368
1007
1008#define S_RX_COALESCE_SIZE 0
1009#define M_RX_COALESCE_SIZE 0xffff
1010#define V_RX_COALESCE_SIZE(x) ((x) << S_RX_COALESCE_SIZE)
1011#define G_RX_COALESCE_SIZE(x) (((x) >> S_RX_COALESCE_SIZE) & M_RX_COALESCE_SIZE)
1012
1013#define S_MAX_RX_SIZE 16
1014#define M_MAX_RX_SIZE 0xffff
1015#define V_MAX_RX_SIZE(x) ((x) << S_MAX_RX_SIZE)
1016#define G_MAX_RX_SIZE(x) (((x) >> S_MAX_RX_SIZE) & M_MAX_RX_SIZE)
1017
1018#define A_TP_PARA_REG3 0x36c
1019
1020#define S_RX_COALESCING_PSH_DELIVER 0
1021#define V_RX_COALESCING_PSH_DELIVER(x) ((x) << S_RX_COALESCING_PSH_DELIVER)
1022#define F_RX_COALESCING_PSH_DELIVER V_RX_COALESCING_PSH_DELIVER(1U)
1023
1024#define S_RX_COALESCING_ENABLE 1
1025#define V_RX_COALESCING_ENABLE(x) ((x) << S_RX_COALESCING_ENABLE)
1026#define F_RX_COALESCING_ENABLE V_RX_COALESCING_ENABLE(1U)
1027
1028#define S_TAHOE_ENABLE 2
1029#define V_TAHOE_ENABLE(x) ((x) << S_TAHOE_ENABLE)
1030#define F_TAHOE_ENABLE V_TAHOE_ENABLE(1U)
1031
1032#define S_MAX_REORDER_FRAGMENTS 12
1033#define M_MAX_REORDER_FRAGMENTS 0x7
1034#define V_MAX_REORDER_FRAGMENTS(x) ((x) << S_MAX_REORDER_FRAGMENTS)
1035#define G_MAX_REORDER_FRAGMENTS(x) (((x) >> S_MAX_REORDER_FRAGMENTS) & M_MAX_REORDER_FRAGMENTS)
1036
1037#define A_TP_TIMER_RESOLUTION 0x390
1038
1039#define S_DELAYED_ACK_TIMER_RESOLUTION 0
1040#define M_DELAYED_ACK_TIMER_RESOLUTION 0x3f
1041#define V_DELAYED_ACK_TIMER_RESOLUTION(x) ((x) << S_DELAYED_ACK_TIMER_RESOLUTION)
1042#define G_DELAYED_ACK_TIMER_RESOLUTION(x) (((x) >> S_DELAYED_ACK_TIMER_RESOLUTION) & M_DELAYED_ACK_TIMER_RESOLUTION)
1043
1044#define S_GENERIC_TIMER_RESOLUTION 16
1045#define M_GENERIC_TIMER_RESOLUTION 0x3f
1046#define V_GENERIC_TIMER_RESOLUTION(x) ((x) << S_GENERIC_TIMER_RESOLUTION)
1047#define G_GENERIC_TIMER_RESOLUTION(x) (((x) >> S_GENERIC_TIMER_RESOLUTION) & M_GENERIC_TIMER_RESOLUTION)
1048
1049#define A_TP_2MSL 0x394
1050
1051#define S_2MSL 0
1052#define M_2MSL 0x3fffffff
1053#define V_2MSL(x) ((x) << S_2MSL)
1054#define G_2MSL(x) (((x) >> S_2MSL) & M_2MSL)
1055
1056#define A_TP_RXT_MIN 0x398
1057
1058#define S_RETRANSMIT_TIMER_MIN 0
1059#define M_RETRANSMIT_TIMER_MIN 0xffff
1060#define V_RETRANSMIT_TIMER_MIN(x) ((x) << S_RETRANSMIT_TIMER_MIN)
1061#define G_RETRANSMIT_TIMER_MIN(x) (((x) >> S_RETRANSMIT_TIMER_MIN) & M_RETRANSMIT_TIMER_MIN)
1062
1063#define A_TP_RXT_MAX 0x39c
1064
1065#define S_RETRANSMIT_TIMER_MAX 0
1066#define M_RETRANSMIT_TIMER_MAX 0x3fffffff
1067#define V_RETRANSMIT_TIMER_MAX(x) ((x) << S_RETRANSMIT_TIMER_MAX)
1068#define G_RETRANSMIT_TIMER_MAX(x) (((x) >> S_RETRANSMIT_TIMER_MAX) & M_RETRANSMIT_TIMER_MAX)
1069
1070#define A_TP_PERS_MIN 0x3a0
1071
1072#define S_PERSIST_TIMER_MIN 0
1073#define M_PERSIST_TIMER_MIN 0xffff
1074#define V_PERSIST_TIMER_MIN(x) ((x) << S_PERSIST_TIMER_MIN)
1075#define G_PERSIST_TIMER_MIN(x) (((x) >> S_PERSIST_TIMER_MIN) & M_PERSIST_TIMER_MIN)
1076
1077#define A_TP_PERS_MAX 0x3a4
1078
1079#define S_PERSIST_TIMER_MAX 0
1080#define M_PERSIST_TIMER_MAX 0x3fffffff
1081#define V_PERSIST_TIMER_MAX(x) ((x) << S_PERSIST_TIMER_MAX)
1082#define G_PERSIST_TIMER_MAX(x) (((x) >> S_PERSIST_TIMER_MAX) & M_PERSIST_TIMER_MAX)
1083
1084#define A_TP_KEEP_IDLE 0x3ac
1085
1086#define S_KEEP_ALIVE_IDLE_TIME 0
1087#define M_KEEP_ALIVE_IDLE_TIME 0x3fffffff
1088#define V_KEEP_ALIVE_IDLE_TIME(x) ((x) << S_KEEP_ALIVE_IDLE_TIME)
1089#define G_KEEP_ALIVE_IDLE_TIME(x) (((x) >> S_KEEP_ALIVE_IDLE_TIME) & M_KEEP_ALIVE_IDLE_TIME)
1090
1091#define A_TP_KEEP_INTVL 0x3b0
1092
1093#define S_KEEP_ALIVE_INTERVAL_TIME 0
1094#define M_KEEP_ALIVE_INTERVAL_TIME 0x3fffffff
1095#define V_KEEP_ALIVE_INTERVAL_TIME(x) ((x) << S_KEEP_ALIVE_INTERVAL_TIME)
1096#define G_KEEP_ALIVE_INTERVAL_TIME(x) (((x) >> S_KEEP_ALIVE_INTERVAL_TIME) & M_KEEP_ALIVE_INTERVAL_TIME)
1097
1098#define A_TP_INIT_SRTT 0x3b4
1099
1100#define S_INITIAL_SRTT 0
1101#define M_INITIAL_SRTT 0xffff
1102#define V_INITIAL_SRTT(x) ((x) << S_INITIAL_SRTT)
1103#define G_INITIAL_SRTT(x) (((x) >> S_INITIAL_SRTT) & M_INITIAL_SRTT)
1104
1105#define A_TP_DACK_TIME 0x3b8
1106
1107#define S_DELAYED_ACK_TIME 0
1108#define M_DELAYED_ACK_TIME 0x7ff
1109#define V_DELAYED_ACK_TIME(x) ((x) << S_DELAYED_ACK_TIME)
1110#define G_DELAYED_ACK_TIME(x) (((x) >> S_DELAYED_ACK_TIME) & M_DELAYED_ACK_TIME)
1111
1112#define A_TP_FINWAIT2_TIME 0x3bc
1113
1114#define S_FINWAIT2_TIME 0
1115#define M_FINWAIT2_TIME 0x3fffffff
1116#define V_FINWAIT2_TIME(x) ((x) << S_FINWAIT2_TIME)
1117#define G_FINWAIT2_TIME(x) (((x) >> S_FINWAIT2_TIME) & M_FINWAIT2_TIME)
1118
1119#define A_TP_FAST_FINWAIT2_TIME 0x3c0
1120
1121#define S_FAST_FINWAIT2_TIME 0
1122#define M_FAST_FINWAIT2_TIME 0x3fffffff
1123#define V_FAST_FINWAIT2_TIME(x) ((x) << S_FAST_FINWAIT2_TIME)
1124#define G_FAST_FINWAIT2_TIME(x) (((x) >> S_FAST_FINWAIT2_TIME) & M_FAST_FINWAIT2_TIME)
1125
1126#define A_TP_SHIFT_CNT 0x3c4
1127
1128#define S_KEEPALIVE_MAX 0
1129#define M_KEEPALIVE_MAX 0xff
1130#define V_KEEPALIVE_MAX(x) ((x) << S_KEEPALIVE_MAX)
1131#define G_KEEPALIVE_MAX(x) (((x) >> S_KEEPALIVE_MAX) & M_KEEPALIVE_MAX)
1132
1133#define S_WINDOWPROBE_MAX 8
1134#define M_WINDOWPROBE_MAX 0xff
1135#define V_WINDOWPROBE_MAX(x) ((x) << S_WINDOWPROBE_MAX)
1136#define G_WINDOWPROBE_MAX(x) (((x) >> S_WINDOWPROBE_MAX) & M_WINDOWPROBE_MAX)
1137
1138#define S_RETRANSMISSION_MAX 16
1139#define M_RETRANSMISSION_MAX 0xff
1140#define V_RETRANSMISSION_MAX(x) ((x) << S_RETRANSMISSION_MAX)
1141#define G_RETRANSMISSION_MAX(x) (((x) >> S_RETRANSMISSION_MAX) & M_RETRANSMISSION_MAX)
1142
1143#define S_SYN_MAX 24
1144#define M_SYN_MAX 0xff
1145#define V_SYN_MAX(x) ((x) << S_SYN_MAX)
1146#define G_SYN_MAX(x) (((x) >> S_SYN_MAX) & M_SYN_MAX)
1147
1148#define A_TP_QOS_REG0 0x3e0
1149
1150#define S_L3_VALUE 0
1151#define M_L3_VALUE 0x3f
1152#define V_L3_VALUE(x) ((x) << S_L3_VALUE)
1153#define G_L3_VALUE(x) (((x) >> S_L3_VALUE) & M_L3_VALUE)
1154
1155#define A_TP_QOS_REG1 0x3e4
1156#define A_TP_QOS_REG2 0x3e8
1157#define A_TP_QOS_REG3 0x3ec
1158#define A_TP_QOS_REG4 0x3f0
1159#define A_TP_QOS_REG5 0x3f4
1160#define A_TP_QOS_REG6 0x3f8
1161#define A_TP_QOS_REG7 0x3fc
1162#define A_TP_MTU_REG0 0x404
1163#define A_TP_MTU_REG1 0x408
1164#define A_TP_MTU_REG2 0x40c
1165#define A_TP_MTU_REG3 0x410
1166#define A_TP_MTU_REG4 0x414
1167#define A_TP_MTU_REG5 0x418
1168#define A_TP_MTU_REG6 0x41c
1169#define A_TP_MTU_REG7 0x420
267#define A_TP_RESET 0x44c 1170#define A_TP_RESET 0x44c
1171
268#define S_TP_RESET 0 1172#define S_TP_RESET 0
269#define V_TP_RESET(x) ((x) << S_TP_RESET) 1173#define V_TP_RESET(x) ((x) << S_TP_RESET)
270#define F_TP_RESET V_TP_RESET(1U) 1174#define F_TP_RESET V_TP_RESET(1U)
271 1175
1176#define S_CM_MEMMGR_INIT 1
1177#define V_CM_MEMMGR_INIT(x) ((x) << S_CM_MEMMGR_INIT)
1178#define F_CM_MEMMGR_INIT V_CM_MEMMGR_INIT(1U)
1179
1180#define A_TP_MIB_INDEX 0x450
1181#define A_TP_MIB_DATA 0x454
1182#define A_TP_SYNC_TIME_HI 0x458
1183#define A_TP_SYNC_TIME_LO 0x45c
1184#define A_TP_CM_MM_RX_FLST_BASE 0x460
1185
1186#define S_CM_MEMMGR_RX_FREE_LIST_BASE 0
1187#define M_CM_MEMMGR_RX_FREE_LIST_BASE 0xfffffff
1188#define V_CM_MEMMGR_RX_FREE_LIST_BASE(x) ((x) << S_CM_MEMMGR_RX_FREE_LIST_BASE)
1189#define G_CM_MEMMGR_RX_FREE_LIST_BASE(x) (((x) >> S_CM_MEMMGR_RX_FREE_LIST_BASE) & M_CM_MEMMGR_RX_FREE_LIST_BASE)
1190
1191#define A_TP_CM_MM_TX_FLST_BASE 0x464
1192
1193#define S_CM_MEMMGR_TX_FREE_LIST_BASE 0
1194#define M_CM_MEMMGR_TX_FREE_LIST_BASE 0xfffffff
1195#define V_CM_MEMMGR_TX_FREE_LIST_BASE(x) ((x) << S_CM_MEMMGR_TX_FREE_LIST_BASE)
1196#define G_CM_MEMMGR_TX_FREE_LIST_BASE(x) (((x) >> S_CM_MEMMGR_TX_FREE_LIST_BASE) & M_CM_MEMMGR_TX_FREE_LIST_BASE)
1197
1198#define A_TP_CM_MM_P_FLST_BASE 0x468
1199
1200#define S_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE 0
1201#define M_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE 0xfffffff
1202#define V_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE(x) ((x) << S_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE)
1203#define G_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE(x) (((x) >> S_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE) & M_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE)
1204
1205#define A_TP_CM_MM_MAX_P 0x46c
1206
1207#define S_CM_MEMMGR_MAX_PSTRUCT 0
1208#define M_CM_MEMMGR_MAX_PSTRUCT 0xfffffff
1209#define V_CM_MEMMGR_MAX_PSTRUCT(x) ((x) << S_CM_MEMMGR_MAX_PSTRUCT)
1210#define G_CM_MEMMGR_MAX_PSTRUCT(x) (((x) >> S_CM_MEMMGR_MAX_PSTRUCT) & M_CM_MEMMGR_MAX_PSTRUCT)
1211
272#define A_TP_INT_ENABLE 0x470 1212#define A_TP_INT_ENABLE 0x470
1213
1214#define S_TX_FREE_LIST_EMPTY 0
1215#define V_TX_FREE_LIST_EMPTY(x) ((x) << S_TX_FREE_LIST_EMPTY)
1216#define F_TX_FREE_LIST_EMPTY V_TX_FREE_LIST_EMPTY(1U)
1217
1218#define S_RX_FREE_LIST_EMPTY 1
1219#define V_RX_FREE_LIST_EMPTY(x) ((x) << S_RX_FREE_LIST_EMPTY)
1220#define F_RX_FREE_LIST_EMPTY V_RX_FREE_LIST_EMPTY(1U)
1221
273#define A_TP_INT_CAUSE 0x474 1222#define A_TP_INT_CAUSE 0x474
1223#define A_TP_TIMER_SEPARATOR 0x4a4
1224
1225#define S_DISABLE_PAST_TIMER_INSERTION 0
1226#define V_DISABLE_PAST_TIMER_INSERTION(x) ((x) << S_DISABLE_PAST_TIMER_INSERTION)
1227#define F_DISABLE_PAST_TIMER_INSERTION V_DISABLE_PAST_TIMER_INSERTION(1U)
1228
1229#define S_MODULATION_TIMER_SEPARATOR 1
1230#define M_MODULATION_TIMER_SEPARATOR 0x7fff
1231#define V_MODULATION_TIMER_SEPARATOR(x) ((x) << S_MODULATION_TIMER_SEPARATOR)
1232#define G_MODULATION_TIMER_SEPARATOR(x) (((x) >> S_MODULATION_TIMER_SEPARATOR) & M_MODULATION_TIMER_SEPARATOR)
1233
1234#define S_GLOBAL_TIMER_SEPARATOR 16
1235#define M_GLOBAL_TIMER_SEPARATOR 0xffff
1236#define V_GLOBAL_TIMER_SEPARATOR(x) ((x) << S_GLOBAL_TIMER_SEPARATOR)
1237#define G_GLOBAL_TIMER_SEPARATOR(x) (((x) >> S_GLOBAL_TIMER_SEPARATOR) & M_GLOBAL_TIMER_SEPARATOR)
1238
1239#define A_TP_CM_FC_MODE 0x4b0
1240#define A_TP_PC_CONGESTION_CNTL 0x4b4
274#define A_TP_TX_DROP_CONFIG 0x4b8 1241#define A_TP_TX_DROP_CONFIG 0x4b8
275 1242
276#define S_ENABLE_TX_DROP 31 1243#define S_ENABLE_TX_DROP 31
@@ -282,12 +1249,108 @@
282#define F_ENABLE_TX_ERROR V_ENABLE_TX_ERROR(1U) 1249#define F_ENABLE_TX_ERROR V_ENABLE_TX_ERROR(1U)
283 1250
284#define S_DROP_TICKS_CNT 4 1251#define S_DROP_TICKS_CNT 4
1252#define M_DROP_TICKS_CNT 0x3ffffff
285#define V_DROP_TICKS_CNT(x) ((x) << S_DROP_TICKS_CNT) 1253#define V_DROP_TICKS_CNT(x) ((x) << S_DROP_TICKS_CNT)
1254#define G_DROP_TICKS_CNT(x) (((x) >> S_DROP_TICKS_CNT) & M_DROP_TICKS_CNT)
286 1255
287#define S_NUM_PKTS_DROPPED 0 1256#define S_NUM_PKTS_DROPPED 0
1257#define M_NUM_PKTS_DROPPED 0xf
288#define V_NUM_PKTS_DROPPED(x) ((x) << S_NUM_PKTS_DROPPED) 1258#define V_NUM_PKTS_DROPPED(x) ((x) << S_NUM_PKTS_DROPPED)
1259#define G_NUM_PKTS_DROPPED(x) (((x) >> S_NUM_PKTS_DROPPED) & M_NUM_PKTS_DROPPED)
1260
1261#define A_TP_TX_DROP_COUNT 0x4bc
1262
1263/* RAT registers */
1264#define A_RAT_ROUTE_CONTROL 0x580
1265
1266#define S_USE_ROUTE_TABLE 0
1267#define V_USE_ROUTE_TABLE(x) ((x) << S_USE_ROUTE_TABLE)
1268#define F_USE_ROUTE_TABLE V_USE_ROUTE_TABLE(1U)
1269
1270#define S_ENABLE_CSPI 1
1271#define V_ENABLE_CSPI(x) ((x) << S_ENABLE_CSPI)
1272#define F_ENABLE_CSPI V_ENABLE_CSPI(1U)
1273
1274#define S_ENABLE_PCIX 2
1275#define V_ENABLE_PCIX(x) ((x) << S_ENABLE_PCIX)
1276#define F_ENABLE_PCIX V_ENABLE_PCIX(1U)
1277
1278#define A_RAT_ROUTE_TABLE_INDEX 0x584
1279
1280#define S_ROUTE_TABLE_INDEX 0
1281#define M_ROUTE_TABLE_INDEX 0xf
1282#define V_ROUTE_TABLE_INDEX(x) ((x) << S_ROUTE_TABLE_INDEX)
1283#define G_ROUTE_TABLE_INDEX(x) (((x) >> S_ROUTE_TABLE_INDEX) & M_ROUTE_TABLE_INDEX)
1284
1285#define A_RAT_ROUTE_TABLE_DATA 0x588
1286#define A_RAT_NO_ROUTE 0x58c
1287
1288#define S_CPL_OPCODE 0
1289#define M_CPL_OPCODE 0xff
1290#define V_CPL_OPCODE(x) ((x) << S_CPL_OPCODE)
1291#define G_CPL_OPCODE(x) (((x) >> S_CPL_OPCODE) & M_CPL_OPCODE)
1292
1293#define A_RAT_INTR_ENABLE 0x590
1294
1295#define S_ZEROROUTEERROR 0
1296#define V_ZEROROUTEERROR(x) ((x) << S_ZEROROUTEERROR)
1297#define F_ZEROROUTEERROR V_ZEROROUTEERROR(1U)
1298
1299#define S_CSPIFRAMINGERROR 1
1300#define V_CSPIFRAMINGERROR(x) ((x) << S_CSPIFRAMINGERROR)
1301#define F_CSPIFRAMINGERROR V_CSPIFRAMINGERROR(1U)
1302
1303#define S_SGEFRAMINGERROR 2
1304#define V_SGEFRAMINGERROR(x) ((x) << S_SGEFRAMINGERROR)
1305#define F_SGEFRAMINGERROR V_SGEFRAMINGERROR(1U)
1306
1307#define S_TPFRAMINGERROR 3
1308#define V_TPFRAMINGERROR(x) ((x) << S_TPFRAMINGERROR)
1309#define F_TPFRAMINGERROR V_TPFRAMINGERROR(1U)
1310
1311#define A_RAT_INTR_CAUSE 0x594
289 1312
290/* CSPI registers */ 1313/* CSPI registers */
1314#define A_CSPI_RX_AE_WM 0x810
1315#define A_CSPI_RX_AF_WM 0x814
1316#define A_CSPI_CALENDAR_LEN 0x818
1317
1318#define S_CALENDARLENGTH 0
1319#define M_CALENDARLENGTH 0xffff
1320#define V_CALENDARLENGTH(x) ((x) << S_CALENDARLENGTH)
1321#define G_CALENDARLENGTH(x) (((x) >> S_CALENDARLENGTH) & M_CALENDARLENGTH)
1322
1323#define A_CSPI_FIFO_STATUS_ENABLE 0x820
1324
1325#define S_FIFOSTATUSENABLE 0
1326#define V_FIFOSTATUSENABLE(x) ((x) << S_FIFOSTATUSENABLE)
1327#define F_FIFOSTATUSENABLE V_FIFOSTATUSENABLE(1U)
1328
1329#define A_CSPI_MAXBURST1_MAXBURST2 0x828
1330
1331#define S_MAXBURST1 0
1332#define M_MAXBURST1 0xffff
1333#define V_MAXBURST1(x) ((x) << S_MAXBURST1)
1334#define G_MAXBURST1(x) (((x) >> S_MAXBURST1) & M_MAXBURST1)
1335
1336#define S_MAXBURST2 16
1337#define M_MAXBURST2 0xffff
1338#define V_MAXBURST2(x) ((x) << S_MAXBURST2)
1339#define G_MAXBURST2(x) (((x) >> S_MAXBURST2) & M_MAXBURST2)
1340
1341#define A_CSPI_TRAIN 0x82c
1342
1343#define S_CSPI_TRAIN_ALPHA 0
1344#define M_CSPI_TRAIN_ALPHA 0xffff
1345#define V_CSPI_TRAIN_ALPHA(x) ((x) << S_CSPI_TRAIN_ALPHA)
1346#define G_CSPI_TRAIN_ALPHA(x) (((x) >> S_CSPI_TRAIN_ALPHA) & M_CSPI_TRAIN_ALPHA)
1347
1348#define S_CSPI_TRAIN_DATA_MAXT 16
1349#define M_CSPI_TRAIN_DATA_MAXT 0xffff
1350#define V_CSPI_TRAIN_DATA_MAXT(x) ((x) << S_CSPI_TRAIN_DATA_MAXT)
1351#define G_CSPI_TRAIN_DATA_MAXT(x) (((x) >> S_CSPI_TRAIN_DATA_MAXT) & M_CSPI_TRAIN_DATA_MAXT)
1352
1353#define A_CSPI_INTR_STATUS 0x848
291 1354
292#define S_DIP4ERR 0 1355#define S_DIP4ERR 0
293#define V_DIP4ERR(x) ((x) << S_DIP4ERR) 1356#define V_DIP4ERR(x) ((x) << S_DIP4ERR)
@@ -309,22 +1372,63 @@
309#define V_RAMPARITYERR(x) ((x) << S_RAMPARITYERR) 1372#define V_RAMPARITYERR(x) ((x) << S_RAMPARITYERR)
310#define F_RAMPARITYERR V_RAMPARITYERR(1U) 1373#define F_RAMPARITYERR V_RAMPARITYERR(1U)
311 1374
312/* ESPI registers */ 1375#define A_CSPI_INTR_ENABLE 0x84c
313 1376
1377/* ESPI registers */
314#define A_ESPI_SCH_TOKEN0 0x880 1378#define A_ESPI_SCH_TOKEN0 0x880
1379
1380#define S_SCHTOKEN0 0
1381#define M_SCHTOKEN0 0xffff
1382#define V_SCHTOKEN0(x) ((x) << S_SCHTOKEN0)
1383#define G_SCHTOKEN0(x) (((x) >> S_SCHTOKEN0) & M_SCHTOKEN0)
1384
315#define A_ESPI_SCH_TOKEN1 0x884 1385#define A_ESPI_SCH_TOKEN1 0x884
1386
1387#define S_SCHTOKEN1 0
1388#define M_SCHTOKEN1 0xffff
1389#define V_SCHTOKEN1(x) ((x) << S_SCHTOKEN1)
1390#define G_SCHTOKEN1(x) (((x) >> S_SCHTOKEN1) & M_SCHTOKEN1)
1391
316#define A_ESPI_SCH_TOKEN2 0x888 1392#define A_ESPI_SCH_TOKEN2 0x888
1393
1394#define S_SCHTOKEN2 0
1395#define M_SCHTOKEN2 0xffff
1396#define V_SCHTOKEN2(x) ((x) << S_SCHTOKEN2)
1397#define G_SCHTOKEN2(x) (((x) >> S_SCHTOKEN2) & M_SCHTOKEN2)
1398
317#define A_ESPI_SCH_TOKEN3 0x88c 1399#define A_ESPI_SCH_TOKEN3 0x88c
1400
1401#define S_SCHTOKEN3 0
1402#define M_SCHTOKEN3 0xffff
1403#define V_SCHTOKEN3(x) ((x) << S_SCHTOKEN3)
1404#define G_SCHTOKEN3(x) (((x) >> S_SCHTOKEN3) & M_SCHTOKEN3)
1405
318#define A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK 0x890 1406#define A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK 0x890
1407
1408#define S_ALMOSTEMPTY 0
1409#define M_ALMOSTEMPTY 0xffff
1410#define V_ALMOSTEMPTY(x) ((x) << S_ALMOSTEMPTY)
1411#define G_ALMOSTEMPTY(x) (((x) >> S_ALMOSTEMPTY) & M_ALMOSTEMPTY)
1412
319#define A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK 0x894 1413#define A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK 0x894
1414
1415#define S_ALMOSTFULL 0
1416#define M_ALMOSTFULL 0xffff
1417#define V_ALMOSTFULL(x) ((x) << S_ALMOSTFULL)
1418#define G_ALMOSTFULL(x) (((x) >> S_ALMOSTFULL) & M_ALMOSTFULL)
1419
320#define A_ESPI_CALENDAR_LENGTH 0x898 1420#define A_ESPI_CALENDAR_LENGTH 0x898
321#define A_PORT_CONFIG 0x89c 1421#define A_PORT_CONFIG 0x89c
322 1422
323#define S_RX_NPORTS 0 1423#define S_RX_NPORTS 0
1424#define M_RX_NPORTS 0xff
324#define V_RX_NPORTS(x) ((x) << S_RX_NPORTS) 1425#define V_RX_NPORTS(x) ((x) << S_RX_NPORTS)
1426#define G_RX_NPORTS(x) (((x) >> S_RX_NPORTS) & M_RX_NPORTS)
325 1427
326#define S_TX_NPORTS 8 1428#define S_TX_NPORTS 8
1429#define M_TX_NPORTS 0xff
327#define V_TX_NPORTS(x) ((x) << S_TX_NPORTS) 1430#define V_TX_NPORTS(x) ((x) << S_TX_NPORTS)
1431#define G_TX_NPORTS(x) (((x) >> S_TX_NPORTS) & M_TX_NPORTS)
328 1432
329#define A_ESPI_FIFO_STATUS_ENABLE 0x8a0 1433#define A_ESPI_FIFO_STATUS_ENABLE 0x8a0
330 1434
@@ -332,12 +1436,124 @@
332#define V_RXSTATUSENABLE(x) ((x) << S_RXSTATUSENABLE) 1436#define V_RXSTATUSENABLE(x) ((x) << S_RXSTATUSENABLE)
333#define F_RXSTATUSENABLE V_RXSTATUSENABLE(1U) 1437#define F_RXSTATUSENABLE V_RXSTATUSENABLE(1U)
334 1438
1439#define S_TXDROPENABLE 1
1440#define V_TXDROPENABLE(x) ((x) << S_TXDROPENABLE)
1441#define F_TXDROPENABLE V_TXDROPENABLE(1U)
1442
1443#define S_RXENDIANMODE 2
1444#define V_RXENDIANMODE(x) ((x) << S_RXENDIANMODE)
1445#define F_RXENDIANMODE V_RXENDIANMODE(1U)
1446
1447#define S_TXENDIANMODE 3
1448#define V_TXENDIANMODE(x) ((x) << S_TXENDIANMODE)
1449#define F_TXENDIANMODE V_TXENDIANMODE(1U)
1450
335#define S_INTEL1010MODE 4 1451#define S_INTEL1010MODE 4
336#define V_INTEL1010MODE(x) ((x) << S_INTEL1010MODE) 1452#define V_INTEL1010MODE(x) ((x) << S_INTEL1010MODE)
337#define F_INTEL1010MODE V_INTEL1010MODE(1U) 1453#define F_INTEL1010MODE V_INTEL1010MODE(1U)
338 1454
339#define A_ESPI_MAXBURST1_MAXBURST2 0x8a8 1455#define A_ESPI_MAXBURST1_MAXBURST2 0x8a8
340#define A_ESPI_TRAIN 0x8ac 1456#define A_ESPI_TRAIN 0x8ac
1457
1458#define S_MAXTRAINALPHA 0
1459#define M_MAXTRAINALPHA 0xffff
1460#define V_MAXTRAINALPHA(x) ((x) << S_MAXTRAINALPHA)
1461#define G_MAXTRAINALPHA(x) (((x) >> S_MAXTRAINALPHA) & M_MAXTRAINALPHA)
1462
1463#define S_MAXTRAINDATA 16
1464#define M_MAXTRAINDATA 0xffff
1465#define V_MAXTRAINDATA(x) ((x) << S_MAXTRAINDATA)
1466#define G_MAXTRAINDATA(x) (((x) >> S_MAXTRAINDATA) & M_MAXTRAINDATA)
1467
1468#define A_RAM_STATUS 0x8b0
1469
1470#define S_RXFIFOPARITYERROR 0
1471#define M_RXFIFOPARITYERROR 0x3ff
1472#define V_RXFIFOPARITYERROR(x) ((x) << S_RXFIFOPARITYERROR)
1473#define G_RXFIFOPARITYERROR(x) (((x) >> S_RXFIFOPARITYERROR) & M_RXFIFOPARITYERROR)
1474
1475#define S_TXFIFOPARITYERROR 10
1476#define M_TXFIFOPARITYERROR 0x3ff
1477#define V_TXFIFOPARITYERROR(x) ((x) << S_TXFIFOPARITYERROR)
1478#define G_TXFIFOPARITYERROR(x) (((x) >> S_TXFIFOPARITYERROR) & M_TXFIFOPARITYERROR)
1479
1480#define S_RXFIFOOVERFLOW 20
1481#define M_RXFIFOOVERFLOW 0x3ff
1482#define V_RXFIFOOVERFLOW(x) ((x) << S_RXFIFOOVERFLOW)
1483#define G_RXFIFOOVERFLOW(x) (((x) >> S_RXFIFOOVERFLOW) & M_RXFIFOOVERFLOW)
1484
1485#define A_TX_DROP_COUNT0 0x8b4
1486
1487#define S_TXPORT0DROPCNT 0
1488#define M_TXPORT0DROPCNT 0xffff
1489#define V_TXPORT0DROPCNT(x) ((x) << S_TXPORT0DROPCNT)
1490#define G_TXPORT0DROPCNT(x) (((x) >> S_TXPORT0DROPCNT) & M_TXPORT0DROPCNT)
1491
1492#define S_TXPORT1DROPCNT 16
1493#define M_TXPORT1DROPCNT 0xffff
1494#define V_TXPORT1DROPCNT(x) ((x) << S_TXPORT1DROPCNT)
1495#define G_TXPORT1DROPCNT(x) (((x) >> S_TXPORT1DROPCNT) & M_TXPORT1DROPCNT)
1496
1497#define A_TX_DROP_COUNT1 0x8b8
1498
1499#define S_TXPORT2DROPCNT 0
1500#define M_TXPORT2DROPCNT 0xffff
1501#define V_TXPORT2DROPCNT(x) ((x) << S_TXPORT2DROPCNT)
1502#define G_TXPORT2DROPCNT(x) (((x) >> S_TXPORT2DROPCNT) & M_TXPORT2DROPCNT)
1503
1504#define S_TXPORT3DROPCNT 16
1505#define M_TXPORT3DROPCNT 0xffff
1506#define V_TXPORT3DROPCNT(x) ((x) << S_TXPORT3DROPCNT)
1507#define G_TXPORT3DROPCNT(x) (((x) >> S_TXPORT3DROPCNT) & M_TXPORT3DROPCNT)
1508
1509#define A_RX_DROP_COUNT0 0x8bc
1510
1511#define S_RXPORT0DROPCNT 0
1512#define M_RXPORT0DROPCNT 0xffff
1513#define V_RXPORT0DROPCNT(x) ((x) << S_RXPORT0DROPCNT)
1514#define G_RXPORT0DROPCNT(x) (((x) >> S_RXPORT0DROPCNT) & M_RXPORT0DROPCNT)
1515
1516#define S_RXPORT1DROPCNT 16
1517#define M_RXPORT1DROPCNT 0xffff
1518#define V_RXPORT1DROPCNT(x) ((x) << S_RXPORT1DROPCNT)
1519#define G_RXPORT1DROPCNT(x) (((x) >> S_RXPORT1DROPCNT) & M_RXPORT1DROPCNT)
1520
1521#define A_RX_DROP_COUNT1 0x8c0
1522
1523#define S_RXPORT2DROPCNT 0
1524#define M_RXPORT2DROPCNT 0xffff
1525#define V_RXPORT2DROPCNT(x) ((x) << S_RXPORT2DROPCNT)
1526#define G_RXPORT2DROPCNT(x) (((x) >> S_RXPORT2DROPCNT) & M_RXPORT2DROPCNT)
1527
1528#define S_RXPORT3DROPCNT 16
1529#define M_RXPORT3DROPCNT 0xffff
1530#define V_RXPORT3DROPCNT(x) ((x) << S_RXPORT3DROPCNT)
1531#define G_RXPORT3DROPCNT(x) (((x) >> S_RXPORT3DROPCNT) & M_RXPORT3DROPCNT)
1532
1533#define A_DIP4_ERROR_COUNT 0x8c4
1534
1535#define S_DIP4ERRORCNT 0
1536#define M_DIP4ERRORCNT 0xfff
1537#define V_DIP4ERRORCNT(x) ((x) << S_DIP4ERRORCNT)
1538#define G_DIP4ERRORCNT(x) (((x) >> S_DIP4ERRORCNT) & M_DIP4ERRORCNT)
1539
1540#define S_DIP4ERRORCNTSHADOW 12
1541#define M_DIP4ERRORCNTSHADOW 0xfff
1542#define V_DIP4ERRORCNTSHADOW(x) ((x) << S_DIP4ERRORCNTSHADOW)
1543#define G_DIP4ERRORCNTSHADOW(x) (((x) >> S_DIP4ERRORCNTSHADOW) & M_DIP4ERRORCNTSHADOW)
1544
1545#define S_TRICN_RX_TRAIN_ERR 24
1546#define V_TRICN_RX_TRAIN_ERR(x) ((x) << S_TRICN_RX_TRAIN_ERR)
1547#define F_TRICN_RX_TRAIN_ERR V_TRICN_RX_TRAIN_ERR(1U)
1548
1549#define S_TRICN_RX_TRAINING 25
1550#define V_TRICN_RX_TRAINING(x) ((x) << S_TRICN_RX_TRAINING)
1551#define F_TRICN_RX_TRAINING V_TRICN_RX_TRAINING(1U)
1552
1553#define S_TRICN_RX_TRAIN_OK 26
1554#define V_TRICN_RX_TRAIN_OK(x) ((x) << S_TRICN_RX_TRAIN_OK)
1555#define F_TRICN_RX_TRAIN_OK V_TRICN_RX_TRAIN_OK(1U)
1556
341#define A_ESPI_INTR_STATUS 0x8c8 1557#define A_ESPI_INTR_STATUS 0x8c8
342 1558
343#define S_DIP2PARITYERR 5 1559#define S_DIP2PARITYERR 5
@@ -347,19 +1563,56 @@
347#define A_ESPI_INTR_ENABLE 0x8cc 1563#define A_ESPI_INTR_ENABLE 0x8cc
348#define A_RX_DROP_THRESHOLD 0x8d0 1564#define A_RX_DROP_THRESHOLD 0x8d0
349#define A_ESPI_RX_RESET 0x8ec 1565#define A_ESPI_RX_RESET 0x8ec
1566
1567#define S_ESPI_RX_LNK_RST 0
1568#define V_ESPI_RX_LNK_RST(x) ((x) << S_ESPI_RX_LNK_RST)
1569#define F_ESPI_RX_LNK_RST V_ESPI_RX_LNK_RST(1U)
1570
1571#define S_ESPI_RX_CORE_RST 1
1572#define V_ESPI_RX_CORE_RST(x) ((x) << S_ESPI_RX_CORE_RST)
1573#define F_ESPI_RX_CORE_RST V_ESPI_RX_CORE_RST(1U)
1574
1575#define S_RX_CLK_STATUS 2
1576#define V_RX_CLK_STATUS(x) ((x) << S_RX_CLK_STATUS)
1577#define F_RX_CLK_STATUS V_RX_CLK_STATUS(1U)
1578
350#define A_ESPI_MISC_CONTROL 0x8f0 1579#define A_ESPI_MISC_CONTROL 0x8f0
351 1580
352#define S_OUT_OF_SYNC_COUNT 0 1581#define S_OUT_OF_SYNC_COUNT 0
1582#define M_OUT_OF_SYNC_COUNT 0xf
353#define V_OUT_OF_SYNC_COUNT(x) ((x) << S_OUT_OF_SYNC_COUNT) 1583#define V_OUT_OF_SYNC_COUNT(x) ((x) << S_OUT_OF_SYNC_COUNT)
1584#define G_OUT_OF_SYNC_COUNT(x) (((x) >> S_OUT_OF_SYNC_COUNT) & M_OUT_OF_SYNC_COUNT)
1585
1586#define S_DIP2_COUNT_MODE_ENABLE 4
1587#define V_DIP2_COUNT_MODE_ENABLE(x) ((x) << S_DIP2_COUNT_MODE_ENABLE)
1588#define F_DIP2_COUNT_MODE_ENABLE V_DIP2_COUNT_MODE_ENABLE(1U)
354 1589
355#define S_DIP2_PARITY_ERR_THRES 5 1590#define S_DIP2_PARITY_ERR_THRES 5
1591#define M_DIP2_PARITY_ERR_THRES 0xf
356#define V_DIP2_PARITY_ERR_THRES(x) ((x) << S_DIP2_PARITY_ERR_THRES) 1592#define V_DIP2_PARITY_ERR_THRES(x) ((x) << S_DIP2_PARITY_ERR_THRES)
1593#define G_DIP2_PARITY_ERR_THRES(x) (((x) >> S_DIP2_PARITY_ERR_THRES) & M_DIP2_PARITY_ERR_THRES)
357 1594
358#define S_DIP4_THRES 9 1595#define S_DIP4_THRES 9
1596#define M_DIP4_THRES 0xfff
359#define V_DIP4_THRES(x) ((x) << S_DIP4_THRES) 1597#define V_DIP4_THRES(x) ((x) << S_DIP4_THRES)
1598#define G_DIP4_THRES(x) (((x) >> S_DIP4_THRES) & M_DIP4_THRES)
1599
1600#define S_DIP4_THRES_ENABLE 21
1601#define V_DIP4_THRES_ENABLE(x) ((x) << S_DIP4_THRES_ENABLE)
1602#define F_DIP4_THRES_ENABLE V_DIP4_THRES_ENABLE(1U)
1603
1604#define S_FORCE_DISABLE_STATUS 22
1605#define V_FORCE_DISABLE_STATUS(x) ((x) << S_FORCE_DISABLE_STATUS)
1606#define F_FORCE_DISABLE_STATUS V_FORCE_DISABLE_STATUS(1U)
1607
1608#define S_DYNAMIC_DESKEW 23
1609#define V_DYNAMIC_DESKEW(x) ((x) << S_DYNAMIC_DESKEW)
1610#define F_DYNAMIC_DESKEW V_DYNAMIC_DESKEW(1U)
360 1611
361#define S_MONITORED_PORT_NUM 25 1612#define S_MONITORED_PORT_NUM 25
1613#define M_MONITORED_PORT_NUM 0x3
362#define V_MONITORED_PORT_NUM(x) ((x) << S_MONITORED_PORT_NUM) 1614#define V_MONITORED_PORT_NUM(x) ((x) << S_MONITORED_PORT_NUM)
1615#define G_MONITORED_PORT_NUM(x) (((x) >> S_MONITORED_PORT_NUM) & M_MONITORED_PORT_NUM)
363 1616
364#define S_MONITORED_DIRECTION 27 1617#define S_MONITORED_DIRECTION 27
365#define V_MONITORED_DIRECTION(x) ((x) << S_MONITORED_DIRECTION) 1618#define V_MONITORED_DIRECTION(x) ((x) << S_MONITORED_DIRECTION)
@@ -370,33 +1623,125 @@
370#define F_MONITORED_INTERFACE V_MONITORED_INTERFACE(1U) 1623#define F_MONITORED_INTERFACE V_MONITORED_INTERFACE(1U)
371 1624
372#define A_ESPI_DIP2_ERR_COUNT 0x8f4 1625#define A_ESPI_DIP2_ERR_COUNT 0x8f4
1626
1627#define S_DIP2_ERR_CNT 0
1628#define M_DIP2_ERR_CNT 0xf
1629#define V_DIP2_ERR_CNT(x) ((x) << S_DIP2_ERR_CNT)
1630#define G_DIP2_ERR_CNT(x) (((x) >> S_DIP2_ERR_CNT) & M_DIP2_ERR_CNT)
1631
373#define A_ESPI_CMD_ADDR 0x8f8 1632#define A_ESPI_CMD_ADDR 0x8f8
374 1633
375#define S_WRITE_DATA 0 1634#define S_WRITE_DATA 0
1635#define M_WRITE_DATA 0xff
376#define V_WRITE_DATA(x) ((x) << S_WRITE_DATA) 1636#define V_WRITE_DATA(x) ((x) << S_WRITE_DATA)
1637#define G_WRITE_DATA(x) (((x) >> S_WRITE_DATA) & M_WRITE_DATA)
377 1638
378#define S_REGISTER_OFFSET 8 1639#define S_REGISTER_OFFSET 8
1640#define M_REGISTER_OFFSET 0xf
379#define V_REGISTER_OFFSET(x) ((x) << S_REGISTER_OFFSET) 1641#define V_REGISTER_OFFSET(x) ((x) << S_REGISTER_OFFSET)
1642#define G_REGISTER_OFFSET(x) (((x) >> S_REGISTER_OFFSET) & M_REGISTER_OFFSET)
380 1643
381#define S_CHANNEL_ADDR 12 1644#define S_CHANNEL_ADDR 12
1645#define M_CHANNEL_ADDR 0xf
382#define V_CHANNEL_ADDR(x) ((x) << S_CHANNEL_ADDR) 1646#define V_CHANNEL_ADDR(x) ((x) << S_CHANNEL_ADDR)
1647#define G_CHANNEL_ADDR(x) (((x) >> S_CHANNEL_ADDR) & M_CHANNEL_ADDR)
383 1648
384#define S_MODULE_ADDR 16 1649#define S_MODULE_ADDR 16
1650#define M_MODULE_ADDR 0x3
385#define V_MODULE_ADDR(x) ((x) << S_MODULE_ADDR) 1651#define V_MODULE_ADDR(x) ((x) << S_MODULE_ADDR)
1652#define G_MODULE_ADDR(x) (((x) >> S_MODULE_ADDR) & M_MODULE_ADDR)
386 1653
387#define S_BUNDLE_ADDR 20 1654#define S_BUNDLE_ADDR 20
1655#define M_BUNDLE_ADDR 0x3
388#define V_BUNDLE_ADDR(x) ((x) << S_BUNDLE_ADDR) 1656#define V_BUNDLE_ADDR(x) ((x) << S_BUNDLE_ADDR)
1657#define G_BUNDLE_ADDR(x) (((x) >> S_BUNDLE_ADDR) & M_BUNDLE_ADDR)
389 1658
390#define S_SPI4_COMMAND 24 1659#define S_SPI4_COMMAND 24
1660#define M_SPI4_COMMAND 0xff
391#define V_SPI4_COMMAND(x) ((x) << S_SPI4_COMMAND) 1661#define V_SPI4_COMMAND(x) ((x) << S_SPI4_COMMAND)
1662#define G_SPI4_COMMAND(x) (((x) >> S_SPI4_COMMAND) & M_SPI4_COMMAND)
392 1663
393#define A_ESPI_GOSTAT 0x8fc 1664#define A_ESPI_GOSTAT 0x8fc
1665
1666#define S_READ_DATA 0
1667#define M_READ_DATA 0xff
1668#define V_READ_DATA(x) ((x) << S_READ_DATA)
1669#define G_READ_DATA(x) (((x) >> S_READ_DATA) & M_READ_DATA)
1670
394#define S_ESPI_CMD_BUSY 8 1671#define S_ESPI_CMD_BUSY 8
395#define V_ESPI_CMD_BUSY(x) ((x) << S_ESPI_CMD_BUSY) 1672#define V_ESPI_CMD_BUSY(x) ((x) << S_ESPI_CMD_BUSY)
396#define F_ESPI_CMD_BUSY V_ESPI_CMD_BUSY(1U) 1673#define F_ESPI_CMD_BUSY V_ESPI_CMD_BUSY(1U)
397 1674
398/* PL registers */ 1675#define S_ERROR_ACK 9
1676#define V_ERROR_ACK(x) ((x) << S_ERROR_ACK)
1677#define F_ERROR_ACK V_ERROR_ACK(1U)
1678
1679#define S_UNMAPPED_ERR 10
1680#define V_UNMAPPED_ERR(x) ((x) << S_UNMAPPED_ERR)
1681#define F_UNMAPPED_ERR V_UNMAPPED_ERR(1U)
1682
1683#define S_TRANSACTION_TIMER 16
1684#define M_TRANSACTION_TIMER 0xff
1685#define V_TRANSACTION_TIMER(x) ((x) << S_TRANSACTION_TIMER)
1686#define G_TRANSACTION_TIMER(x) (((x) >> S_TRANSACTION_TIMER) & M_TRANSACTION_TIMER)
1687
1688
1689/* ULP registers */
1690#define A_ULP_ULIMIT 0x980
1691#define A_ULP_TAGMASK 0x984
1692#define A_ULP_HREG_INDEX 0x988
1693#define A_ULP_HREG_DATA 0x98c
1694#define A_ULP_INT_ENABLE 0x990
1695#define A_ULP_INT_CAUSE 0x994
399 1696
1697#define S_HREG_PAR_ERR 0
1698#define V_HREG_PAR_ERR(x) ((x) << S_HREG_PAR_ERR)
1699#define F_HREG_PAR_ERR V_HREG_PAR_ERR(1U)
1700
1701#define S_EGRS_DATA_PAR_ERR 1
1702#define V_EGRS_DATA_PAR_ERR(x) ((x) << S_EGRS_DATA_PAR_ERR)
1703#define F_EGRS_DATA_PAR_ERR V_EGRS_DATA_PAR_ERR(1U)
1704
1705#define S_INGRS_DATA_PAR_ERR 2
1706#define V_INGRS_DATA_PAR_ERR(x) ((x) << S_INGRS_DATA_PAR_ERR)
1707#define F_INGRS_DATA_PAR_ERR V_INGRS_DATA_PAR_ERR(1U)
1708
1709#define S_PM_INTR 3
1710#define V_PM_INTR(x) ((x) << S_PM_INTR)
1711#define F_PM_INTR V_PM_INTR(1U)
1712
1713#define S_PM_E2C_SYNC_ERR 4
1714#define V_PM_E2C_SYNC_ERR(x) ((x) << S_PM_E2C_SYNC_ERR)
1715#define F_PM_E2C_SYNC_ERR V_PM_E2C_SYNC_ERR(1U)
1716
1717#define S_PM_C2E_SYNC_ERR 5
1718#define V_PM_C2E_SYNC_ERR(x) ((x) << S_PM_C2E_SYNC_ERR)
1719#define F_PM_C2E_SYNC_ERR V_PM_C2E_SYNC_ERR(1U)
1720
1721#define S_PM_E2C_EMPTY_ERR 6
1722#define V_PM_E2C_EMPTY_ERR(x) ((x) << S_PM_E2C_EMPTY_ERR)
1723#define F_PM_E2C_EMPTY_ERR V_PM_E2C_EMPTY_ERR(1U)
1724
1725#define S_PM_C2E_EMPTY_ERR 7
1726#define V_PM_C2E_EMPTY_ERR(x) ((x) << S_PM_C2E_EMPTY_ERR)
1727#define F_PM_C2E_EMPTY_ERR V_PM_C2E_EMPTY_ERR(1U)
1728
1729#define S_PM_PAR_ERR 8
1730#define M_PM_PAR_ERR 0xffff
1731#define V_PM_PAR_ERR(x) ((x) << S_PM_PAR_ERR)
1732#define G_PM_PAR_ERR(x) (((x) >> S_PM_PAR_ERR) & M_PM_PAR_ERR)
1733
1734#define S_PM_E2C_WRT_FULL 24
1735#define V_PM_E2C_WRT_FULL(x) ((x) << S_PM_E2C_WRT_FULL)
1736#define F_PM_E2C_WRT_FULL V_PM_E2C_WRT_FULL(1U)
1737
1738#define S_PM_C2E_WRT_FULL 25
1739#define V_PM_C2E_WRT_FULL(x) ((x) << S_PM_C2E_WRT_FULL)
1740#define F_PM_C2E_WRT_FULL V_PM_C2E_WRT_FULL(1U)
1741
1742#define A_ULP_PIO_CTRL 0x998
1743
1744/* PL registers */
400#define A_PL_ENABLE 0xa00 1745#define A_PL_ENABLE 0xa00
401 1746
402#define S_PL_INTR_SGE_ERR 0 1747#define S_PL_INTR_SGE_ERR 0
@@ -407,14 +1752,38 @@
407#define V_PL_INTR_SGE_DATA(x) ((x) << S_PL_INTR_SGE_DATA) 1752#define V_PL_INTR_SGE_DATA(x) ((x) << S_PL_INTR_SGE_DATA)
408#define F_PL_INTR_SGE_DATA V_PL_INTR_SGE_DATA(1U) 1753#define F_PL_INTR_SGE_DATA V_PL_INTR_SGE_DATA(1U)
409 1754
1755#define S_PL_INTR_MC3 2
1756#define V_PL_INTR_MC3(x) ((x) << S_PL_INTR_MC3)
1757#define F_PL_INTR_MC3 V_PL_INTR_MC3(1U)
1758
1759#define S_PL_INTR_MC4 3
1760#define V_PL_INTR_MC4(x) ((x) << S_PL_INTR_MC4)
1761#define F_PL_INTR_MC4 V_PL_INTR_MC4(1U)
1762
1763#define S_PL_INTR_MC5 4
1764#define V_PL_INTR_MC5(x) ((x) << S_PL_INTR_MC5)
1765#define F_PL_INTR_MC5 V_PL_INTR_MC5(1U)
1766
1767#define S_PL_INTR_RAT 5
1768#define V_PL_INTR_RAT(x) ((x) << S_PL_INTR_RAT)
1769#define F_PL_INTR_RAT V_PL_INTR_RAT(1U)
1770
410#define S_PL_INTR_TP 6 1771#define S_PL_INTR_TP 6
411#define V_PL_INTR_TP(x) ((x) << S_PL_INTR_TP) 1772#define V_PL_INTR_TP(x) ((x) << S_PL_INTR_TP)
412#define F_PL_INTR_TP V_PL_INTR_TP(1U) 1773#define F_PL_INTR_TP V_PL_INTR_TP(1U)
413 1774
1775#define S_PL_INTR_ULP 7
1776#define V_PL_INTR_ULP(x) ((x) << S_PL_INTR_ULP)
1777#define F_PL_INTR_ULP V_PL_INTR_ULP(1U)
1778
414#define S_PL_INTR_ESPI 8 1779#define S_PL_INTR_ESPI 8
415#define V_PL_INTR_ESPI(x) ((x) << S_PL_INTR_ESPI) 1780#define V_PL_INTR_ESPI(x) ((x) << S_PL_INTR_ESPI)
416#define F_PL_INTR_ESPI V_PL_INTR_ESPI(1U) 1781#define F_PL_INTR_ESPI V_PL_INTR_ESPI(1U)
417 1782
1783#define S_PL_INTR_CSPI 9
1784#define V_PL_INTR_CSPI(x) ((x) << S_PL_INTR_CSPI)
1785#define F_PL_INTR_CSPI V_PL_INTR_CSPI(1U)
1786
418#define S_PL_INTR_PCIX 10 1787#define S_PL_INTR_PCIX 10
419#define V_PL_INTR_PCIX(x) ((x) << S_PL_INTR_PCIX) 1788#define V_PL_INTR_PCIX(x) ((x) << S_PL_INTR_PCIX)
420#define F_PL_INTR_PCIX V_PL_INTR_PCIX(1U) 1789#define F_PL_INTR_PCIX V_PL_INTR_PCIX(1U)
@@ -426,43 +1795,374 @@
426#define A_PL_CAUSE 0xa04 1795#define A_PL_CAUSE 0xa04
427 1796
428/* MC5 registers */ 1797/* MC5 registers */
429
430#define A_MC5_CONFIG 0xc04 1798#define A_MC5_CONFIG 0xc04
431 1799
1800#define S_MODE 0
1801#define V_MODE(x) ((x) << S_MODE)
1802#define F_MODE V_MODE(1U)
1803
432#define S_TCAM_RESET 1 1804#define S_TCAM_RESET 1
433#define V_TCAM_RESET(x) ((x) << S_TCAM_RESET) 1805#define V_TCAM_RESET(x) ((x) << S_TCAM_RESET)
434#define F_TCAM_RESET V_TCAM_RESET(1U) 1806#define F_TCAM_RESET V_TCAM_RESET(1U)
435 1807
1808#define S_TCAM_READY 2
1809#define V_TCAM_READY(x) ((x) << S_TCAM_READY)
1810#define F_TCAM_READY V_TCAM_READY(1U)
1811
1812#define S_DBGI_ENABLE 4
1813#define V_DBGI_ENABLE(x) ((x) << S_DBGI_ENABLE)
1814#define F_DBGI_ENABLE V_DBGI_ENABLE(1U)
1815
436#define S_M_BUS_ENABLE 5 1816#define S_M_BUS_ENABLE 5
437#define V_M_BUS_ENABLE(x) ((x) << S_M_BUS_ENABLE) 1817#define V_M_BUS_ENABLE(x) ((x) << S_M_BUS_ENABLE)
438#define F_M_BUS_ENABLE V_M_BUS_ENABLE(1U) 1818#define F_M_BUS_ENABLE V_M_BUS_ENABLE(1U)
439 1819
440/* PCICFG registers */ 1820#define S_PARITY_ENABLE 6
1821#define V_PARITY_ENABLE(x) ((x) << S_PARITY_ENABLE)
1822#define F_PARITY_ENABLE V_PARITY_ENABLE(1U)
1823
1824#define S_SYN_ISSUE_MODE 7
1825#define M_SYN_ISSUE_MODE 0x3
1826#define V_SYN_ISSUE_MODE(x) ((x) << S_SYN_ISSUE_MODE)
1827#define G_SYN_ISSUE_MODE(x) (((x) >> S_SYN_ISSUE_MODE) & M_SYN_ISSUE_MODE)
1828
1829#define S_BUILD 16
1830#define V_BUILD(x) ((x) << S_BUILD)
1831#define F_BUILD V_BUILD(1U)
1832
1833#define S_COMPRESSION_ENABLE 17
1834#define V_COMPRESSION_ENABLE(x) ((x) << S_COMPRESSION_ENABLE)
1835#define F_COMPRESSION_ENABLE V_COMPRESSION_ENABLE(1U)
1836
1837#define S_NUM_LIP 18
1838#define M_NUM_LIP 0x3f
1839#define V_NUM_LIP(x) ((x) << S_NUM_LIP)
1840#define G_NUM_LIP(x) (((x) >> S_NUM_LIP) & M_NUM_LIP)
1841
1842#define S_TCAM_PART_CNT 24
1843#define M_TCAM_PART_CNT 0x3
1844#define V_TCAM_PART_CNT(x) ((x) << S_TCAM_PART_CNT)
1845#define G_TCAM_PART_CNT(x) (((x) >> S_TCAM_PART_CNT) & M_TCAM_PART_CNT)
1846
1847#define S_TCAM_PART_TYPE 26
1848#define M_TCAM_PART_TYPE 0x3
1849#define V_TCAM_PART_TYPE(x) ((x) << S_TCAM_PART_TYPE)
1850#define G_TCAM_PART_TYPE(x) (((x) >> S_TCAM_PART_TYPE) & M_TCAM_PART_TYPE)
1851
1852#define S_TCAM_PART_SIZE 28
1853#define M_TCAM_PART_SIZE 0x3
1854#define V_TCAM_PART_SIZE(x) ((x) << S_TCAM_PART_SIZE)
1855#define G_TCAM_PART_SIZE(x) (((x) >> S_TCAM_PART_SIZE) & M_TCAM_PART_SIZE)
1856
1857#define S_TCAM_PART_TYPE_HI 30
1858#define V_TCAM_PART_TYPE_HI(x) ((x) << S_TCAM_PART_TYPE_HI)
1859#define F_TCAM_PART_TYPE_HI V_TCAM_PART_TYPE_HI(1U)
1860
1861#define A_MC5_SIZE 0xc08
1862
1863#define S_SIZE 0
1864#define M_SIZE 0x3fffff
1865#define V_SIZE(x) ((x) << S_SIZE)
1866#define G_SIZE(x) (((x) >> S_SIZE) & M_SIZE)
1867
1868#define A_MC5_ROUTING_TABLE_INDEX 0xc0c
441 1869
1870#define S_START_OF_ROUTING_TABLE 0
1871#define M_START_OF_ROUTING_TABLE 0x3fffff
1872#define V_START_OF_ROUTING_TABLE(x) ((x) << S_START_OF_ROUTING_TABLE)
1873#define G_START_OF_ROUTING_TABLE(x) (((x) >> S_START_OF_ROUTING_TABLE) & M_START_OF_ROUTING_TABLE)
1874
1875#define A_MC5_SERVER_INDEX 0xc14
1876
1877#define S_START_OF_SERVER_INDEX 0
1878#define M_START_OF_SERVER_INDEX 0x3fffff
1879#define V_START_OF_SERVER_INDEX(x) ((x) << S_START_OF_SERVER_INDEX)
1880#define G_START_OF_SERVER_INDEX(x) (((x) >> S_START_OF_SERVER_INDEX) & M_START_OF_SERVER_INDEX)
1881
1882#define A_MC5_LIP_RAM_ADDR 0xc18
1883
1884#define S_LOCAL_IP_RAM_ADDR 0
1885#define M_LOCAL_IP_RAM_ADDR 0x3f
1886#define V_LOCAL_IP_RAM_ADDR(x) ((x) << S_LOCAL_IP_RAM_ADDR)
1887#define G_LOCAL_IP_RAM_ADDR(x) (((x) >> S_LOCAL_IP_RAM_ADDR) & M_LOCAL_IP_RAM_ADDR)
1888
1889#define S_RAM_WRITE_ENABLE 8
1890#define V_RAM_WRITE_ENABLE(x) ((x) << S_RAM_WRITE_ENABLE)
1891#define F_RAM_WRITE_ENABLE V_RAM_WRITE_ENABLE(1U)
1892
1893#define A_MC5_LIP_RAM_DATA 0xc1c
1894#define A_MC5_RSP_LATENCY 0xc20
1895
1896#define S_SEARCH_RESPONSE_LATENCY 0
1897#define M_SEARCH_RESPONSE_LATENCY 0x1f
1898#define V_SEARCH_RESPONSE_LATENCY(x) ((x) << S_SEARCH_RESPONSE_LATENCY)
1899#define G_SEARCH_RESPONSE_LATENCY(x) (((x) >> S_SEARCH_RESPONSE_LATENCY) & M_SEARCH_RESPONSE_LATENCY)
1900
1901#define S_LEARN_RESPONSE_LATENCY 8
1902#define M_LEARN_RESPONSE_LATENCY 0x1f
1903#define V_LEARN_RESPONSE_LATENCY(x) ((x) << S_LEARN_RESPONSE_LATENCY)
1904#define G_LEARN_RESPONSE_LATENCY(x) (((x) >> S_LEARN_RESPONSE_LATENCY) & M_LEARN_RESPONSE_LATENCY)
1905
1906#define A_MC5_PARITY_LATENCY 0xc24
1907
1908#define S_SRCHLAT 0
1909#define M_SRCHLAT 0x1f
1910#define V_SRCHLAT(x) ((x) << S_SRCHLAT)
1911#define G_SRCHLAT(x) (((x) >> S_SRCHLAT) & M_SRCHLAT)
1912
1913#define S_PARLAT 8
1914#define M_PARLAT 0x1f
1915#define V_PARLAT(x) ((x) << S_PARLAT)
1916#define G_PARLAT(x) (((x) >> S_PARLAT) & M_PARLAT)
1917
1918#define A_MC5_WR_LRN_VERIFY 0xc28
1919
1920#define S_POVEREN 0
1921#define V_POVEREN(x) ((x) << S_POVEREN)
1922#define F_POVEREN V_POVEREN(1U)
1923
1924#define S_LRNVEREN 1
1925#define V_LRNVEREN(x) ((x) << S_LRNVEREN)
1926#define F_LRNVEREN V_LRNVEREN(1U)
1927
1928#define S_VWVEREN 2
1929#define V_VWVEREN(x) ((x) << S_VWVEREN)
1930#define F_VWVEREN V_VWVEREN(1U)
1931
1932#define A_MC5_PART_ID_INDEX 0xc2c
1933
1934#define S_IDINDEX 0
1935#define M_IDINDEX 0xf
1936#define V_IDINDEX(x) ((x) << S_IDINDEX)
1937#define G_IDINDEX(x) (((x) >> S_IDINDEX) & M_IDINDEX)
1938
1939#define A_MC5_RESET_MAX 0xc30
1940
1941#define S_RSTMAX 0
1942#define M_RSTMAX 0x1ff
1943#define V_RSTMAX(x) ((x) << S_RSTMAX)
1944#define G_RSTMAX(x) (((x) >> S_RSTMAX) & M_RSTMAX)
1945
1946#define A_MC5_INT_ENABLE 0xc40
1947
1948#define S_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR 0
1949#define V_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR(x) ((x) << S_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR)
1950#define F_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR V_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR(1U)
1951
1952#define S_MC5_INT_HIT_IN_ACTIVE_REGION_ERR 1
1953#define V_MC5_INT_HIT_IN_ACTIVE_REGION_ERR(x) ((x) << S_MC5_INT_HIT_IN_ACTIVE_REGION_ERR)
1954#define F_MC5_INT_HIT_IN_ACTIVE_REGION_ERR V_MC5_INT_HIT_IN_ACTIVE_REGION_ERR(1U)
1955
1956#define S_MC5_INT_HIT_IN_RT_REGION_ERR 2
1957#define V_MC5_INT_HIT_IN_RT_REGION_ERR(x) ((x) << S_MC5_INT_HIT_IN_RT_REGION_ERR)
1958#define F_MC5_INT_HIT_IN_RT_REGION_ERR V_MC5_INT_HIT_IN_RT_REGION_ERR(1U)
1959
1960#define S_MC5_INT_MISS_ERR 3
1961#define V_MC5_INT_MISS_ERR(x) ((x) << S_MC5_INT_MISS_ERR)
1962#define F_MC5_INT_MISS_ERR V_MC5_INT_MISS_ERR(1U)
1963
1964#define S_MC5_INT_LIP0_ERR 4
1965#define V_MC5_INT_LIP0_ERR(x) ((x) << S_MC5_INT_LIP0_ERR)
1966#define F_MC5_INT_LIP0_ERR V_MC5_INT_LIP0_ERR(1U)
1967
1968#define S_MC5_INT_LIP_MISS_ERR 5
1969#define V_MC5_INT_LIP_MISS_ERR(x) ((x) << S_MC5_INT_LIP_MISS_ERR)
1970#define F_MC5_INT_LIP_MISS_ERR V_MC5_INT_LIP_MISS_ERR(1U)
1971
1972#define S_MC5_INT_PARITY_ERR 6
1973#define V_MC5_INT_PARITY_ERR(x) ((x) << S_MC5_INT_PARITY_ERR)
1974#define F_MC5_INT_PARITY_ERR V_MC5_INT_PARITY_ERR(1U)
1975
1976#define S_MC5_INT_ACTIVE_REGION_FULL 7
1977#define V_MC5_INT_ACTIVE_REGION_FULL(x) ((x) << S_MC5_INT_ACTIVE_REGION_FULL)
1978#define F_MC5_INT_ACTIVE_REGION_FULL V_MC5_INT_ACTIVE_REGION_FULL(1U)
1979
1980#define S_MC5_INT_NFA_SRCH_ERR 8
1981#define V_MC5_INT_NFA_SRCH_ERR(x) ((x) << S_MC5_INT_NFA_SRCH_ERR)
1982#define F_MC5_INT_NFA_SRCH_ERR V_MC5_INT_NFA_SRCH_ERR(1U)
1983
1984#define S_MC5_INT_SYN_COOKIE 9
1985#define V_MC5_INT_SYN_COOKIE(x) ((x) << S_MC5_INT_SYN_COOKIE)
1986#define F_MC5_INT_SYN_COOKIE V_MC5_INT_SYN_COOKIE(1U)
1987
1988#define S_MC5_INT_SYN_COOKIE_BAD 10
1989#define V_MC5_INT_SYN_COOKIE_BAD(x) ((x) << S_MC5_INT_SYN_COOKIE_BAD)
1990#define F_MC5_INT_SYN_COOKIE_BAD V_MC5_INT_SYN_COOKIE_BAD(1U)
1991
1992#define S_MC5_INT_SYN_COOKIE_OFF 11
1993#define V_MC5_INT_SYN_COOKIE_OFF(x) ((x) << S_MC5_INT_SYN_COOKIE_OFF)
1994#define F_MC5_INT_SYN_COOKIE_OFF V_MC5_INT_SYN_COOKIE_OFF(1U)
1995
1996#define S_MC5_INT_UNKNOWN_CMD 15
1997#define V_MC5_INT_UNKNOWN_CMD(x) ((x) << S_MC5_INT_UNKNOWN_CMD)
1998#define F_MC5_INT_UNKNOWN_CMD V_MC5_INT_UNKNOWN_CMD(1U)
1999
2000#define S_MC5_INT_REQUESTQ_PARITY_ERR 16
2001#define V_MC5_INT_REQUESTQ_PARITY_ERR(x) ((x) << S_MC5_INT_REQUESTQ_PARITY_ERR)
2002#define F_MC5_INT_REQUESTQ_PARITY_ERR V_MC5_INT_REQUESTQ_PARITY_ERR(1U)
2003
2004#define S_MC5_INT_DISPATCHQ_PARITY_ERR 17
2005#define V_MC5_INT_DISPATCHQ_PARITY_ERR(x) ((x) << S_MC5_INT_DISPATCHQ_PARITY_ERR)
2006#define F_MC5_INT_DISPATCHQ_PARITY_ERR V_MC5_INT_DISPATCHQ_PARITY_ERR(1U)
2007
2008#define S_MC5_INT_DEL_ACT_EMPTY 18
2009#define V_MC5_INT_DEL_ACT_EMPTY(x) ((x) << S_MC5_INT_DEL_ACT_EMPTY)
2010#define F_MC5_INT_DEL_ACT_EMPTY V_MC5_INT_DEL_ACT_EMPTY(1U)
2011
2012#define A_MC5_INT_CAUSE 0xc44
2013#define A_MC5_INT_TID 0xc48
2014#define A_MC5_INT_PTID 0xc4c
2015#define A_MC5_DBGI_CONFIG 0xc74
2016#define A_MC5_DBGI_REQ_CMD 0xc78
2017
2018#define S_CMDMODE 0
2019#define M_CMDMODE 0x7
2020#define V_CMDMODE(x) ((x) << S_CMDMODE)
2021#define G_CMDMODE(x) (((x) >> S_CMDMODE) & M_CMDMODE)
2022
2023#define S_SADRSEL 4
2024#define V_SADRSEL(x) ((x) << S_SADRSEL)
2025#define F_SADRSEL V_SADRSEL(1U)
2026
2027#define S_WRITE_BURST_SIZE 22
2028#define M_WRITE_BURST_SIZE 0x3ff
2029#define V_WRITE_BURST_SIZE(x) ((x) << S_WRITE_BURST_SIZE)
2030#define G_WRITE_BURST_SIZE(x) (((x) >> S_WRITE_BURST_SIZE) & M_WRITE_BURST_SIZE)
2031
2032#define A_MC5_DBGI_REQ_ADDR0 0xc7c
2033#define A_MC5_DBGI_REQ_ADDR1 0xc80
2034#define A_MC5_DBGI_REQ_ADDR2 0xc84
2035#define A_MC5_DBGI_REQ_DATA0 0xc88
2036#define A_MC5_DBGI_REQ_DATA1 0xc8c
2037#define A_MC5_DBGI_REQ_DATA2 0xc90
2038#define A_MC5_DBGI_REQ_DATA3 0xc94
2039#define A_MC5_DBGI_REQ_DATA4 0xc98
2040#define A_MC5_DBGI_REQ_MASK0 0xc9c
2041#define A_MC5_DBGI_REQ_MASK1 0xca0
2042#define A_MC5_DBGI_REQ_MASK2 0xca4
2043#define A_MC5_DBGI_REQ_MASK3 0xca8
2044#define A_MC5_DBGI_REQ_MASK4 0xcac
2045#define A_MC5_DBGI_RSP_STATUS 0xcb0
2046
2047#define S_DBGI_RSP_VALID 0
2048#define V_DBGI_RSP_VALID(x) ((x) << S_DBGI_RSP_VALID)
2049#define F_DBGI_RSP_VALID V_DBGI_RSP_VALID(1U)
2050
2051#define S_DBGI_RSP_HIT 1
2052#define V_DBGI_RSP_HIT(x) ((x) << S_DBGI_RSP_HIT)
2053#define F_DBGI_RSP_HIT V_DBGI_RSP_HIT(1U)
2054
2055#define S_DBGI_RSP_ERR 2
2056#define V_DBGI_RSP_ERR(x) ((x) << S_DBGI_RSP_ERR)
2057#define F_DBGI_RSP_ERR V_DBGI_RSP_ERR(1U)
2058
2059#define S_DBGI_RSP_ERR_REASON 8
2060#define M_DBGI_RSP_ERR_REASON 0x7
2061#define V_DBGI_RSP_ERR_REASON(x) ((x) << S_DBGI_RSP_ERR_REASON)
2062#define G_DBGI_RSP_ERR_REASON(x) (((x) >> S_DBGI_RSP_ERR_REASON) & M_DBGI_RSP_ERR_REASON)
2063
2064#define A_MC5_DBGI_RSP_DATA0 0xcb4
2065#define A_MC5_DBGI_RSP_DATA1 0xcb8
2066#define A_MC5_DBGI_RSP_DATA2 0xcbc
2067#define A_MC5_DBGI_RSP_DATA3 0xcc0
2068#define A_MC5_DBGI_RSP_DATA4 0xcc4
2069#define A_MC5_DBGI_RSP_LAST_CMD 0xcc8
2070#define A_MC5_POPEN_DATA_WR_CMD 0xccc
2071#define A_MC5_POPEN_MASK_WR_CMD 0xcd0
2072#define A_MC5_AOPEN_SRCH_CMD 0xcd4
2073#define A_MC5_AOPEN_LRN_CMD 0xcd8
2074#define A_MC5_SYN_SRCH_CMD 0xcdc
2075#define A_MC5_SYN_LRN_CMD 0xce0
2076#define A_MC5_ACK_SRCH_CMD 0xce4
2077#define A_MC5_ACK_LRN_CMD 0xce8
2078#define A_MC5_ILOOKUP_CMD 0xcec
2079#define A_MC5_ELOOKUP_CMD 0xcf0
2080#define A_MC5_DATA_WRITE_CMD 0xcf4
2081#define A_MC5_DATA_READ_CMD 0xcf8
2082#define A_MC5_MASK_WRITE_CMD 0xcfc
2083
2084/* PCICFG registers */
442#define A_PCICFG_PM_CSR 0x44 2085#define A_PCICFG_PM_CSR 0x44
443#define A_PCICFG_VPD_ADDR 0x4a 2086#define A_PCICFG_VPD_ADDR 0x4a
444 2087
2088#define S_VPD_ADDR 0
2089#define M_VPD_ADDR 0x7fff
2090#define V_VPD_ADDR(x) ((x) << S_VPD_ADDR)
2091#define G_VPD_ADDR(x) (((x) >> S_VPD_ADDR) & M_VPD_ADDR)
2092
445#define S_VPD_OP_FLAG 15 2093#define S_VPD_OP_FLAG 15
446#define V_VPD_OP_FLAG(x) ((x) << S_VPD_OP_FLAG) 2094#define V_VPD_OP_FLAG(x) ((x) << S_VPD_OP_FLAG)
447#define F_VPD_OP_FLAG V_VPD_OP_FLAG(1U) 2095#define F_VPD_OP_FLAG V_VPD_OP_FLAG(1U)
448 2096
449#define A_PCICFG_VPD_DATA 0x4c 2097#define A_PCICFG_VPD_DATA 0x4c
450 2098#define A_PCICFG_PCIX_CMD 0x60
451#define A_PCICFG_INTR_ENABLE 0xf4 2099#define A_PCICFG_INTR_ENABLE 0xf4
452#define A_PCICFG_INTR_CAUSE 0xf8
453 2100
2101#define S_MASTER_PARITY_ERR 0
2102#define V_MASTER_PARITY_ERR(x) ((x) << S_MASTER_PARITY_ERR)
2103#define F_MASTER_PARITY_ERR V_MASTER_PARITY_ERR(1U)
2104
2105#define S_SIG_TARGET_ABORT 1
2106#define V_SIG_TARGET_ABORT(x) ((x) << S_SIG_TARGET_ABORT)
2107#define F_SIG_TARGET_ABORT V_SIG_TARGET_ABORT(1U)
2108
2109#define S_RCV_TARGET_ABORT 2
2110#define V_RCV_TARGET_ABORT(x) ((x) << S_RCV_TARGET_ABORT)
2111#define F_RCV_TARGET_ABORT V_RCV_TARGET_ABORT(1U)
2112
2113#define S_RCV_MASTER_ABORT 3
2114#define V_RCV_MASTER_ABORT(x) ((x) << S_RCV_MASTER_ABORT)
2115#define F_RCV_MASTER_ABORT V_RCV_MASTER_ABORT(1U)
2116
2117#define S_SIG_SYS_ERR 4
2118#define V_SIG_SYS_ERR(x) ((x) << S_SIG_SYS_ERR)
2119#define F_SIG_SYS_ERR V_SIG_SYS_ERR(1U)
2120
2121#define S_DET_PARITY_ERR 5
2122#define V_DET_PARITY_ERR(x) ((x) << S_DET_PARITY_ERR)
2123#define F_DET_PARITY_ERR V_DET_PARITY_ERR(1U)
2124
2125#define S_PIO_PARITY_ERR 6
2126#define V_PIO_PARITY_ERR(x) ((x) << S_PIO_PARITY_ERR)
2127#define F_PIO_PARITY_ERR V_PIO_PARITY_ERR(1U)
2128
2129#define S_WF_PARITY_ERR 7
2130#define V_WF_PARITY_ERR(x) ((x) << S_WF_PARITY_ERR)
2131#define F_WF_PARITY_ERR V_WF_PARITY_ERR(1U)
2132
2133#define S_RF_PARITY_ERR 8
2134#define M_RF_PARITY_ERR 0x3
2135#define V_RF_PARITY_ERR(x) ((x) << S_RF_PARITY_ERR)
2136#define G_RF_PARITY_ERR(x) (((x) >> S_RF_PARITY_ERR) & M_RF_PARITY_ERR)
2137
2138#define S_CF_PARITY_ERR 10
2139#define M_CF_PARITY_ERR 0x3
2140#define V_CF_PARITY_ERR(x) ((x) << S_CF_PARITY_ERR)
2141#define G_CF_PARITY_ERR(x) (((x) >> S_CF_PARITY_ERR) & M_CF_PARITY_ERR)
2142
2143#define A_PCICFG_INTR_CAUSE 0xf8
454#define A_PCICFG_MODE 0xfc 2144#define A_PCICFG_MODE 0xfc
455 2145
456#define S_PCI_MODE_64BIT 0 2146#define S_PCI_MODE_64BIT 0
457#define V_PCI_MODE_64BIT(x) ((x) << S_PCI_MODE_64BIT) 2147#define V_PCI_MODE_64BIT(x) ((x) << S_PCI_MODE_64BIT)
458#define F_PCI_MODE_64BIT V_PCI_MODE_64BIT(1U) 2148#define F_PCI_MODE_64BIT V_PCI_MODE_64BIT(1U)
459 2149
2150#define S_PCI_MODE_66MHZ 1
2151#define V_PCI_MODE_66MHZ(x) ((x) << S_PCI_MODE_66MHZ)
2152#define F_PCI_MODE_66MHZ V_PCI_MODE_66MHZ(1U)
2153
2154#define S_PCI_MODE_PCIX_INITPAT 2
2155#define M_PCI_MODE_PCIX_INITPAT 0x7
2156#define V_PCI_MODE_PCIX_INITPAT(x) ((x) << S_PCI_MODE_PCIX_INITPAT)
2157#define G_PCI_MODE_PCIX_INITPAT(x) (((x) >> S_PCI_MODE_PCIX_INITPAT) & M_PCI_MODE_PCIX_INITPAT)
2158
460#define S_PCI_MODE_PCIX 5 2159#define S_PCI_MODE_PCIX 5
461#define V_PCI_MODE_PCIX(x) ((x) << S_PCI_MODE_PCIX) 2160#define V_PCI_MODE_PCIX(x) ((x) << S_PCI_MODE_PCIX)
462#define F_PCI_MODE_PCIX V_PCI_MODE_PCIX(1U) 2161#define F_PCI_MODE_PCIX V_PCI_MODE_PCIX(1U)
463 2162
464#define S_PCI_MODE_CLK 6 2163#define S_PCI_MODE_CLK 6
465#define M_PCI_MODE_CLK 0x3 2164#define M_PCI_MODE_CLK 0x3
2165#define V_PCI_MODE_CLK(x) ((x) << S_PCI_MODE_CLK)
466#define G_PCI_MODE_CLK(x) (((x) >> S_PCI_MODE_CLK) & M_PCI_MODE_CLK) 2166#define G_PCI_MODE_CLK(x) (((x) >> S_PCI_MODE_CLK) & M_PCI_MODE_CLK)
467 2167
468#endif /* _CXGB_REGS_H_ */ 2168#endif /* _CXGB_REGS_H_ */
diff --git a/drivers/net/chelsio/sge.c b/drivers/net/chelsio/sge.c
index 9fb77c6d6c6b..26df2049d849 100644
--- a/drivers/net/chelsio/sge.c
+++ b/drivers/net/chelsio/sge.c
@@ -42,12 +42,14 @@
42#include <linux/types.h> 42#include <linux/types.h>
43#include <linux/errno.h> 43#include <linux/errno.h>
44#include <linux/pci.h> 44#include <linux/pci.h>
45#include <linux/ktime.h>
45#include <linux/netdevice.h> 46#include <linux/netdevice.h>
46#include <linux/etherdevice.h> 47#include <linux/etherdevice.h>
47#include <linux/if_vlan.h> 48#include <linux/if_vlan.h>
48#include <linux/skbuff.h> 49#include <linux/skbuff.h>
49#include <linux/init.h> 50#include <linux/init.h>
50#include <linux/mm.h> 51#include <linux/mm.h>
52#include <linux/tcp.h>
51#include <linux/ip.h> 53#include <linux/ip.h>
52#include <linux/in.h> 54#include <linux/in.h>
53#include <linux/if_arp.h> 55#include <linux/if_arp.h>
@@ -57,10 +59,8 @@
57#include "regs.h" 59#include "regs.h"
58#include "espi.h" 60#include "espi.h"
59 61
60 62/* This belongs in if_ether.h */
61#ifdef NETIF_F_TSO 63#define ETH_P_CPL5 0xf
62#include <linux/tcp.h>
63#endif
64 64
65#define SGE_CMDQ_N 2 65#define SGE_CMDQ_N 2
66#define SGE_FREELQ_N 2 66#define SGE_FREELQ_N 2
@@ -73,6 +73,7 @@
73#define SGE_INTRTIMER_NRES 1000 73#define SGE_INTRTIMER_NRES 1000
74#define SGE_RX_COPY_THRES 256 74#define SGE_RX_COPY_THRES 256
75#define SGE_RX_SM_BUF_SIZE 1536 75#define SGE_RX_SM_BUF_SIZE 1536
76#define SGE_TX_DESC_MAX_PLEN 16384
76 77
77# define SGE_RX_DROP_THRES 2 78# define SGE_RX_DROP_THRES 2
78 79
@@ -184,17 +185,17 @@ struct cmdQ {
184 unsigned long status; /* HW DMA fetch status */ 185 unsigned long status; /* HW DMA fetch status */
185 unsigned int in_use; /* # of in-use command descriptors */ 186 unsigned int in_use; /* # of in-use command descriptors */
186 unsigned int size; /* # of descriptors */ 187 unsigned int size; /* # of descriptors */
187 unsigned int processed; /* total # of descs HW has processed */ 188 unsigned int processed; /* total # of descs HW has processed */
188 unsigned int cleaned; /* total # of descs SW has reclaimed */ 189 unsigned int cleaned; /* total # of descs SW has reclaimed */
189 unsigned int stop_thres; /* SW TX queue suspend threshold */ 190 unsigned int stop_thres; /* SW TX queue suspend threshold */
190 u16 pidx; /* producer index (SW) */ 191 u16 pidx; /* producer index (SW) */
191 u16 cidx; /* consumer index (HW) */ 192 u16 cidx; /* consumer index (HW) */
192 u8 genbit; /* current generation (=valid) bit */ 193 u8 genbit; /* current generation (=valid) bit */
193 u8 sop; /* is next entry start of packet? */ 194 u8 sop; /* is next entry start of packet? */
194 struct cmdQ_e *entries; /* HW command descriptor Q */ 195 struct cmdQ_e *entries; /* HW command descriptor Q */
195 struct cmdQ_ce *centries; /* SW command context descriptor Q */ 196 struct cmdQ_ce *centries; /* SW command context descriptor Q */
196 spinlock_t lock; /* Lock to protect cmdQ enqueuing */
197 dma_addr_t dma_addr; /* DMA addr HW command descriptor Q */ 197 dma_addr_t dma_addr; /* DMA addr HW command descriptor Q */
198 spinlock_t lock; /* Lock to protect cmdQ enqueuing */
198}; 199};
199 200
200struct freelQ { 201struct freelQ {
@@ -203,8 +204,8 @@ struct freelQ {
203 u16 pidx; /* producer index (SW) */ 204 u16 pidx; /* producer index (SW) */
204 u16 cidx; /* consumer index (HW) */ 205 u16 cidx; /* consumer index (HW) */
205 u16 rx_buffer_size; /* Buffer size on this free list */ 206 u16 rx_buffer_size; /* Buffer size on this free list */
206 u16 dma_offset; /* DMA offset to align IP headers */ 207 u16 dma_offset; /* DMA offset to align IP headers */
207 u16 recycleq_idx; /* skb recycle q to use */ 208 u16 recycleq_idx; /* skb recycle q to use */
208 u8 genbit; /* current generation (=valid) bit */ 209 u8 genbit; /* current generation (=valid) bit */
209 struct freelQ_e *entries; /* HW freelist descriptor Q */ 210 struct freelQ_e *entries; /* HW freelist descriptor Q */
210 struct freelQ_ce *centries; /* SW freelist context descriptor Q */ 211 struct freelQ_ce *centries; /* SW freelist context descriptor Q */
@@ -226,6 +227,29 @@ enum {
226 CMDQ_STAT_LAST_PKT_DB = 2 /* last packet rung the doorbell */ 227 CMDQ_STAT_LAST_PKT_DB = 2 /* last packet rung the doorbell */
227}; 228};
228 229
230/* T204 TX SW scheduler */
231
232/* Per T204 TX port */
233struct sched_port {
234 unsigned int avail; /* available bits - quota */
235 unsigned int drain_bits_per_1024ns; /* drain rate */
236 unsigned int speed; /* drain rate, mbps */
237 unsigned int mtu; /* mtu size */
238 struct sk_buff_head skbq; /* pending skbs */
239};
240
241/* Per T204 device */
242struct sched {
243 ktime_t last_updated; /* last time quotas were computed */
244 unsigned int max_avail; /* max bits to be sent to any port */
245 unsigned int port; /* port index (round robin ports) */
246 unsigned int num; /* num skbs in per port queues */
247 struct sched_port p[MAX_NPORTS];
248 struct tasklet_struct sched_tsk;/* tasklet used to run scheduler */
249};
250static void restart_sched(unsigned long);
251
252
229/* 253/*
230 * Main SGE data structure 254 * Main SGE data structure
231 * 255 *
@@ -243,18 +267,240 @@ struct sge {
243 unsigned int rx_pkt_pad; /* RX padding for L2 packets */ 267 unsigned int rx_pkt_pad; /* RX padding for L2 packets */
244 unsigned int jumbo_fl; /* jumbo freelist Q index */ 268 unsigned int jumbo_fl; /* jumbo freelist Q index */
245 unsigned int intrtimer_nres; /* no-resource interrupt timer */ 269 unsigned int intrtimer_nres; /* no-resource interrupt timer */
246 unsigned int fixed_intrtimer;/* non-adaptive interrupt timer */ 270 unsigned int fixed_intrtimer;/* non-adaptive interrupt timer */
247 struct timer_list tx_reclaim_timer; /* reclaims TX buffers */ 271 struct timer_list tx_reclaim_timer; /* reclaims TX buffers */
248 struct timer_list espibug_timer; 272 struct timer_list espibug_timer;
249 unsigned int espibug_timeout; 273 unsigned long espibug_timeout;
250 struct sk_buff *espibug_skb; 274 struct sk_buff *espibug_skb[MAX_NPORTS];
251 u32 sge_control; /* shadow value of sge control reg */ 275 u32 sge_control; /* shadow value of sge control reg */
252 struct sge_intr_counts stats; 276 struct sge_intr_counts stats;
253 struct sge_port_stats port_stats[MAX_NPORTS]; 277 struct sge_port_stats port_stats[MAX_NPORTS];
278 struct sched *tx_sched;
254 struct cmdQ cmdQ[SGE_CMDQ_N] ____cacheline_aligned_in_smp; 279 struct cmdQ cmdQ[SGE_CMDQ_N] ____cacheline_aligned_in_smp;
255}; 280};
256 281
257/* 282/*
283 * stop tasklet and free all pending skb's
284 */
285static void tx_sched_stop(struct sge *sge)
286{
287 struct sched *s = sge->tx_sched;
288 int i;
289
290 tasklet_kill(&s->sched_tsk);
291
292 for (i = 0; i < MAX_NPORTS; i++)
293 __skb_queue_purge(&s->p[s->port].skbq);
294}
295
296/*
297 * t1_sched_update_parms() is called when the MTU or link speed changes. It
298 * re-computes scheduler parameters to scope with the change.
299 */
300unsigned int t1_sched_update_parms(struct sge *sge, unsigned int port,
301 unsigned int mtu, unsigned int speed)
302{
303 struct sched *s = sge->tx_sched;
304 struct sched_port *p = &s->p[port];
305 unsigned int max_avail_segs;
306
307 pr_debug("t1_sched_update_params mtu=%d speed=%d\n", mtu, speed);
308 if (speed)
309 p->speed = speed;
310 if (mtu)
311 p->mtu = mtu;
312
313 if (speed || mtu) {
314 unsigned long long drain = 1024ULL * p->speed * (p->mtu - 40);
315 do_div(drain, (p->mtu + 50) * 1000);
316 p->drain_bits_per_1024ns = (unsigned int) drain;
317
318 if (p->speed < 1000)
319 p->drain_bits_per_1024ns =
320 90 * p->drain_bits_per_1024ns / 100;
321 }
322
323 if (board_info(sge->adapter)->board == CHBT_BOARD_CHT204) {
324 p->drain_bits_per_1024ns -= 16;
325 s->max_avail = max(4096U, p->mtu + 16 + 14 + 4);
326 max_avail_segs = max(1U, 4096 / (p->mtu - 40));
327 } else {
328 s->max_avail = 16384;
329 max_avail_segs = max(1U, 9000 / (p->mtu - 40));
330 }
331
332 pr_debug("t1_sched_update_parms: mtu %u speed %u max_avail %u "
333 "max_avail_segs %u drain_bits_per_1024ns %u\n", p->mtu,
334 p->speed, s->max_avail, max_avail_segs,
335 p->drain_bits_per_1024ns);
336
337 return max_avail_segs * (p->mtu - 40);
338}
339
340/*
341 * t1_sched_max_avail_bytes() tells the scheduler the maximum amount of
342 * data that can be pushed per port.
343 */
344void t1_sched_set_max_avail_bytes(struct sge *sge, unsigned int val)
345{
346 struct sched *s = sge->tx_sched;
347 unsigned int i;
348
349 s->max_avail = val;
350 for (i = 0; i < MAX_NPORTS; i++)
351 t1_sched_update_parms(sge, i, 0, 0);
352}
353
354/*
355 * t1_sched_set_drain_bits_per_us() tells the scheduler at which rate a port
356 * is draining.
357 */
358void t1_sched_set_drain_bits_per_us(struct sge *sge, unsigned int port,
359 unsigned int val)
360{
361 struct sched *s = sge->tx_sched;
362 struct sched_port *p = &s->p[port];
363 p->drain_bits_per_1024ns = val * 1024 / 1000;
364 t1_sched_update_parms(sge, port, 0, 0);
365}
366
367
368/*
369 * get_clock() implements a ns clock (see ktime_get)
370 */
371static inline ktime_t get_clock(void)
372{
373 struct timespec ts;
374
375 ktime_get_ts(&ts);
376 return timespec_to_ktime(ts);
377}
378
379/*
380 * tx_sched_init() allocates resources and does basic initialization.
381 */
382static int tx_sched_init(struct sge *sge)
383{
384 struct sched *s;
385 int i;
386
387 s = kzalloc(sizeof (struct sched), GFP_KERNEL);
388 if (!s)
389 return -ENOMEM;
390
391 pr_debug("tx_sched_init\n");
392 tasklet_init(&s->sched_tsk, restart_sched, (unsigned long) sge);
393 sge->tx_sched = s;
394
395 for (i = 0; i < MAX_NPORTS; i++) {
396 skb_queue_head_init(&s->p[i].skbq);
397 t1_sched_update_parms(sge, i, 1500, 1000);
398 }
399
400 return 0;
401}
402
403/*
404 * sched_update_avail() computes the delta since the last time it was called
405 * and updates the per port quota (number of bits that can be sent to the any
406 * port).
407 */
408static inline int sched_update_avail(struct sge *sge)
409{
410 struct sched *s = sge->tx_sched;
411 ktime_t now = get_clock();
412 unsigned int i;
413 long long delta_time_ns;
414
415 delta_time_ns = ktime_to_ns(ktime_sub(now, s->last_updated));
416
417 pr_debug("sched_update_avail delta=%lld\n", delta_time_ns);
418 if (delta_time_ns < 15000)
419 return 0;
420
421 for (i = 0; i < MAX_NPORTS; i++) {
422 struct sched_port *p = &s->p[i];
423 unsigned int delta_avail;
424
425 delta_avail = (p->drain_bits_per_1024ns * delta_time_ns) >> 13;
426 p->avail = min(p->avail + delta_avail, s->max_avail);
427 }
428
429 s->last_updated = now;
430
431 return 1;
432}
433
434/*
435 * sched_skb() is called from two different places. In the tx path, any
436 * packet generating load on an output port will call sched_skb()
437 * (skb != NULL). In addition, sched_skb() is called from the irq/soft irq
438 * context (skb == NULL).
439 * The scheduler only returns a skb (which will then be sent) if the
440 * length of the skb is <= the current quota of the output port.
441 */
442static struct sk_buff *sched_skb(struct sge *sge, struct sk_buff *skb,
443 unsigned int credits)
444{
445 struct sched *s = sge->tx_sched;
446 struct sk_buff_head *skbq;
447 unsigned int i, len, update = 1;
448
449 pr_debug("sched_skb %p\n", skb);
450 if (!skb) {
451 if (!s->num)
452 return NULL;
453 } else {
454 skbq = &s->p[skb->dev->if_port].skbq;
455 __skb_queue_tail(skbq, skb);
456 s->num++;
457 skb = NULL;
458 }
459
460 if (credits < MAX_SKB_FRAGS + 1)
461 goto out;
462
463 again:
464 for (i = 0; i < MAX_NPORTS; i++) {
465 s->port = ++s->port & (MAX_NPORTS - 1);
466 skbq = &s->p[s->port].skbq;
467
468 skb = skb_peek(skbq);
469
470 if (!skb)
471 continue;
472
473 len = skb->len;
474 if (len <= s->p[s->port].avail) {
475 s->p[s->port].avail -= len;
476 s->num--;
477 __skb_unlink(skb, skbq);
478 goto out;
479 }
480 skb = NULL;
481 }
482
483 if (update-- && sched_update_avail(sge))
484 goto again;
485
486 out:
487 /* If there are more pending skbs, we use the hardware to schedule us
488 * again.
489 */
490 if (s->num && !skb) {
491 struct cmdQ *q = &sge->cmdQ[0];
492 clear_bit(CMDQ_STAT_LAST_PKT_DB, &q->status);
493 if (test_and_set_bit(CMDQ_STAT_RUNNING, &q->status) == 0) {
494 set_bit(CMDQ_STAT_LAST_PKT_DB, &q->status);
495 writel(F_CMDQ0_ENABLE, sge->adapter->regs + A_SG_DOORBELL);
496 }
497 }
498 pr_debug("sched_skb ret %p\n", skb);
499
500 return skb;
501}
502
503/*
258 * PIO to indicate that memory mapped Q contains valid descriptor(s). 504 * PIO to indicate that memory mapped Q contains valid descriptor(s).
259 */ 505 */
260static inline void doorbell_pio(struct adapter *adapter, u32 val) 506static inline void doorbell_pio(struct adapter *adapter, u32 val)
@@ -350,8 +596,11 @@ static int alloc_rx_resources(struct sge *sge, struct sge_params *p)
350 sge->freelQ[!sge->jumbo_fl].rx_buffer_size = SGE_RX_SM_BUF_SIZE + 596 sge->freelQ[!sge->jumbo_fl].rx_buffer_size = SGE_RX_SM_BUF_SIZE +
351 sizeof(struct cpl_rx_data) + 597 sizeof(struct cpl_rx_data) +
352 sge->freelQ[!sge->jumbo_fl].dma_offset; 598 sge->freelQ[!sge->jumbo_fl].dma_offset;
353 sge->freelQ[sge->jumbo_fl].rx_buffer_size = (16 * 1024) - 599
354 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 600 size = (16 * 1024) -
601 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
602
603 sge->freelQ[sge->jumbo_fl].rx_buffer_size = size;
355 604
356 /* 605 /*
357 * Setup which skb recycle Q should be used when recycling buffers from 606 * Setup which skb recycle Q should be used when recycling buffers from
@@ -388,17 +637,23 @@ static void free_cmdQ_buffers(struct sge *sge, struct cmdQ *q, unsigned int n)
388 q->in_use -= n; 637 q->in_use -= n;
389 ce = &q->centries[cidx]; 638 ce = &q->centries[cidx];
390 while (n--) { 639 while (n--) {
391 if (q->sop) 640 if (q->sop) {
392 pci_unmap_single(pdev, pci_unmap_addr(ce, dma_addr), 641 if (likely(pci_unmap_len(ce, dma_len))) {
393 pci_unmap_len(ce, dma_len), 642 pci_unmap_single(pdev,
394 PCI_DMA_TODEVICE); 643 pci_unmap_addr(ce, dma_addr),
395 else 644 pci_unmap_len(ce, dma_len),
396 pci_unmap_page(pdev, pci_unmap_addr(ce, dma_addr), 645 PCI_DMA_TODEVICE);
397 pci_unmap_len(ce, dma_len), 646 q->sop = 0;
398 PCI_DMA_TODEVICE); 647 }
399 q->sop = 0; 648 } else {
649 if (likely(pci_unmap_len(ce, dma_len))) {
650 pci_unmap_page(pdev, pci_unmap_addr(ce, dma_addr),
651 pci_unmap_len(ce, dma_len),
652 PCI_DMA_TODEVICE);
653 }
654 }
400 if (ce->skb) { 655 if (ce->skb) {
401 dev_kfree_skb(ce->skb); 656 dev_kfree_skb_any(ce->skb);
402 q->sop = 1; 657 q->sop = 1;
403 } 658 }
404 ce++; 659 ce++;
@@ -504,7 +759,7 @@ void t1_set_vlan_accel(struct adapter *adapter, int on_off)
504 sge->sge_control |= F_VLAN_XTRACT; 759 sge->sge_control |= F_VLAN_XTRACT;
505 if (adapter->open_device_map) { 760 if (adapter->open_device_map) {
506 writel(sge->sge_control, adapter->regs + A_SG_CONTROL); 761 writel(sge->sge_control, adapter->regs + A_SG_CONTROL);
507 readl(adapter->regs + A_SG_CONTROL); /* flush */ 762 readl(adapter->regs + A_SG_CONTROL); /* flush */
508 } 763 }
509} 764}
510 765
@@ -538,7 +793,6 @@ static void configure_sge(struct sge *sge, struct sge_params *p)
538 sge->sge_control = F_CMDQ0_ENABLE | F_CMDQ1_ENABLE | F_FL0_ENABLE | 793 sge->sge_control = F_CMDQ0_ENABLE | F_CMDQ1_ENABLE | F_FL0_ENABLE |
539 F_FL1_ENABLE | F_CPL_ENABLE | F_RESPONSE_QUEUE_ENABLE | 794 F_FL1_ENABLE | F_CPL_ENABLE | F_RESPONSE_QUEUE_ENABLE |
540 V_CMDQ_PRIORITY(2) | F_DISABLE_CMDQ1_GTS | F_ISCSI_COALESCE | 795 V_CMDQ_PRIORITY(2) | F_DISABLE_CMDQ1_GTS | F_ISCSI_COALESCE |
541 F_DISABLE_FL0_GTS | F_DISABLE_FL1_GTS |
542 V_RX_PKT_OFFSET(sge->rx_pkt_pad); 796 V_RX_PKT_OFFSET(sge->rx_pkt_pad);
543 797
544#if defined(__BIG_ENDIAN_BITFIELD) 798#if defined(__BIG_ENDIAN_BITFIELD)
@@ -566,9 +820,7 @@ static inline unsigned int jumbo_payload_capacity(const struct sge *sge)
566 */ 820 */
567void t1_sge_destroy(struct sge *sge) 821void t1_sge_destroy(struct sge *sge)
568{ 822{
569 if (sge->espibug_skb) 823 kfree(sge->tx_sched);
570 kfree_skb(sge->espibug_skb);
571
572 free_tx_resources(sge); 824 free_tx_resources(sge);
573 free_rx_resources(sge); 825 free_rx_resources(sge);
574 kfree(sge); 826 kfree(sge);
@@ -854,6 +1106,99 @@ static void unexpected_offload(struct adapter *adapter, struct freelQ *fl)
854} 1106}
855 1107
856/* 1108/*
1109 * T1/T2 SGE limits the maximum DMA size per TX descriptor to
1110 * SGE_TX_DESC_MAX_PLEN (16KB). If the PAGE_SIZE is larger than 16KB, the
1111 * stack might send more than SGE_TX_DESC_MAX_PLEN in a contiguous manner.
1112 * Note that the *_large_page_tx_descs stuff will be optimized out when
1113 * PAGE_SIZE <= SGE_TX_DESC_MAX_PLEN.
1114 *
1115 * compute_large_page_descs() computes how many additional descriptors are
1116 * required to break down the stack's request.
1117 */
1118static inline unsigned int compute_large_page_tx_descs(struct sk_buff *skb)
1119{
1120 unsigned int count = 0;
1121 if (PAGE_SIZE > SGE_TX_DESC_MAX_PLEN) {
1122 unsigned int nfrags = skb_shinfo(skb)->nr_frags;
1123 unsigned int i, len = skb->len - skb->data_len;
1124 while (len > SGE_TX_DESC_MAX_PLEN) {
1125 count++;
1126 len -= SGE_TX_DESC_MAX_PLEN;
1127 }
1128 for (i = 0; nfrags--; i++) {
1129 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1130 len = frag->size;
1131 while (len > SGE_TX_DESC_MAX_PLEN) {
1132 count++;
1133 len -= SGE_TX_DESC_MAX_PLEN;
1134 }
1135 }
1136 }
1137 return count;
1138}
1139
1140/*
1141 * Write a cmdQ entry.
1142 *
1143 * Since this function writes the 'flags' field, it must not be used to
1144 * write the first cmdQ entry.
1145 */
1146static inline void write_tx_desc(struct cmdQ_e *e, dma_addr_t mapping,
1147 unsigned int len, unsigned int gen,
1148 unsigned int eop)
1149{
1150 if (unlikely(len > SGE_TX_DESC_MAX_PLEN))
1151 BUG();
1152 e->addr_lo = (u32)mapping;
1153 e->addr_hi = (u64)mapping >> 32;
1154 e->len_gen = V_CMD_LEN(len) | V_CMD_GEN1(gen);
1155 e->flags = F_CMD_DATAVALID | V_CMD_EOP(eop) | V_CMD_GEN2(gen);
1156}
1157
1158/*
1159 * See comment for previous function.
1160 *
1161 * write_tx_descs_large_page() writes additional SGE tx descriptors if
1162 * *desc_len exceeds HW's capability.
1163 */
1164static inline unsigned int write_large_page_tx_descs(unsigned int pidx,
1165 struct cmdQ_e **e,
1166 struct cmdQ_ce **ce,
1167 unsigned int *gen,
1168 dma_addr_t *desc_mapping,
1169 unsigned int *desc_len,
1170 unsigned int nfrags,
1171 struct cmdQ *q)
1172{
1173 if (PAGE_SIZE > SGE_TX_DESC_MAX_PLEN) {
1174 struct cmdQ_e *e1 = *e;
1175 struct cmdQ_ce *ce1 = *ce;
1176
1177 while (*desc_len > SGE_TX_DESC_MAX_PLEN) {
1178 *desc_len -= SGE_TX_DESC_MAX_PLEN;
1179 write_tx_desc(e1, *desc_mapping, SGE_TX_DESC_MAX_PLEN,
1180 *gen, nfrags == 0 && *desc_len == 0);
1181 ce1->skb = NULL;
1182 pci_unmap_len_set(ce1, dma_len, 0);
1183 *desc_mapping += SGE_TX_DESC_MAX_PLEN;
1184 if (*desc_len) {
1185 ce1++;
1186 e1++;
1187 if (++pidx == q->size) {
1188 pidx = 0;
1189 *gen ^= 1;
1190 ce1 = q->centries;
1191 e1 = q->entries;
1192 }
1193 }
1194 }
1195 *e = e1;
1196 *ce = ce1;
1197 }
1198 return pidx;
1199}
1200
1201/*
857 * Write the command descriptors to transmit the given skb starting at 1202 * Write the command descriptors to transmit the given skb starting at
858 * descriptor pidx with the given generation. 1203 * descriptor pidx with the given generation.
859 */ 1204 */
@@ -861,50 +1206,84 @@ static inline void write_tx_descs(struct adapter *adapter, struct sk_buff *skb,
861 unsigned int pidx, unsigned int gen, 1206 unsigned int pidx, unsigned int gen,
862 struct cmdQ *q) 1207 struct cmdQ *q)
863{ 1208{
864 dma_addr_t mapping; 1209 dma_addr_t mapping, desc_mapping;
865 struct cmdQ_e *e, *e1; 1210 struct cmdQ_e *e, *e1;
866 struct cmdQ_ce *ce; 1211 struct cmdQ_ce *ce;
867 unsigned int i, flags, nfrags = skb_shinfo(skb)->nr_frags; 1212 unsigned int i, flags, first_desc_len, desc_len,
1213 nfrags = skb_shinfo(skb)->nr_frags;
868 1214
869 mapping = pci_map_single(adapter->pdev, skb->data, 1215 e = e1 = &q->entries[pidx];
870 skb->len - skb->data_len, PCI_DMA_TODEVICE);
871 ce = &q->centries[pidx]; 1216 ce = &q->centries[pidx];
1217
1218 mapping = pci_map_single(adapter->pdev, skb->data,
1219 skb->len - skb->data_len, PCI_DMA_TODEVICE);
1220
1221 desc_mapping = mapping;
1222 desc_len = skb->len - skb->data_len;
1223
1224 flags = F_CMD_DATAVALID | F_CMD_SOP |
1225 V_CMD_EOP(nfrags == 0 && desc_len <= SGE_TX_DESC_MAX_PLEN) |
1226 V_CMD_GEN2(gen);
1227 first_desc_len = (desc_len <= SGE_TX_DESC_MAX_PLEN) ?
1228 desc_len : SGE_TX_DESC_MAX_PLEN;
1229 e->addr_lo = (u32)desc_mapping;
1230 e->addr_hi = (u64)desc_mapping >> 32;
1231 e->len_gen = V_CMD_LEN(first_desc_len) | V_CMD_GEN1(gen);
1232 ce->skb = NULL;
1233 pci_unmap_len_set(ce, dma_len, 0);
1234
1235 if (PAGE_SIZE > SGE_TX_DESC_MAX_PLEN &&
1236 desc_len > SGE_TX_DESC_MAX_PLEN) {
1237 desc_mapping += first_desc_len;
1238 desc_len -= first_desc_len;
1239 e1++;
1240 ce++;
1241 if (++pidx == q->size) {
1242 pidx = 0;
1243 gen ^= 1;
1244 e1 = q->entries;
1245 ce = q->centries;
1246 }
1247 pidx = write_large_page_tx_descs(pidx, &e1, &ce, &gen,
1248 &desc_mapping, &desc_len,
1249 nfrags, q);
1250
1251 if (likely(desc_len))
1252 write_tx_desc(e1, desc_mapping, desc_len, gen,
1253 nfrags == 0);
1254 }
1255
872 ce->skb = NULL; 1256 ce->skb = NULL;
873 pci_unmap_addr_set(ce, dma_addr, mapping); 1257 pci_unmap_addr_set(ce, dma_addr, mapping);
874 pci_unmap_len_set(ce, dma_len, skb->len - skb->data_len); 1258 pci_unmap_len_set(ce, dma_len, skb->len - skb->data_len);
875 1259
876 flags = F_CMD_DATAVALID | F_CMD_SOP | V_CMD_EOP(nfrags == 0) | 1260 for (i = 0; nfrags--; i++) {
877 V_CMD_GEN2(gen);
878 e = &q->entries[pidx];
879 e->addr_lo = (u32)mapping;
880 e->addr_hi = (u64)mapping >> 32;
881 e->len_gen = V_CMD_LEN(skb->len - skb->data_len) | V_CMD_GEN1(gen);
882 for (e1 = e, i = 0; nfrags--; i++) {
883 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1261 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
884
885 ce++;
886 e1++; 1262 e1++;
1263 ce++;
887 if (++pidx == q->size) { 1264 if (++pidx == q->size) {
888 pidx = 0; 1265 pidx = 0;
889 gen ^= 1; 1266 gen ^= 1;
890 ce = q->centries;
891 e1 = q->entries; 1267 e1 = q->entries;
1268 ce = q->centries;
892 } 1269 }
893 1270
894 mapping = pci_map_page(adapter->pdev, frag->page, 1271 mapping = pci_map_page(adapter->pdev, frag->page,
895 frag->page_offset, frag->size, 1272 frag->page_offset, frag->size,
896 PCI_DMA_TODEVICE); 1273 PCI_DMA_TODEVICE);
1274 desc_mapping = mapping;
1275 desc_len = frag->size;
1276
1277 pidx = write_large_page_tx_descs(pidx, &e1, &ce, &gen,
1278 &desc_mapping, &desc_len,
1279 nfrags, q);
1280 if (likely(desc_len))
1281 write_tx_desc(e1, desc_mapping, desc_len, gen,
1282 nfrags == 0);
897 ce->skb = NULL; 1283 ce->skb = NULL;
898 pci_unmap_addr_set(ce, dma_addr, mapping); 1284 pci_unmap_addr_set(ce, dma_addr, mapping);
899 pci_unmap_len_set(ce, dma_len, frag->size); 1285 pci_unmap_len_set(ce, dma_len, frag->size);
900
901 e1->addr_lo = (u32)mapping;
902 e1->addr_hi = (u64)mapping >> 32;
903 e1->len_gen = V_CMD_LEN(frag->size) | V_CMD_GEN1(gen);
904 e1->flags = F_CMD_DATAVALID | V_CMD_EOP(nfrags == 0) |
905 V_CMD_GEN2(gen);
906 } 1286 }
907
908 ce->skb = skb; 1287 ce->skb = skb;
909 wmb(); 1288 wmb();
910 e->flags = flags; 1289 e->flags = flags;
@@ -918,14 +1297,56 @@ static inline void reclaim_completed_tx(struct sge *sge, struct cmdQ *q)
918 unsigned int reclaim = q->processed - q->cleaned; 1297 unsigned int reclaim = q->processed - q->cleaned;
919 1298
920 if (reclaim) { 1299 if (reclaim) {
1300 pr_debug("reclaim_completed_tx processed:%d cleaned:%d\n",
1301 q->processed, q->cleaned);
921 free_cmdQ_buffers(sge, q, reclaim); 1302 free_cmdQ_buffers(sge, q, reclaim);
922 q->cleaned += reclaim; 1303 q->cleaned += reclaim;
923 } 1304 }
924} 1305}
925 1306
926#ifndef SET_ETHTOOL_OPS 1307/*
927# define __netif_rx_complete(dev) netif_rx_complete(dev) 1308 * Called from tasklet. Checks the scheduler for any
928#endif 1309 * pending skbs that can be sent.
1310 */
1311static void restart_sched(unsigned long arg)
1312{
1313 struct sge *sge = (struct sge *) arg;
1314 struct adapter *adapter = sge->adapter;
1315 struct cmdQ *q = &sge->cmdQ[0];
1316 struct sk_buff *skb;
1317 unsigned int credits, queued_skb = 0;
1318
1319 spin_lock(&q->lock);
1320 reclaim_completed_tx(sge, q);
1321
1322 credits = q->size - q->in_use;
1323 pr_debug("restart_sched credits=%d\n", credits);
1324 while ((skb = sched_skb(sge, NULL, credits)) != NULL) {
1325 unsigned int genbit, pidx, count;
1326 count = 1 + skb_shinfo(skb)->nr_frags;
1327 count += compute_large_page_tx_descs(skb);
1328 q->in_use += count;
1329 genbit = q->genbit;
1330 pidx = q->pidx;
1331 q->pidx += count;
1332 if (q->pidx >= q->size) {
1333 q->pidx -= q->size;
1334 q->genbit ^= 1;
1335 }
1336 write_tx_descs(adapter, skb, pidx, genbit, q);
1337 credits = q->size - q->in_use;
1338 queued_skb = 1;
1339 }
1340
1341 if (queued_skb) {
1342 clear_bit(CMDQ_STAT_LAST_PKT_DB, &q->status);
1343 if (test_and_set_bit(CMDQ_STAT_RUNNING, &q->status) == 0) {
1344 set_bit(CMDQ_STAT_LAST_PKT_DB, &q->status);
1345 writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL);
1346 }
1347 }
1348 spin_unlock(&q->lock);
1349}
929 1350
930/** 1351/**
931 * sge_rx - process an ingress ethernet packet 1352 * sge_rx - process an ingress ethernet packet
@@ -953,6 +1374,11 @@ static int sge_rx(struct sge *sge, struct freelQ *fl, unsigned int len)
953 p = (struct cpl_rx_pkt *)skb->data; 1374 p = (struct cpl_rx_pkt *)skb->data;
954 skb_pull(skb, sizeof(*p)); 1375 skb_pull(skb, sizeof(*p));
955 skb->dev = adapter->port[p->iff].dev; 1376 skb->dev = adapter->port[p->iff].dev;
1377 if (p->iff >= adapter->params.nports) {
1378 kfree_skb(skb);
1379 return 0;
1380 }
1381
956 skb->dev->last_rx = jiffies; 1382 skb->dev->last_rx = jiffies;
957 skb->protocol = eth_type_trans(skb, skb->dev); 1383 skb->protocol = eth_type_trans(skb, skb->dev);
958 if ((adapter->flags & RX_CSUM_ENABLED) && p->csum == 0xffff && 1384 if ((adapter->flags & RX_CSUM_ENABLED) && p->csum == 0xffff &&
@@ -1025,18 +1451,24 @@ static unsigned int update_tx_info(struct adapter *adapter,
1025 struct cmdQ *cmdq = &sge->cmdQ[0]; 1451 struct cmdQ *cmdq = &sge->cmdQ[0];
1026 1452
1027 cmdq->processed += pr0; 1453 cmdq->processed += pr0;
1028 1454 if (flags & (F_FL0_ENABLE | F_FL1_ENABLE)) {
1455 freelQs_empty(sge);
1456 flags &= ~(F_FL0_ENABLE | F_FL1_ENABLE);
1457 }
1029 if (flags & F_CMDQ0_ENABLE) { 1458 if (flags & F_CMDQ0_ENABLE) {
1030 clear_bit(CMDQ_STAT_RUNNING, &cmdq->status); 1459 clear_bit(CMDQ_STAT_RUNNING, &cmdq->status);
1031 1460
1032 if (cmdq->cleaned + cmdq->in_use != cmdq->processed && 1461 if (cmdq->cleaned + cmdq->in_use != cmdq->processed &&
1033 !test_and_set_bit(CMDQ_STAT_LAST_PKT_DB, &cmdq->status)) { 1462 !test_and_set_bit(CMDQ_STAT_LAST_PKT_DB, &cmdq->status)) {
1034 set_bit(CMDQ_STAT_RUNNING, &cmdq->status); 1463 set_bit(CMDQ_STAT_RUNNING, &cmdq->status);
1035 writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL); 1464 writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL);
1036 } 1465 }
1037 flags &= ~F_CMDQ0_ENABLE; 1466 if (sge->tx_sched)
1467 tasklet_hi_schedule(&sge->tx_sched->sched_tsk);
1468
1469 flags &= ~F_CMDQ0_ENABLE;
1038 } 1470 }
1039 1471
1040 if (unlikely(sge->stopped_tx_queues != 0)) 1472 if (unlikely(sge->stopped_tx_queues != 0))
1041 restart_tx_queues(sge); 1473 restart_tx_queues(sge);
1042 1474
@@ -1233,14 +1665,15 @@ static irqreturn_t t1_interrupt_napi(int irq, void *data)
1233 printk(KERN_INFO 1665 printk(KERN_INFO
1234 "NAPI schedule failure!\n"); 1666 "NAPI schedule failure!\n");
1235 } else 1667 } else
1236 writel(q->cidx, adapter->regs + A_SG_SLEEPING); 1668 writel(q->cidx, adapter->regs + A_SG_SLEEPING);
1669
1237 handled = 1; 1670 handled = 1;
1238 goto unlock; 1671 goto unlock;
1239 } else 1672 } else
1240 writel(q->cidx, adapter->regs + A_SG_SLEEPING); 1673 writel(q->cidx, adapter->regs + A_SG_SLEEPING);
1241 } else 1674 } else if (readl(adapter->regs + A_PL_CAUSE) & F_PL_INTR_SGE_DATA) {
1242 if (readl(adapter->regs + A_PL_CAUSE) & F_PL_INTR_SGE_DATA) 1675 printk(KERN_ERR "data interrupt while NAPI running\n");
1243 printk(KERN_ERR "data interrupt while NAPI running\n"); 1676 }
1244 1677
1245 handled = t1_slow_intr_handler(adapter); 1678 handled = t1_slow_intr_handler(adapter);
1246 if (!handled) 1679 if (!handled)
@@ -1321,7 +1754,7 @@ static int t1_sge_tx(struct sk_buff *skb, struct adapter *adapter,
1321{ 1754{
1322 struct sge *sge = adapter->sge; 1755 struct sge *sge = adapter->sge;
1323 struct cmdQ *q = &sge->cmdQ[qid]; 1756 struct cmdQ *q = &sge->cmdQ[qid];
1324 unsigned int credits, pidx, genbit, count; 1757 unsigned int credits, pidx, genbit, count, use_sched_skb = 0;
1325 1758
1326 spin_lock(&q->lock); 1759 spin_lock(&q->lock);
1327 reclaim_completed_tx(sge, q); 1760 reclaim_completed_tx(sge, q);
@@ -1329,26 +1762,49 @@ static int t1_sge_tx(struct sk_buff *skb, struct adapter *adapter,
1329 pidx = q->pidx; 1762 pidx = q->pidx;
1330 credits = q->size - q->in_use; 1763 credits = q->size - q->in_use;
1331 count = 1 + skb_shinfo(skb)->nr_frags; 1764 count = 1 + skb_shinfo(skb)->nr_frags;
1765 count += compute_large_page_tx_descs(skb);
1332 1766
1333 { /* Ethernet packet */ 1767 /* Ethernet packet */
1334 if (unlikely(credits < count)) { 1768 if (unlikely(credits < count)) {
1769 if (!netif_queue_stopped(dev)) {
1335 netif_stop_queue(dev); 1770 netif_stop_queue(dev);
1336 set_bit(dev->if_port, &sge->stopped_tx_queues); 1771 set_bit(dev->if_port, &sge->stopped_tx_queues);
1337 sge->stats.cmdQ_full[2]++; 1772 sge->stats.cmdQ_full[2]++;
1338 spin_unlock(&q->lock); 1773 CH_ERR("%s: Tx ring full while queue awake!\n",
1339 if (!netif_queue_stopped(dev)) 1774 adapter->name);
1340 CH_ERR("%s: Tx ring full while queue awake!\n",
1341 adapter->name);
1342 return NETDEV_TX_BUSY;
1343 } 1775 }
1344 if (unlikely(credits - count < q->stop_thres)) { 1776 spin_unlock(&q->lock);
1345 sge->stats.cmdQ_full[2]++; 1777 return NETDEV_TX_BUSY;
1346 netif_stop_queue(dev); 1778 }
1347 set_bit(dev->if_port, &sge->stopped_tx_queues); 1779
1780 if (unlikely(credits - count < q->stop_thres)) {
1781 netif_stop_queue(dev);
1782 set_bit(dev->if_port, &sge->stopped_tx_queues);
1783 sge->stats.cmdQ_full[2]++;
1784 }
1785
1786 /* T204 cmdQ0 skbs that are destined for a certain port have to go
1787 * through the scheduler.
1788 */
1789 if (sge->tx_sched && !qid && skb->dev) {
1790 use_sched:
1791 use_sched_skb = 1;
1792 /* Note that the scheduler might return a different skb than
1793 * the one passed in.
1794 */
1795 skb = sched_skb(sge, skb, credits);
1796 if (!skb) {
1797 spin_unlock(&q->lock);
1798 return NETDEV_TX_OK;
1348 } 1799 }
1800 pidx = q->pidx;
1801 count = 1 + skb_shinfo(skb)->nr_frags;
1802 count += compute_large_page_tx_descs(skb);
1349 } 1803 }
1804
1350 q->in_use += count; 1805 q->in_use += count;
1351 genbit = q->genbit; 1806 genbit = q->genbit;
1807 pidx = q->pidx;
1352 q->pidx += count; 1808 q->pidx += count;
1353 if (q->pidx >= q->size) { 1809 if (q->pidx >= q->size) {
1354 q->pidx -= q->size; 1810 q->pidx -= q->size;
@@ -1374,6 +1830,14 @@ static int t1_sge_tx(struct sk_buff *skb, struct adapter *adapter,
1374 writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL); 1830 writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL);
1375 } 1831 }
1376 } 1832 }
1833
1834 if (use_sched_skb) {
1835 if (spin_trylock(&q->lock)) {
1836 credits = q->size - q->in_use;
1837 skb = NULL;
1838 goto use_sched;
1839 }
1840 }
1377 return NETDEV_TX_OK; 1841 return NETDEV_TX_OK;
1378} 1842}
1379 1843
@@ -1402,8 +1866,10 @@ int t1_start_xmit(struct sk_buff *skb, struct net_device *dev)
1402 struct sge *sge = adapter->sge; 1866 struct sge *sge = adapter->sge;
1403 struct cpl_tx_pkt *cpl; 1867 struct cpl_tx_pkt *cpl;
1404 1868
1405#ifdef NETIF_F_TSO 1869 if (skb->protocol == htons(ETH_P_CPL5))
1406 if (skb_is_gso(skb)) { 1870 goto send;
1871
1872 if (skb_shinfo(skb)->gso_size) {
1407 int eth_type; 1873 int eth_type;
1408 struct cpl_tx_pkt_lso *hdr; 1874 struct cpl_tx_pkt_lso *hdr;
1409 1875
@@ -1418,13 +1884,11 @@ int t1_start_xmit(struct sk_buff *skb, struct net_device *dev)
1418 hdr->ip_hdr_words = skb->nh.iph->ihl; 1884 hdr->ip_hdr_words = skb->nh.iph->ihl;
1419 hdr->tcp_hdr_words = skb->h.th->doff; 1885 hdr->tcp_hdr_words = skb->h.th->doff;
1420 hdr->eth_type_mss = htons(MK_ETH_TYPE_MSS(eth_type, 1886 hdr->eth_type_mss = htons(MK_ETH_TYPE_MSS(eth_type,
1421 skb_shinfo(skb)->gso_size)); 1887 skb_shinfo(skb)->gso_size));
1422 hdr->len = htonl(skb->len - sizeof(*hdr)); 1888 hdr->len = htonl(skb->len - sizeof(*hdr));
1423 cpl = (struct cpl_tx_pkt *)hdr; 1889 cpl = (struct cpl_tx_pkt *)hdr;
1424 sge->stats.tx_lso_pkts++; 1890 sge->stats.tx_lso_pkts++;
1425 } else 1891 } else {
1426#endif
1427 {
1428 /* 1892 /*
1429 * Packets shorter than ETH_HLEN can break the MAC, drop them 1893 * Packets shorter than ETH_HLEN can break the MAC, drop them
1430 * early. Also, we may get oversized packets because some 1894 * early. Also, we may get oversized packets because some
@@ -1433,6 +1897,8 @@ int t1_start_xmit(struct sk_buff *skb, struct net_device *dev)
1433 */ 1897 */
1434 if (unlikely(skb->len < ETH_HLEN || 1898 if (unlikely(skb->len < ETH_HLEN ||
1435 skb->len > dev->mtu + eth_hdr_len(skb->data))) { 1899 skb->len > dev->mtu + eth_hdr_len(skb->data))) {
1900 pr_debug("%s: packet size %d hdr %d mtu%d\n", dev->name,
1901 skb->len, eth_hdr_len(skb->data), dev->mtu);
1436 dev_kfree_skb_any(skb); 1902 dev_kfree_skb_any(skb);
1437 return NETDEV_TX_OK; 1903 return NETDEV_TX_OK;
1438 } 1904 }
@@ -1442,10 +1908,12 @@ int t1_start_xmit(struct sk_buff *skb, struct net_device *dev)
1442 * components, such as pktgen, do not handle it right. 1908 * components, such as pktgen, do not handle it right.
1443 * Complain when this happens but try to fix things up. 1909 * Complain when this happens but try to fix things up.
1444 */ 1910 */
1445 if (unlikely(skb_headroom(skb) < 1911 if (unlikely(skb_headroom(skb) < dev->hard_header_len - ETH_HLEN)) {
1446 dev->hard_header_len - ETH_HLEN)) {
1447 struct sk_buff *orig_skb = skb; 1912 struct sk_buff *orig_skb = skb;
1448 1913
1914 pr_debug("%s: headroom %d header_len %d\n", dev->name,
1915 skb_headroom(skb), dev->hard_header_len);
1916
1449 if (net_ratelimit()) 1917 if (net_ratelimit())
1450 printk(KERN_ERR "%s: inadequate headroom in " 1918 printk(KERN_ERR "%s: inadequate headroom in "
1451 "Tx packet\n", dev->name); 1919 "Tx packet\n", dev->name);
@@ -1457,19 +1925,21 @@ int t1_start_xmit(struct sk_buff *skb, struct net_device *dev)
1457 1925
1458 if (!(adapter->flags & UDP_CSUM_CAPABLE) && 1926 if (!(adapter->flags & UDP_CSUM_CAPABLE) &&
1459 skb->ip_summed == CHECKSUM_PARTIAL && 1927 skb->ip_summed == CHECKSUM_PARTIAL &&
1460 skb->nh.iph->protocol == IPPROTO_UDP) 1928 skb->nh.iph->protocol == IPPROTO_UDP) {
1461 if (unlikely(skb_checksum_help(skb))) { 1929 if (unlikely(skb_checksum_help(skb))) {
1930 pr_debug("%s: unable to do udp checksum\n", dev->name);
1462 dev_kfree_skb_any(skb); 1931 dev_kfree_skb_any(skb);
1463 return NETDEV_TX_OK; 1932 return NETDEV_TX_OK;
1464 } 1933 }
1934 }
1465 1935
1466 /* Hmmm, assuming to catch the gratious arp... and we'll use 1936 /* Hmmm, assuming to catch the gratious arp... and we'll use
1467 * it to flush out stuck espi packets... 1937 * it to flush out stuck espi packets...
1468 */ 1938 */
1469 if (unlikely(!adapter->sge->espibug_skb)) { 1939 if ((unlikely(!adapter->sge->espibug_skb[dev->if_port]))) {
1470 if (skb->protocol == htons(ETH_P_ARP) && 1940 if (skb->protocol == htons(ETH_P_ARP) &&
1471 skb->nh.arph->ar_op == htons(ARPOP_REQUEST)) { 1941 skb->nh.arph->ar_op == htons(ARPOP_REQUEST)) {
1472 adapter->sge->espibug_skb = skb; 1942 adapter->sge->espibug_skb[dev->if_port] = skb;
1473 /* We want to re-use this skb later. We 1943 /* We want to re-use this skb later. We
1474 * simply bump the reference count and it 1944 * simply bump the reference count and it
1475 * will not be freed... 1945 * will not be freed...
@@ -1499,6 +1969,7 @@ int t1_start_xmit(struct sk_buff *skb, struct net_device *dev)
1499#endif 1969#endif
1500 cpl->vlan_valid = 0; 1970 cpl->vlan_valid = 0;
1501 1971
1972send:
1502 dev->trans_start = jiffies; 1973 dev->trans_start = jiffies;
1503 return t1_sge_tx(skb, adapter, 0, dev); 1974 return t1_sge_tx(skb, adapter, 0, dev);
1504} 1975}
@@ -1518,10 +1989,9 @@ static void sge_tx_reclaim_cb(unsigned long data)
1518 continue; 1989 continue;
1519 1990
1520 reclaim_completed_tx(sge, q); 1991 reclaim_completed_tx(sge, q);
1521 if (i == 0 && q->in_use) /* flush pending credits */ 1992 if (i == 0 && q->in_use) { /* flush pending credits */
1522 writel(F_CMDQ0_ENABLE, 1993 writel(F_CMDQ0_ENABLE, sge->adapter->regs + A_SG_DOORBELL);
1523 sge->adapter->regs + A_SG_DOORBELL); 1994 }
1524
1525 spin_unlock(&q->lock); 1995 spin_unlock(&q->lock);
1526 } 1996 }
1527 mod_timer(&sge->tx_reclaim_timer, jiffies + TX_RECLAIM_PERIOD); 1997 mod_timer(&sge->tx_reclaim_timer, jiffies + TX_RECLAIM_PERIOD);
@@ -1568,11 +2038,20 @@ int t1_sge_configure(struct sge *sge, struct sge_params *p)
1568 */ 2038 */
1569void t1_sge_stop(struct sge *sge) 2039void t1_sge_stop(struct sge *sge)
1570{ 2040{
2041 int i;
1571 writel(0, sge->adapter->regs + A_SG_CONTROL); 2042 writel(0, sge->adapter->regs + A_SG_CONTROL);
1572 (void) readl(sge->adapter->regs + A_SG_CONTROL); /* flush */ 2043 readl(sge->adapter->regs + A_SG_CONTROL); /* flush */
2044
1573 if (is_T2(sge->adapter)) 2045 if (is_T2(sge->adapter))
1574 del_timer_sync(&sge->espibug_timer); 2046 del_timer_sync(&sge->espibug_timer);
2047
1575 del_timer_sync(&sge->tx_reclaim_timer); 2048 del_timer_sync(&sge->tx_reclaim_timer);
2049 if (sge->tx_sched)
2050 tx_sched_stop(sge);
2051
2052 for (i = 0; i < MAX_NPORTS; i++)
2053 if (sge->espibug_skb[i])
2054 kfree_skb(sge->espibug_skb[i]);
1576} 2055}
1577 2056
1578/* 2057/*
@@ -1585,48 +2064,86 @@ void t1_sge_start(struct sge *sge)
1585 2064
1586 writel(sge->sge_control, sge->adapter->regs + A_SG_CONTROL); 2065 writel(sge->sge_control, sge->adapter->regs + A_SG_CONTROL);
1587 doorbell_pio(sge->adapter, F_FL0_ENABLE | F_FL1_ENABLE); 2066 doorbell_pio(sge->adapter, F_FL0_ENABLE | F_FL1_ENABLE);
1588 (void) readl(sge->adapter->regs + A_SG_CONTROL); /* flush */ 2067 readl(sge->adapter->regs + A_SG_CONTROL); /* flush */
1589 2068
1590 mod_timer(&sge->tx_reclaim_timer, jiffies + TX_RECLAIM_PERIOD); 2069 mod_timer(&sge->tx_reclaim_timer, jiffies + TX_RECLAIM_PERIOD);
1591 2070
1592 if (is_T2(sge->adapter)) 2071 if (is_T2(sge->adapter))
1593 mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout); 2072 mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout);
1594} 2073}
1595 2074
1596/* 2075/*
1597 * Callback for the T2 ESPI 'stuck packet feature' workaorund 2076 * Callback for the T2 ESPI 'stuck packet feature' workaorund
1598 */ 2077 */
1599static void espibug_workaround(void *data) 2078static void espibug_workaround_t204(unsigned long data)
1600{ 2079{
1601 struct adapter *adapter = (struct adapter *)data; 2080 struct adapter *adapter = (struct adapter *)data;
1602 struct sge *sge = adapter->sge; 2081 struct sge *sge = adapter->sge;
2082 unsigned int nports = adapter->params.nports;
2083 u32 seop[MAX_NPORTS];
1603 2084
1604 if (netif_running(adapter->port[0].dev)) { 2085 if (adapter->open_device_map & PORT_MASK) {
1605 struct sk_buff *skb = sge->espibug_skb; 2086 int i;
1606 2087 if (t1_espi_get_mon_t204(adapter, &(seop[0]), 0) < 0) {
1607 u32 seop = t1_espi_get_mon(adapter, 0x930, 0); 2088 return;
1608 2089 }
1609 if ((seop & 0xfff0fff) == 0xfff && skb) { 2090 for (i = 0; i < nports; i++) {
1610 if (!skb->cb[0]) { 2091 struct sk_buff *skb = sge->espibug_skb[i];
1611 u8 ch_mac_addr[ETH_ALEN] = 2092 if ( (netif_running(adapter->port[i].dev)) &&
1612 {0x0, 0x7, 0x43, 0x0, 0x0, 0x0}; 2093 !(netif_queue_stopped(adapter->port[i].dev)) &&
1613 memcpy(skb->data + sizeof(struct cpl_tx_pkt), 2094 (seop[i] && ((seop[i] & 0xfff) == 0)) &&
1614 ch_mac_addr, ETH_ALEN); 2095 skb ) {
1615 memcpy(skb->data + skb->len - 10, ch_mac_addr, 2096 if (!skb->cb[0]) {
1616 ETH_ALEN); 2097 u8 ch_mac_addr[ETH_ALEN] =
1617 skb->cb[0] = 0xff; 2098 {0x0, 0x7, 0x43, 0x0, 0x0, 0x0};
2099 memcpy(skb->data + sizeof(struct cpl_tx_pkt),
2100 ch_mac_addr, ETH_ALEN);
2101 memcpy(skb->data + skb->len - 10,
2102 ch_mac_addr, ETH_ALEN);
2103 skb->cb[0] = 0xff;
2104 }
2105
2106 /* bump the reference count to avoid freeing of
2107 * the skb once the DMA has completed.
2108 */
2109 skb = skb_get(skb);
2110 t1_sge_tx(skb, adapter, 0, adapter->port[i].dev);
1618 } 2111 }
1619
1620 /* bump the reference count to avoid freeing of the
1621 * skb once the DMA has completed.
1622 */
1623 skb = skb_get(skb);
1624 t1_sge_tx(skb, adapter, 0, adapter->port[0].dev);
1625 } 2112 }
1626 } 2113 }
1627 mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout); 2114 mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout);
1628} 2115}
1629 2116
2117static void espibug_workaround(unsigned long data)
2118{
2119 struct adapter *adapter = (struct adapter *)data;
2120 struct sge *sge = adapter->sge;
2121
2122 if (netif_running(adapter->port[0].dev)) {
2123 struct sk_buff *skb = sge->espibug_skb[0];
2124 u32 seop = t1_espi_get_mon(adapter, 0x930, 0);
2125
2126 if ((seop & 0xfff0fff) == 0xfff && skb) {
2127 if (!skb->cb[0]) {
2128 u8 ch_mac_addr[ETH_ALEN] =
2129 {0x0, 0x7, 0x43, 0x0, 0x0, 0x0};
2130 memcpy(skb->data + sizeof(struct cpl_tx_pkt),
2131 ch_mac_addr, ETH_ALEN);
2132 memcpy(skb->data + skb->len - 10, ch_mac_addr,
2133 ETH_ALEN);
2134 skb->cb[0] = 0xff;
2135 }
2136
2137 /* bump the reference count to avoid freeing of the
2138 * skb once the DMA has completed.
2139 */
2140 skb = skb_get(skb);
2141 t1_sge_tx(skb, adapter, 0, adapter->port[0].dev);
2142 }
2143 }
2144 mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout);
2145}
2146
1630/* 2147/*
1631 * Creates a t1_sge structure and returns suggested resource parameters. 2148 * Creates a t1_sge structure and returns suggested resource parameters.
1632 */ 2149 */
@@ -1649,9 +2166,19 @@ struct sge * __devinit t1_sge_create(struct adapter *adapter,
1649 2166
1650 if (is_T2(sge->adapter)) { 2167 if (is_T2(sge->adapter)) {
1651 init_timer(&sge->espibug_timer); 2168 init_timer(&sge->espibug_timer);
1652 sge->espibug_timer.function = (void *)&espibug_workaround; 2169
2170 if (adapter->params.nports > 1) {
2171 tx_sched_init(sge);
2172 sge->espibug_timer.function = espibug_workaround_t204;
2173 } else {
2174 sge->espibug_timer.function = espibug_workaround;
2175 }
1653 sge->espibug_timer.data = (unsigned long)sge->adapter; 2176 sge->espibug_timer.data = (unsigned long)sge->adapter;
2177
1654 sge->espibug_timeout = 1; 2178 sge->espibug_timeout = 1;
2179 /* for T204, every 10ms */
2180 if (adapter->params.nports > 1)
2181 sge->espibug_timeout = HZ/100;
1655 } 2182 }
1656 2183
1657 2184
@@ -1659,7 +2186,14 @@ struct sge * __devinit t1_sge_create(struct adapter *adapter,
1659 p->cmdQ_size[1] = SGE_CMDQ1_E_N; 2186 p->cmdQ_size[1] = SGE_CMDQ1_E_N;
1660 p->freelQ_size[!sge->jumbo_fl] = SGE_FREEL_SIZE; 2187 p->freelQ_size[!sge->jumbo_fl] = SGE_FREEL_SIZE;
1661 p->freelQ_size[sge->jumbo_fl] = SGE_JUMBO_FREEL_SIZE; 2188 p->freelQ_size[sge->jumbo_fl] = SGE_JUMBO_FREEL_SIZE;
1662 p->rx_coalesce_usecs = 50; 2189 if (sge->tx_sched) {
2190 if (board_info(sge->adapter)->board == CHBT_BOARD_CHT204)
2191 p->rx_coalesce_usecs = 15;
2192 else
2193 p->rx_coalesce_usecs = 50;
2194 } else
2195 p->rx_coalesce_usecs = 50;
2196
1663 p->coalesce_enable = 0; 2197 p->coalesce_enable = 0;
1664 p->sample_interval_usecs = 0; 2198 p->sample_interval_usecs = 0;
1665 p->polling = 0; 2199 p->polling = 0;
diff --git a/drivers/net/chelsio/sge.h b/drivers/net/chelsio/sge.h
index 91af47bab7be..4691c4f58e7f 100644
--- a/drivers/net/chelsio/sge.h
+++ b/drivers/net/chelsio/sge.h
@@ -92,5 +92,9 @@ void t1_sge_intr_disable(struct sge *);
92void t1_sge_intr_clear(struct sge *); 92void t1_sge_intr_clear(struct sge *);
93const struct sge_intr_counts *t1_sge_get_intr_counts(struct sge *sge); 93const struct sge_intr_counts *t1_sge_get_intr_counts(struct sge *sge);
94const struct sge_port_stats *t1_sge_get_port_stats(struct sge *sge, int port); 94const struct sge_port_stats *t1_sge_get_port_stats(struct sge *sge, int port);
95void t1_sched_set_max_avail_bytes(struct sge *, unsigned int);
96void t1_sched_set_drain_bits_per_us(struct sge *, unsigned int, unsigned int);
97unsigned int t1_sched_update_parms(struct sge *, unsigned int, unsigned int,
98 unsigned int);
95 99
96#endif /* _CXGB_SGE_H_ */ 100#endif /* _CXGB_SGE_H_ */
diff --git a/drivers/net/chelsio/subr.c b/drivers/net/chelsio/subr.c
index e4473ec43d26..d41d15a71e4d 100644
--- a/drivers/net/chelsio/subr.c
+++ b/drivers/net/chelsio/subr.c
@@ -43,6 +43,7 @@
43#include "gmac.h" 43#include "gmac.h"
44#include "cphy.h" 44#include "cphy.h"
45#include "sge.h" 45#include "sge.h"
46#include "tp.h"
46#include "espi.h" 47#include "espi.h"
47 48
48/** 49/**
@@ -59,7 +60,7 @@
59 * otherwise. 60 * otherwise.
60 */ 61 */
61static int t1_wait_op_done(adapter_t *adapter, int reg, u32 mask, int polarity, 62static int t1_wait_op_done(adapter_t *adapter, int reg, u32 mask, int polarity,
62 int attempts, int delay) 63 int attempts, int delay)
63{ 64{
64 while (1) { 65 while (1) {
65 u32 val = readl(adapter->regs + reg) & mask; 66 u32 val = readl(adapter->regs + reg) & mask;
@@ -78,7 +79,7 @@ static int t1_wait_op_done(adapter_t *adapter, int reg, u32 mask, int polarity,
78/* 79/*
79 * Write a register over the TPI interface (unlocked and locked versions). 80 * Write a register over the TPI interface (unlocked and locked versions).
80 */ 81 */
81static int __t1_tpi_write(adapter_t *adapter, u32 addr, u32 value) 82int __t1_tpi_write(adapter_t *adapter, u32 addr, u32 value)
82{ 83{
83 int tpi_busy; 84 int tpi_busy;
84 85
@@ -98,16 +99,16 @@ int t1_tpi_write(adapter_t *adapter, u32 addr, u32 value)
98{ 99{
99 int ret; 100 int ret;
100 101
101 spin_lock(&(adapter)->tpi_lock); 102 spin_lock(&adapter->tpi_lock);
102 ret = __t1_tpi_write(adapter, addr, value); 103 ret = __t1_tpi_write(adapter, addr, value);
103 spin_unlock(&(adapter)->tpi_lock); 104 spin_unlock(&adapter->tpi_lock);
104 return ret; 105 return ret;
105} 106}
106 107
107/* 108/*
108 * Read a register over the TPI interface (unlocked and locked versions). 109 * Read a register over the TPI interface (unlocked and locked versions).
109 */ 110 */
110static int __t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp) 111int __t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp)
111{ 112{
112 int tpi_busy; 113 int tpi_busy;
113 114
@@ -128,18 +129,26 @@ int t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp)
128{ 129{
129 int ret; 130 int ret;
130 131
131 spin_lock(&(adapter)->tpi_lock); 132 spin_lock(&adapter->tpi_lock);
132 ret = __t1_tpi_read(adapter, addr, valp); 133 ret = __t1_tpi_read(adapter, addr, valp);
133 spin_unlock(&(adapter)->tpi_lock); 134 spin_unlock(&adapter->tpi_lock);
134 return ret; 135 return ret;
135} 136}
136 137
137/* 138/*
139 * Set a TPI parameter.
140 */
141static void t1_tpi_par(adapter_t *adapter, u32 value)
142{
143 writel(V_TPIPAR(value), adapter->regs + A_TPI_PAR);
144}
145
146/*
138 * Called when a port's link settings change to propagate the new values to the 147 * Called when a port's link settings change to propagate the new values to the
139 * associated PHY and MAC. After performing the common tasks it invokes an 148 * associated PHY and MAC. After performing the common tasks it invokes an
140 * OS-specific handler. 149 * OS-specific handler.
141 */ 150 */
142/* static */ void link_changed(adapter_t *adapter, int port_id) 151void t1_link_changed(adapter_t *adapter, int port_id)
143{ 152{
144 int link_ok, speed, duplex, fc; 153 int link_ok, speed, duplex, fc;
145 struct cphy *phy = adapter->port[port_id].phy; 154 struct cphy *phy = adapter->port[port_id].phy;
@@ -159,7 +168,7 @@ int t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp)
159 mac->ops->set_speed_duplex_fc(mac, speed, duplex, fc); 168 mac->ops->set_speed_duplex_fc(mac, speed, duplex, fc);
160 lc->fc = (unsigned char)fc; 169 lc->fc = (unsigned char)fc;
161 } 170 }
162 t1_link_changed(adapter, port_id, link_ok, speed, duplex, fc); 171 t1_link_negotiated(adapter, port_id, link_ok, speed, duplex, fc);
163} 172}
164 173
165static int t1_pci_intr_handler(adapter_t *adapter) 174static int t1_pci_intr_handler(adapter_t *adapter)
@@ -217,7 +226,7 @@ static int mi1_mdio_ext_read(adapter_t *adapter, int phy_addr, int mmd_addr,
217{ 226{
218 u32 addr = V_MI1_REG_ADDR(mmd_addr) | V_MI1_PHY_ADDR(phy_addr); 227 u32 addr = V_MI1_REG_ADDR(mmd_addr) | V_MI1_PHY_ADDR(phy_addr);
219 228
220 spin_lock(&(adapter)->tpi_lock); 229 spin_lock(&adapter->tpi_lock);
221 230
222 /* Write the address we want. */ 231 /* Write the address we want. */
223 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr); 232 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
@@ -227,12 +236,13 @@ static int mi1_mdio_ext_read(adapter_t *adapter, int phy_addr, int mmd_addr,
227 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP); 236 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
228 237
229 /* Write the operation we want. */ 238 /* Write the operation we want. */
230 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP, MI1_OP_INDIRECT_READ); 239 __t1_tpi_write(adapter,
240 A_ELMER0_PORT0_MI1_OP, MI1_OP_INDIRECT_READ);
231 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP); 241 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
232 242
233 /* Read the data. */ 243 /* Read the data. */
234 __t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, valp); 244 __t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, valp);
235 spin_unlock(&(adapter)->tpi_lock); 245 spin_unlock(&adapter->tpi_lock);
236 return 0; 246 return 0;
237} 247}
238 248
@@ -241,7 +251,7 @@ static int mi1_mdio_ext_write(adapter_t *adapter, int phy_addr, int mmd_addr,
241{ 251{
242 u32 addr = V_MI1_REG_ADDR(mmd_addr) | V_MI1_PHY_ADDR(phy_addr); 252 u32 addr = V_MI1_REG_ADDR(mmd_addr) | V_MI1_PHY_ADDR(phy_addr);
243 253
244 spin_lock(&(adapter)->tpi_lock); 254 spin_lock(&adapter->tpi_lock);
245 255
246 /* Write the address we want. */ 256 /* Write the address we want. */
247 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr); 257 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
@@ -254,7 +264,7 @@ static int mi1_mdio_ext_write(adapter_t *adapter, int phy_addr, int mmd_addr,
254 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, val); 264 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, val);
255 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP, MI1_OP_INDIRECT_WRITE); 265 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP, MI1_OP_INDIRECT_WRITE);
256 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP); 266 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
257 spin_unlock(&(adapter)->tpi_lock); 267 spin_unlock(&adapter->tpi_lock);
258 return 0; 268 return 0;
259} 269}
260 270
@@ -265,12 +275,25 @@ static struct mdio_ops mi1_mdio_ext_ops = {
265}; 275};
266 276
267enum { 277enum {
278 CH_BRD_T110_1CU,
268 CH_BRD_N110_1F, 279 CH_BRD_N110_1F,
269 CH_BRD_N210_1F, 280 CH_BRD_N210_1F,
281 CH_BRD_T210_1F,
282 CH_BRD_T210_1CU,
283 CH_BRD_N204_4CU,
270}; 284};
271 285
272static struct board_info t1_board[] = { 286static struct board_info t1_board[] = {
273 287
288{ CHBT_BOARD_CHT110, 1/*ports#*/,
289 SUPPORTED_10000baseT_Full /*caps*/, CHBT_TERM_T1,
290 CHBT_MAC_PM3393, CHBT_PHY_MY3126,
291 125000000/*clk-core*/, 150000000/*clk-mc3*/, 125000000/*clk-mc4*/,
292 1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 1/*mdien*/,
293 1/*mdiinv*/, 1/*mdc*/, 1/*phybaseaddr*/, &t1_pm3393_ops,
294 &t1_my3126_ops, &mi1_mdio_ext_ops,
295 "Chelsio T110 1x10GBase-CX4 TOE" },
296
274{ CHBT_BOARD_N110, 1/*ports#*/, 297{ CHBT_BOARD_N110, 1/*ports#*/,
275 SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE /*caps*/, CHBT_TERM_T1, 298 SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE /*caps*/, CHBT_TERM_T1,
276 CHBT_MAC_PM3393, CHBT_PHY_88X2010, 299 CHBT_MAC_PM3393, CHBT_PHY_88X2010,
@@ -289,12 +312,36 @@ static struct board_info t1_board[] = {
289 &t1_mv88x201x_ops, &mi1_mdio_ext_ops, 312 &t1_mv88x201x_ops, &mi1_mdio_ext_ops,
290 "Chelsio N210 1x10GBaseX NIC" }, 313 "Chelsio N210 1x10GBaseX NIC" },
291 314
315{ CHBT_BOARD_CHT210, 1/*ports#*/,
316 SUPPORTED_10000baseT_Full /*caps*/, CHBT_TERM_T2,
317 CHBT_MAC_PM3393, CHBT_PHY_88X2010,
318 125000000/*clk-core*/, 133000000/*clk-mc3*/, 125000000/*clk-mc4*/,
319 1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 0/*mdien*/,
320 0/*mdiinv*/, 1/*mdc*/, 0/*phybaseaddr*/, &t1_pm3393_ops,
321 &t1_mv88x201x_ops, &mi1_mdio_ext_ops,
322 "Chelsio T210 1x10GBaseX TOE" },
323
324{ CHBT_BOARD_CHT210, 1/*ports#*/,
325 SUPPORTED_10000baseT_Full /*caps*/, CHBT_TERM_T2,
326 CHBT_MAC_PM3393, CHBT_PHY_MY3126,
327 125000000/*clk-core*/, 133000000/*clk-mc3*/, 125000000/*clk-mc4*/,
328 1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 1/*mdien*/,
329 1/*mdiinv*/, 1/*mdc*/, 1/*phybaseaddr*/, &t1_pm3393_ops,
330 &t1_my3126_ops, &mi1_mdio_ext_ops,
331 "Chelsio T210 1x10GBase-CX4 TOE" },
332
333
292}; 334};
293 335
294struct pci_device_id t1_pci_tbl[] = { 336struct pci_device_id t1_pci_tbl[] = {
337 CH_DEVICE(8, 0, CH_BRD_T110_1CU),
338 CH_DEVICE(8, 1, CH_BRD_T110_1CU),
295 CH_DEVICE(7, 0, CH_BRD_N110_1F), 339 CH_DEVICE(7, 0, CH_BRD_N110_1F),
296 CH_DEVICE(10, 1, CH_BRD_N210_1F), 340 CH_DEVICE(10, 1, CH_BRD_N210_1F),
297 { 0, } 341 CH_DEVICE(11, 1, CH_BRD_T210_1F),
342 CH_DEVICE(14, 1, CH_BRD_T210_1CU),
343 CH_DEVICE(16, 1, CH_BRD_N204_4CU),
344 { 0 }
298}; 345};
299 346
300MODULE_DEVICE_TABLE(pci, t1_pci_tbl); 347MODULE_DEVICE_TABLE(pci, t1_pci_tbl);
@@ -390,9 +437,14 @@ int t1_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc)
390 if (lc->supported & SUPPORTED_Autoneg) { 437 if (lc->supported & SUPPORTED_Autoneg) {
391 lc->advertising &= ~(ADVERTISED_ASYM_PAUSE | ADVERTISED_PAUSE); 438 lc->advertising &= ~(ADVERTISED_ASYM_PAUSE | ADVERTISED_PAUSE);
392 if (fc) { 439 if (fc) {
393 lc->advertising |= ADVERTISED_ASYM_PAUSE; 440 if (fc == ((PAUSE_RX | PAUSE_TX) &
394 if (fc == (PAUSE_RX | PAUSE_TX)) 441 (mac->adapter->params.nports < 2)))
395 lc->advertising |= ADVERTISED_PAUSE; 442 lc->advertising |= ADVERTISED_PAUSE;
443 else {
444 lc->advertising |= ADVERTISED_ASYM_PAUSE;
445 if (fc == PAUSE_RX)
446 lc->advertising |= ADVERTISED_PAUSE;
447 }
396 } 448 }
397 phy->ops->advertise(phy, lc->advertising); 449 phy->ops->advertise(phy, lc->advertising);
398 450
@@ -403,11 +455,15 @@ int t1_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc)
403 mac->ops->set_speed_duplex_fc(mac, lc->speed, 455 mac->ops->set_speed_duplex_fc(mac, lc->speed,
404 lc->duplex, fc); 456 lc->duplex, fc);
405 /* Also disables autoneg */ 457 /* Also disables autoneg */
458 phy->state = PHY_AUTONEG_RDY;
406 phy->ops->set_speed_duplex(phy, lc->speed, lc->duplex); 459 phy->ops->set_speed_duplex(phy, lc->speed, lc->duplex);
407 phy->ops->reset(phy, 0); 460 phy->ops->reset(phy, 0);
408 } else 461 } else {
462 phy->state = PHY_AUTONEG_EN;
409 phy->ops->autoneg_enable(phy); /* also resets PHY */ 463 phy->ops->autoneg_enable(phy); /* also resets PHY */
464 }
410 } else { 465 } else {
466 phy->state = PHY_AUTONEG_RDY;
411 mac->ops->set_speed_duplex_fc(mac, -1, -1, fc); 467 mac->ops->set_speed_duplex_fc(mac, -1, -1, fc);
412 lc->fc = (unsigned char)fc; 468 lc->fc = (unsigned char)fc;
413 phy->ops->reset(phy, 0); 469 phy->ops->reset(phy, 0);
@@ -418,7 +474,7 @@ int t1_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc)
418/* 474/*
419 * External interrupt handler for boards using elmer0. 475 * External interrupt handler for boards using elmer0.
420 */ 476 */
421int elmer0_ext_intr_handler(adapter_t *adapter) 477int t1_elmer0_ext_intr_handler(adapter_t *adapter)
422{ 478{
423 struct cphy *phy; 479 struct cphy *phy;
424 int phy_cause; 480 int phy_cause;
@@ -427,14 +483,33 @@ int elmer0_ext_intr_handler(adapter_t *adapter)
427 t1_tpi_read(adapter, A_ELMER0_INT_CAUSE, &cause); 483 t1_tpi_read(adapter, A_ELMER0_INT_CAUSE, &cause);
428 484
429 switch (board_info(adapter)->board) { 485 switch (board_info(adapter)->board) {
486 case CHBT_BOARD_CHT210:
430 case CHBT_BOARD_N210: 487 case CHBT_BOARD_N210:
431 case CHBT_BOARD_N110: 488 case CHBT_BOARD_N110:
432 if (cause & ELMER0_GP_BIT6) { /* Marvell 88x2010 interrupt */ 489 if (cause & ELMER0_GP_BIT6) { /* Marvell 88x2010 interrupt */
433 phy = adapter->port[0].phy; 490 phy = adapter->port[0].phy;
434 phy_cause = phy->ops->interrupt_handler(phy); 491 phy_cause = phy->ops->interrupt_handler(phy);
435 if (phy_cause & cphy_cause_link_change) 492 if (phy_cause & cphy_cause_link_change)
436 link_changed(adapter, 0); 493 t1_link_changed(adapter, 0);
494 }
495 break;
496 case CHBT_BOARD_8000:
497 case CHBT_BOARD_CHT110:
498 CH_DBG(adapter, INTR, "External interrupt cause 0x%x\n",
499 cause);
500 if (cause & ELMER0_GP_BIT1) { /* PMC3393 INTB */
501 struct cmac *mac = adapter->port[0].mac;
502
503 mac->ops->interrupt_handler(mac);
437 } 504 }
505 if (cause & ELMER0_GP_BIT5) { /* XPAK MOD_DETECT */
506 u32 mod_detect;
507
508 t1_tpi_read(adapter,
509 A_ELMER0_GPI_STAT, &mod_detect);
510 CH_MSG(adapter, INFO, LINK, "XPAK %s\n",
511 mod_detect ? "removed" : "inserted");
512 }
438 break; 513 break;
439 } 514 }
440 t1_tpi_write(adapter, A_ELMER0_INT_CAUSE, cause); 515 t1_tpi_write(adapter, A_ELMER0_INT_CAUSE, cause);
@@ -445,11 +520,11 @@ int elmer0_ext_intr_handler(adapter_t *adapter)
445void t1_interrupts_enable(adapter_t *adapter) 520void t1_interrupts_enable(adapter_t *adapter)
446{ 521{
447 unsigned int i; 522 unsigned int i;
448 u32 pl_intr;
449 523
450 adapter->slow_intr_mask = F_PL_INTR_SGE_ERR; 524 adapter->slow_intr_mask = F_PL_INTR_SGE_ERR | F_PL_INTR_TP;
451 525
452 t1_sge_intr_enable(adapter->sge); 526 t1_sge_intr_enable(adapter->sge);
527 t1_tp_intr_enable(adapter->tp);
453 if (adapter->espi) { 528 if (adapter->espi) {
454 adapter->slow_intr_mask |= F_PL_INTR_ESPI; 529 adapter->slow_intr_mask |= F_PL_INTR_ESPI;
455 t1_espi_intr_enable(adapter->espi); 530 t1_espi_intr_enable(adapter->espi);
@@ -462,15 +537,17 @@ void t1_interrupts_enable(adapter_t *adapter)
462 } 537 }
463 538
464 /* Enable PCIX & external chip interrupts on ASIC boards. */ 539 /* Enable PCIX & external chip interrupts on ASIC boards. */
465 pl_intr = readl(adapter->regs + A_PL_ENABLE); 540 if (t1_is_asic(adapter)) {
541 u32 pl_intr = readl(adapter->regs + A_PL_ENABLE);
466 542
467 /* PCI-X interrupts */ 543 /* PCI-X interrupts */
468 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_ENABLE, 544 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_ENABLE,
469 0xffffffff); 545 0xffffffff);
470 546
471 adapter->slow_intr_mask |= F_PL_INTR_EXT | F_PL_INTR_PCIX; 547 adapter->slow_intr_mask |= F_PL_INTR_EXT | F_PL_INTR_PCIX;
472 pl_intr |= F_PL_INTR_EXT | F_PL_INTR_PCIX; 548 pl_intr |= F_PL_INTR_EXT | F_PL_INTR_PCIX;
473 writel(pl_intr, adapter->regs + A_PL_ENABLE); 549 writel(pl_intr, adapter->regs + A_PL_ENABLE);
550 }
474} 551}
475 552
476/* Disables all interrupts. */ 553/* Disables all interrupts. */
@@ -479,6 +556,7 @@ void t1_interrupts_disable(adapter_t* adapter)
479 unsigned int i; 556 unsigned int i;
480 557
481 t1_sge_intr_disable(adapter->sge); 558 t1_sge_intr_disable(adapter->sge);
559 t1_tp_intr_disable(adapter->tp);
482 if (adapter->espi) 560 if (adapter->espi)
483 t1_espi_intr_disable(adapter->espi); 561 t1_espi_intr_disable(adapter->espi);
484 562
@@ -489,7 +567,8 @@ void t1_interrupts_disable(adapter_t* adapter)
489 } 567 }
490 568
491 /* Disable PCIX & external chip interrupts. */ 569 /* Disable PCIX & external chip interrupts. */
492 writel(0, adapter->regs + A_PL_ENABLE); 570 if (t1_is_asic(adapter))
571 writel(0, adapter->regs + A_PL_ENABLE);
493 572
494 /* PCI-X interrupts */ 573 /* PCI-X interrupts */
495 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_ENABLE, 0); 574 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_ENABLE, 0);
@@ -501,10 +580,9 @@ void t1_interrupts_disable(adapter_t* adapter)
501void t1_interrupts_clear(adapter_t* adapter) 580void t1_interrupts_clear(adapter_t* adapter)
502{ 581{
503 unsigned int i; 582 unsigned int i;
504 u32 pl_intr;
505
506 583
507 t1_sge_intr_clear(adapter->sge); 584 t1_sge_intr_clear(adapter->sge);
585 t1_tp_intr_clear(adapter->tp);
508 if (adapter->espi) 586 if (adapter->espi)
509 t1_espi_intr_clear(adapter->espi); 587 t1_espi_intr_clear(adapter->espi);
510 588
@@ -515,10 +593,12 @@ void t1_interrupts_clear(adapter_t* adapter)
515 } 593 }
516 594
517 /* Enable interrupts for external devices. */ 595 /* Enable interrupts for external devices. */
518 pl_intr = readl(adapter->regs + A_PL_CAUSE); 596 if (t1_is_asic(adapter)) {
597 u32 pl_intr = readl(adapter->regs + A_PL_CAUSE);
519 598
520 writel(pl_intr | F_PL_INTR_EXT | F_PL_INTR_PCIX, 599 writel(pl_intr | F_PL_INTR_EXT | F_PL_INTR_PCIX,
521 adapter->regs + A_PL_CAUSE); 600 adapter->regs + A_PL_CAUSE);
601 }
522 602
523 /* PCI-X interrupts */ 603 /* PCI-X interrupts */
524 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE, 0xffffffff); 604 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE, 0xffffffff);
@@ -527,7 +607,7 @@ void t1_interrupts_clear(adapter_t* adapter)
527/* 607/*
528 * Slow path interrupt handler for ASICs. 608 * Slow path interrupt handler for ASICs.
529 */ 609 */
530int t1_slow_intr_handler(adapter_t *adapter) 610static int asic_slow_intr(adapter_t *adapter)
531{ 611{
532 u32 cause = readl(adapter->regs + A_PL_CAUSE); 612 u32 cause = readl(adapter->regs + A_PL_CAUSE);
533 613
@@ -536,89 +616,50 @@ int t1_slow_intr_handler(adapter_t *adapter)
536 return 0; 616 return 0;
537 if (cause & F_PL_INTR_SGE_ERR) 617 if (cause & F_PL_INTR_SGE_ERR)
538 t1_sge_intr_error_handler(adapter->sge); 618 t1_sge_intr_error_handler(adapter->sge);
619 if (cause & F_PL_INTR_TP)
620 t1_tp_intr_handler(adapter->tp);
539 if (cause & F_PL_INTR_ESPI) 621 if (cause & F_PL_INTR_ESPI)
540 t1_espi_intr_handler(adapter->espi); 622 t1_espi_intr_handler(adapter->espi);
541 if (cause & F_PL_INTR_PCIX) 623 if (cause & F_PL_INTR_PCIX)
542 t1_pci_intr_handler(adapter); 624 t1_pci_intr_handler(adapter);
543 if (cause & F_PL_INTR_EXT) 625 if (cause & F_PL_INTR_EXT)
544 t1_elmer0_ext_intr(adapter); 626 t1_elmer0_ext_intr_handler(adapter);
545 627
546 /* Clear the interrupts just processed. */ 628 /* Clear the interrupts just processed. */
547 writel(cause, adapter->regs + A_PL_CAUSE); 629 writel(cause, adapter->regs + A_PL_CAUSE);
548 (void)readl(adapter->regs + A_PL_CAUSE); /* flush writes */ 630 readl(adapter->regs + A_PL_CAUSE); /* flush writes */
549 return 1; 631 return 1;
550} 632}
551 633
552/* Pause deadlock avoidance parameters */ 634int t1_slow_intr_handler(adapter_t *adapter)
553#define DROP_MSEC 16
554#define DROP_PKTS_CNT 1
555
556static void set_csum_offload(adapter_t *adapter, u32 csum_bit, int enable)
557{
558 u32 val = readl(adapter->regs + A_TP_GLOBAL_CONFIG);
559
560 if (enable)
561 val |= csum_bit;
562 else
563 val &= ~csum_bit;
564 writel(val, adapter->regs + A_TP_GLOBAL_CONFIG);
565}
566
567void t1_tp_set_ip_checksum_offload(adapter_t *adapter, int enable)
568{
569 set_csum_offload(adapter, F_IP_CSUM, enable);
570}
571
572void t1_tp_set_udp_checksum_offload(adapter_t *adapter, int enable)
573{ 635{
574 set_csum_offload(adapter, F_UDP_CSUM, enable); 636 return asic_slow_intr(adapter);
575} 637}
576 638
577void t1_tp_set_tcp_checksum_offload(adapter_t *adapter, int enable) 639/* Power sequencing is a work-around for Intel's XPAKs. */
640static void power_sequence_xpak(adapter_t* adapter)
578{ 641{
579 set_csum_offload(adapter, F_TCP_CSUM, enable); 642 u32 mod_detect;
580} 643 u32 gpo;
581 644
582static void t1_tp_reset(adapter_t *adapter, unsigned int tp_clk) 645 /* Check for XPAK */
583{ 646 t1_tpi_read(adapter, A_ELMER0_GPI_STAT, &mod_detect);
584 u32 val; 647 if (!(ELMER0_GP_BIT5 & mod_detect)) {
585 648 /* XPAK is present */
586 val = F_TP_IN_CSPI_CPL | F_TP_IN_CSPI_CHECK_IP_CSUM | 649 t1_tpi_read(adapter, A_ELMER0_GPO, &gpo);
587 F_TP_IN_CSPI_CHECK_TCP_CSUM | F_TP_IN_ESPI_ETHERNET; 650 gpo |= ELMER0_GP_BIT18;
588 val |= F_TP_IN_ESPI_CHECK_IP_CSUM | 651 t1_tpi_write(adapter, A_ELMER0_GPO, gpo);
589 F_TP_IN_ESPI_CHECK_TCP_CSUM;
590 writel(val, adapter->regs + A_TP_IN_CONFIG);
591 writel(F_TP_OUT_CSPI_CPL |
592 F_TP_OUT_ESPI_ETHERNET |
593 F_TP_OUT_ESPI_GENERATE_IP_CSUM |
594 F_TP_OUT_ESPI_GENERATE_TCP_CSUM,
595 adapter->regs + A_TP_OUT_CONFIG);
596
597 val = readl(adapter->regs + A_TP_GLOBAL_CONFIG);
598 val &= ~(F_IP_CSUM | F_UDP_CSUM | F_TCP_CSUM);
599 writel(val, adapter->regs + A_TP_GLOBAL_CONFIG);
600
601 /*
602 * Enable pause frame deadlock prevention.
603 */
604 if (is_T2(adapter)) {
605 u32 drop_ticks = DROP_MSEC * (tp_clk / 1000);
606
607 writel(F_ENABLE_TX_DROP | F_ENABLE_TX_ERROR |
608 V_DROP_TICKS_CNT(drop_ticks) |
609 V_NUM_PKTS_DROPPED(DROP_PKTS_CNT),
610 adapter->regs + A_TP_TX_DROP_CONFIG);
611 } 652 }
612
613 writel(F_TP_RESET, adapter->regs + A_TP_RESET);
614} 653}
615 654
616int __devinit t1_get_board_rev(adapter_t *adapter, const struct board_info *bi, 655int __devinit t1_get_board_rev(adapter_t *adapter, const struct board_info *bi,
617 struct adapter_params *p) 656 struct adapter_params *p)
618{ 657{
619 p->chip_version = bi->chip_term; 658 p->chip_version = bi->chip_term;
659 p->is_asic = (p->chip_version != CHBT_TERM_FPGA);
620 if (p->chip_version == CHBT_TERM_T1 || 660 if (p->chip_version == CHBT_TERM_T1 ||
621 p->chip_version == CHBT_TERM_T2) { 661 p->chip_version == CHBT_TERM_T2 ||
662 p->chip_version == CHBT_TERM_FPGA) {
622 u32 val = readl(adapter->regs + A_TP_PC_CONFIG); 663 u32 val = readl(adapter->regs + A_TP_PC_CONFIG);
623 664
624 val = G_TP_PC_REV(val); 665 val = G_TP_PC_REV(val);
@@ -640,10 +681,22 @@ int __devinit t1_get_board_rev(adapter_t *adapter, const struct board_info *bi,
640static int board_init(adapter_t *adapter, const struct board_info *bi) 681static int board_init(adapter_t *adapter, const struct board_info *bi)
641{ 682{
642 switch (bi->board) { 683 switch (bi->board) {
684 case CHBT_BOARD_8000:
643 case CHBT_BOARD_N110: 685 case CHBT_BOARD_N110:
644 case CHBT_BOARD_N210: 686 case CHBT_BOARD_N210:
645 writel(V_TPIPAR(0xf), adapter->regs + A_TPI_PAR); 687 case CHBT_BOARD_CHT210:
646 t1_tpi_write(adapter, A_ELMER0_GPO, 0x800); 688 case CHBT_BOARD_COUGAR:
689 t1_tpi_par(adapter, 0xf);
690 t1_tpi_write(adapter, A_ELMER0_GPO, 0x800);
691 break;
692 case CHBT_BOARD_CHT110:
693 t1_tpi_par(adapter, 0xf);
694 t1_tpi_write(adapter, A_ELMER0_GPO, 0x1800);
695
696 /* TBD XXX Might not need. This fixes a problem
697 * described in the Intel SR XPAK errata.
698 */
699 power_sequence_xpak(adapter);
647 break; 700 break;
648 } 701 }
649 return 0; 702 return 0;
@@ -670,7 +723,8 @@ int t1_init_hw_modules(adapter_t *adapter)
670 bi->espi_nports)) 723 bi->espi_nports))
671 goto out_err; 724 goto out_err;
672 725
673 t1_tp_reset(adapter, bi->clock_core); 726 if (t1_tp_reset(adapter->tp, &adapter->params.tp, bi->clock_core))
727 goto out_err;
674 728
675 err = t1_sge_configure(adapter->sge, &adapter->params.sge); 729 err = t1_sge_configure(adapter->sge, &adapter->params.sge);
676 if (err) 730 if (err)
@@ -714,6 +768,8 @@ void t1_free_sw_modules(adapter_t *adapter)
714 768
715 if (adapter->sge) 769 if (adapter->sge)
716 t1_sge_destroy(adapter->sge); 770 t1_sge_destroy(adapter->sge);
771 if (adapter->tp)
772 t1_tp_destroy(adapter->tp);
717 if (adapter->espi) 773 if (adapter->espi)
718 t1_espi_destroy(adapter->espi); 774 t1_espi_destroy(adapter->espi);
719} 775}
@@ -762,6 +818,13 @@ int __devinit t1_init_sw_modules(adapter_t *adapter,
762 goto error; 818 goto error;
763 } 819 }
764 820
821 adapter->tp = t1_tp_create(adapter, &adapter->params.tp);
822 if (!adapter->tp) {
823 CH_ERR("%s: TP initialization failed\n",
824 adapter->name);
825 goto error;
826 }
827
765 board_init(adapter, bi); 828 board_init(adapter, bi);
766 bi->mdio_ops->init(adapter, bi); 829 bi->mdio_ops->init(adapter, bi);
767 if (bi->gphy->reset) 830 if (bi->gphy->reset)
@@ -793,7 +856,9 @@ int __devinit t1_init_sw_modules(adapter_t *adapter,
793 * Get the port's MAC addresses either from the EEPROM if one 856 * Get the port's MAC addresses either from the EEPROM if one
794 * exists or the one hardcoded in the MAC. 857 * exists or the one hardcoded in the MAC.
795 */ 858 */
796 if (vpd_macaddress_get(adapter, i, hw_addr)) { 859 if (!t1_is_asic(adapter) || bi->chip_mac == CHBT_MAC_DUMMY)
860 mac->ops->macaddress_get(mac, hw_addr);
861 else if (vpd_macaddress_get(adapter, i, hw_addr)) {
797 CH_ERR("%s: could not read MAC address from VPD ROM\n", 862 CH_ERR("%s: could not read MAC address from VPD ROM\n",
798 adapter->port[i].dev->name); 863 adapter->port[i].dev->name);
799 goto error; 864 goto error;
@@ -806,7 +871,7 @@ int __devinit t1_init_sw_modules(adapter_t *adapter,
806 t1_interrupts_clear(adapter); 871 t1_interrupts_clear(adapter);
807 return 0; 872 return 0;
808 873
809 error: 874error:
810 t1_free_sw_modules(adapter); 875 t1_free_sw_modules(adapter);
811 return -1; 876 return -1;
812} 877}
diff --git a/drivers/net/chelsio/suni1x10gexp_regs.h b/drivers/net/chelsio/suni1x10gexp_regs.h
index 81816c2b708a..269d097dd927 100644
--- a/drivers/net/chelsio/suni1x10gexp_regs.h
+++ b/drivers/net/chelsio/suni1x10gexp_regs.h
@@ -32,6 +32,30 @@
32#ifndef _CXGB_SUNI1x10GEXP_REGS_H_ 32#ifndef _CXGB_SUNI1x10GEXP_REGS_H_
33#define _CXGB_SUNI1x10GEXP_REGS_H_ 33#define _CXGB_SUNI1x10GEXP_REGS_H_
34 34
35/*
36** Space allocated for each Exact Match Filter
37** There are 8 filter configurations
38*/
39#define SUNI1x10GEXP_REG_SIZEOF_MAC_FILTER 0x0003
40
41#define mSUNI1x10GEXP_MAC_FILTER_OFFSET(filterId) ( (filterId) * SUNI1x10GEXP_REG_SIZEOF_MAC_FILTER )
42
43/*
44** Space allocated for VLAN-Id Filter
45** There are 8 filter configurations
46*/
47#define SUNI1x10GEXP_REG_SIZEOF_MAC_VID_FILTER 0x0001
48
49#define mSUNI1x10GEXP_MAC_VID_FILTER_OFFSET(filterId) ( (filterId) * SUNI1x10GEXP_REG_SIZEOF_MAC_VID_FILTER )
50
51/*
52** Space allocated for each MSTAT Counter
53*/
54#define SUNI1x10GEXP_REG_SIZEOF_MSTAT_COUNT 0x0004
55
56#define mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(countId) ( (countId) * SUNI1x10GEXP_REG_SIZEOF_MSTAT_COUNT )
57
58
35/******************************************************************************/ 59/******************************************************************************/
36/** S/UNI-1x10GE-XP REGISTER ADDRESS MAP **/ 60/** S/UNI-1x10GE-XP REGISTER ADDRESS MAP **/
37/******************************************************************************/ 61/******************************************************************************/
@@ -39,33 +63,125 @@
39/* to the S/UNI-1x10GE-XP Data Sheet for the signification of each bit */ 63/* to the S/UNI-1x10GE-XP Data Sheet for the signification of each bit */
40/******************************************************************************/ 64/******************************************************************************/
41 65
66
67#define SUNI1x10GEXP_REG_IDENTIFICATION 0x0000
68#define SUNI1x10GEXP_REG_PRODUCT_REVISION 0x0001
69#define SUNI1x10GEXP_REG_CONFIG_AND_RESET_CONTROL 0x0002
70#define SUNI1x10GEXP_REG_LOOPBACK_MISC_CTRL 0x0003
42#define SUNI1x10GEXP_REG_DEVICE_STATUS 0x0004 71#define SUNI1x10GEXP_REG_DEVICE_STATUS 0x0004
72#define SUNI1x10GEXP_REG_GLOBAL_PERFORMANCE_MONITOR_UPDATE 0x0005
73
74#define SUNI1x10GEXP_REG_MDIO_COMMAND 0x0006
75#define SUNI1x10GEXP_REG_MDIO_INTERRUPT_ENABLE 0x0007
76#define SUNI1x10GEXP_REG_MDIO_INTERRUPT_STATUS 0x0008
77#define SUNI1x10GEXP_REG_MMD_PHY_ADDRESS 0x0009
78#define SUNI1x10GEXP_REG_MMD_CONTROL_ADDRESS_DATA 0x000A
79#define SUNI1x10GEXP_REG_MDIO_READ_STATUS_DATA 0x000B
80
81#define SUNI1x10GEXP_REG_OAM_INTF_CTRL 0x000C
43#define SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS 0x000D 82#define SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS 0x000D
44#define SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE 0x000E 83#define SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE 0x000E
84#define SUNI1x10GEXP_REG_FREE 0x000F
85
86#define SUNI1x10GEXP_REG_XTEF_MISC_CTRL 0x0010
87#define SUNI1x10GEXP_REG_XRF_MISC_CTRL 0x0011
88
89#define SUNI1x10GEXP_REG_SERDES_3125_CONFIG_1 0x0100
90#define SUNI1x10GEXP_REG_SERDES_3125_CONFIG_2 0x0101
45#define SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE 0x0102 91#define SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE 0x0102
92#define SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_VISIBLE 0x0103
46#define SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_STATUS 0x0104 93#define SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_STATUS 0x0104
94#define SUNI1x10GEXP_REG_SERDES_3125_TEST_CONFIG 0x0107
95
47#define SUNI1x10GEXP_REG_RXXG_CONFIG_1 0x2040 96#define SUNI1x10GEXP_REG_RXXG_CONFIG_1 0x2040
97#define SUNI1x10GEXP_REG_RXXG_CONFIG_2 0x2041
48#define SUNI1x10GEXP_REG_RXXG_CONFIG_3 0x2042 98#define SUNI1x10GEXP_REG_RXXG_CONFIG_3 0x2042
49#define SUNI1x10GEXP_REG_RXXG_INTERRUPT 0x2043 99#define SUNI1x10GEXP_REG_RXXG_INTERRUPT 0x2043
50#define SUNI1x10GEXP_REG_RXXG_MAX_FRAME_LENGTH 0x2045 100#define SUNI1x10GEXP_REG_RXXG_MAX_FRAME_LENGTH 0x2045
51#define SUNI1x10GEXP_REG_RXXG_SA_15_0 0x2046 101#define SUNI1x10GEXP_REG_RXXG_SA_15_0 0x2046
52#define SUNI1x10GEXP_REG_RXXG_SA_31_16 0x2047 102#define SUNI1x10GEXP_REG_RXXG_SA_31_16 0x2047
53#define SUNI1x10GEXP_REG_RXXG_SA_47_32 0x2048 103#define SUNI1x10GEXP_REG_RXXG_SA_47_32 0x2048
104#define SUNI1x10GEXP_REG_RXXG_RECEIVE_FIFO_THRESHOLD 0x2049
105#define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_LOW(filterId) (0x204A + mSUNI1x10GEXP_MAC_FILTER_OFFSET(filterId))
106#define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_MID(filterId) (0x204B + mSUNI1x10GEXP_MAC_FILTER_OFFSET(filterId))
107#define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_HIGH(filterId)(0x204C + mSUNI1x10GEXP_MAC_FILTER_OFFSET(filterId))
108#define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID(filterId) (0x2062 + mSUNI1x10GEXP_MAC_VID_FILTER_OFFSET(filterId)
109#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_0_LOW 0x204A
110#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_0_MID 0x204B
111#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_0_HIGH 0x204C
54#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_LOW 0x204D 112#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_LOW 0x204D
55#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_MID 0x204E 113#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_MID 0x204E
56#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_HIGH 0x204F 114#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_HIGH 0x204F
115#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_2_LOW 0x2050
116#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_2_MID 0x2051
117#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_2_HIGH 0x2052
118#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_3_LOW 0x2053
119#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_3_MID 0x2054
120#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_3_HIGH 0x2055
121#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_4_LOW 0x2056
122#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_4_MID 0x2057
123#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_4_HIGH 0x2058
124#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_5_LOW 0x2059
125#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_5_MID 0x205A
126#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_5_HIGH 0x205B
127#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_6_LOW 0x205C
128#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_6_MID 0x205D
129#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_6_HIGH 0x205E
130#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_7_LOW 0x205F
131#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_7_MID 0x2060
132#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_7_HIGH 0x2061
133#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_0 0x2062
134#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_1 0x2063
135#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_2 0x2064
136#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_3 0x2065
137#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_4 0x2066
138#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_5 0x2067
139#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_6 0x2068
140#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_7 0x2069
57#define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW 0x206A 141#define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW 0x206A
58#define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW 0x206B 142#define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW 0x206B
59#define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH 0x206C 143#define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH 0x206C
60#define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH 0x206D 144#define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH 0x206D
61#define SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0 0x206E 145#define SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0 0x206E
146#define SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_1 0x206F
62#define SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2 0x2070 147#define SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2 0x2070
148
149#define SUNI1x10GEXP_REG_XRF_PATTERN_GEN_CTRL 0x2081
150#define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_0 0x2084
151#define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_1 0x2085
152#define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_2 0x2086
153#define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_3 0x2087
63#define SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE 0x2088 154#define SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE 0x2088
64#define SUNI1x10GEXP_REG_XRF_INTERRUPT_STATUS 0x2089 155#define SUNI1x10GEXP_REG_XRF_INTERRUPT_STATUS 0x2089
156#define SUNI1x10GEXP_REG_XRF_ERR_STATUS 0x208A
65#define SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE 0x208B 157#define SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE 0x208B
66#define SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_STATUS 0x208C 158#define SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_STATUS 0x208C
159#define SUNI1x10GEXP_REG_XRF_CODE_ERR_THRES 0x2092
160
161#define SUNI1x10GEXP_REG_RXOAM_CONFIG 0x20C0
162#define SUNI1x10GEXP_REG_RXOAM_FILTER_1_CONFIG 0x20C1
163#define SUNI1x10GEXP_REG_RXOAM_FILTER_2_CONFIG 0x20C2
164#define SUNI1x10GEXP_REG_RXOAM_CONFIG_2 0x20C3
165#define SUNI1x10GEXP_REG_RXOAM_HEC_CONFIG 0x20C4
166#define SUNI1x10GEXP_REG_RXOAM_HEC_ERR_THRES 0x20C5
67#define SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE 0x20C7 167#define SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE 0x20C7
68#define SUNI1x10GEXP_REG_RXOAM_INTERRUPT_STATUS 0x20C8 168#define SUNI1x10GEXP_REG_RXOAM_INTERRUPT_STATUS 0x20C8
169#define SUNI1x10GEXP_REG_RXOAM_STATUS 0x20C9
170#define SUNI1x10GEXP_REG_RXOAM_HEC_ERR_COUNT 0x20CA
171#define SUNI1x10GEXP_REG_RXOAM_FIFO_OVERFLOW_COUNT 0x20CB
172#define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_COUNT_LSB 0x20CC
173#define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_COUNT_MSB 0x20CD
174#define SUNI1x10GEXP_REG_RXOAM_FILTER_1_MISMATCH_COUNT_LSB 0x20CE
175#define SUNI1x10GEXP_REG_RXOAM_FILTER_1_MISMATCH_COUNT_MSB 0x20CF
176#define SUNI1x10GEXP_REG_RXOAM_FILTER_2_MISMATCH_COUNT_LSB 0x20D0
177#define SUNI1x10GEXP_REG_RXOAM_FILTER_2_MISMATCH_COUNT_MSB 0x20D1
178#define SUNI1x10GEXP_REG_RXOAM_OAM_EXTRACT_COUNT_LSB 0x20D2
179#define SUNI1x10GEXP_REG_RXOAM_OAM_EXTRACT_COUNT_MSB 0x20D3
180#define SUNI1x10GEXP_REG_RXOAM_MINI_PACKET_COUNT_LSB 0x20D4
181#define SUNI1x10GEXP_REG_RXOAM_MINI_PACKET_COUNT_MSB 0x20D5
182#define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_THRES_LSB 0x20D6
183#define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_THRES_MSB 0x20D7
184
69#define SUNI1x10GEXP_REG_MSTAT_CONTROL 0x2100 185#define SUNI1x10GEXP_REG_MSTAT_CONTROL 0x2100
70#define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_0 0x2101 186#define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_0 0x2101
71#define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_1 0x2102 187#define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_1 0x2102
@@ -75,50 +191,321 @@
75#define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1 0x2106 191#define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1 0x2106
76#define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2 0x2107 192#define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2 0x2107
77#define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3 0x2108 193#define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3 0x2108
194#define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_ADDRESS 0x2109
195#define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_DATA_LOW 0x210A
196#define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_DATA_MIDDLE 0x210B
197#define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_DATA_HIGH 0x210C
198#define mSUNI1x10GEXP_REG_MSTAT_COUNTER_LOW(countId) (0x2110 + mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(countId))
199#define mSUNI1x10GEXP_REG_MSTAT_COUNTER_MID(countId) (0x2111 + mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(countId))
200#define mSUNI1x10GEXP_REG_MSTAT_COUNTER_HIGH(countId) (0x2112 + mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(countId))
78#define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_LOW 0x2110 201#define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_LOW 0x2110
202#define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_MID 0x2111
203#define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_HIGH 0x2112
204#define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_RESVD 0x2113
79#define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_LOW 0x2114 205#define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_LOW 0x2114
206#define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_MID 0x2115
207#define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_HIGH 0x2116
208#define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_RESVD 0x2117
209#define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_LOW 0x2118
210#define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_MID 0x2119
211#define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_HIGH 0x211A
212#define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_RESVD 0x211B
213#define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_LOW 0x211C
214#define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_MID 0x211D
215#define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_HIGH 0x211E
216#define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_RESVD 0x211F
80#define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_LOW 0x2120 217#define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_LOW 0x2120
218#define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_MID 0x2121
219#define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_HIGH 0x2122
220#define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_RESVD 0x2123
81#define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_LOW 0x2124 221#define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_LOW 0x2124
222#define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_MID 0x2125
223#define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_HIGH 0x2126
224#define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_RESVD 0x2127
82#define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_LOW 0x2128 225#define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_LOW 0x2128
226#define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_MID 0x2129
227#define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_HIGH 0x212A
228#define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_RESVD 0x212B
229#define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_LOW 0x212C
230#define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_MID 0x212D
231#define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_HIGH 0x212E
232#define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_RESVD 0x212F
83#define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_LOW 0x2130 233#define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_LOW 0x2130
234#define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_MID 0x2131
235#define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_HIGH 0x2132
236#define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_RESVD 0x2133
237#define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_LOW 0x2134
238#define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_MID 0x2135
239#define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_HIGH 0x2136
240#define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_RESVD 0x2137
84#define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_LOW 0x2138 241#define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_LOW 0x2138
242#define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_MID 0x2139
243#define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_HIGH 0x213A
244#define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_RESVD 0x213B
85#define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_LOW 0x213C 245#define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_LOW 0x213C
246#define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_MID 0x213D
247#define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_HIGH 0x213E
248#define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_RESVD 0x213F
86#define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_LOW 0x2140 249#define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_LOW 0x2140
250#define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_MID 0x2141
251#define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_HIGH 0x2142
252#define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_RESVD 0x2143
87#define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_LOW 0x2144 253#define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_LOW 0x2144
254#define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_MID 0x2145
255#define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_HIGH 0x2146
256#define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_RESVD 0x2147
257#define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_LOW 0x2148
258#define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_MID 0x2149
259#define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_HIGH 0x214A
260#define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_RESVD 0x214B
88#define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_LOW 0x214C 261#define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_LOW 0x214C
262#define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_MID 0x214D
263#define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_HIGH 0x214E
264#define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_RESVD 0x214F
89#define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_LOW 0x2150 265#define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_LOW 0x2150
266#define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_MID 0x2151
267#define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_HIGH 0x2152
268#define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_RESVD 0x2153
90#define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_LOW 0x2154 269#define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_LOW 0x2154
270#define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_MID 0x2155
271#define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_HIGH 0x2156
272#define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_RESVD 0x2157
91#define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_LOW 0x2158 273#define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_LOW 0x2158
274#define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_MID 0x2159
275#define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_HIGH 0x215A
276#define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_RESVD 0x215B
277#define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_LOW 0x215C
278#define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_MID 0x215D
279#define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_HIGH 0x215E
280#define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_RESVD 0x215F
281#define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_LOW 0x2160
282#define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_MID 0x2161
283#define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_HIGH 0x2162
284#define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_RESVD 0x2163
285#define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_LOW 0x2164
286#define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_MID 0x2165
287#define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_HIGH 0x2166
288#define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_RESVD 0x2167
289#define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_LOW 0x2168
290#define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_MID 0x2169
291#define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_HIGH 0x216A
292#define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_RESVD 0x216B
293#define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_LOW 0x216C
294#define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_MID 0x216D
295#define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_HIGH 0x216E
296#define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_RESVD 0x216F
297#define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_LOW 0x2170
298#define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_MID 0x2171
299#define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_HIGH 0x2172
300#define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_RESVD 0x2173
301#define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_LOW 0x2174
302#define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_MID 0x2175
303#define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_HIGH 0x2176
304#define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_RESVD 0x2177
305#define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_LOW 0x2178
306#define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_MID 0x2179
307#define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_HIGH 0x217a
308#define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_RESVD 0x217b
309#define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_LOW 0x217c
310#define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_MID 0x217d
311#define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_HIGH 0x217e
312#define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_RESVD 0x217f
313#define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_LOW 0x2180
314#define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_MID 0x2181
315#define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_HIGH 0x2182
316#define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_RESVD 0x2183
317#define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_LOW 0x2184
318#define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_MID 0x2185
319#define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_HIGH 0x2186
320#define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_RESVD 0x2187
321#define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_LOW 0x2188
322#define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_MID 0x2189
323#define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_HIGH 0x218A
324#define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_RESVD 0x218B
325#define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_LOW 0x218C
326#define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_MID 0x218D
327#define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_HIGH 0x218E
328#define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_RESVD 0x218F
329#define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_LOW 0x2190
330#define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_MID 0x2191
331#define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_HIGH 0x2192
332#define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_RESVD 0x2193
92#define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_LOW 0x2194 333#define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_LOW 0x2194
334#define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_MID 0x2195
335#define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_HIGH 0x2196
336#define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_RESVD 0x2197
337#define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_LOW 0x2198
338#define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_MID 0x2199
339#define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_HIGH 0x219A
340#define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_RESVD 0x219B
93#define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_LOW 0x219C 341#define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_LOW 0x219C
342#define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_MID 0x219D
343#define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_HIGH 0x219E
344#define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_RESVD 0x219F
94#define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_LOW 0x21A0 345#define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_LOW 0x21A0
346#define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_MID 0x21A1
347#define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_HIGH 0x21A2
348#define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_RESVD 0x21A3
349#define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_LOW 0x21A4
350#define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_MID 0x21A5
351#define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_HIGH 0x21A6
352#define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_RESVD 0x21A7
95#define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_LOW 0x21A8 353#define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_LOW 0x21A8
354#define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_MID 0x21A9
355#define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_HIGH 0x21AA
356#define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_RESVD 0x21AB
357#define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_LOW 0x21AC
358#define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_MID 0x21AD
359#define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_HIGH 0x21AE
360#define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_RESVD 0x21AF
96#define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_LOW 0x21B0 361#define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_LOW 0x21B0
362#define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_MID 0x21B1
363#define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_HIGH 0x21B2
364#define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_RESVD 0x21B3
365#define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_LOW 0x21B4
366#define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_MID 0x21B5
367#define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_HIGH 0x21B6
368#define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_RESVD 0x21B7
97#define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_LOW 0x21B8 369#define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_LOW 0x21B8
370#define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_MID 0x21B9
371#define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_HIGH 0x21BA
372#define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_RESVD 0x21BB
98#define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_LOW 0x21BC 373#define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_LOW 0x21BC
374#define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_MID 0x21BD
375#define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_HIGH 0x21BE
376#define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_RESVD 0x21BF
377#define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_LOW 0x21C0
378#define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_MID 0x21C1
379#define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_HIGH 0x21C2
380#define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_RESVD 0x21C3
381#define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_LOW 0x21C4
382#define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_MID 0x21C5
383#define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_HIGH 0x21C6
384#define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_RESVD 0x21C7
385#define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_LOW 0x21C8
386#define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_MID 0x21C9
387#define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_HIGH 0x21CA
388#define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_RESVD 0x21CB
389#define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_LOW 0x21CC
390#define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_MID 0x21CD
391#define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_HIGH 0x21CE
392#define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_RESVD 0x21CF
393#define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_LOW 0x21D0
394#define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_MID 0x21D1
395#define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_HIGH 0x21D2
396#define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_RESVD 0x21D3
397#define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_LOW 0x21D4
398#define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_MID 0x21D5
399#define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_HIGH 0x21D6
400#define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_RESVD 0x21D7
401#define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_LOW 0x21D8
402#define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_MID 0x21D9
403#define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_HIGH 0x21DA
404#define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_RESVD 0x21DB
405#define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_LOW 0x21DC
406#define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_MID 0x21DD
407#define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_HIGH 0x21DE
408#define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_RESVD 0x21DF
409#define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_LOW 0x21E0
410#define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_MID 0x21E1
411#define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_HIGH 0x21E2
412#define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_RESVD 0x21E3
413#define SUNI1x10GEXP_REG_MSTAT_COUNTER_53_LOW 0x21E4
414#define SUNI1x10GEXP_REG_MSTAT_COUNTER_53_MID 0x21E5
415#define SUNI1x10GEXP_REG_MSTAT_COUNTER_53_HIGH 0x21E6
416#define SUNI1x10GEXP_CNTR_MAC_ETHERNET_NUM 51
417
418#define SUNI1x10GEXP_REG_IFLX_GLOBAL_CONFIG 0x2200
419#define SUNI1x10GEXP_REG_IFLX_CHANNEL_PROVISION 0x2201
99#define SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE 0x2209 420#define SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE 0x2209
100#define SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_INTERRUPT 0x220A 421#define SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_INTERRUPT 0x220A
422#define SUNI1x10GEXP_REG_IFLX_INDIR_CHANNEL_ADDRESS 0x220D
423#define SUNI1x10GEXP_REG_IFLX_INDIR_LOGICAL_FIFO_LOW_LIMIT_PROVISION 0x220E
424#define SUNI1x10GEXP_REG_IFLX_INDIR_LOGICAL_FIFO_HIGH_LIMIT 0x220F
425#define SUNI1x10GEXP_REG_IFLX_INDIR_FULL_ALMOST_FULL_STATUS_LIMIT 0x2210
426#define SUNI1x10GEXP_REG_IFLX_INDIR_EMPTY_ALMOST_EMPTY_STATUS_LIMIT 0x2211
427
428#define SUNI1x10GEXP_REG_PL4MOS_CONFIG 0x2240
429#define SUNI1x10GEXP_REG_PL4MOS_MASK 0x2241
430#define SUNI1x10GEXP_REG_PL4MOS_FAIRNESS_MASKING 0x2242
431#define SUNI1x10GEXP_REG_PL4MOS_MAXBURST1 0x2243
432#define SUNI1x10GEXP_REG_PL4MOS_MAXBURST2 0x2244
433#define SUNI1x10GEXP_REG_PL4MOS_TRANSFER_SIZE 0x2245
434
435#define SUNI1x10GEXP_REG_PL4ODP_CONFIG 0x2280
101#define SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK 0x2282 436#define SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK 0x2282
102#define SUNI1x10GEXP_REG_PL4ODP_INTERRUPT 0x2283 437#define SUNI1x10GEXP_REG_PL4ODP_INTERRUPT 0x2283
438#define SUNI1x10GEXP_REG_PL4ODP_CONFIG_MAX_T 0x2284
439
103#define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_STATUS 0x2300 440#define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_STATUS 0x2300
104#define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_CHANGE 0x2301 441#define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_CHANGE 0x2301
105#define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK 0x2302 442#define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK 0x2302
443#define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_LIMITS 0x2303
444#define SUNI1x10GEXP_REG_PL4IO_CALENDAR_REPETITIONS 0x2304
445#define SUNI1x10GEXP_REG_PL4IO_CONFIG 0x2305
446
106#define SUNI1x10GEXP_REG_TXXG_CONFIG_1 0x3040 447#define SUNI1x10GEXP_REG_TXXG_CONFIG_1 0x3040
448#define SUNI1x10GEXP_REG_TXXG_CONFIG_2 0x3041
107#define SUNI1x10GEXP_REG_TXXG_CONFIG_3 0x3042 449#define SUNI1x10GEXP_REG_TXXG_CONFIG_3 0x3042
108#define SUNI1x10GEXP_REG_TXXG_INTERRUPT 0x3043 450#define SUNI1x10GEXP_REG_TXXG_INTERRUPT 0x3043
451#define SUNI1x10GEXP_REG_TXXG_STATUS 0x3044
109#define SUNI1x10GEXP_REG_TXXG_MAX_FRAME_SIZE 0x3045 452#define SUNI1x10GEXP_REG_TXXG_MAX_FRAME_SIZE 0x3045
453#define SUNI1x10GEXP_REG_TXXG_MIN_FRAME_SIZE 0x3046
110#define SUNI1x10GEXP_REG_TXXG_SA_15_0 0x3047 454#define SUNI1x10GEXP_REG_TXXG_SA_15_0 0x3047
111#define SUNI1x10GEXP_REG_TXXG_SA_31_16 0x3048 455#define SUNI1x10GEXP_REG_TXXG_SA_31_16 0x3048
112#define SUNI1x10GEXP_REG_TXXG_SA_47_32 0x3049 456#define SUNI1x10GEXP_REG_TXXG_SA_47_32 0x3049
457#define SUNI1x10GEXP_REG_TXXG_PAUSE_TIMER 0x304D
458#define SUNI1x10GEXP_REG_TXXG_PAUSE_TIMER_INTERVAL 0x304E
459#define SUNI1x10GEXP_REG_TXXG_FILTER_ERROR_COUNTER 0x3051
460#define SUNI1x10GEXP_REG_TXXG_PAUSE_QUANTUM_CONFIG 0x3052
461
462#define SUNI1x10GEXP_REG_XTEF_CTRL 0x3080
113#define SUNI1x10GEXP_REG_XTEF_INTERRUPT_STATUS 0x3084 463#define SUNI1x10GEXP_REG_XTEF_INTERRUPT_STATUS 0x3084
114#define SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE 0x3085 464#define SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE 0x3085
465#define SUNI1x10GEXP_REG_XTEF_VISIBILITY 0x3086
466
467#define SUNI1x10GEXP_REG_TXOAM_OAM_CONFIG 0x30C0
468#define SUNI1x10GEXP_REG_TXOAM_MINI_RATE_CONFIG 0x30C1
469#define SUNI1x10GEXP_REG_TXOAM_MINI_GAP_FIFO_CONFIG 0x30C2
470#define SUNI1x10GEXP_REG_TXOAM_P1P2_STATIC_VALUES 0x30C3
471#define SUNI1x10GEXP_REG_TXOAM_P3P4_STATIC_VALUES 0x30C4
472#define SUNI1x10GEXP_REG_TXOAM_P5P6_STATIC_VALUES 0x30C5
115#define SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE 0x30C6 473#define SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE 0x30C6
116#define SUNI1x10GEXP_REG_TXOAM_INTERRUPT_STATUS 0x30C7 474#define SUNI1x10GEXP_REG_TXOAM_INTERRUPT_STATUS 0x30C7
475#define SUNI1x10GEXP_REG_TXOAM_INSERT_COUNT_LSB 0x30C8
476#define SUNI1x10GEXP_REG_TXOAM_INSERT_COUNT_MSB 0x30C9
477#define SUNI1x10GEXP_REG_TXOAM_OAM_MINI_COUNT_LSB 0x30CA
478#define SUNI1x10GEXP_REG_TXOAM_OAM_MINI_COUNT_MSB 0x30CB
479#define SUNI1x10GEXP_REG_TXOAM_P1P2_MINI_MASK 0x30CC
480#define SUNI1x10GEXP_REG_TXOAM_P3P4_MINI_MASK 0x30CD
481#define SUNI1x10GEXP_REG_TXOAM_P5P6_MINI_MASK 0x30CE
482#define SUNI1x10GEXP_REG_TXOAM_COSET 0x30CF
483#define SUNI1x10GEXP_REG_TXOAM_EMPTY_FIFO_INS_OP_CNT_LSB 0x30D0
484#define SUNI1x10GEXP_REG_TXOAM_EMPTY_FIFO_INS_OP_CNT_MSB 0x30D1
485#define SUNI1x10GEXP_REG_TXOAM_STATIC_VALUE_MINI_COUNT_LSB 0x30D2
486#define SUNI1x10GEXP_REG_TXOAM_STATIC_VALUE_MINI_COUNT_MSB 0x30D3
487
488
489#define SUNI1x10GEXP_REG_EFLX_GLOBAL_CONFIG 0x3200
490#define SUNI1x10GEXP_REG_EFLX_ERCU_GLOBAL_STATUS 0x3201
491#define SUNI1x10GEXP_REG_EFLX_INDIR_CHANNEL_ADDRESS 0x3202
492#define SUNI1x10GEXP_REG_EFLX_INDIR_FIFO_LOW_LIMIT 0x3203
493#define SUNI1x10GEXP_REG_EFLX_INDIR_FIFO_HIGH_LIMIT 0x3204
494#define SUNI1x10GEXP_REG_EFLX_INDIR_FULL_ALMOST_FULL_STATUS_AND_LIMIT 0x3205
495#define SUNI1x10GEXP_REG_EFLX_INDIR_EMPTY_ALMOST_EMPTY_STATUS_AND_LIMIT 0x3206
496#define SUNI1x10GEXP_REG_EFLX_INDIR_FIFO_CUT_THROUGH_THRESHOLD 0x3207
117#define SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE 0x320C 497#define SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE 0x320C
118#define SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_INDICATION 0x320D 498#define SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_INDICATION 0x320D
499#define SUNI1x10GEXP_REG_EFLX_CHANNEL_PROVISION 0x3210
500
501#define SUNI1x10GEXP_REG_PL4IDU_CONFIG 0x3280
119#define SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK 0x3282 502#define SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK 0x3282
120#define SUNI1x10GEXP_REG_PL4IDU_INTERRUPT 0x3283 503#define SUNI1x10GEXP_REG_PL4IDU_INTERRUPT 0x3283
121 504
505
506/*----------------------------------------*/
507#define SUNI1x10GEXP_REG_MAX_OFFSET 0x3480
508
122/******************************************************************************/ 509/******************************************************************************/
123/* -- End register offset definitions -- */ 510/* -- End register offset definitions -- */
124/******************************************************************************/ 511/******************************************************************************/
@@ -127,6 +514,81 @@
127/** SUNI-1x10GE-XP REGISTER BIT MASKS **/ 514/** SUNI-1x10GE-XP REGISTER BIT MASKS **/
128/******************************************************************************/ 515/******************************************************************************/
129 516
517#define SUNI1x10GEXP_BITMSK_BITS_1 0x00001
518#define SUNI1x10GEXP_BITMSK_BITS_2 0x00003
519#define SUNI1x10GEXP_BITMSK_BITS_3 0x00007
520#define SUNI1x10GEXP_BITMSK_BITS_4 0x0000f
521#define SUNI1x10GEXP_BITMSK_BITS_5 0x0001f
522#define SUNI1x10GEXP_BITMSK_BITS_6 0x0003f
523#define SUNI1x10GEXP_BITMSK_BITS_7 0x0007f
524#define SUNI1x10GEXP_BITMSK_BITS_8 0x000ff
525#define SUNI1x10GEXP_BITMSK_BITS_9 0x001ff
526#define SUNI1x10GEXP_BITMSK_BITS_10 0x003ff
527#define SUNI1x10GEXP_BITMSK_BITS_11 0x007ff
528#define SUNI1x10GEXP_BITMSK_BITS_12 0x00fff
529#define SUNI1x10GEXP_BITMSK_BITS_13 0x01fff
530#define SUNI1x10GEXP_BITMSK_BITS_14 0x03fff
531#define SUNI1x10GEXP_BITMSK_BITS_15 0x07fff
532#define SUNI1x10GEXP_BITMSK_BITS_16 0x0ffff
533
534#define mSUNI1x10GEXP_CLR_MSBITS_1(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_15)
535#define mSUNI1x10GEXP_CLR_MSBITS_2(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_14)
536#define mSUNI1x10GEXP_CLR_MSBITS_3(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_13)
537#define mSUNI1x10GEXP_CLR_MSBITS_4(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_12)
538#define mSUNI1x10GEXP_CLR_MSBITS_5(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_11)
539#define mSUNI1x10GEXP_CLR_MSBITS_6(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_10)
540#define mSUNI1x10GEXP_CLR_MSBITS_7(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_9)
541#define mSUNI1x10GEXP_CLR_MSBITS_8(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_8)
542#define mSUNI1x10GEXP_CLR_MSBITS_9(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_7)
543#define mSUNI1x10GEXP_CLR_MSBITS_10(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_6)
544#define mSUNI1x10GEXP_CLR_MSBITS_11(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_5)
545#define mSUNI1x10GEXP_CLR_MSBITS_12(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_4)
546#define mSUNI1x10GEXP_CLR_MSBITS_13(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_3)
547#define mSUNI1x10GEXP_CLR_MSBITS_14(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_2)
548#define mSUNI1x10GEXP_CLR_MSBITS_15(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_1)
549
550#define mSUNI1x10GEXP_GET_BIT(val, bitMsk) (((val)&(bitMsk)) ? 1:0)
551
552
553
554/*----------------------------------------------------------------------------
555 * Register 0x0001: S/UNI-1x10GE-XP Product Revision
556 * Bit 3-0 REVISION
557 *----------------------------------------------------------------------------*/
558#define SUNI1x10GEXP_BITMSK_REVISION 0x000F
559
560/*----------------------------------------------------------------------------
561 * Register 0x0002: S/UNI-1x10GE-XP Configuration and Reset Control
562 * Bit 2 XAUI_ARESETB
563 * Bit 1 PL4_ARESETB
564 * Bit 0 DRESETB
565 *----------------------------------------------------------------------------*/
566#define SUNI1x10GEXP_BITMSK_XAUI_ARESET 0x0004
567#define SUNI1x10GEXP_BITMSK_PL4_ARESET 0x0002
568#define SUNI1x10GEXP_BITMSK_DRESETB 0x0001
569
570/*----------------------------------------------------------------------------
571 * Register 0x0003: S/UNI-1x10GE-XP Loop Back and Miscellaneous Control
572 * Bit 11 PL4IO_OUTCLKSEL
573 * Bit 9 SYSPCSLB
574 * Bit 8 LINEPCSLB
575 * Bit 7 MSTAT_BYPASS
576 * Bit 6 RXXG_BYPASS
577 * Bit 5 TXXG_BYPASS
578 * Bit 4 SOP_PAD_EN
579 * Bit 1 LOS_INV
580 * Bit 0 OVERRIDE_LOS
581 *----------------------------------------------------------------------------*/
582#define SUNI1x10GEXP_BITMSK_PL4IO_OUTCLKSEL 0x0800
583#define SUNI1x10GEXP_BITMSK_SYSPCSLB 0x0200
584#define SUNI1x10GEXP_BITMSK_LINEPCSLB 0x0100
585#define SUNI1x10GEXP_BITMSK_MSTAT_BYPASS 0x0080
586#define SUNI1x10GEXP_BITMSK_RXXG_BYPASS 0x0040
587#define SUNI1x10GEXP_BITMSK_TXXG_BYPASS 0x0020
588#define SUNI1x10GEXP_BITMSK_SOP_PAD_EN 0x0010
589#define SUNI1x10GEXP_BITMSK_LOS_INV 0x0002
590#define SUNI1x10GEXP_BITMSK_OVERRIDE_LOS 0x0001
591
130/*---------------------------------------------------------------------------- 592/*----------------------------------------------------------------------------
131 * Register 0x0004: S/UNI-1x10GE-XP Device Status 593 * Register 0x0004: S/UNI-1x10GE-XP Device Status
132 * Bit 9 TOP_SXRA_EXPIRED 594 * Bit 9 TOP_SXRA_EXPIRED
@@ -141,7 +603,10 @@
141 * Bit 0 TOP_PL4_OUT_ROOL 603 * Bit 0 TOP_PL4_OUT_ROOL
142 *----------------------------------------------------------------------------*/ 604 *----------------------------------------------------------------------------*/
143#define SUNI1x10GEXP_BITMSK_TOP_SXRA_EXPIRED 0x0200 605#define SUNI1x10GEXP_BITMSK_TOP_SXRA_EXPIRED 0x0200
606#define SUNI1x10GEXP_BITMSK_TOP_MDIO_BUSY 0x0100
607#define SUNI1x10GEXP_BITMSK_TOP_DTRB 0x0080
144#define SUNI1x10GEXP_BITMSK_TOP_EXPIRED 0x0040 608#define SUNI1x10GEXP_BITMSK_TOP_EXPIRED 0x0040
609#define SUNI1x10GEXP_BITMSK_TOP_PAUSED 0x0020
145#define SUNI1x10GEXP_BITMSK_TOP_PL4_ID_DOOL 0x0010 610#define SUNI1x10GEXP_BITMSK_TOP_PL4_ID_DOOL 0x0010
146#define SUNI1x10GEXP_BITMSK_TOP_PL4_IS_DOOL 0x0008 611#define SUNI1x10GEXP_BITMSK_TOP_PL4_IS_DOOL 0x0008
147#define SUNI1x10GEXP_BITMSK_TOP_PL4_ID_ROOL 0x0004 612#define SUNI1x10GEXP_BITMSK_TOP_PL4_ID_ROOL 0x0004
@@ -149,12 +614,219 @@
149#define SUNI1x10GEXP_BITMSK_TOP_PL4_OUT_ROOL 0x0001 614#define SUNI1x10GEXP_BITMSK_TOP_PL4_OUT_ROOL 0x0001
150 615
151/*---------------------------------------------------------------------------- 616/*----------------------------------------------------------------------------
617 * Register 0x0005: Global Performance Update and Clock Monitors
618 * Bit 15 TIP
619 * Bit 8 XAUI_REF_CLKA
620 * Bit 7 RXLANE3CLKA
621 * Bit 6 RXLANE2CLKA
622 * Bit 5 RXLANE1CLKA
623 * Bit 4 RXLANE0CLKA
624 * Bit 3 CSUCLKA
625 * Bit 2 TDCLKA
626 * Bit 1 RSCLKA
627 * Bit 0 RDCLKA
628 *----------------------------------------------------------------------------*/
629#define SUNI1x10GEXP_BITMSK_TIP 0x8000
630#define SUNI1x10GEXP_BITMSK_XAUI_REF_CLKA 0x0100
631#define SUNI1x10GEXP_BITMSK_RXLANE3CLKA 0x0080
632#define SUNI1x10GEXP_BITMSK_RXLANE2CLKA 0x0040
633#define SUNI1x10GEXP_BITMSK_RXLANE1CLKA 0x0020
634#define SUNI1x10GEXP_BITMSK_RXLANE0CLKA 0x0010
635#define SUNI1x10GEXP_BITMSK_CSUCLKA 0x0008
636#define SUNI1x10GEXP_BITMSK_TDCLKA 0x0004
637#define SUNI1x10GEXP_BITMSK_RSCLKA 0x0002
638#define SUNI1x10GEXP_BITMSK_RDCLKA 0x0001
639
640/*----------------------------------------------------------------------------
641 * Register 0x0006: MDIO Command
642 * Bit 4 MDIO_RDINC
643 * Bit 3 MDIO_RSTAT
644 * Bit 2 MDIO_LCTLD
645 * Bit 1 MDIO_LCTLA
646 * Bit 0 MDIO_SPRE
647 *----------------------------------------------------------------------------*/
648#define SUNI1x10GEXP_BITMSK_MDIO_RDINC 0x0010
649#define SUNI1x10GEXP_BITMSK_MDIO_RSTAT 0x0008
650#define SUNI1x10GEXP_BITMSK_MDIO_LCTLD 0x0004
651#define SUNI1x10GEXP_BITMSK_MDIO_LCTLA 0x0002
652#define SUNI1x10GEXP_BITMSK_MDIO_SPRE 0x0001
653
654/*----------------------------------------------------------------------------
655 * Register 0x0007: MDIO Interrupt Enable
656 * Bit 0 MDIO_BUSY_EN
657 *----------------------------------------------------------------------------*/
658#define SUNI1x10GEXP_BITMSK_MDIO_BUSY_EN 0x0001
659
660/*----------------------------------------------------------------------------
661 * Register 0x0008: MDIO Interrupt Status
662 * Bit 0 MDIO_BUSYI
663 *----------------------------------------------------------------------------*/
664#define SUNI1x10GEXP_BITMSK_MDIO_BUSYI 0x0001
665
666/*----------------------------------------------------------------------------
667 * Register 0x0009: MMD PHY Address
668 * Bit 12-8 MDIO_DEVADR
669 * Bit 4-0 MDIO_PRTADR
670 *----------------------------------------------------------------------------*/
671#define SUNI1x10GEXP_BITMSK_MDIO_DEVADR 0x1F00
672#define SUNI1x10GEXP_BITOFF_MDIO_DEVADR 8
673#define SUNI1x10GEXP_BITMSK_MDIO_PRTADR 0x001F
674#define SUNI1x10GEXP_BITOFF_MDIO_PRTADR 0
675
676/*----------------------------------------------------------------------------
677 * Register 0x000C: OAM Interface Control
678 * Bit 6 MDO_OD_ENB
679 * Bit 5 MDI_INV
680 * Bit 4 MDI_SEL
681 * Bit 3 RXOAMEN
682 * Bit 2 RXOAMCLKEN
683 * Bit 1 TXOAMEN
684 * Bit 0 TXOAMCLKEN
685 *----------------------------------------------------------------------------*/
686#define SUNI1x10GEXP_BITMSK_MDO_OD_ENB 0x0040
687#define SUNI1x10GEXP_BITMSK_MDI_INV 0x0020
688#define SUNI1x10GEXP_BITMSK_MDI_SEL 0x0010
689#define SUNI1x10GEXP_BITMSK_RXOAMEN 0x0008
690#define SUNI1x10GEXP_BITMSK_RXOAMCLKEN 0x0004
691#define SUNI1x10GEXP_BITMSK_TXOAMEN 0x0002
692#define SUNI1x10GEXP_BITMSK_TXOAMCLKEN 0x0001
693
694/*----------------------------------------------------------------------------
695 * Register 0x000D: S/UNI-1x10GE-XP Master Interrupt Status
696 * Bit 15 TOP_PL4IO_INT
697 * Bit 14 TOP_IRAM_INT
698 * Bit 13 TOP_ERAM_INT
699 * Bit 12 TOP_XAUI_INT
700 * Bit 11 TOP_MSTAT_INT
701 * Bit 10 TOP_RXXG_INT
702 * Bit 9 TOP_TXXG_INT
703 * Bit 8 TOP_XRF_INT
704 * Bit 7 TOP_XTEF_INT
705 * Bit 6 TOP_MDIO_BUSY_INT
706 * Bit 5 TOP_RXOAM_INT
707 * Bit 4 TOP_TXOAM_INT
708 * Bit 3 TOP_IFLX_INT
709 * Bit 2 TOP_EFLX_INT
710 * Bit 1 TOP_PL4ODP_INT
711 * Bit 0 TOP_PL4IDU_INT
712 *----------------------------------------------------------------------------*/
713#define SUNI1x10GEXP_BITMSK_TOP_PL4IO_INT 0x8000
714#define SUNI1x10GEXP_BITMSK_TOP_IRAM_INT 0x4000
715#define SUNI1x10GEXP_BITMSK_TOP_ERAM_INT 0x2000
716#define SUNI1x10GEXP_BITMSK_TOP_XAUI_INT 0x1000
717#define SUNI1x10GEXP_BITMSK_TOP_MSTAT_INT 0x0800
718#define SUNI1x10GEXP_BITMSK_TOP_RXXG_INT 0x0400
719#define SUNI1x10GEXP_BITMSK_TOP_TXXG_INT 0x0200
720#define SUNI1x10GEXP_BITMSK_TOP_XRF_INT 0x0100
721#define SUNI1x10GEXP_BITMSK_TOP_XTEF_INT 0x0080
722#define SUNI1x10GEXP_BITMSK_TOP_MDIO_BUSY_INT 0x0040
723#define SUNI1x10GEXP_BITMSK_TOP_RXOAM_INT 0x0020
724#define SUNI1x10GEXP_BITMSK_TOP_TXOAM_INT 0x0010
725#define SUNI1x10GEXP_BITMSK_TOP_IFLX_INT 0x0008
726#define SUNI1x10GEXP_BITMSK_TOP_EFLX_INT 0x0004
727#define SUNI1x10GEXP_BITMSK_TOP_PL4ODP_INT 0x0002
728#define SUNI1x10GEXP_BITMSK_TOP_PL4IDU_INT 0x0001
729
730/*----------------------------------------------------------------------------
152 * Register 0x000E:PM3393 Global interrupt enable 731 * Register 0x000E:PM3393 Global interrupt enable
153 * Bit 15 TOP_INTE 732 * Bit 15 TOP_INTE
154 *----------------------------------------------------------------------------*/ 733 *----------------------------------------------------------------------------*/
155#define SUNI1x10GEXP_BITMSK_TOP_INTE 0x8000 734#define SUNI1x10GEXP_BITMSK_TOP_INTE 0x8000
156 735
157/*---------------------------------------------------------------------------- 736/*----------------------------------------------------------------------------
737 * Register 0x0010: XTEF Miscellaneous Control
738 * Bit 7 RF_VAL
739 * Bit 6 RF_OVERRIDE
740 * Bit 5 LF_VAL
741 * Bit 4 LF_OVERRIDE
742 *----------------------------------------------------------------------------*/
743#define SUNI1x10GEXP_BITMSK_RF_VAL 0x0080
744#define SUNI1x10GEXP_BITMSK_RF_OVERRIDE 0x0040
745#define SUNI1x10GEXP_BITMSK_LF_VAL 0x0020
746#define SUNI1x10GEXP_BITMSK_LF_OVERRIDE 0x0010
747#define SUNI1x10GEXP_BITMSK_LFRF_OVERRIDE_VAL 0x00F0
748
749/*----------------------------------------------------------------------------
750 * Register 0x0011: XRF Miscellaneous Control
751 * Bit 6-4 EN_IDLE_REP
752 *----------------------------------------------------------------------------*/
753#define SUNI1x10GEXP_BITMSK_EN_IDLE_REP 0x0070
754
755/*----------------------------------------------------------------------------
756 * Register 0x0100: SERDES 3125 Configuration Register 1
757 * Bit 10 RXEQB_3
758 * Bit 8 RXEQB_2
759 * Bit 6 RXEQB_1
760 * Bit 4 RXEQB_0
761 *----------------------------------------------------------------------------*/
762#define SUNI1x10GEXP_BITMSK_RXEQB 0x0FF0
763#define SUNI1x10GEXP_BITOFF_RXEQB_3 10
764#define SUNI1x10GEXP_BITOFF_RXEQB_2 8
765#define SUNI1x10GEXP_BITOFF_RXEQB_1 6
766#define SUNI1x10GEXP_BITOFF_RXEQB_0 4
767
768/*----------------------------------------------------------------------------
769 * Register 0x0101: SERDES 3125 Configuration Register 2
770 * Bit 12 YSEL
771 * Bit 7 PRE_EMPH_3
772 * Bit 6 PRE_EMPH_2
773 * Bit 5 PRE_EMPH_1
774 * Bit 4 PRE_EMPH_0
775 *----------------------------------------------------------------------------*/
776#define SUNI1x10GEXP_BITMSK_YSEL 0x1000
777#define SUNI1x10GEXP_BITMSK_PRE_EMPH 0x00F0
778#define SUNI1x10GEXP_BITMSK_PRE_EMPH_3 0x0080
779#define SUNI1x10GEXP_BITMSK_PRE_EMPH_2 0x0040
780#define SUNI1x10GEXP_BITMSK_PRE_EMPH_1 0x0020
781#define SUNI1x10GEXP_BITMSK_PRE_EMPH_0 0x0010
782
783/*----------------------------------------------------------------------------
784 * Register 0x0102: SERDES 3125 Interrupt Enable Register
785 * Bit 3 LASIE
786 * Bit 2 SPLL_RAE
787 * Bit 1 MPLL_RAE
788 * Bit 0 PLL_LOCKE
789 *----------------------------------------------------------------------------*/
790#define SUNI1x10GEXP_BITMSK_LASIE 0x0008
791#define SUNI1x10GEXP_BITMSK_SPLL_RAE 0x0004
792#define SUNI1x10GEXP_BITMSK_MPLL_RAE 0x0002
793#define SUNI1x10GEXP_BITMSK_PLL_LOCKE 0x0001
794
795/*----------------------------------------------------------------------------
796 * Register 0x0103: SERDES 3125 Interrupt Visibility Register
797 * Bit 3 LASIV
798 * Bit 2 SPLL_RAV
799 * Bit 1 MPLL_RAV
800 * Bit 0 PLL_LOCKV
801 *----------------------------------------------------------------------------*/
802#define SUNI1x10GEXP_BITMSK_LASIV 0x0008
803#define SUNI1x10GEXP_BITMSK_SPLL_RAV 0x0004
804#define SUNI1x10GEXP_BITMSK_MPLL_RAV 0x0002
805#define SUNI1x10GEXP_BITMSK_PLL_LOCKV 0x0001
806
807/*----------------------------------------------------------------------------
808 * Register 0x0104: SERDES 3125 Interrupt Status Register
809 * Bit 3 LASII
810 * Bit 2 SPLL_RAI
811 * Bit 1 MPLL_RAI
812 * Bit 0 PLL_LOCKI
813 *----------------------------------------------------------------------------*/
814#define SUNI1x10GEXP_BITMSK_LASII 0x0008
815#define SUNI1x10GEXP_BITMSK_SPLL_RAI 0x0004
816#define SUNI1x10GEXP_BITMSK_MPLL_RAI 0x0002
817#define SUNI1x10GEXP_BITMSK_PLL_LOCKI 0x0001
818
819/*----------------------------------------------------------------------------
820 * Register 0x0107: SERDES 3125 Test Configuration
821 * Bit 12 DUALTX
822 * Bit 10 HC_1
823 * Bit 9 HC_0
824 *----------------------------------------------------------------------------*/
825#define SUNI1x10GEXP_BITMSK_DUALTX 0x1000
826#define SUNI1x10GEXP_BITMSK_HC 0x0600
827#define SUNI1x10GEXP_BITOFF_HC_0 9
828
829/*----------------------------------------------------------------------------
158 * Register 0x2040: RXXG Configuration 1 830 * Register 0x2040: RXXG Configuration 1
159 * Bit 15 RXXG_RXEN 831 * Bit 15 RXXG_RXEN
160 * Bit 14 RXXG_ROCF 832 * Bit 14 RXXG_ROCF
@@ -168,11 +840,84 @@
168 * Bit 2-0 RXXG_MIFG 840 * Bit 2-0 RXXG_MIFG
169 *----------------------------------------------------------------------------*/ 841 *----------------------------------------------------------------------------*/
170#define SUNI1x10GEXP_BITMSK_RXXG_RXEN 0x8000 842#define SUNI1x10GEXP_BITMSK_RXXG_RXEN 0x8000
843#define SUNI1x10GEXP_BITMSK_RXXG_ROCF 0x4000
844#define SUNI1x10GEXP_BITMSK_RXXG_PAD_STRIP 0x2000
171#define SUNI1x10GEXP_BITMSK_RXXG_PUREP 0x0400 845#define SUNI1x10GEXP_BITMSK_RXXG_PUREP 0x0400
846#define SUNI1x10GEXP_BITMSK_RXXG_LONGP 0x0200
847#define SUNI1x10GEXP_BITMSK_RXXG_PARF 0x0100
172#define SUNI1x10GEXP_BITMSK_RXXG_FLCHK 0x0080 848#define SUNI1x10GEXP_BITMSK_RXXG_FLCHK 0x0080
849#define SUNI1x10GEXP_BITMSK_RXXG_PASS_CTRL 0x0020
173#define SUNI1x10GEXP_BITMSK_RXXG_CRC_STRIP 0x0008 850#define SUNI1x10GEXP_BITMSK_RXXG_CRC_STRIP 0x0008
174 851
175/*---------------------------------------------------------------------------- 852/*----------------------------------------------------------------------------
853 * Register 0x02041: RXXG Configuration 2
854 * Bit 7-0 RXXG_HDRSIZE
855 *----------------------------------------------------------------------------*/
856#define SUNI1x10GEXP_BITMSK_RXXG_HDRSIZE 0x00FF
857
858/*----------------------------------------------------------------------------
859 * Register 0x2042: RXXG Configuration 3
860 * Bit 15 RXXG_MIN_LERRE
861 * Bit 14 RXXG_MAX_LERRE
862 * Bit 12 RXXG_LINE_ERRE
863 * Bit 10 RXXG_RX_OVRE
864 * Bit 9 RXXG_ADR_FILTERE
865 * Bit 8 RXXG_ERR_FILTERE
866 * Bit 5 RXXG_PRMB_ERRE
867 *----------------------------------------------------------------------------*/
868#define SUNI1x10GEXP_BITMSK_RXXG_MIN_LERRE 0x8000
869#define SUNI1x10GEXP_BITMSK_RXXG_MAX_LERRE 0x4000
870#define SUNI1x10GEXP_BITMSK_RXXG_LINE_ERRE 0x1000
871#define SUNI1x10GEXP_BITMSK_RXXG_RX_OVRE 0x0400
872#define SUNI1x10GEXP_BITMSK_RXXG_ADR_FILTERE 0x0200
873#define SUNI1x10GEXP_BITMSK_RXXG_ERR_FILTERRE 0x0100
874#define SUNI1x10GEXP_BITMSK_RXXG_PRMB_ERRE 0x0020
875
876/*----------------------------------------------------------------------------
877 * Register 0x2043: RXXG Interrupt
878 * Bit 15 RXXG_MIN_LERRI
879 * Bit 14 RXXG_MAX_LERRI
880 * Bit 12 RXXG_LINE_ERRI
881 * Bit 10 RXXG_RX_OVRI
882 * Bit 9 RXXG_ADR_FILTERI
883 * Bit 8 RXXG_ERR_FILTERI
884 * Bit 5 RXXG_PRMB_ERRE
885 *----------------------------------------------------------------------------*/
886#define SUNI1x10GEXP_BITMSK_RXXG_MIN_LERRI 0x8000
887#define SUNI1x10GEXP_BITMSK_RXXG_MAX_LERRI 0x4000
888#define SUNI1x10GEXP_BITMSK_RXXG_LINE_ERRI 0x1000
889#define SUNI1x10GEXP_BITMSK_RXXG_RX_OVRI 0x0400
890#define SUNI1x10GEXP_BITMSK_RXXG_ADR_FILTERI 0x0200
891#define SUNI1x10GEXP_BITMSK_RXXG_ERR_FILTERI 0x0100
892#define SUNI1x10GEXP_BITMSK_RXXG_PRMB_ERRE 0x0020
893
894/*----------------------------------------------------------------------------
895 * Register 0x2049: RXXG Receive FIFO Threshold
896 * Bit 2-0 RXXG_CUT_THRU
897 *----------------------------------------------------------------------------*/
898#define SUNI1x10GEXP_BITMSK_RXXG_CUT_THRU 0x0007
899#define SUNI1x10GEXP_BITOFF_RXXG_CUT_THRU 0
900
901/*----------------------------------------------------------------------------
902 * Register 0x2062H - 0x2069: RXXG Exact Match VID
903 * Bit 11-0 RXXG_VID_MATCH
904 *----------------------------------------------------------------------------*/
905#define SUNI1x10GEXP_BITMSK_RXXG_VID_MATCH 0x0FFF
906#define SUNI1x10GEXP_BITOFF_RXXG_VID_MATCH 0
907
908/*----------------------------------------------------------------------------
909 * Register 0x206EH - 0x206F: RXXG Address Filter Control
910 * Bit 3 RXXG_FORWARD_ENABLE
911 * Bit 2 RXXG_VLAN_ENABLE
912 * Bit 1 RXXG_SRC_ADDR
913 * Bit 0 RXXG_MATCH_ENABLE
914 *----------------------------------------------------------------------------*/
915#define SUNI1x10GEXP_BITMSK_RXXG_FORWARD_ENABLE 0x0008
916#define SUNI1x10GEXP_BITMSK_RXXG_VLAN_ENABLE 0x0004
917#define SUNI1x10GEXP_BITMSK_RXXG_SRC_ADDR 0x0002
918#define SUNI1x10GEXP_BITMSK_RXXG_MATCH_ENABLE 0x0001
919
920/*----------------------------------------------------------------------------
176 * Register 0x2070: RXXG Address Filter Control 2 921 * Register 0x2070: RXXG Address Filter Control 2
177 * Bit 1 RXXG_PMODE 922 * Bit 1 RXXG_PMODE
178 * Bit 0 RXXG_MHASH_EN 923 * Bit 0 RXXG_MHASH_EN
@@ -181,15 +926,446 @@
181#define SUNI1x10GEXP_BITMSK_RXXG_MHASH_EN 0x0001 926#define SUNI1x10GEXP_BITMSK_RXXG_MHASH_EN 0x0001
182 927
183/*---------------------------------------------------------------------------- 928/*----------------------------------------------------------------------------
929 * Register 0x2081: XRF Control Register 2
930 * Bit 6 EN_PKT_GEN
931 * Bit 4-2 PATT
932 *----------------------------------------------------------------------------*/
933#define SUNI1x10GEXP_BITMSK_EN_PKT_GEN 0x0040
934#define SUNI1x10GEXP_BITMSK_PATT 0x001C
935#define SUNI1x10GEXP_BITOFF_PATT 2
936
937/*----------------------------------------------------------------------------
938 * Register 0x2088: XRF Interrupt Enable
939 * Bit 12-9 LANE_HICERE
940 * Bit 8-5 HS_SD_LANEE
941 * Bit 4 ALIGN_STATUS_ERRE
942 * Bit 3-0 LANE_SYNC_STAT_ERRE
943 *----------------------------------------------------------------------------*/
944#define SUNI1x10GEXP_BITMSK_LANE_HICERE 0x1E00
945#define SUNI1x10GEXP_BITOFF_LANE_HICERE 9
946#define SUNI1x10GEXP_BITMSK_HS_SD_LANEE 0x01E0
947#define SUNI1x10GEXP_BITOFF_HS_SD_LANEE 5
948#define SUNI1x10GEXP_BITMSK_ALIGN_STATUS_ERRE 0x0010
949#define SUNI1x10GEXP_BITMSK_LANE_SYNC_STAT_ERRE 0x000F
950#define SUNI1x10GEXP_BITOFF_LANE_SYNC_STAT_ERRE 0
951
952/*----------------------------------------------------------------------------
953 * Register 0x2089: XRF Interrupt Status
954 * Bit 12-9 LANE_HICERI
955 * Bit 8-5 HS_SD_LANEI
956 * Bit 4 ALIGN_STATUS_ERRI
957 * Bit 3-0 LANE_SYNC_STAT_ERRI
958 *----------------------------------------------------------------------------*/
959#define SUNI1x10GEXP_BITMSK_LANE_HICERI 0x1E00
960#define SUNI1x10GEXP_BITOFF_LANE_HICERI 9
961#define SUNI1x10GEXP_BITMSK_HS_SD_LANEI 0x01E0
962#define SUNI1x10GEXP_BITOFF_HS_SD_LANEI 5
963#define SUNI1x10GEXP_BITMSK_ALIGN_STATUS_ERRI 0x0010
964#define SUNI1x10GEXP_BITMSK_LANE_SYNC_STAT_ERRI 0x000F
965#define SUNI1x10GEXP_BITOFF_LANE_SYNC_STAT_ERRI 0
966
967/*----------------------------------------------------------------------------
968 * Register 0x208A: XRF Error Status
969 * Bit 8-5 HS_SD_LANE
970 * Bit 4 ALIGN_STATUS_ERR
971 * Bit 3-0 LANE_SYNC_STAT_ERR
972 *----------------------------------------------------------------------------*/
973#define SUNI1x10GEXP_BITMSK_HS_SD_LANE3 0x0100
974#define SUNI1x10GEXP_BITMSK_HS_SD_LANE2 0x0080
975#define SUNI1x10GEXP_BITMSK_HS_SD_LANE1 0x0040
976#define SUNI1x10GEXP_BITMSK_HS_SD_LANE0 0x0020
977#define SUNI1x10GEXP_BITMSK_ALIGN_STATUS_ERR 0x0010
978#define SUNI1x10GEXP_BITMSK_LANE3_SYNC_STAT_ERR 0x0008
979#define SUNI1x10GEXP_BITMSK_LANE2_SYNC_STAT_ERR 0x0004
980#define SUNI1x10GEXP_BITMSK_LANE1_SYNC_STAT_ERR 0x0002
981#define SUNI1x10GEXP_BITMSK_LANE0_SYNC_STAT_ERR 0x0001
982
983/*----------------------------------------------------------------------------
984 * Register 0x208B: XRF Diagnostic Interrupt Enable
985 * Bit 7-4 LANE_OVERRUNE
986 * Bit 3-0 LANE_UNDERRUNE
987 *----------------------------------------------------------------------------*/
988#define SUNI1x10GEXP_BITMSK_LANE_OVERRUNE 0x00F0
989#define SUNI1x10GEXP_BITOFF_LANE_OVERRUNE 4
990#define SUNI1x10GEXP_BITMSK_LANE_UNDERRUNE 0x000F
991#define SUNI1x10GEXP_BITOFF_LANE_UNDERRUNE 0
992
993/*----------------------------------------------------------------------------
994 * Register 0x208C: XRF Diagnostic Interrupt Status
995 * Bit 7-4 LANE_OVERRUNI
996 * Bit 3-0 LANE_UNDERRUNI
997 *----------------------------------------------------------------------------*/
998#define SUNI1x10GEXP_BITMSK_LANE_OVERRUNI 0x00F0
999#define SUNI1x10GEXP_BITOFF_LANE_OVERRUNI 4
1000#define SUNI1x10GEXP_BITMSK_LANE_UNDERRUNI 0x000F
1001#define SUNI1x10GEXP_BITOFF_LANE_UNDERRUNI 0
1002
1003/*----------------------------------------------------------------------------
1004 * Register 0x20C0: RXOAM Configuration
1005 * Bit 15 RXOAM_BUSY
1006 * Bit 14-12 RXOAM_F2_SEL
1007 * Bit 10-8 RXOAM_F1_SEL
1008 * Bit 7-6 RXOAM_FILTER_CTRL
1009 * Bit 5-0 RXOAM_PX_EN
1010 *----------------------------------------------------------------------------*/
1011#define SUNI1x10GEXP_BITMSK_RXOAM_BUSY 0x8000
1012#define SUNI1x10GEXP_BITMSK_RXOAM_F2_SEL 0x7000
1013#define SUNI1x10GEXP_BITOFF_RXOAM_F2_SEL 12
1014#define SUNI1x10GEXP_BITMSK_RXOAM_F1_SEL 0x0700
1015#define SUNI1x10GEXP_BITOFF_RXOAM_F1_SEL 8
1016#define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_CTRL 0x00C0
1017#define SUNI1x10GEXP_BITOFF_RXOAM_FILTER_CTRL 6
1018#define SUNI1x10GEXP_BITMSK_RXOAM_PX_EN 0x003F
1019#define SUNI1x10GEXP_BITOFF_RXOAM_PX_EN 0
1020
1021/*----------------------------------------------------------------------------
1022 * Register 0x20C1,0x20C2: RXOAM Filter Configuration
1023 * Bit 15-8 RXOAM_FX_MASK
1024 * Bit 7-0 RXOAM_FX_VAL
1025 *----------------------------------------------------------------------------*/
1026#define SUNI1x10GEXP_BITMSK_RXOAM_FX_MASK 0xFF00
1027#define SUNI1x10GEXP_BITOFF_RXOAM_FX_MASK 8
1028#define SUNI1x10GEXP_BITMSK_RXOAM_FX_VAL 0x00FF
1029#define SUNI1x10GEXP_BITOFF_RXOAM_FX_VAl 0
1030
1031/*----------------------------------------------------------------------------
1032 * Register 0x20C3: RXOAM Configuration Register 2
1033 * Bit 13 RXOAM_REC_BYTE_VAL
1034 * Bit 11-10 RXOAM_BYPASS_MODE
1035 * Bit 5-0 RXOAM_PX_CLEAR
1036 *----------------------------------------------------------------------------*/
1037#define SUNI1x10GEXP_BITMSK_RXOAM_REC_BYTE_VAL 0x2000
1038#define SUNI1x10GEXP_BITMSK_RXOAM_BYPASS_MODE 0x0C00
1039#define SUNI1x10GEXP_BITOFF_RXOAM_BYPASS_MODE 10
1040#define SUNI1x10GEXP_BITMSK_RXOAM_PX_CLEAR 0x003F
1041#define SUNI1x10GEXP_BITOFF_RXOAM_PX_CLEAR 0
1042
1043/*----------------------------------------------------------------------------
1044 * Register 0x20C4: RXOAM HEC Configuration
1045 * Bit 15-8 RXOAM_COSET
1046 * Bit 2 RXOAM_HEC_ERR_PKT
1047 * Bit 0 RXOAM_HEC_EN
1048 *----------------------------------------------------------------------------*/
1049#define SUNI1x10GEXP_BITMSK_RXOAM_COSET 0xFF00
1050#define SUNI1x10GEXP_BITOFF_RXOAM_COSET 8
1051#define SUNI1x10GEXP_BITMSK_RXOAM_HEC_ERR_PKT 0x0004
1052#define SUNI1x10GEXP_BITMSK_RXOAM_HEC_EN 0x0001
1053
1054/*----------------------------------------------------------------------------
1055 * Register 0x20C7: RXOAM Interrupt Enable
1056 * Bit 10 RXOAM_FILTER_THRSHE
1057 * Bit 9 RXOAM_OAM_ERRE
1058 * Bit 8 RXOAM_HECE_THRSHE
1059 * Bit 7 RXOAM_SOPE
1060 * Bit 6 RXOAM_RFE
1061 * Bit 5 RXOAM_LFE
1062 * Bit 4 RXOAM_DV_ERRE
1063 * Bit 3 RXOAM_DATA_INVALIDE
1064 * Bit 2 RXOAM_FILTER_DROPE
1065 * Bit 1 RXOAM_HECE
1066 * Bit 0 RXOAM_OFLE
1067 *----------------------------------------------------------------------------*/
1068#define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_THRSHE 0x0400
1069#define SUNI1x10GEXP_BITMSK_RXOAM_OAM_ERRE 0x0200
1070#define SUNI1x10GEXP_BITMSK_RXOAM_HECE_THRSHE 0x0100
1071#define SUNI1x10GEXP_BITMSK_RXOAM_SOPE 0x0080
1072#define SUNI1x10GEXP_BITMSK_RXOAM_RFE 0x0040
1073#define SUNI1x10GEXP_BITMSK_RXOAM_LFE 0x0020
1074#define SUNI1x10GEXP_BITMSK_RXOAM_DV_ERRE 0x0010
1075#define SUNI1x10GEXP_BITMSK_RXOAM_DATA_INVALIDE 0x0008
1076#define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_DROPE 0x0004
1077#define SUNI1x10GEXP_BITMSK_RXOAM_HECE 0x0002
1078#define SUNI1x10GEXP_BITMSK_RXOAM_OFLE 0x0001
1079
1080/*----------------------------------------------------------------------------
1081 * Register 0x20C8: RXOAM Interrupt Status
1082 * Bit 10 RXOAM_FILTER_THRSHI
1083 * Bit 9 RXOAM_OAM_ERRI
1084 * Bit 8 RXOAM_HECE_THRSHI
1085 * Bit 7 RXOAM_SOPI
1086 * Bit 6 RXOAM_RFI
1087 * Bit 5 RXOAM_LFI
1088 * Bit 4 RXOAM_DV_ERRI
1089 * Bit 3 RXOAM_DATA_INVALIDI
1090 * Bit 2 RXOAM_FILTER_DROPI
1091 * Bit 1 RXOAM_HECI
1092 * Bit 0 RXOAM_OFLI
1093 *----------------------------------------------------------------------------*/
1094#define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_THRSHI 0x0400
1095#define SUNI1x10GEXP_BITMSK_RXOAM_OAM_ERRI 0x0200
1096#define SUNI1x10GEXP_BITMSK_RXOAM_HECE_THRSHI 0x0100
1097#define SUNI1x10GEXP_BITMSK_RXOAM_SOPI 0x0080
1098#define SUNI1x10GEXP_BITMSK_RXOAM_RFI 0x0040
1099#define SUNI1x10GEXP_BITMSK_RXOAM_LFI 0x0020
1100#define SUNI1x10GEXP_BITMSK_RXOAM_DV_ERRI 0x0010
1101#define SUNI1x10GEXP_BITMSK_RXOAM_DATA_INVALIDI 0x0008
1102#define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_DROPI 0x0004
1103#define SUNI1x10GEXP_BITMSK_RXOAM_HECI 0x0002
1104#define SUNI1x10GEXP_BITMSK_RXOAM_OFLI 0x0001
1105
1106/*----------------------------------------------------------------------------
1107 * Register 0x20C9: RXOAM Status
1108 * Bit 10 RXOAM_FILTER_THRSHV
1109 * Bit 8 RXOAM_HECE_THRSHV
1110 * Bit 6 RXOAM_RFV
1111 * Bit 5 RXOAM_LFV
1112 *----------------------------------------------------------------------------*/
1113#define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_THRSHV 0x0400
1114#define SUNI1x10GEXP_BITMSK_RXOAM_HECE_THRSHV 0x0100
1115#define SUNI1x10GEXP_BITMSK_RXOAM_RFV 0x0040
1116#define SUNI1x10GEXP_BITMSK_RXOAM_LFV 0x0020
1117
1118/*----------------------------------------------------------------------------
184 * Register 0x2100: MSTAT Control 1119 * Register 0x2100: MSTAT Control
185 * Bit 2 MSTAT_WRITE 1120 * Bit 2 MSTAT_WRITE
186 * Bit 1 MSTAT_CLEAR 1121 * Bit 1 MSTAT_CLEAR
187 * Bit 0 MSTAT_SNAP 1122 * Bit 0 MSTAT_SNAP
188 *----------------------------------------------------------------------------*/ 1123 *----------------------------------------------------------------------------*/
1124#define SUNI1x10GEXP_BITMSK_MSTAT_WRITE 0x0004
189#define SUNI1x10GEXP_BITMSK_MSTAT_CLEAR 0x0002 1125#define SUNI1x10GEXP_BITMSK_MSTAT_CLEAR 0x0002
190#define SUNI1x10GEXP_BITMSK_MSTAT_SNAP 0x0001 1126#define SUNI1x10GEXP_BITMSK_MSTAT_SNAP 0x0001
191 1127
192/*---------------------------------------------------------------------------- 1128/*----------------------------------------------------------------------------
1129 * Register 0x2109: MSTAT Counter Write Address
1130 * Bit 5-0 MSTAT_WRITE_ADDRESS
1131 *----------------------------------------------------------------------------*/
1132#define SUNI1x10GEXP_BITMSK_MSTAT_WRITE_ADDRESS 0x003F
1133#define SUNI1x10GEXP_BITOFF_MSTAT_WRITE_ADDRESS 0
1134
1135/*----------------------------------------------------------------------------
1136 * Register 0x2200: IFLX Global Configuration Register
1137 * Bit 15 IFLX_IRCU_ENABLE
1138 * Bit 14 IFLX_IDSWT_ENABLE
1139 * Bit 13-0 IFLX_IFD_CNT
1140 *----------------------------------------------------------------------------*/
1141#define SUNI1x10GEXP_BITMSK_IFLX_IRCU_ENABLE 0x8000
1142#define SUNI1x10GEXP_BITMSK_IFLX_IDSWT_ENABLE 0x4000
1143#define SUNI1x10GEXP_BITMSK_IFLX_IFD_CNT 0x3FFF
1144#define SUNI1x10GEXP_BITOFF_IFLX_IFD_CNT 0
1145
1146/*----------------------------------------------------------------------------
1147 * Register 0x2209: IFLX FIFO Overflow Enable
1148 * Bit 0 IFLX_OVFE
1149 *----------------------------------------------------------------------------*/
1150#define SUNI1x10GEXP_BITMSK_IFLX_OVFE 0x0001
1151
1152/*----------------------------------------------------------------------------
1153 * Register 0x220A: IFLX FIFO Overflow Interrupt
1154 * Bit 0 IFLX_OVFI
1155 *----------------------------------------------------------------------------*/
1156#define SUNI1x10GEXP_BITMSK_IFLX_OVFI 0x0001
1157
1158/*----------------------------------------------------------------------------
1159 * Register 0x220D: IFLX Indirect Channel Address
1160 * Bit 15 IFLX_BUSY
1161 * Bit 14 IFLX_RWB
1162 *----------------------------------------------------------------------------*/
1163#define SUNI1x10GEXP_BITMSK_IFLX_BUSY 0x8000
1164#define SUNI1x10GEXP_BITMSK_IFLX_RWB 0x4000
1165
1166/*----------------------------------------------------------------------------
1167 * Register 0x220E: IFLX Indirect Logical FIFO Low Limit & Provision
1168 * Bit 9-0 IFLX_LOLIM
1169 *----------------------------------------------------------------------------*/
1170#define SUNI1x10GEXP_BITMSK_IFLX_LOLIM 0x03FF
1171#define SUNI1x10GEXP_BITOFF_IFLX_LOLIM 0
1172
1173/*----------------------------------------------------------------------------
1174 * Register 0x220F: IFLX Indirect Logical FIFO High Limit
1175 * Bit 9-0 IFLX_HILIM
1176 *----------------------------------------------------------------------------*/
1177#define SUNI1x10GEXP_BITMSK_IFLX_HILIM 0x03FF
1178#define SUNI1x10GEXP_BITOFF_IFLX_HILIM 0
1179
1180/*----------------------------------------------------------------------------
1181 * Register 0x2210: IFLX Indirect Full/Almost Full Status & Limit
1182 * Bit 15 IFLX_FULL
1183 * Bit 14 IFLX_AFULL
1184 * Bit 13-0 IFLX_AFTH
1185 *----------------------------------------------------------------------------*/
1186#define SUNI1x10GEXP_BITMSK_IFLX_FULL 0x8000
1187#define SUNI1x10GEXP_BITMSK_IFLX_AFULL 0x4000
1188#define SUNI1x10GEXP_BITMSK_IFLX_AFTH 0x3FFF
1189#define SUNI1x10GEXP_BITOFF_IFLX_AFTH 0
1190
1191/*----------------------------------------------------------------------------
1192 * Register 0x2211: IFLX Indirect Empty/Almost Empty Status & Limit
1193 * Bit 15 IFLX_EMPTY
1194 * Bit 14 IFLX_AEMPTY
1195 * Bit 13-0 IFLX_AETH
1196 *----------------------------------------------------------------------------*/
1197#define SUNI1x10GEXP_BITMSK_IFLX_EMPTY 0x8000
1198#define SUNI1x10GEXP_BITMSK_IFLX_AEMPTY 0x4000
1199#define SUNI1x10GEXP_BITMSK_IFLX_AETH 0x3FFF
1200#define SUNI1x10GEXP_BITOFF_IFLX_AETH 0
1201
1202/*----------------------------------------------------------------------------
1203 * Register 0x2240: PL4MOS Configuration Register
1204 * Bit 3 PL4MOS_RE_INIT
1205 * Bit 2 PL4MOS_EN
1206 * Bit 1 PL4MOS_NO_STATUS
1207 *----------------------------------------------------------------------------*/
1208#define SUNI1x10GEXP_BITMSK_PL4MOS_RE_INIT 0x0008
1209#define SUNI1x10GEXP_BITMSK_PL4MOS_EN 0x0004
1210#define SUNI1x10GEXP_BITMSK_PL4MOS_NO_STATUS 0x0002
1211
1212/*----------------------------------------------------------------------------
1213 * Register 0x2243: PL4MOS MaxBurst1 Register
1214 * Bit 11-0 PL4MOS_MAX_BURST1
1215 *----------------------------------------------------------------------------*/
1216#define SUNI1x10GEXP_BITMSK_PL4MOS_MAX_BURST1 0x0FFF
1217#define SUNI1x10GEXP_BITOFF_PL4MOS_MAX_BURST1 0
1218
1219/*----------------------------------------------------------------------------
1220 * Register 0x2244: PL4MOS MaxBurst2 Register
1221 * Bit 11-0 PL4MOS_MAX_BURST2
1222 *----------------------------------------------------------------------------*/
1223#define SUNI1x10GEXP_BITMSK_PL4MOS_MAX_BURST2 0x0FFF
1224#define SUNI1x10GEXP_BITOFF_PL4MOS_MAX_BURST2 0
1225
1226/*----------------------------------------------------------------------------
1227 * Register 0x2245: PL4MOS Transfer Size Register
1228 * Bit 7-0 PL4MOS_MAX_TRANSFER
1229 *----------------------------------------------------------------------------*/
1230#define SUNI1x10GEXP_BITMSK_PL4MOS_MAX_TRANSFER 0x00FF
1231#define SUNI1x10GEXP_BITOFF_PL4MOS_MAX_TRANSFER 0
1232
1233/*----------------------------------------------------------------------------
1234 * Register 0x2280: PL4ODP Configuration
1235 * Bit 15-12 PL4ODP_REPEAT_T
1236 * Bit 8 PL4ODP_SOP_RULE
1237 * Bit 1 PL4ODP_EN_PORTS
1238 * Bit 0 PL4ODP_EN_DFWD
1239 *----------------------------------------------------------------------------*/
1240#define SUNI1x10GEXP_BITMSK_PL4ODP_REPEAT_T 0xF000
1241#define SUNI1x10GEXP_BITOFF_PL4ODP_REPEAT_T 12
1242#define SUNI1x10GEXP_BITMSK_PL4ODP_SOP_RULE 0x0100
1243#define SUNI1x10GEXP_BITMSK_PL4ODP_EN_PORTS 0x0002
1244#define SUNI1x10GEXP_BITMSK_PL4ODP_EN_DFWD 0x0001
1245
1246/*----------------------------------------------------------------------------
1247 * Register 0x2282: PL4ODP Interrupt Mask
1248 * Bit 0 PL4ODP_OUT_DISE
1249 *----------------------------------------------------------------------------*/
1250#define SUNI1x10GEXP_BITMSK_PL4ODP_OUT_DISE 0x0001
1251
1252
1253
1254#define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_EOPEOBE 0x0080
1255#define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_ERREOPE 0x0040
1256#define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_MEOPE 0x0008
1257#define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_MSOPE 0x0004
1258#define SUNI1x10GEXP_BITMSK_PL4ODP_ES_OVRE 0x0002
1259
1260
1261/*----------------------------------------------------------------------------
1262 * Register 0x2283: PL4ODP Interrupt
1263 * Bit 0 PL4ODP_OUT_DISI
1264 *----------------------------------------------------------------------------*/
1265#define SUNI1x10GEXP_BITMSK_PL4ODP_OUT_DISI 0x0001
1266
1267
1268
1269#define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_EOPEOBI 0x0080
1270#define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_ERREOPI 0x0040
1271#define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_MEOPI 0x0008
1272#define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_MSOPI 0x0004
1273#define SUNI1x10GEXP_BITMSK_PL4ODP_ES_OVRI 0x0002
1274
1275/*----------------------------------------------------------------------------
1276 * Register 0x2300: PL4IO Lock Detect Status
1277 * Bit 15 PL4IO_OUT_ROOLV
1278 * Bit 12 PL4IO_IS_ROOLV
1279 * Bit 11 PL4IO_DIP2_ERRV
1280 * Bit 8 PL4IO_ID_ROOLV
1281 * Bit 4 PL4IO_IS_DOOLV
1282 * Bit 0 PL4IO_ID_DOOLV
1283 *----------------------------------------------------------------------------*/
1284#define SUNI1x10GEXP_BITMSK_PL4IO_OUT_ROOLV 0x8000
1285#define SUNI1x10GEXP_BITMSK_PL4IO_IS_ROOLV 0x1000
1286#define SUNI1x10GEXP_BITMSK_PL4IO_DIP2_ERRV 0x0800
1287#define SUNI1x10GEXP_BITMSK_PL4IO_ID_ROOLV 0x0100
1288#define SUNI1x10GEXP_BITMSK_PL4IO_IS_DOOLV 0x0010
1289#define SUNI1x10GEXP_BITMSK_PL4IO_ID_DOOLV 0x0001
1290
1291/*----------------------------------------------------------------------------
1292 * Register 0x2301: PL4IO Lock Detect Change
1293 * Bit 15 PL4IO_OUT_ROOLI
1294 * Bit 12 PL4IO_IS_ROOLI
1295 * Bit 11 PL4IO_DIP2_ERRI
1296 * Bit 8 PL4IO_ID_ROOLI
1297 * Bit 4 PL4IO_IS_DOOLI
1298 * Bit 0 PL4IO_ID_DOOLI
1299 *----------------------------------------------------------------------------*/
1300#define SUNI1x10GEXP_BITMSK_PL4IO_OUT_ROOLI 0x8000
1301#define SUNI1x10GEXP_BITMSK_PL4IO_IS_ROOLI 0x1000
1302#define SUNI1x10GEXP_BITMSK_PL4IO_DIP2_ERRI 0x0800
1303#define SUNI1x10GEXP_BITMSK_PL4IO_ID_ROOLI 0x0100
1304#define SUNI1x10GEXP_BITMSK_PL4IO_IS_DOOLI 0x0010
1305#define SUNI1x10GEXP_BITMSK_PL4IO_ID_DOOLI 0x0001
1306
1307/*----------------------------------------------------------------------------
1308 * Register 0x2302: PL4IO Lock Detect Mask
1309 * Bit 15 PL4IO_OUT_ROOLE
1310 * Bit 12 PL4IO_IS_ROOLE
1311 * Bit 11 PL4IO_DIP2_ERRE
1312 * Bit 8 PL4IO_ID_ROOLE
1313 * Bit 4 PL4IO_IS_DOOLE
1314 * Bit 0 PL4IO_ID_DOOLE
1315 *----------------------------------------------------------------------------*/
1316#define SUNI1x10GEXP_BITMSK_PL4IO_OUT_ROOLE 0x8000
1317#define SUNI1x10GEXP_BITMSK_PL4IO_IS_ROOLE 0x1000
1318#define SUNI1x10GEXP_BITMSK_PL4IO_DIP2_ERRE 0x0800
1319#define SUNI1x10GEXP_BITMSK_PL4IO_ID_ROOLE 0x0100
1320#define SUNI1x10GEXP_BITMSK_PL4IO_IS_DOOLE 0x0010
1321#define SUNI1x10GEXP_BITMSK_PL4IO_ID_DOOLE 0x0001
1322
1323/*----------------------------------------------------------------------------
1324 * Register 0x2303: PL4IO Lock Detect Limits
1325 * Bit 15-8 PL4IO_REF_LIMIT
1326 * Bit 7-0 PL4IO_TRAN_LIMIT
1327 *----------------------------------------------------------------------------*/
1328#define SUNI1x10GEXP_BITMSK_PL4IO_REF_LIMIT 0xFF00
1329#define SUNI1x10GEXP_BITOFF_PL4IO_REF_LIMIT 8
1330#define SUNI1x10GEXP_BITMSK_PL4IO_TRAN_LIMIT 0x00FF
1331#define SUNI1x10GEXP_BITOFF_PL4IO_TRAN_LIMIT 0
1332
1333/*----------------------------------------------------------------------------
1334 * Register 0x2304: PL4IO Calendar Repetitions
1335 * Bit 15-8 PL4IO_IN_MUL
1336 * Bit 7-0 PL4IO_OUT_MUL
1337 *----------------------------------------------------------------------------*/
1338#define SUNI1x10GEXP_BITMSK_PL4IO_IN_MUL 0xFF00
1339#define SUNI1x10GEXP_BITOFF_PL4IO_IN_MUL 8
1340#define SUNI1x10GEXP_BITMSK_PL4IO_OUT_MUL 0x00FF
1341#define SUNI1x10GEXP_BITOFF_PL4IO_OUT_MUL 0
1342
1343/*----------------------------------------------------------------------------
1344 * Register 0x2305: PL4IO Configuration
1345 * Bit 15 PL4IO_DIP2_ERR_CHK
1346 * Bit 11 PL4IO_ODAT_DIS
1347 * Bit 10 PL4IO_TRAIN_DIS
1348 * Bit 9 PL4IO_OSTAT_DIS
1349 * Bit 8 PL4IO_ISTAT_DIS
1350 * Bit 7 PL4IO_NO_ISTAT
1351 * Bit 6 PL4IO_STAT_OUTSEL
1352 * Bit 5 PL4IO_INSEL
1353 * Bit 4 PL4IO_DLSEL
1354 * Bit 1-0 PL4IO_OUTSEL
1355 *----------------------------------------------------------------------------*/
1356#define SUNI1x10GEXP_BITMSK_PL4IO_DIP2_ERR_CHK 0x8000
1357#define SUNI1x10GEXP_BITMSK_PL4IO_ODAT_DIS 0x0800
1358#define SUNI1x10GEXP_BITMSK_PL4IO_TRAIN_DIS 0x0400
1359#define SUNI1x10GEXP_BITMSK_PL4IO_OSTAT_DIS 0x0200
1360#define SUNI1x10GEXP_BITMSK_PL4IO_ISTAT_DIS 0x0100
1361#define SUNI1x10GEXP_BITMSK_PL4IO_NO_ISTAT 0x0080
1362#define SUNI1x10GEXP_BITMSK_PL4IO_STAT_OUTSEL 0x0040
1363#define SUNI1x10GEXP_BITMSK_PL4IO_INSEL 0x0020
1364#define SUNI1x10GEXP_BITMSK_PL4IO_DLSEL 0x0010
1365#define SUNI1x10GEXP_BITMSK_PL4IO_OUTSEL 0x0003
1366#define SUNI1x10GEXP_BITOFF_PL4IO_OUTSEL 0
1367
1368/*----------------------------------------------------------------------------
193 * Register 0x3040: TXXG Configuration Register 1 1369 * Register 0x3040: TXXG Configuration Register 1
194 * Bit 15 TXXG_TXEN0 1370 * Bit 15 TXXG_TXEN0
195 * Bit 13 TXXG_HOSTPAUSE 1371 * Bit 13 TXXG_HOSTPAUSE
@@ -202,12 +1378,266 @@
202 * Bit 0 TXXG_SPRE 1378 * Bit 0 TXXG_SPRE
203 *----------------------------------------------------------------------------*/ 1379 *----------------------------------------------------------------------------*/
204#define SUNI1x10GEXP_BITMSK_TXXG_TXEN0 0x8000 1380#define SUNI1x10GEXP_BITMSK_TXXG_TXEN0 0x8000
1381#define SUNI1x10GEXP_BITMSK_TXXG_HOSTPAUSE 0x2000
1382#define SUNI1x10GEXP_BITMSK_TXXG_IPGT 0x1F80
205#define SUNI1x10GEXP_BITOFF_TXXG_IPGT 7 1383#define SUNI1x10GEXP_BITOFF_TXXG_IPGT 7
206#define SUNI1x10GEXP_BITMSK_TXXG_32BIT_ALIGN 0x0020 1384#define SUNI1x10GEXP_BITMSK_TXXG_32BIT_ALIGN 0x0020
207#define SUNI1x10GEXP_BITMSK_TXXG_CRCEN 0x0010 1385#define SUNI1x10GEXP_BITMSK_TXXG_CRCEN 0x0010
208#define SUNI1x10GEXP_BITMSK_TXXG_FCTX 0x0008 1386#define SUNI1x10GEXP_BITMSK_TXXG_FCTX 0x0008
209#define SUNI1x10GEXP_BITMSK_TXXG_FCRX 0x0004 1387#define SUNI1x10GEXP_BITMSK_TXXG_FCRX 0x0004
210#define SUNI1x10GEXP_BITMSK_TXXG_PADEN 0x0002 1388#define SUNI1x10GEXP_BITMSK_TXXG_PADEN 0x0002
1389#define SUNI1x10GEXP_BITMSK_TXXG_SPRE 0x0001
1390
1391/*----------------------------------------------------------------------------
1392 * Register 0x3041: TXXG Configuration Register 2
1393 * Bit 7-0 TXXG_HDRSIZE
1394 *----------------------------------------------------------------------------*/
1395#define SUNI1x10GEXP_BITMSK_TXXG_HDRSIZE 0x00FF
1396
1397/*----------------------------------------------------------------------------
1398 * Register 0x3042: TXXG Configuration Register 3
1399 * Bit 15 TXXG_FIFO_ERRE
1400 * Bit 14 TXXG_FIFO_UDRE
1401 * Bit 13 TXXG_MAX_LERRE
1402 * Bit 12 TXXG_MIN_LERRE
1403 * Bit 11 TXXG_XFERE
1404 *----------------------------------------------------------------------------*/
1405#define SUNI1x10GEXP_BITMSK_TXXG_FIFO_ERRE 0x8000
1406#define SUNI1x10GEXP_BITMSK_TXXG_FIFO_UDRE 0x4000
1407#define SUNI1x10GEXP_BITMSK_TXXG_MAX_LERRE 0x2000
1408#define SUNI1x10GEXP_BITMSK_TXXG_MIN_LERRE 0x1000
1409#define SUNI1x10GEXP_BITMSK_TXXG_XFERE 0x0800
1410
1411/*----------------------------------------------------------------------------
1412 * Register 0x3043: TXXG Interrupt
1413 * Bit 15 TXXG_FIFO_ERRI
1414 * Bit 14 TXXG_FIFO_UDRI
1415 * Bit 13 TXXG_MAX_LERRI
1416 * Bit 12 TXXG_MIN_LERRI
1417 * Bit 11 TXXG_XFERI
1418 *----------------------------------------------------------------------------*/
1419#define SUNI1x10GEXP_BITMSK_TXXG_FIFO_ERRI 0x8000
1420#define SUNI1x10GEXP_BITMSK_TXXG_FIFO_UDRI 0x4000
1421#define SUNI1x10GEXP_BITMSK_TXXG_MAX_LERRI 0x2000
1422#define SUNI1x10GEXP_BITMSK_TXXG_MIN_LERRI 0x1000
1423#define SUNI1x10GEXP_BITMSK_TXXG_XFERI 0x0800
1424
1425/*----------------------------------------------------------------------------
1426 * Register 0x3044: TXXG Status Register
1427 * Bit 1 TXXG_TXACTIVE
1428 * Bit 0 TXXG_PAUSED
1429 *----------------------------------------------------------------------------*/
1430#define SUNI1x10GEXP_BITMSK_TXXG_TXACTIVE 0x0002
1431#define SUNI1x10GEXP_BITMSK_TXXG_PAUSED 0x0001
1432
1433/*----------------------------------------------------------------------------
1434 * Register 0x3046: TXXG TX_MINFR - Transmit Min Frame Size Register
1435 * Bit 7-0 TXXG_TX_MINFR
1436 *----------------------------------------------------------------------------*/
1437#define SUNI1x10GEXP_BITMSK_TXXG_TX_MINFR 0x00FF
1438#define SUNI1x10GEXP_BITOFF_TXXG_TX_MINFR 0
1439
1440/*----------------------------------------------------------------------------
1441 * Register 0x3052: TXXG Pause Quantum Value Configuration Register
1442 * Bit 7-0 TXXG_FC_PAUSE_QNTM
1443 *----------------------------------------------------------------------------*/
1444#define SUNI1x10GEXP_BITMSK_TXXG_FC_PAUSE_QNTM 0x00FF
1445#define SUNI1x10GEXP_BITOFF_TXXG_FC_PAUSE_QNTM 0
1446
1447/*----------------------------------------------------------------------------
1448 * Register 0x3080: XTEF Control
1449 * Bit 3-0 XTEF_FORCE_PARITY_ERR
1450 *----------------------------------------------------------------------------*/
1451#define SUNI1x10GEXP_BITMSK_XTEF_FORCE_PARITY_ERR 0x000F
1452#define SUNI1x10GEXP_BITOFF_XTEF_FORCE_PARITY_ERR 0
1453
1454/*----------------------------------------------------------------------------
1455 * Register 0x3084: XTEF Interrupt Event Register
1456 * Bit 0 XTEF_LOST_SYNCI
1457 *----------------------------------------------------------------------------*/
1458#define SUNI1x10GEXP_BITMSK_XTEF_LOST_SYNCI 0x0001
1459
1460/*----------------------------------------------------------------------------
1461 * Register 0x3085: XTEF Interrupt Enable Register
1462 * Bit 0 XTEF_LOST_SYNCE
1463 *----------------------------------------------------------------------------*/
1464#define SUNI1x10GEXP_BITMSK_XTEF_LOST_SYNCE 0x0001
1465
1466/*----------------------------------------------------------------------------
1467 * Register 0x3086: XTEF Visibility Register
1468 * Bit 0 XTEF_LOST_SYNCV
1469 *----------------------------------------------------------------------------*/
1470#define SUNI1x10GEXP_BITMSK_XTEF_LOST_SYNCV 0x0001
1471
1472/*----------------------------------------------------------------------------
1473 * Register 0x30C0: TXOAM OAM Configuration
1474 * Bit 15 TXOAM_HEC_EN
1475 * Bit 14 TXOAM_EMPTYCODE_EN
1476 * Bit 13 TXOAM_FORCE_IDLE
1477 * Bit 12 TXOAM_IGNORE_IDLE
1478 * Bit 11-6 TXOAM_PX_OVERWRITE
1479 * Bit 5-0 TXOAM_PX_SEL
1480 *----------------------------------------------------------------------------*/
1481#define SUNI1x10GEXP_BITMSK_TXOAM_HEC_EN 0x8000
1482#define SUNI1x10GEXP_BITMSK_TXOAM_EMPTYCODE_EN 0x4000
1483#define SUNI1x10GEXP_BITMSK_TXOAM_FORCE_IDLE 0x2000
1484#define SUNI1x10GEXP_BITMSK_TXOAM_IGNORE_IDLE 0x1000
1485#define SUNI1x10GEXP_BITMSK_TXOAM_PX_OVERWRITE 0x0FC0
1486#define SUNI1x10GEXP_BITOFF_TXOAM_PX_OVERWRITE 6
1487#define SUNI1x10GEXP_BITMSK_TXOAM_PX_SEL 0x003F
1488#define SUNI1x10GEXP_BITOFF_TXOAM_PX_SEL 0
1489
1490/*----------------------------------------------------------------------------
1491 * Register 0x30C1: TXOAM Mini-Packet Rate Configuration
1492 * Bit 15 TXOAM_MINIDIS
1493 * Bit 14 TXOAM_BUSY
1494 * Bit 13 TXOAM_TRANS_EN
1495 * Bit 10-0 TXOAM_MINIRATE
1496 *----------------------------------------------------------------------------*/
1497#define SUNI1x10GEXP_BITMSK_TXOAM_MINIDIS 0x8000
1498#define SUNI1x10GEXP_BITMSK_TXOAM_BUSY 0x4000
1499#define SUNI1x10GEXP_BITMSK_TXOAM_TRANS_EN 0x2000
1500#define SUNI1x10GEXP_BITMSK_TXOAM_MINIRATE 0x07FF
1501
1502/*----------------------------------------------------------------------------
1503 * Register 0x30C2: TXOAM Mini-Packet Gap and FIFO Configuration
1504 * Bit 13-10 TXOAM_FTHRESH
1505 * Bit 9-6 TXOAM_MINIPOST
1506 * Bit 5-0 TXOAM_MINIPRE
1507 *----------------------------------------------------------------------------*/
1508#define SUNI1x10GEXP_BITMSK_TXOAM_FTHRESH 0x3C00
1509#define SUNI1x10GEXP_BITOFF_TXOAM_FTHRESH 10
1510#define SUNI1x10GEXP_BITMSK_TXOAM_MINIPOST 0x03C0
1511#define SUNI1x10GEXP_BITOFF_TXOAM_MINIPOST 6
1512#define SUNI1x10GEXP_BITMSK_TXOAM_MINIPRE 0x003F
1513
1514/*----------------------------------------------------------------------------
1515 * Register 0x30C6: TXOAM Interrupt Enable
1516 * Bit 2 TXOAM_SOP_ERRE
1517 * Bit 1 TXOAM_OFLE
1518 * Bit 0 TXOAM_ERRE
1519 *----------------------------------------------------------------------------*/
1520#define SUNI1x10GEXP_BITMSK_TXOAM_SOP_ERRE 0x0004
1521#define SUNI1x10GEXP_BITMSK_TXOAM_OFLE 0x0002
1522#define SUNI1x10GEXP_BITMSK_TXOAM_ERRE 0x0001
1523
1524/*----------------------------------------------------------------------------
1525 * Register 0x30C7: TXOAM Interrupt Status
1526 * Bit 2 TXOAM_SOP_ERRI
1527 * Bit 1 TXOAM_OFLI
1528 * Bit 0 TXOAM_ERRI
1529 *----------------------------------------------------------------------------*/
1530#define SUNI1x10GEXP_BITMSK_TXOAM_SOP_ERRI 0x0004
1531#define SUNI1x10GEXP_BITMSK_TXOAM_OFLI 0x0002
1532#define SUNI1x10GEXP_BITMSK_TXOAM_ERRI 0x0001
1533
1534/*----------------------------------------------------------------------------
1535 * Register 0x30CF: TXOAM Coset
1536 * Bit 7-0 TXOAM_COSET
1537 *----------------------------------------------------------------------------*/
1538#define SUNI1x10GEXP_BITMSK_TXOAM_COSET 0x00FF
1539
1540/*----------------------------------------------------------------------------
1541 * Register 0x3200: EFLX Global Configuration
1542 * Bit 15 EFLX_ERCU_EN
1543 * Bit 7 EFLX_EN_EDSWT
1544 *----------------------------------------------------------------------------*/
1545#define SUNI1x10GEXP_BITMSK_EFLX_ERCU_EN 0x8000
1546#define SUNI1x10GEXP_BITMSK_EFLX_EN_EDSWT 0x0080
1547
1548/*----------------------------------------------------------------------------
1549 * Register 0x3201: EFLX ERCU Global Status
1550 * Bit 13 EFLX_OVF_ERR
1551 *----------------------------------------------------------------------------*/
1552#define SUNI1x10GEXP_BITMSK_EFLX_OVF_ERR 0x2000
1553
1554/*----------------------------------------------------------------------------
1555 * Register 0x3202: EFLX Indirect Channel Address
1556 * Bit 15 EFLX_BUSY
1557 * Bit 14 EFLX_RDWRB
1558 *----------------------------------------------------------------------------*/
1559#define SUNI1x10GEXP_BITMSK_EFLX_BUSY 0x8000
1560#define SUNI1x10GEXP_BITMSK_EFLX_RDWRB 0x4000
1561
1562/*----------------------------------------------------------------------------
1563 * Register 0x3203: EFLX Indirect Logical FIFO Low Limit
1564 *----------------------------------------------------------------------------*/
1565#define SUNI1x10GEXP_BITMSK_EFLX_LOLIM 0x03FF
1566#define SUNI1x10GEXP_BITOFF_EFLX_LOLIM 0
1567
1568/*----------------------------------------------------------------------------
1569 * Register 0x3204: EFLX Indirect Logical FIFO High Limit
1570 *----------------------------------------------------------------------------*/
1571#define SUNI1x10GEXP_BITMSK_EFLX_HILIM 0x03FF
1572#define SUNI1x10GEXP_BITOFF_EFLX_HILIM 0
1573
1574/*----------------------------------------------------------------------------
1575 * Register 0x3205: EFLX Indirect Full/Almost-Full Status and Limit
1576 * Bit 15 EFLX_FULL
1577 * Bit 14 EFLX_AFULL
1578 * Bit 13-0 EFLX_AFTH
1579 *----------------------------------------------------------------------------*/
1580#define SUNI1x10GEXP_BITMSK_EFLX_FULL 0x8000
1581#define SUNI1x10GEXP_BITMSK_EFLX_AFULL 0x4000
1582#define SUNI1x10GEXP_BITMSK_EFLX_AFTH 0x3FFF
1583#define SUNI1x10GEXP_BITOFF_EFLX_AFTH 0
1584
1585/*----------------------------------------------------------------------------
1586 * Register 0x3206: EFLX Indirect Empty/Almost-Empty Status and Limit
1587 * Bit 15 EFLX_EMPTY
1588 * Bit 14 EFLX_AEMPTY
1589 * Bit 13-0 EFLX_AETH
1590 *----------------------------------------------------------------------------*/
1591#define SUNI1x10GEXP_BITMSK_EFLX_EMPTY 0x8000
1592#define SUNI1x10GEXP_BITMSK_EFLX_AEMPTY 0x4000
1593#define SUNI1x10GEXP_BITMSK_EFLX_AETH 0x3FFF
1594#define SUNI1x10GEXP_BITOFF_EFLX_AETH 0
1595
1596/*----------------------------------------------------------------------------
1597 * Register 0x3207: EFLX Indirect FIFO Cut-Through Threshold
1598 *----------------------------------------------------------------------------*/
1599#define SUNI1x10GEXP_BITMSK_EFLX_CUT_THRU 0x3FFF
1600#define SUNI1x10GEXP_BITOFF_EFLX_CUT_THRU 0
1601
1602/*----------------------------------------------------------------------------
1603 * Register 0x320C: EFLX FIFO Overflow Error Enable
1604 * Bit 0 EFLX_OVFE
1605 *----------------------------------------------------------------------------*/
1606#define SUNI1x10GEXP_BITMSK_EFLX_OVFE 0x0001
1607
1608/*----------------------------------------------------------------------------
1609 * Register 0x320D: EFLX FIFO Overflow Error Indication
1610 * Bit 0 EFLX_OVFI
1611 *----------------------------------------------------------------------------*/
1612#define SUNI1x10GEXP_BITMSK_EFLX_OVFI 0x0001
1613
1614/*----------------------------------------------------------------------------
1615 * Register 0x3210: EFLX Channel Provision
1616 * Bit 0 EFLX_PROV
1617 *----------------------------------------------------------------------------*/
1618#define SUNI1x10GEXP_BITMSK_EFLX_PROV 0x0001
1619
1620/*----------------------------------------------------------------------------
1621 * Register 0x3280: PL4IDU Configuration
1622 * Bit 2 PL4IDU_SYNCH_ON_TRAIN
1623 * Bit 1 PL4IDU_EN_PORTS
1624 * Bit 0 PL4IDU_EN_DFWD
1625 *----------------------------------------------------------------------------*/
1626#define SUNI1x10GEXP_BITMSK_PL4IDU_SYNCH_ON_TRAIN 0x0004
1627#define SUNI1x10GEXP_BITMSK_PL4IDU_EN_PORTS 0x0002
1628#define SUNI1x10GEXP_BITMSK_PL4IDU_EN_DFWD 0x0001
1629
1630/*----------------------------------------------------------------------------
1631 * Register 0x3282: PL4IDU Interrupt Mask
1632 * Bit 1 PL4IDU_DIP4E
1633 *----------------------------------------------------------------------------*/
1634#define SUNI1x10GEXP_BITMSK_PL4IDU_DIP4E 0x0002
1635
1636/*----------------------------------------------------------------------------
1637 * Register 0x3283: PL4IDU Interrupt
1638 * Bit 1 PL4IDU_DIP4I
1639 *----------------------------------------------------------------------------*/
1640#define SUNI1x10GEXP_BITMSK_PL4IDU_DIP4I 0x0002
211 1641
212#endif /* _CXGB_SUNI1x10GEXP_REGS_H_ */ 1642#endif /* _CXGB_SUNI1x10GEXP_REGS_H_ */
213 1643
diff --git a/drivers/net/chelsio/tp.c b/drivers/net/chelsio/tp.c
new file mode 100644
index 000000000000..04a7073e9d15
--- /dev/null
+++ b/drivers/net/chelsio/tp.c
@@ -0,0 +1,145 @@
1/* $Date: 2006/02/07 04:21:54 $ $RCSfile: tp.c,v $ $Revision: 1.73 $ */
2#include "common.h"
3#include "regs.h"
4#include "tp.h"
5
6struct petp {
7 adapter_t *adapter;
8};
9
10/* Pause deadlock avoidance parameters */
11#define DROP_MSEC 16
12#define DROP_PKTS_CNT 1
13
14static void tp_init(adapter_t * ap, const struct tp_params *p,
15 unsigned int tp_clk)
16{
17 if (t1_is_asic(ap)) {
18 u32 val;
19
20 val = F_TP_IN_CSPI_CPL | F_TP_IN_CSPI_CHECK_IP_CSUM |
21 F_TP_IN_CSPI_CHECK_TCP_CSUM | F_TP_IN_ESPI_ETHERNET;
22 if (!p->pm_size)
23 val |= F_OFFLOAD_DISABLE;
24 else
25 val |= F_TP_IN_ESPI_CHECK_IP_CSUM |
26 F_TP_IN_ESPI_CHECK_TCP_CSUM;
27 writel(val, ap->regs + A_TP_IN_CONFIG);
28 writel(F_TP_OUT_CSPI_CPL |
29 F_TP_OUT_ESPI_ETHERNET |
30 F_TP_OUT_ESPI_GENERATE_IP_CSUM |
31 F_TP_OUT_ESPI_GENERATE_TCP_CSUM,
32 ap->regs + A_TP_OUT_CONFIG);
33 writel(V_IP_TTL(64) |
34 F_PATH_MTU /* IP DF bit */ |
35 V_5TUPLE_LOOKUP(p->use_5tuple_mode) |
36 V_SYN_COOKIE_PARAMETER(29),
37 ap->regs + A_TP_GLOBAL_CONFIG);
38 /*
39 * Enable pause frame deadlock prevention.
40 */
41 if (is_T2(ap) && ap->params.nports > 1) {
42 u32 drop_ticks = DROP_MSEC * (tp_clk / 1000);
43
44 writel(F_ENABLE_TX_DROP | F_ENABLE_TX_ERROR |
45 V_DROP_TICKS_CNT(drop_ticks) |
46 V_NUM_PKTS_DROPPED(DROP_PKTS_CNT),
47 ap->regs + A_TP_TX_DROP_CONFIG);
48 }
49
50 }
51}
52
53void t1_tp_destroy(struct petp *tp)
54{
55 kfree(tp);
56}
57
58struct petp *__devinit t1_tp_create(adapter_t * adapter, struct tp_params *p)
59{
60 struct petp *tp = kzalloc(sizeof(*tp), GFP_KERNEL);
61 if (!tp)
62 return NULL;
63
64 tp->adapter = adapter;
65
66 return tp;
67}
68
69void t1_tp_intr_enable(struct petp *tp)
70{
71 u32 tp_intr = readl(tp->adapter->regs + A_PL_ENABLE);
72
73 {
74 /* We don't use any TP interrupts */
75 writel(0, tp->adapter->regs + A_TP_INT_ENABLE);
76 writel(tp_intr | F_PL_INTR_TP,
77 tp->adapter->regs + A_PL_ENABLE);
78 }
79}
80
81void t1_tp_intr_disable(struct petp *tp)
82{
83 u32 tp_intr = readl(tp->adapter->regs + A_PL_ENABLE);
84
85 {
86 writel(0, tp->adapter->regs + A_TP_INT_ENABLE);
87 writel(tp_intr & ~F_PL_INTR_TP,
88 tp->adapter->regs + A_PL_ENABLE);
89 }
90}
91
92void t1_tp_intr_clear(struct petp *tp)
93{
94 writel(0xffffffff, tp->adapter->regs + A_TP_INT_CAUSE);
95 writel(F_PL_INTR_TP, tp->adapter->regs + A_PL_CAUSE);
96}
97
98int t1_tp_intr_handler(struct petp *tp)
99{
100 u32 cause;
101
102
103 cause = readl(tp->adapter->regs + A_TP_INT_CAUSE);
104 writel(cause, tp->adapter->regs + A_TP_INT_CAUSE);
105 return 0;
106}
107
108static void set_csum_offload(struct petp *tp, u32 csum_bit, int enable)
109{
110 u32 val = readl(tp->adapter->regs + A_TP_GLOBAL_CONFIG);
111
112 if (enable)
113 val |= csum_bit;
114 else
115 val &= ~csum_bit;
116 writel(val, tp->adapter->regs + A_TP_GLOBAL_CONFIG);
117}
118
119void t1_tp_set_ip_checksum_offload(struct petp *tp, int enable)
120{
121 set_csum_offload(tp, F_IP_CSUM, enable);
122}
123
124void t1_tp_set_udp_checksum_offload(struct petp *tp, int enable)
125{
126 set_csum_offload(tp, F_UDP_CSUM, enable);
127}
128
129void t1_tp_set_tcp_checksum_offload(struct petp *tp, int enable)
130{
131 set_csum_offload(tp, F_TCP_CSUM, enable);
132}
133
134/*
135 * Initialize TP state. tp_params contains initial settings for some TP
136 * parameters, particularly the one-time PM and CM settings.
137 */
138int t1_tp_reset(struct petp *tp, struct tp_params *p, unsigned int tp_clk)
139{
140 adapter_t *adapter = tp->adapter;
141
142 tp_init(adapter, p, tp_clk);
143 writel(F_TP_RESET, adapter->regs + A_TP_RESET);
144 return 0;
145}
diff --git a/drivers/net/chelsio/tp.h b/drivers/net/chelsio/tp.h
new file mode 100644
index 000000000000..32fc71e58913
--- /dev/null
+++ b/drivers/net/chelsio/tp.h
@@ -0,0 +1,73 @@
1/* $Date: 2005/03/07 23:59:05 $ $RCSfile: tp.h,v $ $Revision: 1.20 $ */
2#ifndef CHELSIO_TP_H
3#define CHELSIO_TP_H
4
5#include "common.h"
6
7#define TP_MAX_RX_COALESCING_SIZE 16224U
8
9struct tp_mib_statistics {
10
11 /* IP */
12 u32 ipInReceive_hi;
13 u32 ipInReceive_lo;
14 u32 ipInHdrErrors_hi;
15 u32 ipInHdrErrors_lo;
16 u32 ipInAddrErrors_hi;
17 u32 ipInAddrErrors_lo;
18 u32 ipInUnknownProtos_hi;
19 u32 ipInUnknownProtos_lo;
20 u32 ipInDiscards_hi;
21 u32 ipInDiscards_lo;
22 u32 ipInDelivers_hi;
23 u32 ipInDelivers_lo;
24 u32 ipOutRequests_hi;
25 u32 ipOutRequests_lo;
26 u32 ipOutDiscards_hi;
27 u32 ipOutDiscards_lo;
28 u32 ipOutNoRoutes_hi;
29 u32 ipOutNoRoutes_lo;
30 u32 ipReasmTimeout;
31 u32 ipReasmReqds;
32 u32 ipReasmOKs;
33 u32 ipReasmFails;
34
35 u32 reserved[8];
36
37 /* TCP */
38 u32 tcpActiveOpens;
39 u32 tcpPassiveOpens;
40 u32 tcpAttemptFails;
41 u32 tcpEstabResets;
42 u32 tcpOutRsts;
43 u32 tcpCurrEstab;
44 u32 tcpInSegs_hi;
45 u32 tcpInSegs_lo;
46 u32 tcpOutSegs_hi;
47 u32 tcpOutSegs_lo;
48 u32 tcpRetransSeg_hi;
49 u32 tcpRetransSeg_lo;
50 u32 tcpInErrs_hi;
51 u32 tcpInErrs_lo;
52 u32 tcpRtoMin;
53 u32 tcpRtoMax;
54};
55
56struct petp;
57struct tp_params;
58
59struct petp *t1_tp_create(adapter_t *adapter, struct tp_params *p);
60void t1_tp_destroy(struct petp *tp);
61
62void t1_tp_intr_disable(struct petp *tp);
63void t1_tp_intr_enable(struct petp *tp);
64void t1_tp_intr_clear(struct petp *tp);
65int t1_tp_intr_handler(struct petp *tp);
66
67void t1_tp_get_mib_statistics(adapter_t *adap, struct tp_mib_statistics *tps);
68void t1_tp_set_udp_checksum_offload(struct petp *tp, int enable);
69void t1_tp_set_tcp_checksum_offload(struct petp *tp, int enable);
70void t1_tp_set_ip_checksum_offload(struct petp *tp, int enable);
71int t1_tp_set_coalescing_size(struct petp *tp, unsigned int size);
72int t1_tp_reset(struct petp *tp, struct tp_params *p, unsigned int tp_clk);
73#endif
diff --git a/drivers/net/chelsio/vsc7326_reg.h b/drivers/net/chelsio/vsc7326_reg.h
new file mode 100644
index 000000000000..491bcf75c4fb
--- /dev/null
+++ b/drivers/net/chelsio/vsc7326_reg.h
@@ -0,0 +1,286 @@
1/* $Date: 2006/04/28 19:20:17 $ $RCSfile: vsc7326_reg.h,v $ $Revision: 1.5 $ */
2#ifndef _VSC7321_REG_H_
3#define _VSC7321_REG_H_
4
5/* Register definitions for Vitesse VSC7321 (Meigs II) MAC
6 *
7 * Straight off the data sheet, VMDS-10038 Rev 2.0 and
8 * PD0011-01-14-Meigs-II 2002-12-12
9 */
10
11/* Just 'cause it's in here doesn't mean it's used. */
12
13#define CRA(blk,sub,adr) ((((blk) & 0x7) << 13) | (((sub) & 0xf) << 9) | (((adr) & 0xff) << 1))
14
15/* System and CPU comm's registers */
16#define REG_CHIP_ID CRA(0x7,0xf,0x00) /* Chip ID */
17#define REG_BLADE_ID CRA(0x7,0xf,0x01) /* Blade ID */
18#define REG_SW_RESET CRA(0x7,0xf,0x02) /* Global Soft Reset */
19#define REG_MEM_BIST CRA(0x7,0xf,0x04) /* mem */
20#define REG_IFACE_MODE CRA(0x7,0xf,0x07) /* Interface mode */
21#define REG_MSCH CRA(0x7,0x2,0x06) /* CRC error count */
22#define REG_CRC_CNT CRA(0x7,0x2,0x0a) /* CRC error count */
23#define REG_CRC_CFG CRA(0x7,0x2,0x0b) /* CRC config */
24#define REG_SI_TRANSFER_SEL CRA(0x7,0xf,0x18) /* SI Transfer Select */
25#define REG_PLL_CLK_SPEED CRA(0x7,0xf,0x19) /* Clock Speed Selection */
26#define REG_SYS_CLK_SELECT CRA(0x7,0xf,0x1c) /* System Clock Select */
27#define REG_GPIO_CTRL CRA(0x7,0xf,0x1d) /* GPIO Control */
28#define REG_GPIO_OUT CRA(0x7,0xf,0x1e) /* GPIO Out */
29#define REG_GPIO_IN CRA(0x7,0xf,0x1f) /* GPIO In */
30#define REG_CPU_TRANSFER_SEL CRA(0x7,0xf,0x20) /* CPU Transfer Select */
31#define REG_LOCAL_DATA CRA(0x7,0xf,0xfe) /* Local CPU Data Register */
32#define REG_LOCAL_STATUS CRA(0x7,0xf,0xff) /* Local CPU Status Register */
33
34/* Aggregator registers */
35#define REG_AGGR_SETUP CRA(0x7,0x1,0x00) /* Aggregator Setup */
36#define REG_PMAP_TABLE CRA(0x7,0x1,0x01) /* Port map table */
37#define REG_MPLS_BIT0 CRA(0x7,0x1,0x08) /* MPLS bit0 position */
38#define REG_MPLS_BIT1 CRA(0x7,0x1,0x09) /* MPLS bit1 position */
39#define REG_MPLS_BIT2 CRA(0x7,0x1,0x0a) /* MPLS bit2 position */
40#define REG_MPLS_BIT3 CRA(0x7,0x1,0x0b) /* MPLS bit3 position */
41#define REG_MPLS_BITMASK CRA(0x7,0x1,0x0c) /* MPLS bit mask */
42#define REG_PRE_BIT0POS CRA(0x7,0x1,0x10) /* Preamble bit0 position */
43#define REG_PRE_BIT1POS CRA(0x7,0x1,0x11) /* Preamble bit1 position */
44#define REG_PRE_BIT2POS CRA(0x7,0x1,0x12) /* Preamble bit2 position */
45#define REG_PRE_BIT3POS CRA(0x7,0x1,0x13) /* Preamble bit3 position */
46#define REG_PRE_ERR_CNT CRA(0x7,0x1,0x14) /* Preamble parity error count */
47
48/* BIST registers */
49/*#define REG_RAM_BIST_CMD CRA(0x7,0x2,0x00)*/ /* RAM BIST Command Register */
50/*#define REG_RAM_BIST_RESULT CRA(0x7,0x2,0x01)*/ /* RAM BIST Read Status/Result */
51#define REG_RAM_BIST_CMD CRA(0x7,0x1,0x00) /* RAM BIST Command Register */
52#define REG_RAM_BIST_RESULT CRA(0x7,0x1,0x01) /* RAM BIST Read Status/Result */
53#define BIST_PORT_SELECT 0x00 /* BIST port select */
54#define BIST_COMMAND 0x01 /* BIST enable/disable */
55#define BIST_STATUS 0x02 /* BIST operation status */
56#define BIST_ERR_CNT_LSB 0x03 /* BIST error count lo 8b */
57#define BIST_ERR_CNT_MSB 0x04 /* BIST error count hi 8b */
58#define BIST_ERR_SEL_LSB 0x05 /* BIST error select lo 8b */
59#define BIST_ERR_SEL_MSB 0x06 /* BIST error select hi 8b */
60#define BIST_ERROR_STATE 0x07 /* BIST engine internal state */
61#define BIST_ERR_ADR0 0x08 /* BIST error address lo 8b */
62#define BIST_ERR_ADR1 0x09 /* BIST error address lomid 8b */
63#define BIST_ERR_ADR2 0x0a /* BIST error address himid 8b */
64#define BIST_ERR_ADR3 0x0b /* BIST error address hi 8b */
65
66/* FIFO registers
67 * ie = 0 for ingress, 1 for egress
68 * fn = FIFO number, 0-9
69 */
70#define REG_TEST(ie,fn) CRA(0x2,ie&1,0x00+fn) /* Mode & Test Register */
71#define REG_TOP_BOTTOM(ie,fn) CRA(0x2,ie&1,0x10+fn) /* FIFO Buffer Top & Bottom */
72#define REG_TAIL(ie,fn) CRA(0x2,ie&1,0x20+fn) /* FIFO Write Pointer */
73#define REG_HEAD(ie,fn) CRA(0x2,ie&1,0x30+fn) /* FIFO Read Pointer */
74#define REG_HIGH_LOW_WM(ie,fn) CRA(0x2,ie&1,0x40+fn) /* Flow Control Water Marks */
75#define REG_CT_THRHLD(ie,fn) CRA(0x2,ie&1,0x50+fn) /* Cut Through Threshold */
76#define REG_FIFO_DROP_CNT(ie,fn) CRA(0x2,ie&1,0x60+fn) /* Drop & CRC Error Counter */
77#define REG_DEBUG_BUF_CNT(ie,fn) CRA(0x2,ie&1,0x70+fn) /* Input Side Debug Counter */
78#define REG_BUCKI(fn) CRA(0x2,2,0x20+fn) /* Input Side Debug Counter */
79#define REG_BUCKE(fn) CRA(0x2,3,0x20+fn) /* Input Side Debug Counter */
80
81/* Traffic shaper buckets
82 * ie = 0 for ingress, 1 for egress
83 * bn = bucket number 0-10 (yes, 11 buckets)
84 */
85/* OK, this one's kinda ugly. Some hardware designers are perverse. */
86#define REG_TRAFFIC_SHAPER_BUCKET(ie,bn) CRA(0x2,ie&1,0x0a + (bn>7) | ((bn&7)<<4))
87#define REG_TRAFFIC_SHAPER_CONTROL(ie) CRA(0x2,ie&1,0x3b)
88
89#define REG_SRAM_ADR(ie) CRA(0x2,ie&1,0x0e) /* FIFO SRAM address */
90#define REG_SRAM_WR_STRB(ie) CRA(0x2,ie&1,0x1e) /* FIFO SRAM write strobe */
91#define REG_SRAM_RD_STRB(ie) CRA(0x2,ie&1,0x2e) /* FIFO SRAM read strobe */
92#define REG_SRAM_DATA_0(ie) CRA(0x2,ie&1,0x3e) /* FIFO SRAM data lo 8b */
93#define REG_SRAM_DATA_1(ie) CRA(0x2,ie&1,0x4e) /* FIFO SRAM data lomid 8b */
94#define REG_SRAM_DATA_2(ie) CRA(0x2,ie&1,0x5e) /* FIFO SRAM data himid 8b */
95#define REG_SRAM_DATA_3(ie) CRA(0x2,ie&1,0x6e) /* FIFO SRAM data hi 8b */
96#define REG_SRAM_DATA_BLK_TYPE(ie) CRA(0x2,ie&1,0x7e) /* FIFO SRAM tag */
97/* REG_ING_CONTROL equals REG_CONTROL with ie = 0, likewise REG_EGR_CONTROL is ie = 1 */
98#define REG_CONTROL(ie) CRA(0x2,ie&1,0x0f) /* FIFO control */
99#define REG_ING_CONTROL CRA(0x2,0x0,0x0f) /* Ingress control (alias) */
100#define REG_EGR_CONTROL CRA(0x2,0x1,0x0f) /* Egress control (alias) */
101#define REG_AGE_TIMER(ie) CRA(0x2,ie&1,0x1f) /* Aging timer */
102#define REG_AGE_INC(ie) CRA(0x2,ie&1,0x2f) /* Aging increment */
103#define DEBUG_OUT(ie) CRA(0x2,ie&1,0x3f) /* Output debug counter control */
104#define DEBUG_CNT(ie) CRA(0x2,ie&1,0x4f) /* Output debug counter */
105
106/* SPI4 interface */
107#define REG_SPI4_MISC CRA(0x5,0x0,0x00) /* Misc Register */
108#define REG_SPI4_STATUS CRA(0x5,0x0,0x01) /* CML Status */
109#define REG_SPI4_ING_SETUP0 CRA(0x5,0x0,0x02) /* Ingress Status Channel Setup */
110#define REG_SPI4_ING_SETUP1 CRA(0x5,0x0,0x03) /* Ingress Data Training Setup */
111#define REG_SPI4_ING_SETUP2 CRA(0x5,0x0,0x04) /* Ingress Data Burst Size Setup */
112#define REG_SPI4_EGR_SETUP0 CRA(0x5,0x0,0x05) /* Egress Status Channel Setup */
113#define REG_SPI4_DBG_CNT(n) CRA(0x5,0x0,0x10+n) /* Debug counters 0-9 */
114#define REG_SPI4_DBG_SETUP CRA(0x5,0x0,0x1A) /* Debug counters setup */
115#define REG_SPI4_TEST CRA(0x5,0x0,0x20) /* Test Setup Register */
116#define REG_TPGEN_UP0 CRA(0x5,0x0,0x21) /* Test Pattern generator user pattern 0 */
117#define REG_TPGEN_UP1 CRA(0x5,0x0,0x22) /* Test Pattern generator user pattern 1 */
118#define REG_TPCHK_UP0 CRA(0x5,0x0,0x23) /* Test Pattern checker user pattern 0 */
119#define REG_TPCHK_UP1 CRA(0x5,0x0,0x24) /* Test Pattern checker user pattern 1 */
120#define REG_TPSAM_P0 CRA(0x5,0x0,0x25) /* Sampled pattern 0 */
121#define REG_TPSAM_P1 CRA(0x5,0x0,0x26) /* Sampled pattern 1 */
122#define REG_TPERR_CNT CRA(0x5,0x0,0x27) /* Pattern checker error counter */
123#define REG_SPI4_STICKY CRA(0x5,0x0,0x30) /* Sticky bits register */
124#define REG_SPI4_DBG_INH CRA(0x5,0x0,0x31) /* Core egress & ingress inhibit */
125#define REG_SPI4_DBG_STATUS CRA(0x5,0x0,0x32) /* Sampled ingress status */
126#define REG_SPI4_DBG_GRANT CRA(0x5,0x0,0x33) /* Ingress cranted credit value */
127
128#define REG_SPI4_DESKEW CRA(0x5,0x0,0x43) /* Ingress cranted credit value */
129
130/* 10GbE MAC Block Registers */
131/* Note that those registers that are exactly the same for 10GbE as for
132 * tri-speed are only defined with the version that needs a port number.
133 * Pass 0xa in those cases.
134 *
135 * Also note that despite the presence of a MAC address register, this part
136 * does no ingress MAC address filtering. That register is used only for
137 * pause frame detection and generation.
138 */
139/* 10GbE specific, and different from tri-speed */
140#define REG_MISC_10G CRA(0x1,0xa,0x00) /* Misc 10GbE setup */
141#define REG_PAUSE_10G CRA(0x1,0xa,0x01) /* Pause register */
142#define REG_NORMALIZER_10G CRA(0x1,0xa,0x05) /* 10G normalizer */
143#define REG_STICKY_RX CRA(0x1,0xa,0x06) /* RX debug register */
144#define REG_DENORM_10G CRA(0x1,0xa,0x07) /* Denormalizer */
145#define REG_STICKY_TX CRA(0x1,0xa,0x08) /* TX sticky bits */
146#define REG_MAX_RXHIGH CRA(0x1,0xa,0x0a) /* XGMII lane 0-3 debug */
147#define REG_MAX_RXLOW CRA(0x1,0xa,0x0b) /* XGMII lane 4-7 debug */
148#define REG_MAC_TX_STICKY CRA(0x1,0xa,0x0c) /* MAC Tx state sticky debug */
149#define REG_MAC_TX_RUNNING CRA(0x1,0xa,0x0d) /* MAC Tx state running debug */
150#define REG_TX_ABORT_AGE CRA(0x1,0xa,0x14) /* Aged Tx frames discarded */
151#define REG_TX_ABORT_SHORT CRA(0x1,0xa,0x15) /* Short Tx frames discarded */
152#define REG_TX_ABORT_TAXI CRA(0x1,0xa,0x16) /* Taxi error frames discarded */
153#define REG_TX_ABORT_UNDERRUN CRA(0x1,0xa,0x17) /* Tx Underrun abort counter */
154#define REG_TX_DENORM_DISCARD CRA(0x1,0xa,0x18) /* Tx denormalizer discards */
155#define REG_XAUI_STAT_A CRA(0x1,0xa,0x20) /* XAUI status A */
156#define REG_XAUI_STAT_B CRA(0x1,0xa,0x21) /* XAUI status B */
157#define REG_XAUI_STAT_C CRA(0x1,0xa,0x22) /* XAUI status C */
158#define REG_XAUI_CONF_A CRA(0x1,0xa,0x23) /* XAUI configuration A */
159#define REG_XAUI_CONF_B CRA(0x1,0xa,0x24) /* XAUI configuration B */
160#define REG_XAUI_CODE_GRP_CNT CRA(0x1,0xa,0x25) /* XAUI code group error count */
161#define REG_XAUI_CONF_TEST_A CRA(0x1,0xa,0x26) /* XAUI test register A */
162#define REG_PDERRCNT CRA(0x1,0xa,0x27) /* XAUI test register B */
163
164/* pn = port number 0-9 for tri-speed, 10 for 10GbE */
165/* Both tri-speed and 10GbE */
166#define REG_MAX_LEN(pn) CRA(0x1,pn,0x02) /* Max length */
167#define REG_MAC_HIGH_ADDR(pn) CRA(0x1,pn,0x03) /* Upper 24 bits of MAC addr */
168#define REG_MAC_LOW_ADDR(pn) CRA(0x1,pn,0x04) /* Lower 24 bits of MAC addr */
169
170/* tri-speed only
171 * pn = port number, 0-9
172 */
173#define REG_MODE_CFG(pn) CRA(0x1,pn,0x00) /* Mode configuration */
174#define REG_PAUSE_CFG(pn) CRA(0x1,pn,0x01) /* Pause configuration */
175#define REG_NORMALIZER(pn) CRA(0x1,pn,0x05) /* Normalizer */
176#define REG_TBI_STATUS(pn) CRA(0x1,pn,0x06) /* TBI status */
177#define REG_PCS_STATUS_DBG(pn) CRA(0x1,pn,0x07) /* PCS status debug */
178#define REG_PCS_CTRL(pn) CRA(0x1,pn,0x08) /* PCS control */
179#define REG_TBI_CONFIG(pn) CRA(0x1,pn,0x09) /* TBI configuration */
180#define REG_STICK_BIT(pn) CRA(0x1,pn,0x0a) /* Sticky bits */
181#define REG_DEV_SETUP(pn) CRA(0x1,pn,0x0b) /* MAC clock/reset setup */
182#define REG_DROP_CNT(pn) CRA(0x1,pn,0x0c) /* Drop counter */
183#define REG_PORT_POS(pn) CRA(0x1,pn,0x0d) /* Preamble port position */
184#define REG_PORT_FAIL(pn) CRA(0x1,pn,0x0e) /* Preamble port position */
185#define REG_SERDES_CONF(pn) CRA(0x1,pn,0x0f) /* SerDes configuration */
186#define REG_SERDES_TEST(pn) CRA(0x1,pn,0x10) /* SerDes test */
187#define REG_SERDES_STAT(pn) CRA(0x1,pn,0x11) /* SerDes status */
188#define REG_SERDES_COM_CNT(pn) CRA(0x1,pn,0x12) /* SerDes comma counter */
189#define REG_DENORM(pn) CRA(0x1,pn,0x15) /* Frame denormalization */
190#define REG_DBG(pn) CRA(0x1,pn,0x16) /* Device 1G debug */
191#define REG_TX_IFG(pn) CRA(0x1,pn,0x18) /* Tx IFG config */
192#define REG_HDX(pn) CRA(0x1,pn,0x19) /* Half-duplex config */
193
194/* Statistics */
195/* pn = port number, 0-a, a = 10GbE */
196#define REG_RX_IN_BYTES(pn) CRA(0x4,pn,0x00) /* # Rx in octets */
197#define REG_RX_SYMBOL_CARRIER(pn) CRA(0x4,pn,0x01) /* Frames w/ symbol errors */
198#define REG_RX_PAUSE(pn) CRA(0x4,pn,0x02) /* # pause frames received */
199#define REG_RX_UNSUP_OPCODE(pn) CRA(0x4,pn,0x03) /* # control frames with unsupported opcode */
200#define REG_RX_OK_BYTES(pn) CRA(0x4,pn,0x04) /* # octets in good frames */
201#define REG_RX_BAD_BYTES(pn) CRA(0x4,pn,0x05) /* # octets in bad frames */
202#define REG_RX_UNICAST(pn) CRA(0x4,pn,0x06) /* # good unicast frames */
203#define REG_RX_MULTICAST(pn) CRA(0x4,pn,0x07) /* # good multicast frames */
204#define REG_RX_BROADCAST(pn) CRA(0x4,pn,0x08) /* # good broadcast frames */
205#define REG_CRC(pn) CRA(0x4,pn,0x09) /* # frames w/ bad CRC only */
206#define REG_RX_ALIGNMENT(pn) CRA(0x4,pn,0x0a) /* # frames w/ alignment err */
207#define REG_RX_UNDERSIZE(pn) CRA(0x4,pn,0x0b) /* # frames undersize */
208#define REG_RX_FRAGMENTS(pn) CRA(0x4,pn,0x0c) /* # frames undersize w/ crc err */
209#define REG_RX_IN_RANGE_LENGTH_ERROR(pn) CRA(0x4,pn,0x0d) /* # frames with length error */
210#define REG_RX_OUT_OF_RANGE_ERROR(pn) CRA(0x4,pn,0x0e) /* # frames with illegal length field */
211#define REG_RX_OVERSIZE(pn) CRA(0x4,pn,0x0f) /* # frames oversize */
212#define REG_RX_JABBERS(pn) CRA(0x4,pn,0x10) /* # frames oversize w/ crc err */
213#define REG_RX_SIZE_64(pn) CRA(0x4,pn,0x11) /* # frames 64 octets long */
214#define REG_RX_SIZE_65_TO_127(pn) CRA(0x4,pn,0x12) /* # frames 65-127 octets */
215#define REG_RX_SIZE_128_TO_255(pn) CRA(0x4,pn,0x13) /* # frames 128-255 */
216#define REG_RX_SIZE_256_TO_511(pn) CRA(0x4,pn,0x14) /* # frames 256-511 */
217#define REG_RX_SIZE_512_TO_1023(pn) CRA(0x4,pn,0x15) /* # frames 512-1023 */
218#define REG_RX_SIZE_1024_TO_1518(pn) CRA(0x4,pn,0x16) /* # frames 1024-1518 */
219#define REG_RX_SIZE_1519_TO_MAX(pn) CRA(0x4,pn,0x17) /* # frames 1519-max */
220
221#define REG_TX_OUT_BYTES(pn) CRA(0x4,pn,0x18) /* # octets tx */
222#define REG_TX_PAUSE(pn) CRA(0x4,pn,0x19) /* # pause frames sent */
223#define REG_TX_OK_BYTES(pn) CRA(0x4,pn,0x1a) /* # octets tx OK */
224#define REG_TX_UNICAST(pn) CRA(0x4,pn,0x1b) /* # frames unicast */
225#define REG_TX_MULTICAST(pn) CRA(0x4,pn,0x1c) /* # frames multicast */
226#define REG_TX_BROADCAST(pn) CRA(0x4,pn,0x1d) /* # frames broadcast */
227#define REG_TX_MULTIPLE_COLL(pn) CRA(0x4,pn,0x1e) /* # frames tx after multiple collisions */
228#define REG_TX_LATE_COLL(pn) CRA(0x4,pn,0x1f) /* # late collisions detected */
229#define REG_TX_XCOLL(pn) CRA(0x4,pn,0x20) /* # frames lost, excessive collisions */
230#define REG_TX_DEFER(pn) CRA(0x4,pn,0x21) /* # frames deferred on first tx attempt */
231#define REG_TX_XDEFER(pn) CRA(0x4,pn,0x22) /* # frames excessively deferred */
232#define REG_TX_CSENSE(pn) CRA(0x4,pn,0x23) /* carrier sense errors at frame end */
233#define REG_TX_SIZE_64(pn) CRA(0x4,pn,0x24) /* # frames 64 octets long */
234#define REG_TX_SIZE_65_TO_127(pn) CRA(0x4,pn,0x25) /* # frames 65-127 octets */
235#define REG_TX_SIZE_128_TO_255(pn) CRA(0x4,pn,0x26) /* # frames 128-255 */
236#define REG_TX_SIZE_256_TO_511(pn) CRA(0x4,pn,0x27) /* # frames 256-511 */
237#define REG_TX_SIZE_512_TO_1023(pn) CRA(0x4,pn,0x28) /* # frames 512-1023 */
238#define REG_TX_SIZE_1024_TO_1518(pn) CRA(0x4,pn,0x29) /* # frames 1024-1518 */
239#define REG_TX_SIZE_1519_TO_MAX(pn) CRA(0x4,pn,0x2a) /* # frames 1519-max */
240#define REG_TX_SINGLE_COLL(pn) CRA(0x4,pn,0x2b) /* # frames tx after single collision */
241#define REG_TX_BACKOFF2(pn) CRA(0x4,pn,0x2c) /* # frames tx ok after 2 backoffs/collisions */
242#define REG_TX_BACKOFF3(pn) CRA(0x4,pn,0x2d) /* after 3 backoffs/collisions */
243#define REG_TX_BACKOFF4(pn) CRA(0x4,pn,0x2e) /* after 4 */
244#define REG_TX_BACKOFF5(pn) CRA(0x4,pn,0x2f) /* after 5 */
245#define REG_TX_BACKOFF6(pn) CRA(0x4,pn,0x30) /* after 6 */
246#define REG_TX_BACKOFF7(pn) CRA(0x4,pn,0x31) /* after 7 */
247#define REG_TX_BACKOFF8(pn) CRA(0x4,pn,0x32) /* after 8 */
248#define REG_TX_BACKOFF9(pn) CRA(0x4,pn,0x33) /* after 9 */
249#define REG_TX_BACKOFF10(pn) CRA(0x4,pn,0x34) /* after 10 */
250#define REG_TX_BACKOFF11(pn) CRA(0x4,pn,0x35) /* after 11 */
251#define REG_TX_BACKOFF12(pn) CRA(0x4,pn,0x36) /* after 12 */
252#define REG_TX_BACKOFF13(pn) CRA(0x4,pn,0x37) /* after 13 */
253#define REG_TX_BACKOFF14(pn) CRA(0x4,pn,0x38) /* after 14 */
254#define REG_TX_BACKOFF15(pn) CRA(0x4,pn,0x39) /* after 15 */
255#define REG_TX_UNDERRUN(pn) CRA(0x4,pn,0x3a) /* # frames dropped from underrun */
256#define REG_RX_XGMII_PROT_ERR CRA(0x4,0xa,0x3b) /* # protocol errors detected on XGMII interface */
257#define REG_RX_IPG_SHRINK(pn) CRA(0x4,pn,0x3c) /* # of IPG shrinks detected */
258
259#define REG_STAT_STICKY1G(pn) CRA(0x4,pn,0x3e) /* tri-speed sticky bits */
260#define REG_STAT_STICKY10G CRA(0x4,0xa,0x3e) /* 10GbE sticky bits */
261#define REG_STAT_INIT(pn) CRA(0x4,pn,0x3f) /* Clear all statistics */
262
263/* MII-Management Block registers */
264/* These are for MII-M interface 0, which is the bidirectional LVTTL one. If
265 * we hooked up to the one with separate directions, the middle 0x0 needs to
266 * change to 0x1. And the current errata states that MII-M 1 doesn't work.
267 */
268
269#define REG_MIIM_STATUS CRA(0x3,0x0,0x00) /* MII-M Status */
270#define REG_MIIM_CMD CRA(0x3,0x0,0x01) /* MII-M Command */
271#define REG_MIIM_DATA CRA(0x3,0x0,0x02) /* MII-M Data */
272#define REG_MIIM_PRESCALE CRA(0x3,0x0,0x03) /* MII-M MDC Prescale */
273
274#define REG_ING_FFILT_UM_EN CRA(0x2, 0, 0xd)
275#define REG_ING_FFILT_BE_EN CRA(0x2, 0, 0x1d)
276#define REG_ING_FFILT_VAL0 CRA(0x2, 0, 0x2d)
277#define REG_ING_FFILT_VAL1 CRA(0x2, 0, 0x3d)
278#define REG_ING_FFILT_MASK0 CRA(0x2, 0, 0x4d)
279#define REG_ING_FFILT_MASK1 CRA(0x2, 0, 0x5d)
280#define REG_ING_FFILT_MASK2 CRA(0x2, 0, 0x6d)
281#define REG_ING_FFILT_ETYPE CRA(0x2, 0, 0x7d)
282
283
284/* Whew. */
285
286#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-21 00:37:05 -0500