diff options
| author | Zhenyu Wang <zhenyuw@linux.intel.com> | 2009-09-19 02:54:06 -0400 |
|---|---|---|
| committer | Jesse Barnes <jbarnes@virtuousgeek.org> | 2009-09-17 17:30:14 -0400 |
| commit | b09aea7fb38f328c02e9f9b79617cabed02455e4 (patch) | |
| tree | aa85ac56e90308aed425eb1a40016639ca8eab13 | |
| parent | 6f465a8925016633891f5bf030f9c37036529b39 (diff) | |
drm/i915: Fix typo for wrong LVDS clock setting on IGDNG
New register for PCH LVDS on IGDNG should be used.
This is a copy-n-paste typo. This fixes possible dual
channel LVDS panel failure on IGDNG.
Cc: Stable Team <stable@kernel.org>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index cadb9efdfb1b..d2f3692be8eb 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
| @@ -877,7 +877,7 @@ intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |||
| 877 | refclk, best_clock); | 877 | refclk, best_clock); |
| 878 | 878 | ||
| 879 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | 879 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
| 880 | if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == | 880 | if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == |
| 881 | LVDS_CLKB_POWER_UP) | 881 | LVDS_CLKB_POWER_UP) |
| 882 | clock.p2 = limit->p2.p2_fast; | 882 | clock.p2 = limit->p2.p2_fast; |
| 883 | else | 883 | else |