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authorThomas Bogendoerfer <tsbogend@alpha.franken.de>2008-04-17 16:07:42 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-06-05 13:13:15 -0400
commit96173a6c4ebca4c146bb87026cce78bbe392cb61 (patch)
treef4af691b3efca01f01ff1581ffd26b16ddbf48d0
parentb32bb803fb52cc669762780d44b4c3d9e3d799f6 (diff)
[MIPS] IP27: misc fixes
- fix PCI interrupt assignment by emulating ioc3 interrupt pin register - use pci_probe_only mode - select correct page size in bridge - remove no longer needed ioc3_sio_init() code [Ralf: Fix for 64kB or larger pagesizes] Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r--arch/mips/pci/ops-bridge.c20
-rw-r--r--arch/mips/pci/pci-ip27.c8
-rw-r--r--arch/mips/sgi-ip27/ip27-init.c22
3 files changed, 26 insertions, 24 deletions
diff --git a/arch/mips/pci/ops-bridge.c b/arch/mips/pci/ops-bridge.c
index 1fa09929cd7a..b46b3e211775 100644
--- a/arch/mips/pci/ops-bridge.c
+++ b/arch/mips/pci/ops-bridge.c
@@ -14,6 +14,22 @@
14#include <asm/sn/sn0/hub.h> 14#include <asm/sn/sn0/hub.h>
15 15
16/* 16/*
17 * Most of the IOC3 PCI config register aren't present
18 * we emulate what is needed for a normal PCI enumeration
19 */
20static u32 emulate_ioc3_cfg(int where, int size)
21{
22 if (size == 1 && where == 0x3d)
23 return 0x01;
24 else if (size == 2 && where == 0x3c)
25 return 0x0100;
26 else if (size == 4 && where == 0x3c)
27 return 0x00000100;
28
29 return 0;
30}
31
32/*
17 * The Bridge ASIC supports both type 0 and type 1 access. Type 1 is 33 * The Bridge ASIC supports both type 0 and type 1 access. Type 1 is
18 * not really documented, so right now I can't write code which uses it. 34 * not really documented, so right now I can't write code which uses it.
19 * Therefore we use type 0 accesses for now even though they won't work 35 * Therefore we use type 0 accesses for now even though they won't work
@@ -64,7 +80,7 @@ oh_my_gawd:
64 * generic PCI code a chance to look at the wrong register. 80 * generic PCI code a chance to look at the wrong register.
65 */ 81 */
66 if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) { 82 if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) {
67 *value = 0; 83 *value = emulate_ioc3_cfg(where, size);
68 return PCIBIOS_SUCCESSFUL; 84 return PCIBIOS_SUCCESSFUL;
69 } 85 }
70 86
@@ -127,7 +143,7 @@ oh_my_gawd:
127 * generic PCI code a chance to look at the wrong register. 143 * generic PCI code a chance to look at the wrong register.
128 */ 144 */
129 if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) { 145 if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) {
130 *value = 0; 146 *value = emulate_ioc3_cfg(where, size);
131 return PCIBIOS_SUCCESSFUL; 147 return PCIBIOS_SUCCESSFUL;
132 } 148 }
133 149
diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c
index bb64828a92fe..a18516925cdd 100644
--- a/arch/mips/pci/pci-ip27.c
+++ b/arch/mips/pci/pci-ip27.c
@@ -47,6 +47,9 @@ int __cpuinit bridge_probe(nasid_t nasid, int widget_id, int masterwid)
47 static int num_bridges = 0; 47 static int num_bridges = 0;
48 bridge_t *bridge; 48 bridge_t *bridge;
49 int slot; 49 int slot;
50 extern int pci_probe_only;
51
52 pci_probe_only = 1;
50 53
51 printk("a bridge\n"); 54 printk("a bridge\n");
52 55
@@ -100,6 +103,11 @@ int __cpuinit bridge_probe(nasid_t nasid, int widget_id, int masterwid)
100 */ 103 */
101 bridge->b_wid_control |= BRIDGE_CTRL_IO_SWAP | 104 bridge->b_wid_control |= BRIDGE_CTRL_IO_SWAP |
102 BRIDGE_CTRL_MEM_SWAP; 105 BRIDGE_CTRL_MEM_SWAP;
106#ifdef CONFIG_PAGE_SIZE_4KB
107 bridge->b_wid_control &= ~BRIDGE_CTRL_PAGE_SIZE;
108#else /* 16kB or larger */
109 bridge->b_wid_control |= BRIDGE_CTRL_PAGE_SIZE;
110#endif
103 111
104 /* 112 /*
105 * Hmm... IRIX sets additional bits in the address which 113 * Hmm... IRIX sets additional bits in the address which
diff --git a/arch/mips/sgi-ip27/ip27-init.c b/arch/mips/sgi-ip27/ip27-init.c
index 7093e7c573a4..4a500e8cd3cc 100644
--- a/arch/mips/sgi-ip27/ip27-init.c
+++ b/arch/mips/sgi-ip27/ip27-init.c
@@ -161,27 +161,6 @@ cnodeid_t get_compact_nodeid(void)
161 return NASID_TO_COMPACT_NODEID(get_nasid()); 161 return NASID_TO_COMPACT_NODEID(get_nasid());
162} 162}
163 163
164/* Extracted from the IOC3 meta driver. FIXME. */
165static inline void ioc3_sio_init(void)
166{
167 struct ioc3 *ioc3;
168 nasid_t nid;
169 long loops;
170
171 nid = get_nasid();
172 ioc3 = (struct ioc3 *) KL_CONFIG_CH_CONS_INFO(nid)->memory_base;
173
174 ioc3->sscr_a = 0; /* PIO mode for uarta. */
175 ioc3->sscr_b = 0; /* PIO mode for uartb. */
176 ioc3->sio_iec = ~0;
177 ioc3->sio_ies = (SIO_IR_SA_INT | SIO_IR_SB_INT);
178
179 loops=1000000; while(loops--);
180 ioc3->sregs.uarta.iu_fcr = 0;
181 ioc3->sregs.uartb.iu_fcr = 0;
182 loops=1000000; while(loops--);
183}
184
185static inline void ioc3_eth_init(void) 164static inline void ioc3_eth_init(void)
186{ 165{
187 struct ioc3 *ioc3; 166 struct ioc3 *ioc3;
@@ -234,7 +213,6 @@ void __init plat_mem_setup(void)
234 panic("Kernel compiled for N mode."); 213 panic("Kernel compiled for N mode.");
235#endif 214#endif
236 215
237 ioc3_sio_init();
238 ioc3_eth_init(); 216 ioc3_eth_init();
239 per_cpu_init(); 217 per_cpu_init();
240 218