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authorLi Peng <peng.li@linux.intel.com>2010-05-18 06:58:44 -0400
committerEric Anholt <eric@anholt.net>2010-05-26 17:22:51 -0400
commit9553426372eef71c849499fb1d232f4b0577c0f9 (patch)
tree8df1e5e08fd759c2c7279c232ef7e6732a3e65db
parentd8201ab6514f8dc1a0ccfac52c688d80976a425a (diff)
drm/i915: Add CxSR support on Pineview DDR3
Pineview with DDR3 memory has different latencies to enable CxSR. This patch updates CxSR latency table to add Pineview DDR3 latency configuration. It also adds one flag "is_ddr3" for checking DDR3 setting in MCHBAR. Cc: Shaohua Li <shaohua.li@intel.com> Cc: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Li Peng <peng.li@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c4
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h2
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h4
-rw-r--r--drivers/gpu/drm/i915/intel_display.c72
4 files changed, 53 insertions, 29 deletions
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 12e92f2cc3a7..a5f401664845 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1491,6 +1491,10 @@ static void i915_pineview_get_mem_freq(struct drm_device *dev)
1491 dev_priv->mem_freq = 800; 1491 dev_priv->mem_freq = 800;
1492 break; 1492 break;
1493 } 1493 }
1494
1495 /* detect pineview DDR3 setting */
1496 tmp = I915_READ(CSHRDDR3CTL);
1497 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
1494} 1498}
1495 1499
1496static void i915_ironlake_get_mem_freq(struct drm_device *dev) 1500static void i915_ironlake_get_mem_freq(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cccf8019f65a..e6b4cab6565f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -326,7 +326,7 @@ typedef struct drm_i915_private {
326 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ 326 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
327 int num_fence_regs; /* 8 on pre-965, 16 otherwise */ 327 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
328 328
329 unsigned int fsb_freq, mem_freq; 329 unsigned int fsb_freq, mem_freq, is_ddr3;
330 330
331 spinlock_t error_lock; 331 spinlock_t error_lock;
332 struct drm_i915_error_state *first_error; 332 struct drm_i915_error_state *first_error;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 881fbe9a17f2..af7b10853e33 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -817,6 +817,10 @@
817#define DCC_CHANNEL_XOR_DISABLE (1 << 10) 817#define DCC_CHANNEL_XOR_DISABLE (1 << 10)
818#define DCC_CHANNEL_XOR_BIT_17 (1 << 9) 818#define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
819 819
820/** Pineview MCH register contains DDR3 setting */
821#define CSHRDDR3CTL 0x101a8
822#define CSHRDDR3CTL_DDR3 (1 << 2)
823
820/** 965 MCH register controlling DRAM channel configuration */ 824/** 965 MCH register controlling DRAM channel configuration */
821#define C0DRB3 0x10206 825#define C0DRB3 0x10206
822#define C1DRB3 0x10606 826#define C1DRB3 0x10606
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f946332612ec..cfac4dd1d483 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2640,6 +2640,7 @@ static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2640 2640
2641struct cxsr_latency { 2641struct cxsr_latency {
2642 int is_desktop; 2642 int is_desktop;
2643 int is_ddr3;
2643 unsigned long fsb_freq; 2644 unsigned long fsb_freq;
2644 unsigned long mem_freq; 2645 unsigned long mem_freq;
2645 unsigned long display_sr; 2646 unsigned long display_sr;
@@ -2649,33 +2650,45 @@ struct cxsr_latency {
2649}; 2650};
2650 2651
2651static struct cxsr_latency cxsr_latency_table[] = { 2652static struct cxsr_latency cxsr_latency_table[] = {
2652 {1, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ 2653 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
2653 {1, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ 2654 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
2654 {1, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ 2655 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
2655 2656 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
2656 {1, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ 2657 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
2657 {1, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ 2658
2658 {1, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ 2659 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
2659 2660 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
2660 {1, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ 2661 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
2661 {1, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ 2662 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
2662 {1, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ 2663 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
2663 2664
2664 {0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ 2665 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
2665 {0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ 2666 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
2666 {0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ 2667 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
2667 2668 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
2668 {0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ 2669 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
2669 {0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ 2670
2670 {0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ 2671 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
2671 2672 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
2672 {0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ 2673 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
2673 {0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ 2674 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
2674 {0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ 2675 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
2676
2677 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
2678 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
2679 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
2680 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
2681 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
2682
2683 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
2684 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
2685 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
2686 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
2687 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
2675}; 2688};
2676 2689
2677static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb, 2690static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int is_ddr3,
2678 int mem) 2691 int fsb, int mem)
2679{ 2692{
2680 int i; 2693 int i;
2681 struct cxsr_latency *latency; 2694 struct cxsr_latency *latency;
@@ -2686,6 +2699,7 @@ static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
2686 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { 2699 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2687 latency = &cxsr_latency_table[i]; 2700 latency = &cxsr_latency_table[i];
2688 if (is_desktop == latency->is_desktop && 2701 if (is_desktop == latency->is_desktop &&
2702 is_ddr3 == latency->is_ddr3 &&
2689 fsb == latency->fsb_freq && mem == latency->mem_freq) 2703 fsb == latency->fsb_freq && mem == latency->mem_freq)
2690 return latency; 2704 return latency;
2691 } 2705 }
@@ -2800,8 +2814,8 @@ static void pineview_update_wm(struct drm_device *dev, int planea_clock,
2800 struct cxsr_latency *latency; 2814 struct cxsr_latency *latency;
2801 int sr_clock; 2815 int sr_clock;
2802 2816
2803 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->fsb_freq, 2817 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
2804 dev_priv->mem_freq); 2818 dev_priv->fsb_freq, dev_priv->mem_freq);
2805 if (!latency) { 2819 if (!latency) {
2806 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); 2820 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2807 pineview_disable_cxsr(dev); 2821 pineview_disable_cxsr(dev);
@@ -5406,11 +5420,13 @@ static void intel_init_display(struct drm_device *dev)
5406 dev_priv->display.update_wm = NULL; 5420 dev_priv->display.update_wm = NULL;
5407 } else if (IS_PINEVIEW(dev)) { 5421 } else if (IS_PINEVIEW(dev)) {
5408 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), 5422 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5423 dev_priv->is_ddr3,
5409 dev_priv->fsb_freq, 5424 dev_priv->fsb_freq,
5410 dev_priv->mem_freq)) { 5425 dev_priv->mem_freq)) {
5411 DRM_INFO("failed to find known CxSR latency " 5426 DRM_INFO("failed to find known CxSR latency "
5412 "(found fsb freq %d, mem freq %d), " 5427 "(found ddr%s fsb freq %d, mem freq %d), "
5413 "disabling CxSR\n", 5428 "disabling CxSR\n",
5429 (dev_priv->is_ddr3 == 1) ? "3": "2",
5414 dev_priv->fsb_freq, dev_priv->mem_freq); 5430 dev_priv->fsb_freq, dev_priv->mem_freq);
5415 /* Disable CxSR and never update its watermark again */ 5431 /* Disable CxSR and never update its watermark again */
5416 pineview_disable_cxsr(dev); 5432 pineview_disable_cxsr(dev);