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authorEric Miao <eric.y.miao@gmail.com>2010-10-13 02:51:25 -0400
committerEric Miao <eric.y.miao@gmail.com>2010-12-16 01:31:15 -0500
commit64ed267bdac799485a938dd2cba8243ba383cd5f (patch)
tree5e5c234ddaa0ffb6709bc9fad67a01e0729da612
parentead67b6e6679b14befb0cef59db60e2853e19cd8 (diff)
ARM: pxa: introduce addr-map.h for large bus addresses and ranges
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
-rw-r--r--arch/arm/mach-pxa/include/mach/addr-map.h48
-rw-r--r--arch/arm/mach-pxa/include/mach/hardware.h2
-rw-r--r--arch/arm/mach-pxa/include/mach/pxa2xx-regs.h11
-rw-r--r--arch/arm/mach-pxa/include/mach/pxa3xx-regs.h9
4 files changed, 50 insertions, 20 deletions
diff --git a/arch/arm/mach-pxa/include/mach/addr-map.h b/arch/arm/mach-pxa/include/mach/addr-map.h
new file mode 100644
index 000000000000..f4c03659168c
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/addr-map.h
@@ -0,0 +1,48 @@
1#ifndef __ASM_MACH_ADDR_MAP_H
2#define __ASM_MACH_ADDR_MAP_H
3
4/*
5 * Chip Selects
6 */
7#define PXA_CS0_PHYS 0x00000000
8#define PXA_CS1_PHYS 0x04000000
9#define PXA_CS2_PHYS 0x08000000
10#define PXA_CS3_PHYS 0x0C000000
11#define PXA_CS4_PHYS 0x10000000
12#define PXA_CS5_PHYS 0x14000000
13
14#define PXA300_CS0_PHYS 0x00000000 /* PXA300/PXA310 _only_ */
15#define PXA300_CS1_PHYS 0x30000000 /* PXA300/PXA310 _only_ */
16#define PXA3xx_CS2_PHYS 0x10000000
17#define PXA3xx_CS3_PHYS 0x14000000
18
19/*
20 * Peripheral Bus
21 */
22#define PERIPH_PHYS 0x40000000
23#define PERIPH_VIRT 0xf2000000
24#define PERIPH_SIZE 0x02000000
25
26/*
27 * Static Memory Controller (w/ SDRAM controls on PXA25x/PXA27x)
28 */
29#define PXA2XX_SMEMC_PHYS 0x48000000
30#define PXA3XX_SMEMC_PHYS 0x4a000000
31#define SMEMC_VIRT 0xf6000000
32#define SMEMC_SIZE 0x00100000
33
34/*
35 * Dynamic Memory Controller (only on PXA3xx)
36 */
37#define DMEMC_PHYS 0x48100000
38#define DMEMC_VIRT 0xf6100000
39#define DMEMC_SIZE 0x00100000
40
41/*
42 * Internal Memory Controller (PXA27x and later)
43 */
44#define IMEMC_PHYS 0x58000000
45#define IMEMC_VIRT 0xfe000000
46#define IMEMC_SIZE 0x00100000
47
48#endif /* __ASM_MACH_ADDR_MAP_H */
diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h
index 814f1458a06a..ca188cd576f9 100644
--- a/arch/arm/mach-pxa/include/mach/hardware.h
+++ b/arch/arm/mach-pxa/include/mach/hardware.h
@@ -13,6 +13,8 @@
13#ifndef __ASM_ARCH_HARDWARE_H 13#ifndef __ASM_ARCH_HARDWARE_H
14#define __ASM_ARCH_HARDWARE_H 14#define __ASM_ARCH_HARDWARE_H
15 15
16#include <mach/addr-map.h>
17
16/* 18/*
17 * Workarounds for at least 2 errata so far require this. 19 * Workarounds for at least 2 errata so far require this.
18 * The mapping is set in mach-pxa/generic.c. 20 * The mapping is set in mach-pxa/generic.c.
diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
index 4fcddd9cab76..dd0fc1c95cc0 100644
--- a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
+++ b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
@@ -17,17 +17,6 @@
17#include <mach/hardware.h> 17#include <mach/hardware.h>
18 18
19/* 19/*
20 * PXA Chip selects
21 */
22
23#define PXA_CS0_PHYS 0x00000000
24#define PXA_CS1_PHYS 0x04000000
25#define PXA_CS2_PHYS 0x08000000
26#define PXA_CS3_PHYS 0x0C000000
27#define PXA_CS4_PHYS 0x10000000
28#define PXA_CS5_PHYS 0x14000000
29
30/*
31 * Memory controller 20 * Memory controller
32 */ 21 */
33 22
diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
index e91d63cfe811..e4fb4668c26e 100644
--- a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
+++ b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
@@ -16,15 +16,6 @@
16#include <mach/hardware.h> 16#include <mach/hardware.h>
17 17
18/* 18/*
19 * Static Chip Selects
20 */
21
22#define PXA300_CS0_PHYS (0x00000000) /* PXA300/PXA310 _only_ */
23#define PXA300_CS1_PHYS (0x30000000) /* PXA300/PXA310 _only_ */
24#define PXA3xx_CS2_PHYS (0x10000000)
25#define PXA3xx_CS3_PHYS (0x14000000)
26
27/*
28 * Oscillator Configuration Register (OSCC) 19 * Oscillator Configuration Register (OSCC)
29 */ 20 */
30#define OSCC __REG(0x41350000) /* Oscillator Configuration Register */ 21#define OSCC __REG(0x41350000) /* Oscillator Configuration Register */