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authorLinus Walleij <linus.walleij@stericsson.com>2009-11-19 13:49:17 -0500
committerDan Williams <dan.j.williams@intel.com>2009-11-20 01:45:19 -0500
commit61f135b92f4758bc4d4767cd0a5d2da954e27f14 (patch)
tree388fdc08150e2f8fcb2859f70ca67cdd86616f36
parentb419148e567728f6af0c3b01965c1cc141e3e13a (diff)
Add COH 901 318 DMA block driver v5
This patch adds support for the ST-Ericsson COH 901 318 DMA block, found in the U300 series platforms. It registers a DMA slave for device I/O and also a memcpy slave for memcpy. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat
-rw-r--r--arch/arm/mach-u300/include/mach/coh901318.h281
-rw-r--r--drivers/dma/Kconfig7
-rw-r--r--drivers/dma/Makefile1
-rw-r--r--drivers/dma/coh901318.c1325
-rw-r--r--drivers/dma/coh901318_lli.c318
-rw-r--r--drivers/dma/coh901318_lli.h124
6 files changed, 2056 insertions, 0 deletions
diff --git a/arch/arm/mach-u300/include/mach/coh901318.h b/arch/arm/mach-u300/include/mach/coh901318.h
new file mode 100644
index 000000000000..f4cfee9c7d28
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/coh901318.h
@@ -0,0 +1,281 @@
1/*
2 *
3 * include/linux/coh901318.h
4 *
5 *
6 * Copyright (C) 2007-2009 ST-Ericsson
7 * License terms: GNU General Public License (GPL) version 2
8 * DMA driver for COH 901 318
9 * Author: Per Friden <per.friden@stericsson.com>
10 */
11
12#ifndef COH901318_H
13#define COH901318_H
14
15#include <linux/device.h>
16#include <linux/dmaengine.h>
17
18#define MAX_DMA_PACKET_SIZE_SHIFT 11
19#define MAX_DMA_PACKET_SIZE (1 << MAX_DMA_PACKET_SIZE_SHIFT)
20
21/**
22 * struct coh901318_lli - linked list item for DMAC
23 * @control: control settings for DMAC
24 * @src_addr: transfer source address
25 * @dst_addr: transfer destination address
26 * @link_addr: physical address to next lli
27 * @virt_link_addr: virtual addres of next lli (only used by pool_free)
28 * @phy_this: physical address of current lli (only used by pool_free)
29 */
30struct coh901318_lli {
31 u32 control;
32 dma_addr_t src_addr;
33 dma_addr_t dst_addr;
34 dma_addr_t link_addr;
35
36 void *virt_link_addr;
37 dma_addr_t phy_this;
38};
39/**
40 * struct coh901318_params - parameters for DMAC configuration
41 * @config: DMA config register
42 * @ctrl_lli_last: DMA control register for the last lli in the list
43 * @ctrl_lli: DMA control register for an lli
44 * @ctrl_lli_chained: DMA control register for a chained lli
45 */
46struct coh901318_params {
47 u32 config;
48 u32 ctrl_lli_last;
49 u32 ctrl_lli;
50 u32 ctrl_lli_chained;
51};
52/**
53 * struct coh_dma_channel - dma channel base
54 * @name: ascii name of dma channel
55 * @number: channel id number
56 * @desc_nbr_max: number of preallocated descriptortors
57 * @priority_high: prio of channel, 0 low otherwise high.
58 * @param: configuration parameters
59 * @dev_addr: physical address of periphal connected to channel
60 */
61struct coh_dma_channel {
62 const char name[32];
63 const int number;
64 const int desc_nbr_max;
65 const int priority_high;
66 const struct coh901318_params param;
67 const dma_addr_t dev_addr;
68};
69
70/**
71 * dma_access_memory_state_t - register dma for memory access
72 *
73 * @dev: The dma device
74 * @active: 1 means dma intends to access memory
75 * 0 means dma wont access memory
76 */
77typedef void (*dma_access_memory_state_t)(struct device *dev,
78 bool active);
79
80/**
81 * struct powersave - DMA power save structure
82 * @lock: lock protecting data in this struct
83 * @started_channels: bit mask indicating active dma channels
84 */
85struct powersave {
86 spinlock_t lock;
87 u64 started_channels;
88};
89/**
90 * struct coh901318_platform - platform arch structure
91 * @chans_slave: specifying dma slave channels
92 * @chans_memcpy: specifying dma memcpy channels
93 * @access_memory_state: requesting DMA memeory access (on / off)
94 * @chan_conf: dma channel configurations
95 * @max_channels: max number of dma chanenls
96 */
97struct coh901318_platform {
98 const int *chans_slave;
99 const int *chans_memcpy;
100 const dma_access_memory_state_t access_memory_state;
101 const struct coh_dma_channel *chan_conf;
102 const int max_channels;
103};
104
105/**
106 * coh901318_get_bytes_left() - Get number of bytes left on a current transfer
107 * @chan: dma channel handle
108 * return number of bytes left, or negative on error
109 */
110u32 coh901318_get_bytes_left(struct dma_chan *chan);
111
112/**
113 * coh901318_stop() - Stops dma transfer
114 * @chan: dma channel handle
115 * return 0 on success otherwise negative value
116 */
117void coh901318_stop(struct dma_chan *chan);
118
119/**
120 * coh901318_continue() - Resumes a stopped dma transfer
121 * @chan: dma channel handle
122 * return 0 on success otherwise negative value
123 */
124void coh901318_continue(struct dma_chan *chan);
125
126/**
127 * coh901318_filter_id() - DMA channel filter function
128 * @chan: dma channel handle
129 * @chan_id: id of dma channel to be filter out
130 *
131 * In dma_request_channel() it specifies what channel id to be requested
132 */
133bool coh901318_filter_id(struct dma_chan *chan, void *chan_id);
134
135/*
136 * DMA Controller - this access the static mappings of the coh901318 dma.
137 *
138 */
139
140#define COH901318_MOD32_MASK (0x1F)
141#define COH901318_WORD_MASK (0xFFFFFFFF)
142/* INT_STATUS - Interrupt Status Registers 32bit (R/-) */
143#define COH901318_INT_STATUS1 (0x0000)
144#define COH901318_INT_STATUS2 (0x0004)
145/* TC_INT_STATUS - Terminal Count Interrupt Status Registers 32bit (R/-) */
146#define COH901318_TC_INT_STATUS1 (0x0008)
147#define COH901318_TC_INT_STATUS2 (0x000C)
148/* TC_INT_CLEAR - Terminal Count Interrupt Clear Registers 32bit (-/W) */
149#define COH901318_TC_INT_CLEAR1 (0x0010)
150#define COH901318_TC_INT_CLEAR2 (0x0014)
151/* RAW_TC_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
152#define COH901318_RAW_TC_INT_STATUS1 (0x0018)
153#define COH901318_RAW_TC_INT_STATUS2 (0x001C)
154/* BE_INT_STATUS - Bus Error Interrupt Status Registers 32bit (R/-) */
155#define COH901318_BE_INT_STATUS1 (0x0020)
156#define COH901318_BE_INT_STATUS2 (0x0024)
157/* BE_INT_CLEAR - Bus Error Interrupt Clear Registers 32bit (-/W) */
158#define COH901318_BE_INT_CLEAR1 (0x0028)
159#define COH901318_BE_INT_CLEAR2 (0x002C)
160/* RAW_BE_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
161#define COH901318_RAW_BE_INT_STATUS1 (0x0030)
162#define COH901318_RAW_BE_INT_STATUS2 (0x0034)
163
164/*
165 * CX_CFG - Channel Configuration Registers 32bit (R/W)
166 */
167#define COH901318_CX_CFG (0x0100)
168#define COH901318_CX_CFG_SPACING (0x04)
169/* Channel enable activates tha dma job */
170#define COH901318_CX_CFG_CH_ENABLE (0x00000001)
171#define COH901318_CX_CFG_CH_DISABLE (0x00000000)
172/* Request Mode */
173#define COH901318_CX_CFG_RM_MASK (0x00000006)
174#define COH901318_CX_CFG_RM_MEMORY_TO_MEMORY (0x0 << 1)
175#define COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY (0x1 << 1)
176#define COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY (0x1 << 1)
177#define COH901318_CX_CFG_RM_PRIMARY_TO_SECONDARY (0x3 << 1)
178#define COH901318_CX_CFG_RM_SECONDARY_TO_PRIMARY (0x3 << 1)
179/* Linked channel request field. RM must == 11 */
180#define COH901318_CX_CFG_LCRF_SHIFT 3
181#define COH901318_CX_CFG_LCRF_MASK (0x000001F8)
182#define COH901318_CX_CFG_LCR_DISABLE (0x00000000)
183/* Terminal Counter Interrupt Request Mask */
184#define COH901318_CX_CFG_TC_IRQ_ENABLE (0x00000200)
185#define COH901318_CX_CFG_TC_IRQ_DISABLE (0x00000000)
186/* Bus Error interrupt Mask */
187#define COH901318_CX_CFG_BE_IRQ_ENABLE (0x00000400)
188#define COH901318_CX_CFG_BE_IRQ_DISABLE (0x00000000)
189
190/*
191 * CX_STAT - Channel Status Registers 32bit (R/-)
192 */
193#define COH901318_CX_STAT (0x0200)
194#define COH901318_CX_STAT_SPACING (0x04)
195#define COH901318_CX_STAT_RBE_IRQ_IND (0x00000008)
196#define COH901318_CX_STAT_RTC_IRQ_IND (0x00000004)
197#define COH901318_CX_STAT_ACTIVE (0x00000002)
198#define COH901318_CX_STAT_ENABLED (0x00000001)
199
200/*
201 * CX_CTRL - Channel Control Registers 32bit (R/W)
202 */
203#define COH901318_CX_CTRL (0x0400)
204#define COH901318_CX_CTRL_SPACING (0x10)
205/* Transfer Count Enable */
206#define COH901318_CX_CTRL_TC_ENABLE (0x00001000)
207#define COH901318_CX_CTRL_TC_DISABLE (0x00000000)
208/* Transfer Count Value 0 - 4095 */
209#define COH901318_CX_CTRL_TC_VALUE_MASK (0x00000FFF)
210/* Burst count */
211#define COH901318_CX_CTRL_BURST_COUNT_MASK (0x0000E000)
212#define COH901318_CX_CTRL_BURST_COUNT_64_BYTES (0x7 << 13)
213#define COH901318_CX_CTRL_BURST_COUNT_48_BYTES (0x6 << 13)
214#define COH901318_CX_CTRL_BURST_COUNT_32_BYTES (0x5 << 13)
215#define COH901318_CX_CTRL_BURST_COUNT_16_BYTES (0x4 << 13)
216#define COH901318_CX_CTRL_BURST_COUNT_8_BYTES (0x3 << 13)
217#define COH901318_CX_CTRL_BURST_COUNT_4_BYTES (0x2 << 13)
218#define COH901318_CX_CTRL_BURST_COUNT_2_BYTES (0x1 << 13)
219#define COH901318_CX_CTRL_BURST_COUNT_1_BYTE (0x0 << 13)
220/* Source bus size */
221#define COH901318_CX_CTRL_SRC_BUS_SIZE_MASK (0x00030000)
222#define COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS (0x2 << 16)
223#define COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS (0x1 << 16)
224#define COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS (0x0 << 16)
225/* Source address increment */
226#define COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE (0x00040000)
227#define COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE (0x00000000)
228/* Destination Bus Size */
229#define COH901318_CX_CTRL_DST_BUS_SIZE_MASK (0x00180000)
230#define COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS (0x2 << 19)
231#define COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS (0x1 << 19)
232#define COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS (0x0 << 19)
233/* Destination address increment */
234#define COH901318_CX_CTRL_DST_ADDR_INC_ENABLE (0x00200000)
235#define COH901318_CX_CTRL_DST_ADDR_INC_DISABLE (0x00000000)
236/* Master Mode (Master2 is only connected to MSL) */
237#define COH901318_CX_CTRL_MASTER_MODE_MASK (0x00C00000)
238#define COH901318_CX_CTRL_MASTER_MODE_M2R_M1W (0x3 << 22)
239#define COH901318_CX_CTRL_MASTER_MODE_M1R_M2W (0x2 << 22)
240#define COH901318_CX_CTRL_MASTER_MODE_M2RW (0x1 << 22)
241#define COH901318_CX_CTRL_MASTER_MODE_M1RW (0x0 << 22)
242/* Terminal Count flag to PER enable */
243#define COH901318_CX_CTRL_TCP_ENABLE (0x01000000)
244#define COH901318_CX_CTRL_TCP_DISABLE (0x00000000)
245/* Terminal Count flags to CPU enable */
246#define COH901318_CX_CTRL_TC_IRQ_ENABLE (0x02000000)
247#define COH901318_CX_CTRL_TC_IRQ_DISABLE (0x00000000)
248/* Hand shake to peripheral */
249#define COH901318_CX_CTRL_HSP_ENABLE (0x04000000)
250#define COH901318_CX_CTRL_HSP_DISABLE (0x00000000)
251#define COH901318_CX_CTRL_HSS_ENABLE (0x08000000)
252#define COH901318_CX_CTRL_HSS_DISABLE (0x00000000)
253/* DMA mode */
254#define COH901318_CX_CTRL_DDMA_MASK (0x30000000)
255#define COH901318_CX_CTRL_DDMA_LEGACY (0x0 << 28)
256#define COH901318_CX_CTRL_DDMA_DEMAND_DMA1 (0x1 << 28)
257#define COH901318_CX_CTRL_DDMA_DEMAND_DMA2 (0x2 << 28)
258/* Primary Request Data Destination */
259#define COH901318_CX_CTRL_PRDD_MASK (0x40000000)
260#define COH901318_CX_CTRL_PRDD_DEST (0x1 << 30)
261#define COH901318_CX_CTRL_PRDD_SOURCE (0x0 << 30)
262
263/*
264 * CX_SRC_ADDR - Channel Source Address Registers 32bit (R/W)
265 */
266#define COH901318_CX_SRC_ADDR (0x0404)
267#define COH901318_CX_SRC_ADDR_SPACING (0x10)
268
269/*
270 * CX_DST_ADDR - Channel Destination Address Registers 32bit R/W
271 */
272#define COH901318_CX_DST_ADDR (0x0408)
273#define COH901318_CX_DST_ADDR_SPACING (0x10)
274
275/*
276 * CX_LNK_ADDR - Channel Link Address Registers 32bit (R/W)
277 */
278#define COH901318_CX_LNK_ADDR (0x040C)
279#define COH901318_CX_LNK_ADDR_SPACING (0x10)
280#define COH901318_CX_LNK_LINK_IMMEDIATE (0x00000001)
281#endif /* COH901318_H */
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 5903a88351bf..24cdd20fe462 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -109,6 +109,13 @@ config SH_DMAE
109 help 109 help
110 Enable support for the Renesas SuperH DMA controllers. 110 Enable support for the Renesas SuperH DMA controllers.
111 111
112config COH901318
113 bool "ST-Ericsson COH901318 DMA support"
114 select DMA_ENGINE
115 depends on ARCH_U300
116 help
117 Enable support for ST-Ericsson COH 901 318 DMA.
118
112config DMA_ENGINE 119config DMA_ENGINE
113 bool 120 bool
114 121
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index eca71ba78ae9..4db768e09cf3 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_AT_HDMAC) += at_hdmac.o
10obj-$(CONFIG_MX3_IPU) += ipu/ 10obj-$(CONFIG_MX3_IPU) += ipu/
11obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o 11obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o
12obj-$(CONFIG_SH_DMAE) += shdma.o 12obj-$(CONFIG_SH_DMAE) += shdma.o
13obj-$(CONFIG_COH901318) += coh901318.o coh901318_lli.o
diff --git a/drivers/dma/coh901318.c b/drivers/dma/coh901318.c
new file mode 100644
index 000000000000..4a99cd94536b
--- /dev/null
+++ b/drivers/dma/coh901318.c
@@ -0,0 +1,1325 @@
1/*
2 * driver/dma/coh901318.c
3 *
4 * Copyright (C) 2007-2009 ST-Ericsson
5 * License terms: GNU General Public License (GPL) version 2
6 * DMA driver for COH 901 318
7 * Author: Per Friden <per.friden@stericsson.com>
8 */
9
10#include <linux/init.h>
11#include <linux/module.h>
12#include <linux/kernel.h> /* printk() */
13#include <linux/fs.h> /* everything... */
14#include <linux/slab.h> /* kmalloc() */
15#include <linux/dmaengine.h>
16#include <linux/platform_device.h>
17#include <linux/device.h>
18#include <linux/irqreturn.h>
19#include <linux/interrupt.h>
20#include <linux/io.h>
21#include <linux/uaccess.h>
22#include <linux/debugfs.h>
23#include <mach/coh901318.h>
24
25#include "coh901318_lli.h"
26
27#define COHC_2_DEV(cohc) (&cohc->chan.dev->device)
28
29#ifdef VERBOSE_DEBUG
30#define COH_DBG(x) ({ if (1) x; 0; })
31#else
32#define COH_DBG(x) ({ if (0) x; 0; })
33#endif
34
35struct coh901318_desc {
36 struct dma_async_tx_descriptor desc;
37 struct list_head node;
38 struct scatterlist *sg;
39 unsigned int sg_len;
40 struct coh901318_lli *data;
41 enum dma_data_direction dir;
42 int pending_irqs;
43 unsigned long flags;
44};
45
46struct coh901318_base {
47 struct device *dev;
48 void __iomem *virtbase;
49 struct coh901318_pool pool;
50 struct powersave pm;
51 struct dma_device dma_slave;
52 struct dma_device dma_memcpy;
53 struct coh901318_chan *chans;
54 struct coh901318_platform *platform;
55};
56
57struct coh901318_chan {
58 spinlock_t lock;
59 int allocated;
60 int completed;
61 int id;
62 int stopped;
63
64 struct work_struct free_work;
65 struct dma_chan chan;
66
67 struct tasklet_struct tasklet;
68
69 struct list_head active;
70 struct list_head queue;
71 struct list_head free;
72
73 unsigned long nbr_active_done;
74 unsigned long busy;
75 int pending_irqs;
76
77 struct coh901318_base *base;
78};
79
80static void coh901318_list_print(struct coh901318_chan *cohc,
81 struct coh901318_lli *lli)
82{
83 struct coh901318_lli *l;
84 dma_addr_t addr = virt_to_phys(lli);
85 int i = 0;
86
87 while (addr) {
88 l = phys_to_virt(addr);
89 dev_vdbg(COHC_2_DEV(cohc), "i %d, lli %p, ctrl 0x%x, src 0x%x"
90 ", dst 0x%x, link 0x%x link_virt 0x%p\n",
91 i, l, l->control, l->src_addr, l->dst_addr,
92 l->link_addr, phys_to_virt(l->link_addr));
93 i++;
94 addr = l->link_addr;
95 }
96}
97
98#ifdef CONFIG_DEBUG_FS
99
100#define COH901318_DEBUGFS_ASSIGN(x, y) (x = y)
101
102static struct coh901318_base *debugfs_dma_base;
103static struct dentry *dma_dentry;
104
105static int coh901318_debugfs_open(struct inode *inode, struct file *file)
106{
107
108 file->private_data = inode->i_private;
109 return 0;
110}
111
112static int coh901318_debugfs_read(struct file *file, char __user *buf,
113 size_t count, loff_t *f_pos)
114{
115 u64 started_channels = debugfs_dma_base->pm.started_channels;
116 int pool_count = debugfs_dma_base->pool.debugfs_pool_counter;
117 int i;
118 int ret = 0;
119 char *dev_buf;
120 char *tmp;
121 int dev_size;
122
123 dev_buf = kmalloc(4*1024, GFP_KERNEL);
124 if (dev_buf == NULL)
125 goto err_kmalloc;
126 tmp = dev_buf;
127
128 tmp += sprintf(tmp, "DMA -- enable dma channels\n");
129
130 for (i = 0; i < debugfs_dma_base->platform->max_channels; i++)
131 if (started_channels & (1 << i))
132 tmp += sprintf(tmp, "channel %d\n", i);
133
134 tmp += sprintf(tmp, "Pool alloc nbr %d\n", pool_count);
135 dev_size = tmp - dev_buf;
136
137 /* No more to read if offset != 0 */
138 if (*f_pos > dev_size)
139 goto out;
140
141 if (count > dev_size - *f_pos)
142 count = dev_size - *f_pos;
143
144 if (copy_to_user(buf, dev_buf + *f_pos, count))
145 ret = -EINVAL;
146 ret = count;
147 *f_pos += count;
148
149 out:
150 kfree(dev_buf);
151 return ret;
152
153 err_kmalloc:
154 return 0;
155}
156
157static const struct file_operations coh901318_debugfs_status_operations = {
158 .owner = THIS_MODULE,
159 .open = coh901318_debugfs_open,
160 .read = coh901318_debugfs_read,
161};
162
163
164static int __init init_coh901318_debugfs(void)
165{
166
167 dma_dentry = debugfs_create_dir("dma", NULL);
168
169 (void) debugfs_create_file("status",
170 S_IFREG | S_IRUGO,
171 dma_dentry, NULL,
172 &coh901318_debugfs_status_operations);
173 return 0;
174}
175
176static void __exit exit_coh901318_debugfs(void)
177{
178 debugfs_remove_recursive(dma_dentry);
179}
180
181module_init(init_coh901318_debugfs);
182module_exit(exit_coh901318_debugfs);
183#else
184
185#define COH901318_DEBUGFS_ASSIGN(x, y)
186
187#endif /* CONFIG_DEBUG_FS */
188
189static inline struct coh901318_chan *to_coh901318_chan(struct dma_chan *chan)
190{
191 return container_of(chan, struct coh901318_chan, chan);
192}
193
194static inline dma_addr_t
195cohc_dev_addr(struct coh901318_chan *cohc)
196{
197 return cohc->base->platform->chan_conf[cohc->id].dev_addr;
198}
199
200static inline const struct coh901318_params *
201cohc_chan_param(struct coh901318_chan *cohc)
202{
203 return &cohc->base->platform->chan_conf[cohc->id].param;
204}
205
206static inline const struct coh_dma_channel *
207cohc_chan_conf(struct coh901318_chan *cohc)
208{
209 return &cohc->base->platform->chan_conf[cohc->id];
210}
211
212static void enable_powersave(struct coh901318_chan *cohc)
213{
214 unsigned long flags;
215 struct powersave *pm = &cohc->base->pm;
216
217 spin_lock_irqsave(&pm->lock, flags);
218
219 pm->started_channels &= ~(1ULL << cohc->id);
220
221 if (!pm->started_channels) {
222 /* DMA no longer intends to access memory */
223 cohc->base->platform->access_memory_state(cohc->base->dev,
224 false);
225 }
226
227 spin_unlock_irqrestore(&pm->lock, flags);
228}
229static void disable_powersave(struct coh901318_chan *cohc)
230{
231 unsigned long flags;
232 struct powersave *pm = &cohc->base->pm;
233
234 spin_lock_irqsave(&pm->lock, flags);
235
236 if (!pm->started_channels) {
237 /* DMA intends to access memory */
238 cohc->base->platform->access_memory_state(cohc->base->dev,
239 true);
240 }
241
242 pm->started_channels |= (1ULL << cohc->id);
243
244 spin_unlock_irqrestore(&pm->lock, flags);
245}
246
247static inline int coh901318_set_ctrl(struct coh901318_chan *cohc, u32 control)
248{
249 int channel = cohc->id;
250 void __iomem *virtbase = cohc->base->virtbase;
251
252 writel(control,
253 virtbase + COH901318_CX_CTRL +
254 COH901318_CX_CTRL_SPACING * channel);
255 return 0;
256}
257
258static inline int coh901318_set_conf(struct coh901318_chan *cohc, u32 conf)
259{
260 int channel = cohc->id;
261 void __iomem *virtbase = cohc->base->virtbase;
262
263 writel(conf,
264 virtbase + COH901318_CX_CFG +
265 COH901318_CX_CFG_SPACING*channel);
266 return 0;
267}
268
269
270static int coh901318_start(struct coh901318_chan *cohc)
271{
272 u32 val;
273 int channel = cohc->id;
274 void __iomem *virtbase = cohc->base->virtbase;
275
276 disable_powersave(cohc);
277
278 val = readl(virtbase + COH901318_CX_CFG +
279 COH901318_CX_CFG_SPACING * channel);
280
281 /* Enable channel */
282 val |= COH901318_CX_CFG_CH_ENABLE;
283 writel(val, virtbase + COH901318_CX_CFG +
284 COH901318_CX_CFG_SPACING * channel);
285
286 return 0;
287}
288
289static int coh901318_prep_linked_list(struct coh901318_chan *cohc,
290 struct coh901318_lli *data)
291{
292 int channel = cohc->id;
293 void __iomem *virtbase = cohc->base->virtbase;
294
295 BUG_ON(readl(virtbase + COH901318_CX_STAT +
296 COH901318_CX_STAT_SPACING*channel) &
297 COH901318_CX_STAT_ACTIVE);
298
299 writel(data->src_addr,
300 virtbase + COH901318_CX_SRC_ADDR +
301 COH901318_CX_SRC_ADDR_SPACING * channel);
302
303 writel(data->dst_addr, virtbase +
304 COH901318_CX_DST_ADDR +
305 COH901318_CX_DST_ADDR_SPACING * channel);
306
307 writel(data->link_addr, virtbase + COH901318_CX_LNK_ADDR +
308 COH901318_CX_LNK_ADDR_SPACING * channel);
309
310 writel(data->control, virtbase + COH901318_CX_CTRL +
311 COH901318_CX_CTRL_SPACING * channel);
312
313 return 0;
314}
315static dma_cookie_t
316coh901318_assign_cookie(struct coh901318_chan *cohc,
317 struct coh901318_desc *cohd)
318{
319 dma_cookie_t cookie = cohc->chan.cookie;
320
321 if (++cookie < 0)
322 cookie = 1;
323
324 cohc->chan.cookie = cookie;
325 cohd->desc.cookie = cookie;
326
327 return cookie;
328}
329
330static struct coh901318_desc *
331coh901318_desc_get(struct coh901318_chan *cohc)
332{
333 struct coh901318_desc *desc;
334
335 if (list_empty(&cohc->free)) {
336 /* alloc new desc because we're out of used ones
337 * TODO: alloc a pile of descs instead of just one,
338 * avoid many small allocations.
339 */
340 desc = kmalloc(sizeof(struct coh901318_desc), GFP_NOWAIT);
341 if (desc == NULL)
342 goto out;
343 INIT_LIST_HEAD(&desc->node);
344 } else {
345 /* Reuse an old desc. */
346 desc = list_first_entry(&cohc->free,
347 struct coh901318_desc,
348 node);
349 list_del(&desc->node);
350 }
351
352 out:
353 return desc;
354}
355
356static void
357coh901318_desc_free(struct coh901318_chan *cohc, struct coh901318_desc *cohd)
358{
359 list_add_tail(&cohd->node, &cohc->free);
360}
361
362/* call with irq lock held */
363static void
364coh901318_desc_submit(struct coh901318_chan *cohc, struct coh901318_desc *desc)
365{
366 list_add_tail(&desc->node, &cohc->active);
367
368 BUG_ON(cohc->pending_irqs != 0);
369
370 cohc->pending_irqs = desc->pending_irqs;
371}
372
373static struct coh901318_desc *
374coh901318_first_active_get(struct coh901318_chan *cohc)
375{
376 struct coh901318_desc *d;
377
378 if (list_empty(&cohc->active))
379 return NULL;
380
381 d = list_first_entry(&cohc->active,
382 struct coh901318_desc,
383 node);
384 return d;
385}
386
387static void
388coh901318_desc_remove(struct coh901318_desc *cohd)
389{
390 list_del(&cohd->node);
391}
392
393static void
394coh901318_desc_queue(struct coh901318_chan *cohc, struct coh901318_desc *desc)
395{
396 list_add_tail(&desc->node, &cohc->queue);
397}
398
399static struct coh901318_desc *
400coh901318_first_queued(struct coh901318_chan *cohc)
401{
402 struct coh901318_desc *d;
403
404 if (list_empty(&cohc->queue))
405 return NULL;
406
407 d = list_first_entry(&cohc->queue,
408 struct coh901318_desc,
409 node);
410 return d;
411}
412
413/*
414 * DMA start/stop controls
415 */
416u32 coh901318_get_bytes_left(struct dma_chan *chan)
417{
418 unsigned long flags;
419 u32 ret;
420 struct coh901318_chan *cohc = to_coh901318_chan(chan);
421
422 spin_lock_irqsave(&cohc->lock, flags);
423
424 /* Read transfer count value */
425 ret = readl(cohc->base->virtbase +
426 COH901318_CX_CTRL+COH901318_CX_CTRL_SPACING *
427 cohc->id) & COH901318_CX_CTRL_TC_VALUE_MASK;
428
429 spin_unlock_irqrestore(&cohc->lock, flags);
430
431 return ret;
432}
433EXPORT_SYMBOL(coh901318_get_bytes_left);
434
435
436/* Stops a transfer without losing data. Enables power save.
437 Use this function in conjunction with coh901318_continue(..)
438*/
439void coh901318_stop(struct dma_chan *chan)
440{
441 u32 val;
442 unsigned long flags;
443 struct coh901318_chan *cohc = to_coh901318_chan(chan);
444 int channel = cohc->id;
445 void __iomem *virtbase = cohc->base->virtbase;
446
447 spin_lock_irqsave(&cohc->lock, flags);
448
449 /* Disable channel in HW */
450 val = readl(virtbase + COH901318_CX_CFG +
451 COH901318_CX_CFG_SPACING * channel);
452
453 /* Stopping infinit transfer */
454 if ((val & COH901318_CX_CTRL_TC_ENABLE) == 0 &&
455 (val & COH901318_CX_CFG_CH_ENABLE))
456 cohc->stopped = 1;
457
458
459 val &= ~COH901318_CX_CFG_CH_ENABLE;
460 /* Enable twice, HW bug work around */
461 writel(val, virtbase + COH901318_CX_CFG +
462 COH901318_CX_CFG_SPACING * channel);
463 writel(val, virtbase + COH901318_CX_CFG +
464 COH901318_CX_CFG_SPACING * channel);
465
466 /* Spin-wait for it to actually go inactive */
467 while (readl(virtbase + COH901318_CX_STAT+COH901318_CX_STAT_SPACING *
468 channel) & COH901318_CX_STAT_ACTIVE)
469 cpu_relax();
470
471 /* Check if we stopped an active job */
472 if ((readl(virtbase + COH901318_CX_CTRL+COH901318_CX_CTRL_SPACING *
473 channel) & COH901318_CX_CTRL_TC_VALUE_MASK) > 0)
474 cohc->stopped = 1;
475
476 enable_powersave(cohc);
477
478 spin_unlock_irqrestore(&cohc->lock, flags);
479}
480EXPORT_SYMBOL(coh901318_stop);
481
482/* Continues a transfer that has been stopped via 300_dma_stop(..).
483 Power save is handled.
484*/
485void coh901318_continue(struct dma_chan *chan)
486{
487 u32 val;
488 unsigned long flags;
489 struct coh901318_chan *cohc = to_coh901318_chan(chan);
490 int channel = cohc->id;
491
492 spin_lock_irqsave(&cohc->lock, flags);
493
494 disable_powersave(cohc);
495
496 if (cohc->stopped) {
497 /* Enable channel in HW */
498 val = readl(cohc->base->virtbase + COH901318_CX_CFG +
499 COH901318_CX_CFG_SPACING * channel);
500
501 val |= COH901318_CX_CFG_CH_ENABLE;
502
503 writel(val, cohc->base->virtbase + COH901318_CX_CFG +
504 COH901318_CX_CFG_SPACING*channel);
505
506 cohc->stopped = 0;
507 }
508
509 spin_unlock_irqrestore(&cohc->lock, flags);
510}
511EXPORT_SYMBOL(coh901318_continue);
512
513bool coh901318_filter_id(struct dma_chan *chan, void *chan_id)
514{
515 unsigned int ch_nr = (unsigned int) chan_id;
516
517 if (ch_nr == to_coh901318_chan(chan)->id)
518 return true;
519
520 return false;
521}
522EXPORT_SYMBOL(coh901318_filter_id);
523
524/*
525 * DMA channel allocation
526 */
527static int coh901318_config(struct coh901318_chan *cohc,
528 struct coh901318_params *param)
529{
530 unsigned long flags;
531 const struct coh901318_params *p;
532 int channel = cohc->id;
533 void __iomem *virtbase = cohc->base->virtbase;
534
535 spin_lock_irqsave(&cohc->lock, flags);
536
537 if (param)
538 p = param;
539 else
540 p = &cohc->base->platform->chan_conf[channel].param;
541
542 /* Clear any pending BE or TC interrupt */
543 if (channel < 32) {
544 writel(1 << channel, virtbase + COH901318_BE_INT_CLEAR1);
545 writel(1 << channel, virtbase + COH901318_TC_INT_CLEAR1);
546 } else {
547 writel(1 << (channel - 32), virtbase +
548 COH901318_BE_INT_CLEAR2);
549 writel(1 << (channel - 32), virtbase +
550 COH901318_TC_INT_CLEAR2);
551 }
552
553 coh901318_set_conf(cohc, p->config);
554 coh901318_set_ctrl(cohc, p->ctrl_lli_last);
555
556 spin_unlock_irqrestore(&cohc->lock, flags);
557
558 return 0;
559}
560
561/* must lock when calling this function
562 * start queued jobs, if any
563 * TODO: start all queued jobs in one go
564 *
565 * Returns descriptor if queued job is started otherwise NULL.
566 * If the queue is empty NULL is returned.
567 */
568static struct coh901318_desc *coh901318_queue_start(struct coh901318_chan *cohc)
569{
570 struct coh901318_desc *cohd_que;
571
572 /* start queued jobs, if any
573 * TODO: transmit all queued jobs in one go
574 */
575 cohd_que = coh901318_first_queued(cohc);
576
577 if (cohd_que != NULL) {
578 /* Remove from queue */
579 coh901318_desc_remove(cohd_que);
580 /* initiate DMA job */
581 cohc->busy = 1;
582
583 coh901318_desc_submit(cohc, cohd_que);
584
585 coh901318_prep_linked_list(cohc, cohd_que->data);
586
587 /* start dma job */
588 coh901318_start(cohc);
589
590 }
591
592 return cohd_que;
593}
594
595static void dma_tasklet(unsigned long data)
596{
597 struct coh901318_chan *cohc = (struct coh901318_chan *) data;
598 struct coh901318_desc *cohd_fin;
599 unsigned long flags;
600 dma_async_tx_callback callback;
601 void *callback_param;
602
603 spin_lock_irqsave(&cohc->lock, flags);
604
605 /* get first active entry from list */
606 cohd_fin = coh901318_first_active_get(cohc);
607
608 BUG_ON(cohd_fin->pending_irqs == 0);
609
610 if (cohd_fin == NULL)
611 goto err;
612
613 cohd_fin->pending_irqs--;
614 cohc->completed = cohd_fin->desc.cookie;
615
616 BUG_ON(cohc->nbr_active_done && cohd_fin == NULL);
617
618 if (cohc->nbr_active_done == 0)
619 return;
620
621 if (!cohd_fin->pending_irqs) {
622 /* release the lli allocation*/
623 coh901318_lli_free(&cohc->base->pool, &cohd_fin->data);
624 }
625
626 dev_vdbg(COHC_2_DEV(cohc), "[%s] chan_id %d pending_irqs %d"
627 " nbr_active_done %ld\n", __func__,
628 cohc->id, cohc->pending_irqs, cohc->nbr_active_done);
629
630 /* callback to client */
631 callback = cohd_fin->desc.callback;
632 callback_param = cohd_fin->desc.callback_param;
633
634 if (!cohd_fin->pending_irqs) {
635 coh901318_desc_remove(cohd_fin);
636
637 /* return desc to free-list */
638 coh901318_desc_free(cohc, cohd_fin);
639 }
640
641 if (cohc->nbr_active_done)
642 cohc->nbr_active_done--;
643
644 if (cohc->nbr_active_done) {
645 if (cohc_chan_conf(cohc)->priority_high)
646 tasklet_hi_schedule(&cohc->tasklet);
647 else
648 tasklet_schedule(&cohc->tasklet);
649 }
650 spin_unlock_irqrestore(&cohc->lock, flags);
651
652 if (callback)
653 callback(callback_param);
654
655 return;
656
657 err:
658 spin_unlock_irqrestore(&cohc->lock, flags);
659 dev_err(COHC_2_DEV(cohc), "[%s] No active dma desc\n", __func__);
660}
661
662
663/* called from interrupt context */
664static void dma_tc_handle(struct coh901318_chan *cohc)
665{
666 BUG_ON(!cohc->allocated && (list_empty(&cohc->active) ||
667 list_empty(&cohc->queue)));
668
669 if (!cohc->allocated)
670 return;
671
672 BUG_ON(cohc->pending_irqs == 0);
673
674 cohc->pending_irqs--;
675 cohc->nbr_active_done++;
676
677 if (cohc->pending_irqs == 0 && coh901318_queue_start(cohc) == NULL)
678 cohc->busy = 0;
679
680 BUG_ON(list_empty(&cohc->active));
681
682 if (cohc_chan_conf(cohc)->priority_high)
683 tasklet_hi_schedule(&cohc->tasklet);
684 else
685 tasklet_schedule(&cohc->tasklet);
686}
687
688
689static irqreturn_t dma_irq_handler(int irq, void *dev_id)
690{
691 u32 status1;
692 u32 status2;
693 int i;
694 int ch;
695 struct coh901318_base *base = dev_id;
696 struct coh901318_chan *cohc;
697 void __iomem *virtbase = base->virtbase;
698
699 status1 = readl(virtbase + COH901318_INT_STATUS1);
700 status2 = readl(virtbase + COH901318_INT_STATUS2);
701
702 if (unlikely(status1 == 0 && status2 == 0)) {
703 dev_warn(base->dev, "spurious DMA IRQ from no channel!\n");
704 return IRQ_HANDLED;
705 }
706
707 /* TODO: consider handle IRQ in tasklet here to
708 * minimize interrupt latency */
709
710 /* Check the first 32 DMA channels for IRQ */
711 while (status1) {
712 /* Find first bit set, return as a number. */
713 i = ffs(status1) - 1;
714 ch = i;
715
716 cohc = &base->chans[ch];
717 spin_lock(&cohc->lock);
718
719 /* Mask off this bit */
720 status1 &= ~(1 << i);
721 /* Check the individual channel bits */
722 if (test_bit(i, virtbase + COH901318_BE_INT_STATUS1)) {
723 dev_crit(COHC_2_DEV(cohc),
724 "DMA bus error on channel %d!\n", ch);
725 BUG_ON(1);
726 /* Clear BE interrupt */
727 __set_bit(i, virtbase + COH901318_BE_INT_CLEAR1);
728 } else {
729 /* Caused by TC, really? */
730 if (unlikely(!test_bit(i, virtbase +
731 COH901318_TC_INT_STATUS1))) {
732 dev_warn(COHC_2_DEV(cohc),
733 "ignoring interrupt not caused by terminal count on channel %d\n", ch);
734 /* Clear TC interrupt */
735 BUG_ON(1);
736 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1);
737 } else {
738 /* Enable powersave if transfer has finished */
739 if (!(readl(virtbase + COH901318_CX_STAT +
740 COH901318_CX_STAT_SPACING*ch) &
741 COH901318_CX_STAT_ENABLED)) {
742 enable_powersave(cohc);
743 }
744
745 /* Must clear TC interrupt before calling
746 * dma_tc_handle
747 * in case tc_handle initate a new dma job
748 */
749 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1);
750
751 dma_tc_handle(cohc);
752 }
753 }
754 spin_unlock(&cohc->lock);
755 }
756
757 /* Check the remaining 32 DMA channels for IRQ */
758 while (status2) {
759 /* Find first bit set, return as a number. */
760 i = ffs(status2) - 1;
761 ch = i + 32;
762 cohc = &base->chans[ch];
763 spin_lock(&cohc->lock);
764
765 /* Mask off this bit */
766 status2 &= ~(1 << i);
767 /* Check the individual channel bits */
768 if (test_bit(i, virtbase + COH901318_BE_INT_STATUS2)) {
769 dev_crit(COHC_2_DEV(cohc),
770 "DMA bus error on channel %d!\n", ch);
771 /* Clear BE interrupt */
772 BUG_ON(1);
773 __set_bit(i, virtbase + COH901318_BE_INT_CLEAR2);
774 } else {
775 /* Caused by TC, really? */
776 if (unlikely(!test_bit(i, virtbase +
777 COH901318_TC_INT_STATUS2))) {
778 dev_warn(COHC_2_DEV(cohc),
779 "ignoring interrupt not caused by terminal count on channel %d\n", ch);
780 /* Clear TC interrupt */
781 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2);
782 BUG_ON(1);
783 } else {
784 /* Enable powersave if transfer has finished */
785 if (!(readl(virtbase + COH901318_CX_STAT +
786 COH901318_CX_STAT_SPACING*ch) &
787 COH901318_CX_STAT_ENABLED)) {
788 enable_powersave(cohc);
789 }
790 /* Must clear TC interrupt before calling
791 * dma_tc_handle
792 * in case tc_handle initate a new dma job
793 */
794 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2);
795
796 dma_tc_handle(cohc);
797 }
798 }
799 spin_unlock(&cohc->lock);
800 }
801
802 return IRQ_HANDLED;
803}
804
805static int coh901318_alloc_chan_resources(struct dma_chan *chan)
806{
807 struct coh901318_chan *cohc = to_coh901318_chan(chan);
808
809 dev_vdbg(COHC_2_DEV(cohc), "[%s] DMA channel %d\n",
810 __func__, cohc->id);
811
812 if (chan->client_count > 1)
813 return -EBUSY;
814
815 coh901318_config(cohc, NULL);
816
817 cohc->allocated = 1;
818 cohc->completed = chan->cookie = 1;
819
820 return 1;
821}
822
823static void
824coh901318_free_chan_resources(struct dma_chan *chan)
825{
826 struct coh901318_chan *cohc = to_coh901318_chan(chan);
827 int channel = cohc->id;
828 unsigned long flags;
829
830 spin_lock_irqsave(&cohc->lock, flags);
831
832 /* Disable HW */
833 writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CFG +
834 COH901318_CX_CFG_SPACING*channel);
835 writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CTRL +
836 COH901318_CX_CTRL_SPACING*channel);
837
838 cohc->allocated = 0;
839
840 spin_unlock_irqrestore(&cohc->lock, flags);
841
842 chan->device->device_terminate_all(chan);
843}
844
845
846static dma_cookie_t
847coh901318_tx_submit(struct dma_async_tx_descriptor *tx)
848{
849 struct coh901318_desc *cohd = container_of(tx, struct coh901318_desc,
850 desc);
851 struct coh901318_chan *cohc = to_coh901318_chan(tx->chan);
852 unsigned long flags;
853
854 spin_lock_irqsave(&cohc->lock, flags);
855
856 tx->cookie = coh901318_assign_cookie(cohc, cohd);
857
858 coh901318_desc_queue(cohc, cohd);
859
860 spin_unlock_irqrestore(&cohc->lock, flags);
861
862 return tx->cookie;
863}
864
865static struct dma_async_tx_descriptor *
866coh901318_prep_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
867 size_t size, unsigned long flags)
868{
869 struct coh901318_lli *data;
870 struct coh901318_desc *cohd;
871 unsigned long flg;
872 struct coh901318_chan *cohc = to_coh901318_chan(chan);
873 int lli_len;
874 u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
875
876 spin_lock_irqsave(&cohc->lock, flg);
877
878 dev_vdbg(COHC_2_DEV(cohc),
879 "[%s] channel %d src 0x%x dest 0x%x size %d\n",
880 __func__, cohc->id, src, dest, size);
881
882 if (flags & DMA_PREP_INTERRUPT)
883 /* Trigger interrupt after last lli */
884 ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE;
885
886 lli_len = size >> MAX_DMA_PACKET_SIZE_SHIFT;
887 if ((lli_len << MAX_DMA_PACKET_SIZE_SHIFT) < size)
888 lli_len++;
889
890 data = coh901318_lli_alloc(&cohc->base->pool, lli_len);
891
892 if (data == NULL)
893 goto err;
894
895 cohd = coh901318_desc_get(cohc);
896 cohd->sg = NULL;
897 cohd->sg_len = 0;
898 cohd->data = data;
899
900 cohd->pending_irqs =
901 coh901318_lli_fill_memcpy(
902 &cohc->base->pool, data, src, size, dest,
903 cohc_chan_param(cohc)->ctrl_lli_chained,
904 ctrl_last);
905 cohd->flags = flags;
906
907 COH_DBG(coh901318_list_print(cohc, data));
908
909 dma_async_tx_descriptor_init(&cohd->desc, chan);
910
911 cohd->desc.tx_submit = coh901318_tx_submit;
912
913 spin_unlock_irqrestore(&cohc->lock, flg);
914
915 return &cohd->desc;
916 err:
917 spin_unlock_irqrestore(&cohc->lock, flg);
918 return NULL;
919}
920
921static struct dma_async_tx_descriptor *
922coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
923 unsigned int sg_len, enum dma_data_direction direction,
924 unsigned long flags)
925{
926 struct coh901318_chan *cohc = to_coh901318_chan(chan);
927 struct coh901318_lli *data;
928 struct coh901318_desc *cohd;
929 struct scatterlist *sg;
930 int len = 0;
931 int size;
932 int i;
933 u32 ctrl_chained = cohc_chan_param(cohc)->ctrl_lli_chained;
934 u32 ctrl = cohc_chan_param(cohc)->ctrl_lli;
935 u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
936 unsigned long flg;
937
938 if (!sgl)
939 goto out;
940 if (sgl->length == 0)
941 goto out;
942
943 spin_lock_irqsave(&cohc->lock, flg);
944
945 dev_vdbg(COHC_2_DEV(cohc), "[%s] sg_len %d dir %d\n",
946 __func__, sg_len, direction);
947
948 if (flags & DMA_PREP_INTERRUPT)
949 /* Trigger interrupt after last lli */
950 ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE;
951
952 cohd = coh901318_desc_get(cohc);
953 cohd->sg = NULL;
954 cohd->sg_len = 0;
955 cohd->dir = direction;
956
957 if (direction == DMA_TO_DEVICE) {
958 u32 tx_flags = COH901318_CX_CTRL_PRDD_SOURCE |
959 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE;
960
961 ctrl_chained |= tx_flags;
962 ctrl_last |= tx_flags;
963 ctrl |= tx_flags;
964 } else if (direction == DMA_FROM_DEVICE) {
965 u32 rx_flags = COH901318_CX_CTRL_PRDD_DEST |
966 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE;
967
968 ctrl_chained |= rx_flags;
969 ctrl_last |= rx_flags;
970 ctrl |= rx_flags;
971 } else
972 goto err_direction;
973
974 dma_async_tx_descriptor_init(&cohd->desc, chan);
975
976 cohd->desc.tx_submit = coh901318_tx_submit;
977
978
979 /* The dma only supports transmitting packages up to
980 * MAX_DMA_PACKET_SIZE. Calculate to total number of
981 * dma elemts required to send the entire sg list
982 */
983 for_each_sg(sgl, sg, sg_len, i) {
984 unsigned int factor;
985 size = sg_dma_len(sg);
986
987 if (size <= MAX_DMA_PACKET_SIZE) {
988 len++;
989 continue;
990 }
991
992 factor = size >> MAX_DMA_PACKET_SIZE_SHIFT;
993 if ((factor << MAX_DMA_PACKET_SIZE_SHIFT) < size)
994 factor++;
995
996 len += factor;
997 }
998
999 data = coh901318_lli_alloc(&cohc->base->pool, len);
1000
1001 if (data == NULL)
1002 goto err_dma_alloc;
1003
1004 /* initiate allocated data list */
1005 cohd->pending_irqs =
1006 coh901318_lli_fill_sg(&cohc->base->pool, data, sgl, sg_len,
1007 cohc_dev_addr(cohc),
1008 ctrl_chained,
1009 ctrl,
1010 ctrl_last,
1011 direction, COH901318_CX_CTRL_TC_IRQ_ENABLE);
1012 cohd->data = data;
1013
1014 cohd->flags = flags;
1015
1016 COH_DBG(coh901318_list_print(cohc, data));
1017
1018 spin_unlock_irqrestore(&cohc->lock, flg);
1019
1020 return &cohd->desc;
1021 err_dma_alloc:
1022 err_direction:
1023 coh901318_desc_remove(cohd);
1024 coh901318_desc_free(cohc, cohd);
1025 spin_unlock_irqrestore(&cohc->lock, flg);
1026 out:
1027 return NULL;
1028}
1029
1030static enum dma_status
1031coh901318_is_tx_complete(struct dma_chan *chan,
1032 dma_cookie_t cookie, dma_cookie_t *done,
1033 dma_cookie_t *used)
1034{
1035 struct coh901318_chan *cohc = to_coh901318_chan(chan);
1036 dma_cookie_t last_used;
1037 dma_cookie_t last_complete;
1038 int ret;
1039
1040 last_complete = cohc->completed;
1041 last_used = chan->cookie;
1042
1043 ret = dma_async_is_complete(cookie, last_complete, last_used);
1044
1045 if (done)
1046 *done = last_complete;
1047 if (used)
1048 *used = last_used;
1049
1050 return ret;
1051}
1052
1053static void
1054coh901318_issue_pending(struct dma_chan *chan)
1055{
1056 struct coh901318_chan *cohc = to_coh901318_chan(chan);
1057 unsigned long flags;
1058
1059 spin_lock_irqsave(&cohc->lock, flags);
1060
1061 /* Busy means that pending jobs are already being processed */
1062 if (!cohc->busy)
1063 coh901318_queue_start(cohc);
1064
1065 spin_unlock_irqrestore(&cohc->lock, flags);
1066}
1067
1068static void
1069coh901318_terminate_all(struct dma_chan *chan)
1070{
1071 unsigned long flags;
1072 struct coh901318_chan *cohc = to_coh901318_chan(chan);
1073 struct coh901318_desc *cohd;
1074 void __iomem *virtbase = cohc->base->virtbase;
1075
1076 coh901318_stop(chan);
1077
1078 spin_lock_irqsave(&cohc->lock, flags);
1079
1080 /* Clear any pending BE or TC interrupt */
1081 if (cohc->id < 32) {
1082 writel(1 << cohc->id, virtbase + COH901318_BE_INT_CLEAR1);
1083 writel(1 << cohc->id, virtbase + COH901318_TC_INT_CLEAR1);
1084 } else {
1085 writel(1 << (cohc->id - 32), virtbase +
1086 COH901318_BE_INT_CLEAR2);
1087 writel(1 << (cohc->id - 32), virtbase +
1088 COH901318_TC_INT_CLEAR2);
1089 }
1090
1091 enable_powersave(cohc);
1092
1093 while ((cohd = coh901318_first_active_get(cohc))) {
1094 /* release the lli allocation*/
1095 coh901318_lli_free(&cohc->base->pool, &cohd->data);
1096
1097 coh901318_desc_remove(cohd);
1098
1099 /* return desc to free-list */
1100 coh901318_desc_free(cohc, cohd);
1101 }
1102
1103 while ((cohd = coh901318_first_queued(cohc))) {
1104 /* release the lli allocation*/
1105 coh901318_lli_free(&cohc->base->pool, &cohd->data);
1106
1107 coh901318_desc_remove(cohd);
1108
1109 /* return desc to free-list */
1110 coh901318_desc_free(cohc, cohd);
1111 }
1112
1113
1114 cohc->nbr_active_done = 0;
1115 cohc->busy = 0;
1116 cohc->pending_irqs = 0;
1117
1118 spin_unlock_irqrestore(&cohc->lock, flags);
1119}
1120void coh901318_base_init(struct dma_device *dma, const int *pick_chans,
1121 struct coh901318_base *base)
1122{
1123 int chans_i;
1124 int i = 0;
1125 struct coh901318_chan *cohc;
1126
1127 INIT_LIST_HEAD(&dma->channels);
1128
1129 for (chans_i = 0; pick_chans[chans_i] != -1; chans_i += 2) {
1130 for (i = pick_chans[chans_i]; i <= pick_chans[chans_i+1]; i++) {
1131 cohc = &base->chans[i];
1132
1133 cohc->base = base;
1134 cohc->chan.device = dma;
1135 cohc->id = i;
1136
1137 /* TODO: do we really need this lock if only one
1138 * client is connected to each channel?
1139 */
1140
1141 spin_lock_init(&cohc->lock);
1142
1143 cohc->pending_irqs = 0;
1144 cohc->nbr_active_done = 0;
1145 cohc->busy = 0;
1146 INIT_LIST_HEAD(&cohc->free);
1147 INIT_LIST_HEAD(&cohc->active);
1148 INIT_LIST_HEAD(&cohc->queue);
1149
1150 tasklet_init(&cohc->tasklet, dma_tasklet,
1151 (unsigned long) cohc);
1152
1153 list_add_tail(&cohc->chan.device_node,
1154 &dma->channels);
1155 }
1156 }
1157}
1158
1159static int __init coh901318_probe(struct platform_device *pdev)
1160{
1161 int err = 0;
1162 struct coh901318_platform *pdata;
1163 struct coh901318_base *base;
1164 int irq;
1165 struct resource *io;
1166
1167 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1168 if (!io)
1169 goto err_get_resource;
1170
1171 /* Map DMA controller registers to virtual memory */
1172 if (request_mem_region(io->start,
1173 resource_size(io),
1174 pdev->dev.driver->name) == NULL) {
1175 err = -EBUSY;
1176 goto err_request_mem;
1177 }
1178
1179 pdata = pdev->dev.platform_data;
1180 if (!pdata)
1181 goto err_no_platformdata;
1182
1183 base = kmalloc(ALIGN(sizeof(struct coh901318_base), 4) +
1184 pdata->max_channels *
1185 sizeof(struct coh901318_chan),
1186 GFP_KERNEL);
1187 if (!base)
1188 goto err_alloc_coh_dma_channels;
1189
1190 base->chans = ((void *)base) + ALIGN(sizeof(struct coh901318_base), 4);
1191
1192 base->virtbase = ioremap(io->start, resource_size(io));
1193 if (!base->virtbase) {
1194 err = -ENOMEM;
1195 goto err_no_ioremap;
1196 }
1197
1198 base->dev = &pdev->dev;
1199 base->platform = pdata;
1200 spin_lock_init(&base->pm.lock);
1201 base->pm.started_channels = 0;
1202
1203 COH901318_DEBUGFS_ASSIGN(debugfs_dma_base, base);
1204
1205 platform_set_drvdata(pdev, base);
1206
1207 irq = platform_get_irq(pdev, 0);
1208 if (irq < 0)
1209 goto err_no_irq;
1210
1211 err = request_irq(irq, dma_irq_handler, IRQF_DISABLED,
1212 "coh901318", base);
1213 if (err) {
1214 dev_crit(&pdev->dev,
1215 "Cannot allocate IRQ for DMA controller!\n");
1216 goto err_request_irq;
1217 }
1218
1219 err = coh901318_pool_create(&base->pool, &pdev->dev,
1220 sizeof(struct coh901318_lli),
1221 32);
1222 if (err)
1223 goto err_pool_create;
1224
1225 /* init channels for device transfers */
1226 coh901318_base_init(&base->dma_slave, base->platform->chans_slave,
1227 base);
1228
1229 dma_cap_zero(base->dma_slave.cap_mask);
1230 dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
1231
1232 base->dma_slave.device_alloc_chan_resources = coh901318_alloc_chan_resources;
1233 base->dma_slave.device_free_chan_resources = coh901318_free_chan_resources;
1234 base->dma_slave.device_prep_slave_sg = coh901318_prep_slave_sg;
1235 base->dma_slave.device_is_tx_complete = coh901318_is_tx_complete;
1236 base->dma_slave.device_issue_pending = coh901318_issue_pending;
1237 base->dma_slave.device_terminate_all = coh901318_terminate_all;
1238 base->dma_slave.dev = &pdev->dev;
1239
1240 err = dma_async_device_register(&base->dma_slave);
1241
1242 if (err)
1243 goto err_register_slave;
1244
1245 /* init channels for memcpy */
1246 coh901318_base_init(&base->dma_memcpy, base->platform->chans_memcpy,
1247 base);
1248
1249 dma_cap_zero(base->dma_memcpy.cap_mask);
1250 dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
1251
1252 base->dma_memcpy.device_alloc_chan_resources = coh901318_alloc_chan_resources;
1253 base->dma_memcpy.device_free_chan_resources = coh901318_free_chan_resources;
1254 base->dma_memcpy.device_prep_dma_memcpy = coh901318_prep_memcpy;
1255 base->dma_memcpy.device_is_tx_complete = coh901318_is_tx_complete;
1256 base->dma_memcpy.device_issue_pending = coh901318_issue_pending;
1257 base->dma_memcpy.device_terminate_all = coh901318_terminate_all;
1258 base->dma_memcpy.dev = &pdev->dev;
1259 err = dma_async_device_register(&base->dma_memcpy);
1260
1261 if (err)
1262 goto err_register_memcpy;
1263
1264 dev_dbg(&pdev->dev, "Initialized COH901318 DMA on virtual base 0x%08x\n",
1265 (u32) base->virtbase);
1266
1267 return err;
1268
1269 err_register_memcpy:
1270 dma_async_device_unregister(&base->dma_slave);
1271 err_register_slave:
1272 coh901318_pool_destroy(&base->pool);
1273 err_pool_create:
1274 free_irq(platform_get_irq(pdev, 0), base);
1275 err_request_irq:
1276 err_no_irq:
1277 iounmap(base->virtbase);
1278 err_no_ioremap:
1279 kfree(base);
1280 err_alloc_coh_dma_channels:
1281 err_no_platformdata:
1282 release_mem_region(pdev->resource->start,
1283 resource_size(pdev->resource));
1284 err_request_mem:
1285 err_get_resource:
1286 return err;
1287}
1288
1289static int __exit coh901318_remove(struct platform_device *pdev)
1290{
1291 struct coh901318_base *base = platform_get_drvdata(pdev);
1292
1293 dma_async_device_unregister(&base->dma_memcpy);
1294 dma_async_device_unregister(&base->dma_slave);
1295 coh901318_pool_destroy(&base->pool);
1296 free_irq(platform_get_irq(pdev, 0), base);
1297 kfree(base);
1298 iounmap(base->virtbase);
1299 release_mem_region(pdev->resource->start,
1300 resource_size(pdev->resource));
1301 return 0;
1302}
1303
1304
1305static struct platform_driver coh901318_driver = {
1306 .remove = __exit_p(coh901318_remove),
1307 .driver = {
1308 .name = "coh901318",
1309 },
1310};
1311
1312int __init coh901318_init(void)
1313{
1314 return platform_driver_probe(&coh901318_driver, coh901318_probe);
1315}
1316subsys_initcall(coh901318_init);
1317
1318void __exit coh901318_exit(void)
1319{
1320 platform_driver_unregister(&coh901318_driver);
1321}
1322module_exit(coh901318_exit);
1323
1324MODULE_LICENSE("GPL");
1325MODULE_AUTHOR("Per Friden");
diff --git a/drivers/dma/coh901318_lli.c b/drivers/dma/coh901318_lli.c
new file mode 100644
index 000000000000..f5120f238a4d
--- /dev/null
+++ b/drivers/dma/coh901318_lli.c
@@ -0,0 +1,318 @@
1/*
2 * driver/dma/coh901318_lli.c
3 *
4 * Copyright (C) 2007-2009 ST-Ericsson
5 * License terms: GNU General Public License (GPL) version 2
6 * Support functions for handling lli for dma
7 * Author: Per Friden <per.friden@stericsson.com>
8 */
9
10#include <linux/dma-mapping.h>
11#include <linux/spinlock.h>
12#include <linux/dmapool.h>
13#include <linux/memory.h>
14#include <mach/coh901318.h>
15
16#include "coh901318_lli.h"
17
18#if (defined(CONFIG_DEBUG_FS) && defined(CONFIG_U300_DEBUG))
19#define DEBUGFS_POOL_COUNTER_RESET(pool) (pool->debugfs_pool_counter = 0)
20#define DEBUGFS_POOL_COUNTER_ADD(pool, add) (pool->debugfs_pool_counter += add)
21#else
22#define DEBUGFS_POOL_COUNTER_RESET(pool)
23#define DEBUGFS_POOL_COUNTER_ADD(pool, add)
24#endif
25
26static struct coh901318_lli *
27coh901318_lli_next(struct coh901318_lli *data)
28{
29 if (data == NULL || data->link_addr == 0)
30 return NULL;
31
32 return (struct coh901318_lli *) data->virt_link_addr;
33}
34
35int coh901318_pool_create(struct coh901318_pool *pool,
36 struct device *dev,
37 size_t size, size_t align)
38{
39 spin_lock_init(&pool->lock);
40 pool->dev = dev;
41 pool->dmapool = dma_pool_create("lli_pool", dev, size, align, 0);
42
43 DEBUGFS_POOL_COUNTER_RESET(pool);
44 return 0;
45}
46
47int coh901318_pool_destroy(struct coh901318_pool *pool)
48{
49
50 dma_pool_destroy(pool->dmapool);
51 return 0;
52}
53
54struct coh901318_lli *
55coh901318_lli_alloc(struct coh901318_pool *pool, unsigned int len)
56{
57 int i;
58 struct coh901318_lli *head;
59 struct coh901318_lli *lli;
60 struct coh901318_lli *lli_prev;
61 dma_addr_t phy;
62
63 if (len == 0)
64 goto err;
65
66 spin_lock(&pool->lock);
67
68 head = dma_pool_alloc(pool->dmapool, GFP_NOWAIT, &phy);
69
70 if (head == NULL)
71 goto err;
72
73 DEBUGFS_POOL_COUNTER_ADD(pool, 1);
74
75 lli = head;
76 lli->phy_this = phy;
77
78 for (i = 1; i < len; i++) {
79 lli_prev = lli;
80
81 lli = dma_pool_alloc(pool->dmapool, GFP_NOWAIT, &phy);
82
83 if (lli == NULL)
84 goto err_clean_up;
85
86 DEBUGFS_POOL_COUNTER_ADD(pool, 1);
87 lli->phy_this = phy;
88
89 lli_prev->link_addr = phy;
90 lli_prev->virt_link_addr = lli;
91 }
92
93 lli->link_addr = 0x00000000U;
94
95 spin_unlock(&pool->lock);
96
97 return head;
98
99 err:
100 spin_unlock(&pool->lock);
101 return NULL;
102
103 err_clean_up:
104 lli_prev->link_addr = 0x00000000U;
105 spin_unlock(&pool->lock);
106 coh901318_lli_free(pool, &head);
107 return NULL;
108}
109
110void coh901318_lli_free(struct coh901318_pool *pool,
111 struct coh901318_lli **lli)
112{
113 struct coh901318_lli *l;
114 struct coh901318_lli *next;
115
116 if (lli == NULL)
117 return;
118
119 l = *lli;
120
121 if (l == NULL)
122 return;
123
124 spin_lock(&pool->lock);
125
126 while (l->link_addr) {
127 next = l->virt_link_addr;
128 dma_pool_free(pool->dmapool, l, l->phy_this);
129 DEBUGFS_POOL_COUNTER_ADD(pool, -1);
130 l = next;
131 }
132 dma_pool_free(pool->dmapool, l, l->phy_this);
133 DEBUGFS_POOL_COUNTER_ADD(pool, -1);
134
135 spin_unlock(&pool->lock);
136 *lli = NULL;
137}
138
139int
140coh901318_lli_fill_memcpy(struct coh901318_pool *pool,
141 struct coh901318_lli *lli,
142 dma_addr_t source, unsigned int size,
143 dma_addr_t destination, u32 ctrl_chained,
144 u32 ctrl_eom)
145{
146 int s = size;
147 dma_addr_t src = source;
148 dma_addr_t dst = destination;
149
150 lli->src_addr = src;
151 lli->dst_addr = dst;
152
153 while (lli->link_addr) {
154 lli->control = ctrl_chained | MAX_DMA_PACKET_SIZE;
155 lli->src_addr = src;
156 lli->dst_addr = dst;
157
158 s -= MAX_DMA_PACKET_SIZE;
159 lli = coh901318_lli_next(lli);
160
161 src += MAX_DMA_PACKET_SIZE;
162 dst += MAX_DMA_PACKET_SIZE;
163 }
164
165 lli->control = ctrl_eom | s;
166 lli->src_addr = src;
167 lli->dst_addr = dst;
168
169 /* One irq per single transfer */
170 return 1;
171}
172
173int
174coh901318_lli_fill_single(struct coh901318_pool *pool,
175 struct coh901318_lli *lli,
176 dma_addr_t buf, unsigned int size,
177 dma_addr_t dev_addr, u32 ctrl_chained, u32 ctrl_eom,
178 enum dma_data_direction dir)
179{
180 int s = size;
181 dma_addr_t src;
182 dma_addr_t dst;
183
184
185 if (dir == DMA_TO_DEVICE) {
186 src = buf;
187 dst = dev_addr;
188
189 } else if (dir == DMA_FROM_DEVICE) {
190
191 src = dev_addr;
192 dst = buf;
193 } else {
194 return -EINVAL;
195 }
196
197 while (lli->link_addr) {
198 size_t block_size = MAX_DMA_PACKET_SIZE;
199 lli->control = ctrl_chained | MAX_DMA_PACKET_SIZE;
200
201 /* If we are on the next-to-final block and there will
202 * be less than half a DMA packet left for the last
203 * block, then we want to make this block a little
204 * smaller to balance the sizes. This is meant to
205 * avoid too small transfers if the buffer size is
206 * (MAX_DMA_PACKET_SIZE*N + 1) */
207 if (s < (MAX_DMA_PACKET_SIZE + MAX_DMA_PACKET_SIZE/2))
208 block_size = MAX_DMA_PACKET_SIZE/2;
209
210 s -= block_size;
211 lli->src_addr = src;
212 lli->dst_addr = dst;
213
214 lli = coh901318_lli_next(lli);
215
216 if (dir == DMA_TO_DEVICE)
217 src += block_size;
218 else if (dir == DMA_FROM_DEVICE)
219 dst += block_size;
220 }
221
222 lli->control = ctrl_eom | s;
223 lli->src_addr = src;
224 lli->dst_addr = dst;
225
226 /* One irq per single transfer */
227 return 1;
228}
229
230int
231coh901318_lli_fill_sg(struct coh901318_pool *pool,
232 struct coh901318_lli *lli,
233 struct scatterlist *sgl, unsigned int nents,
234 dma_addr_t dev_addr, u32 ctrl_chained, u32 ctrl,
235 u32 ctrl_last,
236 enum dma_data_direction dir, u32 ctrl_irq_mask)
237{
238 int i;
239 struct scatterlist *sg;
240 u32 ctrl_sg;
241 dma_addr_t src = 0;
242 dma_addr_t dst = 0;
243 int nbr_of_irq = 0;
244 u32 bytes_to_transfer;
245 u32 elem_size;
246
247 if (lli == NULL)
248 goto err;
249
250 spin_lock(&pool->lock);
251
252 if (dir == DMA_TO_DEVICE)
253 dst = dev_addr;
254 else if (dir == DMA_FROM_DEVICE)
255 src = dev_addr;
256 else
257 goto err;
258
259 for_each_sg(sgl, sg, nents, i) {
260 if (sg_is_chain(sg)) {
261 /* sg continues to the next sg-element don't
262 * send ctrl_finish until the last
263 * sg-element in the chain
264 */
265 ctrl_sg = ctrl_chained;
266 } else if (i == nents - 1)
267 ctrl_sg = ctrl_last;
268 else
269 ctrl_sg = ctrl ? ctrl : ctrl_last;
270
271
272 if ((ctrl_sg & ctrl_irq_mask))
273 nbr_of_irq++;
274
275 if (dir == DMA_TO_DEVICE)
276 /* increment source address */
277 src = sg_dma_address(sg);
278 else
279 /* increment destination address */
280 dst = sg_dma_address(sg);
281
282 bytes_to_transfer = sg_dma_len(sg);
283
284 while (bytes_to_transfer) {
285 u32 val;
286
287 if (bytes_to_transfer > MAX_DMA_PACKET_SIZE) {
288 elem_size = MAX_DMA_PACKET_SIZE;
289 val = ctrl_chained;
290 } else {
291 elem_size = bytes_to_transfer;
292 val = ctrl_sg;
293 }
294
295 lli->control = val | elem_size;
296 lli->src_addr = src;
297 lli->dst_addr = dst;
298
299 if (dir == DMA_FROM_DEVICE)
300 dst += elem_size;
301 else
302 src += elem_size;
303
304 BUG_ON(lli->link_addr & 3);
305
306 bytes_to_transfer -= elem_size;
307 lli = coh901318_lli_next(lli);
308 }
309
310 }
311 spin_unlock(&pool->lock);
312
313 /* There can be many IRQs per sg transfer */
314 return nbr_of_irq;
315 err:
316 spin_unlock(&pool->lock);
317 return -EINVAL;
318}
diff --git a/drivers/dma/coh901318_lli.h b/drivers/dma/coh901318_lli.h
new file mode 100644
index 000000000000..7bf713b79c6b
--- /dev/null
+++ b/drivers/dma/coh901318_lli.h
@@ -0,0 +1,124 @@
1/*
2 * driver/dma/coh901318_lli.h
3 *
4 * Copyright (C) 2007-2009 ST-Ericsson
5 * License terms: GNU General Public License (GPL) version 2
6 * Support functions for handling lli for coh901318
7 * Author: Per Friden <per.friden@stericsson.com>
8 */
9
10#ifndef COH901318_LLI_H
11#define COH901318_LLI_H
12
13#include <mach/coh901318.h>
14
15struct device;
16
17struct coh901318_pool {
18 spinlock_t lock;
19 struct dma_pool *dmapool;
20 struct device *dev;
21
22#ifdef CONFIG_DEBUG_FS
23 int debugfs_pool_counter;
24#endif
25};
26
27struct device;
28/**
29 * coh901318_pool_create() - Creates an dma pool for lli:s
30 * @pool: pool handle
31 * @dev: dma device
32 * @lli_nbr: number of lli:s in the pool
33 * @algin: adress alignemtn of lli:s
34 * returns 0 on success otherwise none zero
35 */
36int coh901318_pool_create(struct coh901318_pool *pool,
37 struct device *dev,
38 size_t lli_nbr, size_t align);
39
40/**
41 * coh901318_pool_destroy() - Destroys the dma pool
42 * @pool: pool handle
43 * returns 0 on success otherwise none zero
44 */
45int coh901318_pool_destroy(struct coh901318_pool *pool);
46
47/**
48 * coh901318_lli_alloc() - Allocates a linked list
49 *
50 * @pool: pool handle
51 * @len: length to list
52 * return: none NULL if success otherwise NULL
53 */
54struct coh901318_lli *
55coh901318_lli_alloc(struct coh901318_pool *pool,
56 unsigned int len);
57
58/**
59 * coh901318_lli_free() - Returns the linked list items to the pool
60 * @pool: pool handle
61 * @lli: reference to lli pointer to be freed
62 */
63void coh901318_lli_free(struct coh901318_pool *pool,
64 struct coh901318_lli **lli);
65
66/**
67 * coh901318_lli_fill_memcpy() - Prepares the lli:s for dma memcpy
68 * @pool: pool handle
69 * @lli: allocated lli
70 * @src: src address
71 * @size: transfer size
72 * @dst: destination address
73 * @ctrl_chained: ctrl for chained lli
74 * @ctrl_last: ctrl for the last lli
75 * returns number of CPU interrupts for the lli, negative on error.
76 */
77int
78coh901318_lli_fill_memcpy(struct coh901318_pool *pool,
79 struct coh901318_lli *lli,
80 dma_addr_t src, unsigned int size,
81 dma_addr_t dst, u32 ctrl_chained, u32 ctrl_last);
82
83/**
84 * coh901318_lli_fill_single() - Prepares the lli:s for dma single transfer
85 * @pool: pool handle
86 * @lli: allocated lli
87 * @buf: transfer buffer
88 * @size: transfer size
89 * @dev_addr: address of periphal
90 * @ctrl_chained: ctrl for chained lli
91 * @ctrl_last: ctrl for the last lli
92 * @dir: direction of transfer (to or from device)
93 * returns number of CPU interrupts for the lli, negative on error.
94 */
95int
96coh901318_lli_fill_single(struct coh901318_pool *pool,
97 struct coh901318_lli *lli,
98 dma_addr_t buf, unsigned int size,
99 dma_addr_t dev_addr, u32 ctrl_chained, u32 ctrl_last,
100 enum dma_data_direction dir);
101
102/**
103 * coh901318_lli_fill_single() - Prepares the lli:s for dma scatter list transfer
104 * @pool: pool handle
105 * @lli: allocated lli
106 * @sg: scatter gather list
107 * @nents: number of entries in sg
108 * @dev_addr: address of periphal
109 * @ctrl_chained: ctrl for chained lli
110 * @ctrl: ctrl of middle lli
111 * @ctrl_last: ctrl for the last lli
112 * @dir: direction of transfer (to or from device)
113 * @ctrl_irq_mask: ctrl mask for CPU interrupt
114 * returns number of CPU interrupts for the lli, negative on error.
115 */
116int
117coh901318_lli_fill_sg(struct coh901318_pool *pool,
118 struct coh901318_lli *lli,
119 struct scatterlist *sg, unsigned int nents,
120 dma_addr_t dev_addr, u32 ctrl_chained,
121 u32 ctrl, u32 ctrl_last,
122 enum dma_data_direction dir, u32 ctrl_irq_mask);
123
124#endif /* COH901318_LLI_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-19 22:33:07 -0400