ARM: v6k: select TLS register code according to V6 variants

If CONFIG_CPU_V6 is enabled, we may or may not have the TLS register.
Use the conditional code which copes with this variability.  Otherwise,
if CONFIG_CPU_32v6K is set, we know we have the TLS register on all
supported CPUs, so use it unconditionally.

Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Sourav Poddar <sourav.poddar@ti.com>
Tested-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 5 insertions, 6 deletions

diff --git a/arch/arm/include/asm/tls.h b/arch/arm/include/asm/tls.h
index e71d6ff8d104..60843eb0f61c 100644
--- a/arch/arm/include/asm/tls.h
+++ b/arch/arm/include/asm/tls.h
@@ -28,15 +28,14 @@
 #define tls_emu         1
 #define has_tls_reg             1
 #define set_tls         set_tls_none
-#elif __LINUX_ARM_ARCH__ >= 7 ||                                        \
-        (__LINUX_ARM_ARCH__ == 6 && defined(CONFIG_CPU_32v6K))
-#define tls_emu         0
-#define has_tls_reg             1
-#define set_tls         set_tls_v6k
-#elif __LINUX_ARM_ARCH__ == 6
+#elif defined(CONFIG_CPU_V6)
 #define tls_emu         0
 #define has_tls_reg             (elf_hwcap & HWCAP_TLS)
 #define set_tls         set_tls_v6
+#elif defined(CONFIG_CPU_32v6K)
+#define tls_emu         0
+#define has_tls_reg             1
+#define set_tls         set_tls_v6k
 #else
 #define tls_emu         0
 #define has_tls_reg             0