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authorGreg Ungerer <gerg@uclinux.org>2009-05-19 00:52:40 -0400
committerGreg Ungerer <gerg@uclinux.org>2009-09-15 19:43:51 -0400
commit04b75b10dceadf937e3707ecc3dfccf6a076fd29 (patch)
tree87965d12b8f7eb622efd1d36bebd2a7b8a26452e
parentf9311f26434cea3e926f56ca2aa3e5740e962c72 (diff)
m68knommu: simplify ColdFire "timers" clock initialization
The ColdFire "timers" clock setup can be simplified. There is really no need for the flexible per-platform setup code. The clock interrupt can be hard defined per CPU platform (in CPU include files). This makes the actual timer code simpler. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
-rw-r--r--arch/m68k/include/asm/m5206sim.h13
-rw-r--r--arch/m68k/include/asm/m5249sim.h6
-rw-r--r--arch/m68k/include/asm/m5272sim.h5
-rw-r--r--arch/m68k/include/asm/m5307sim.h6
-rw-r--r--arch/m68k/include/asm/m5407sim.h5
-rw-r--r--arch/m68knommu/platform/5206/config.c25
-rw-r--r--arch/m68knommu/platform/5206e/config.c25
-rw-r--r--arch/m68knommu/platform/5249/config.c26
-rw-r--r--arch/m68knommu/platform/5272/config.c22
-rw-r--r--arch/m68knommu/platform/5307/config.c35
-rw-r--r--arch/m68knommu/platform/5407/config.c39
-rw-r--r--arch/m68knommu/platform/coldfire/timers.c17
12 files changed, 97 insertions, 127 deletions
diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h
index b50061aaf8f0..9c384e294af9 100644
--- a/arch/m68k/include/asm/m5206sim.h
+++ b/arch/m68k/include/asm/m5206sim.h
@@ -89,11 +89,18 @@
89#define MCFSIM_PADAT (MCF_MBAR + 0x1c9) /* Parallel Port Value (r/w) */ 89#define MCFSIM_PADAT (MCF_MBAR + 0x1c9) /* Parallel Port Value (r/w) */
90 90
91/* 91/*
92 * Define system peripheral IRQ usage.
93 */
94#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
95#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
96
97/*
92 * Generic GPIO 98 * Generic GPIO
93 */ 99 */
94#define MCFGPIO_PIN_MAX 8 100#define MCFGPIO_PIN_MAX 8
95#define MCFGPIO_IRQ_VECBASE -1 101#define MCFGPIO_IRQ_VECBASE -1
96#define MCFGPIO_IRQ_MAX -1 102#define MCFGPIO_IRQ_MAX -1
103
97/* 104/*
98 * Some symbol defines for the Parallel Port Pin Assignment Register 105 * Some symbol defines for the Parallel Port Pin Assignment Register
99 */ 106 */
@@ -117,11 +124,5 @@
117#define MCFSIM_DMA2ICR MCFSIM_ICR15 /* DMA 2 ICR */ 124#define MCFSIM_DMA2ICR MCFSIM_ICR15 /* DMA 2 ICR */
118#endif 125#endif
119 126
120/*
121 * Let the common interrupt handler code know that the ColdFire 5206*
122 * family of CPU's only has a 16bit sized IMR register.
123 */
124#define MCFSIM_IMR_IS_16BITS
125
126/****************************************************************************/ 127/****************************************************************************/
127#endif /* m5206sim_h */ 128#endif /* m5206sim_h */
diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h
index 36ed31bbf6cb..8d76a1930718 100644
--- a/arch/m68k/include/asm/m5249sim.h
+++ b/arch/m68k/include/asm/m5249sim.h
@@ -71,6 +71,12 @@
71#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ 71#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
72 72
73/* 73/*
74 * Define system peripheral IRQ usage.
75 */
76#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
77#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
78
79/*
74 * General purpose IO registers (in MBAR2). 80 * General purpose IO registers (in MBAR2).
75 */ 81 */
76#define MCFSIM2_GPIOREAD (MCF_MBAR2 + 0x000) /* GPIO read values */ 82#define MCFSIM2_GPIOREAD (MCF_MBAR2 + 0x000) /* GPIO read values */
diff --git a/arch/m68k/include/asm/m5272sim.h b/arch/m68k/include/asm/m5272sim.h
index 0665ba1a5d3c..469686ffc4af 100644
--- a/arch/m68k/include/asm/m5272sim.h
+++ b/arch/m68k/include/asm/m5272sim.h
@@ -73,6 +73,11 @@
73#define MCFSIM_PCDAT (MCF_MBAR + 0x96) /* Port C Data (r/w) */ 73#define MCFSIM_PCDAT (MCF_MBAR + 0x96) /* Port C Data (r/w) */
74#define MCFSIM_PDCNT (MCF_MBAR + 0x98) /* Port D Control (r/w) */ 74#define MCFSIM_PDCNT (MCF_MBAR + 0x98) /* Port D Control (r/w) */
75 75
76/*
77 * Define system peripheral IRQ usage.
78 */
79#define MCF_IRQ_TIMER 69 /* Timer0, Level 6 */
80#define MCF_IRQ_PROFILER 70 /* Timer1, Level 7 */
76 81
77/* 82/*
78 * Generic GPIO support 83 * Generic GPIO support
diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h
index 60946225699d..c6830e5b54ce 100644
--- a/arch/m68k/include/asm/m5307sim.h
+++ b/arch/m68k/include/asm/m5307sim.h
@@ -124,6 +124,7 @@
124#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */ 124#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
125#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ 125#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
126 126
127
127/* 128/*
128 * Some symbol defines for the Parallel Port Pin Assignment Register 129 * Some symbol defines for the Parallel Port Pin Assignment Register
129 */ 130 */
@@ -139,6 +140,11 @@
139#define IRQ3_LEVEL6 0x40 140#define IRQ3_LEVEL6 0x40
140#define IRQ1_LEVEL2 0x20 141#define IRQ1_LEVEL2 0x20
141 142
143/*
144 * Define system peripheral IRQ usage.
145 */
146#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
147#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
142 148
143/* 149/*
144 * Define the Cache register flags. 150 * Define the Cache register flags.
diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h
index 3c4bd5f08cde..c399abbf953c 100644
--- a/arch/m68k/include/asm/m5407sim.h
+++ b/arch/m68k/include/asm/m5407sim.h
@@ -111,6 +111,11 @@
111#define IRQ3_LEVEL6 0x40 111#define IRQ3_LEVEL6 0x40
112#define IRQ1_LEVEL2 0x20 112#define IRQ1_LEVEL2 0x20
113 113
114/*
115 * Define system peripheral IRQ usage.
116 */
117#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
118#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
114 119
115/* 120/*
116 * Define the Cache register flags. 121 * Define the Cache register flags.
diff --git a/arch/m68knommu/platform/5206/config.c b/arch/m68knommu/platform/5206/config.c
index 0dce2383320d..c1d24796ef2f 100644
--- a/arch/m68knommu/platform/5206/config.c
+++ b/arch/m68knommu/platform/5206/config.c
@@ -68,21 +68,17 @@ static void __init m5206_uarts_init(void)
68 68
69/***************************************************************************/ 69/***************************************************************************/
70 70
71void mcf_settimericr(unsigned int timer, unsigned int level) 71static void __init m5206_timers_init(void)
72{ 72{
73 volatile unsigned char *icrp; 73 /* Timer1 is always used as system timer */
74 unsigned int icr, imr; 74 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
75 75 MCF_MBAR + MCFSIM_TIMER1ICR);
76 if (timer <= 2) { 76
77 switch (timer) { 77#ifdef CONFIG_HIGHPROFILE
78 case 2: icr = MCFSIM_TIMER2ICR; imr = MCFINTC_TIMER2; break; 78 /* Timer2 is to be used as a high speed profile timer */
79 default: icr = MCFSIM_TIMER1ICR; imr = MCFINTC_TIMER1; break; 79 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
80 } 80 MCF_MBAR + MCFSIM_TIMER2ICR);
81 81#endif
82 icrp = (volatile unsigned char *) (MCF_MBAR + icr);
83 *icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3;
84 mcf_clrimr(imr);
85 }
86} 82}
87 83
88/***************************************************************************/ 84/***************************************************************************/
@@ -101,6 +97,7 @@ void m5206_cpu_reset(void)
101void __init config_BSP(char *commandp, int size) 97void __init config_BSP(char *commandp, int size)
102{ 98{
103 mach_reset = m5206_cpu_reset; 99 mach_reset = m5206_cpu_reset;
100 m5206_timers_init();
104} 101}
105 102
106/***************************************************************************/ 103/***************************************************************************/
diff --git a/arch/m68knommu/platform/5206e/config.c b/arch/m68knommu/platform/5206e/config.c
index 08ef7e268989..363296af2ee5 100644
--- a/arch/m68knommu/platform/5206e/config.c
+++ b/arch/m68knommu/platform/5206e/config.c
@@ -69,21 +69,17 @@ static void __init m5206e_uarts_init(void)
69 69
70/***************************************************************************/ 70/***************************************************************************/
71 71
72void mcf_settimericr(unsigned int timer, unsigned int level) 72static void __init m5206e_timers_init(void)
73{ 73{
74 volatile unsigned char *icrp; 74 /* Timer1 is always used as system timer */
75 unsigned int icr, imr; 75 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
76 76 MCF_MBAR + MCFSIM_TIMER1ICR);
77 if (timer <= 2) { 77
78 switch (timer) { 78#ifdef CONFIG_HIGHPROFILE
79 case 2: icr = MCFSIM_TIMER2ICR; imr = MCFINTC_TIMER2; break; 79 /* Timer2 is to be used as a high speed profile timer */
80 default: icr = MCFSIM_TIMER1ICR; imr = MCFINTC_TIMER1; break; 80 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
81 } 81 MCF_MBAR + MCFSIM_TIMER2ICR);
82 82#endif
83 icrp = (volatile unsigned char *) (MCF_MBAR + icr);
84 *icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3;
85 mcf_clrimr(imr);
86 }
87} 83}
88 84
89/***************************************************************************/ 85/***************************************************************************/
@@ -108,6 +104,7 @@ void __init config_BSP(char *commandp, int size)
108#endif /* CONFIG_NETtel */ 104#endif /* CONFIG_NETtel */
109 105
110 mach_reset = m5206e_cpu_reset; 106 mach_reset = m5206e_cpu_reset;
107 m5206e_timers_init();
111} 108}
112 109
113/***************************************************************************/ 110/***************************************************************************/
diff --git a/arch/m68knommu/platform/5249/config.c b/arch/m68knommu/platform/5249/config.c
index 7261a3d28adc..51202b1096cc 100644
--- a/arch/m68knommu/platform/5249/config.c
+++ b/arch/m68knommu/platform/5249/config.c
@@ -65,24 +65,19 @@ static void __init m5249_uarts_init(void)
65 m5249_uart_init_line(line, m5249_uart_platform[line].irq); 65 m5249_uart_init_line(line, m5249_uart_platform[line].irq);
66} 66}
67 67
68
69/***************************************************************************/ 68/***************************************************************************/
70 69
71void mcf_settimericr(unsigned int timer, unsigned int level) 70static void __init m5249_timers_init(void)
72{ 71{
73 volatile unsigned char *icrp; 72 /* Timer1 is always used as system timer */
74 unsigned int icr, imr; 73 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
75 74 MCF_MBAR + MCFSIM_TIMER1ICR);
76 if (timer <= 2) { 75
77 switch (timer) { 76#ifdef CONFIG_HIGHPROFILE
78 case 2: icr = MCFSIM_TIMER2ICR; imr = MCFINTC_TIMER2; break; 77 /* Timer2 is to be used as a high speed profile timer */
79 default: icr = MCFSIM_TIMER1ICR; imr = MCFINTC_TIMER1; break; 78 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
80 } 79 MCF_MBAR + MCFSIM_TIMER2ICR);
81 80#endif
82 icrp = (volatile unsigned char *) (MCF_MBAR + icr);
83 *icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3;
84 mcf_clrimr(imr);
85 }
86} 81}
87 82
88/***************************************************************************/ 83/***************************************************************************/
@@ -101,6 +96,7 @@ void m5249_cpu_reset(void)
101void __init config_BSP(char *commandp, int size) 96void __init config_BSP(char *commandp, int size)
102{ 97{
103 mach_reset = m5249_cpu_reset; 98 mach_reset = m5249_cpu_reset;
99 m5249_timers_init();
104} 100}
105 101
106/***************************************************************************/ 102/***************************************************************************/
diff --git a/arch/m68knommu/platform/5272/config.c b/arch/m68knommu/platform/5272/config.c
index 94a66c12c96a..b16add9aa4e5 100644
--- a/arch/m68knommu/platform/5272/config.c
+++ b/arch/m68knommu/platform/5272/config.c
@@ -20,12 +20,6 @@
20 20
21/***************************************************************************/ 21/***************************************************************************/
22 22
23extern unsigned int mcf_timervector;
24extern unsigned int mcf_profilevector;
25extern unsigned int mcf_timerlevel;
26
27/***************************************************************************/
28
29/* 23/*
30 * Some platforms need software versions of the GPIO data registers. 24 * Some platforms need software versions of the GPIO data registers.
31 */ 25 */
@@ -148,14 +142,15 @@ void mcf_disableall(void)
148 142
149/***************************************************************************/ 143/***************************************************************************/
150 144
151void mcf_settimericr(int timer, int level) 145static void __init m5272_timers_init(void)
152{ 146{
153 volatile unsigned long *icrp; 147 /* Timer1 @ level6 is always used as system timer */
148 writel((0x8 | 0x6) << ((4 - 1) * 4), MCF_MBAR + MCFSIM_ICR1);
154 149
155 if ((timer >= 1 ) && (timer <= 4)) { 150#ifdef CONFIG_HIGHPROFILE
156 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1); 151 /* Timer2 @ level7 is to be used as a high speed profile timer */
157 *icrp = (0x8 | level) << ((4 - timer) * 4); 152 writel((0x8 | 0x7) << ((4 - 2) * 4), MCF_MBAR + MCFSIM_ICR1);
158 } 153#endif
159} 154}
160 155
161/***************************************************************************/ 156/***************************************************************************/
@@ -195,9 +190,8 @@ void __init config_BSP(char *commandp, int size)
195 commandp[size-1] = 0; 190 commandp[size-1] = 0;
196#endif 191#endif
197 192
198 mcf_timervector = 69;
199 mcf_profilevector = 70;
200 mach_reset = m5272_cpu_reset; 193 mach_reset = m5272_cpu_reset;
194 m5272_timers_init();
201} 195}
202 196
203/***************************************************************************/ 197/***************************************************************************/
diff --git a/arch/m68knommu/platform/5307/config.c b/arch/m68knommu/platform/5307/config.c
index 3e27d2ec03f0..b711597ac8e1 100644
--- a/arch/m68knommu/platform/5307/config.c
+++ b/arch/m68knommu/platform/5307/config.c
@@ -21,12 +21,6 @@
21 21
22/***************************************************************************/ 22/***************************************************************************/
23 23
24extern unsigned int mcf_timervector;
25extern unsigned int mcf_profilevector;
26extern unsigned int mcf_timerlevel;
27
28/***************************************************************************/
29
30/* 24/*
31 * Some platforms need software versions of the GPIO data registers. 25 * Some platforms need software versions of the GPIO data registers.
32 */ 26 */
@@ -83,21 +77,17 @@ static void __init m5307_uarts_init(void)
83 77
84/***************************************************************************/ 78/***************************************************************************/
85 79
86void mcf_settimericr(unsigned int timer, unsigned int level) 80static void __init m5307_timers_init(void)
87{ 81{
88 volatile unsigned char *icrp; 82 /* Timer1 is always used as system timer */
89 unsigned int icr, imr; 83 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
90 84 MCF_MBAR + MCFSIM_TIMER1ICR);
91 if (timer <= 2) { 85
92 switch (timer) { 86#ifdef CONFIG_HIGHPROFILE
93 case 2: icr = MCFSIM_TIMER2ICR; imr = MCFINTC_TIMER2; break; 87 /* Timer2 is to be used as a high speed profile timer */
94 default: icr = MCFSIM_TIMER1ICR; imr = MCFINTC_TIMER1; break; 88 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
95 } 89 MCF_MBAR + MCFSIM_TIMER2ICR);
96 90#endif
97 icrp = (volatile unsigned char *) (MCF_MBAR + icr);
98 *icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3;
99 mcf_clrimr(imr);
100 }
101} 91}
102 92
103/***************************************************************************/ 93/***************************************************************************/
@@ -120,13 +110,10 @@ void __init config_BSP(char *commandp, int size)
120 /* Copy command line from FLASH to local buffer... */ 110 /* Copy command line from FLASH to local buffer... */
121 memcpy(commandp, (char *) 0xf0004000, size); 111 memcpy(commandp, (char *) 0xf0004000, size);
122 commandp[size-1] = 0; 112 commandp[size-1] = 0;
123 /* Different timer setup - to prevent device clash */
124 mcf_timervector = 30;
125 mcf_profilevector = 31;
126 mcf_timerlevel = 6;
127#endif 113#endif
128 114
129 mach_reset = m5307_cpu_reset; 115 mach_reset = m5307_cpu_reset;
116 m5307_timers_init();
130 117
131#ifdef CONFIG_BDM_DISABLE 118#ifdef CONFIG_BDM_DISABLE
132 /* 119 /*
diff --git a/arch/m68knommu/platform/5407/config.c b/arch/m68knommu/platform/5407/config.c
index 8aa94837bbc3..cc80029a4a00 100644
--- a/arch/m68knommu/platform/5407/config.c
+++ b/arch/m68knommu/platform/5407/config.c
@@ -20,12 +20,6 @@
20 20
21/***************************************************************************/ 21/***************************************************************************/
22 22
23extern unsigned int mcf_timervector;
24extern unsigned int mcf_profilevector;
25extern unsigned int mcf_timerlevel;
26
27/***************************************************************************/
28
29static struct mcf_platform_uart m5407_uart_platform[] = { 23static struct mcf_platform_uart m5407_uart_platform[] = {
30 { 24 {
31 .mapbase = MCF_MBAR + MCFUART_BASE1, 25 .mapbase = MCF_MBAR + MCFUART_BASE1,
@@ -59,6 +53,7 @@ static void __init m5407_uart_init_line(int line, int irq)
59 } else if (line == 1) { 53 } else if (line == 1) {
60 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR); 54 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
61 writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR); 55 writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR);
56 mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART2);
62 mcf_clrimr(MCFINTC_UART1); 57 mcf_clrimr(MCFINTC_UART1);
63 } 58 }
64} 59}
@@ -74,21 +69,17 @@ static void __init m5407_uarts_init(void)
74 69
75/***************************************************************************/ 70/***************************************************************************/
76 71
77void mcf_settimericr(unsigned int timer, unsigned int level) 72static void __init m5407_timers_init(void)
78{ 73{
79 volatile unsigned char *icrp; 74 /* Timer1 is always used as system timer */
80 unsigned int icr, imr; 75 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
81 76 MCF_MBAR + MCFSIM_TIMER1ICR);
82 if (timer <= 2) { 77
83 switch (timer) { 78#ifdef CONFIG_HIGHPROFILE
84 case 2: icr = MCFSIM_TIMER2ICR; imr = MCFINTC_TIMER2; break; 79 /* Timer2 is to be used as a high speed profile timer */
85 default: icr = MCFSIM_TIMER1ICR; imr = MCFINTC_TIMER1; break; 80 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
86 } 81 MCF_MBAR + MCFSIM_TIMER2ICR);
87 82#endif
88 icrp = (volatile unsigned char *) (MCF_MBAR + icr);
89 *icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3;
90 mcf_clrimr(imr);
91 }
92} 83}
93 84
94/***************************************************************************/ 85/***************************************************************************/
@@ -106,14 +97,8 @@ void m5407_cpu_reset(void)
106 97
107void __init config_BSP(char *commandp, int size) 98void __init config_BSP(char *commandp, int size)
108{ 99{
109#if defined(CONFIG_CLEOPATRA)
110 /* Different timer setup - to prevent device clash */
111 mcf_timervector = 30;
112 mcf_profilevector = 31;
113 mcf_timerlevel = 6;
114#endif
115
116 mach_reset = m5407_cpu_reset; 100 mach_reset = m5407_cpu_reset;
101 m5407_timers_init();
117} 102}
118 103
119/***************************************************************************/ 104/***************************************************************************/
diff --git a/arch/m68knommu/platform/coldfire/timers.c b/arch/m68knommu/platform/coldfire/timers.c
index 1ba8a3731653..77b0c17ce6ba 100644
--- a/arch/m68knommu/platform/coldfire/timers.c
+++ b/arch/m68knommu/platform/coldfire/timers.c
@@ -31,15 +31,6 @@
31#define TA(a) (MCF_MBAR + MCFTIMER_BASE1 + (a)) 31#define TA(a) (MCF_MBAR + MCFTIMER_BASE1 + (a))
32 32
33/* 33/*
34 * Default the timer and vector to use for ColdFire. Some ColdFire
35 * CPU's and some boards may want different. Their sub-architecture
36 * startup code (in config.c) can change these if they want.
37 */
38unsigned int mcf_timervector = 29;
39unsigned int mcf_profilevector = 31;
40unsigned int mcf_timerlevel = 5;
41
42/*
43 * These provide the underlying interrupt vector support. 34 * These provide the underlying interrupt vector support.
44 * Unfortunately it is a little different on each ColdFire. 35 * Unfortunately it is a little different on each ColdFire.
45 */ 36 */
@@ -107,7 +98,7 @@ static struct clocksource mcftmr_clk = {
107 98
108void hw_timer_init(void) 99void hw_timer_init(void)
109{ 100{
110 setup_irq(mcf_timervector, &mcftmr_timer_irq); 101 setup_irq(MCF_IRQ_TIMER, &mcftmr_timer_irq);
111 102
112 __raw_writew(MCFTIMER_TMR_DISABLE, TA(MCFTIMER_TMR)); 103 __raw_writew(MCFTIMER_TMR_DISABLE, TA(MCFTIMER_TMR));
113 mcftmr_cycles_per_jiffy = FREQ / HZ; 104 mcftmr_cycles_per_jiffy = FREQ / HZ;
@@ -124,7 +115,7 @@ void hw_timer_init(void)
124 mcftmr_clk.mult = clocksource_hz2mult(FREQ, mcftmr_clk.shift); 115 mcftmr_clk.mult = clocksource_hz2mult(FREQ, mcftmr_clk.shift);
125 clocksource_register(&mcftmr_clk); 116 clocksource_register(&mcftmr_clk);
126 117
127 mcf_settimericr(1, mcf_timerlevel); 118 mcf_clrimr(MCFINTC_TIMER1);
128 119
129#ifdef CONFIG_HIGHPROFILE 120#ifdef CONFIG_HIGHPROFILE
130 coldfire_profile_init(); 121 coldfire_profile_init();
@@ -171,7 +162,7 @@ void coldfire_profile_init(void)
171 printk(KERN_INFO "PROFILE: lodging TIMER2 @ %dHz as profile timer\n", 162 printk(KERN_INFO "PROFILE: lodging TIMER2 @ %dHz as profile timer\n",
172 PROFILEHZ); 163 PROFILEHZ);
173 164
174 setup_irq(mcf_profilevector, &coldfire_profile_irq); 165 setup_irq(MCF_IRQ_PROFILER, &coldfire_profile_irq);
175 166
176 /* Set up TIMER 2 as high speed profile clock */ 167 /* Set up TIMER 2 as high speed profile clock */
177 __raw_writew(MCFTIMER_TMR_DISABLE, PA(MCFTIMER_TMR)); 168 __raw_writew(MCFTIMER_TMR_DISABLE, PA(MCFTIMER_TMR));
@@ -180,7 +171,7 @@ void coldfire_profile_init(void)
180 __raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 | 171 __raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
181 MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, PA(MCFTIMER_TMR)); 172 MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, PA(MCFTIMER_TMR));
182 173
183 mcf_settimericr(2, 7); 174 mcf_clrimr(MCFINTC_TIMER2);
184} 175}
185 176
186/***************************************************************************/ 177/***************************************************************************/