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authorDavid Howells <dhowells@redhat.com>2007-08-01 14:04:51 -0400
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-08-01 23:48:17 -0400
commit04668873daa822aa6c806ba28d1143db8dcb26e8 (patch)
treec71f7864aa5ccd364619d6ee02b7ab3cb269c498
parentb5625481832ef1ab1a8e31fac0b1d14acdbbc148 (diff)
FRV: Enable the MB86943 PCI arbiter correctly
Enable the MB93090 motherboard's MB86943 PCI arbiter correctly by assigning to the register rather than comparing against it. This is required to support bus mastering. Signed-off-by: David Howells <dhowells@redhat.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
-rw-r--r--arch/frv/mb93090-mb00/pci-vdk.c3
-rw-r--r--include/asm-frv/mb86943a.h3
2 files changed, 5 insertions, 1 deletions
diff --git a/arch/frv/mb93090-mb00/pci-vdk.c b/arch/frv/mb93090-mb00/pci-vdk.c
index 0b581e3cf7c7..6d51f133fb23 100644
--- a/arch/frv/mb93090-mb00/pci-vdk.c
+++ b/arch/frv/mb93090-mb00/pci-vdk.c
@@ -400,7 +400,8 @@ int __init pcibios_init(void)
400 __reg_MB86943_pci_sl_mem_base = __region_CS2 + 0x08000000; 400 __reg_MB86943_pci_sl_mem_base = __region_CS2 + 0x08000000;
401 mb(); 401 mb();
402 402
403 *(volatile unsigned long *)(__region_CS2+0x01300014) == 1; 403 /* enable PCI arbitration */
404 __reg_MB86943_pci_arbiter = MB86943_PCIARB_EN;
404 405
405 ioport_resource.start = (__reg_MB86943_sl_pci_io_base << 9) & 0xfffffc00; 406 ioport_resource.start = (__reg_MB86943_sl_pci_io_base << 9) & 0xfffffc00;
406 ioport_resource.end = (__reg_MB86943_sl_pci_io_range << 9) | 0x3ff; 407 ioport_resource.end = (__reg_MB86943_sl_pci_io_range << 9) | 0x3ff;
diff --git a/include/asm-frv/mb86943a.h b/include/asm-frv/mb86943a.h
index b89fd0b56bb3..e87ef924bfb4 100644
--- a/include/asm-frv/mb86943a.h
+++ b/include/asm-frv/mb86943a.h
@@ -36,4 +36,7 @@
36#define __reg_MB86943_pci_sl_io_base *(volatile uint32_t *) (__region_CS1 + 0x70) 36#define __reg_MB86943_pci_sl_io_base *(volatile uint32_t *) (__region_CS1 + 0x70)
37#define __reg_MB86943_pci_sl_mem_base *(volatile uint32_t *) (__region_CS1 + 0x78) 37#define __reg_MB86943_pci_sl_mem_base *(volatile uint32_t *) (__region_CS1 + 0x78)
38 38
39#define __reg_MB86943_pci_arbiter *(volatile uint32_t *) (__region_CS2 + 0x01300014)
40#define MB86943_PCIARB_EN 0x00000001
41
39#endif /* _ASM_MB86943A_H */ 42#endif /* _ASM_MB86943A_H */