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authorKukjin Kim <kgene.kim@samsung.com>2010-08-06 08:31:29 -0400
committerKukjin Kim <kgene.kim@samsung.com>2010-08-06 08:31:29 -0400
commit0321c51f8f0ea8d0a7185a334356b2dca28a0846 (patch)
treea77c2fa19b6b046d0b7757a81558aa46c53191d8
parente4201764a474fcb3e858c1aa09b4f5c878216d5a (diff)
parentaaeedff6b1f3cc8e2de0d2899c9ab2699a1ce817 (diff)
Merge branch 'next-s5pc100' into for-next
-rw-r--r--arch/arm/mach-s5pc100/Kconfig20
-rw-r--r--arch/arm/mach-s5pc100/Makefile2
-rw-r--r--arch/arm/mach-s5pc100/clock.c8
-rw-r--r--arch/arm/mach-s5pc100/cpu.c5
-rw-r--r--arch/arm/mach-s5pc100/include/mach/irqs.h2
-rw-r--r--arch/arm/mach-s5pc100/include/mach/map.h13
-rw-r--r--arch/arm/mach-s5pc100/include/mach/regs-clock.h3
-rw-r--r--arch/arm/mach-s5pc100/mach-smdkc100.c45
-rw-r--r--arch/arm/mach-s5pc100/setup-ide.c70
-rw-r--r--arch/arm/mach-s5pc100/setup-keypad.c34
-rw-r--r--arch/arm/mach-s5pc100/setup-sdhci.c8
11 files changed, 201 insertions, 9 deletions
diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig
index b2a11dfa3399..25ca7c686e77 100644
--- a/arch/arm/mach-s5pc100/Kconfig
+++ b/arch/arm/mach-s5pc100/Kconfig
@@ -25,6 +25,16 @@ config S5PC100_SETUP_I2C1
25 help 25 help
26 Common setup code for i2c bus 1. 26 Common setup code for i2c bus 1.
27 27
28config S5PC100_SETUP_IDE
29 bool
30 help
31 Common setup code for S5PC100 IDE GPIO configurations
32
33config S5PC100_SETUP_KEYPAD
34 bool
35 help
36 Common setup code for KEYPAD GPIO configurations.
37
28config S5PC100_SETUP_SDHCI 38config S5PC100_SETUP_SDHCI
29 bool 39 bool
30 select S5PC100_SETUP_SDHCI_GPIO 40 select S5PC100_SETUP_SDHCI_GPIO
@@ -39,14 +49,24 @@ config S5PC100_SETUP_SDHCI_GPIO
39config MACH_SMDKC100 49config MACH_SMDKC100
40 bool "SMDKC100" 50 bool "SMDKC100"
41 select CPU_S5PC100 51 select CPU_S5PC100
52 select SAMSUNG_DEV_ADC
42 select S3C_DEV_FB 53 select S3C_DEV_FB
43 select S3C_DEV_I2C1 54 select S3C_DEV_I2C1
55 select SAMSUNG_DEV_IDE
44 select S3C_DEV_HSMMC 56 select S3C_DEV_HSMMC
45 select S3C_DEV_HSMMC1 57 select S3C_DEV_HSMMC1
46 select S3C_DEV_HSMMC2 58 select S3C_DEV_HSMMC2
59 select SAMSUNG_DEV_KEYPAD
60 select S3C_DEV_RTC
61 select SAMSUNG_DEV_TS
62 select S3C_DEV_WDT
63 select HAVE_S3C2410_WATCHDOG
47 select S5PC100_SETUP_FB_24BPP 64 select S5PC100_SETUP_FB_24BPP
48 select S5PC100_SETUP_I2C1 65 select S5PC100_SETUP_I2C1
66 select S5PC100_SETUP_IDE
67 select S5PC100_SETUP_KEYPAD
49 select S5PC100_SETUP_SDHCI 68 select S5PC100_SETUP_SDHCI
69 select HAVE_S3C_RTC
50 help 70 help
51 Machine support for the Samsung SMDKC100 71 Machine support for the Samsung SMDKC100
52 72
diff --git a/arch/arm/mach-s5pc100/Makefile b/arch/arm/mach-s5pc100/Makefile
index 543f3de5131e..a021ed1fb4b6 100644
--- a/arch/arm/mach-s5pc100/Makefile
+++ b/arch/arm/mach-s5pc100/Makefile
@@ -19,6 +19,8 @@ obj-$(CONFIG_CPU_S5PC100) += dma.o
19 19
20obj-$(CONFIG_S5PC100_SETUP_FB_24BPP) += setup-fb-24bpp.o 20obj-$(CONFIG_S5PC100_SETUP_FB_24BPP) += setup-fb-24bpp.o
21obj-$(CONFIG_S5PC100_SETUP_I2C1) += setup-i2c1.o 21obj-$(CONFIG_S5PC100_SETUP_I2C1) += setup-i2c1.o
22obj-$(CONFIG_S5PC100_SETUP_IDE) += setup-ide.o
23obj-$(CONFIG_S5PC100_SETUP_KEYPAD) += setup-keypad.o
22obj-$(CONFIG_S5PC100_SETUP_SDHCI) += setup-sdhci.o 24obj-$(CONFIG_S5PC100_SETUP_SDHCI) += setup-sdhci.o
23obj-$(CONFIG_S5PC100_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o 25obj-$(CONFIG_S5PC100_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
24 26
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
index e3fed4cfe7ad..084abd13b0a5 100644
--- a/arch/arm/mach-s5pc100/clock.c
+++ b/arch/arm/mach-s5pc100/clock.c
@@ -737,7 +737,7 @@ static struct clk init_clocks_disable[] = {
737 .enable = s5pc100_d1_5_ctrl, 737 .enable = s5pc100_d1_5_ctrl,
738 .ctrlbit = (1 << 7), 738 .ctrlbit = (1 << 7),
739 }, { 739 }, {
740 .name = "keyif", 740 .name = "keypad",
741 .id = -1, 741 .id = -1,
742 .parent = &clk_div_d1_bus.clk, 742 .parent = &clk_div_d1_bus.clk,
743 .enable = s5pc100_d1_5_ctrl, 743 .enable = s5pc100_d1_5_ctrl,
@@ -1078,7 +1078,7 @@ static struct clksrc_clk clksrcs[] = {
1078 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 }, 1078 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 },
1079 }, { 1079 }, {
1080 .clk = { 1080 .clk = {
1081 .name = "mmc_bus", 1081 .name = "sclk_mmc",
1082 .id = 0, 1082 .id = 0,
1083 .ctrlbit = (1 << 12), 1083 .ctrlbit = (1 << 12),
1084 .enable = s5pc100_sclk1_ctrl, 1084 .enable = s5pc100_sclk1_ctrl,
@@ -1089,7 +1089,7 @@ static struct clksrc_clk clksrcs[] = {
1089 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 }, 1089 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
1090 }, { 1090 }, {
1091 .clk = { 1091 .clk = {
1092 .name = "mmc_bus", 1092 .name = "sclk_mmc",
1093 .id = 1, 1093 .id = 1,
1094 .ctrlbit = (1 << 13), 1094 .ctrlbit = (1 << 13),
1095 .enable = s5pc100_sclk1_ctrl, 1095 .enable = s5pc100_sclk1_ctrl,
@@ -1100,7 +1100,7 @@ static struct clksrc_clk clksrcs[] = {
1100 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 }, 1100 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
1101 }, { 1101 }, {
1102 .clk = { 1102 .clk = {
1103 .name = "mmc_bus", 1103 .name = "sclk_mmc",
1104 .id = 2, 1104 .id = 2,
1105 .ctrlbit = (1 << 14), 1105 .ctrlbit = (1 << 14),
1106 .enable = s5pc100_sclk1_ctrl, 1106 .enable = s5pc100_sclk1_ctrl,
diff --git a/arch/arm/mach-s5pc100/cpu.c b/arch/arm/mach-s5pc100/cpu.c
index 7b5bdbc9a5df..799d22f41fcd 100644
--- a/arch/arm/mach-s5pc100/cpu.c
+++ b/arch/arm/mach-s5pc100/cpu.c
@@ -38,8 +38,10 @@
38#include <plat/cpu.h> 38#include <plat/cpu.h>
39#include <plat/devs.h> 39#include <plat/devs.h>
40#include <plat/clock.h> 40#include <plat/clock.h>
41#include <plat/ata-core.h>
41#include <plat/iic-core.h> 42#include <plat/iic-core.h>
42#include <plat/sdhci.h> 43#include <plat/sdhci.h>
44#include <plat/adc-core.h>
43#include <plat/onenand-core.h> 45#include <plat/onenand-core.h>
44 46
45#include <plat/s5pc100.h> 47#include <plat/s5pc100.h>
@@ -87,11 +89,14 @@ void __init s5pc100_map_io(void)
87 s5pc100_default_sdhci1(); 89 s5pc100_default_sdhci1();
88 s5pc100_default_sdhci2(); 90 s5pc100_default_sdhci2();
89 91
92 s3c_adc_setname("s3c64xx-adc");
93
90 /* the i2c devices are directly compatible with s3c2440 */ 94 /* the i2c devices are directly compatible with s3c2440 */
91 s3c_i2c0_setname("s3c2440-i2c"); 95 s3c_i2c0_setname("s3c2440-i2c");
92 s3c_i2c1_setname("s3c2440-i2c"); 96 s3c_i2c1_setname("s3c2440-i2c");
93 97
94 s3c_onenand_setname("s5pc100-onenand"); 98 s3c_onenand_setname("s5pc100-onenand");
99 s3c_cfcon_setname("s5pc100-pata");
95} 100}
96 101
97void __init s5pc100_init_clocks(int xtal) 102void __init s5pc100_init_clocks(int xtal)
diff --git a/arch/arm/mach-s5pc100/include/mach/irqs.h b/arch/arm/mach-s5pc100/include/mach/irqs.h
index 28aa551dc3a8..bfcc0b9d7ad7 100644
--- a/arch/arm/mach-s5pc100/include/mach/irqs.h
+++ b/arch/arm/mach-s5pc100/include/mach/irqs.h
@@ -38,7 +38,7 @@
38#define IRQ_IEMIEC S5P_IRQ_VIC1(6) 38#define IRQ_IEMIEC S5P_IRQ_VIC1(6)
39#define IRQ_ONENAND S5P_IRQ_VIC1(7) 39#define IRQ_ONENAND S5P_IRQ_VIC1(7)
40#define IRQ_NFC S5P_IRQ_VIC1(8) 40#define IRQ_NFC S5P_IRQ_VIC1(8)
41#define IRQ_CFC S5P_IRQ_VIC1(9) 41#define IRQ_CFCON S5P_IRQ_VIC1(9)
42#define IRQ_UART0 S5P_IRQ_VIC1(10) 42#define IRQ_UART0 S5P_IRQ_VIC1(10)
43#define IRQ_UART1 S5P_IRQ_VIC1(11) 43#define IRQ_UART1 S5P_IRQ_VIC1(11)
44#define IRQ_UART2 S5P_IRQ_VIC1(12) 44#define IRQ_UART2 S5P_IRQ_VIC1(12)
diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h
index cadae4305688..c018697e79bf 100644
--- a/arch/arm/mach-s5pc100/include/mach/map.h
+++ b/arch/arm/mach-s5pc100/include/mach/map.h
@@ -61,6 +61,8 @@
61 61
62#define S5PC100_PA_ONENAND (0xE7100000) 62#define S5PC100_PA_ONENAND (0xE7100000)
63 63
64#define S5PC100_PA_CFCON (0xE7800000)
65
64/* DMA */ 66/* DMA */
65#define S5PC100_PA_MDMA (0xE8100000) 67#define S5PC100_PA_MDMA (0xE8100000)
66#define S5PC100_PA_PDMA0 (0xE9000000) 68#define S5PC100_PA_PDMA0 (0xE9000000)
@@ -72,6 +74,9 @@
72 74
73#define S5PC100_PA_SYSTIMER (0xEA100000) 75#define S5PC100_PA_SYSTIMER (0xEA100000)
74 76
77#define S5PC100_PA_WATCHDOG (0xEA200000)
78#define S5PC100_PA_RTC (0xEA300000)
79
75#define S5PC100_PA_UART (0xEC000000) 80#define S5PC100_PA_UART (0xEC000000)
76 81
77#define S5P_PA_UART0 (S5PC100_PA_UART + 0x0) 82#define S5P_PA_UART0 (S5PC100_PA_UART + 0x0)
@@ -104,6 +109,8 @@
104#define S5PC100_PA_PCM0 0xF2400000 109#define S5PC100_PA_PCM0 0xF2400000
105#define S5PC100_PA_PCM1 0xF2500000 110#define S5PC100_PA_PCM1 0xF2500000
106 111
112#define S5PC100_PA_TSADC (0xF3000000)
113
107/* KEYPAD */ 114/* KEYPAD */
108#define S5PC100_PA_KEYPAD (0xF3100000) 115#define S5PC100_PA_KEYPAD (0xF3100000)
109 116
@@ -130,9 +137,15 @@
130#define S3C_PA_HSMMC1 S5PC100_PA_HSMMC(1) 137#define S3C_PA_HSMMC1 S5PC100_PA_HSMMC(1)
131#define S3C_PA_HSMMC2 S5PC100_PA_HSMMC(2) 138#define S3C_PA_HSMMC2 S5PC100_PA_HSMMC(2)
132#define S3C_PA_KEYPAD S5PC100_PA_KEYPAD 139#define S3C_PA_KEYPAD S5PC100_PA_KEYPAD
140#define S3C_PA_WDT S5PC100_PA_WATCHDOG
133#define S3C_PA_TSADC S5PC100_PA_TSADC 141#define S3C_PA_TSADC S5PC100_PA_TSADC
134#define S3C_PA_ONENAND S5PC100_PA_ONENAND 142#define S3C_PA_ONENAND S5PC100_PA_ONENAND
135#define S3C_PA_ONENAND_BUF S5PC100_PA_ONENAND_BUF 143#define S3C_PA_ONENAND_BUF S5PC100_PA_ONENAND_BUF
136#define S3C_SZ_ONENAND_BUF S5PC100_SZ_ONENAND_BUF 144#define S3C_SZ_ONENAND_BUF S5PC100_SZ_ONENAND_BUF
145#define S3C_PA_RTC S5PC100_PA_RTC
146
147#define SAMSUNG_PA_ADC S5PC100_PA_TSADC
148#define SAMSUNG_PA_CFCON S5PC100_PA_CFCON
149#define SAMSUNG_PA_KEYPAD S5PC100_PA_KEYPAD
137 150
138#endif /* __ASM_ARCH_C100_MAP_H */ 151#endif /* __ASM_ARCH_C100_MAP_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-clock.h b/arch/arm/mach-s5pc100/include/mach/regs-clock.h
index 5d27d286d504..bc92da2e0ba2 100644
--- a/arch/arm/mach-s5pc100/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5pc100/include/mach/regs-clock.h
@@ -71,7 +71,10 @@
71#define S5P_CLKDIV1_PCLKD1_SHIFT (16) 71#define S5P_CLKDIV1_PCLKD1_SHIFT (16)
72 72
73#define S5PC100_SWRESET S5PC100_REG_OTHERS(0x000) 73#define S5PC100_SWRESET S5PC100_REG_OTHERS(0x000)
74#define S5PC100_MEM_SYS_CFG S5PC100_REG_OTHERS(0x200)
74 75
75#define S5PC100_SWRESET_RESETVAL 0xc100 76#define S5PC100_SWRESET_RESETVAL 0xc100
76 77
78#define MEM_SYS_CFG_EBI_FIX_PRI_CFCON 0x30
79
77#endif /* __ASM_ARCH_REGS_CLOCK_H */ 80#endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index af22f8202a07..83a5d648a980 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -22,6 +22,7 @@
22#include <linux/i2c.h> 22#include <linux/i2c.h>
23#include <linux/fb.h> 23#include <linux/fb.h>
24#include <linux/delay.h> 24#include <linux/delay.h>
25#include <linux/input.h>
25 26
26#include <asm/mach/arch.h> 27#include <asm/mach/arch.h>
27#include <asm/mach/map.h> 28#include <asm/mach/map.h>
@@ -42,6 +43,10 @@
42#include <plat/s5pc100.h> 43#include <plat/s5pc100.h>
43#include <plat/fb.h> 44#include <plat/fb.h>
44#include <plat/iic.h> 45#include <plat/iic.h>
46#include <plat/ata.h>
47#include <plat/adc.h>
48#include <plat/keypad.h>
49#include <plat/ts.h>
45 50
46/* Following are default values for UCON, ULCON and UFCON UART registers */ 51/* Following are default values for UCON, ULCON and UFCON UART registers */
47#define S5PC100_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 52#define S5PC100_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
@@ -149,16 +154,51 @@ static struct s3c_fb_platdata smdkc100_lcd_pdata __initdata = {
149 .setup_gpio = s5pc100_fb_gpio_setup_24bpp, 154 .setup_gpio = s5pc100_fb_gpio_setup_24bpp,
150}; 155};
151 156
157static struct s3c_ide_platdata smdkc100_ide_pdata __initdata = {
158 .setup_gpio = s5pc100_ide_setup_gpio,
159};
160
161static uint32_t smdkc100_keymap[] __initdata = {
162 /* KEY(row, col, keycode) */
163 KEY(0, 3, KEY_1), KEY(0, 4, KEY_2), KEY(0, 5, KEY_3),
164 KEY(0, 6, KEY_4), KEY(0, 7, KEY_5),
165 KEY(1, 3, KEY_A), KEY(1, 4, KEY_B), KEY(1, 5, KEY_C),
166 KEY(1, 6, KEY_D), KEY(1, 7, KEY_E)
167};
168
169static struct matrix_keymap_data smdkc100_keymap_data __initdata = {
170 .keymap = smdkc100_keymap,
171 .keymap_size = ARRAY_SIZE(smdkc100_keymap),
172};
173
174static struct samsung_keypad_platdata smdkc100_keypad_data __initdata = {
175 .keymap_data = &smdkc100_keymap_data,
176 .rows = 2,
177 .cols = 8,
178};
179
152static struct platform_device *smdkc100_devices[] __initdata = { 180static struct platform_device *smdkc100_devices[] __initdata = {
181 &s3c_device_adc,
182 &s3c_device_cfcon,
153 &s3c_device_i2c0, 183 &s3c_device_i2c0,
154 &s3c_device_i2c1, 184 &s3c_device_i2c1,
155 &s3c_device_fb, 185 &s3c_device_fb,
156 &s3c_device_hsmmc0, 186 &s3c_device_hsmmc0,
157 &s3c_device_hsmmc1, 187 &s3c_device_hsmmc1,
158 &s3c_device_hsmmc2, 188 &s3c_device_hsmmc2,
189 &s3c_device_ts,
190 &s3c_device_wdt,
159 &smdkc100_lcd_powerdev, 191 &smdkc100_lcd_powerdev,
160 &s5pc100_device_iis0, 192 &s5pc100_device_iis0,
193 &samsung_device_keypad,
161 &s5pc100_device_ac97, 194 &s5pc100_device_ac97,
195 &s3c_device_rtc,
196};
197
198static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
199 .delay = 10000,
200 .presc = 49,
201 .oversampling_shift = 2,
162}; 202};
163 203
164static void __init smdkc100_map_io(void) 204static void __init smdkc100_map_io(void)
@@ -170,6 +210,8 @@ static void __init smdkc100_map_io(void)
170 210
171static void __init smdkc100_machine_init(void) 211static void __init smdkc100_machine_init(void)
172{ 212{
213 s3c24xx_ts_set_platdata(&s3c_ts_platform);
214
173 /* I2C */ 215 /* I2C */
174 s3c_i2c0_set_platdata(NULL); 216 s3c_i2c0_set_platdata(NULL);
175 s3c_i2c1_set_platdata(NULL); 217 s3c_i2c1_set_platdata(NULL);
@@ -177,6 +219,9 @@ static void __init smdkc100_machine_init(void)
177 i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1)); 219 i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
178 220
179 s3c_fb_set_platdata(&smdkc100_lcd_pdata); 221 s3c_fb_set_platdata(&smdkc100_lcd_pdata);
222 s3c_ide_set_platdata(&smdkc100_ide_pdata);
223
224 samsung_keypad_set_platdata(&smdkc100_keypad_data);
180 225
181 /* LCD init */ 226 /* LCD init */
182 gpio_request(S5PC100_GPD(0), "GPD"); 227 gpio_request(S5PC100_GPD(0), "GPD");
diff --git a/arch/arm/mach-s5pc100/setup-ide.c b/arch/arm/mach-s5pc100/setup-ide.c
new file mode 100644
index 000000000000..83575671fb59
--- /dev/null
+++ b/arch/arm/mach-s5pc100/setup-ide.c
@@ -0,0 +1,70 @@
1/* linux/arch/arm/mach-s5pc100/setup-ide.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5PC100 setup information for IDE
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/gpio.h>
15#include <linux/io.h>
16
17#include <mach/regs-clock.h>
18#include <plat/gpio-cfg.h>
19
20void s5pc100_ide_setup_gpio(void)
21{
22 u32 reg;
23 u32 gpio = 0;
24
25 /* Independent CF interface, CF chip select configuration */
26 reg = readl(S5PC100_MEM_SYS_CFG) & (~0x3f);
27 writel(reg | MEM_SYS_CFG_EBI_FIX_PRI_CFCON, S5PC100_MEM_SYS_CFG);
28
29 /* CF_Add[0 - 2], CF_IORDY, CF_INTRQ, CF_DMARQ, CF_DMARST, CF_DMACK */
30 for (gpio = S5PC100_GPJ0(0); gpio <= S5PC100_GPJ0(7); gpio++) {
31 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
32 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
33 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
34 }
35
36 /*CF_Data[0 - 7] */
37 for (gpio = S5PC100_GPJ2(0); gpio <= S5PC100_GPJ2(7); gpio++) {
38 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
39 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
40 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
41 }
42
43 /* CF_Data[8 - 15] */
44 for (gpio = S5PC100_GPJ3(0); gpio <= S5PC100_GPJ3(7); gpio++) {
45 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
46 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
47 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
48 }
49
50 /* CF_CS0, CF_CS1, CF_IORD, CF_IOWR */
51 for (gpio = S5PC100_GPJ4(0); gpio <= S5PC100_GPJ4(3); gpio++) {
52 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
53 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
54 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
55 }
56
57 /* EBI_OE, EBI_WE */
58 for (gpio = S5PC100_GPK0(6); gpio <= S5PC100_GPK0(7); gpio++)
59 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0));
60
61 /* CF_OE, CF_WE */
62 for (gpio = S5PC100_GPK1(6); gpio <= S5PC100_GPK1(7); gpio++) {
63 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
64 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
65 }
66
67 /* CF_CD */
68 s3c_gpio_cfgpin(S5PC100_GPK3(5), S3C_GPIO_SFN(2));
69 s3c_gpio_setpull(S5PC100_GPK3(5), S3C_GPIO_PULL_NONE);
70}
diff --git a/arch/arm/mach-s5pc100/setup-keypad.c b/arch/arm/mach-s5pc100/setup-keypad.c
new file mode 100644
index 000000000000..d0837a72a58e
--- /dev/null
+++ b/arch/arm/mach-s5pc100/setup-keypad.c
@@ -0,0 +1,34 @@
1/* linux/arch/arm/mach-s5pc100/setup-keypad.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * GPIO configuration for S5PC100 KeyPad device
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/gpio.h>
14#include <plat/gpio-cfg.h>
15
16void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
17{
18 unsigned int gpio;
19 unsigned int end;
20
21 /* Set all the necessary GPH3 pins to special-function 3: KP_ROW[x] */
22 end = S5PC100_GPH3(rows);
23 for (gpio = S5PC100_GPH3(0); gpio < end; gpio++) {
24 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
25 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
26 }
27
28 /* Set all the necessary GPH2 pins to special-function 3: KP_COL[x] */
29 end = S5PC100_GPH2(cols);
30 for (gpio = S5PC100_GPH2(0); gpio < end; gpio++) {
31 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
32 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
33 }
34}
diff --git a/arch/arm/mach-s5pc100/setup-sdhci.c b/arch/arm/mach-s5pc100/setup-sdhci.c
index ea7ff19adb95..f16946e456e9 100644
--- a/arch/arm/mach-s5pc100/setup-sdhci.c
+++ b/arch/arm/mach-s5pc100/setup-sdhci.c
@@ -26,10 +26,10 @@
26/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ 26/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
27 27
28char *s5pc100_hsmmc_clksrcs[4] = { 28char *s5pc100_hsmmc_clksrcs[4] = {
29 [0] = "hsmmc", 29 [0] = "hsmmc", /* HCLK */
30 [1] = "hsmmc", 30 /* [1] = "hsmmc", - duplicate HCLK entry */
31 /* [2] = "mmc_bus", not yet successfully used yet */ 31 [2] = "sclk_mmc", /* mmc_bus */
32 /* [3] = "48m", - note not successfully used yet */ 32 /* [3] = "48m", - note not successfully used yet */
33}; 33};
34 34
35 35