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authorMark Brown <broonie@opensource.wolfsonmicro.com>2011-11-02 10:47:24 -0400
committerMark Brown <broonie@opensource.wolfsonmicro.com>2011-11-21 13:11:43 -0500
commitf733547aa30b9e85cc5f2739f3c236408157d2ce (patch)
tree1deca6797a4c68519649fdf8f5154fb580de514e
parent56a926dd72bd836f71216ba5b034adb7f48e80e9 (diff)
ASoC: Remove WM5100 DSP memory windows from register default data
They're all volatile so shouldn't have defaults and as we've got pages into the DSP memory the registers themselves aren't that useful - a further patch adding support for the DSPs will provide direct diagnostic access to the DSP memories. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat
-rw-r--r--sound/soc/codecs/wm5100-tables.c168
1 files changed, 0 insertions, 168 deletions
diff --git a/sound/soc/codecs/wm5100-tables.c b/sound/soc/codecs/wm5100-tables.c
index 3e90dea4e267..9a18fae68204 100644
--- a/sound/soc/codecs/wm5100-tables.c
+++ b/sound/soc/codecs/wm5100-tables.c
@@ -697,90 +697,6 @@ bool wm5100_readable_register(struct device *dev, unsigned int reg)
697 case WM5100_HPLPF3_2: 697 case WM5100_HPLPF3_2:
698 case WM5100_HPLPF4_1: 698 case WM5100_HPLPF4_1:
699 case WM5100_HPLPF4_2: 699 case WM5100_HPLPF4_2:
700 case WM5100_DSP1_DM_0:
701 case WM5100_DSP1_DM_1:
702 case WM5100_DSP1_DM_2:
703 case WM5100_DSP1_DM_3:
704 case WM5100_DSP1_DM_508:
705 case WM5100_DSP1_DM_509:
706 case WM5100_DSP1_DM_510:
707 case WM5100_DSP1_DM_511:
708 case WM5100_DSP1_PM_0:
709 case WM5100_DSP1_PM_1:
710 case WM5100_DSP1_PM_2:
711 case WM5100_DSP1_PM_3:
712 case WM5100_DSP1_PM_4:
713 case WM5100_DSP1_PM_5:
714 case WM5100_DSP1_PM_1530:
715 case WM5100_DSP1_PM_1531:
716 case WM5100_DSP1_PM_1532:
717 case WM5100_DSP1_PM_1533:
718 case WM5100_DSP1_PM_1534:
719 case WM5100_DSP1_PM_1535:
720 case WM5100_DSP1_ZM_0:
721 case WM5100_DSP1_ZM_1:
722 case WM5100_DSP1_ZM_2:
723 case WM5100_DSP1_ZM_3:
724 case WM5100_DSP1_ZM_2044:
725 case WM5100_DSP1_ZM_2045:
726 case WM5100_DSP1_ZM_2046:
727 case WM5100_DSP1_ZM_2047:
728 case WM5100_DSP2_DM_0:
729 case WM5100_DSP2_DM_1:
730 case WM5100_DSP2_DM_2:
731 case WM5100_DSP2_DM_3:
732 case WM5100_DSP2_DM_508:
733 case WM5100_DSP2_DM_509:
734 case WM5100_DSP2_DM_510:
735 case WM5100_DSP2_DM_511:
736 case WM5100_DSP2_PM_0:
737 case WM5100_DSP2_PM_1:
738 case WM5100_DSP2_PM_2:
739 case WM5100_DSP2_PM_3:
740 case WM5100_DSP2_PM_4:
741 case WM5100_DSP2_PM_5:
742 case WM5100_DSP2_PM_1530:
743 case WM5100_DSP2_PM_1531:
744 case WM5100_DSP2_PM_1532:
745 case WM5100_DSP2_PM_1533:
746 case WM5100_DSP2_PM_1534:
747 case WM5100_DSP2_PM_1535:
748 case WM5100_DSP2_ZM_0:
749 case WM5100_DSP2_ZM_1:
750 case WM5100_DSP2_ZM_2:
751 case WM5100_DSP2_ZM_3:
752 case WM5100_DSP2_ZM_2044:
753 case WM5100_DSP2_ZM_2045:
754 case WM5100_DSP2_ZM_2046:
755 case WM5100_DSP2_ZM_2047:
756 case WM5100_DSP3_DM_0:
757 case WM5100_DSP3_DM_1:
758 case WM5100_DSP3_DM_2:
759 case WM5100_DSP3_DM_3:
760 case WM5100_DSP3_DM_508:
761 case WM5100_DSP3_DM_509:
762 case WM5100_DSP3_DM_510:
763 case WM5100_DSP3_DM_511:
764 case WM5100_DSP3_PM_0:
765 case WM5100_DSP3_PM_1:
766 case WM5100_DSP3_PM_2:
767 case WM5100_DSP3_PM_3:
768 case WM5100_DSP3_PM_4:
769 case WM5100_DSP3_PM_5:
770 case WM5100_DSP3_PM_1530:
771 case WM5100_DSP3_PM_1531:
772 case WM5100_DSP3_PM_1532:
773 case WM5100_DSP3_PM_1533:
774 case WM5100_DSP3_PM_1534:
775 case WM5100_DSP3_PM_1535:
776 case WM5100_DSP3_ZM_0:
777 case WM5100_DSP3_ZM_1:
778 case WM5100_DSP3_ZM_2:
779 case WM5100_DSP3_ZM_3:
780 case WM5100_DSP3_ZM_2044:
781 case WM5100_DSP3_ZM_2045:
782 case WM5100_DSP3_ZM_2046:
783 case WM5100_DSP3_ZM_2047:
784 return 1; 700 return 1;
785 default: 701 default:
786 return 0; 702 return 0;
@@ -1445,88 +1361,4 @@ struct reg_default wm5100_reg_defaults[WM5100_REGISTER_COUNT] = {
1445 { 0x0EC9, 0x0000 }, /* R3785 - HPLPF3_2 */ 1361 { 0x0EC9, 0x0000 }, /* R3785 - HPLPF3_2 */
1446 { 0x0ECC, 0x0000 }, /* R3788 - HPLPF4_1 */ 1362 { 0x0ECC, 0x0000 }, /* R3788 - HPLPF4_1 */
1447 { 0x0ECD, 0x0000 }, /* R3789 - HPLPF4_2 */ 1363 { 0x0ECD, 0x0000 }, /* R3789 - HPLPF4_2 */
1448 { 0x4000, 0x0000 }, /* R16384 - DSP1 DM 0 */
1449 { 0x4001, 0x0000 }, /* R16385 - DSP1 DM 1 */
1450 { 0x4002, 0x0000 }, /* R16386 - DSP1 DM 2 */
1451 { 0x4003, 0x0000 }, /* R16387 - DSP1 DM 3 */
1452 { 0x41FC, 0x0000 }, /* R16892 - DSP1 DM 508 */
1453 { 0x41FD, 0x0000 }, /* R16893 - DSP1 DM 509 */
1454 { 0x41FE, 0x0000 }, /* R16894 - DSP1 DM 510 */
1455 { 0x41FF, 0x0000 }, /* R16895 - DSP1 DM 511 */
1456 { 0x4800, 0x0000 }, /* R18432 - DSP1 PM 0 */
1457 { 0x4801, 0x0000 }, /* R18433 - DSP1 PM 1 */
1458 { 0x4802, 0x0000 }, /* R18434 - DSP1 PM 2 */
1459 { 0x4803, 0x0000 }, /* R18435 - DSP1 PM 3 */
1460 { 0x4804, 0x0000 }, /* R18436 - DSP1 PM 4 */
1461 { 0x4805, 0x0000 }, /* R18437 - DSP1 PM 5 */
1462 { 0x4DFA, 0x0000 }, /* R19962 - DSP1 PM 1530 */
1463 { 0x4DFB, 0x0000 }, /* R19963 - DSP1 PM 1531 */
1464 { 0x4DFC, 0x0000 }, /* R19964 - DSP1 PM 1532 */
1465 { 0x4DFD, 0x0000 }, /* R19965 - DSP1 PM 1533 */
1466 { 0x4DFE, 0x0000 }, /* R19966 - DSP1 PM 1534 */
1467 { 0x4DFF, 0x0000 }, /* R19967 - DSP1 PM 1535 */
1468 { 0x5000, 0x0000 }, /* R20480 - DSP1 ZM 0 */
1469 { 0x5001, 0x0000 }, /* R20481 - DSP1 ZM 1 */
1470 { 0x5002, 0x0000 }, /* R20482 - DSP1 ZM 2 */
1471 { 0x5003, 0x0000 }, /* R20483 - DSP1 ZM 3 */
1472 { 0x57FC, 0x0000 }, /* R22524 - DSP1 ZM 2044 */
1473 { 0x57FD, 0x0000 }, /* R22525 - DSP1 ZM 2045 */
1474 { 0x57FE, 0x0000 }, /* R22526 - DSP1 ZM 2046 */
1475 { 0x57FF, 0x0000 }, /* R22527 - DSP1 ZM 2047 */
1476 { 0x6000, 0x0000 }, /* R24576 - DSP2 DM 0 */
1477 { 0x6001, 0x0000 }, /* R24577 - DSP2 DM 1 */
1478 { 0x6002, 0x0000 }, /* R24578 - DSP2 DM 2 */
1479 { 0x6003, 0x0000 }, /* R24579 - DSP2 DM 3 */
1480 { 0x61FC, 0x0000 }, /* R25084 - DSP2 DM 508 */
1481 { 0x61FD, 0x0000 }, /* R25085 - DSP2 DM 509 */
1482 { 0x61FE, 0x0000 }, /* R25086 - DSP2 DM 510 */
1483 { 0x61FF, 0x0000 }, /* R25087 - DSP2 DM 511 */
1484 { 0x6800, 0x0000 }, /* R26624 - DSP2 PM 0 */
1485 { 0x6801, 0x0000 }, /* R26625 - DSP2 PM 1 */
1486 { 0x6802, 0x0000 }, /* R26626 - DSP2 PM 2 */
1487 { 0x6803, 0x0000 }, /* R26627 - DSP2 PM 3 */
1488 { 0x6804, 0x0000 }, /* R26628 - DSP2 PM 4 */
1489 { 0x6805, 0x0000 }, /* R26629 - DSP2 PM 5 */
1490 { 0x6DFA, 0x0000 }, /* R28154 - DSP2 PM 1530 */
1491 { 0x6DFB, 0x0000 }, /* R28155 - DSP2 PM 1531 */
1492 { 0x6DFC, 0x0000 }, /* R28156 - DSP2 PM 1532 */
1493 { 0x6DFD, 0x0000 }, /* R28157 - DSP2 PM 1533 */
1494 { 0x6DFE, 0x0000 }, /* R28158 - DSP2 PM 1534 */
1495 { 0x6DFF, 0x0000 }, /* R28159 - DSP2 PM 1535 */
1496 { 0x7000, 0x0000 }, /* R28672 - DSP2 ZM 0 */
1497 { 0x7001, 0x0000 }, /* R28673 - DSP2 ZM 1 */
1498 { 0x7002, 0x0000 }, /* R28674 - DSP2 ZM 2 */
1499 { 0x7003, 0x0000 }, /* R28675 - DSP2 ZM 3 */
1500 { 0x77FC, 0x0000 }, /* R30716 - DSP2 ZM 2044 */
1501 { 0x77FD, 0x0000 }, /* R30717 - DSP2 ZM 2045 */
1502 { 0x77FE, 0x0000 }, /* R30718 - DSP2 ZM 2046 */
1503 { 0x77FF, 0x0000 }, /* R30719 - DSP2 ZM 2047 */
1504 { 0x8000, 0x0000 }, /* R32768 - DSP3 DM 0 */
1505 { 0x8001, 0x0000 }, /* R32769 - DSP3 DM 1 */
1506 { 0x8002, 0x0000 }, /* R32770 - DSP3 DM 2 */
1507 { 0x8003, 0x0000 }, /* R32771 - DSP3 DM 3 */
1508 { 0x81FC, 0x0000 }, /* R33276 - DSP3 DM 508 */
1509 { 0x81FD, 0x0000 }, /* R33277 - DSP3 DM 509 */
1510 { 0x81FE, 0x0000 }, /* R33278 - DSP3 DM 510 */
1511 { 0x81FF, 0x0000 }, /* R33279 - DSP3 DM 511 */
1512 { 0x8800, 0x0000 }, /* R34816 - DSP3 PM 0 */
1513 { 0x8801, 0x0000 }, /* R34817 - DSP3 PM 1 */
1514 { 0x8802, 0x0000 }, /* R34818 - DSP3 PM 2 */
1515 { 0x8803, 0x0000 }, /* R34819 - DSP3 PM 3 */
1516 { 0x8804, 0x0000 }, /* R34820 - DSP3 PM 4 */
1517 { 0x8805, 0x0000 }, /* R34821 - DSP3 PM 5 */
1518 { 0x8DFA, 0x0000 }, /* R36346 - DSP3 PM 1530 */
1519 { 0x8DFB, 0x0000 }, /* R36347 - DSP3 PM 1531 */
1520 { 0x8DFC, 0x0000 }, /* R36348 - DSP3 PM 1532 */
1521 { 0x8DFD, 0x0000 }, /* R36349 - DSP3 PM 1533 */
1522 { 0x8DFE, 0x0000 }, /* R36350 - DSP3 PM 1534 */
1523 { 0x8DFF, 0x0000 }, /* R36351 - DSP3 PM 1535 */
1524 { 0x9000, 0x0000 }, /* R36864 - DSP3 ZM 0 */
1525 { 0x9001, 0x0000 }, /* R36865 - DSP3 ZM 1 */
1526 { 0x9002, 0x0000 }, /* R36866 - DSP3 ZM 2 */
1527 { 0x9003, 0x0000 }, /* R36867 - DSP3 ZM 3 */
1528 { 0x97FC, 0x0000 }, /* R38908 - DSP3 ZM 2044 */
1529 { 0x97FD, 0x0000 }, /* R38909 - DSP3 ZM 2045 */
1530 { 0x97FE, 0x0000 }, /* R38910 - DSP3 ZM 2046 */
1531 { 0x97FF, 0x0000 }, /* R38911 - DSP3 ZM 2047 */
1532}; 1364};
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-22 12:17:25 -0500