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authorJaecheol Lee <jc.lee@samsung.com>2011-07-18 06:21:27 -0400
committerKukjin Kim <kgene.kim@samsung.com>2011-07-20 10:38:13 -0400
commite4cf2d1495fc6030c6b01e266aaa125061f58d5b (patch)
treea1c63b485ad46a4be5fcf69a89dedc40c570424f
parente28e301475f373b4c4361a47c83da20c951c2201 (diff)
ARM: EXYNOS4: Remove PMU configuration for S2RAM
PMU(Power Management Unit) configuraion for S2RAM(SLEEP) is removed and using function which provided by PMU support code to configure PMU register. Signed-off-by: Jaecheol Lee <jc.lee@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat
-rw-r--r--arch/arm/mach-exynos4/pm.c77
1 files changed, 2 insertions, 75 deletions
diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c
index 8755ca8dd48d..a073a0156daa 100644
--- a/arch/arm/mach-exynos4/pm.c
+++ b/arch/arm/mach-exynos4/pm.c
@@ -30,80 +30,7 @@
30#include <mach/regs-clock.h> 30#include <mach/regs-clock.h>
31#include <mach/regs-pmu.h> 31#include <mach/regs-pmu.h>
32#include <mach/pm-core.h> 32#include <mach/pm-core.h>
33 33#include <mach/pmu.h>
34static struct sleep_save exynos4_sleep[] = {
35 { .reg = S5P_ARM_CORE0_LOWPWR , .val = 0x2, },
36 { .reg = S5P_DIS_IRQ_CORE0 , .val = 0x0, },
37 { .reg = S5P_DIS_IRQ_CENTRAL0 , .val = 0x0, },
38 { .reg = S5P_ARM_CORE1_LOWPWR , .val = 0x2, },
39 { .reg = S5P_DIS_IRQ_CORE1 , .val = 0x0, },
40 { .reg = S5P_DIS_IRQ_CENTRAL1 , .val = 0x0, },
41 { .reg = S5P_ARM_COMMON_LOWPWR , .val = 0x2, },
42 { .reg = S5P_L2_0_LOWPWR , .val = 0x3, },
43 { .reg = S5P_L2_1_LOWPWR , .val = 0x3, },
44 { .reg = S5P_CMU_ACLKSTOP_LOWPWR , .val = 0x0, },
45 { .reg = S5P_CMU_SCLKSTOP_LOWPWR , .val = 0x0, },
46 { .reg = S5P_CMU_RESET_LOWPWR , .val = 0x0, },
47 { .reg = S5P_APLL_SYSCLK_LOWPWR , .val = 0x0, },
48 { .reg = S5P_MPLL_SYSCLK_LOWPWR , .val = 0x0, },
49 { .reg = S5P_VPLL_SYSCLK_LOWPWR , .val = 0x0, },
50 { .reg = S5P_EPLL_SYSCLK_LOWPWR , .val = 0x0, },
51 { .reg = S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR , .val = 0x0, },
52 { .reg = S5P_CMU_RESET_GPSALIVE_LOWPWR , .val = 0x0, },
53 { .reg = S5P_CMU_CLKSTOP_CAM_LOWPWR , .val = 0x0, },
54 { .reg = S5P_CMU_CLKSTOP_TV_LOWPWR , .val = 0x0, },
55 { .reg = S5P_CMU_CLKSTOP_MFC_LOWPWR , .val = 0x0, },
56 { .reg = S5P_CMU_CLKSTOP_G3D_LOWPWR , .val = 0x0, },
57 { .reg = S5P_CMU_CLKSTOP_LCD0_LOWPWR , .val = 0x0, },
58 { .reg = S5P_CMU_CLKSTOP_LCD1_LOWPWR , .val = 0x0, },
59 { .reg = S5P_CMU_CLKSTOP_MAUDIO_LOWPWR , .val = 0x0, },
60 { .reg = S5P_CMU_CLKSTOP_GPS_LOWPWR , .val = 0x0, },
61 { .reg = S5P_CMU_RESET_CAM_LOWPWR , .val = 0x0, },
62 { .reg = S5P_CMU_RESET_TV_LOWPWR , .val = 0x0, },
63 { .reg = S5P_CMU_RESET_MFC_LOWPWR , .val = 0x0, },
64 { .reg = S5P_CMU_RESET_G3D_LOWPWR , .val = 0x0, },
65 { .reg = S5P_CMU_RESET_LCD0_LOWPWR , .val = 0x0, },
66 { .reg = S5P_CMU_RESET_LCD1_LOWPWR , .val = 0x0, },
67 { .reg = S5P_CMU_RESET_MAUDIO_LOWPWR , .val = 0x0, },
68 { .reg = S5P_CMU_RESET_GPS_LOWPWR , .val = 0x0, },
69 { .reg = S5P_TOP_BUS_LOWPWR , .val = 0x0, },
70 { .reg = S5P_TOP_RETENTION_LOWPWR , .val = 0x1, },
71 { .reg = S5P_TOP_PWR_LOWPWR , .val = 0x3, },
72 { .reg = S5P_LOGIC_RESET_LOWPWR , .val = 0x0, },
73 { .reg = S5P_ONENAND_MEM_LOWPWR , .val = 0x0, },
74 { .reg = S5P_MODIMIF_MEM_LOWPWR , .val = 0x0, },
75 { .reg = S5P_G2D_ACP_MEM_LOWPWR , .val = 0x0, },
76 { .reg = S5P_USBOTG_MEM_LOWPWR , .val = 0x0, },
77 { .reg = S5P_HSMMC_MEM_LOWPWR , .val = 0x0, },
78 { .reg = S5P_CSSYS_MEM_LOWPWR , .val = 0x0, },
79 { .reg = S5P_SECSS_MEM_LOWPWR , .val = 0x0, },
80 { .reg = S5P_PCIE_MEM_LOWPWR , .val = 0x0, },
81 { .reg = S5P_SATA_MEM_LOWPWR , .val = 0x0, },
82 { .reg = S5P_PAD_RETENTION_DRAM_LOWPWR , .val = 0x0, },
83 { .reg = S5P_PAD_RETENTION_MAUDIO_LOWPWR , .val = 0x0, },
84 { .reg = S5P_PAD_RETENTION_GPIO_LOWPWR , .val = 0x0, },
85 { .reg = S5P_PAD_RETENTION_UART_LOWPWR , .val = 0x0, },
86 { .reg = S5P_PAD_RETENTION_MMCA_LOWPWR , .val = 0x0, },
87 { .reg = S5P_PAD_RETENTION_MMCB_LOWPWR , .val = 0x0, },
88 { .reg = S5P_PAD_RETENTION_EBIA_LOWPWR , .val = 0x0, },
89 { .reg = S5P_PAD_RETENTION_EBIB_LOWPWR , .val = 0x0, },
90 { .reg = S5P_PAD_RETENTION_ISOLATION_LOWPWR , .val = 0x0, },
91 { .reg = S5P_PAD_RETENTION_ALV_SEL_LOWPWR , .val = 0x0, },
92 { .reg = S5P_XUSBXTI_LOWPWR , .val = 0x0, },
93 { .reg = S5P_XXTI_LOWPWR , .val = 0x0, },
94 { .reg = S5P_EXT_REGULATOR_LOWPWR , .val = 0x0, },
95 { .reg = S5P_GPIO_MODE_LOWPWR , .val = 0x0, },
96 { .reg = S5P_GPIO_MODE_MAUDIO_LOWPWR , .val = 0x0, },
97 { .reg = S5P_CAM_LOWPWR , .val = 0x0, },
98 { .reg = S5P_TV_LOWPWR , .val = 0x0, },
99 { .reg = S5P_MFC_LOWPWR , .val = 0x0, },
100 { .reg = S5P_G3D_LOWPWR , .val = 0x0, },
101 { .reg = S5P_LCD0_LOWPWR , .val = 0x0, },
102 { .reg = S5P_LCD1_LOWPWR , .val = 0x0, },
103 { .reg = S5P_MAUDIO_LOWPWR , .val = 0x0, },
104 { .reg = S5P_GPS_LOWPWR , .val = 0x0, },
105 { .reg = S5P_GPS_ALIVE_LOWPWR , .val = 0x0, },
106};
107 34
108static struct sleep_save exynos4_set_clksrc[] = { 35static struct sleep_save exynos4_set_clksrc[] = {
109 { .reg = S5P_CLKSRC_MASK_TOP , .val = 0x00000001, }, 36 { .reg = S5P_CLKSRC_MASK_TOP , .val = 0x00000001, },
@@ -331,7 +258,7 @@ static void exynos4_pm_prepare(void)
331 258
332 /* Set value of power down register for sleep mode */ 259 /* Set value of power down register for sleep mode */
333 260
334 s3c_pm_do_restore_core(exynos4_sleep, ARRAY_SIZE(exynos4_sleep)); 261 exynos4_sys_powerdown_conf(SYS_SLEEP);
335 __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1); 262 __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
336 263
337 /* ensure at least INFORM0 has the resume address */ 264 /* ensure at least INFORM0 has the resume address */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-10 18:02:26 -0500