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authorLeonid Yegoshin <Leonid.Yegoshin@imgtec.com>2013-12-16 06:46:33 -0500
committerRalf Baechle <ralf@linux-mips.org>2014-03-26 18:09:18 -0400
commitde8974e3f76c00231cf6839797b4766d5a926ca3 (patch)
treec15c79b04e6b796decfc00c71581e305bb9c23f0
parenta80538549957bb0e0fdce147584450be802c04e1 (diff)
MIPS: asm: r4kcache: Add EVA cache flushing functions
Add EVA cache flushing functions similar to non-EVA configurations. Because the cache may or may not contain user virtual addresses, we need to use the 'cache' or 'cachee' instruction based on whether we flush the cache on behalf of kernel or user respectively. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Diffstat
-rw-r--r--arch/mips/include/asm/r4kcache.h152
1 files changed, 151 insertions, 1 deletions
diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h
index cac279c65601..69c2ada7d4aa 100644
--- a/arch/mips/include/asm/r4kcache.h
+++ b/arch/mips/include/asm/r4kcache.h
@@ -17,6 +17,7 @@
17#include <asm/cpu-features.h> 17#include <asm/cpu-features.h>
18#include <asm/cpu-type.h> 18#include <asm/cpu-type.h>
19#include <asm/mipsmtregs.h> 19#include <asm/mipsmtregs.h>
20#include <asm/uaccess.h> /* for segment_eq() */
20 21
21/* 22/*
22 * This macro return a properly sign-extended address suitable as base address 23 * This macro return a properly sign-extended address suitable as base address
@@ -374,6 +375,91 @@ static inline void invalidate_tcache_page(unsigned long addr)
374 : "r" (base), \ 375 : "r" (base), \
375 "i" (op)); 376 "i" (op));
376 377
378/*
379 * Perform the cache operation specified by op using a user mode virtual
380 * address while in kernel mode.
381 */
382#define cache16_unroll32_user(base,op) \
383 __asm__ __volatile__( \
384 " .set push \n" \
385 " .set noreorder \n" \
386 " .set mips0 \n" \
387 " .set eva \n" \
388 " cachee %1, 0x000(%0); cachee %1, 0x010(%0) \n" \
389 " cachee %1, 0x020(%0); cachee %1, 0x030(%0) \n" \
390 " cachee %1, 0x040(%0); cachee %1, 0x050(%0) \n" \
391 " cachee %1, 0x060(%0); cachee %1, 0x070(%0) \n" \
392 " cachee %1, 0x080(%0); cachee %1, 0x090(%0) \n" \
393 " cachee %1, 0x0a0(%0); cachee %1, 0x0b0(%0) \n" \
394 " cachee %1, 0x0c0(%0); cachee %1, 0x0d0(%0) \n" \
395 " cachee %1, 0x0e0(%0); cachee %1, 0x0f0(%0) \n" \
396 " cachee %1, 0x100(%0); cachee %1, 0x110(%0) \n" \
397 " cachee %1, 0x120(%0); cachee %1, 0x130(%0) \n" \
398 " cachee %1, 0x140(%0); cachee %1, 0x150(%0) \n" \
399 " cachee %1, 0x160(%0); cachee %1, 0x170(%0) \n" \
400 " cachee %1, 0x180(%0); cachee %1, 0x190(%0) \n" \
401 " cachee %1, 0x1a0(%0); cachee %1, 0x1b0(%0) \n" \
402 " cachee %1, 0x1c0(%0); cachee %1, 0x1d0(%0) \n" \
403 " cachee %1, 0x1e0(%0); cachee %1, 0x1f0(%0) \n" \
404 " .set pop \n" \
405 : \
406 : "r" (base), \
407 "i" (op));
408
409#define cache32_unroll32_user(base, op) \
410 __asm__ __volatile__( \
411 " .set push \n" \
412 " .set noreorder \n" \
413 " .set mips0 \n" \
414 " .set eva \n" \
415 " cachee %1, 0x000(%0); cachee %1, 0x020(%0) \n" \
416 " cachee %1, 0x040(%0); cachee %1, 0x060(%0) \n" \
417 " cachee %1, 0x080(%0); cachee %1, 0x0a0(%0) \n" \
418 " cachee %1, 0x0c0(%0); cachee %1, 0x0e0(%0) \n" \
419 " cachee %1, 0x100(%0); cachee %1, 0x120(%0) \n" \
420 " cachee %1, 0x140(%0); cachee %1, 0x160(%0) \n" \
421 " cachee %1, 0x180(%0); cachee %1, 0x1a0(%0) \n" \
422 " cachee %1, 0x1c0(%0); cachee %1, 0x1e0(%0) \n" \
423 " cachee %1, 0x200(%0); cachee %1, 0x220(%0) \n" \
424 " cachee %1, 0x240(%0); cachee %1, 0x260(%0) \n" \
425 " cachee %1, 0x280(%0); cachee %1, 0x2a0(%0) \n" \
426 " cachee %1, 0x2c0(%0); cachee %1, 0x2e0(%0) \n" \
427 " cachee %1, 0x300(%0); cachee %1, 0x320(%0) \n" \
428 " cachee %1, 0x340(%0); cachee %1, 0x360(%0) \n" \
429 " cachee %1, 0x380(%0); cachee %1, 0x3a0(%0) \n" \
430 " cachee %1, 0x3c0(%0); cachee %1, 0x3e0(%0) \n" \
431 " .set pop \n" \
432 : \
433 : "r" (base), \
434 "i" (op));
435
436#define cache64_unroll32_user(base, op) \
437 __asm__ __volatile__( \
438 " .set push \n" \
439 " .set noreorder \n" \
440 " .set mips0 \n" \
441 " .set eva \n" \
442 " cachee %1, 0x000(%0); cachee %1, 0x040(%0) \n" \
443 " cachee %1, 0x080(%0); cachee %1, 0x0c0(%0) \n" \
444 " cachee %1, 0x100(%0); cachee %1, 0x140(%0) \n" \
445 " cachee %1, 0x180(%0); cachee %1, 0x1c0(%0) \n" \
446 " cachee %1, 0x200(%0); cachee %1, 0x240(%0) \n" \
447 " cachee %1, 0x280(%0); cachee %1, 0x2c0(%0) \n" \
448 " cachee %1, 0x300(%0); cachee %1, 0x340(%0) \n" \
449 " cachee %1, 0x380(%0); cachee %1, 0x3c0(%0) \n" \
450 " cachee %1, 0x400(%0); cachee %1, 0x440(%0) \n" \
451 " cachee %1, 0x480(%0); cachee %1, 0x4c0(%0) \n" \
452 " cachee %1, 0x500(%0); cachee %1, 0x540(%0) \n" \
453 " cachee %1, 0x580(%0); cachee %1, 0x5c0(%0) \n" \
454 " cachee %1, 0x600(%0); cachee %1, 0x640(%0) \n" \
455 " cachee %1, 0x680(%0); cachee %1, 0x6c0(%0) \n" \
456 " cachee %1, 0x700(%0); cachee %1, 0x740(%0) \n" \
457 " cachee %1, 0x780(%0); cachee %1, 0x7c0(%0) \n" \
458 " .set pop \n" \
459 : \
460 : "r" (base), \
461 "i" (op));
462
377/* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */ 463/* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
378#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra) \ 464#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra) \
379static inline void extra##blast_##pfx##cache##lsize(void) \ 465static inline void extra##blast_##pfx##cache##lsize(void) \
@@ -447,6 +533,32 @@ __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32
447__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, ) 533__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, )
448__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, ) 534__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, )
449 535
536#define __BUILD_BLAST_USER_CACHE(pfx, desc, indexop, hitop, lsize) \
537static inline void blast_##pfx##cache##lsize##_user_page(unsigned long page) \
538{ \
539 unsigned long start = page; \
540 unsigned long end = page + PAGE_SIZE; \
541 \
542 __##pfx##flush_prologue \
543 \
544 do { \
545 cache##lsize##_unroll32_user(start, hitop); \
546 start += lsize * 32; \
547 } while (start < end); \
548 \
549 __##pfx##flush_epilogue \
550}
551
552__BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D,
553 16)
554__BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16)
555__BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D,
556 32)
557__BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
558__BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D,
559 64)
560__BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
561
450/* build blast_xxx_range, protected_blast_xxx_range */ 562/* build blast_xxx_range, protected_blast_xxx_range */
451#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra) \ 563#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra) \
452static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start, \ 564static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start, \
@@ -468,9 +580,47 @@ static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start,
468 __##pfx##flush_epilogue \ 580 __##pfx##flush_epilogue \
469} 581}
470 582
583#ifndef CONFIG_EVA
584
471__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, ) 585__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, )
472__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, )
473__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, ) 586__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, )
587
588#else
589
590#define __BUILD_PROT_BLAST_CACHE_RANGE(pfx, desc, hitop) \
591static inline void protected_blast_##pfx##cache##_range(unsigned long start,\
592 unsigned long end) \
593{ \
594 unsigned long lsize = cpu_##desc##_line_size(); \
595 unsigned long addr = start & ~(lsize - 1); \
596 unsigned long aend = (end - 1) & ~(lsize - 1); \
597 \
598 __##pfx##flush_prologue \
599 \
600 if (segment_eq(get_fs(), USER_DS)) { \
601 while (1) { \
602 protected_cachee_op(hitop, addr); \
603 if (addr == aend) \
604 break; \
605 addr += lsize; \
606 } \
607 } else { \
608 while (1) { \
609 protected_cache_op(hitop, addr); \
610 if (addr == aend) \
611 break; \
612 addr += lsize; \
613 } \
614 \
615 } \
616 __##pfx##flush_epilogue \
617}
618
619__BUILD_PROT_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D)
620__BUILD_PROT_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I)
621
622#endif
623__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, )
474__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson2, \ 624__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson2, \
475 protected_, loongson2_) 625 protected_, loongson2_)
476__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , ) 626__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , )
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