diff options
author | Heiko Stuebner <heiko@sntech.de> | 2014-11-20 14:38:51 -0500 |
---|---|---|
committer | Heiko Stuebner <heiko@sntech.de> | 2014-11-25 03:57:13 -0500 |
commit | d0e7a0ca4b57483e424334c453818529148baafd (patch) | |
tree | 0ea15bed86188e5a8fb522dd690011c2b6fdcaae | |
parent | 4f8a7c549f373f33c065c9cbb5a5f3f1a9d8f56c (diff) |
clk: rockchip: setup pll_mux data earlier
In some cases we might need to access the data of the pll mux before the actual
mux gets registered - like in the following patch adding an init-callback.
Therefore populate pll_mux before registering the core pll-clock.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
-rw-r--r-- | drivers/clk/rockchip/clk-pll.c | 27 |
1 files changed, 13 insertions, 14 deletions
diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index feb9cad3e676..1bb68910a76b 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c | |||
@@ -349,6 +349,19 @@ struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type, | |||
349 | pll->flags = clk_pll_flags; | 349 | pll->flags = clk_pll_flags; |
350 | pll->lock = lock; | 350 | pll->lock = lock; |
351 | 351 | ||
352 | /* create the mux on top of the real pll */ | ||
353 | pll->pll_mux_ops = &clk_mux_ops; | ||
354 | pll_mux = &pll->pll_mux; | ||
355 | pll_mux->reg = base + mode_offset; | ||
356 | pll_mux->shift = mode_shift; | ||
357 | pll_mux->mask = PLL_MODE_MASK; | ||
358 | pll_mux->flags = 0; | ||
359 | pll_mux->lock = lock; | ||
360 | pll_mux->hw.init = &init; | ||
361 | |||
362 | if (pll_type == pll_rk3066) | ||
363 | pll_mux->flags |= CLK_MUX_HIWORD_MASK; | ||
364 | |||
352 | pll_clk = clk_register(NULL, &pll->hw); | 365 | pll_clk = clk_register(NULL, &pll->hw); |
353 | if (IS_ERR(pll_clk)) { | 366 | if (IS_ERR(pll_clk)) { |
354 | pr_err("%s: failed to register pll clock %s : %ld\n", | 367 | pr_err("%s: failed to register pll clock %s : %ld\n", |
@@ -357,10 +370,6 @@ struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type, | |||
357 | goto err_pll; | 370 | goto err_pll; |
358 | } | 371 | } |
359 | 372 | ||
360 | /* create the mux on top of the real pll */ | ||
361 | pll->pll_mux_ops = &clk_mux_ops; | ||
362 | pll_mux = &pll->pll_mux; | ||
363 | |||
364 | /* the actual muxing is xin24m, pll-output, xin32k */ | 373 | /* the actual muxing is xin24m, pll-output, xin32k */ |
365 | pll_parents[0] = parent_names[0]; | 374 | pll_parents[0] = parent_names[0]; |
366 | pll_parents[1] = pll_name; | 375 | pll_parents[1] = pll_name; |
@@ -372,16 +381,6 @@ struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type, | |||
372 | init.parent_names = pll_parents; | 381 | init.parent_names = pll_parents; |
373 | init.num_parents = ARRAY_SIZE(pll_parents); | 382 | init.num_parents = ARRAY_SIZE(pll_parents); |
374 | 383 | ||
375 | pll_mux->reg = base + mode_offset; | ||
376 | pll_mux->shift = mode_shift; | ||
377 | pll_mux->mask = PLL_MODE_MASK; | ||
378 | pll_mux->flags = 0; | ||
379 | pll_mux->lock = lock; | ||
380 | pll_mux->hw.init = &init; | ||
381 | |||
382 | if (pll_type == pll_rk3066) | ||
383 | pll_mux->flags |= CLK_MUX_HIWORD_MASK; | ||
384 | |||
385 | mux_clk = clk_register(NULL, &pll_mux->hw); | 384 | mux_clk = clk_register(NULL, &pll_mux->hw); |
386 | if (IS_ERR(mux_clk)) | 385 | if (IS_ERR(mux_clk)) |
387 | goto err_mux; | 386 | goto err_mux; |