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authorArnd Bergmann <arnd@arndb.de>2011-12-27 18:56:31 -0500
committerArnd Bergmann <arnd@arndb.de>2011-12-27 18:56:31 -0500
commitcecd902ab4d1c489a121ad4b36f8982842802af5 (patch)
tree3199daf288236296fb8f91579c48274aca4c8a7e
parent7a09266c69e2a0791334600c1ce72200bb679446 (diff)
parenta153e31abb01484d0088ac28425dc98204848ad4 (diff)
Merge branch 'next-samsung-devel-spi3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into samsung/cleanup
Diffstat
-rw-r--r--arch/arm/mach-s3c64xx/clock.c80
-rw-r--r--arch/arm/mach-s3c64xx/dev-spi.c7
-rw-r--r--arch/arm/mach-s5p64x0/clock-s5p6440.c61
-rw-r--r--arch/arm/mach-s5p64x0/clock-s5p6450.c49
-rw-r--r--arch/arm/mach-s5p64x0/dev-spi.c6
-rw-r--r--arch/arm/mach-s5pc100/clock.c124
-rw-r--r--arch/arm/mach-s5pc100/dev-spi.c7
-rw-r--r--arch/arm/mach-s5pv210/clock.c50
-rw-r--r--arch/arm/mach-s5pv210/dev-spi.c6
-rw-r--r--arch/arm/plat-samsung/include/plat/s3c64xx-spi.h2
-rw-r--r--drivers/spi/spi-s3c64xx.c14
11 files changed, 215 insertions, 191 deletions
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index 415c5406b17c..0187cde3a5dc 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -184,18 +184,6 @@ static struct clk init_clocks_off[] = {
184 .enable = s3c64xx_pclk_ctrl, 184 .enable = s3c64xx_pclk_ctrl,
185 .ctrlbit = S3C_CLKCON_PCLK_SPI1, 185 .ctrlbit = S3C_CLKCON_PCLK_SPI1,
186 }, { 186 }, {
187 .name = "spi_48m",
188 .devname = "s3c64xx-spi.0",
189 .parent = &clk_48m,
190 .enable = s3c64xx_sclk_ctrl,
191 .ctrlbit = S3C_CLKCON_SCLK_SPI0_48,
192 }, {
193 .name = "spi_48m",
194 .devname = "s3c64xx-spi.1",
195 .parent = &clk_48m,
196 .enable = s3c64xx_sclk_ctrl,
197 .ctrlbit = S3C_CLKCON_SCLK_SPI1_48,
198 }, {
199 .name = "48m", 187 .name = "48m",
200 .devname = "s3c-sdhci.0", 188 .devname = "s3c-sdhci.0",
201 .parent = &clk_48m, 189 .parent = &clk_48m,
@@ -226,6 +214,22 @@ static struct clk init_clocks_off[] = {
226 }, 214 },
227}; 215};
228 216
217static struct clk clk_48m_spi0 = {
218 .name = "spi_48m",
219 .devname = "s3c64xx-spi.0",
220 .parent = &clk_48m,
221 .enable = s3c64xx_sclk_ctrl,
222 .ctrlbit = S3C_CLKCON_SCLK_SPI0_48,
223};
224
225static struct clk clk_48m_spi1 = {
226 .name = "spi_48m",
227 .devname = "s3c64xx-spi.1",
228 .parent = &clk_48m,
229 .enable = s3c64xx_sclk_ctrl,
230 .ctrlbit = S3C_CLKCON_SCLK_SPI1_48,
231};
232
229static struct clk init_clocks[] = { 233static struct clk init_clocks[] = {
230 { 234 {
231 .name = "lcd", 235 .name = "lcd",
@@ -592,25 +596,6 @@ static struct clksrc_clk clksrcs[] = {
592 .sources = &clkset_uhost, 596 .sources = &clkset_uhost,
593 }, { 597 }, {
594 .clk = { 598 .clk = {
595 .name = "spi-bus",
596 .devname = "s3c64xx-spi.0",
597 .ctrlbit = S3C_CLKCON_SCLK_SPI0,
598 .enable = s3c64xx_sclk_ctrl,
599 },
600 .reg_src = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2 },
601 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4 },
602 .sources = &clkset_spi_mmc,
603 }, {
604 .clk = {
605 .name = "spi-bus",
606 .devname = "s3c64xx-spi.1",
607 .enable = s3c64xx_sclk_ctrl,
608 },
609 .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 },
610 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4 },
611 .sources = &clkset_spi_mmc,
612 }, {
613 .clk = {
614 .name = "audio-bus", 599 .name = "audio-bus",
615 .devname = "samsung-i2s.0", 600 .devname = "samsung-i2s.0",
616 .ctrlbit = S3C_CLKCON_SCLK_AUDIO0, 601 .ctrlbit = S3C_CLKCON_SCLK_AUDIO0,
@@ -708,6 +693,30 @@ static struct clksrc_clk clk_sclk_mmc2 = {
708 .sources = &clkset_spi_mmc, 693 .sources = &clkset_spi_mmc,
709}; 694};
710 695
696static struct clksrc_clk clk_sclk_spi0 = {
697 .clk = {
698 .name = "spi-bus",
699 .devname = "s3c64xx-spi.0",
700 .ctrlbit = S3C_CLKCON_SCLK_SPI0,
701 .enable = s3c64xx_sclk_ctrl,
702 },
703 .reg_src = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2 },
704 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4 },
705 .sources = &clkset_spi_mmc,
706};
707
708static struct clksrc_clk clk_sclk_spi1 = {
709 .clk = {
710 .name = "spi-bus",
711 .devname = "s3c64xx-spi.1",
712 .ctrlbit = S3C_CLKCON_SCLK_SPI1,
713 .enable = s3c64xx_sclk_ctrl,
714 },
715 .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 },
716 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4 },
717 .sources = &clkset_spi_mmc,
718};
719
711/* Clock initialisation code */ 720/* Clock initialisation code */
712 721
713static struct clksrc_clk *init_parents[] = { 722static struct clksrc_clk *init_parents[] = {
@@ -721,12 +730,16 @@ static struct clksrc_clk *clksrc_cdev[] = {
721 &clk_sclk_mmc0, 730 &clk_sclk_mmc0,
722 &clk_sclk_mmc1, 731 &clk_sclk_mmc1,
723 &clk_sclk_mmc2, 732 &clk_sclk_mmc2,
733 &clk_sclk_spi0,
734 &clk_sclk_spi1,
724}; 735};
725 736
726static struct clk *clk_cdev[] = { 737static struct clk *clk_cdev[] = {
727 &clk_hsmmc0, 738 &clk_hsmmc0,
728 &clk_hsmmc1, 739 &clk_hsmmc1,
729 &clk_hsmmc2, 740 &clk_hsmmc2,
741 &clk_48m_spi0,
742 &clk_48m_spi1,
730}; 743};
731 744
732static struct clk_lookup s3c64xx_clk_lookup[] = { 745static struct clk_lookup s3c64xx_clk_lookup[] = {
@@ -738,6 +751,11 @@ static struct clk_lookup s3c64xx_clk_lookup[] = {
738 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), 751 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
739 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), 752 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
740 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), 753 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
754 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
755 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
756 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_48m_spi0),
757 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
758 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_48m_spi1),
741}; 759};
742 760
743#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) 761#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
diff --git a/arch/arm/mach-s3c64xx/dev-spi.c b/arch/arm/mach-s3c64xx/dev-spi.c
index 3341fd118723..3f437e7a6ba5 100644
--- a/arch/arm/mach-s3c64xx/dev-spi.c
+++ b/arch/arm/mach-s3c64xx/dev-spi.c
@@ -24,12 +24,6 @@
24#include <plat/gpio-cfg.h> 24#include <plat/gpio-cfg.h>
25#include <plat/devs.h> 25#include <plat/devs.h>
26 26
27static char *spi_src_clks[] = {
28 [S3C64XX_SPI_SRCCLK_PCLK] = "pclk",
29 [S3C64XX_SPI_SRCCLK_SPIBUS] = "spi-bus",
30 [S3C64XX_SPI_SRCCLK_48M] = "spi_48m",
31};
32
33/* SPI Controller platform_devices */ 27/* SPI Controller platform_devices */
34 28
35/* Since we emulate multi-cs capability, we do not touch the GPC-3,7. 29/* Since we emulate multi-cs capability, we do not touch the GPC-3,7.
@@ -176,5 +170,4 @@ void __init s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
176 170
177 pd->num_cs = num_cs; 171 pd->num_cs = num_cs;
178 pd->src_clk_nr = src_clk_nr; 172 pd->src_clk_nr = src_clk_nr;
179 pd->src_clk_name = spi_src_clks[src_clk_nr];
180} 173}
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
index bfb1917ad0da..73c7cc9ef0dd 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -268,18 +268,6 @@ static struct clk init_clocks_off[] = {
268 .enable = s5p64x0_pclk_ctrl, 268 .enable = s5p64x0_pclk_ctrl,
269 .ctrlbit = (1 << 31), 269 .ctrlbit = (1 << 31),
270 }, { 270 }, {
271 .name = "sclk_spi_48",
272 .devname = "s3c64xx-spi.0",
273 .parent = &clk_48m,
274 .enable = s5p64x0_sclk_ctrl,
275 .ctrlbit = (1 << 22),
276 }, {
277 .name = "sclk_spi_48",
278 .devname = "s3c64xx-spi.1",
279 .parent = &clk_48m,
280 .enable = s5p64x0_sclk_ctrl,
281 .ctrlbit = (1 << 23),
282 }, {
283 .name = "mmc_48m", 271 .name = "mmc_48m",
284 .devname = "s3c-sdhci.0", 272 .devname = "s3c-sdhci.0",
285 .parent = &clk_48m, 273 .parent = &clk_48m,
@@ -421,26 +409,6 @@ static struct clksrc_clk clksrcs[] = {
421 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 }, 409 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
422 }, { 410 }, {
423 .clk = { 411 .clk = {
424 .name = "sclk_spi",
425 .devname = "s3c64xx-spi.0",
426 .ctrlbit = (1 << 20),
427 .enable = s5p64x0_sclk_ctrl,
428 },
429 .sources = &clkset_group1,
430 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
431 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
432 }, {
433 .clk = {
434 .name = "sclk_spi",
435 .devname = "s3c64xx-spi.1",
436 .ctrlbit = (1 << 21),
437 .enable = s5p64x0_sclk_ctrl,
438 },
439 .sources = &clkset_group1,
440 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
441 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
442 }, {
443 .clk = {
444 .name = "sclk_post", 412 .name = "sclk_post",
445 .ctrlbit = (1 << 10), 413 .ctrlbit = (1 << 10),
446 .enable = s5p64x0_sclk_ctrl, 414 .enable = s5p64x0_sclk_ctrl,
@@ -489,6 +457,30 @@ static struct clksrc_clk clk_sclk_uclk = {
489 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 }, 457 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
490}; 458};
491 459
460static struct clksrc_clk clk_sclk_spi0 = {
461 .clk = {
462 .name = "sclk_spi",
463 .devname = "s3c64xx-spi.0",
464 .ctrlbit = (1 << 20),
465 .enable = s5p64x0_sclk_ctrl,
466 },
467 .sources = &clkset_group1,
468 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
469 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
470};
471
472static struct clksrc_clk clk_sclk_spi1 = {
473 .clk = {
474 .name = "sclk_spi",
475 .devname = "s3c64xx-spi.1",
476 .ctrlbit = (1 << 21),
477 .enable = s5p64x0_sclk_ctrl,
478 },
479 .sources = &clkset_group1,
480 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
481 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
482};
483
492/* Clock initialization code */ 484/* Clock initialization code */
493static struct clksrc_clk *sysclks[] = { 485static struct clksrc_clk *sysclks[] = {
494 &clk_mout_apll, 486 &clk_mout_apll,
@@ -509,11 +501,16 @@ static struct clk dummy_apb_pclk = {
509 501
510static struct clksrc_clk *clksrc_cdev[] = { 502static struct clksrc_clk *clksrc_cdev[] = {
511 &clk_sclk_uclk, 503 &clk_sclk_uclk,
504 &clk_sclk_spi0,
505 &clk_sclk_spi1,
512}; 506};
513 507
514static struct clk_lookup s5p6440_clk_lookup[] = { 508static struct clk_lookup s5p6440_clk_lookup[] = {
515 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk), 509 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
516 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk), 510 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
511 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
512 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
513 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
517}; 514};
518 515
519void __init_or_cpufreq s5p6440_setup_clocks(void) 516void __init_or_cpufreq s5p6440_setup_clocks(void)
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
index d132638c7b23..50f90cbf7798 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
@@ -443,26 +443,6 @@ static struct clksrc_clk clksrcs[] = {
443 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 }, 443 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
444 }, { 444 }, {
445 .clk = { 445 .clk = {
446 .name = "sclk_spi",
447 .devname = "s3c64xx-spi.0",
448 .ctrlbit = (1 << 20),
449 .enable = s5p64x0_sclk_ctrl,
450 },
451 .sources = &clkset_group2,
452 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
453 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
454 }, {
455 .clk = {
456 .name = "sclk_spi",
457 .devname = "s3c64xx-spi.1",
458 .ctrlbit = (1 << 21),
459 .enable = s5p64x0_sclk_ctrl,
460 },
461 .sources = &clkset_group2,
462 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
463 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
464 }, {
465 .clk = {
466 .name = "sclk_fimc", 446 .name = "sclk_fimc",
467 .ctrlbit = (1 << 10), 447 .ctrlbit = (1 << 10),
468 .enable = s5p64x0_sclk_ctrl, 448 .enable = s5p64x0_sclk_ctrl,
@@ -538,13 +518,42 @@ static struct clksrc_clk clk_sclk_uclk = {
538 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 }, 518 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
539}; 519};
540 520
521static struct clksrc_clk clk_sclk_spi0 = {
522 .clk = {
523 .name = "sclk_spi",
524 .devname = "s3c64xx-spi.0",
525 .ctrlbit = (1 << 20),
526 .enable = s5p64x0_sclk_ctrl,
527 },
528 .sources = &clkset_group2,
529 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
530 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
531};
532
533static struct clksrc_clk clk_sclk_spi1 = {
534 .clk = {
535 .name = "sclk_spi",
536 .devname = "s3c64xx-spi.1",
537 .ctrlbit = (1 << 21),
538 .enable = s5p64x0_sclk_ctrl,
539 },
540 .sources = &clkset_group2,
541 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
542 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
543};
544
541static struct clksrc_clk *clksrc_cdev[] = { 545static struct clksrc_clk *clksrc_cdev[] = {
542 &clk_sclk_uclk, 546 &clk_sclk_uclk,
547 &clk_sclk_spi0,
548 &clk_sclk_spi1,
543}; 549};
544 550
545static struct clk_lookup s5p6450_clk_lookup[] = { 551static struct clk_lookup s5p6450_clk_lookup[] = {
546 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk), 552 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
547 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk), 553 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
554 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
555 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
556 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
548}; 557};
549 558
550/* Clock initialization code */ 559/* Clock initialization code */
diff --git a/arch/arm/mach-s5p64x0/dev-spi.c b/arch/arm/mach-s5p64x0/dev-spi.c
index 1fd9c79c7dbc..5b5d3c083644 100644
--- a/arch/arm/mach-s5p64x0/dev-spi.c
+++ b/arch/arm/mach-s5p64x0/dev-spi.c
@@ -25,11 +25,6 @@
25#include <plat/s3c64xx-spi.h> 25#include <plat/s3c64xx-spi.h>
26#include <plat/gpio-cfg.h> 26#include <plat/gpio-cfg.h>
27 27
28static char *s5p64x0_spi_src_clks[] = {
29 [S5P64X0_SPI_SRCCLK_PCLK] = "pclk",
30 [S5P64X0_SPI_SRCCLK_SCLK] = "sclk_spi",
31};
32
33/* SPI Controller platform_devices */ 28/* SPI Controller platform_devices */
34 29
35/* Since we emulate multi-cs capability, we do not touch the CS. 30/* Since we emulate multi-cs capability, we do not touch the CS.
@@ -220,5 +215,4 @@ void __init s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
220 215
221 pd->num_cs = num_cs; 216 pd->num_cs = num_cs;
222 pd->src_clk_nr = src_clk_nr; 217 pd->src_clk_nr = src_clk_nr;
223 pd->src_clk_name = s5p64x0_spi_src_clks[src_clk_nr];
224} 218}
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
index 69829ba9c01b..eba721b551fc 100644
--- a/arch/arm/mach-s5pc100/clock.c
+++ b/arch/arm/mach-s5pc100/clock.c
@@ -655,24 +655,6 @@ static struct clk init_clocks_off[] = {
655 .enable = s5pc100_d1_5_ctrl, 655 .enable = s5pc100_d1_5_ctrl,
656 .ctrlbit = (1 << 8), 656 .ctrlbit = (1 << 8),
657 }, { 657 }, {
658 .name = "spi_48m",
659 .devname = "s3c64xx-spi.0",
660 .parent = &clk_mout_48m.clk,
661 .enable = s5pc100_sclk0_ctrl,
662 .ctrlbit = (1 << 7),
663 }, {
664 .name = "spi_48m",
665 .devname = "s3c64xx-spi.1",
666 .parent = &clk_mout_48m.clk,
667 .enable = s5pc100_sclk0_ctrl,
668 .ctrlbit = (1 << 8),
669 }, {
670 .name = "spi_48m",
671 .devname = "s3c64xx-spi.2",
672 .parent = &clk_mout_48m.clk,
673 .enable = s5pc100_sclk0_ctrl,
674 .ctrlbit = (1 << 9),
675 }, {
676 .name = "mmc_48m", 658 .name = "mmc_48m",
677 .devname = "s3c-sdhci.0", 659 .devname = "s3c-sdhci.0",
678 .parent = &clk_mout_48m.clk, 660 .parent = &clk_mout_48m.clk,
@@ -717,6 +699,30 @@ static struct clk clk_hsmmc0 = {
717 .ctrlbit = (1 << 5), 699 .ctrlbit = (1 << 5),
718}; 700};
719 701
702static struct clk clk_48m_spi0 = {
703 .name = "spi_48m",
704 .devname = "s3c64xx-spi.0",
705 .parent = &clk_mout_48m.clk,
706 .enable = s5pc100_sclk0_ctrl,
707 .ctrlbit = (1 << 7),
708};
709
710static struct clk clk_48m_spi1 = {
711 .name = "spi_48m",
712 .devname = "s3c64xx-spi.1",
713 .parent = &clk_mout_48m.clk,
714 .enable = s5pc100_sclk0_ctrl,
715 .ctrlbit = (1 << 8),
716};
717
718static struct clk clk_48m_spi2 = {
719 .name = "spi_48m",
720 .devname = "s3c64xx-spi.2",
721 .parent = &clk_mout_48m.clk,
722 .enable = s5pc100_sclk0_ctrl,
723 .ctrlbit = (1 << 9),
724};
725
720static struct clk clk_vclk54m = { 726static struct clk clk_vclk54m = {
721 .name = "vclk_54m", 727 .name = "vclk_54m",
722 .rate = 54000000, 728 .rate = 54000000,
@@ -935,39 +941,6 @@ static struct clksrc_clk clk_sclk_spdif = {
935static struct clksrc_clk clksrcs[] = { 941static struct clksrc_clk clksrcs[] = {
936 { 942 {
937 .clk = { 943 .clk = {
938 .name = "sclk_spi",
939 .devname = "s3c64xx-spi.0",
940 .ctrlbit = (1 << 4),
941 .enable = s5pc100_sclk0_ctrl,
942
943 },
944 .sources = &clk_src_group1,
945 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
946 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
947 }, {
948 .clk = {
949 .name = "sclk_spi",
950 .devname = "s3c64xx-spi.1",
951 .ctrlbit = (1 << 5),
952 .enable = s5pc100_sclk0_ctrl,
953
954 },
955 .sources = &clk_src_group1,
956 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
957 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
958 }, {
959 .clk = {
960 .name = "sclk_spi",
961 .devname = "s3c64xx-spi.2",
962 .ctrlbit = (1 << 6),
963 .enable = s5pc100_sclk0_ctrl,
964
965 },
966 .sources = &clk_src_group1,
967 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 2 },
968 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 },
969 }, {
970 .clk = {
971 .name = "sclk_mixer", 944 .name = "sclk_mixer",
972 .ctrlbit = (1 << 6), 945 .ctrlbit = (1 << 6),
973 .enable = s5pc100_sclk0_ctrl, 946 .enable = s5pc100_sclk0_ctrl,
@@ -1108,6 +1081,42 @@ static struct clksrc_clk clk_sclk_mmc2 = {
1108 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 }, 1081 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
1109}; 1082};
1110 1083
1084static struct clksrc_clk clk_sclk_spi0 = {
1085 .clk = {
1086 .name = "sclk_spi",
1087 .devname = "s3c64xx-spi.0",
1088 .ctrlbit = (1 << 4),
1089 .enable = s5pc100_sclk0_ctrl,
1090 },
1091 .sources = &clk_src_group1,
1092 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
1093 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
1094};
1095
1096static struct clksrc_clk clk_sclk_spi1 = {
1097 .clk = {
1098 .name = "sclk_spi",
1099 .devname = "s3c64xx-spi.1",
1100 .ctrlbit = (1 << 5),
1101 .enable = s5pc100_sclk0_ctrl,
1102 },
1103 .sources = &clk_src_group1,
1104 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
1105 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
1106};
1107
1108static struct clksrc_clk clk_sclk_spi2 = {
1109 .clk = {
1110 .name = "sclk_spi",
1111 .devname = "s3c64xx-spi.2",
1112 .ctrlbit = (1 << 6),
1113 .enable = s5pc100_sclk0_ctrl,
1114 },
1115 .sources = &clk_src_group1,
1116 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 2 },
1117 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 },
1118};
1119
1111/* Clock initialisation code */ 1120/* Clock initialisation code */
1112static struct clksrc_clk *sysclks[] = { 1121static struct clksrc_clk *sysclks[] = {
1113 &clk_mout_apll, 1122 &clk_mout_apll,
@@ -1141,6 +1150,9 @@ static struct clk *clk_cdev[] = {
1141 &clk_hsmmc0, 1150 &clk_hsmmc0,
1142 &clk_hsmmc1, 1151 &clk_hsmmc1,
1143 &clk_hsmmc2, 1152 &clk_hsmmc2,
1153 &clk_48m_spi0,
1154 &clk_48m_spi1,
1155 &clk_48m_spi2,
1144}; 1156};
1145 1157
1146static struct clksrc_clk *clksrc_cdev[] = { 1158static struct clksrc_clk *clksrc_cdev[] = {
@@ -1148,6 +1160,9 @@ static struct clksrc_clk *clksrc_cdev[] = {
1148 &clk_sclk_mmc0, 1160 &clk_sclk_mmc0,
1149 &clk_sclk_mmc1, 1161 &clk_sclk_mmc1,
1150 &clk_sclk_mmc2, 1162 &clk_sclk_mmc2,
1163 &clk_sclk_spi0,
1164 &clk_sclk_spi1,
1165 &clk_sclk_spi2,
1151}; 1166};
1152 1167
1153void __init_or_cpufreq s5pc100_setup_clocks(void) 1168void __init_or_cpufreq s5pc100_setup_clocks(void)
@@ -1298,6 +1313,13 @@ static struct clk_lookup s5pc100_clk_lookup[] = {
1298 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), 1313 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
1299 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), 1314 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
1300 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), 1315 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
1316 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
1317 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_48m_spi0),
1318 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_sclk_spi0.clk),
1319 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_48m_spi1),
1320 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_sclk_spi1.clk),
1321 CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk1", &clk_48m_spi2),
1322 CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk2", &clk_sclk_spi2.clk),
1301}; 1323};
1302 1324
1303void __init s5pc100_register_clocks(void) 1325void __init s5pc100_register_clocks(void)
diff --git a/arch/arm/mach-s5pc100/dev-spi.c b/arch/arm/mach-s5pc100/dev-spi.c
index e5d6c4dceb56..155f50da2d78 100644
--- a/arch/arm/mach-s5pc100/dev-spi.c
+++ b/arch/arm/mach-s5pc100/dev-spi.c
@@ -21,12 +21,6 @@
21#include <plat/gpio-cfg.h> 21#include <plat/gpio-cfg.h>
22#include <plat/irqs.h> 22#include <plat/irqs.h>
23 23
24static char *spi_src_clks[] = {
25 [S5PC100_SPI_SRCCLK_PCLK] = "pclk",
26 [S5PC100_SPI_SRCCLK_48M] = "spi_48m",
27 [S5PC100_SPI_SRCCLK_SPIBUS] = "spi_bus",
28};
29
30/* SPI Controller platform_devices */ 24/* SPI Controller platform_devices */
31 25
32/* Since we emulate multi-cs capability, we do not touch the CS. 26/* Since we emulate multi-cs capability, we do not touch the CS.
@@ -223,5 +217,4 @@ void __init s5pc100_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
223 217
224 pd->num_cs = num_cs; 218 pd->num_cs = num_cs;
225 pd->src_clk_nr = src_clk_nr; 219 pd->src_clk_nr = src_clk_nr;
226 pd->src_clk_name = spi_src_clks[src_clk_nr];
227} 220}
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index dc4586b2b322..cead51321b29 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -911,26 +911,6 @@ static struct clksrc_clk clksrcs[] = {
911 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 }, 911 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 },
912 }, { 912 }, {
913 .clk = { 913 .clk = {
914 .name = "sclk_spi",
915 .devname = "s3c64xx-spi.0",
916 .enable = s5pv210_clk_mask0_ctrl,
917 .ctrlbit = (1 << 16),
918 },
919 .sources = &clkset_group2,
920 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
921 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
922 }, {
923 .clk = {
924 .name = "sclk_spi",
925 .devname = "s3c64xx-spi.1",
926 .enable = s5pv210_clk_mask0_ctrl,
927 .ctrlbit = (1 << 17),
928 },
929 .sources = &clkset_group2,
930 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
931 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
932 }, {
933 .clk = {
934 .name = "sclk_pwi", 914 .name = "sclk_pwi",
935 .enable = s5pv210_clk_mask0_ctrl, 915 .enable = s5pv210_clk_mask0_ctrl,
936 .ctrlbit = (1 << 29), 916 .ctrlbit = (1 << 29),
@@ -1046,6 +1026,31 @@ static struct clksrc_clk clk_sclk_mmc3 = {
1046 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 }, 1026 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
1047}; 1027};
1048 1028
1029static struct clksrc_clk clk_sclk_spi0 = {
1030 .clk = {
1031 .name = "sclk_spi",
1032 .devname = "s3c64xx-spi.0",
1033 .enable = s5pv210_clk_mask0_ctrl,
1034 .ctrlbit = (1 << 16),
1035 },
1036 .sources = &clkset_group2,
1037 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
1038 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
1039 };
1040
1041static struct clksrc_clk clk_sclk_spi1 = {
1042 .clk = {
1043 .name = "sclk_spi",
1044 .devname = "s3c64xx-spi.1",
1045 .enable = s5pv210_clk_mask0_ctrl,
1046 .ctrlbit = (1 << 17),
1047 },
1048 .sources = &clkset_group2,
1049 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
1050 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
1051 };
1052
1053
1049static struct clksrc_clk *clksrc_cdev[] = { 1054static struct clksrc_clk *clksrc_cdev[] = {
1050 &clk_sclk_uart0, 1055 &clk_sclk_uart0,
1051 &clk_sclk_uart1, 1056 &clk_sclk_uart1,
@@ -1055,6 +1060,8 @@ static struct clksrc_clk *clksrc_cdev[] = {
1055 &clk_sclk_mmc1, 1060 &clk_sclk_mmc1,
1056 &clk_sclk_mmc2, 1061 &clk_sclk_mmc2,
1057 &clk_sclk_mmc3, 1062 &clk_sclk_mmc3,
1063 &clk_sclk_spi0,
1064 &clk_sclk_spi1,
1058}; 1065};
1059 1066
1060static struct clk *clk_cdev[] = { 1067static struct clk *clk_cdev[] = {
@@ -1317,6 +1324,9 @@ static struct clk_lookup s5pv210_clk_lookup[] = {
1317 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), 1324 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
1318 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), 1325 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
1319 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk), 1326 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
1327 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
1328 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
1329 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
1320}; 1330};
1321 1331
1322void __init s5pv210_register_clocks(void) 1332void __init s5pv210_register_clocks(void)
diff --git a/arch/arm/mach-s5pv210/dev-spi.c b/arch/arm/mach-s5pv210/dev-spi.c
index eaf9a7bff7a0..39bef19dbd68 100644
--- a/arch/arm/mach-s5pv210/dev-spi.c
+++ b/arch/arm/mach-s5pv210/dev-spi.c
@@ -20,11 +20,6 @@
20#include <plat/s3c64xx-spi.h> 20#include <plat/s3c64xx-spi.h>
21#include <plat/gpio-cfg.h> 21#include <plat/gpio-cfg.h>
22 22
23static char *spi_src_clks[] = {
24 [S5PV210_SPI_SRCCLK_PCLK] = "pclk",
25 [S5PV210_SPI_SRCCLK_SCLK] = "sclk_spi",
26};
27
28/* SPI Controller platform_devices */ 23/* SPI Controller platform_devices */
29 24
30/* Since we emulate multi-cs capability, we do not touch the CS. 25/* Since we emulate multi-cs capability, we do not touch the CS.
@@ -171,5 +166,4 @@ void __init s5pv210_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
171 166
172 pd->num_cs = num_cs; 167 pd->num_cs = num_cs;
173 pd->src_clk_nr = src_clk_nr; 168 pd->src_clk_nr = src_clk_nr;
174 pd->src_clk_name = spi_src_clks[src_clk_nr];
175} 169}
diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
index 4c16fa3621bb..c3d82a5f5630 100644
--- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
+++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
@@ -31,7 +31,6 @@ struct s3c64xx_spi_csinfo {
31/** 31/**
32 * struct s3c64xx_spi_info - SPI Controller defining structure 32 * struct s3c64xx_spi_info - SPI Controller defining structure
33 * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field. 33 * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field.
34 * @src_clk_name: Platform name of the corresponding clock.
35 * @clk_from_cmu: If the SPI clock/prescalar control block is present 34 * @clk_from_cmu: If the SPI clock/prescalar control block is present
36 * by the platform's clock-management-unit and not in SPI controller. 35 * by the platform's clock-management-unit and not in SPI controller.
37 * @num_cs: Number of CS this controller emulates. 36 * @num_cs: Number of CS this controller emulates.
@@ -43,7 +42,6 @@ struct s3c64xx_spi_csinfo {
43 */ 42 */
44struct s3c64xx_spi_info { 43struct s3c64xx_spi_info {
45 int src_clk_nr; 44 int src_clk_nr;
46 char *src_clk_name;
47 bool clk_from_cmu; 45 bool clk_from_cmu;
48 46
49 int num_cs; 47 int num_cs;
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index 019a7163572f..dcf7e1006426 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -971,6 +971,7 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev)
971 struct s3c64xx_spi_info *sci; 971 struct s3c64xx_spi_info *sci;
972 struct spi_master *master; 972 struct spi_master *master;
973 int ret; 973 int ret;
974 char clk_name[16];
974 975
975 if (pdev->id < 0) { 976 if (pdev->id < 0) {
976 dev_err(&pdev->dev, 977 dev_err(&pdev->dev,
@@ -984,11 +985,6 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev)
984 } 985 }
985 986
986 sci = pdev->dev.platform_data; 987 sci = pdev->dev.platform_data;
987 if (!sci->src_clk_name) {
988 dev_err(&pdev->dev,
989 "Board init must call s3c64xx_spi_set_info()\n");
990 return -EINVAL;
991 }
992 988
993 /* Check for availability of necessary resource */ 989 /* Check for availability of necessary resource */
994 990
@@ -1073,17 +1069,17 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev)
1073 goto err4; 1069 goto err4;
1074 } 1070 }
1075 1071
1076 sdd->src_clk = clk_get(&pdev->dev, sci->src_clk_name); 1072 sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
1073 sdd->src_clk = clk_get(&pdev->dev, clk_name);
1077 if (IS_ERR(sdd->src_clk)) { 1074 if (IS_ERR(sdd->src_clk)) {
1078 dev_err(&pdev->dev, 1075 dev_err(&pdev->dev,
1079 "Unable to acquire clock '%s'\n", sci->src_clk_name); 1076 "Unable to acquire clock '%s'\n", clk_name);
1080 ret = PTR_ERR(sdd->src_clk); 1077 ret = PTR_ERR(sdd->src_clk);
1081 goto err5; 1078 goto err5;
1082 } 1079 }
1083 1080
1084 if (clk_enable(sdd->src_clk)) { 1081 if (clk_enable(sdd->src_clk)) {
1085 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", 1082 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
1086 sci->src_clk_name);
1087 ret = -EBUSY; 1083 ret = -EBUSY;
1088 goto err6; 1084 goto err6;
1089 } 1085 }
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-09 00:14:50 -0500