MIPS: Loongson: Fix the write-combine CCA value setting

All Loongson-2/3 processors support _CACHE_UNCACHED_ACCELERATED, not
only Loongson-3A.

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Cc: John Crispin <john@phrozen.org>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/8319/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 1 insertions, 1 deletions

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 94c4a0c0a577..08dc945f7608 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -765,7 +765,6 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
                         break;
                 case PRID_REV_LOONGSON3A:
                         c->cputype = CPU_LOONGSON3;
-                        c->writecombine = _CACHE_UNCACHED_ACCELERATED;
                         __cpu_name[cpu] = "ICT Loongson-3";
                         set_elf_platform(cpu, "loongson3a");
                         break;
@@ -782,6 +781,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
                              MIPS_CPU_FPU | MIPS_CPU_LLSC |
                              MIPS_CPU_32FPR;
                 c->tlbsize = 64;
+                c->writecombine = _CACHE_UNCACHED_ACCELERATED;
                 break;
         case PRID_IMP_LOONGSON_32:  /* Loongson-1 */
                 decode_configs(c);