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authorGuenter Roeck <linux@roeck-us.net>2012-01-14 16:25:01 -0500
committerGuenter Roeck <guenter.roeck@ericsson.com>2012-03-18 21:27:21 -0400
commitc8de83624c33b2f5dc6ba497477fc2019b547949 (patch)
tree9defdec308ed8ed012fe8594a407fb997803d9be
parent8c103696fa59e1b810bf24a63304acd5ab585c12 (diff)
hwmon: (dme1737) Fix checkpatch issues
Fixed: WARNING: braces {} are not necessary for any arm of this statement WARNING: braces {} are not necessary for single statement blocks WARNING: simple_strtol is obsolete, use kstrtol instead Modify multi-line comments to follow Documentation/CodingStyle. Also: s/#define^I/#define / Not fixed (false positive): ERROR: Macros with multiple statements should be enclosed in a do - while loop Cc: Juerg Haefliger <juergh@gmail.com> Signed-off-by: Guenter Roeck <linux@roeck-us.net>
-rw-r--r--drivers/hwmon/dme1737.c506
1 files changed, 290 insertions, 216 deletions
diff --git a/drivers/hwmon/dme1737.c b/drivers/hwmon/dme1737.c
index ffb229af7861..e7c6a19f3b25 100644
--- a/drivers/hwmon/dme1737.c
+++ b/drivers/hwmon/dme1737.c
@@ -82,12 +82,12 @@ enum chips { dme1737, sch5027, sch311x, sch5127 };
82 * --------------------------------------------------------------------- */ 82 * --------------------------------------------------------------------- */
83 83
84/* Voltages (in) numbered 0-7 (ix) */ 84/* Voltages (in) numbered 0-7 (ix) */
85#define DME1737_REG_IN(ix) ((ix) < 5 ? 0x20 + (ix) : \ 85#define DME1737_REG_IN(ix) ((ix) < 5 ? 0x20 + (ix) : \
86 (ix) < 7 ? 0x94 + (ix) : \ 86 (ix) < 7 ? 0x94 + (ix) : \
87 0x1f) 87 0x1f)
88#define DME1737_REG_IN_MIN(ix) ((ix) < 5 ? 0x44 + (ix) * 2 \ 88#define DME1737_REG_IN_MIN(ix) ((ix) < 5 ? 0x44 + (ix) * 2 \
89 : 0x91 + (ix) * 2) 89 : 0x91 + (ix) * 2)
90#define DME1737_REG_IN_MAX(ix) ((ix) < 5 ? 0x45 + (ix) * 2 \ 90#define DME1737_REG_IN_MAX(ix) ((ix) < 5 ? 0x45 + (ix) * 2 \
91 : 0x92 + (ix) * 2) 91 : 0x92 + (ix) * 2)
92 92
93/* Temperatures (temp) numbered 0-2 (ix) */ 93/* Temperatures (temp) numbered 0-2 (ix) */
@@ -97,14 +97,16 @@ enum chips { dme1737, sch5027, sch311x, sch5127 };
97#define DME1737_REG_TEMP_OFFSET(ix) ((ix) == 0 ? 0x1f \ 97#define DME1737_REG_TEMP_OFFSET(ix) ((ix) == 0 ? 0x1f \
98 : 0x1c + (ix)) 98 : 0x1c + (ix))
99 99
100/* Voltage and temperature LSBs 100/*
101 * Voltage and temperature LSBs
101 * The LSBs (4 bits each) are stored in 5 registers with the following layouts: 102 * The LSBs (4 bits each) are stored in 5 registers with the following layouts:
102 * IN_TEMP_LSB(0) = [in5, in6] 103 * IN_TEMP_LSB(0) = [in5, in6]
103 * IN_TEMP_LSB(1) = [temp3, temp1] 104 * IN_TEMP_LSB(1) = [temp3, temp1]
104 * IN_TEMP_LSB(2) = [in4, temp2] 105 * IN_TEMP_LSB(2) = [in4, temp2]
105 * IN_TEMP_LSB(3) = [in3, in0] 106 * IN_TEMP_LSB(3) = [in3, in0]
106 * IN_TEMP_LSB(4) = [in2, in1] 107 * IN_TEMP_LSB(4) = [in2, in1]
107 * IN_TEMP_LSB(5) = [res, in7] */ 108 * IN_TEMP_LSB(5) = [res, in7]
109 */
108#define DME1737_REG_IN_TEMP_LSB(ix) (0x84 + (ix)) 110#define DME1737_REG_IN_TEMP_LSB(ix) (0x84 + (ix))
109static const u8 DME1737_REG_IN_LSB[] = {3, 4, 4, 3, 2, 0, 0, 5}; 111static const u8 DME1737_REG_IN_LSB[] = {3, 4, 4, 3, 2, 0, 0, 5};
110static const u8 DME1737_REG_IN_LSB_SHL[] = {4, 4, 0, 0, 0, 0, 4, 4}; 112static const u8 DME1737_REG_IN_LSB_SHL[] = {4, 4, 0, 0, 0, 0, 4, 4};
@@ -127,24 +129,30 @@ static const u8 DME1737_REG_TEMP_LSB_SHL[] = {4, 4, 0};
127#define DME1737_REG_PWM_MIN(ix) (0x64 + (ix)) /* only for pwm[0-2] */ 129#define DME1737_REG_PWM_MIN(ix) (0x64 + (ix)) /* only for pwm[0-2] */
128#define DME1737_REG_PWM_FREQ(ix) ((ix) < 3 ? 0x5f + (ix) \ 130#define DME1737_REG_PWM_FREQ(ix) ((ix) < 3 ? 0x5f + (ix) \
129 : 0xa3 + (ix)) 131 : 0xa3 + (ix))
130/* The layout of the ramp rate registers is different from the other pwm 132/*
133 * The layout of the ramp rate registers is different from the other pwm
131 * registers. The bits for the 3 PWMs are stored in 2 registers: 134 * registers. The bits for the 3 PWMs are stored in 2 registers:
132 * PWM_RR(0) = [OFF3, OFF2, OFF1, RES, RR1E, RR1-2, RR1-1, RR1-0] 135 * PWM_RR(0) = [OFF3, OFF2, OFF1, RES, RR1E, RR1-2, RR1-1, RR1-0]
133 * PWM_RR(1) = [RR2E, RR2-2, RR2-1, RR2-0, RR3E, RR3-2, RR3-1, RR3-0] */ 136 * PWM_RR(1) = [RR2E, RR2-2, RR2-1, RR2-0, RR3E, RR3-2, RR3-1, RR3-0]
137 */
134#define DME1737_REG_PWM_RR(ix) (0x62 + (ix)) /* only for pwm[0-2] */ 138#define DME1737_REG_PWM_RR(ix) (0x62 + (ix)) /* only for pwm[0-2] */
135 139
136/* Thermal zones 0-2 */ 140/* Thermal zones 0-2 */
137#define DME1737_REG_ZONE_LOW(ix) (0x67 + (ix)) 141#define DME1737_REG_ZONE_LOW(ix) (0x67 + (ix))
138#define DME1737_REG_ZONE_ABS(ix) (0x6a + (ix)) 142#define DME1737_REG_ZONE_ABS(ix) (0x6a + (ix))
139/* The layout of the hysteresis registers is different from the other zone 143/*
144 * The layout of the hysteresis registers is different from the other zone
140 * registers. The bits for the 3 zones are stored in 2 registers: 145 * registers. The bits for the 3 zones are stored in 2 registers:
141 * ZONE_HYST(0) = [H1-3, H1-2, H1-1, H1-0, H2-3, H2-2, H2-1, H2-0] 146 * ZONE_HYST(0) = [H1-3, H1-2, H1-1, H1-0, H2-3, H2-2, H2-1, H2-0]
142 * ZONE_HYST(1) = [H3-3, H3-2, H3-1, H3-0, RES, RES, RES, RES] */ 147 * ZONE_HYST(1) = [H3-3, H3-2, H3-1, H3-0, RES, RES, RES, RES]
148 */
143#define DME1737_REG_ZONE_HYST(ix) (0x6d + (ix)) 149#define DME1737_REG_ZONE_HYST(ix) (0x6d + (ix))
144 150
145/* Alarm registers and bit mapping 151/*
152 * Alarm registers and bit mapping
146 * The 3 8-bit alarm registers will be concatenated to a single 32-bit 153 * The 3 8-bit alarm registers will be concatenated to a single 32-bit
147 * alarm value [0, ALARM3, ALARM2, ALARM1]. */ 154 * alarm value [0, ALARM3, ALARM2, ALARM1].
155 */
148#define DME1737_REG_ALARM1 0x41 156#define DME1737_REG_ALARM1 0x41
149#define DME1737_REG_ALARM2 0x42 157#define DME1737_REG_ALARM2 0x42
150#define DME1737_REG_ALARM3 0x83 158#define DME1737_REG_ALARM3 0x83
@@ -257,9 +265,11 @@ static const int IN_NOMINAL_SCH5127[] = {2500, 2250, 3300, 1125, 1125, 3300,
257 (type) == sch5127 ? IN_NOMINAL_SCH5127 : \ 265 (type) == sch5127 ? IN_NOMINAL_SCH5127 : \
258 IN_NOMINAL_DME1737) 266 IN_NOMINAL_DME1737)
259 267
260/* Voltage input 268/*
269 * Voltage input
261 * Voltage inputs have 16 bits resolution, limit values have 8 bits 270 * Voltage inputs have 16 bits resolution, limit values have 8 bits
262 * resolution. */ 271 * resolution.
272 */
263static inline int IN_FROM_REG(int reg, int nominal, int res) 273static inline int IN_FROM_REG(int reg, int nominal, int res)
264{ 274{
265 return (reg * nominal + (3 << (res - 3))) / (3 << (res - 2)); 275 return (reg * nominal + (3 << (res - 3))) / (3 << (res - 2));
@@ -270,10 +280,12 @@ static inline int IN_TO_REG(int val, int nominal)
270 return SENSORS_LIMIT((val * 192 + nominal / 2) / nominal, 0, 255); 280 return SENSORS_LIMIT((val * 192 + nominal / 2) / nominal, 0, 255);
271} 281}
272 282
273/* Temperature input 283/*
284 * Temperature input
274 * The register values represent temperatures in 2's complement notation from 285 * The register values represent temperatures in 2's complement notation from
275 * -127 degrees C to +127 degrees C. Temp inputs have 16 bits resolution, limit 286 * -127 degrees C to +127 degrees C. Temp inputs have 16 bits resolution, limit
276 * values have 8 bits resolution. */ 287 * values have 8 bits resolution.
288 */
277static inline int TEMP_FROM_REG(int reg, int res) 289static inline int TEMP_FROM_REG(int reg, int res)
278{ 290{
279 return (reg * 1000) >> (res - 8); 291 return (reg * 1000) >> (res - 8);
@@ -300,18 +312,19 @@ static int TEMP_RANGE_TO_REG(int val, int reg)
300 int i; 312 int i;
301 313
302 for (i = 15; i > 0; i--) { 314 for (i = 15; i > 0; i--) {
303 if (val > (TEMP_RANGE[i] + TEMP_RANGE[i - 1] + 1) / 2) { 315 if (val > (TEMP_RANGE[i] + TEMP_RANGE[i - 1] + 1) / 2)
304 break; 316 break;
305 }
306 } 317 }
307 318
308 return (reg & 0x0f) | (i << 4); 319 return (reg & 0x0f) | (i << 4);
309} 320}
310 321
311/* Temperature hysteresis 322/*
323 * Temperature hysteresis
312 * Register layout: 324 * Register layout:
313 * reg[0] = [H1-3, H1-2, H1-1, H1-0, H2-3, H2-2, H2-1, H2-0] 325 * reg[0] = [H1-3, H1-2, H1-1, H1-0, H2-3, H2-2, H2-1, H2-0]
314 * reg[1] = [H3-3, H3-2, H3-1, H3-0, xxxx, xxxx, xxxx, xxxx] */ 326 * reg[1] = [H3-3, H3-2, H3-1, H3-0, xxxx, xxxx, xxxx, xxxx]
327 */
315static inline int TEMP_HYST_FROM_REG(int reg, int ix) 328static inline int TEMP_HYST_FROM_REG(int reg, int ix)
316{ 329{
317 return (((ix == 1) ? reg : reg >> 4) & 0x0f) * 1000; 330 return (((ix == 1) ? reg : reg >> 4) & 0x0f) * 1000;
@@ -327,11 +340,10 @@ static inline int TEMP_HYST_TO_REG(int val, int ix, int reg)
327/* Fan input RPM */ 340/* Fan input RPM */
328static inline int FAN_FROM_REG(int reg, int tpc) 341static inline int FAN_FROM_REG(int reg, int tpc)
329{ 342{
330 if (tpc) { 343 if (tpc)
331 return tpc * reg; 344 return tpc * reg;
332 } else { 345 else
333 return (reg == 0 || reg == 0xffff) ? 0 : 90000 * 60 / reg; 346 return (reg == 0 || reg == 0xffff) ? 0 : 90000 * 60 / reg;
334 }
335} 347}
336 348
337static inline int FAN_TO_REG(int val, int tpc) 349static inline int FAN_TO_REG(int val, int tpc)
@@ -344,17 +356,21 @@ static inline int FAN_TO_REG(int val, int tpc)
344 } 356 }
345} 357}
346 358
347/* Fan TPC (tach pulse count) 359/*
360 * Fan TPC (tach pulse count)
348 * Converts a register value to a TPC multiplier or returns 0 if the tachometer 361 * Converts a register value to a TPC multiplier or returns 0 if the tachometer
349 * is configured in legacy (non-tpc) mode */ 362 * is configured in legacy (non-tpc) mode
363 */
350static inline int FAN_TPC_FROM_REG(int reg) 364static inline int FAN_TPC_FROM_REG(int reg)
351{ 365{
352 return (reg & 0x20) ? 0 : 60 >> (reg & 0x03); 366 return (reg & 0x20) ? 0 : 60 >> (reg & 0x03);
353} 367}
354 368
355/* Fan type 369/*
370 * Fan type
356 * The type of a fan is expressed in number of pulses-per-revolution that it 371 * The type of a fan is expressed in number of pulses-per-revolution that it
357 * emits */ 372 * emits
373 */
358static inline int FAN_TYPE_FROM_REG(int reg) 374static inline int FAN_TYPE_FROM_REG(int reg)
359{ 375{
360 int edge = (reg >> 1) & 0x03; 376 int edge = (reg >> 1) & 0x03;
@@ -378,9 +394,8 @@ static int FAN_MAX_FROM_REG(int reg)
378 int i; 394 int i;
379 395
380 for (i = 10; i > 0; i--) { 396 for (i = 10; i > 0; i--) {
381 if (reg == FAN_MAX[i]) { 397 if (reg == FAN_MAX[i])
382 break; 398 break;
383 }
384 } 399 }
385 400
386 return 1000 + i * 500; 401 return 1000 + i * 500;
@@ -391,15 +406,15 @@ static int FAN_MAX_TO_REG(int val)
391 int i; 406 int i;
392 407
393 for (i = 10; i > 0; i--) { 408 for (i = 10; i > 0; i--) {
394 if (val > (1000 + (i - 1) * 500)) { 409 if (val > (1000 + (i - 1) * 500))
395 break; 410 break;
396 }
397 } 411 }
398 412
399 return FAN_MAX[i]; 413 return FAN_MAX[i];
400} 414}
401 415
402/* PWM enable 416/*
417 * PWM enable
403 * Register to enable mapping: 418 * Register to enable mapping:
404 * 000: 2 fan on zone 1 auto 419 * 000: 2 fan on zone 1 auto
405 * 001: 2 fan on zone 2 auto 420 * 001: 2 fan on zone 2 auto
@@ -408,7 +423,8 @@ static int FAN_MAX_TO_REG(int val)
408 * 100: -1 fan disabled 423 * 100: -1 fan disabled
409 * 101: 2 fan on hottest of zones 2,3 auto 424 * 101: 2 fan on hottest of zones 2,3 auto
410 * 110: 2 fan on hottest of zones 1,2,3 auto 425 * 110: 2 fan on hottest of zones 1,2,3 auto
411 * 111: 1 fan in manual mode */ 426 * 111: 1 fan in manual mode
427 */
412static inline int PWM_EN_FROM_REG(int reg) 428static inline int PWM_EN_FROM_REG(int reg)
413{ 429{
414 static const int en[] = {2, 2, 2, 0, -1, 2, 2, 1}; 430 static const int en[] = {2, 2, 2, 0, -1, 2, 2, 1};
@@ -423,7 +439,8 @@ static inline int PWM_EN_TO_REG(int val, int reg)
423 return (reg & 0x1f) | ((en & 0x07) << 5); 439 return (reg & 0x1f) | ((en & 0x07) << 5);
424} 440}
425 441
426/* PWM auto channels zone 442/*
443 * PWM auto channels zone
427 * Register to auto channels zone mapping (ACZ is a bitfield with bit x 444 * Register to auto channels zone mapping (ACZ is a bitfield with bit x
428 * corresponding to zone x+1): 445 * corresponding to zone x+1):
429 * 000: 001 fan on zone 1 auto 446 * 000: 001 fan on zone 1 auto
@@ -433,7 +450,8 @@ static inline int PWM_EN_TO_REG(int val, int reg)
433 * 100: 000 fan disabled 450 * 100: 000 fan disabled
434 * 101: 110 fan on hottest of zones 2,3 auto 451 * 101: 110 fan on hottest of zones 2,3 auto
435 * 110: 111 fan on hottest of zones 1,2,3 auto 452 * 110: 111 fan on hottest of zones 1,2,3 auto
436 * 111: 000 fan in manual mode */ 453 * 111: 000 fan in manual mode
454 */
437static inline int PWM_ACZ_FROM_REG(int reg) 455static inline int PWM_ACZ_FROM_REG(int reg)
438{ 456{
439 static const int acz[] = {1, 2, 4, 0, 0, 6, 7, 0}; 457 static const int acz[] = {1, 2, 4, 0, 0, 6, 7, 0};
@@ -468,19 +486,20 @@ static int PWM_FREQ_TO_REG(int val, int reg)
468 i = 11; 486 i = 11;
469 } else { 487 } else {
470 for (i = 9; i > 0; i--) { 488 for (i = 9; i > 0; i--) {
471 if (val > (PWM_FREQ[i] + PWM_FREQ[i - 1] + 1) / 2) { 489 if (val > (PWM_FREQ[i] + PWM_FREQ[i - 1] + 1) / 2)
472 break; 490 break;
473 }
474 } 491 }
475 } 492 }
476 493
477 return (reg & 0xf0) | i; 494 return (reg & 0xf0) | i;
478} 495}
479 496
480/* PWM ramp rate 497/*
498 * PWM ramp rate
481 * Register layout: 499 * Register layout:
482 * reg[0] = [OFF3, OFF2, OFF1, RES, RR1-E, RR1-2, RR1-1, RR1-0] 500 * reg[0] = [OFF3, OFF2, OFF1, RES, RR1-E, RR1-2, RR1-1, RR1-0]
483 * reg[1] = [RR2-E, RR2-2, RR2-1, RR2-0, RR3-E, RR3-2, RR3-1, RR3-0] */ 501 * reg[1] = [RR2-E, RR2-2, RR2-1, RR2-0, RR3-E, RR3-2, RR3-1, RR3-0]
502 */
484static const u8 PWM_RR[] = {206, 104, 69, 41, 26, 18, 10, 5}; 503static const u8 PWM_RR[] = {206, 104, 69, 41, 26, 18, 10, 5};
485 504
486static inline int PWM_RR_FROM_REG(int reg, int ix) 505static inline int PWM_RR_FROM_REG(int reg, int ix)
@@ -495,9 +514,8 @@ static int PWM_RR_TO_REG(int val, int ix, int reg)
495 int i; 514 int i;
496 515
497 for (i = 0; i < 7; i++) { 516 for (i = 0; i < 7; i++) {
498 if (val > (PWM_RR[i] + PWM_RR[i + 1] + 1) / 2) { 517 if (val > (PWM_RR[i] + PWM_RR[i + 1] + 1) / 2)
499 break; 518 break;
500 }
501 } 519 }
502 520
503 return (ix == 1) ? (reg & 0x8f) | (i << 4) : (reg & 0xf8) | i; 521 return (ix == 1) ? (reg & 0x8f) | (i << 4) : (reg & 0xf8) | i;
@@ -516,9 +534,11 @@ static inline int PWM_RR_EN_TO_REG(int val, int ix, int reg)
516 return val ? reg | en : reg & ~en; 534 return val ? reg | en : reg & ~en;
517} 535}
518 536
519/* PWM min/off 537/*
538 * PWM min/off
520 * The PWM min/off bits are part of the PMW ramp rate register 0 (see above for 539 * The PWM min/off bits are part of the PMW ramp rate register 0 (see above for
521 * the register layout). */ 540 * the register layout).
541 */
522static inline int PWM_OFF_FROM_REG(int reg, int ix) 542static inline int PWM_OFF_FROM_REG(int reg, int ix)
523{ 543{
524 return (reg >> (ix + 5)) & 0x01; 544 return (reg >> (ix + 5)) & 0x01;
@@ -604,12 +624,13 @@ static struct dme1737_data *dme1737_update_device(struct device *dev)
604 624
605 /* In (voltage) registers */ 625 /* In (voltage) registers */
606 for (ix = 0; ix < ARRAY_SIZE(data->in); ix++) { 626 for (ix = 0; ix < ARRAY_SIZE(data->in); ix++) {
607 /* Voltage inputs are stored as 16 bit values even 627 /*
628 * Voltage inputs are stored as 16 bit values even
608 * though they have only 12 bits resolution. This is 629 * though they have only 12 bits resolution. This is
609 * to make it consistent with the temp inputs. */ 630 * to make it consistent with the temp inputs.
610 if (ix == 7 && !(data->has_features & HAS_IN7)) { 631 */
632 if (ix == 7 && !(data->has_features & HAS_IN7))
611 continue; 633 continue;
612 }
613 data->in[ix] = dme1737_read(data, 634 data->in[ix] = dme1737_read(data,
614 DME1737_REG_IN(ix)) << 8; 635 DME1737_REG_IN(ix)) << 8;
615 data->in_min[ix] = dme1737_read(data, 636 data->in_min[ix] = dme1737_read(data,
@@ -620,11 +641,13 @@ static struct dme1737_data *dme1737_update_device(struct device *dev)
620 641
621 /* Temp registers */ 642 /* Temp registers */
622 for (ix = 0; ix < ARRAY_SIZE(data->temp); ix++) { 643 for (ix = 0; ix < ARRAY_SIZE(data->temp); ix++) {
623 /* Temp inputs are stored as 16 bit values even 644 /*
645 * Temp inputs are stored as 16 bit values even
624 * though they have only 12 bits resolution. This is 646 * though they have only 12 bits resolution. This is
625 * to take advantage of implicit conversions between 647 * to take advantage of implicit conversions between
626 * register values (2's complement) and temp values 648 * register values (2's complement) and temp values
627 * (signed decimal). */ 649 * (signed decimal).
650 */
628 data->temp[ix] = dme1737_read(data, 651 data->temp[ix] = dme1737_read(data,
629 DME1737_REG_TEMP(ix)) << 8; 652 DME1737_REG_TEMP(ix)) << 8;
630 data->temp_min[ix] = dme1737_read(data, 653 data->temp_min[ix] = dme1737_read(data,
@@ -637,21 +660,21 @@ static struct dme1737_data *dme1737_update_device(struct device *dev)
637 } 660 }
638 } 661 }
639 662
640 /* In and temp LSB registers 663 /*
664 * In and temp LSB registers
641 * The LSBs are latched when the MSBs are read, so the order in 665 * The LSBs are latched when the MSBs are read, so the order in
642 * which the registers are read (MSB first, then LSB) is 666 * which the registers are read (MSB first, then LSB) is
643 * important! */ 667 * important!
668 */
644 for (ix = 0; ix < ARRAY_SIZE(lsb); ix++) { 669 for (ix = 0; ix < ARRAY_SIZE(lsb); ix++) {
645 if (ix == 5 && !(data->has_features & HAS_IN7)) { 670 if (ix == 5 && !(data->has_features & HAS_IN7))
646 continue; 671 continue;
647 }
648 lsb[ix] = dme1737_read(data, 672 lsb[ix] = dme1737_read(data,
649 DME1737_REG_IN_TEMP_LSB(ix)); 673 DME1737_REG_IN_TEMP_LSB(ix));
650 } 674 }
651 for (ix = 0; ix < ARRAY_SIZE(data->in); ix++) { 675 for (ix = 0; ix < ARRAY_SIZE(data->in); ix++) {
652 if (ix == 7 && !(data->has_features & HAS_IN7)) { 676 if (ix == 7 && !(data->has_features & HAS_IN7))
653 continue; 677 continue;
654 }
655 data->in[ix] |= (lsb[DME1737_REG_IN_LSB[ix]] << 678 data->in[ix] |= (lsb[DME1737_REG_IN_LSB[ix]] <<
656 DME1737_REG_IN_LSB_SHL[ix]) & 0xf0; 679 DME1737_REG_IN_LSB_SHL[ix]) & 0xf0;
657 } 680 }
@@ -662,11 +685,12 @@ static struct dme1737_data *dme1737_update_device(struct device *dev)
662 685
663 /* Fan registers */ 686 /* Fan registers */
664 for (ix = 0; ix < ARRAY_SIZE(data->fan); ix++) { 687 for (ix = 0; ix < ARRAY_SIZE(data->fan); ix++) {
665 /* Skip reading registers if optional fans are not 688 /*
666 * present */ 689 * Skip reading registers if optional fans are not
667 if (!(data->has_features & HAS_FAN(ix))) { 690 * present
691 */
692 if (!(data->has_features & HAS_FAN(ix)))
668 continue; 693 continue;
669 }
670 data->fan[ix] = dme1737_read(data, 694 data->fan[ix] = dme1737_read(data,
671 DME1737_REG_FAN(ix)); 695 DME1737_REG_FAN(ix));
672 data->fan[ix] |= dme1737_read(data, 696 data->fan[ix] |= dme1737_read(data,
@@ -686,11 +710,12 @@ static struct dme1737_data *dme1737_update_device(struct device *dev)
686 710
687 /* PWM registers */ 711 /* PWM registers */
688 for (ix = 0; ix < ARRAY_SIZE(data->pwm); ix++) { 712 for (ix = 0; ix < ARRAY_SIZE(data->pwm); ix++) {
689 /* Skip reading registers if optional PWMs are not 713 /*
690 * present */ 714 * Skip reading registers if optional PWMs are not
691 if (!(data->has_features & HAS_PWM(ix))) { 715 * present
716 */
717 if (!(data->has_features & HAS_PWM(ix)))
692 continue; 718 continue;
693 }
694 data->pwm[ix] = dme1737_read(data, 719 data->pwm[ix] = dme1737_read(data,
695 DME1737_REG_PWM(ix)); 720 DME1737_REG_PWM(ix));
696 data->pwm_freq[ix] = dme1737_read(data, 721 data->pwm_freq[ix] = dme1737_read(data,
@@ -711,9 +736,8 @@ static struct dme1737_data *dme1737_update_device(struct device *dev)
711 /* Thermal zone registers */ 736 /* Thermal zone registers */
712 for (ix = 0; ix < ARRAY_SIZE(data->zone_low); ix++) { 737 for (ix = 0; ix < ARRAY_SIZE(data->zone_low); ix++) {
713 /* Skip reading registers if zone3 is not present */ 738 /* Skip reading registers if zone3 is not present */
714 if ((ix == 2) && !(data->has_features & HAS_ZONE3)) { 739 if ((ix == 2) && !(data->has_features & HAS_ZONE3))
715 continue; 740 continue;
716 }
717 /* sch5127 zone2 registers are special */ 741 /* sch5127 zone2 registers are special */
718 if ((ix == 1) && (data->type == sch5127)) { 742 if ((ix == 1) && (data->type == sch5127)) {
719 data->zone_low[1] = dme1737_read(data, 743 data->zone_low[1] = dme1737_read(data,
@@ -737,8 +761,10 @@ static struct dme1737_data *dme1737_update_device(struct device *dev)
737 /* Alarm registers */ 761 /* Alarm registers */
738 data->alarms = dme1737_read(data, 762 data->alarms = dme1737_read(data,
739 DME1737_REG_ALARM1); 763 DME1737_REG_ALARM1);
740 /* Bit 7 tells us if the other alarm registers are non-zero and 764 /*
741 * therefore also need to be read */ 765 * Bit 7 tells us if the other alarm registers are non-zero and
766 * therefore also need to be read
767 */
742 if (data->alarms & 0x80) { 768 if (data->alarms & 0x80) {
743 data->alarms |= dme1737_read(data, 769 data->alarms |= dme1737_read(data,
744 DME1737_REG_ALARM2) << 8; 770 DME1737_REG_ALARM2) << 8;
@@ -746,22 +772,18 @@ static struct dme1737_data *dme1737_update_device(struct device *dev)
746 DME1737_REG_ALARM3) << 16; 772 DME1737_REG_ALARM3) << 16;
747 } 773 }
748 774
749 /* The ISA chips require explicit clearing of alarm bits. 775 /*
776 * The ISA chips require explicit clearing of alarm bits.
750 * Don't worry, an alarm will come back if the condition 777 * Don't worry, an alarm will come back if the condition
751 * that causes it still exists */ 778 * that causes it still exists
779 */
752 if (!data->client) { 780 if (!data->client) {
753 if (data->alarms & 0xff0000) { 781 if (data->alarms & 0xff0000)
754 dme1737_write(data, DME1737_REG_ALARM3, 782 dme1737_write(data, DME1737_REG_ALARM3, 0xff);
755 0xff); 783 if (data->alarms & 0xff00)
756 } 784 dme1737_write(data, DME1737_REG_ALARM2, 0xff);
757 if (data->alarms & 0xff00) { 785 if (data->alarms & 0xff)
758 dme1737_write(data, DME1737_REG_ALARM2, 786 dme1737_write(data, DME1737_REG_ALARM1, 0xff);
759 0xff);
760 }
761 if (data->alarms & 0xff) {
762 dme1737_write(data, DME1737_REG_ALARM1,
763 0xff);
764 }
765 } 787 }
766 788
767 data->last_update = jiffies; 789 data->last_update = jiffies;
@@ -822,7 +844,12 @@ static ssize_t set_in(struct device *dev, struct device_attribute *attr,
822 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 844 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
823 int ix = sensor_attr_2->index; 845 int ix = sensor_attr_2->index;
824 int fn = sensor_attr_2->nr; 846 int fn = sensor_attr_2->nr;
825 long val = simple_strtol(buf, NULL, 10); 847 long val;
848 int err;
849
850 err = kstrtol(buf, 10, &val);
851 if (err)
852 return err;
826 853
827 mutex_lock(&data->update_lock); 854 mutex_lock(&data->update_lock);
828 switch (fn) { 855 switch (fn) {
@@ -901,7 +928,12 @@ static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
901 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 928 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
902 int ix = sensor_attr_2->index; 929 int ix = sensor_attr_2->index;
903 int fn = sensor_attr_2->nr; 930 int fn = sensor_attr_2->nr;
904 long val = simple_strtol(buf, NULL, 10); 931 long val;
932 int err;
933
934 err = kstrtol(buf, 10, &val);
935 if (err)
936 return err;
905 937
906 mutex_lock(&data->update_lock); 938 mutex_lock(&data->update_lock);
907 switch (fn) { 939 switch (fn) {
@@ -952,11 +984,10 @@ static ssize_t show_zone(struct device *dev, struct device_attribute *attr,
952 switch (fn) { 984 switch (fn) {
953 case SYS_ZONE_AUTO_CHANNELS_TEMP: 985 case SYS_ZONE_AUTO_CHANNELS_TEMP:
954 /* check config2 for non-standard temp-to-zone mapping */ 986 /* check config2 for non-standard temp-to-zone mapping */
955 if ((ix == 1) && (data->config2 & 0x02)) { 987 if ((ix == 1) && (data->config2 & 0x02))
956 res = 4; 988 res = 4;
957 } else { 989 else
958 res = 1 << ix; 990 res = 1 << ix;
959 }
960 break; 991 break;
961 case SYS_ZONE_AUTO_POINT1_TEMP_HYST: 992 case SYS_ZONE_AUTO_POINT1_TEMP_HYST:
962 res = TEMP_FROM_REG(data->zone_low[ix], 8) - 993 res = TEMP_FROM_REG(data->zone_low[ix], 8) -
@@ -989,7 +1020,12 @@ static ssize_t set_zone(struct device *dev, struct device_attribute *attr,
989 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 1020 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
990 int ix = sensor_attr_2->index; 1021 int ix = sensor_attr_2->index;
991 int fn = sensor_attr_2->nr; 1022 int fn = sensor_attr_2->nr;
992 long val = simple_strtol(buf, NULL, 10); 1023 long val;
1024 int err;
1025
1026 err = kstrtol(buf, 10, &val);
1027 if (err)
1028 return err;
993 1029
994 mutex_lock(&data->update_lock); 1030 mutex_lock(&data->update_lock);
995 switch (fn) { 1031 switch (fn) {
@@ -1014,8 +1050,10 @@ static ssize_t set_zone(struct device *dev, struct device_attribute *attr,
1014 /* Refresh the cache */ 1050 /* Refresh the cache */
1015 data->zone_low[ix] = dme1737_read(data, 1051 data->zone_low[ix] = dme1737_read(data,
1016 DME1737_REG_ZONE_LOW(ix)); 1052 DME1737_REG_ZONE_LOW(ix));
1017 /* Modify the temp range value (which is stored in the upper 1053 /*
1018 * nibble of the pwm_freq register) */ 1054 * Modify the temp range value (which is stored in the upper
1055 * nibble of the pwm_freq register)
1056 */
1019 data->pwm_freq[ix] = TEMP_RANGE_TO_REG(val - 1057 data->pwm_freq[ix] = TEMP_RANGE_TO_REG(val -
1020 TEMP_FROM_REG(data->zone_low[ix], 8), 1058 TEMP_FROM_REG(data->zone_low[ix], 8),
1021 dme1737_read(data, 1059 dme1737_read(data,
@@ -1095,7 +1133,12 @@ static ssize_t set_fan(struct device *dev, struct device_attribute *attr,
1095 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 1133 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
1096 int ix = sensor_attr_2->index; 1134 int ix = sensor_attr_2->index;
1097 int fn = sensor_attr_2->nr; 1135 int fn = sensor_attr_2->nr;
1098 long val = simple_strtol(buf, NULL, 10); 1136 long val;
1137 int err;
1138
1139 err = kstrtol(buf, 10, &val);
1140 if (err)
1141 return err;
1099 1142
1100 mutex_lock(&data->update_lock); 1143 mutex_lock(&data->update_lock);
1101 switch (fn) { 1144 switch (fn) {
@@ -1170,21 +1213,19 @@ static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
1170 1213
1171 switch (fn) { 1214 switch (fn) {
1172 case SYS_PWM: 1215 case SYS_PWM:
1173 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 0) { 1216 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 0)
1174 res = 255; 1217 res = 255;
1175 } else { 1218 else
1176 res = data->pwm[ix]; 1219 res = data->pwm[ix];
1177 }
1178 break; 1220 break;
1179 case SYS_PWM_FREQ: 1221 case SYS_PWM_FREQ:
1180 res = PWM_FREQ_FROM_REG(data->pwm_freq[ix]); 1222 res = PWM_FREQ_FROM_REG(data->pwm_freq[ix]);
1181 break; 1223 break;
1182 case SYS_PWM_ENABLE: 1224 case SYS_PWM_ENABLE:
1183 if (ix >= 3) { 1225 if (ix >= 3)
1184 res = 1; /* pwm[5-6] hard-wired to manual mode */ 1226 res = 1; /* pwm[5-6] hard-wired to manual mode */
1185 } else { 1227 else
1186 res = PWM_EN_FROM_REG(data->pwm_config[ix]); 1228 res = PWM_EN_FROM_REG(data->pwm_config[ix]);
1187 }
1188 break; 1229 break;
1189 case SYS_PWM_RAMP_RATE: 1230 case SYS_PWM_RAMP_RATE:
1190 /* Only valid for pwm[1-3] */ 1231 /* Only valid for pwm[1-3] */
@@ -1192,19 +1233,17 @@ static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
1192 break; 1233 break;
1193 case SYS_PWM_AUTO_CHANNELS_ZONE: 1234 case SYS_PWM_AUTO_CHANNELS_ZONE:
1194 /* Only valid for pwm[1-3] */ 1235 /* Only valid for pwm[1-3] */
1195 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) { 1236 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2)
1196 res = PWM_ACZ_FROM_REG(data->pwm_config[ix]); 1237 res = PWM_ACZ_FROM_REG(data->pwm_config[ix]);
1197 } else { 1238 else
1198 res = data->pwm_acz[ix]; 1239 res = data->pwm_acz[ix];
1199 }
1200 break; 1240 break;
1201 case SYS_PWM_AUTO_PWM_MIN: 1241 case SYS_PWM_AUTO_PWM_MIN:
1202 /* Only valid for pwm[1-3] */ 1242 /* Only valid for pwm[1-3] */
1203 if (PWM_OFF_FROM_REG(data->pwm_rr[0], ix)) { 1243 if (PWM_OFF_FROM_REG(data->pwm_rr[0], ix))
1204 res = data->pwm_min[ix]; 1244 res = data->pwm_min[ix];
1205 } else { 1245 else
1206 res = 0; 1246 res = 0;
1207 }
1208 break; 1247 break;
1209 case SYS_PWM_AUTO_POINT1_PWM: 1248 case SYS_PWM_AUTO_POINT1_PWM:
1210 /* Only valid for pwm[1-3] */ 1249 /* Only valid for pwm[1-3] */
@@ -1233,7 +1272,12 @@ static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
1233 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 1272 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
1234 int ix = sensor_attr_2->index; 1273 int ix = sensor_attr_2->index;
1235 int fn = sensor_attr_2->nr; 1274 int fn = sensor_attr_2->nr;
1236 long val = simple_strtol(buf, NULL, 10); 1275 long val;
1276 int err;
1277
1278 err = kstrtol(buf, 10, &val);
1279 if (err)
1280 return err;
1237 1281
1238 mutex_lock(&data->update_lock); 1282 mutex_lock(&data->update_lock);
1239 switch (fn) { 1283 switch (fn) {
@@ -1307,8 +1351,10 @@ static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
1307 /* Change permissions of pwm[ix] to read-only */ 1351 /* Change permissions of pwm[ix] to read-only */
1308 dme1737_chmod_file(dev, dme1737_pwm_chmod_attr[ix], 1352 dme1737_chmod_file(dev, dme1737_pwm_chmod_attr[ix],
1309 S_IRUGO); 1353 S_IRUGO);
1310 /* Turn on auto mode using the saved zone channel 1354 /*
1311 * assignment */ 1355 * Turn on auto mode using the saved zone channel
1356 * assignment
1357 */
1312 data->pwm_config[ix] = PWM_ACZ_TO_REG( 1358 data->pwm_config[ix] = PWM_ACZ_TO_REG(
1313 data->pwm_acz[ix], 1359 data->pwm_acz[ix],
1314 data->pwm_config[ix]); 1360 data->pwm_config[ix]);
@@ -1338,8 +1384,10 @@ static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
1338 data->pwm_rr[ix > 0] = PWM_RR_TO_REG(val, ix, 1384 data->pwm_rr[ix > 0] = PWM_RR_TO_REG(val, ix,
1339 data->pwm_rr[ix > 0]); 1385 data->pwm_rr[ix > 0]);
1340 } 1386 }
1341 /* Enable/disable the feature only if the associated PWM 1387 /*
1342 * output is in automatic mode. */ 1388 * Enable/disable the feature only if the associated PWM
1389 * output is in automatic mode.
1390 */
1343 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) { 1391 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) {
1344 data->pwm_rr[ix > 0] = PWM_RR_EN_TO_REG(val > 0, ix, 1392 data->pwm_rr[ix > 0] = PWM_RR_EN_TO_REG(val > 0, ix,
1345 data->pwm_rr[ix > 0]); 1393 data->pwm_rr[ix > 0]);
@@ -1361,15 +1409,19 @@ static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
1361 data->pwm_config[ix] = dme1737_read(data, 1409 data->pwm_config[ix] = dme1737_read(data,
1362 DME1737_REG_PWM_CONFIG(ix)); 1410 DME1737_REG_PWM_CONFIG(ix));
1363 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) { 1411 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) {
1364 /* PWM is already in auto mode so update the temp 1412 /*
1365 * channel assignment */ 1413 * PWM is already in auto mode so update the temp
1414 * channel assignment
1415 */
1366 data->pwm_config[ix] = PWM_ACZ_TO_REG(val, 1416 data->pwm_config[ix] = PWM_ACZ_TO_REG(val,
1367 data->pwm_config[ix]); 1417 data->pwm_config[ix]);
1368 dme1737_write(data, DME1737_REG_PWM_CONFIG(ix), 1418 dme1737_write(data, DME1737_REG_PWM_CONFIG(ix),
1369 data->pwm_config[ix]); 1419 data->pwm_config[ix]);
1370 } else { 1420 } else {
1371 /* PWM is not in auto mode so we save the temp 1421 /*
1372 * channel assignment for later use */ 1422 * PWM is not in auto mode so we save the temp
1423 * channel assignment for later use
1424 */
1373 data->pwm_acz[ix] = val; 1425 data->pwm_acz[ix] = val;
1374 } 1426 }
1375 break; 1427 break;
@@ -1378,10 +1430,12 @@ static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
1378 /* Refresh the cache */ 1430 /* Refresh the cache */
1379 data->pwm_min[ix] = dme1737_read(data, 1431 data->pwm_min[ix] = dme1737_read(data,
1380 DME1737_REG_PWM_MIN(ix)); 1432 DME1737_REG_PWM_MIN(ix));
1381 /* There are only 2 values supported for the auto_pwm_min 1433 /*
1434 * There are only 2 values supported for the auto_pwm_min
1382 * value: 0 or auto_point1_pwm. So if the temperature drops 1435 * value: 0 or auto_point1_pwm. So if the temperature drops
1383 * below the auto_point1_temp_hyst value, the fan either turns 1436 * below the auto_point1_temp_hyst value, the fan either turns
1384 * off or runs at auto_point1_pwm duty-cycle. */ 1437 * off or runs at auto_point1_pwm duty-cycle.
1438 */
1385 if (val > ((data->pwm_min[ix] + 1) / 2)) { 1439 if (val > ((data->pwm_min[ix] + 1) / 2)) {
1386 data->pwm_rr[0] = PWM_OFF_TO_REG(1, ix, 1440 data->pwm_rr[0] = PWM_OFF_TO_REG(1, ix,
1387 dme1737_read(data, 1441 dme1737_read(data,
@@ -1426,7 +1480,12 @@ static ssize_t set_vrm(struct device *dev, struct device_attribute *attr,
1426 const char *buf, size_t count) 1480 const char *buf, size_t count)
1427{ 1481{
1428 struct dme1737_data *data = dev_get_drvdata(dev); 1482 struct dme1737_data *data = dev_get_drvdata(dev);
1429 long val = simple_strtol(buf, NULL, 10); 1483 long val;
1484 int err;
1485
1486 err = kstrtol(buf, 10, &val);
1487 if (err)
1488 return err;
1430 1489
1431 data->vrm = val; 1490 data->vrm = val;
1432 return count; 1491 return count;
@@ -1586,10 +1645,12 @@ static DEVICE_ATTR(vrm, S_IRUGO | S_IWUSR, show_vrm, set_vrm);
1586static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid, NULL); 1645static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid, NULL);
1587static DEVICE_ATTR(name, S_IRUGO, show_name, NULL); /* for ISA devices */ 1646static DEVICE_ATTR(name, S_IRUGO, show_name, NULL); /* for ISA devices */
1588 1647
1589/* This struct holds all the attributes that are always present and need to be 1648/*
1649 * This struct holds all the attributes that are always present and need to be
1590 * created unconditionally. The attributes that need modification of their 1650 * created unconditionally. The attributes that need modification of their
1591 * permissions are created read-only and write permissions are added or removed 1651 * permissions are created read-only and write permissions are added or removed
1592 * on the fly when required */ 1652 * on the fly when required
1653 */
1593static struct attribute *dme1737_attr[] = { 1654static struct attribute *dme1737_attr[] = {
1594 /* Voltages */ 1655 /* Voltages */
1595 &sensor_dev_attr_in0_input.dev_attr.attr, 1656 &sensor_dev_attr_in0_input.dev_attr.attr,
@@ -1652,9 +1713,11 @@ static const struct attribute_group dme1737_group = {
1652 .attrs = dme1737_attr, 1713 .attrs = dme1737_attr,
1653}; 1714};
1654 1715
1655/* The following struct holds temp offset attributes, which are not available 1716/*
1717 * The following struct holds temp offset attributes, which are not available
1656 * in all chips. The following chips support them: 1718 * in all chips. The following chips support them:
1657 * DME1737, SCH311x */ 1719 * DME1737, SCH311x
1720 */
1658static struct attribute *dme1737_temp_offset_attr[] = { 1721static struct attribute *dme1737_temp_offset_attr[] = {
1659 &sensor_dev_attr_temp1_offset.dev_attr.attr, 1722 &sensor_dev_attr_temp1_offset.dev_attr.attr,
1660 &sensor_dev_attr_temp2_offset.dev_attr.attr, 1723 &sensor_dev_attr_temp2_offset.dev_attr.attr,
@@ -1666,9 +1729,11 @@ static const struct attribute_group dme1737_temp_offset_group = {
1666 .attrs = dme1737_temp_offset_attr, 1729 .attrs = dme1737_temp_offset_attr,
1667}; 1730};
1668 1731
1669/* The following struct holds VID related attributes, which are not available 1732/*
1733 * The following struct holds VID related attributes, which are not available
1670 * in all chips. The following chips support them: 1734 * in all chips. The following chips support them:
1671 * DME1737 */ 1735 * DME1737
1736 */
1672static struct attribute *dme1737_vid_attr[] = { 1737static struct attribute *dme1737_vid_attr[] = {
1673 &dev_attr_vrm.attr, 1738 &dev_attr_vrm.attr,
1674 &dev_attr_cpu0_vid.attr, 1739 &dev_attr_cpu0_vid.attr,
@@ -1679,9 +1744,11 @@ static const struct attribute_group dme1737_vid_group = {
1679 .attrs = dme1737_vid_attr, 1744 .attrs = dme1737_vid_attr,
1680}; 1745};
1681 1746
1682/* The following struct holds temp zone 3 related attributes, which are not 1747/*
1748 * The following struct holds temp zone 3 related attributes, which are not
1683 * available in all chips. The following chips support them: 1749 * available in all chips. The following chips support them:
1684 * DME1737, SCH311x, SCH5027 */ 1750 * DME1737, SCH311x, SCH5027
1751 */
1685static struct attribute *dme1737_zone3_attr[] = { 1752static struct attribute *dme1737_zone3_attr[] = {
1686 &sensor_dev_attr_zone3_auto_point1_temp.dev_attr.attr, 1753 &sensor_dev_attr_zone3_auto_point1_temp.dev_attr.attr,
1687 &sensor_dev_attr_zone3_auto_point2_temp.dev_attr.attr, 1754 &sensor_dev_attr_zone3_auto_point2_temp.dev_attr.attr,
@@ -1695,9 +1762,11 @@ static const struct attribute_group dme1737_zone3_group = {
1695}; 1762};
1696 1763
1697 1764
1698/* The following struct holds temp zone hysteresis related attributes, which 1765/*
1766 * The following struct holds temp zone hysteresis related attributes, which
1699 * are not available in all chips. The following chips support them: 1767 * are not available in all chips. The following chips support them:
1700 * DME1737, SCH311x */ 1768 * DME1737, SCH311x
1769 */
1701static struct attribute *dme1737_zone_hyst_attr[] = { 1770static struct attribute *dme1737_zone_hyst_attr[] = {
1702 &sensor_dev_attr_zone1_auto_point1_temp_hyst.dev_attr.attr, 1771 &sensor_dev_attr_zone1_auto_point1_temp_hyst.dev_attr.attr,
1703 &sensor_dev_attr_zone2_auto_point1_temp_hyst.dev_attr.attr, 1772 &sensor_dev_attr_zone2_auto_point1_temp_hyst.dev_attr.attr,
@@ -1709,9 +1778,11 @@ static const struct attribute_group dme1737_zone_hyst_group = {
1709 .attrs = dme1737_zone_hyst_attr, 1778 .attrs = dme1737_zone_hyst_attr,
1710}; 1779};
1711 1780
1712/* The following struct holds voltage in7 related attributes, which 1781/*
1782 * The following struct holds voltage in7 related attributes, which
1713 * are not available in all chips. The following chips support them: 1783 * are not available in all chips. The following chips support them:
1714 * SCH5127 */ 1784 * SCH5127
1785 */
1715static struct attribute *dme1737_in7_attr[] = { 1786static struct attribute *dme1737_in7_attr[] = {
1716 &sensor_dev_attr_in7_input.dev_attr.attr, 1787 &sensor_dev_attr_in7_input.dev_attr.attr,
1717 &sensor_dev_attr_in7_min.dev_attr.attr, 1788 &sensor_dev_attr_in7_min.dev_attr.attr,
@@ -1724,9 +1795,11 @@ static const struct attribute_group dme1737_in7_group = {
1724 .attrs = dme1737_in7_attr, 1795 .attrs = dme1737_in7_attr,
1725}; 1796};
1726 1797
1727/* The following structs hold the PWM attributes, some of which are optional. 1798/*
1799 * The following structs hold the PWM attributes, some of which are optional.
1728 * Their creation depends on the chip configuration which is determined during 1800 * Their creation depends on the chip configuration which is determined during
1729 * module load. */ 1801 * module load.
1802 */
1730static struct attribute *dme1737_pwm1_attr[] = { 1803static struct attribute *dme1737_pwm1_attr[] = {
1731 &sensor_dev_attr_pwm1.dev_attr.attr, 1804 &sensor_dev_attr_pwm1.dev_attr.attr,
1732 &sensor_dev_attr_pwm1_freq.dev_attr.attr, 1805 &sensor_dev_attr_pwm1_freq.dev_attr.attr,
@@ -1779,18 +1852,22 @@ static const struct attribute_group dme1737_pwm_group[] = {
1779 { .attrs = dme1737_pwm6_attr }, 1852 { .attrs = dme1737_pwm6_attr },
1780}; 1853};
1781 1854
1782/* The following struct holds auto PWM min attributes, which are not available 1855/*
1856 * The following struct holds auto PWM min attributes, which are not available
1783 * in all chips. Their creation depends on the chip type which is determined 1857 * in all chips. Their creation depends on the chip type which is determined
1784 * during module load. */ 1858 * during module load.
1859 */
1785static struct attribute *dme1737_auto_pwm_min_attr[] = { 1860static struct attribute *dme1737_auto_pwm_min_attr[] = {
1786 &sensor_dev_attr_pwm1_auto_pwm_min.dev_attr.attr, 1861 &sensor_dev_attr_pwm1_auto_pwm_min.dev_attr.attr,
1787 &sensor_dev_attr_pwm2_auto_pwm_min.dev_attr.attr, 1862 &sensor_dev_attr_pwm2_auto_pwm_min.dev_attr.attr,
1788 &sensor_dev_attr_pwm3_auto_pwm_min.dev_attr.attr, 1863 &sensor_dev_attr_pwm3_auto_pwm_min.dev_attr.attr,
1789}; 1864};
1790 1865
1791/* The following structs hold the fan attributes, some of which are optional. 1866/*
1867 * The following structs hold the fan attributes, some of which are optional.
1792 * Their creation depends on the chip configuration which is determined during 1868 * Their creation depends on the chip configuration which is determined during
1793 * module load. */ 1869 * module load.
1870 */
1794static struct attribute *dme1737_fan1_attr[] = { 1871static struct attribute *dme1737_fan1_attr[] = {
1795 &sensor_dev_attr_fan1_input.dev_attr.attr, 1872 &sensor_dev_attr_fan1_input.dev_attr.attr,
1796 &sensor_dev_attr_fan1_min.dev_attr.attr, 1873 &sensor_dev_attr_fan1_min.dev_attr.attr,
@@ -1843,8 +1920,10 @@ static const struct attribute_group dme1737_fan_group[] = {
1843 { .attrs = dme1737_fan6_attr }, 1920 { .attrs = dme1737_fan6_attr },
1844}; 1921};
1845 1922
1846/* The permissions of the following zone attributes are changed to read- 1923/*
1847 * writeable if the chip is *not* locked. Otherwise they stay read-only. */ 1924 * The permissions of the following zone attributes are changed to read-
1925 * writeable if the chip is *not* locked. Otherwise they stay read-only.
1926 */
1848static struct attribute *dme1737_zone_chmod_attr[] = { 1927static struct attribute *dme1737_zone_chmod_attr[] = {
1849 &sensor_dev_attr_zone1_auto_point1_temp.dev_attr.attr, 1928 &sensor_dev_attr_zone1_auto_point1_temp.dev_attr.attr,
1850 &sensor_dev_attr_zone1_auto_point2_temp.dev_attr.attr, 1929 &sensor_dev_attr_zone1_auto_point2_temp.dev_attr.attr,
@@ -1860,8 +1939,10 @@ static const struct attribute_group dme1737_zone_chmod_group = {
1860}; 1939};
1861 1940
1862 1941
1863/* The permissions of the following zone 3 attributes are changed to read- 1942/*
1864 * writeable if the chip is *not* locked. Otherwise they stay read-only. */ 1943 * The permissions of the following zone 3 attributes are changed to read-
1944 * writeable if the chip is *not* locked. Otherwise they stay read-only.
1945 */
1865static struct attribute *dme1737_zone3_chmod_attr[] = { 1946static struct attribute *dme1737_zone3_chmod_attr[] = {
1866 &sensor_dev_attr_zone3_auto_point1_temp.dev_attr.attr, 1947 &sensor_dev_attr_zone3_auto_point1_temp.dev_attr.attr,
1867 &sensor_dev_attr_zone3_auto_point2_temp.dev_attr.attr, 1948 &sensor_dev_attr_zone3_auto_point2_temp.dev_attr.attr,
@@ -1873,9 +1954,11 @@ static const struct attribute_group dme1737_zone3_chmod_group = {
1873 .attrs = dme1737_zone3_chmod_attr, 1954 .attrs = dme1737_zone3_chmod_attr,
1874}; 1955};
1875 1956
1876/* The permissions of the following PWM attributes are changed to read- 1957/*
1958 * The permissions of the following PWM attributes are changed to read-
1877 * writeable if the chip is *not* locked and the respective PWM is available. 1959 * writeable if the chip is *not* locked and the respective PWM is available.
1878 * Otherwise they stay read-only. */ 1960 * Otherwise they stay read-only.
1961 */
1879static struct attribute *dme1737_pwm1_chmod_attr[] = { 1962static struct attribute *dme1737_pwm1_chmod_attr[] = {
1880 &sensor_dev_attr_pwm1_freq.dev_attr.attr, 1963 &sensor_dev_attr_pwm1_freq.dev_attr.attr,
1881 &sensor_dev_attr_pwm1_enable.dev_attr.attr, 1964 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
@@ -1920,8 +2003,10 @@ static const struct attribute_group dme1737_pwm_chmod_group[] = {
1920 { .attrs = dme1737_pwm6_chmod_attr }, 2003 { .attrs = dme1737_pwm6_chmod_attr },
1921}; 2004};
1922 2005
1923/* Pwm[1-3] are read-writeable if the associated pwm is in manual mode and the 2006/*
1924 * chip is not locked. Otherwise they are read-only. */ 2007 * Pwm[1-3] are read-writeable if the associated pwm is in manual mode and the
2008 * chip is not locked. Otherwise they are read-only.
2009 */
1925static struct attribute *dme1737_pwm_chmod_attr[] = { 2010static struct attribute *dme1737_pwm_chmod_attr[] = {
1926 &sensor_dev_attr_pwm1.dev_attr.attr, 2011 &sensor_dev_attr_pwm1.dev_attr.attr,
1927 &sensor_dev_attr_pwm2.dev_attr.attr, 2012 &sensor_dev_attr_pwm2.dev_attr.attr,
@@ -1975,9 +2060,8 @@ static void dme1737_chmod_group(struct device *dev,
1975{ 2060{
1976 struct attribute **attr; 2061 struct attribute **attr;
1977 2062
1978 for (attr = group->attrs; *attr; attr++) { 2063 for (attr = group->attrs; *attr; attr++)
1979 dme1737_chmod_file(dev, *attr, mode); 2064 dme1737_chmod_file(dev, *attr, mode);
1980 }
1981} 2065}
1982 2066
1983static void dme1737_remove_files(struct device *dev) 2067static void dme1737_remove_files(struct device *dev)
@@ -2003,26 +2087,20 @@ static void dme1737_remove_files(struct device *dev)
2003 } 2087 }
2004 } 2088 }
2005 2089
2006 if (data->has_features & HAS_TEMP_OFFSET) { 2090 if (data->has_features & HAS_TEMP_OFFSET)
2007 sysfs_remove_group(&dev->kobj, &dme1737_temp_offset_group); 2091 sysfs_remove_group(&dev->kobj, &dme1737_temp_offset_group);
2008 } 2092 if (data->has_features & HAS_VID)
2009 if (data->has_features & HAS_VID) {
2010 sysfs_remove_group(&dev->kobj, &dme1737_vid_group); 2093 sysfs_remove_group(&dev->kobj, &dme1737_vid_group);
2011 } 2094 if (data->has_features & HAS_ZONE3)
2012 if (data->has_features & HAS_ZONE3) {
2013 sysfs_remove_group(&dev->kobj, &dme1737_zone3_group); 2095 sysfs_remove_group(&dev->kobj, &dme1737_zone3_group);
2014 } 2096 if (data->has_features & HAS_ZONE_HYST)
2015 if (data->has_features & HAS_ZONE_HYST) {
2016 sysfs_remove_group(&dev->kobj, &dme1737_zone_hyst_group); 2097 sysfs_remove_group(&dev->kobj, &dme1737_zone_hyst_group);
2017 } 2098 if (data->has_features & HAS_IN7)
2018 if (data->has_features & HAS_IN7) {
2019 sysfs_remove_group(&dev->kobj, &dme1737_in7_group); 2099 sysfs_remove_group(&dev->kobj, &dme1737_in7_group);
2020 }
2021 sysfs_remove_group(&dev->kobj, &dme1737_group); 2100 sysfs_remove_group(&dev->kobj, &dme1737_group);
2022 2101
2023 if (!data->client) { 2102 if (!data->client)
2024 sysfs_remove_file(&dev->kobj, &dev_attr_name.attr); 2103 sysfs_remove_file(&dev->kobj, &dev_attr_name.attr);
2025 }
2026} 2104}
2027 2105
2028static int dme1737_create_files(struct device *dev) 2106static int dme1737_create_files(struct device *dev)
@@ -2033,48 +2111,41 @@ static int dme1737_create_files(struct device *dev)
2033 /* Create a name attribute for ISA devices */ 2111 /* Create a name attribute for ISA devices */
2034 if (!data->client) { 2112 if (!data->client) {
2035 err = sysfs_create_file(&dev->kobj, &dev_attr_name.attr); 2113 err = sysfs_create_file(&dev->kobj, &dev_attr_name.attr);
2036 if (err) { 2114 if (err)
2037 goto exit; 2115 goto exit;
2038 }
2039 } 2116 }
2040 2117
2041 /* Create standard sysfs attributes */ 2118 /* Create standard sysfs attributes */
2042 err = sysfs_create_group(&dev->kobj, &dme1737_group); 2119 err = sysfs_create_group(&dev->kobj, &dme1737_group);
2043 if (err) { 2120 if (err)
2044 goto exit_remove; 2121 goto exit_remove;
2045 }
2046 2122
2047 /* Create chip-dependent sysfs attributes */ 2123 /* Create chip-dependent sysfs attributes */
2048 if (data->has_features & HAS_TEMP_OFFSET) { 2124 if (data->has_features & HAS_TEMP_OFFSET) {
2049 err = sysfs_create_group(&dev->kobj, 2125 err = sysfs_create_group(&dev->kobj,
2050 &dme1737_temp_offset_group); 2126 &dme1737_temp_offset_group);
2051 if (err) { 2127 if (err)
2052 goto exit_remove; 2128 goto exit_remove;
2053 }
2054 } 2129 }
2055 if (data->has_features & HAS_VID) { 2130 if (data->has_features & HAS_VID) {
2056 err = sysfs_create_group(&dev->kobj, &dme1737_vid_group); 2131 err = sysfs_create_group(&dev->kobj, &dme1737_vid_group);
2057 if (err) { 2132 if (err)
2058 goto exit_remove; 2133 goto exit_remove;
2059 }
2060 } 2134 }
2061 if (data->has_features & HAS_ZONE3) { 2135 if (data->has_features & HAS_ZONE3) {
2062 err = sysfs_create_group(&dev->kobj, &dme1737_zone3_group); 2136 err = sysfs_create_group(&dev->kobj, &dme1737_zone3_group);
2063 if (err) { 2137 if (err)
2064 goto exit_remove; 2138 goto exit_remove;
2065 }
2066 } 2139 }
2067 if (data->has_features & HAS_ZONE_HYST) { 2140 if (data->has_features & HAS_ZONE_HYST) {
2068 err = sysfs_create_group(&dev->kobj, &dme1737_zone_hyst_group); 2141 err = sysfs_create_group(&dev->kobj, &dme1737_zone_hyst_group);
2069 if (err) { 2142 if (err)
2070 goto exit_remove; 2143 goto exit_remove;
2071 }
2072 } 2144 }
2073 if (data->has_features & HAS_IN7) { 2145 if (data->has_features & HAS_IN7) {
2074 err = sysfs_create_group(&dev->kobj, &dme1737_in7_group); 2146 err = sysfs_create_group(&dev->kobj, &dme1737_in7_group);
2075 if (err) { 2147 if (err)
2076 goto exit_remove; 2148 goto exit_remove;
2077 }
2078 } 2149 }
2079 2150
2080 /* Create fan sysfs attributes */ 2151 /* Create fan sysfs attributes */
@@ -2082,9 +2153,8 @@ static int dme1737_create_files(struct device *dev)
2082 if (data->has_features & HAS_FAN(ix)) { 2153 if (data->has_features & HAS_FAN(ix)) {
2083 err = sysfs_create_group(&dev->kobj, 2154 err = sysfs_create_group(&dev->kobj,
2084 &dme1737_fan_group[ix]); 2155 &dme1737_fan_group[ix]);
2085 if (err) { 2156 if (err)
2086 goto exit_remove; 2157 goto exit_remove;
2087 }
2088 } 2158 }
2089 } 2159 }
2090 2160
@@ -2093,21 +2163,21 @@ static int dme1737_create_files(struct device *dev)
2093 if (data->has_features & HAS_PWM(ix)) { 2163 if (data->has_features & HAS_PWM(ix)) {
2094 err = sysfs_create_group(&dev->kobj, 2164 err = sysfs_create_group(&dev->kobj,
2095 &dme1737_pwm_group[ix]); 2165 &dme1737_pwm_group[ix]);
2096 if (err) { 2166 if (err)
2097 goto exit_remove; 2167 goto exit_remove;
2098 }
2099 if ((data->has_features & HAS_PWM_MIN) && (ix < 3)) { 2168 if ((data->has_features & HAS_PWM_MIN) && (ix < 3)) {
2100 err = sysfs_create_file(&dev->kobj, 2169 err = sysfs_create_file(&dev->kobj,
2101 dme1737_auto_pwm_min_attr[ix]); 2170 dme1737_auto_pwm_min_attr[ix]);
2102 if (err) { 2171 if (err)
2103 goto exit_remove; 2172 goto exit_remove;
2104 }
2105 } 2173 }
2106 } 2174 }
2107 } 2175 }
2108 2176
2109 /* Inform if the device is locked. Otherwise change the permissions of 2177 /*
2110 * selected attributes from read-only to read-writeable. */ 2178 * Inform if the device is locked. Otherwise change the permissions of
2179 * selected attributes from read-only to read-writeable.
2180 */
2111 if (data->config & 0x02) { 2181 if (data->config & 0x02) {
2112 dev_info(dev, "Device is locked. Some attributes " 2182 dev_info(dev, "Device is locked. Some attributes "
2113 "will be read-only.\n"); 2183 "will be read-only.\n");
@@ -2194,26 +2264,30 @@ static int dme1737_init_device(struct device *dev)
2194 return -EFAULT; 2264 return -EFAULT;
2195 } 2265 }
2196 2266
2197 /* Determine which optional fan and pwm features are enabled (only 2267 /*
2198 * valid for I2C devices) */ 2268 * Determine which optional fan and pwm features are enabled (only
2269 * valid for I2C devices)
2270 */
2199 if (client) { /* I2C chip */ 2271 if (client) { /* I2C chip */
2200 data->config2 = dme1737_read(data, DME1737_REG_CONFIG2); 2272 data->config2 = dme1737_read(data, DME1737_REG_CONFIG2);
2201 /* Check if optional fan3 input is enabled */ 2273 /* Check if optional fan3 input is enabled */
2202 if (data->config2 & 0x04) { 2274 if (data->config2 & 0x04)
2203 data->has_features |= HAS_FAN(2); 2275 data->has_features |= HAS_FAN(2);
2204 }
2205 2276
2206 /* Fan4 and pwm3 are only available if the client's I2C address 2277 /*
2278 * Fan4 and pwm3 are only available if the client's I2C address
2207 * is the default 0x2e. Otherwise the I/Os associated with 2279 * is the default 0x2e. Otherwise the I/Os associated with
2208 * these functions are used for addr enable/select. */ 2280 * these functions are used for addr enable/select.
2209 if (client->addr == 0x2e) { 2281 */
2282 if (client->addr == 0x2e)
2210 data->has_features |= HAS_FAN(3) | HAS_PWM(2); 2283 data->has_features |= HAS_FAN(3) | HAS_PWM(2);
2211 }
2212 2284
2213 /* Determine which of the optional fan[5-6] and pwm[5-6] 2285 /*
2286 * Determine which of the optional fan[5-6] and pwm[5-6]
2214 * features are enabled. For this, we need to query the runtime 2287 * features are enabled. For this, we need to query the runtime
2215 * registers through the Super-IO LPC interface. Try both 2288 * registers through the Super-IO LPC interface. Try both
2216 * config ports 0x2e and 0x4e. */ 2289 * config ports 0x2e and 0x4e.
2290 */
2217 if (dme1737_i2c_get_features(0x2e, data) && 2291 if (dme1737_i2c_get_features(0x2e, data) &&
2218 dme1737_i2c_get_features(0x4e, data)) { 2292 dme1737_i2c_get_features(0x4e, data)) {
2219 dev_warn(dev, "Failed to query Super-IO for optional " 2293 dev_warn(dev, "Failed to query Super-IO for optional "
@@ -2271,9 +2345,11 @@ static int dme1737_init_device(struct device *dev)
2271 ((reg >> 4) & 0x03) + 1); 2345 ((reg >> 4) & 0x03) + 1);
2272 } 2346 }
2273 2347
2274 /* Switch pwm[1-3] to manual mode if they are currently disabled and 2348 /*
2349 * Switch pwm[1-3] to manual mode if they are currently disabled and
2275 * set the duty-cycles to 0% (which is identical to the PWMs being 2350 * set the duty-cycles to 0% (which is identical to the PWMs being
2276 * disabled). */ 2351 * disabled).
2352 */
2277 if (!(data->config & 0x02)) { 2353 if (!(data->config & 0x02)) {
2278 for (ix = 0; ix < 3; ix++) { 2354 for (ix = 0; ix < 3; ix++) {
2279 data->pwm_config[ix] = dme1737_read(data, 2355 data->pwm_config[ix] = dme1737_read(data,
@@ -2298,9 +2374,8 @@ static int dme1737_init_device(struct device *dev)
2298 data->pwm_acz[2] = 4; /* pwm3 -> zone3 */ 2374 data->pwm_acz[2] = 4; /* pwm3 -> zone3 */
2299 2375
2300 /* Set VRM */ 2376 /* Set VRM */
2301 if (data->has_features & HAS_VID) { 2377 if (data->has_features & HAS_VID)
2302 data->vrm = vid_which_vrm(); 2378 data->vrm = vid_which_vrm();
2303 }
2304 2379
2305 return 0; 2380 return 0;
2306} 2381}
@@ -2318,8 +2393,10 @@ static int dme1737_i2c_get_features(int sio_cip, struct dme1737_data *data)
2318 2393
2319 dme1737_sio_enter(sio_cip); 2394 dme1737_sio_enter(sio_cip);
2320 2395
2321 /* Check device ID 2396 /*
2322 * We currently know about two kinds of DME1737 and SCH5027. */ 2397 * Check device ID
2398 * We currently know about two kinds of DME1737 and SCH5027.
2399 */
2323 reg = force_id ? force_id : dme1737_sio_inb(sio_cip, 0x20); 2400 reg = force_id ? force_id : dme1737_sio_inb(sio_cip, 0x20);
2324 if (!(reg == DME1737_ID_1 || reg == DME1737_ID_2 || 2401 if (!(reg == DME1737_ID_1 || reg == DME1737_ID_2 ||
2325 reg == SCH5027_ID)) { 2402 reg == SCH5027_ID)) {
@@ -2338,21 +2415,19 @@ static int dme1737_i2c_get_features(int sio_cip, struct dme1737_data *data)
2338 goto exit; 2415 goto exit;
2339 } 2416 }
2340 2417
2341 /* Read the runtime registers to determine which optional features 2418 /*
2419 * Read the runtime registers to determine which optional features
2342 * are enabled and available. Bits [3:2] of registers 0x43-0x46 are set 2420 * are enabled and available. Bits [3:2] of registers 0x43-0x46 are set
2343 * to '10' if the respective feature is enabled. */ 2421 * to '10' if the respective feature is enabled.
2344 if ((inb(addr + 0x43) & 0x0c) == 0x08) { /* fan6 */ 2422 */
2423 if ((inb(addr + 0x43) & 0x0c) == 0x08) /* fan6 */
2345 data->has_features |= HAS_FAN(5); 2424 data->has_features |= HAS_FAN(5);
2346 } 2425 if ((inb(addr + 0x44) & 0x0c) == 0x08) /* pwm6 */
2347 if ((inb(addr + 0x44) & 0x0c) == 0x08) { /* pwm6 */
2348 data->has_features |= HAS_PWM(5); 2426 data->has_features |= HAS_PWM(5);
2349 } 2427 if ((inb(addr + 0x45) & 0x0c) == 0x08) /* fan5 */
2350 if ((inb(addr + 0x45) & 0x0c) == 0x08) { /* fan5 */
2351 data->has_features |= HAS_FAN(4); 2428 data->has_features |= HAS_FAN(4);
2352 } 2429 if ((inb(addr + 0x46) & 0x0c) == 0x08) /* pwm5 */
2353 if ((inb(addr + 0x46) & 0x0c) == 0x08) { /* pwm5 */
2354 data->has_features |= HAS_PWM(4); 2430 data->has_features |= HAS_PWM(4);
2355 }
2356 2431
2357exit: 2432exit:
2358 dme1737_sio_exit(sio_cip); 2433 dme1737_sio_exit(sio_cip);
@@ -2369,9 +2444,8 @@ static int dme1737_i2c_detect(struct i2c_client *client,
2369 u8 company, verstep = 0; 2444 u8 company, verstep = 0;
2370 const char *name; 2445 const char *name;
2371 2446
2372 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) { 2447 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
2373 return -ENODEV; 2448 return -ENODEV;
2374 }
2375 2449
2376 company = i2c_smbus_read_byte_data(client, DME1737_REG_COMPANY); 2450 company = i2c_smbus_read_byte_data(client, DME1737_REG_COMPANY);
2377 verstep = i2c_smbus_read_byte_data(client, DME1737_REG_VERSTEP); 2451 verstep = i2c_smbus_read_byte_data(client, DME1737_REG_VERSTEP);
@@ -2486,8 +2560,10 @@ static int __init dme1737_isa_detect(int sio_cip, unsigned short *addr)
2486 2560
2487 dme1737_sio_enter(sio_cip); 2561 dme1737_sio_enter(sio_cip);
2488 2562
2489 /* Check device ID 2563 /*
2490 * We currently know about SCH3112, SCH3114, SCH3116, and SCH5127 */ 2564 * Check device ID
2565 * We currently know about SCH3112, SCH3114, SCH3116, and SCH5127
2566 */
2491 reg = force_id ? force_id : dme1737_sio_inb(sio_cip, 0x20); 2567 reg = force_id ? force_id : dme1737_sio_inb(sio_cip, 0x20);
2492 if (!(reg == SCH3112_ID || reg == SCH3114_ID || reg == SCH3116_ID || 2568 if (!(reg == SCH3112_ID || reg == SCH3114_ID || reg == SCH3116_ID ||
2493 reg == SCH5127_ID)) { 2569 reg == SCH5127_ID)) {
@@ -2507,8 +2583,10 @@ static int __init dme1737_isa_detect(int sio_cip, unsigned short *addr)
2507 goto exit; 2583 goto exit;
2508 } 2584 }
2509 2585
2510 /* Access to the hwmon registers is through an index/data register 2586 /*
2511 * pair located at offset 0x70/0x71. */ 2587 * Access to the hwmon registers is through an index/data register
2588 * pair located at offset 0x70/0x71.
2589 */
2512 *addr = base_addr + 0x70; 2590 *addr = base_addr + 0x70;
2513 2591
2514exit: 2592exit:
@@ -2610,11 +2688,10 @@ static int __devinit dme1737_isa_probe(struct platform_device *pdev)
2610 } 2688 }
2611 } 2689 }
2612 2690
2613 if (data->type == sch5127) { 2691 if (data->type == sch5127)
2614 data->name = "sch5127"; 2692 data->name = "sch5127";
2615 } else { 2693 else
2616 data->name = "sch311x"; 2694 data->name = "sch311x";
2617 }
2618 2695
2619 /* Initialize the mutex */ 2696 /* Initialize the mutex */
2620 mutex_init(&data->update_lock); 2697 mutex_init(&data->update_lock);
@@ -2689,9 +2766,8 @@ static int __init dme1737_init(void)
2689 unsigned short addr; 2766 unsigned short addr;
2690 2767
2691 err = i2c_add_driver(&dme1737_i2c_driver); 2768 err = i2c_add_driver(&dme1737_i2c_driver);
2692 if (err) { 2769 if (err)
2693 goto exit; 2770 goto exit;
2694 }
2695 2771
2696 if (dme1737_isa_detect(0x2e, &addr) && 2772 if (dme1737_isa_detect(0x2e, &addr) &&
2697 dme1737_isa_detect(0x4e, &addr) && 2773 dme1737_isa_detect(0x4e, &addr) &&
@@ -2703,15 +2779,13 @@ static int __init dme1737_init(void)
2703 } 2779 }
2704 2780
2705 err = platform_driver_register(&dme1737_isa_driver); 2781 err = platform_driver_register(&dme1737_isa_driver);
2706 if (err) { 2782 if (err)
2707 goto exit_del_i2c_driver; 2783 goto exit_del_i2c_driver;
2708 }
2709 2784
2710 /* Sets global pdev as a side effect */ 2785 /* Sets global pdev as a side effect */
2711 err = dme1737_isa_device_add(addr); 2786 err = dme1737_isa_device_add(addr);
2712 if (err) { 2787 if (err)
2713 goto exit_del_isa_driver; 2788 goto exit_del_isa_driver;
2714 }
2715 2789
2716 return 0; 2790 return 0;
2717 2791