m68knommu: use MCF_IRQ_PIT1 instead of MCFINT_VECBASE + MCFINT_PIT1

use MCF_IRQ_PIT1 instead of MCFINT_VECBASE + MCFINT_PIT1 so we can support
those parts that have the pit1 interrupt on other than the first interrupt
controller.

Signed-off-by: Steven King <sfking@fdwdc.com>
Signed-off-by: Greg Ungerer <gerg@uclinux.org>

5 files changed, 6 insertions, 3 deletions

diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h
index 17f2aab9cf97..5a8b5e4da12b 100644
--- a/arch/m68k/include/asm/m520xsim.h
+++ b/arch/m68k/include/asm/m520xsim.h
@@ -62,6 +62,7 @@
 #define MCF_IRQ_FECENTC0    (MCFINT_VECBASE + MCFINT_FECENTC0)
 
 #define MCF_IRQ_QSPI        (MCFINT_VECBASE + MCFINT_QSPI)
+#define MCF_IRQ_PIT1        (MCFINT_VECBASE + MCFINT_PIT1)
 
 /*
  *  SDRAM configuration registers.
diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h
index 075062d4eecd..91d3abc3f2a5 100644
--- a/arch/m68k/include/asm/m523xsim.h
+++ b/arch/m68k/include/asm/m523xsim.h
@@ -52,6 +52,7 @@
 #define MCF_IRQ_FECENTC0        (MCFINT_VECBASE + MCFINT_FECENTC0)
 
 #define MCF_IRQ_QSPI            (MCFINT_VECBASE + MCFINT_QSPI)
+#define MCF_IRQ_PIT1            (MCFINT_VECBASE + MCFINT_PIT1)
 
 /*
  *      SDRAM configuration registers.
diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h
index 83db8106f50a..71aa5104d3d6 100644
--- a/arch/m68k/include/asm/m527xsim.h
+++ b/arch/m68k/include/asm/m527xsim.h
@@ -60,6 +60,7 @@
 #define MCF_IRQ_FECENTC1        (MCFINT2_VECBASE + MCFINT2_FECENTC1)
 
 #define MCF_IRQ_QSPI            (MCFINT_VECBASE + MCFINT_QSPI)
+#define MCF_IRQ_PIT1            (MCFINT_VECBASE + MCFINT_PIT1)
 
 /*
  *      SDRAM configuration registers.
diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h
index 497c31c803ff..4acb3c0a642e 100644
--- a/arch/m68k/include/asm/m528xsim.h
+++ b/arch/m68k/include/asm/m528xsim.h
@@ -52,7 +52,7 @@
 #define MCF_IRQ_FECENTC0        (MCFINT_VECBASE + MCFINT_FECENTC0)
 
 #define MCF_IRQ_QSPI            (MCFINT_VECBASE + MCFINT_QSPI)
-
+#define MCF_IRQ_PIT1            (MCFINT_VECBASE + MCFINT_PIT1)
 /*
  *      SDRAM configuration registers.
  */
diff --git a/arch/m68k/platform/coldfire/pit.c b/arch/m68k/platform/coldfire/pit.c
index e62dbbcb10f6..e8f3b97b0f77 100644
--- a/arch/m68k/platform/coldfire/pit.c
+++ b/arch/m68k/platform/coldfire/pit.c
@@ -93,7 +93,7 @@ struct clock_event_device cf_pit_clockevent = {
         .set_mode       = init_cf_pit_timer,
         .set_next_event = cf_pit_next_event,
         .shift          = 32,
-        .irq            = MCFINT_VECBASE + MCFINT_PIT1,
+        .irq            = MCF_IRQ_PIT1,
 };
 
 
@@ -159,7 +159,7 @@ void hw_timer_init(irq_handler_t handler)
                 clockevent_delta2ns(0x3f, &cf_pit_clockevent);
         clockevents_register_device(&cf_pit_clockevent);
 
-        setup_irq(MCFINT_VECBASE + MCFINT_PIT1, &pit_irq);
+        setup_irq(MCF_IRQ_PIT1, &pit_irq);
 
         clocksource_register_hz(&pit_clk, FREQ);
 }