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authorMartyn Welch <martyn.welch@gefanuc.com>2009-01-19 06:33:24 -0500
committerKumar Gala <galak@kernel.crashing.org>2009-01-29 00:03:20 -0500
commitbb2b66dca1c4cbe16d8208d4b2910cf0eb6e9f75 (patch)
treea7da9bce77072855c0a6d13bb93aca46664bdeff
parentd0839118f396f6d7af553e99ad204aa2b3209cde (diff)
powerpc/86xx: Board support for GE Fanuc SBC310
Support for the SBC310 VPX Single Board Computer from GE Fanuc (PowerPC MPC8641D). This is the basic board support for GE Fanuc's SBC310, a 3U single board computer, based on Freescale's MPC8641D. Signed-off-by: Martyn Welch <martyn.welch@gefanuc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat
-rw-r--r--arch/powerpc/boot/dts/gef_sbc310.dts364
-rw-r--r--arch/powerpc/platforms/86xx/Kconfig10
-rw-r--r--arch/powerpc/platforms/86xx/Makefile1
-rw-r--r--arch/powerpc/platforms/86xx/gef_sbc310.c230
-rw-r--r--drivers/watchdog/Kconfig2
5 files changed, 605 insertions, 2 deletions
diff --git a/arch/powerpc/boot/dts/gef_sbc310.dts b/arch/powerpc/boot/dts/gef_sbc310.dts
new file mode 100644
index 000000000000..09eeb438216b
--- /dev/null
+++ b/arch/powerpc/boot/dts/gef_sbc310.dts
@@ -0,0 +1,364 @@
1/*
2 * GE Fanuc SBC310 Device Tree Source
3 *
4 * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * Based on: SBS CM6 Device Tree Source
12 * Copyright 2007 SBS Technologies GmbH & Co. KG
13 * And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
14 * Copyright 2006 Freescale Semiconductor Inc.
15 */
16
17/*
18 * Compiled with dtc -I dts -O dtb -o gef_sbc310.dtb gef_sbc310.dts
19 */
20
21/dts-v1/;
22
23/ {
24 model = "GEF_SBC310";
25 compatible = "gef,sbc310";
26 #address-cells = <1>;
27 #size-cells = <1>;
28
29 aliases {
30 ethernet0 = &enet0;
31 ethernet1 = &enet1;
32 serial0 = &serial0;
33 serial1 = &serial1;
34 pci0 = &pci0;
35 };
36
37 cpus {
38 #address-cells = <1>;
39 #size-cells = <0>;
40
41 PowerPC,8641@0 {
42 device_type = "cpu";
43 reg = <0>;
44 d-cache-line-size = <32>; // 32 bytes
45 i-cache-line-size = <32>; // 32 bytes
46 d-cache-size = <32768>; // L1, 32K
47 i-cache-size = <32768>; // L1, 32K
48 timebase-frequency = <0>; // From uboot
49 bus-frequency = <0>; // From uboot
50 clock-frequency = <0>; // From uboot
51 };
52 PowerPC,8641@1 {
53 device_type = "cpu";
54 reg = <1>;
55 d-cache-line-size = <32>; // 32 bytes
56 i-cache-line-size = <32>; // 32 bytes
57 d-cache-size = <32768>; // L1, 32K
58 i-cache-size = <32768>; // L1, 32K
59 timebase-frequency = <0>; // From uboot
60 bus-frequency = <0>; // From uboot
61 clock-frequency = <0>; // From uboot
62 };
63 };
64
65 memory {
66 device_type = "memory";
67 reg = <0x0 0x40000000>; // set by uboot
68 };
69
70 localbus@fef05000 {
71 #address-cells = <2>;
72 #size-cells = <1>;
73 compatible = "fsl,mpc8641-localbus", "simple-bus";
74 reg = <0xfef05000 0x1000>;
75 interrupts = <19 2>;
76 interrupt-parent = <&mpic>;
77
78 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
79 1 0 0xe0000000 0x08000000 // Paged Flash 0
80 2 0 0xe8000000 0x08000000 // Paged Flash 1
81 3 0 0xfc100000 0x00020000 // NVRAM
82 4 0 0xfc000000 0x00010000>; // FPGA
83
84 /* flash@0,0 is a mirror of part of the memory in flash@1,0
85 flash@0,0 {
86 compatible = "cfi-flash";
87 reg = <0 0 0x01000000>;
88 bank-width = <2>;
89 device-width = <2>;
90 #address-cells = <1>;
91 #size-cells = <1>;
92 partition@0 {
93 label = "firmware";
94 reg = <0x00000000 0x01000000>;
95 read-only;
96 };
97 };
98 */
99
100 flash@1,0 {
101 compatible = "cfi-flash";
102 reg = <1 0 0x8000000>;
103 bank-width = <2>;
104 device-width = <2>;
105 #address-cells = <1>;
106 #size-cells = <1>;
107 partition@0 {
108 label = "user";
109 reg = <0x00000000 0x07800000>;
110 };
111 partition@7800000 {
112 label = "firmware";
113 reg = <0x07800000 0x00800000>;
114 read-only;
115 };
116 };
117
118 fpga@4,0 {
119 compatible = "gef,fpga-regs";
120 reg = <0x4 0x0 0x40>;
121 };
122
123 wdt@4,2000 {
124 #interrupt-cells = <2>;
125 device_type = "watchdog";
126 compatible = "gef,fpga-wdt";
127 reg = <0x4 0x2000 0x8>;
128 interrupts = <0x1a 0x4>;
129 interrupt-parent = <&gef_pic>;
130 };
131/*
132 wdt@4,2010 {
133 #interrupt-cells = <2>;
134 device_type = "watchdog";
135 compatible = "gef,fpga-wdt";
136 reg = <0x4 0x2010 0x8>;
137 interrupts = <0x1b 0x4>;
138 interrupt-parent = <&gef_pic>;
139 };
140*/
141 gef_pic: pic@4,4000 {
142 #interrupt-cells = <1>;
143 interrupt-controller;
144 compatible = "gef,fpga-pic";
145 reg = <0x4 0x4000 0x20>;
146 interrupts = <0x8
147 0x9>;
148 interrupt-parent = <&mpic>;
149
150 };
151 gef_gpio: gpio@4,8000 {
152 #gpio-cells = <2>;
153 compatible = "gef,sbc310-gpio";
154 reg = <0x4 0x8000 0x24>;
155 gpio-controller;
156 };
157 };
158
159 soc@fef00000 {
160 #address-cells = <1>;
161 #size-cells = <1>;
162 #interrupt-cells = <2>;
163 device_type = "soc";
164 compatible = "simple-bus";
165 ranges = <0x0 0xfef00000 0x00100000>;
166 reg = <0xfef00000 0x100000>; // CCSRBAR 1M
167 bus-frequency = <33333333>;
168
169 i2c1: i2c@3000 {
170 #address-cells = <1>;
171 #size-cells = <0>;
172 compatible = "fsl-i2c";
173 reg = <0x3000 0x100>;
174 interrupts = <0x2b 0x2>;
175 interrupt-parent = <&mpic>;
176 dfsrr;
177
178 rtc@51 {
179 compatible = "epson,rx8581";
180 reg = <0x00000051>;
181 };
182 };
183
184 i2c2: i2c@3100 {
185 #address-cells = <1>;
186 #size-cells = <0>;
187 compatible = "fsl-i2c";
188 reg = <0x3100 0x100>;
189 interrupts = <0x2b 0x2>;
190 interrupt-parent = <&mpic>;
191 dfsrr;
192
193 hwmon@48 {
194 compatible = "national,lm92";
195 reg = <0x48>;
196 };
197
198 hwmon@4c {
199 compatible = "adi,adt7461";
200 reg = <0x4c>;
201 };
202
203 eti@6b {
204 compatible = "dallas,ds1682";
205 reg = <0x6b>;
206 };
207 };
208
209 dma@21300 {
210 #address-cells = <1>;
211 #size-cells = <1>;
212 compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
213 reg = <0x21300 0x4>;
214 ranges = <0x0 0x21100 0x200>;
215 cell-index = <0>;
216 dma-channel@0 {
217 compatible = "fsl,mpc8641-dma-channel",
218 "fsl,eloplus-dma-channel";
219 reg = <0x0 0x80>;
220 cell-index = <0>;
221 interrupt-parent = <&mpic>;
222 interrupts = <20 2>;
223 };
224 dma-channel@80 {
225 compatible = "fsl,mpc8641-dma-channel",
226 "fsl,eloplus-dma-channel";
227 reg = <0x80 0x80>;
228 cell-index = <1>;
229 interrupt-parent = <&mpic>;
230 interrupts = <21 2>;
231 };
232 dma-channel@100 {
233 compatible = "fsl,mpc8641-dma-channel",
234 "fsl,eloplus-dma-channel";
235 reg = <0x100 0x80>;
236 cell-index = <2>;
237 interrupt-parent = <&mpic>;
238 interrupts = <22 2>;
239 };
240 dma-channel@180 {
241 compatible = "fsl,mpc8641-dma-channel",
242 "fsl,eloplus-dma-channel";
243 reg = <0x180 0x80>;
244 cell-index = <3>;
245 interrupt-parent = <&mpic>;
246 interrupts = <23 2>;
247 };
248 };
249
250 mdio@24520 {
251 #address-cells = <1>;
252 #size-cells = <0>;
253 compatible = "fsl,gianfar-mdio";
254 reg = <0x24520 0x20>;
255
256 phy0: ethernet-phy@0 {
257 interrupt-parent = <&gef_pic>;
258 interrupts = <0x9 0x4>;
259 reg = <1>;
260 };
261 phy2: ethernet-phy@2 {
262 interrupt-parent = <&gef_pic>;
263 interrupts = <0x8 0x4>;
264 reg = <3>;
265 };
266 };
267
268 enet0: ethernet@24000 {
269 device_type = "network";
270 model = "eTSEC";
271 compatible = "gianfar";
272 reg = <0x24000 0x1000>;
273 local-mac-address = [ 00 00 00 00 00 00 ];
274 interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
275 interrupt-parent = <&mpic>;
276 phy-handle = <&phy0>;
277 phy-connection-type = "gmii";
278 };
279
280 enet1: ethernet@26000 {
281 device_type = "network";
282 model = "eTSEC";
283 compatible = "gianfar";
284 reg = <0x26000 0x1000>;
285 local-mac-address = [ 00 00 00 00 00 00 ];
286 interrupts = <0x1f 0x2 0x20 0x2 0x21 0x2>;
287 interrupt-parent = <&mpic>;
288 phy-handle = <&phy2>;
289 phy-connection-type = "gmii";
290 };
291
292 serial0: serial@4500 {
293 cell-index = <0>;
294 device_type = "serial";
295 compatible = "ns16550";
296 reg = <0x4500 0x100>;
297 clock-frequency = <0>;
298 interrupts = <0x2a 0x2>;
299 interrupt-parent = <&mpic>;
300 };
301
302 serial1: serial@4600 {
303 cell-index = <1>;
304 device_type = "serial";
305 compatible = "ns16550";
306 reg = <0x4600 0x100>;
307 clock-frequency = <0>;
308 interrupts = <0x1c 0x2>;
309 interrupt-parent = <&mpic>;
310 };
311
312 mpic: pic@40000 {
313 clock-frequency = <0>;
314 interrupt-controller;
315 #address-cells = <0>;
316 #interrupt-cells = <2>;
317 reg = <0x40000 0x40000>;
318 compatible = "chrp,open-pic";
319 device_type = "open-pic";
320 };
321
322 global-utilities@e0000 {
323 compatible = "fsl,mpc8641-guts";
324 reg = <0xe0000 0x1000>;
325 fsl,has-rstcr;
326 };
327 };
328
329 pci0: pcie@fef08000 {
330 compatible = "fsl,mpc8641-pcie";
331 device_type = "pci";
332 #interrupt-cells = <1>;
333 #size-cells = <2>;
334 #address-cells = <3>;
335 reg = <0xfef08000 0x1000>;
336 bus-range = <0x0 0xff>;
337 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
338 0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
339 clock-frequency = <33333333>;
340 interrupt-parent = <&mpic>;
341 interrupts = <0x18 0x2>;
342 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
343 interrupt-map = <
344 0x0000 0x0 0x0 0x1 &mpic 0x0 0x2
345 0x0000 0x0 0x0 0x2 &mpic 0x1 0x2
346 0x0000 0x0 0x0 0x3 &mpic 0x2 0x2
347 0x0000 0x0 0x0 0x4 &mpic 0x3 0x2
348 >;
349
350 pcie@0 {
351 reg = <0 0 0 0 0>;
352 #size-cells = <2>;
353 #address-cells = <3>;
354 device_type = "pci";
355 ranges = <0x02000000 0x0 0x80000000
356 0x02000000 0x0 0x80000000
357 0x0 0x40000000
358
359 0x01000000 0x0 0x00000000
360 0x01000000 0x0 0x00000000
361 0x0 0x00400000>;
362 };
363 };
364};
diff --git a/arch/powerpc/platforms/86xx/Kconfig b/arch/powerpc/platforms/86xx/Kconfig
index 8e5693935975..fa276c689cf9 100644
--- a/arch/powerpc/platforms/86xx/Kconfig
+++ b/arch/powerpc/platforms/86xx/Kconfig
@@ -31,6 +31,14 @@ config MPC8610_HPCD
31 help 31 help
32 This option enables support for the MPC8610 HPCD board. 32 This option enables support for the MPC8610 HPCD board.
33 33
34config GEF_SBC310
35 bool "GE Fanuc SBC310"
36 select DEFAULT_UIMAGE
37 select GENERIC_GPIO
38 select ARCH_REQUIRE_GPIOLIB
39 help
40 This option enables support for GE Fanuc's SBC310.
41
34config GEF_SBC610 42config GEF_SBC610
35 bool "GE Fanuc SBC610" 43 bool "GE Fanuc SBC610"
36 select DEFAULT_UIMAGE 44 select DEFAULT_UIMAGE
@@ -48,7 +56,7 @@ config MPC8641
48 select FSL_PCI if PCI 56 select FSL_PCI if PCI
49 select PPC_UDBG_16550 57 select PPC_UDBG_16550
50 select MPIC 58 select MPIC
51 default y if MPC8641_HPCN || SBC8641D || GEF_SBC610 59 default y if MPC8641_HPCN || SBC8641D || GEF_SBC610 || GEF_SBC310
52 60
53config MPC8610 61config MPC8610
54 bool 62 bool
diff --git a/arch/powerpc/platforms/86xx/Makefile b/arch/powerpc/platforms/86xx/Makefile
index 31e540c2ebbc..7c080da4523a 100644
--- a/arch/powerpc/platforms/86xx/Makefile
+++ b/arch/powerpc/platforms/86xx/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_SBC8641D) += sbc8641d.o
9obj-$(CONFIG_MPC8610_HPCD) += mpc8610_hpcd.o 9obj-$(CONFIG_MPC8610_HPCD) += mpc8610_hpcd.o
10gef-gpio-$(CONFIG_GPIOLIB) += gef_gpio.o 10gef-gpio-$(CONFIG_GPIOLIB) += gef_gpio.o
11obj-$(CONFIG_GEF_SBC610) += gef_sbc610.o gef_pic.o $(gef-gpio-y) 11obj-$(CONFIG_GEF_SBC610) += gef_sbc610.o gef_pic.o $(gef-gpio-y)
12obj-$(CONFIG_GEF_SBC310) += gef_sbc310.o gef_pic.o $(gef-gpio-y)
diff --git a/arch/powerpc/platforms/86xx/gef_sbc310.c b/arch/powerpc/platforms/86xx/gef_sbc310.c
new file mode 100644
index 000000000000..0f20172af84b
--- /dev/null
+++ b/arch/powerpc/platforms/86xx/gef_sbc310.c
@@ -0,0 +1,230 @@
1/*
2 * GE Fanuc SBC310 board support
3 *
4 * Author: Martyn Welch <martyn.welch@gefanuc.com>
5 *
6 * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * Based on: mpc86xx_hpcn.c (MPC86xx HPCN board specific routines)
14 * Copyright 2006 Freescale Semiconductor Inc.
15 *
16 * NEC fixup adapted from arch/mips/pci/fixup-lm2e.c
17 */
18
19#include <linux/stddef.h>
20#include <linux/kernel.h>
21#include <linux/pci.h>
22#include <linux/kdev_t.h>
23#include <linux/delay.h>
24#include <linux/seq_file.h>
25#include <linux/of_platform.h>
26
27#include <asm/system.h>
28#include <asm/time.h>
29#include <asm/machdep.h>
30#include <asm/pci-bridge.h>
31#include <asm/mpc86xx.h>
32#include <asm/prom.h>
33#include <mm/mmu_decl.h>
34#include <asm/udbg.h>
35
36#include <asm/mpic.h>
37
38#include <sysdev/fsl_pci.h>
39#include <sysdev/fsl_soc.h>
40
41#include "mpc86xx.h"
42#include "gef_pic.h"
43
44#undef DEBUG
45
46#ifdef DEBUG
47#define DBG (fmt...) do { printk(KERN_ERR "SBC310: " fmt); } while (0)
48#else
49#define DBG (fmt...) do { } while (0)
50#endif
51
52void __iomem *sbc310_regs;
53
54static void __init gef_sbc310_init_irq(void)
55{
56 struct device_node *cascade_node = NULL;
57
58 mpc86xx_init_irq();
59
60 /*
61 * There is a simple interrupt handler in the main FPGA, this needs
62 * to be cascaded into the MPIC
63 */
64 cascade_node = of_find_compatible_node(NULL, NULL, "gef,fpga-pic");
65 if (!cascade_node) {
66 printk(KERN_WARNING "SBC310: No FPGA PIC\n");
67 return;
68 }
69
70 gef_pic_init(cascade_node);
71 of_node_put(cascade_node);
72}
73
74static void __init gef_sbc310_setup_arch(void)
75{
76 struct device_node *regs;
77#ifdef CONFIG_PCI
78 struct device_node *np;
79
80 for_each_compatible_node(np, "pci", "fsl,mpc8641-pcie") {
81 fsl_add_bridge(np, 1);
82 }
83#endif
84
85 printk(KERN_INFO "GE Fanuc Intelligent Platforms SBC310 6U VPX SBC\n");
86
87#ifdef CONFIG_SMP
88 mpc86xx_smp_init();
89#endif
90
91 /* Remap basic board registers */
92 regs = of_find_compatible_node(NULL, NULL, "gef,fpga-regs");
93 if (regs) {
94 sbc310_regs = of_iomap(regs, 0);
95 if (sbc310_regs == NULL)
96 printk(KERN_WARNING "Unable to map board registers\n");
97 of_node_put(regs);
98 }
99}
100
101/* Return the PCB revision */
102static unsigned int gef_sbc310_get_board_id(void)
103{
104 unsigned int reg;
105
106 reg = ioread32(sbc310_regs);
107 return reg & 0xff;
108}
109
110/* Return the PCB revision */
111static unsigned int gef_sbc310_get_pcb_rev(void)
112{
113 unsigned int reg;
114
115 reg = ioread32(sbc310_regs);
116 return (reg >> 8) & 0xff;
117}
118
119/* Return the board (software) revision */
120static unsigned int gef_sbc310_get_board_rev(void)
121{
122 unsigned int reg;
123
124 reg = ioread32(sbc310_regs);
125 return (reg >> 16) & 0xff;
126}
127
128/* Return the FPGA revision */
129static unsigned int gef_sbc310_get_fpga_rev(void)
130{
131 unsigned int reg;
132
133 reg = ioread32(sbc310_regs);
134 return (reg >> 24) & 0xf;
135}
136
137static void gef_sbc310_show_cpuinfo(struct seq_file *m)
138{
139 uint svid = mfspr(SPRN_SVR);
140
141 seq_printf(m, "Vendor\t\t: GE Fanuc Intelligent Platforms\n");
142
143 seq_printf(m, "Board ID\t: 0x%2.2x\n", gef_sbc310_get_board_id());
144 seq_printf(m, "Revision\t: %u%c\n", gef_sbc310_get_pcb_rev(),
145 ('A' + gef_sbc310_get_board_rev() - 1));
146 seq_printf(m, "FPGA Revision\t: %u\n", gef_sbc310_get_fpga_rev());
147
148 seq_printf(m, "SVR\t\t: 0x%x\n", svid);
149
150}
151
152static void __init gef_sbc310_nec_fixup(struct pci_dev *pdev)
153{
154 unsigned int val;
155
156 printk(KERN_INFO "Running NEC uPD720101 Fixup\n");
157
158 /* Ensure only ports 1 & 2 are enabled */
159 pci_read_config_dword(pdev, 0xe0, &val);
160 pci_write_config_dword(pdev, 0xe0, (val & ~7) | 0x2);
161
162 /* System clock is 48-MHz Oscillator and EHCI Enabled. */
163 pci_write_config_dword(pdev, 0xe4, 1 << 5);
164}
165DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB,
166 gef_sbc310_nec_fixup);
167
168/*
169 * Called very early, device-tree isn't unflattened
170 *
171 * This function is called to determine whether the BSP is compatible with the
172 * supplied device-tree, which is assumed to be the correct one for the actual
173 * board. It is expected thati, in the future, a kernel may support multiple
174 * boards.
175 */
176static int __init gef_sbc310_probe(void)
177{
178 unsigned long root = of_get_flat_dt_root();
179
180 if (of_flat_dt_is_compatible(root, "gef,sbc310"))
181 return 1;
182
183 return 0;
184}
185
186static long __init mpc86xx_time_init(void)
187{
188 unsigned int temp;
189
190 /* Set the time base to zero */
191 mtspr(SPRN_TBWL, 0);
192 mtspr(SPRN_TBWU, 0);
193
194 temp = mfspr(SPRN_HID0);
195 temp |= HID0_TBEN;
196 mtspr(SPRN_HID0, temp);
197 asm volatile("isync");
198
199 return 0;
200}
201
202static __initdata struct of_device_id of_bus_ids[] = {
203 { .compatible = "simple-bus", },
204 {},
205};
206
207static int __init declare_of_platform_devices(void)
208{
209 printk(KERN_DEBUG "Probe platform devices\n");
210 of_platform_bus_probe(NULL, of_bus_ids, NULL);
211
212 return 0;
213}
214machine_device_initcall(gef_sbc310, declare_of_platform_devices);
215
216define_machine(gef_sbc310) {
217 .name = "GE Fanuc SBC310",
218 .probe = gef_sbc310_probe,
219 .setup_arch = gef_sbc310_setup_arch,
220 .init_IRQ = gef_sbc310_init_irq,
221 .show_cpuinfo = gef_sbc310_show_cpuinfo,
222 .get_irq = mpic_get_irq,
223 .restart = fsl_rstcr_restart,
224 .time_init = mpc86xx_time_init,
225 .calibrate_decr = generic_calibrate_decr,
226 .progress = udbg_progress,
227#ifdef CONFIG_PCI
228 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
229#endif
230};
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 09a3d5522b43..316ee964b945 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -772,7 +772,7 @@ config TXX9_WDT
772 772
773config GEF_WDT 773config GEF_WDT
774 tristate "GE Fanuc Watchdog Timer" 774 tristate "GE Fanuc Watchdog Timer"
775 depends on GEF_SBC610 775 depends on GEF_SBC610 || GEF_SBC310
776 ---help--- 776 ---help---
777 Watchdog timer found in a number of GE Fanuc single board computers. 777 Watchdog timer found in a number of GE Fanuc single board computers.
778 778
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-25 07:46:23 -0500