diff options
author | Rafał Miłecki <zajec5@gmail.com> | 2011-04-01 06:07:34 -0400 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2011-04-04 16:20:07 -0400 |
commit | ba91d1a1bcccd90247b5b9703c1a236cc2e95698 (patch) | |
tree | c675d1dc7cebe0396e9df0a27d690eea9e853173 | |
parent | 1b1c7acd9709e545399d1b6b89888f025911c0a2 (diff) |
ssb: pci: implement mdio reading
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
-rw-r--r-- | drivers/ssb/driver_pcicore.c | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/drivers/ssb/driver_pcicore.c b/drivers/ssb/driver_pcicore.c index 08fa6fdfc101..76cbf96001f1 100644 --- a/drivers/ssb/driver_pcicore.c +++ b/drivers/ssb/driver_pcicore.c | |||
@@ -467,6 +467,49 @@ static void ssb_pcie_mdio_set_phy(struct ssb_pcicore *pc, u8 phy) | |||
467 | } | 467 | } |
468 | } | 468 | } |
469 | 469 | ||
470 | #if 0 | ||
471 | //done but not used yet | ||
472 | static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address) | ||
473 | { | ||
474 | const u16 mdio_control = 0x128; | ||
475 | const u16 mdio_data = 0x12C; | ||
476 | int max_retries = 10; | ||
477 | u16 ret = 0; | ||
478 | u32 v; | ||
479 | int i; | ||
480 | |||
481 | v = 0x80; /* Enable Preamble Sequence */ | ||
482 | v |= 0x2; /* MDIO Clock Divisor */ | ||
483 | pcicore_write32(pc, mdio_control, v); | ||
484 | |||
485 | if (pc->dev->id.revision >= 10) { | ||
486 | max_retries = 200; | ||
487 | ssb_pcie_mdio_set_phy(pc, device); | ||
488 | } | ||
489 | |||
490 | v = (1 << 30); /* Start of Transaction */ | ||
491 | v |= (1 << 29); /* Read Transaction */ | ||
492 | v |= (1 << 17); /* Turnaround */ | ||
493 | if (pc->dev->id.revision < 10) | ||
494 | v |= (u32)device << 22; | ||
495 | v |= (u32)address << 18; | ||
496 | pcicore_write32(pc, mdio_data, v); | ||
497 | /* Wait for the device to complete the transaction */ | ||
498 | udelay(10); | ||
499 | for (i = 0; i < 200; i++) { | ||
500 | v = pcicore_read32(pc, mdio_control); | ||
501 | if (v & 0x100 /* Trans complete */) { | ||
502 | udelay(10); | ||
503 | ret = pcicore_read32(pc, mdio_data); | ||
504 | break; | ||
505 | } | ||
506 | msleep(1); | ||
507 | } | ||
508 | pcicore_write32(pc, mdio_control, 0); | ||
509 | return ret; | ||
510 | } | ||
511 | #endif | ||
512 | |||
470 | static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device, | 513 | static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device, |
471 | u8 address, u16 data) | 514 | u8 address, u16 data) |
472 | { | 515 | { |