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authorTomoya MORINAGA <tomoya-linux@dsn.okisemi.com>2010-12-23 21:40:50 -0500
committerGrant Likely <grant.likely@secretlab.ca>2010-12-23 22:30:11 -0500
commit9d32af66aa3a0e28d95fc607e208795ef6cc993a (patch)
tree43b196812ee508b532696642ccb193527b91cfc7
parent893421745a052100b981401b7c5c6dc8708fb8a0 (diff)
spi/topcliff_pch: Fix data transfer issue
It seems spi_topcliff_pch of linux-2.6.37-rc6 degraded by previous patch. In fact, data transfer fails on evaluation board testing. I found like the following register miss-setting line. Using this patch, I have confirmed data transfer can work well. Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
-rw-r--r--drivers/spi/spi_topcliff_pch.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/spi/spi_topcliff_pch.c b/drivers/spi/spi_topcliff_pch.c
index 58e187f45ec7..56b758847c04 100644
--- a/drivers/spi/spi_topcliff_pch.c
+++ b/drivers/spi/spi_topcliff_pch.c
@@ -267,7 +267,7 @@ static void pch_spi_handler_sub(struct pch_spi_data *data, u32 reg_spsr_val,
267 if (reg_spsr_val & SPSR_FI_BIT) { 267 if (reg_spsr_val & SPSR_FI_BIT) {
268 /* disable FI & RFI interrupts */ 268 /* disable FI & RFI interrupts */
269 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, 269 pch_spi_setclr_reg(data->master, PCH_SPCR, 0,
270 SPCR_FIE_BIT | SPCR_TFIE_BIT); 270 SPCR_FIE_BIT | SPCR_RFIE_BIT);
271 271
272 /* transfer is completed;inform pch_spi_process_messages */ 272 /* transfer is completed;inform pch_spi_process_messages */
273 data->transfer_complete = true; 273 data->transfer_complete = true;
@@ -679,11 +679,11 @@ static void pch_spi_set_ir(struct pch_spi_data *data)
679 if ((data->bpw_len) > PCH_MAX_FIFO_DEPTH) { 679 if ((data->bpw_len) > PCH_MAX_FIFO_DEPTH) {
680 /* set receive threhold to PCH_RX_THOLD */ 680 /* set receive threhold to PCH_RX_THOLD */
681 pch_spi_setclr_reg(data->master, PCH_SPCR, 681 pch_spi_setclr_reg(data->master, PCH_SPCR,
682 PCH_RX_THOLD << SPCR_TFIC_FIELD, 682 PCH_RX_THOLD << SPCR_RFIC_FIELD,
683 ~MASK_TFIC_SPCR_BITS); 683 ~MASK_RFIC_SPCR_BITS);
684 /* enable FI and RFI interrupts */ 684 /* enable FI and RFI interrupts */
685 pch_spi_setclr_reg(data->master, PCH_SPCR, 685 pch_spi_setclr_reg(data->master, PCH_SPCR,
686 SPCR_RFIE_BIT | SPCR_TFIE_BIT, 0); 686 SPCR_RFIE_BIT | SPCR_FIE_BIT, 0);
687 } else { 687 } else {
688 /* set receive threhold to maximum */ 688 /* set receive threhold to maximum */
689 pch_spi_setclr_reg(data->master, PCH_SPCR, 689 pch_spi_setclr_reg(data->master, PCH_SPCR,