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authorAlexander Shiyan <shc_work@mail.ru>2013-12-21 02:11:39 -0500
committerShawn Guo <shawn.guo@linaro.org>2014-02-09 08:33:32 -0500
commit986cc4920412d8a7b5c9dba85601651f6373f45e (patch)
tree37b110f3db15fa66650923f1c160ebc97092aa5d
parent5e01e58578a6a4e92223dc6cbc993a32a529dd79 (diff)
ARM: dts: imx27-phytec-phycore-som: Add spi-cs-high property to PMIC
Since SPI core does not use GPIO bindings for CS GPIOs, we should add an active high level declaration. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
-rw-r--r--arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi3
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
index 73920a1e7634..230cfafa6bd9 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
@@ -61,8 +61,9 @@
61 #address-cells = <1>; 61 #address-cells = <1>;
62 #size-cells = <0>; 62 #size-cells = <0>;
63 compatible = "fsl,mc13783"; 63 compatible = "fsl,mc13783";
64 spi-max-frequency = <20000000>;
65 reg = <0>; 64 reg = <0>;
65 spi-cs-high;
66 spi-max-frequency = <20000000>;
66 interrupt-parent = <&gpio2>; 67 interrupt-parent = <&gpio2>;
67 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; 68 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
68 fsl,mc13xxx-uses-adc; 69 fsl,mc13xxx-uses-adc;