diff options
author | Kevin Hilman <khilman@linaro.org> | 2013-08-22 11:10:52 -0400 |
---|---|---|
committer | Kevin Hilman <khilman@linaro.org> | 2013-08-22 11:11:41 -0400 |
commit | 8a75f0a07c7aa1e4454c077042ab2b56b72299b9 (patch) | |
tree | 3dc4153b8abb78e324168f46a47d5df99d1b1ec3 | |
parent | 30f9c3bdcec9c810f5bd05b177367c7eeab24d90 (diff) | |
parent | 8c3736e20ee387acefffdfcac560ea23ee6fd4d8 (diff) |
Merge tag 'samsung-cleanup-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/cleanup
From Kukjin Kim:
samsung cleanup for v3.12
- cleanup non-dt stuff in exynos
- remove 0x from exynos dt files
- remove unused codes
* tag 'samsung-cleanup-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: SAMSUNG: Remove unnecessary exynos4_default_sdhci*()
ARM: dts: Remove '0x's from Exynos5440 DTS file
ARM: dts: Remove '0x's from Exynos5420 DTS file
ARM: dts: Remove '0x's from Exynos5250 DTS file
ARM: dts: Remove '0x's from Exynos4x12 DTSI file
ARM: dts: Remove '0x's from Exynos4210 DTSI file
ARM: EXYNOS: Cleanup common.h file
irqchip: exynos: cleanup non-DT stuff in exynos-combiner
Signed-off-by: Kevin Hilman <khilman@linaro.org>
-rw-r--r-- | arch/arm/boot/dts/exynos4210.dtsi | 2 | ||||
-rw-r--r-- | arch/arm/boot/dts/exynos4x12.dtsi | 2 | ||||
-rw-r--r-- | arch/arm/boot/dts/exynos5250.dtsi | 14 | ||||
-rw-r--r-- | arch/arm/boot/dts/exynos5420.dtsi | 2 | ||||
-rw-r--r-- | arch/arm/boot/dts/exynos5440.dtsi | 2 | ||||
-rw-r--r-- | arch/arm/mach-exynos/common.h | 43 | ||||
-rw-r--r-- | arch/arm/plat-samsung/include/plat/sdhci.h | 38 | ||||
-rw-r--r-- | drivers/irqchip/exynos-combiner.c | 44 |
8 files changed, 12 insertions, 135 deletions
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index b7f358a93bcb..53e25273ca74 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi | |||
@@ -72,7 +72,7 @@ | |||
72 | }; | 72 | }; |
73 | }; | 73 | }; |
74 | 74 | ||
75 | clock: clock-controller@0x10030000 { | 75 | clock: clock-controller@10030000 { |
76 | compatible = "samsung,exynos4210-clock"; | 76 | compatible = "samsung,exynos4210-clock"; |
77 | reg = <0x10030000 0x20000>; | 77 | reg = <0x10030000 0x20000>; |
78 | #clock-cells = <1>; | 78 | #clock-cells = <1>; |
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi index 01da194ba329..3aa2f060ba61 100644 --- a/arch/arm/boot/dts/exynos4x12.dtsi +++ b/arch/arm/boot/dts/exynos4x12.dtsi | |||
@@ -28,7 +28,7 @@ | |||
28 | pinctrl3 = &pinctrl_3; | 28 | pinctrl3 = &pinctrl_3; |
29 | }; | 29 | }; |
30 | 30 | ||
31 | clock: clock-controller@0x10030000 { | 31 | clock: clock-controller@10030000 { |
32 | compatible = "samsung,exynos4412-clock"; | 32 | compatible = "samsung,exynos4412-clock"; |
33 | reg = <0x10030000 0x20000>; | 33 | reg = <0x10030000 0x20000>; |
34 | #clock-cells = <1>; | 34 | #clock-cells = <1>; |
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index ef57277fc38f..24c0888dd409 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi | |||
@@ -68,17 +68,17 @@ | |||
68 | }; | 68 | }; |
69 | }; | 69 | }; |
70 | 70 | ||
71 | pd_gsc: gsc-power-domain@0x10044000 { | 71 | pd_gsc: gsc-power-domain@10044000 { |
72 | compatible = "samsung,exynos4210-pd"; | 72 | compatible = "samsung,exynos4210-pd"; |
73 | reg = <0x10044000 0x20>; | 73 | reg = <0x10044000 0x20>; |
74 | }; | 74 | }; |
75 | 75 | ||
76 | pd_mfc: mfc-power-domain@0x10044040 { | 76 | pd_mfc: mfc-power-domain@10044040 { |
77 | compatible = "samsung,exynos4210-pd"; | 77 | compatible = "samsung,exynos4210-pd"; |
78 | reg = <0x10044040 0x20>; | 78 | reg = <0x10044040 0x20>; |
79 | }; | 79 | }; |
80 | 80 | ||
81 | clock: clock-controller@0x10010000 { | 81 | clock: clock-controller@10010000 { |
82 | compatible = "samsung,exynos5250-clock"; | 82 | compatible = "samsung,exynos5250-clock"; |
83 | reg = <0x10010000 0x30000>; | 83 | reg = <0x10010000 0x30000>; |
84 | #clock-cells = <1>; | 84 | #clock-cells = <1>; |
@@ -562,7 +562,7 @@ | |||
562 | }; | 562 | }; |
563 | }; | 563 | }; |
564 | 564 | ||
565 | gsc_0: gsc@0x13e00000 { | 565 | gsc_0: gsc@13e00000 { |
566 | compatible = "samsung,exynos5-gsc"; | 566 | compatible = "samsung,exynos5-gsc"; |
567 | reg = <0x13e00000 0x1000>; | 567 | reg = <0x13e00000 0x1000>; |
568 | interrupts = <0 85 0>; | 568 | interrupts = <0 85 0>; |
@@ -571,7 +571,7 @@ | |||
571 | clock-names = "gscl"; | 571 | clock-names = "gscl"; |
572 | }; | 572 | }; |
573 | 573 | ||
574 | gsc_1: gsc@0x13e10000 { | 574 | gsc_1: gsc@13e10000 { |
575 | compatible = "samsung,exynos5-gsc"; | 575 | compatible = "samsung,exynos5-gsc"; |
576 | reg = <0x13e10000 0x1000>; | 576 | reg = <0x13e10000 0x1000>; |
577 | interrupts = <0 86 0>; | 577 | interrupts = <0 86 0>; |
@@ -580,7 +580,7 @@ | |||
580 | clock-names = "gscl"; | 580 | clock-names = "gscl"; |
581 | }; | 581 | }; |
582 | 582 | ||
583 | gsc_2: gsc@0x13e20000 { | 583 | gsc_2: gsc@13e20000 { |
584 | compatible = "samsung,exynos5-gsc"; | 584 | compatible = "samsung,exynos5-gsc"; |
585 | reg = <0x13e20000 0x1000>; | 585 | reg = <0x13e20000 0x1000>; |
586 | interrupts = <0 87 0>; | 586 | interrupts = <0 87 0>; |
@@ -589,7 +589,7 @@ | |||
589 | clock-names = "gscl"; | 589 | clock-names = "gscl"; |
590 | }; | 590 | }; |
591 | 591 | ||
592 | gsc_3: gsc@0x13e30000 { | 592 | gsc_3: gsc@13e30000 { |
593 | compatible = "samsung,exynos5-gsc"; | 593 | compatible = "samsung,exynos5-gsc"; |
594 | reg = <0x13e30000 0x1000>; | 594 | reg = <0x13e30000 0x1000>; |
595 | interrupts = <0 88 0>; | 595 | interrupts = <0 88 0>; |
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 8c54c4b74f0e..9e90d1ec0c28 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi | |||
@@ -59,7 +59,7 @@ | |||
59 | }; | 59 | }; |
60 | }; | 60 | }; |
61 | 61 | ||
62 | clock: clock-controller@0x10010000 { | 62 | clock: clock-controller@10010000 { |
63 | compatible = "samsung,exynos5420-clock"; | 63 | compatible = "samsung,exynos5420-clock"; |
64 | reg = <0x10010000 0x30000>; | 64 | reg = <0x10010000 0x30000>; |
65 | #clock-cells = <1>; | 65 | #clock-cells = <1>; |
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi index ff7f5d855845..0cedba4d8529 100644 --- a/arch/arm/boot/dts/exynos5440.dtsi +++ b/arch/arm/boot/dts/exynos5440.dtsi | |||
@@ -20,7 +20,7 @@ | |||
20 | spi0 = &spi_0; | 20 | spi0 = &spi_0; |
21 | }; | 21 | }; |
22 | 22 | ||
23 | clock: clock-controller@0x160000 { | 23 | clock: clock-controller@160000 { |
24 | compatible = "samsung,exynos5440-clock"; | 24 | compatible = "samsung,exynos5440-clock"; |
25 | reg = <0x160000 0x1000>; | 25 | reg = <0x160000 0x1000>; |
26 | #clock-cells = <1>; | 26 | #clock-cells = <1>; |
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index 972490fc09d6..8646a141ae46 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h | |||
@@ -17,7 +17,6 @@ | |||
17 | 17 | ||
18 | void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1); | 18 | void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1); |
19 | void exynos_init_time(void); | 19 | void exynos_init_time(void); |
20 | extern unsigned long xxti_f, xusbxti_f; | ||
21 | 20 | ||
22 | struct map_desc; | 21 | struct map_desc; |
23 | void exynos_init_io(void); | 22 | void exynos_init_io(void); |
@@ -25,56 +24,14 @@ void exynos4_restart(enum reboot_mode mode, const char *cmd); | |||
25 | void exynos5_restart(enum reboot_mode mode, const char *cmd); | 24 | void exynos5_restart(enum reboot_mode mode, const char *cmd); |
26 | void exynos_init_late(void); | 25 | void exynos_init_late(void); |
27 | 26 | ||
28 | /* ToDo: remove these after migrating legacy exynos4 platforms to dt */ | ||
29 | void exynos4_clk_init(struct device_node *np, int is_exynos4210, void __iomem *reg_base, unsigned long xom); | ||
30 | void exynos4_clk_register_fixed_ext(unsigned long, unsigned long); | ||
31 | |||
32 | void exynos_firmware_init(void); | 27 | void exynos_firmware_init(void); |
33 | 28 | ||
34 | void exynos_set_timer_source(u8 channels); | ||
35 | |||
36 | #ifdef CONFIG_PM_GENERIC_DOMAINS | 29 | #ifdef CONFIG_PM_GENERIC_DOMAINS |
37 | int exynos_pm_late_initcall(void); | 30 | int exynos_pm_late_initcall(void); |
38 | #else | 31 | #else |
39 | static inline int exynos_pm_late_initcall(void) { return 0; } | 32 | static inline int exynos_pm_late_initcall(void) { return 0; } |
40 | #endif | 33 | #endif |
41 | 34 | ||
42 | #ifdef CONFIG_ARCH_EXYNOS4 | ||
43 | void exynos4_register_clocks(void); | ||
44 | void exynos4_setup_clocks(void); | ||
45 | |||
46 | #else | ||
47 | #define exynos4_register_clocks() | ||
48 | #define exynos4_setup_clocks() | ||
49 | #endif | ||
50 | |||
51 | #ifdef CONFIG_ARCH_EXYNOS5 | ||
52 | void exynos5_register_clocks(void); | ||
53 | void exynos5_setup_clocks(void); | ||
54 | |||
55 | #else | ||
56 | #define exynos5_register_clocks() | ||
57 | #define exynos5_setup_clocks() | ||
58 | #endif | ||
59 | |||
60 | #ifdef CONFIG_CPU_EXYNOS4210 | ||
61 | void exynos4210_register_clocks(void); | ||
62 | |||
63 | #else | ||
64 | #define exynos4210_register_clocks() | ||
65 | #endif | ||
66 | |||
67 | #ifdef CONFIG_SOC_EXYNOS4212 | ||
68 | void exynos4212_register_clocks(void); | ||
69 | |||
70 | #else | ||
71 | #define exynos4212_register_clocks() | ||
72 | #endif | ||
73 | |||
74 | struct device_node; | ||
75 | void combiner_init(void __iomem *combiner_base, struct device_node *np, | ||
76 | unsigned int max_nr, int irq_base); | ||
77 | |||
78 | extern struct smp_operations exynos_smp_ops; | 35 | extern struct smp_operations exynos_smp_ops; |
79 | 36 | ||
80 | extern void exynos_cpu_die(unsigned int cpu); | 37 | extern void exynos_cpu_die(unsigned int cpu); |
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h index ce1d0f785efd..bf650218b40e 100644 --- a/arch/arm/plat-samsung/include/plat/sdhci.h +++ b/arch/arm/plat-samsung/include/plat/sdhci.h | |||
@@ -260,44 +260,6 @@ static inline void s5pv210_default_sdhci3(void) { } | |||
260 | 260 | ||
261 | #endif /* CONFIG_S5PV210_SETUP_SDHCI */ | 261 | #endif /* CONFIG_S5PV210_SETUP_SDHCI */ |
262 | 262 | ||
263 | /* EXYNOS4 SDHCI setup */ | ||
264 | #ifdef CONFIG_EXYNOS4_SETUP_SDHCI | ||
265 | static inline void exynos4_default_sdhci0(void) | ||
266 | { | ||
267 | #ifdef CONFIG_S3C_DEV_HSMMC | ||
268 | s3c_hsmmc0_def_platdata.cfg_gpio = exynos4_setup_sdhci0_cfg_gpio; | ||
269 | #endif | ||
270 | } | ||
271 | |||
272 | static inline void exynos4_default_sdhci1(void) | ||
273 | { | ||
274 | #ifdef CONFIG_S3C_DEV_HSMMC1 | ||
275 | s3c_hsmmc1_def_platdata.cfg_gpio = exynos4_setup_sdhci1_cfg_gpio; | ||
276 | #endif | ||
277 | } | ||
278 | |||
279 | static inline void exynos4_default_sdhci2(void) | ||
280 | { | ||
281 | #ifdef CONFIG_S3C_DEV_HSMMC2 | ||
282 | s3c_hsmmc2_def_platdata.cfg_gpio = exynos4_setup_sdhci2_cfg_gpio; | ||
283 | #endif | ||
284 | } | ||
285 | |||
286 | static inline void exynos4_default_sdhci3(void) | ||
287 | { | ||
288 | #ifdef CONFIG_S3C_DEV_HSMMC3 | ||
289 | s3c_hsmmc3_def_platdata.cfg_gpio = exynos4_setup_sdhci3_cfg_gpio; | ||
290 | #endif | ||
291 | } | ||
292 | |||
293 | #else | ||
294 | static inline void exynos4_default_sdhci0(void) { } | ||
295 | static inline void exynos4_default_sdhci1(void) { } | ||
296 | static inline void exynos4_default_sdhci2(void) { } | ||
297 | static inline void exynos4_default_sdhci3(void) { } | ||
298 | |||
299 | #endif /* CONFIG_EXYNOS4_SETUP_SDHCI */ | ||
300 | |||
301 | static inline void s3c_sdhci_setname(int id, char *name) | 263 | static inline void s3c_sdhci_setname(int id, char *name) |
302 | { | 264 | { |
303 | switch (id) { | 265 | switch (id) { |
diff --git a/drivers/irqchip/exynos-combiner.c b/drivers/irqchip/exynos-combiner.c index 4c6826513901..868ed40cb6bf 100644 --- a/drivers/irqchip/exynos-combiner.c +++ b/drivers/irqchip/exynos-combiner.c | |||
@@ -19,10 +19,6 @@ | |||
19 | #include <linux/of_irq.h> | 19 | #include <linux/of_irq.h> |
20 | #include <asm/mach/irq.h> | 20 | #include <asm/mach/irq.h> |
21 | 21 | ||
22 | #ifdef CONFIG_EXYNOS_ATAGS | ||
23 | #include <plat/cpu.h> | ||
24 | #endif | ||
25 | |||
26 | #include "irqchip.h" | 22 | #include "irqchip.h" |
27 | 23 | ||
28 | #define COMBINER_ENABLE_SET 0x0 | 24 | #define COMBINER_ENABLE_SET 0x0 |
@@ -138,7 +134,6 @@ static void __init combiner_init_one(struct combiner_chip_data *combiner_data, | |||
138 | __raw_writel(combiner_data->irq_mask, base + COMBINER_ENABLE_CLEAR); | 134 | __raw_writel(combiner_data->irq_mask, base + COMBINER_ENABLE_CLEAR); |
139 | } | 135 | } |
140 | 136 | ||
141 | #ifdef CONFIG_OF | ||
142 | static int combiner_irq_domain_xlate(struct irq_domain *d, | 137 | static int combiner_irq_domain_xlate(struct irq_domain *d, |
143 | struct device_node *controller, | 138 | struct device_node *controller, |
144 | const u32 *intspec, unsigned int intsize, | 139 | const u32 *intspec, unsigned int intsize, |
@@ -156,16 +151,6 @@ static int combiner_irq_domain_xlate(struct irq_domain *d, | |||
156 | 151 | ||
157 | return 0; | 152 | return 0; |
158 | } | 153 | } |
159 | #else | ||
160 | static int combiner_irq_domain_xlate(struct irq_domain *d, | ||
161 | struct device_node *controller, | ||
162 | const u32 *intspec, unsigned int intsize, | ||
163 | unsigned long *out_hwirq, | ||
164 | unsigned int *out_type) | ||
165 | { | ||
166 | return -EINVAL; | ||
167 | } | ||
168 | #endif | ||
169 | 154 | ||
170 | static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq, | 155 | static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq, |
171 | irq_hw_number_t hw) | 156 | irq_hw_number_t hw) |
@@ -184,26 +169,6 @@ static struct irq_domain_ops combiner_irq_domain_ops = { | |||
184 | .map = combiner_irq_domain_map, | 169 | .map = combiner_irq_domain_map, |
185 | }; | 170 | }; |
186 | 171 | ||
187 | static unsigned int combiner_lookup_irq(int group) | ||
188 | { | ||
189 | #ifdef CONFIG_EXYNOS_ATAGS | ||
190 | if (group < EXYNOS4210_MAX_COMBINER_NR || soc_is_exynos5250()) | ||
191 | return IRQ_SPI(group); | ||
192 | |||
193 | switch (group) { | ||
194 | case 16: | ||
195 | return IRQ_SPI(107); | ||
196 | case 17: | ||
197 | return IRQ_SPI(108); | ||
198 | case 18: | ||
199 | return IRQ_SPI(48); | ||
200 | case 19: | ||
201 | return IRQ_SPI(42); | ||
202 | } | ||
203 | #endif | ||
204 | return 0; | ||
205 | } | ||
206 | |||
207 | static void __init combiner_init(void __iomem *combiner_base, | 172 | static void __init combiner_init(void __iomem *combiner_base, |
208 | struct device_node *np, | 173 | struct device_node *np, |
209 | unsigned int max_nr, | 174 | unsigned int max_nr, |
@@ -229,12 +194,7 @@ static void __init combiner_init(void __iomem *combiner_base, | |||
229 | } | 194 | } |
230 | 195 | ||
231 | for (i = 0; i < max_nr; i++) { | 196 | for (i = 0; i < max_nr; i++) { |
232 | #ifdef CONFIG_OF | 197 | irq = irq_of_parse_and_map(np, i); |
233 | if (np) | ||
234 | irq = irq_of_parse_and_map(np, i); | ||
235 | else | ||
236 | #endif | ||
237 | irq = combiner_lookup_irq(i); | ||
238 | 198 | ||
239 | combiner_init_one(&combiner_data[i], i, | 199 | combiner_init_one(&combiner_data[i], i, |
240 | combiner_base + (i >> 2) * 0x10, irq); | 200 | combiner_base + (i >> 2) * 0x10, irq); |
@@ -242,7 +202,6 @@ static void __init combiner_init(void __iomem *combiner_base, | |||
242 | } | 202 | } |
243 | } | 203 | } |
244 | 204 | ||
245 | #ifdef CONFIG_OF | ||
246 | static int __init combiner_of_init(struct device_node *np, | 205 | static int __init combiner_of_init(struct device_node *np, |
247 | struct device_node *parent) | 206 | struct device_node *parent) |
248 | { | 207 | { |
@@ -275,4 +234,3 @@ static int __init combiner_of_init(struct device_node *np, | |||
275 | } | 234 | } |
276 | IRQCHIP_DECLARE(exynos4210_combiner, "samsung,exynos4210-combiner", | 235 | IRQCHIP_DECLARE(exynos4210_combiner, "samsung,exynos4210-combiner", |
277 | combiner_of_init); | 236 | combiner_of_init); |
278 | #endif | ||