diff options
author | Borislav Petkov <borislav.petkov@amd.com> | 2010-01-22 10:01:06 -0500 |
---|---|---|
committer | H. Peter Anvin <hpa@zytor.com> | 2010-01-22 19:06:31 -0500 |
commit | 897de50e08937663912c86fb12ad7f708af2386c (patch) | |
tree | e38af91f2e48bec90246b2976a391c4aad07dd9b | |
parent | dcf39daf3d6d97f8741e82f0b9fb7554704ed2d1 (diff) |
x86, cacheinfo: Add cache index disable sysfs attrs only to L3 caches
The cache_disable_[01] attribute in
/sys/devices/system/cpu/cpu?/cache/index[0-3]/
is enabled on all cache levels although only L3 supports it. Add it only
to the cache level that actually supports it.
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
LKML-Reference: <1264172467-25155-5-git-send-email-bp@amd64.org>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
-rw-r--r-- | arch/x86/kernel/cpu/intel_cacheinfo.c | 35 |
1 files changed, 26 insertions, 9 deletions
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c index 08c91abc4d32..3976ce95095f 100644 --- a/arch/x86/kernel/cpu/intel_cacheinfo.c +++ b/arch/x86/kernel/cpu/intel_cacheinfo.c | |||
@@ -814,16 +814,24 @@ static struct _cache_attr cache_disable_0 = __ATTR(cache_disable_0, 0644, | |||
814 | static struct _cache_attr cache_disable_1 = __ATTR(cache_disable_1, 0644, | 814 | static struct _cache_attr cache_disable_1 = __ATTR(cache_disable_1, 0644, |
815 | show_cache_disable_1, store_cache_disable_1); | 815 | show_cache_disable_1, store_cache_disable_1); |
816 | 816 | ||
817 | #define DEFAULT_SYSFS_CACHE_ATTRS \ | ||
818 | &type.attr, \ | ||
819 | &level.attr, \ | ||
820 | &coherency_line_size.attr, \ | ||
821 | &physical_line_partition.attr, \ | ||
822 | &ways_of_associativity.attr, \ | ||
823 | &number_of_sets.attr, \ | ||
824 | &size.attr, \ | ||
825 | &shared_cpu_map.attr, \ | ||
826 | &shared_cpu_list.attr | ||
827 | |||
817 | static struct attribute *default_attrs[] = { | 828 | static struct attribute *default_attrs[] = { |
818 | &type.attr, | 829 | DEFAULT_SYSFS_CACHE_ATTRS, |
819 | &level.attr, | 830 | NULL |
820 | &coherency_line_size.attr, | 831 | }; |
821 | &physical_line_partition.attr, | 832 | |
822 | &ways_of_associativity.attr, | 833 | static struct attribute *default_l3_attrs[] = { |
823 | &number_of_sets.attr, | 834 | DEFAULT_SYSFS_CACHE_ATTRS, |
824 | &size.attr, | ||
825 | &shared_cpu_map.attr, | ||
826 | &shared_cpu_list.attr, | ||
827 | &cache_disable_0.attr, | 835 | &cache_disable_0.attr, |
828 | &cache_disable_1.attr, | 836 | &cache_disable_1.attr, |
829 | NULL | 837 | NULL |
@@ -916,6 +924,7 @@ static int __cpuinit cache_add_dev(struct sys_device * sys_dev) | |||
916 | unsigned int cpu = sys_dev->id; | 924 | unsigned int cpu = sys_dev->id; |
917 | unsigned long i, j; | 925 | unsigned long i, j; |
918 | struct _index_kobject *this_object; | 926 | struct _index_kobject *this_object; |
927 | struct _cpuid4_info *this_leaf; | ||
919 | int retval; | 928 | int retval; |
920 | 929 | ||
921 | retval = cpuid4_cache_sysfs_init(cpu); | 930 | retval = cpuid4_cache_sysfs_init(cpu); |
@@ -934,6 +943,14 @@ static int __cpuinit cache_add_dev(struct sys_device * sys_dev) | |||
934 | this_object = INDEX_KOBJECT_PTR(cpu, i); | 943 | this_object = INDEX_KOBJECT_PTR(cpu, i); |
935 | this_object->cpu = cpu; | 944 | this_object->cpu = cpu; |
936 | this_object->index = i; | 945 | this_object->index = i; |
946 | |||
947 | this_leaf = CPUID4_INFO_IDX(cpu, i); | ||
948 | |||
949 | if (this_leaf->can_disable) | ||
950 | ktype_cache.default_attrs = default_l3_attrs; | ||
951 | else | ||
952 | ktype_cache.default_attrs = default_attrs; | ||
953 | |||
937 | retval = kobject_init_and_add(&(this_object->kobj), | 954 | retval = kobject_init_and_add(&(this_object->kobj), |
938 | &ktype_cache, | 955 | &ktype_cache, |
939 | per_cpu(ici_cache_kobject, cpu), | 956 | per_cpu(ici_cache_kobject, cpu), |