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authorLinus Torvalds <torvalds@linux-foundation.org>2014-10-26 14:35:51 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2014-10-26 14:35:51 -0400
commit88e237610b426897f0e9935adb6a60bd38bfe6c6 (patch)
treee14c47586af20c1edeb46f8cab93a08dc6747995
parentd1e14f1d63eb15ebe97d1a8544ddc143486b0204 (diff)
parentefc176a8ee1f959b89292597bd8a99417475a79a (diff)
Merge tag 'armsoc-for-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson: "Another week, another small batch of fixes. Most of these make zynq, socfpga and sunxi platforms work a bit better: - due to new requirements for regulators, DWMMC on socfpga broke past v3.17 - SMP spinup fix for socfpga - a few DT fixes for zynq - another option (FIXED_REGULATOR) for sunxi is needed that used to be selected by other options but no longer is. - a couple of small DT fixes for at91 - ...and a couple for i.MX" * tag 'armsoc-for-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: ARM: dts: imx28-evk: Let i2c0 run at 100kHz ARM: i.MX6: Fix "emi" clock name typo ARM: multi_v7_defconfig: enable CONFIG_MMC_DW_ROCKCHIP ARM: sunxi_defconfig: enable CONFIG_REGULATOR_FIXED_VOLTAGE ARM: dts: socfpga: Add a 3.3V fixed regulator node ARM: dts: socfpga: Fix SD card detect ARM: dts: socfpga: rename gpio nodes ARM: at91/dt: sam9263: fix PLLB frequencies power: reset: at91-reset: fix power down register MAINTAINERS: add atmel ssc driver maintainer entry arm: socfpga: fix fetching cpu1start_addr for SMP ARM: zynq: DT: trivial: Fix mc node ARM: zynq: DT: Add cadence watchdog node ARM: zynq: DT: Add missing reference for memory-controller ARM: zynq: DT: Add missing reference for ADC ARM: zynq: DT: Add missing address for L2 pl310 ARM: zynq: DT: Remove 222 MHz OPP ARM: zynq: DT: Fix GEM register area size
Diffstat
-rw-r--r--MAINTAINERS7
-rw-r--r--arch/arm/boot/dts/at91sam9263.dtsi5
-rw-r--r--arch/arm/boot/dts/imx28-evk.dts1
-rw-r--r--arch/arm/boot/dts/socfpga.dtsi12
-rw-r--r--arch/arm/boot/dts/socfpga_arria5.dtsi2
-rw-r--r--arch/arm/boot/dts/socfpga_arria5_socdk.dts12
-rw-r--r--arch/arm/boot/dts/socfpga_cyclone5_socdk.dts15
-rw-r--r--arch/arm/boot/dts/socfpga_cyclone5_sockit.dts12
-rw-r--r--arch/arm/boot/dts/zynq-7000.dtsi24
-rw-r--r--arch/arm/configs/multi_v7_defconfig1
-rw-r--r--arch/arm/configs/sunxi_defconfig1
-rw-r--r--arch/arm/mach-imx/clk-imx6q.c14
-rw-r--r--arch/arm/mach-socfpga/core.h2
-rw-r--r--arch/arm/mach-socfpga/headsmp.S25
-rw-r--r--arch/arm/mach-socfpga/platsmp.c4
-rw-r--r--arch/arm/mach-socfpga/socfpga.c4
-rw-r--r--drivers/power/reset/at91-reset.c4
-rw-r--r--include/dt-bindings/clock/imx6qdl-clock.h8
18 files changed, 107 insertions, 46 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index ec25b0e1e745..dab92a78d1d5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1749,6 +1749,13 @@ M: Nicolas Ferre <nicolas.ferre@atmel.com>
1749S: Supported 1749S: Supported
1750F: drivers/spi/spi-atmel.* 1750F: drivers/spi/spi-atmel.*
1751 1751
1752ATMEL SSC DRIVER
1753M: Bo Shen <voice.shen@atmel.com>
1754L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
1755S: Supported
1756F: drivers/misc/atmel-ssc.c
1757F: include/linux/atmel-ssc.h
1758
1752ATMEL Timer Counter (TC) AND CLOCKSOURCE DRIVERS 1759ATMEL Timer Counter (TC) AND CLOCKSOURCE DRIVERS
1753M: Nicolas Ferre <nicolas.ferre@atmel.com> 1760M: Nicolas Ferre <nicolas.ferre@atmel.com>
1754L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 1761L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index d68b3c4862bc..51416c7d0625 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -122,9 +122,10 @@
122 interrupts-extended = <&pmc AT91_PMC_LOCKB>; 122 interrupts-extended = <&pmc AT91_PMC_LOCKB>;
123 clocks = <&main>; 123 clocks = <&main>;
124 reg = <1>; 124 reg = <1>;
125 atmel,clk-input-range = <1000000 5000000>; 125 atmel,clk-input-range = <1000000 32000000>;
126 #atmel,pll-clk-output-range-cells = <4>; 126 #atmel,pll-clk-output-range-cells = <4>;
127 atmel,pll-clk-output-ranges = <70000000 130000000 1 1>; 127 atmel,pll-clk-output-ranges = <80000000 200000000 0 1>,
128 <190000000 240000000 2 1>;
128 }; 129 };
129 130
130 mck: masterck { 131 mck: masterck {
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
index 09664fcf5afb..0e13b4b10a92 100644
--- a/arch/arm/boot/dts/imx28-evk.dts
+++ b/arch/arm/boot/dts/imx28-evk.dts
@@ -193,7 +193,6 @@
193 i2c0: i2c@80058000 { 193 i2c0: i2c@80058000 {
194 pinctrl-names = "default"; 194 pinctrl-names = "default";
195 pinctrl-0 = <&i2c0_pins_a>; 195 pinctrl-0 = <&i2c0_pins_a>;
196 clock-frequency = <400000>;
197 status = "okay"; 196 status = "okay";
198 197
199 sgtl5000: codec@0a { 198 sgtl5000: codec@0a {
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 45fce2cf6fed..4472fd92685c 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -547,7 +547,7 @@
547 status = "disabled"; 547 status = "disabled";
548 }; 548 };
549 549
550 gpio@ff708000 { 550 gpio0: gpio@ff708000 {
551 #address-cells = <1>; 551 #address-cells = <1>;
552 #size-cells = <0>; 552 #size-cells = <0>;
553 compatible = "snps,dw-apb-gpio"; 553 compatible = "snps,dw-apb-gpio";
@@ -555,7 +555,7 @@
555 clocks = <&per_base_clk>; 555 clocks = <&per_base_clk>;
556 status = "disabled"; 556 status = "disabled";
557 557
558 gpio0: gpio-controller@0 { 558 porta: gpio-controller@0 {
559 compatible = "snps,dw-apb-gpio-port"; 559 compatible = "snps,dw-apb-gpio-port";
560 gpio-controller; 560 gpio-controller;
561 #gpio-cells = <2>; 561 #gpio-cells = <2>;
@@ -567,7 +567,7 @@
567 }; 567 };
568 }; 568 };
569 569
570 gpio@ff709000 { 570 gpio1: gpio@ff709000 {
571 #address-cells = <1>; 571 #address-cells = <1>;
572 #size-cells = <0>; 572 #size-cells = <0>;
573 compatible = "snps,dw-apb-gpio"; 573 compatible = "snps,dw-apb-gpio";
@@ -575,7 +575,7 @@
575 clocks = <&per_base_clk>; 575 clocks = <&per_base_clk>;
576 status = "disabled"; 576 status = "disabled";
577 577
578 gpio1: gpio-controller@0 { 578 portb: gpio-controller@0 {
579 compatible = "snps,dw-apb-gpio-port"; 579 compatible = "snps,dw-apb-gpio-port";
580 gpio-controller; 580 gpio-controller;
581 #gpio-cells = <2>; 581 #gpio-cells = <2>;
@@ -587,7 +587,7 @@
587 }; 587 };
588 }; 588 };
589 589
590 gpio@ff70a000 { 590 gpio2: gpio@ff70a000 {
591 #address-cells = <1>; 591 #address-cells = <1>;
592 #size-cells = <0>; 592 #size-cells = <0>;
593 compatible = "snps,dw-apb-gpio"; 593 compatible = "snps,dw-apb-gpio";
@@ -595,7 +595,7 @@
595 clocks = <&per_base_clk>; 595 clocks = <&per_base_clk>;
596 status = "disabled"; 596 status = "disabled";
597 597
598 gpio2: gpio-controller@0 { 598 portc: gpio-controller@0 {
599 compatible = "snps,dw-apb-gpio-port"; 599 compatible = "snps,dw-apb-gpio-port";
600 gpio-controller; 600 gpio-controller;
601 #gpio-cells = <2>; 601 #gpio-cells = <2>;
diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi
index 03e8268ae219..1907cc600452 100644
--- a/arch/arm/boot/dts/socfpga_arria5.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria5.dtsi
@@ -29,7 +29,7 @@
29 }; 29 };
30 }; 30 };
31 31
32 dwmmc0@ff704000 { 32 mmc0: dwmmc0@ff704000 {
33 num-slots = <1>; 33 num-slots = <1>;
34 broken-cd; 34 broken-cd;
35 bus-width = <4>; 35 bus-width = <4>;
diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
index 27d551c384d0..ccaf41742fc3 100644
--- a/arch/arm/boot/dts/socfpga_arria5_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
@@ -37,6 +37,13 @@
37 */ 37 */
38 ethernet0 = &gmac1; 38 ethernet0 = &gmac1;
39 }; 39 };
40
41 regulator_3_3v: 3-3-v-regulator {
42 compatible = "regulator-fixed";
43 regulator-name = "3.3V";
44 regulator-min-microvolt = <3300000>;
45 regulator-max-microvolt = <3300000>;
46 };
40}; 47};
41 48
42&gmac1 { 49&gmac1 {
@@ -68,6 +75,11 @@
68 }; 75 };
69}; 76};
70 77
78&mmc0 {
79 vmmc-supply = <&regulator_3_3v>;
80 vqmmc-supply = <&regulator_3_3v>;
81};
82
71&usb1 { 83&usb1 {
72 status = "okay"; 84 status = "okay";
73}; 85};
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
index d7296a5f750c..258865da8f6a 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
@@ -37,6 +37,13 @@
37 */ 37 */
38 ethernet0 = &gmac1; 38 ethernet0 = &gmac1;
39 }; 39 };
40
41 regulator_3_3v: 3-3-v-regulator {
42 compatible = "regulator-fixed";
43 regulator-name = "3.3V";
44 regulator-min-microvolt = <3300000>;
45 regulator-max-microvolt = <3300000>;
46 };
40}; 47};
41 48
42&gmac1 { 49&gmac1 {
@@ -53,6 +60,10 @@
53 rxc-skew-ps = <2000>; 60 rxc-skew-ps = <2000>;
54}; 61};
55 62
63&gpio1 {
64 status = "okay";
65};
66
56&i2c0 { 67&i2c0 {
57 status = "okay"; 68 status = "okay";
58 69
@@ -69,7 +80,9 @@
69}; 80};
70 81
71&mmc0 { 82&mmc0 {
72 cd-gpios = <&gpio1 18 0>; 83 cd-gpios = <&portb 18 0>;
84 vmmc-supply = <&regulator_3_3v>;
85 vqmmc-supply = <&regulator_3_3v>;
73}; 86};
74 87
75&usb1 { 88&usb1 {
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
index d26f155f5fd9..16ea6f5f2ab8 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
@@ -37,6 +37,13 @@
37 */ 37 */
38 ethernet0 = &gmac1; 38 ethernet0 = &gmac1;
39 }; 39 };
40
41 regulator_3_3v: vcc3p3-regulator {
42 compatible = "regulator-fixed";
43 regulator-name = "VCC3P3";
44 regulator-min-microvolt = <3300000>;
45 regulator-max-microvolt = <3300000>;
46 };
40}; 47};
41 48
42&gmac1 { 49&gmac1 {
@@ -53,6 +60,11 @@
53 rxc-skew-ps = <2000>; 60 rxc-skew-ps = <2000>;
54}; 61};
55 62
63&mmc0 {
64 vmmc-supply = <&regulator_3_3v>;
65 vqmmc-supply = <&regulator_3_3v>;
66};
67
56&usb1 { 68&usb1 {
57 status = "okay"; 69 status = "okay";
58}; 70};
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 24036c440440..ce2ef5bec4f2 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -30,7 +30,6 @@
30 /* kHz uV */ 30 /* kHz uV */
31 666667 1000000 31 666667 1000000
32 333334 1000000 32 333334 1000000
33 222223 1000000
34 >; 33 >;
35 }; 34 };
36 35
@@ -65,7 +64,7 @@
65 interrupt-parent = <&intc>; 64 interrupt-parent = <&intc>;
66 ranges; 65 ranges;
67 66
68 adc@f8007100 { 67 adc: adc@f8007100 {
69 compatible = "xlnx,zynq-xadc-1.00.a"; 68 compatible = "xlnx,zynq-xadc-1.00.a";
70 reg = <0xf8007100 0x20>; 69 reg = <0xf8007100 0x20>;
71 interrupts = <0 7 4>; 70 interrupts = <0 7 4>;
@@ -137,7 +136,7 @@
137 <0xF8F00100 0x100>; 136 <0xF8F00100 0x100>;
138 }; 137 };
139 138
140 L2: cache-controller { 139 L2: cache-controller@f8f02000 {
141 compatible = "arm,pl310-cache"; 140 compatible = "arm,pl310-cache";
142 reg = <0xF8F02000 0x1000>; 141 reg = <0xF8F02000 0x1000>;
143 arm,data-latency = <3 2 2>; 142 arm,data-latency = <3 2 2>;
@@ -146,10 +145,10 @@
146 cache-level = <2>; 145 cache-level = <2>;
147 }; 146 };
148 147
149 memory-controller@f8006000 { 148 mc: memory-controller@f8006000 {
150 compatible = "xlnx,zynq-ddrc-a05"; 149 compatible = "xlnx,zynq-ddrc-a05";
151 reg = <0xf8006000 0x1000>; 150 reg = <0xf8006000 0x1000>;
152 } ; 151 };
153 152
154 uart0: serial@e0000000 { 153 uart0: serial@e0000000 {
155 compatible = "xlnx,xuartps", "cdns,uart-r1p8"; 154 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
@@ -195,7 +194,7 @@
195 194
196 gem0: ethernet@e000b000 { 195 gem0: ethernet@e000b000 {
197 compatible = "cdns,gem"; 196 compatible = "cdns,gem";
198 reg = <0xe000b000 0x4000>; 197 reg = <0xe000b000 0x1000>;
199 status = "disabled"; 198 status = "disabled";
200 interrupts = <0 22 4>; 199 interrupts = <0 22 4>;
201 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; 200 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
@@ -206,7 +205,7 @@
206 205
207 gem1: ethernet@e000c000 { 206 gem1: ethernet@e000c000 {
208 compatible = "cdns,gem"; 207 compatible = "cdns,gem";
209 reg = <0xe000c000 0x4000>; 208 reg = <0xe000c000 0x1000>;
210 status = "disabled"; 209 status = "disabled";
211 interrupts = <0 45 4>; 210 interrupts = <0 45 4>;
212 clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; 211 clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
@@ -315,5 +314,16 @@
315 reg = <0xf8f00600 0x20>; 314 reg = <0xf8f00600 0x20>;
316 clocks = <&clkc 4>; 315 clocks = <&clkc 4>;
317 }; 316 };
317
318 watchdog0: watchdog@f8005000 {
319 clocks = <&clkc 45>;
320 compatible = "xlnx,zynq-wdt-r1p2";
321 device_type = "watchdog";
322 interrupt-parent = <&intc>;
323 interrupts = <0 9 1>;
324 reg = <0xf8005000 0x1000>;
325 reset = <0>;
326 timeout-sec = <10>;
327 };
318 }; 328 };
319}; 329};
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 9702b140ae04..f1dc7fc668f3 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -354,6 +354,7 @@ CONFIG_MMC_MVSDIO=y
354CONFIG_MMC_SUNXI=y 354CONFIG_MMC_SUNXI=y
355CONFIG_MMC_DW=y 355CONFIG_MMC_DW=y
356CONFIG_MMC_DW_EXYNOS=y 356CONFIG_MMC_DW_EXYNOS=y
357CONFIG_MMC_DW_ROCKCHIP=y
357CONFIG_NEW_LEDS=y 358CONFIG_NEW_LEDS=y
358CONFIG_LEDS_CLASS=y 359CONFIG_LEDS_CLASS=y
359CONFIG_LEDS_GPIO=y 360CONFIG_LEDS_GPIO=y
diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig
index 847045313101..f7ac0379850f 100644
--- a/arch/arm/configs/sunxi_defconfig
+++ b/arch/arm/configs/sunxi_defconfig
@@ -76,6 +76,7 @@ CONFIG_WATCHDOG=y
76CONFIG_SUNXI_WATCHDOG=y 76CONFIG_SUNXI_WATCHDOG=y
77CONFIG_MFD_AXP20X=y 77CONFIG_MFD_AXP20X=y
78CONFIG_REGULATOR=y 78CONFIG_REGULATOR=y
79CONFIG_REGULATOR_FIXED_VOLTAGE=y
79CONFIG_REGULATOR_GPIO=y 80CONFIG_REGULATOR_GPIO=y
80CONFIG_USB=y 81CONFIG_USB=y
81CONFIG_USB_EHCI_HCD=y 82CONFIG_USB_EHCI_HCD=y
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 1412daf4a714..4e79da7c5e30 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -50,8 +50,8 @@ static const char *pcie_axi_sels[] = { "axi", "ahb", };
50static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio_div", }; 50static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio_div", };
51static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", }; 51static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
52static const char *enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", }; 52static const char *enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", };
53static const char *emi_sels[] = { "pll2_pfd2_396m", "pll3_usb_otg", "axi", "pll2_pfd0_352m", }; 53static const char *eim_sels[] = { "pll2_pfd2_396m", "pll3_usb_otg", "axi", "pll2_pfd0_352m", };
54static const char *emi_slow_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", }; 54static const char *eim_slow_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", };
55static const char *vdo_axi_sels[] = { "axi", "ahb", }; 55static const char *vdo_axi_sels[] = { "axi", "ahb", };
56static const char *vpu_axi_sels[] = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", }; 56static const char *vpu_axi_sels[] = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", };
57static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div", 57static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div",
@@ -302,8 +302,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
302 clk[IMX6QDL_CLK_USDHC3_SEL] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); 302 clk[IMX6QDL_CLK_USDHC3_SEL] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
303 clk[IMX6QDL_CLK_USDHC4_SEL] = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); 303 clk[IMX6QDL_CLK_USDHC4_SEL] = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
304 clk[IMX6QDL_CLK_ENFC_SEL] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels)); 304 clk[IMX6QDL_CLK_ENFC_SEL] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels));
305 clk[IMX6QDL_CLK_EMI_SEL] = imx_clk_fixup_mux("emi_sel", base + 0x1c, 27, 2, emi_sels, ARRAY_SIZE(emi_sels), imx_cscmr1_fixup); 305 clk[IMX6QDL_CLK_EIM_SEL] = imx_clk_fixup_mux("eim_sel", base + 0x1c, 27, 2, eim_sels, ARRAY_SIZE(eim_sels), imx_cscmr1_fixup);
306 clk[IMX6QDL_CLK_EMI_SLOW_SEL] = imx_clk_fixup_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_slow_sels, ARRAY_SIZE(emi_slow_sels), imx_cscmr1_fixup); 306 clk[IMX6QDL_CLK_EIM_SLOW_SEL] = imx_clk_fixup_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels, ARRAY_SIZE(eim_slow_sels), imx_cscmr1_fixup);
307 clk[IMX6QDL_CLK_VDO_AXI_SEL] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels)); 307 clk[IMX6QDL_CLK_VDO_AXI_SEL] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels));
308 clk[IMX6QDL_CLK_VPU_AXI_SEL] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels)); 308 clk[IMX6QDL_CLK_VPU_AXI_SEL] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels));
309 clk[IMX6QDL_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels)); 309 clk[IMX6QDL_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels));
@@ -354,8 +354,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
354 clk[IMX6QDL_CLK_USDHC4_PODF] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3); 354 clk[IMX6QDL_CLK_USDHC4_PODF] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3);
355 clk[IMX6QDL_CLK_ENFC_PRED] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3); 355 clk[IMX6QDL_CLK_ENFC_PRED] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3);
356 clk[IMX6QDL_CLK_ENFC_PODF] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6); 356 clk[IMX6QDL_CLK_ENFC_PODF] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6);
357 clk[IMX6QDL_CLK_EMI_PODF] = imx_clk_fixup_divider("emi_podf", "emi_sel", base + 0x1c, 20, 3, imx_cscmr1_fixup); 357 clk[IMX6QDL_CLK_EIM_PODF] = imx_clk_fixup_divider("eim_podf", "eim_sel", base + 0x1c, 20, 3, imx_cscmr1_fixup);
358 clk[IMX6QDL_CLK_EMI_SLOW_PODF] = imx_clk_fixup_divider("emi_slow_podf", "emi_slow_sel", base + 0x1c, 23, 3, imx_cscmr1_fixup); 358 clk[IMX6QDL_CLK_EIM_SLOW_PODF] = imx_clk_fixup_divider("eim_slow_podf", "eim_slow_sel", base + 0x1c, 23, 3, imx_cscmr1_fixup);
359 clk[IMX6QDL_CLK_VPU_AXI_PODF] = imx_clk_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3); 359 clk[IMX6QDL_CLK_VPU_AXI_PODF] = imx_clk_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3);
360 clk[IMX6QDL_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3); 360 clk[IMX6QDL_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3);
361 clk[IMX6QDL_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3); 361 clk[IMX6QDL_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3);
@@ -456,7 +456,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
456 clk[IMX6QDL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4); 456 clk[IMX6QDL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
457 clk[IMX6QDL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6); 457 clk[IMX6QDL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
458 clk[IMX6QDL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8); 458 clk[IMX6QDL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
459 clk[IMX6QDL_CLK_EIM_SLOW] = imx_clk_gate2("eim_slow", "emi_slow_podf", base + 0x80, 10); 459 clk[IMX6QDL_CLK_EIM_SLOW] = imx_clk_gate2("eim_slow", "eim_slow_podf", base + 0x80, 10);
460 clk[IMX6QDL_CLK_VDO_AXI] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12); 460 clk[IMX6QDL_CLK_VDO_AXI] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12);
461 clk[IMX6QDL_CLK_VPU_AXI] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14); 461 clk[IMX6QDL_CLK_VPU_AXI] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14);
462 clk[IMX6QDL_CLK_CKO1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7); 462 clk[IMX6QDL_CLK_CKO1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7);
diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h
index 572b8f719ffb..60c443dadb58 100644
--- a/arch/arm/mach-socfpga/core.h
+++ b/arch/arm/mach-socfpga/core.h
@@ -40,7 +40,7 @@ extern void __iomem *rst_manager_base_addr;
40extern struct smp_operations socfpga_smp_ops; 40extern struct smp_operations socfpga_smp_ops;
41extern char secondary_trampoline, secondary_trampoline_end; 41extern char secondary_trampoline, secondary_trampoline_end;
42 42
43extern unsigned long cpu1start_addr; 43extern unsigned long socfpga_cpu1start_addr;
44 44
45#define SOCFPGA_SCU_VIRT_BASE 0xfffec000 45#define SOCFPGA_SCU_VIRT_BASE 0xfffec000
46 46
diff --git a/arch/arm/mach-socfpga/headsmp.S b/arch/arm/mach-socfpga/headsmp.S
index 95c115d8b5ee..f65ea0af4af3 100644
--- a/arch/arm/mach-socfpga/headsmp.S
+++ b/arch/arm/mach-socfpga/headsmp.S
@@ -9,21 +9,26 @@
9 */ 9 */
10#include <linux/linkage.h> 10#include <linux/linkage.h>
11#include <linux/init.h> 11#include <linux/init.h>
12#include <asm/memory.h>
12 13
13 .arch armv7-a 14 .arch armv7-a
14 15
15ENTRY(secondary_trampoline) 16ENTRY(secondary_trampoline)
16 movw r2, #:lower16:cpu1start_addr 17 /* CPU1 will always fetch from 0x0 when it is brought out of reset.
17 movt r2, #:upper16:cpu1start_addr 18 * Thus, we can just subtract the PAGE_OFFSET to get the physical
18 19 * address of &cpu1start_addr. This would not work for platforms
19 /* The socfpga VT cannot handle a 0xC0000000 page offset when loading 20 * where the physical memory does not start at 0x0.
20 the cpu1start_addr, we bit clear it. Tested on HW and VT. */ 21 */
21 bic r2, r2, #0x40000000 22 adr r0, 1f
22 23 ldmia r0, {r1, r2}
23 ldr r0, [r2] 24 sub r2, r2, #PAGE_OFFSET
24 ldr r1, [r0] 25 ldr r3, [r2]
25 bx r1 26 ldr r4, [r3]
27 bx r4
26 28
29 .align
301: .long .
31 .long socfpga_cpu1start_addr
27ENTRY(secondary_trampoline_end) 32ENTRY(secondary_trampoline_end)
28 33
29ENTRY(socfpga_secondary_startup) 34ENTRY(socfpga_secondary_startup)
diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c
index 5356a72bc8ce..16ca97b039f9 100644
--- a/arch/arm/mach-socfpga/platsmp.c
+++ b/arch/arm/mach-socfpga/platsmp.c
@@ -33,11 +33,11 @@ static int socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
33{ 33{
34 int trampoline_size = &secondary_trampoline_end - &secondary_trampoline; 34 int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;
35 35
36 if (cpu1start_addr) { 36 if (socfpga_cpu1start_addr) {
37 memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size); 37 memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
38 38
39 __raw_writel(virt_to_phys(socfpga_secondary_startup), 39 __raw_writel(virt_to_phys(socfpga_secondary_startup),
40 (sys_manager_base_addr + (cpu1start_addr & 0x000000ff))); 40 (sys_manager_base_addr + (socfpga_cpu1start_addr & 0x000000ff)));
41 41
42 flush_cache_all(); 42 flush_cache_all();
43 smp_wmb(); 43 smp_wmb();
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index adbf38314ca8..383d61e138af 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -29,7 +29,7 @@
29void __iomem *socfpga_scu_base_addr = ((void __iomem *)(SOCFPGA_SCU_VIRT_BASE)); 29void __iomem *socfpga_scu_base_addr = ((void __iomem *)(SOCFPGA_SCU_VIRT_BASE));
30void __iomem *sys_manager_base_addr; 30void __iomem *sys_manager_base_addr;
31void __iomem *rst_manager_base_addr; 31void __iomem *rst_manager_base_addr;
32unsigned long cpu1start_addr; 32unsigned long socfpga_cpu1start_addr;
33 33
34static struct map_desc scu_io_desc __initdata = { 34static struct map_desc scu_io_desc __initdata = {
35 .virtual = SOCFPGA_SCU_VIRT_BASE, 35 .virtual = SOCFPGA_SCU_VIRT_BASE,
@@ -70,7 +70,7 @@ void __init socfpga_sysmgr_init(void)
70 np = of_find_compatible_node(NULL, NULL, "altr,sys-mgr"); 70 np = of_find_compatible_node(NULL, NULL, "altr,sys-mgr");
71 71
72 if (of_property_read_u32(np, "cpu1-start-addr", 72 if (of_property_read_u32(np, "cpu1-start-addr",
73 (u32 *) &cpu1start_addr)) 73 (u32 *) &socfpga_cpu1start_addr))
74 pr_err("SMP: Need cpu1-start-addr in device tree.\n"); 74 pr_err("SMP: Need cpu1-start-addr in device tree.\n");
75 75
76 sys_manager_base_addr = of_iomap(np, 0); 76 sys_manager_base_addr = of_iomap(np, 0);
diff --git a/drivers/power/reset/at91-reset.c b/drivers/power/reset/at91-reset.c
index 3611806c9cfd..3cb36693343a 100644
--- a/drivers/power/reset/at91-reset.c
+++ b/drivers/power/reset/at91-reset.c
@@ -100,11 +100,11 @@ static void at91sam9g45_restart(enum reboot_mode mode, const char *cmd)
100 /* Disable SDRAM0 accesses */ 100 /* Disable SDRAM0 accesses */
101 "1: str %3, [%0, #" __stringify(AT91_DDRSDRC_RTR) "]\n\t" 101 "1: str %3, [%0, #" __stringify(AT91_DDRSDRC_RTR) "]\n\t"
102 /* Power down SDRAM0 */ 102 /* Power down SDRAM0 */
103 " str %4, [%0, #" __stringify(AT91_DDRSDRC_RTR) "]\n\t" 103 " str %4, [%0, #" __stringify(AT91_DDRSDRC_LPR) "]\n\t"
104 /* Disable SDRAM1 accesses */ 104 /* Disable SDRAM1 accesses */
105 " strne %3, [%1, #" __stringify(AT91_DDRSDRC_RTR) "]\n\t" 105 " strne %3, [%1, #" __stringify(AT91_DDRSDRC_RTR) "]\n\t"
106 /* Power down SDRAM1 */ 106 /* Power down SDRAM1 */
107 " strne %4, [%1, #" __stringify(AT91_DDRSDRC_RTR) "]\n\t" 107 " strne %4, [%1, #" __stringify(AT91_DDRSDRC_LPR) "]\n\t"
108 /* Reset CPU */ 108 /* Reset CPU */
109 " str %5, [%2, #" __stringify(AT91_RSTC_CR) "]\n\t" 109 " str %5, [%2, #" __stringify(AT91_RSTC_CR) "]\n\t"
110 110
diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h
index ddaef8620b2c..b690cdba163b 100644
--- a/include/dt-bindings/clock/imx6qdl-clock.h
+++ b/include/dt-bindings/clock/imx6qdl-clock.h
@@ -62,8 +62,8 @@
62#define IMX6QDL_CLK_USDHC3_SEL 50 62#define IMX6QDL_CLK_USDHC3_SEL 50
63#define IMX6QDL_CLK_USDHC4_SEL 51 63#define IMX6QDL_CLK_USDHC4_SEL 51
64#define IMX6QDL_CLK_ENFC_SEL 52 64#define IMX6QDL_CLK_ENFC_SEL 52
65#define IMX6QDL_CLK_EMI_SEL 53 65#define IMX6QDL_CLK_EIM_SEL 53
66#define IMX6QDL_CLK_EMI_SLOW_SEL 54 66#define IMX6QDL_CLK_EIM_SLOW_SEL 54
67#define IMX6QDL_CLK_VDO_AXI_SEL 55 67#define IMX6QDL_CLK_VDO_AXI_SEL 55
68#define IMX6QDL_CLK_VPU_AXI_SEL 56 68#define IMX6QDL_CLK_VPU_AXI_SEL 56
69#define IMX6QDL_CLK_CKO1_SEL 57 69#define IMX6QDL_CLK_CKO1_SEL 57
@@ -106,8 +106,8 @@
106#define IMX6QDL_CLK_USDHC4_PODF 94 106#define IMX6QDL_CLK_USDHC4_PODF 94
107#define IMX6QDL_CLK_ENFC_PRED 95 107#define IMX6QDL_CLK_ENFC_PRED 95
108#define IMX6QDL_CLK_ENFC_PODF 96 108#define IMX6QDL_CLK_ENFC_PODF 96
109#define IMX6QDL_CLK_EMI_PODF 97 109#define IMX6QDL_CLK_EIM_PODF 97
110#define IMX6QDL_CLK_EMI_SLOW_PODF 98 110#define IMX6QDL_CLK_EIM_SLOW_PODF 98
111#define IMX6QDL_CLK_VPU_AXI_PODF 99 111#define IMX6QDL_CLK_VPU_AXI_PODF 99
112#define IMX6QDL_CLK_CKO1_PODF 100 112#define IMX6QDL_CLK_CKO1_PODF 100
113#define IMX6QDL_CLK_AXI 101 113#define IMX6QDL_CLK_AXI 101
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-27 16:13:32 -0500