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authorViresh Kumar <viresh.kumar@st.com>2012-04-09 23:32:35 -0400
committerArnd Bergmann <arnd@arndb.de>2012-05-12 15:44:12 -0400
commit5df33a62c4a028d6fc7f2dcc159827d09b7334b8 (patch)
treef4da61ce3bf14e9bf4a1dae3188109a6de34f708
parentf8abc080d33e69dfa2c3dd0f84c31832e2679091 (diff)
SPEAr: Switch to common clock framework
SPEAr SoCs used its own clock framework since now. From now on they will move to use common clock framework. This patch updates existing SPEAr machine support to adapt for common clock framework. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Reviewed-by: Mike Turquette <mturquette@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de>
Diffstat
-rw-r--r--MAINTAINERS4
-rw-r--r--arch/arm/Kconfig1
-rw-r--r--arch/arm/mach-spear3xx/Makefile2
-rw-r--r--arch/arm/mach-spear3xx/clock.c760
-rw-r--r--arch/arm/mach-spear3xx/include/mach/generic.h3
-rw-r--r--arch/arm/mach-spear3xx/include/mach/misc_regs.h144
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear.h13
-rw-r--r--arch/arm/mach-spear3xx/spear320.c1
-rw-r--r--arch/arm/mach-spear3xx/spear3xx.c2
-rw-r--r--arch/arm/mach-spear6xx/Makefile2
-rw-r--r--arch/arm/mach-spear6xx/clock.c683
-rw-r--r--arch/arm/mach-spear6xx/include/mach/misc_regs.h154
-rw-r--r--arch/arm/mach-spear6xx/spear6xx.c5
-rw-r--r--arch/arm/plat-spear/Makefile2
-rw-r--r--arch/arm/plat-spear/clock.c1005
-rw-r--r--arch/arm/plat-spear/include/plat/clock.h249
-rw-r--r--drivers/clk/spear/Makefile3
-rw-r--r--drivers/clk/spear/spear3xx_clock.c612
-rw-r--r--drivers/clk/spear/spear6xx_clock.c342
19 files changed, 983 insertions, 3004 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index 164e9a1df0f6..cb5425e3cd42 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6336,9 +6336,7 @@ L: spear-devel@list.st.com
6336L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 6336L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
6337W: http://www.st.com/spear 6337W: http://www.st.com/spear
6338S: Maintained 6338S: Maintained
6339F: arch/arm/mach-spear*/clock.c 6339F: drivers/clk/spear/
6340F: arch/arm/plat-spear/clock.c
6341F: arch/arm/plat-spear/include/plat/clock.h
6342 6340
6343SPEAR PAD MULTIPLEXING SUPPORT 6341SPEAR PAD MULTIPLEXING SUPPORT
6344M: Viresh Kumar <viresh.kumar@st.com> 6342M: Viresh Kumar <viresh.kumar@st.com>
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index cf006d40342c..ce030c242644 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -980,6 +980,7 @@ config PLAT_SPEAR
980 select ARM_AMBA 980 select ARM_AMBA
981 select ARCH_REQUIRE_GPIOLIB 981 select ARCH_REQUIRE_GPIOLIB
982 select CLKDEV_LOOKUP 982 select CLKDEV_LOOKUP
983 select COMMON_CLK
983 select CLKSRC_MMIO 984 select CLKSRC_MMIO
984 select GENERIC_CLOCKEVENTS 985 select GENERIC_CLOCKEVENTS
985 select HAVE_CLK 986 select HAVE_CLK
diff --git a/arch/arm/mach-spear3xx/Makefile b/arch/arm/mach-spear3xx/Makefile
index b24862489704..5b30d0d10892 100644
--- a/arch/arm/mach-spear3xx/Makefile
+++ b/arch/arm/mach-spear3xx/Makefile
@@ -3,7 +3,7 @@
3# 3#
4 4
5# common files 5# common files
6obj-y += spear3xx.o clock.o 6obj-y += spear3xx.o
7 7
8# spear300 specific files 8# spear300 specific files
9obj-$(CONFIG_MACH_SPEAR300) += spear300.o 9obj-$(CONFIG_MACH_SPEAR300) += spear300.o
diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c
deleted file mode 100644
index 6c4841f55223..000000000000
--- a/arch/arm/mach-spear3xx/clock.c
+++ /dev/null
@@ -1,760 +0,0 @@
1/*
2 * arch/arm/mach-spear3xx/clock.c
3 *
4 * SPEAr3xx machines clock framework source file
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/init.h>
15#include <linux/io.h>
16#include <linux/kernel.h>
17#include <asm/mach-types.h>
18#include <plat/clock.h>
19#include <mach/misc_regs.h>
20
21/* root clks */
22/* 32 KHz oscillator clock */
23static struct clk osc_32k_clk = {
24 .flags = ALWAYS_ENABLED,
25 .rate = 32000,
26};
27
28/* 24 MHz oscillator clock */
29static struct clk osc_24m_clk = {
30 .flags = ALWAYS_ENABLED,
31 .rate = 24000000,
32};
33
34/* clock derived from 32 KHz osc clk */
35/* rtc clock */
36static struct clk rtc_clk = {
37 .pclk = &osc_32k_clk,
38 .en_reg = PERIP1_CLK_ENB,
39 .en_reg_bit = RTC_CLK_ENB,
40 .recalc = &follow_parent,
41};
42
43/* clock derived from 24 MHz osc clk */
44/* pll masks structure */
45static struct pll_clk_masks pll1_masks = {
46 .mode_mask = PLL_MODE_MASK,
47 .mode_shift = PLL_MODE_SHIFT,
48 .norm_fdbk_m_mask = PLL_NORM_FDBK_M_MASK,
49 .norm_fdbk_m_shift = PLL_NORM_FDBK_M_SHIFT,
50 .dith_fdbk_m_mask = PLL_DITH_FDBK_M_MASK,
51 .dith_fdbk_m_shift = PLL_DITH_FDBK_M_SHIFT,
52 .div_p_mask = PLL_DIV_P_MASK,
53 .div_p_shift = PLL_DIV_P_SHIFT,
54 .div_n_mask = PLL_DIV_N_MASK,
55 .div_n_shift = PLL_DIV_N_SHIFT,
56};
57
58/* pll1 configuration structure */
59static struct pll_clk_config pll1_config = {
60 .mode_reg = PLL1_CTR,
61 .cfg_reg = PLL1_FRQ,
62 .masks = &pll1_masks,
63};
64
65/* pll rate configuration table, in ascending order of rates */
66struct pll_rate_tbl pll_rtbl[] = {
67 {.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* 266 MHz */
68 {.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* 332 MHz */
69};
70
71/* PLL1 clock */
72static struct clk pll1_clk = {
73 .flags = ENABLED_ON_INIT,
74 .pclk = &osc_24m_clk,
75 .en_reg = PLL1_CTR,
76 .en_reg_bit = PLL_ENABLE,
77 .calc_rate = &pll_calc_rate,
78 .recalc = &pll_clk_recalc,
79 .set_rate = &pll_clk_set_rate,
80 .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 1},
81 .private_data = &pll1_config,
82};
83
84/* PLL3 48 MHz clock */
85static struct clk pll3_48m_clk = {
86 .flags = ALWAYS_ENABLED,
87 .pclk = &osc_24m_clk,
88 .rate = 48000000,
89};
90
91/* watch dog timer clock */
92static struct clk wdt_clk = {
93 .flags = ALWAYS_ENABLED,
94 .pclk = &osc_24m_clk,
95 .recalc = &follow_parent,
96};
97
98/* clock derived from pll1 clk */
99/* cpu clock */
100static struct clk cpu_clk = {
101 .flags = ALWAYS_ENABLED,
102 .pclk = &pll1_clk,
103 .recalc = &follow_parent,
104};
105
106/* ahb masks structure */
107static struct bus_clk_masks ahb_masks = {
108 .mask = PLL_HCLK_RATIO_MASK,
109 .shift = PLL_HCLK_RATIO_SHIFT,
110};
111
112/* ahb configuration structure */
113static struct bus_clk_config ahb_config = {
114 .reg = CORE_CLK_CFG,
115 .masks = &ahb_masks,
116};
117
118/* ahb rate configuration table, in ascending order of rates */
119struct bus_rate_tbl bus_rtbl[] = {
120 {.div = 3}, /* == parent divided by 4 */
121 {.div = 2}, /* == parent divided by 3 */
122 {.div = 1}, /* == parent divided by 2 */
123 {.div = 0}, /* == parent divided by 1 */
124};
125
126/* ahb clock */
127static struct clk ahb_clk = {
128 .flags = ALWAYS_ENABLED,
129 .pclk = &pll1_clk,
130 .calc_rate = &bus_calc_rate,
131 .recalc = &bus_clk_recalc,
132 .set_rate = &bus_clk_set_rate,
133 .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
134 .private_data = &ahb_config,
135};
136
137/* auxiliary synthesizers masks */
138static struct aux_clk_masks aux_masks = {
139 .eq_sel_mask = AUX_EQ_SEL_MASK,
140 .eq_sel_shift = AUX_EQ_SEL_SHIFT,
141 .eq1_mask = AUX_EQ1_SEL,
142 .eq2_mask = AUX_EQ2_SEL,
143 .xscale_sel_mask = AUX_XSCALE_MASK,
144 .xscale_sel_shift = AUX_XSCALE_SHIFT,
145 .yscale_sel_mask = AUX_YSCALE_MASK,
146 .yscale_sel_shift = AUX_YSCALE_SHIFT,
147};
148
149/* uart synth configurations */
150static struct aux_clk_config uart_synth_config = {
151 .synth_reg = UART_CLK_SYNT,
152 .masks = &aux_masks,
153};
154
155/* aux rate configuration table, in ascending order of rates */
156struct aux_rate_tbl aux_rtbl[] = {
157 /* For PLL1 = 332 MHz */
158 {.xscale = 1, .yscale = 8, .eq = 1}, /* 41.5 MHz */
159 {.xscale = 1, .yscale = 4, .eq = 1}, /* 83 MHz */
160 {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
161};
162
163/* uart synth clock */
164static struct clk uart_synth_clk = {
165 .en_reg = UART_CLK_SYNT,
166 .en_reg_bit = AUX_SYNT_ENB,
167 .pclk = &pll1_clk,
168 .calc_rate = &aux_calc_rate,
169 .recalc = &aux_clk_recalc,
170 .set_rate = &aux_clk_set_rate,
171 .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 1},
172 .private_data = &uart_synth_config,
173};
174
175/* uart parents */
176static struct pclk_info uart_pclk_info[] = {
177 {
178 .pclk = &uart_synth_clk,
179 .pclk_val = AUX_CLK_PLL1_VAL,
180 }, {
181 .pclk = &pll3_48m_clk,
182 .pclk_val = AUX_CLK_PLL3_VAL,
183 },
184};
185
186/* uart parent select structure */
187static struct pclk_sel uart_pclk_sel = {
188 .pclk_info = uart_pclk_info,
189 .pclk_count = ARRAY_SIZE(uart_pclk_info),
190 .pclk_sel_reg = PERIP_CLK_CFG,
191 .pclk_sel_mask = UART_CLK_MASK,
192};
193
194/* uart clock */
195static struct clk uart_clk = {
196 .en_reg = PERIP1_CLK_ENB,
197 .en_reg_bit = UART_CLK_ENB,
198 .pclk_sel = &uart_pclk_sel,
199 .pclk_sel_shift = UART_CLK_SHIFT,
200 .recalc = &follow_parent,
201};
202
203/* firda configurations */
204static struct aux_clk_config firda_synth_config = {
205 .synth_reg = FIRDA_CLK_SYNT,
206 .masks = &aux_masks,
207};
208
209/* firda synth clock */
210static struct clk firda_synth_clk = {
211 .en_reg = FIRDA_CLK_SYNT,
212 .en_reg_bit = AUX_SYNT_ENB,
213 .pclk = &pll1_clk,
214 .calc_rate = &aux_calc_rate,
215 .recalc = &aux_clk_recalc,
216 .set_rate = &aux_clk_set_rate,
217 .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 1},
218 .private_data = &firda_synth_config,
219};
220
221/* firda parents */
222static struct pclk_info firda_pclk_info[] = {
223 {
224 .pclk = &firda_synth_clk,
225 .pclk_val = AUX_CLK_PLL1_VAL,
226 }, {
227 .pclk = &pll3_48m_clk,
228 .pclk_val = AUX_CLK_PLL3_VAL,
229 },
230};
231
232/* firda parent select structure */
233static struct pclk_sel firda_pclk_sel = {
234 .pclk_info = firda_pclk_info,
235 .pclk_count = ARRAY_SIZE(firda_pclk_info),
236 .pclk_sel_reg = PERIP_CLK_CFG,
237 .pclk_sel_mask = FIRDA_CLK_MASK,
238};
239
240/* firda clock */
241static struct clk firda_clk = {
242 .en_reg = PERIP1_CLK_ENB,
243 .en_reg_bit = FIRDA_CLK_ENB,
244 .pclk_sel = &firda_pclk_sel,
245 .pclk_sel_shift = FIRDA_CLK_SHIFT,
246 .recalc = &follow_parent,
247};
248
249/* gpt synthesizer masks */
250static struct gpt_clk_masks gpt_masks = {
251 .mscale_sel_mask = GPT_MSCALE_MASK,
252 .mscale_sel_shift = GPT_MSCALE_SHIFT,
253 .nscale_sel_mask = GPT_NSCALE_MASK,
254 .nscale_sel_shift = GPT_NSCALE_SHIFT,
255};
256
257/* gpt rate configuration table, in ascending order of rates */
258struct gpt_rate_tbl gpt_rtbl[] = {
259 /* For pll1 = 332 MHz */
260 {.mscale = 4, .nscale = 0}, /* 41.5 MHz */
261 {.mscale = 2, .nscale = 0}, /* 55.3 MHz */
262 {.mscale = 1, .nscale = 0}, /* 83 MHz */
263};
264
265/* gpt0 synth clk config*/
266static struct gpt_clk_config gpt0_synth_config = {
267 .synth_reg = PRSC1_CLK_CFG,
268 .masks = &gpt_masks,
269};
270
271/* gpt synth clock */
272static struct clk gpt0_synth_clk = {
273 .flags = ALWAYS_ENABLED,
274 .pclk = &pll1_clk,
275 .calc_rate = &gpt_calc_rate,
276 .recalc = &gpt_clk_recalc,
277 .set_rate = &gpt_clk_set_rate,
278 .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
279 .private_data = &gpt0_synth_config,
280};
281
282/* gpt parents */
283static struct pclk_info gpt0_pclk_info[] = {
284 {
285 .pclk = &gpt0_synth_clk,
286 .pclk_val = AUX_CLK_PLL1_VAL,
287 }, {
288 .pclk = &pll3_48m_clk,
289 .pclk_val = AUX_CLK_PLL3_VAL,
290 },
291};
292
293/* gpt parent select structure */
294static struct pclk_sel gpt0_pclk_sel = {
295 .pclk_info = gpt0_pclk_info,
296 .pclk_count = ARRAY_SIZE(gpt0_pclk_info),
297 .pclk_sel_reg = PERIP_CLK_CFG,
298 .pclk_sel_mask = GPT_CLK_MASK,
299};
300
301/* gpt0 timer clock */
302static struct clk gpt0_clk = {
303 .flags = ALWAYS_ENABLED,
304 .pclk_sel = &gpt0_pclk_sel,
305 .pclk_sel_shift = GPT0_CLK_SHIFT,
306 .recalc = &follow_parent,
307};
308
309/* gpt1 synth clk configurations */
310static struct gpt_clk_config gpt1_synth_config = {
311 .synth_reg = PRSC2_CLK_CFG,
312 .masks = &gpt_masks,
313};
314
315/* gpt1 synth clock */
316static struct clk gpt1_synth_clk = {
317 .flags = ALWAYS_ENABLED,
318 .pclk = &pll1_clk,
319 .calc_rate = &gpt_calc_rate,
320 .recalc = &gpt_clk_recalc,
321 .set_rate = &gpt_clk_set_rate,
322 .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
323 .private_data = &gpt1_synth_config,
324};
325
326static struct pclk_info gpt1_pclk_info[] = {
327 {
328 .pclk = &gpt1_synth_clk,
329 .pclk_val = AUX_CLK_PLL1_VAL,
330 }, {
331 .pclk = &pll3_48m_clk,
332 .pclk_val = AUX_CLK_PLL3_VAL,
333 },
334};
335
336/* gpt parent select structure */
337static struct pclk_sel gpt1_pclk_sel = {
338 .pclk_info = gpt1_pclk_info,
339 .pclk_count = ARRAY_SIZE(gpt1_pclk_info),
340 .pclk_sel_reg = PERIP_CLK_CFG,
341 .pclk_sel_mask = GPT_CLK_MASK,
342};
343
344/* gpt1 timer clock */
345static struct clk gpt1_clk = {
346 .en_reg = PERIP1_CLK_ENB,
347 .en_reg_bit = GPT1_CLK_ENB,
348 .pclk_sel = &gpt1_pclk_sel,
349 .pclk_sel_shift = GPT1_CLK_SHIFT,
350 .recalc = &follow_parent,
351};
352
353/* gpt2 synth clk configurations */
354static struct gpt_clk_config gpt2_synth_config = {
355 .synth_reg = PRSC3_CLK_CFG,
356 .masks = &gpt_masks,
357};
358
359/* gpt1 synth clock */
360static struct clk gpt2_synth_clk = {
361 .flags = ALWAYS_ENABLED,
362 .pclk = &pll1_clk,
363 .calc_rate = &gpt_calc_rate,
364 .recalc = &gpt_clk_recalc,
365 .set_rate = &gpt_clk_set_rate,
366 .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
367 .private_data = &gpt2_synth_config,
368};
369
370static struct pclk_info gpt2_pclk_info[] = {
371 {
372 .pclk = &gpt2_synth_clk,
373 .pclk_val = AUX_CLK_PLL1_VAL,
374 }, {
375 .pclk = &pll3_48m_clk,
376 .pclk_val = AUX_CLK_PLL3_VAL,
377 },
378};
379
380/* gpt parent select structure */
381static struct pclk_sel gpt2_pclk_sel = {
382 .pclk_info = gpt2_pclk_info,
383 .pclk_count = ARRAY_SIZE(gpt2_pclk_info),
384 .pclk_sel_reg = PERIP_CLK_CFG,
385 .pclk_sel_mask = GPT_CLK_MASK,
386};
387
388/* gpt2 timer clock */
389static struct clk gpt2_clk = {
390 .en_reg = PERIP1_CLK_ENB,
391 .en_reg_bit = GPT2_CLK_ENB,
392 .pclk_sel = &gpt2_pclk_sel,
393 .pclk_sel_shift = GPT2_CLK_SHIFT,
394 .recalc = &follow_parent,
395};
396
397/* clock derived from pll3 clk */
398/* usbh clock */
399static struct clk usbh_clk = {
400 .pclk = &pll3_48m_clk,
401 .en_reg = PERIP1_CLK_ENB,
402 .en_reg_bit = USBH_CLK_ENB,
403 .recalc = &follow_parent,
404};
405
406/* usbd clock */
407static struct clk usbd_clk = {
408 .pclk = &pll3_48m_clk,
409 .en_reg = PERIP1_CLK_ENB,
410 .en_reg_bit = USBD_CLK_ENB,
411 .recalc = &follow_parent,
412};
413
414/* clock derived from ahb clk */
415/* apb masks structure */
416static struct bus_clk_masks apb_masks = {
417 .mask = HCLK_PCLK_RATIO_MASK,
418 .shift = HCLK_PCLK_RATIO_SHIFT,
419};
420
421/* apb configuration structure */
422static struct bus_clk_config apb_config = {
423 .reg = CORE_CLK_CFG,
424 .masks = &apb_masks,
425};
426
427/* apb clock */
428static struct clk apb_clk = {
429 .flags = ALWAYS_ENABLED,
430 .pclk = &ahb_clk,
431 .calc_rate = &bus_calc_rate,
432 .recalc = &bus_clk_recalc,
433 .set_rate = &bus_clk_set_rate,
434 .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
435 .private_data = &apb_config,
436};
437
438/* i2c clock */
439static struct clk i2c_clk = {
440 .pclk = &ahb_clk,
441 .en_reg = PERIP1_CLK_ENB,
442 .en_reg_bit = I2C_CLK_ENB,
443 .recalc = &follow_parent,
444};
445
446/* dma clock */
447static struct clk dma_clk = {
448 .pclk = &ahb_clk,
449 .en_reg = PERIP1_CLK_ENB,
450 .en_reg_bit = DMA_CLK_ENB,
451 .recalc = &follow_parent,
452};
453
454/* jpeg clock */
455static struct clk jpeg_clk = {
456 .pclk = &ahb_clk,
457 .en_reg = PERIP1_CLK_ENB,
458 .en_reg_bit = JPEG_CLK_ENB,
459 .recalc = &follow_parent,
460};
461
462/* gmac clock */
463static struct clk gmac_clk = {
464 .pclk = &ahb_clk,
465 .en_reg = PERIP1_CLK_ENB,
466 .en_reg_bit = GMAC_CLK_ENB,
467 .recalc = &follow_parent,
468};
469
470/* smi clock */
471static struct clk smi_clk = {
472 .pclk = &ahb_clk,
473 .en_reg = PERIP1_CLK_ENB,
474 .en_reg_bit = SMI_CLK_ENB,
475 .recalc = &follow_parent,
476};
477
478/* c3 clock */
479static struct clk c3_clk = {
480 .pclk = &ahb_clk,
481 .en_reg = PERIP1_CLK_ENB,
482 .en_reg_bit = C3_CLK_ENB,
483 .recalc = &follow_parent,
484};
485
486/* clock derived from apb clk */
487/* adc clock */
488static struct clk adc_clk = {
489 .pclk = &apb_clk,
490 .en_reg = PERIP1_CLK_ENB,
491 .en_reg_bit = ADC_CLK_ENB,
492 .recalc = &follow_parent,
493};
494
495#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
496/* emi clock */
497static struct clk emi_clk = {
498 .flags = ALWAYS_ENABLED,
499 .pclk = &ahb_clk,
500 .recalc = &follow_parent,
501};
502#endif
503
504/* ssp clock */
505static struct clk ssp0_clk = {
506 .pclk = &apb_clk,
507 .en_reg = PERIP1_CLK_ENB,
508 .en_reg_bit = SSP_CLK_ENB,
509 .recalc = &follow_parent,
510};
511
512/* gpio clock */
513static struct clk gpio_clk = {
514 .pclk = &apb_clk,
515 .en_reg = PERIP1_CLK_ENB,
516 .en_reg_bit = GPIO_CLK_ENB,
517 .recalc = &follow_parent,
518};
519
520static struct clk dummy_apb_pclk;
521
522#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR310) || \
523 defined(CONFIG_MACH_SPEAR320)
524/* fsmc clock */
525static struct clk fsmc_clk = {
526 .flags = ALWAYS_ENABLED,
527 .pclk = &ahb_clk,
528 .recalc = &follow_parent,
529};
530#endif
531
532/* common clocks to spear310 and spear320 */
533#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
534/* uart1 clock */
535static struct clk uart1_clk = {
536 .flags = ALWAYS_ENABLED,
537 .pclk = &apb_clk,
538 .recalc = &follow_parent,
539};
540
541/* uart2 clock */
542static struct clk uart2_clk = {
543 .flags = ALWAYS_ENABLED,
544 .pclk = &apb_clk,
545 .recalc = &follow_parent,
546};
547#endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */
548
549/* common clocks to spear300 and spear320 */
550#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR320)
551/* clcd clock */
552static struct clk clcd_clk = {
553 .flags = ALWAYS_ENABLED,
554 .pclk = &pll3_48m_clk,
555 .recalc = &follow_parent,
556};
557
558/* sdhci clock */
559static struct clk sdhci_clk = {
560 .flags = ALWAYS_ENABLED,
561 .pclk = &ahb_clk,
562 .recalc = &follow_parent,
563};
564#endif /* CONFIG_MACH_SPEAR300 || CONFIG_MACH_SPEAR320 */
565
566/* spear300 machine specific clock structures */
567#ifdef CONFIG_MACH_SPEAR300
568/* gpio1 clock */
569static struct clk gpio1_clk = {
570 .flags = ALWAYS_ENABLED,
571 .pclk = &apb_clk,
572 .recalc = &follow_parent,
573};
574
575/* keyboard clock */
576static struct clk kbd_clk = {
577 .flags = ALWAYS_ENABLED,
578 .pclk = &apb_clk,
579 .recalc = &follow_parent,
580};
581
582#endif
583
584/* spear310 machine specific clock structures */
585#ifdef CONFIG_MACH_SPEAR310
586/* uart3 clock */
587static struct clk uart3_clk = {
588 .flags = ALWAYS_ENABLED,
589 .pclk = &apb_clk,
590 .recalc = &follow_parent,
591};
592
593/* uart4 clock */
594static struct clk uart4_clk = {
595 .flags = ALWAYS_ENABLED,
596 .pclk = &apb_clk,
597 .recalc = &follow_parent,
598};
599
600/* uart5 clock */
601static struct clk uart5_clk = {
602 .flags = ALWAYS_ENABLED,
603 .pclk = &apb_clk,
604 .recalc = &follow_parent,
605};
606#endif
607
608/* spear320 machine specific clock structures */
609#ifdef CONFIG_MACH_SPEAR320
610/* can0 clock */
611static struct clk can0_clk = {
612 .flags = ALWAYS_ENABLED,
613 .pclk = &apb_clk,
614 .recalc = &follow_parent,
615};
616
617/* can1 clock */
618static struct clk can1_clk = {
619 .flags = ALWAYS_ENABLED,
620 .pclk = &apb_clk,
621 .recalc = &follow_parent,
622};
623
624/* i2c1 clock */
625static struct clk i2c1_clk = {
626 .flags = ALWAYS_ENABLED,
627 .pclk = &ahb_clk,
628 .recalc = &follow_parent,
629};
630
631/* ssp1 clock */
632static struct clk ssp1_clk = {
633 .flags = ALWAYS_ENABLED,
634 .pclk = &apb_clk,
635 .recalc = &follow_parent,
636};
637
638/* ssp2 clock */
639static struct clk ssp2_clk = {
640 .flags = ALWAYS_ENABLED,
641 .pclk = &apb_clk,
642 .recalc = &follow_parent,
643};
644
645/* pwm clock */
646static struct clk pwm_clk = {
647 .flags = ALWAYS_ENABLED,
648 .pclk = &apb_clk,
649 .recalc = &follow_parent,
650};
651#endif
652
653/* array of all spear 3xx clock lookups */
654static struct clk_lookup spear_clk_lookups[] = {
655 { .con_id = "apb_pclk", .clk = &dummy_apb_pclk},
656 /* root clks */
657 { .con_id = "osc_32k_clk", .clk = &osc_32k_clk},
658 { .con_id = "osc_24m_clk", .clk = &osc_24m_clk},
659 /* clock derived from 32 KHz osc clk */
660 { .dev_id = "rtc-spear", .clk = &rtc_clk},
661 /* clock derived from 24 MHz osc clk */
662 { .con_id = "pll1_clk", .clk = &pll1_clk},
663 { .con_id = "pll3_48m_clk", .clk = &pll3_48m_clk},
664 { .dev_id = "wdt", .clk = &wdt_clk},
665 /* clock derived from pll1 clk */
666 { .con_id = "cpu_clk", .clk = &cpu_clk},
667 { .con_id = "ahb_clk", .clk = &ahb_clk},
668 { .con_id = "uart_synth_clk", .clk = &uart_synth_clk},
669 { .con_id = "firda_synth_clk", .clk = &firda_synth_clk},
670 { .con_id = "gpt0_synth_clk", .clk = &gpt0_synth_clk},
671 { .con_id = "gpt1_synth_clk", .clk = &gpt1_synth_clk},
672 { .con_id = "gpt2_synth_clk", .clk = &gpt2_synth_clk},
673 { .dev_id = "uart", .clk = &uart_clk},
674 { .dev_id = "firda", .clk = &firda_clk},
675 { .dev_id = "gpt0", .clk = &gpt0_clk},
676 { .dev_id = "gpt1", .clk = &gpt1_clk},
677 { .dev_id = "gpt2", .clk = &gpt2_clk},
678 /* clock derived from pll3 clk */
679 { .dev_id = "designware_udc", .clk = &usbd_clk},
680 { .con_id = "usbh_clk", .clk = &usbh_clk},
681 /* clock derived from ahb clk */
682 { .con_id = "apb_clk", .clk = &apb_clk},
683 { .dev_id = "i2c_designware.0", .clk = &i2c_clk},
684 { .dev_id = "dma", .clk = &dma_clk},
685 { .dev_id = "jpeg", .clk = &jpeg_clk},
686 { .dev_id = "gmac", .clk = &gmac_clk},
687 { .dev_id = "smi", .clk = &smi_clk},
688 { .dev_id = "c3", .clk = &c3_clk},
689 /* clock derived from apb clk */
690 { .dev_id = "adc", .clk = &adc_clk},
691 { .dev_id = "ssp-pl022.0", .clk = &ssp0_clk},
692 { .dev_id = "gpio", .clk = &gpio_clk},
693};
694
695/* array of all spear 300 clock lookups */
696#ifdef CONFIG_MACH_SPEAR300
697static struct clk_lookup spear300_clk_lookups[] = {
698 { .dev_id = "clcd", .clk = &clcd_clk},
699 { .con_id = "fsmc", .clk = &fsmc_clk},
700 { .dev_id = "gpio1", .clk = &gpio1_clk},
701 { .dev_id = "keyboard", .clk = &kbd_clk},
702 { .dev_id = "sdhci", .clk = &sdhci_clk},
703};
704#endif
705
706/* array of all spear 310 clock lookups */
707#ifdef CONFIG_MACH_SPEAR310
708static struct clk_lookup spear310_clk_lookups[] = {
709 { .con_id = "fsmc", .clk = &fsmc_clk},
710 { .con_id = "emi", .clk = &emi_clk},
711 { .dev_id = "uart1", .clk = &uart1_clk},
712 { .dev_id = "uart2", .clk = &uart2_clk},
713 { .dev_id = "uart3", .clk = &uart3_clk},
714 { .dev_id = "uart4", .clk = &uart4_clk},
715 { .dev_id = "uart5", .clk = &uart5_clk},
716};
717#endif
718
719/* array of all spear 320 clock lookups */
720#ifdef CONFIG_MACH_SPEAR320
721static struct clk_lookup spear320_clk_lookups[] = {
722 { .dev_id = "clcd", .clk = &clcd_clk},
723 { .con_id = "fsmc", .clk = &fsmc_clk},
724 { .dev_id = "i2c_designware.1", .clk = &i2c1_clk},
725 { .con_id = "emi", .clk = &emi_clk},
726 { .dev_id = "pwm", .clk = &pwm_clk},
727 { .dev_id = "sdhci", .clk = &sdhci_clk},
728 { .dev_id = "c_can_platform.0", .clk = &can0_clk},
729 { .dev_id = "c_can_platform.1", .clk = &can1_clk},
730 { .dev_id = "ssp-pl022.1", .clk = &ssp1_clk},
731 { .dev_id = "ssp-pl022.2", .clk = &ssp2_clk},
732 { .dev_id = "uart1", .clk = &uart1_clk},
733 { .dev_id = "uart2", .clk = &uart2_clk},
734};
735#endif
736
737void __init spear3xx_clk_init(void)
738{
739 int i, cnt;
740 struct clk_lookup *lookups;
741
742 if (machine_is_spear300()) {
743 cnt = ARRAY_SIZE(spear300_clk_lookups);
744 lookups = spear300_clk_lookups;
745 } else if (machine_is_spear310()) {
746 cnt = ARRAY_SIZE(spear310_clk_lookups);
747 lookups = spear310_clk_lookups;
748 } else {
749 cnt = ARRAY_SIZE(spear320_clk_lookups);
750 lookups = spear320_clk_lookups;
751 }
752
753 for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
754 clk_register(&spear_clk_lookups[i]);
755
756 for (i = 0; i < cnt; i++)
757 clk_register(&lookups[i]);
758
759 clk_init();
760}
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index 14276e5a98d2..15c107aad202 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -36,8 +36,8 @@ extern struct amba_device spear3xx_uart_device;
36extern struct sys_timer spear3xx_timer; 36extern struct sys_timer spear3xx_timer;
37 37
38/* Add spear3xx family function declarations here */ 38/* Add spear3xx family function declarations here */
39void __init spear3xx_clk_init(void);
40void __init spear_setup_timer(void); 39void __init spear_setup_timer(void);
40void __init spear3xx_clk_init(void);
41void __init spear3xx_map_io(void); 41void __init spear3xx_map_io(void);
42void __init spear3xx_init_irq(void); 42void __init spear3xx_init_irq(void);
43void __init spear3xx_init(void); 43void __init spear3xx_init(void);
@@ -156,7 +156,6 @@ extern struct pmx_dev spear310_pmx_tdm0;
156/* Add spear310 machine function declarations here */ 156/* Add spear310 machine function declarations here */
157void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs, 157void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
158 u8 pmx_dev_count); 158 u8 pmx_dev_count);
159
160#endif /* CONFIG_MACH_SPEAR310 */ 159#endif /* CONFIG_MACH_SPEAR310 */
161 160
162/* spear320 declarations */ 161/* spear320 declarations */
diff --git a/arch/arm/mach-spear3xx/include/mach/misc_regs.h b/arch/arm/mach-spear3xx/include/mach/misc_regs.h
index 5bd8cd8d4852..50cfe0d1a7c4 100644
--- a/arch/arm/mach-spear3xx/include/mach/misc_regs.h
+++ b/arch/arm/mach-spear3xx/include/mach/misc_regs.h
@@ -15,150 +15,8 @@
15#define __MACH_MISC_REGS_H 15#define __MACH_MISC_REGS_H
16 16
17#include <mach/hardware.h> 17#include <mach/hardware.h>
18#include <mach/spear.h>
18 19
19#define MISC_BASE IOMEM(VA_SPEAR3XX_ICM3_MISC_REG_BASE) 20#define MISC_BASE IOMEM(VA_SPEAR3XX_ICM3_MISC_REG_BASE)
20 21
21#define SOC_CFG_CTR (MISC_BASE + 0x000)
22#define DIAG_CFG_CTR (MISC_BASE + 0x004)
23#define PLL1_CTR (MISC_BASE + 0x008)
24#define PLL1_FRQ (MISC_BASE + 0x00C)
25#define PLL1_MOD (MISC_BASE + 0x010)
26#define PLL2_CTR (MISC_BASE + 0x014)
27/* PLL_CTR register masks */
28#define PLL_ENABLE 2
29#define PLL_MODE_SHIFT 4
30#define PLL_MODE_MASK 0x3
31#define PLL_MODE_NORMAL 0
32#define PLL_MODE_FRACTION 1
33#define PLL_MODE_DITH_DSB 2
34#define PLL_MODE_DITH_SSB 3
35
36#define PLL2_FRQ (MISC_BASE + 0x018)
37/* PLL FRQ register masks */
38#define PLL_DIV_N_SHIFT 0
39#define PLL_DIV_N_MASK 0xFF
40#define PLL_DIV_P_SHIFT 8
41#define PLL_DIV_P_MASK 0x7
42#define PLL_NORM_FDBK_M_SHIFT 24
43#define PLL_NORM_FDBK_M_MASK 0xFF
44#define PLL_DITH_FDBK_M_SHIFT 16
45#define PLL_DITH_FDBK_M_MASK 0xFFFF
46
47#define PLL2_MOD (MISC_BASE + 0x01C)
48#define PLL_CLK_CFG (MISC_BASE + 0x020)
49#define CORE_CLK_CFG (MISC_BASE + 0x024)
50/* CORE CLK CFG register masks */
51#define PLL_HCLK_RATIO_SHIFT 10
52#define PLL_HCLK_RATIO_MASK 0x3
53#define HCLK_PCLK_RATIO_SHIFT 8
54#define HCLK_PCLK_RATIO_MASK 0x3
55
56#define PERIP_CLK_CFG (MISC_BASE + 0x028)
57/* PERIP_CLK_CFG register masks */
58#define UART_CLK_SHIFT 4
59#define UART_CLK_MASK 0x1
60#define FIRDA_CLK_SHIFT 5
61#define FIRDA_CLK_MASK 0x3
62#define GPT0_CLK_SHIFT 8
63#define GPT1_CLK_SHIFT 11
64#define GPT2_CLK_SHIFT 12
65#define GPT_CLK_MASK 0x1
66#define AUX_CLK_PLL3_VAL 0
67#define AUX_CLK_PLL1_VAL 1
68
69#define PERIP1_CLK_ENB (MISC_BASE + 0x02C)
70/* PERIP1_CLK_ENB register masks */
71#define UART_CLK_ENB 3
72#define SSP_CLK_ENB 5
73#define I2C_CLK_ENB 7
74#define JPEG_CLK_ENB 8
75#define FIRDA_CLK_ENB 10
76#define GPT1_CLK_ENB 11
77#define GPT2_CLK_ENB 12
78#define ADC_CLK_ENB 15
79#define RTC_CLK_ENB 17
80#define GPIO_CLK_ENB 18
81#define DMA_CLK_ENB 19
82#define SMI_CLK_ENB 21
83#define GMAC_CLK_ENB 23
84#define USBD_CLK_ENB 24
85#define USBH_CLK_ENB 25
86#define C3_CLK_ENB 31
87
88#define SOC_CORE_ID (MISC_BASE + 0x030)
89#define RAS_CLK_ENB (MISC_BASE + 0x034)
90#define PERIP1_SOF_RST (MISC_BASE + 0x038)
91/* PERIP1_SOF_RST register masks */
92#define JPEG_SOF_RST 8
93
94#define SOC_USER_ID (MISC_BASE + 0x03C)
95#define RAS_SOF_RST (MISC_BASE + 0x040)
96#define PRSC1_CLK_CFG (MISC_BASE + 0x044)
97#define PRSC2_CLK_CFG (MISC_BASE + 0x048)
98#define PRSC3_CLK_CFG (MISC_BASE + 0x04C)
99/* gpt synthesizer register masks */
100#define GPT_MSCALE_SHIFT 0
101#define GPT_MSCALE_MASK 0xFFF
102#define GPT_NSCALE_SHIFT 12
103#define GPT_NSCALE_MASK 0xF
104
105#define AMEM_CLK_CFG (MISC_BASE + 0x050)
106#define EXPI_CLK_CFG (MISC_BASE + 0x054)
107#define CLCD_CLK_SYNT (MISC_BASE + 0x05C)
108#define FIRDA_CLK_SYNT (MISC_BASE + 0x060)
109#define UART_CLK_SYNT (MISC_BASE + 0x064)
110#define GMAC_CLK_SYNT (MISC_BASE + 0x068)
111#define RAS1_CLK_SYNT (MISC_BASE + 0x06C)
112#define RAS2_CLK_SYNT (MISC_BASE + 0x070)
113#define RAS3_CLK_SYNT (MISC_BASE + 0x074)
114#define RAS4_CLK_SYNT (MISC_BASE + 0x078)
115/* aux clk synthesiser register masks for irda to ras4 */
116#define AUX_SYNT_ENB 31
117#define AUX_EQ_SEL_SHIFT 30
118#define AUX_EQ_SEL_MASK 1
119#define AUX_EQ1_SEL 0
120#define AUX_EQ2_SEL 1
121#define AUX_XSCALE_SHIFT 16
122#define AUX_XSCALE_MASK 0xFFF
123#define AUX_YSCALE_SHIFT 0
124#define AUX_YSCALE_MASK 0xFFF
125
126#define ICM1_ARB_CFG (MISC_BASE + 0x07C)
127#define ICM2_ARB_CFG (MISC_BASE + 0x080)
128#define ICM3_ARB_CFG (MISC_BASE + 0x084)
129#define ICM4_ARB_CFG (MISC_BASE + 0x088)
130#define ICM5_ARB_CFG (MISC_BASE + 0x08C)
131#define ICM6_ARB_CFG (MISC_BASE + 0x090)
132#define ICM7_ARB_CFG (MISC_BASE + 0x094)
133#define ICM8_ARB_CFG (MISC_BASE + 0x098)
134#define ICM9_ARB_CFG (MISC_BASE + 0x09C)
135#define DMA_CHN_CFG (MISC_BASE + 0x0A0)
136#define USB2_PHY_CFG (MISC_BASE + 0x0A4)
137#define GMAC_CFG_CTR (MISC_BASE + 0x0A8)
138#define EXPI_CFG_CTR (MISC_BASE + 0x0AC)
139#define PRC1_LOCK_CTR (MISC_BASE + 0x0C0)
140#define PRC2_LOCK_CTR (MISC_BASE + 0x0C4)
141#define PRC3_LOCK_CTR (MISC_BASE + 0x0C8)
142#define PRC4_LOCK_CTR (MISC_BASE + 0x0CC)
143#define PRC1_IRQ_CTR (MISC_BASE + 0x0D0)
144#define PRC2_IRQ_CTR (MISC_BASE + 0x0D4)
145#define PRC3_IRQ_CTR (MISC_BASE + 0x0D8)
146#define PRC4_IRQ_CTR (MISC_BASE + 0x0DC)
147#define PWRDOWN_CFG_CTR (MISC_BASE + 0x0E0)
148#define COMPSSTL_1V8_CFG (MISC_BASE + 0x0E4)
149#define COMPSSTL_2V5_CFG (MISC_BASE + 0x0E8)
150#define COMPCOR_3V3_CFG (MISC_BASE + 0x0EC)
151#define SSTLPAD_CFG_CTR (MISC_BASE + 0x0F0)
152#define BIST1_CFG_CTR (MISC_BASE + 0x0F4)
153#define BIST2_CFG_CTR (MISC_BASE + 0x0F8)
154#define BIST3_CFG_CTR (MISC_BASE + 0x0FC)
155#define BIST4_CFG_CTR (MISC_BASE + 0x100)
156#define BIST5_CFG_CTR (MISC_BASE + 0x104)
157#define BIST1_STS_RES (MISC_BASE + 0x108)
158#define BIST2_STS_RES (MISC_BASE + 0x10C)
159#define BIST3_STS_RES (MISC_BASE + 0x110)
160#define BIST4_STS_RES (MISC_BASE + 0x114)
161#define BIST5_STS_RES (MISC_BASE + 0x118)
162#define SYSERR_CFG_CTR (MISC_BASE + 0x11C)
163
164#endif /* __MACH_MISC_REGS_H */ 22#endif /* __MACH_MISC_REGS_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear.h b/arch/arm/mach-spear3xx/include/mach/spear.h
index 63fd98356919..881109522060 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear.h
@@ -78,4 +78,17 @@
78#define SPEAR_SYS_CTRL_BASE SPEAR3XX_ICM3_SYS_CTRL_BASE 78#define SPEAR_SYS_CTRL_BASE SPEAR3XX_ICM3_SYS_CTRL_BASE
79#define VA_SPEAR_SYS_CTRL_BASE VA_SPEAR3XX_ICM3_SYS_CTRL_BASE 79#define VA_SPEAR_SYS_CTRL_BASE VA_SPEAR3XX_ICM3_SYS_CTRL_BASE
80 80
81/* SPEAr320 Macros */
82#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000)
83#define VA_SPEAR320_SOC_CONFIG_BASE UL(0xFE000000)
84#define SPEAR320_CONTROL_REG IOMEM(VA_SPEAR320_SOC_CONFIG_BASE)
85#define SPEAR320_EXT_CTRL_REG IOMEM(VA_SPEAR320_SOC_CONFIG_BASE + 0x0018)
86 #define SPEAR320_UARTX_PCLK_MASK 0x1
87 #define SPEAR320_UART2_PCLK_SHIFT 8
88 #define SPEAR320_UART3_PCLK_SHIFT 9
89 #define SPEAR320_UART4_PCLK_SHIFT 10
90 #define SPEAR320_UART5_PCLK_SHIFT 11
91 #define SPEAR320_UART6_PCLK_SHIFT 12
92 #define SPEAR320_RS485_PCLK_SHIFT 13
93
81#endif /* __MACH_SPEAR3XX_H */ 94#endif /* __MACH_SPEAR3XX_H */
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index deaaf199612c..bfdad554319c 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -16,6 +16,7 @@
16#include <plat/shirq.h> 16#include <plat/shirq.h>
17#include <mach/generic.h> 17#include <mach/generic.h>
18#include <mach/hardware.h> 18#include <mach/hardware.h>
19#include <mach/spear.h>
19 20
20/* pad multiplexing support */ 21/* pad multiplexing support */
21/* muxing registers */ 22/* muxing registers */
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index b1733c37f209..2625ab9a6c8b 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -511,6 +511,8 @@ static void __init spear3xx_timer_init(void)
511 char pclk_name[] = "pll3_48m_clk"; 511 char pclk_name[] = "pll3_48m_clk";
512 struct clk *gpt_clk, *pclk; 512 struct clk *gpt_clk, *pclk;
513 513
514 spear3xx_clk_init();
515
514 /* get the system timer clock */ 516 /* get the system timer clock */
515 gpt_clk = clk_get_sys("gpt0", NULL); 517 gpt_clk = clk_get_sys("gpt0", NULL);
516 if (IS_ERR(gpt_clk)) { 518 if (IS_ERR(gpt_clk)) {
diff --git a/arch/arm/mach-spear6xx/Makefile b/arch/arm/mach-spear6xx/Makefile
index 76e5750552fc..898831d93f37 100644
--- a/arch/arm/mach-spear6xx/Makefile
+++ b/arch/arm/mach-spear6xx/Makefile
@@ -3,4 +3,4 @@
3# 3#
4 4
5# common files 5# common files
6obj-y += clock.o spear6xx.o 6obj-y += spear6xx.o
diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c
deleted file mode 100644
index a86499a8a15f..000000000000
--- a/arch/arm/mach-spear6xx/clock.c
+++ /dev/null
@@ -1,683 +0,0 @@
1/*
2 * arch/arm/mach-spear6xx/clock.c
3 *
4 * SPEAr6xx machines clock framework source file
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/init.h>
15#include <linux/io.h>
16#include <linux/kernel.h>
17#include <plat/clock.h>
18#include <mach/misc_regs.h>
19
20/* root clks */
21/* 32 KHz oscillator clock */
22static struct clk osc_32k_clk = {
23 .flags = ALWAYS_ENABLED,
24 .rate = 32000,
25};
26
27/* 30 MHz oscillator clock */
28static struct clk osc_30m_clk = {
29 .flags = ALWAYS_ENABLED,
30 .rate = 30000000,
31};
32
33/* clock derived from 32 KHz osc clk */
34/* rtc clock */
35static struct clk rtc_clk = {
36 .pclk = &osc_32k_clk,
37 .en_reg = PERIP1_CLK_ENB,
38 .en_reg_bit = RTC_CLK_ENB,
39 .recalc = &follow_parent,
40};
41
42/* clock derived from 30 MHz osc clk */
43/* pll masks structure */
44static struct pll_clk_masks pll1_masks = {
45 .mode_mask = PLL_MODE_MASK,
46 .mode_shift = PLL_MODE_SHIFT,
47 .norm_fdbk_m_mask = PLL_NORM_FDBK_M_MASK,
48 .norm_fdbk_m_shift = PLL_NORM_FDBK_M_SHIFT,
49 .dith_fdbk_m_mask = PLL_DITH_FDBK_M_MASK,
50 .dith_fdbk_m_shift = PLL_DITH_FDBK_M_SHIFT,
51 .div_p_mask = PLL_DIV_P_MASK,
52 .div_p_shift = PLL_DIV_P_SHIFT,
53 .div_n_mask = PLL_DIV_N_MASK,
54 .div_n_shift = PLL_DIV_N_SHIFT,
55};
56
57/* pll1 configuration structure */
58static struct pll_clk_config pll1_config = {
59 .mode_reg = PLL1_CTR,
60 .cfg_reg = PLL1_FRQ,
61 .masks = &pll1_masks,
62};
63
64/* pll rate configuration table, in ascending order of rates */
65struct pll_rate_tbl pll_rtbl[] = {
66 {.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* 266 MHz */
67 {.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* 332 MHz */
68};
69
70/* PLL1 clock */
71static struct clk pll1_clk = {
72 .flags = ENABLED_ON_INIT,
73 .pclk = &osc_30m_clk,
74 .en_reg = PLL1_CTR,
75 .en_reg_bit = PLL_ENABLE,
76 .calc_rate = &pll_calc_rate,
77 .recalc = &pll_clk_recalc,
78 .set_rate = &pll_clk_set_rate,
79 .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 1},
80 .private_data = &pll1_config,
81};
82
83/* PLL3 48 MHz clock */
84static struct clk pll3_48m_clk = {
85 .flags = ALWAYS_ENABLED,
86 .pclk = &osc_30m_clk,
87 .rate = 48000000,
88};
89
90/* watch dog timer clock */
91static struct clk wdt_clk = {
92 .flags = ALWAYS_ENABLED,
93 .pclk = &osc_30m_clk,
94 .recalc = &follow_parent,
95};
96
97/* clock derived from pll1 clk */
98/* cpu clock */
99static struct clk cpu_clk = {
100 .flags = ALWAYS_ENABLED,
101 .pclk = &pll1_clk,
102 .recalc = &follow_parent,
103};
104
105/* ahb masks structure */
106static struct bus_clk_masks ahb_masks = {
107 .mask = PLL_HCLK_RATIO_MASK,
108 .shift = PLL_HCLK_RATIO_SHIFT,
109};
110
111/* ahb configuration structure */
112static struct bus_clk_config ahb_config = {
113 .reg = CORE_CLK_CFG,
114 .masks = &ahb_masks,
115};
116
117/* ahb rate configuration table, in ascending order of rates */
118struct bus_rate_tbl bus_rtbl[] = {
119 {.div = 3}, /* == parent divided by 4 */
120 {.div = 2}, /* == parent divided by 3 */
121 {.div = 1}, /* == parent divided by 2 */
122 {.div = 0}, /* == parent divided by 1 */
123};
124
125/* ahb clock */
126static struct clk ahb_clk = {
127 .flags = ALWAYS_ENABLED,
128 .pclk = &pll1_clk,
129 .calc_rate = &bus_calc_rate,
130 .recalc = &bus_clk_recalc,
131 .set_rate = &bus_clk_set_rate,
132 .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
133 .private_data = &ahb_config,
134};
135
136/* auxiliary synthesizers masks */
137static struct aux_clk_masks aux_masks = {
138 .eq_sel_mask = AUX_EQ_SEL_MASK,
139 .eq_sel_shift = AUX_EQ_SEL_SHIFT,
140 .eq1_mask = AUX_EQ1_SEL,
141 .eq2_mask = AUX_EQ2_SEL,
142 .xscale_sel_mask = AUX_XSCALE_MASK,
143 .xscale_sel_shift = AUX_XSCALE_SHIFT,
144 .yscale_sel_mask = AUX_YSCALE_MASK,
145 .yscale_sel_shift = AUX_YSCALE_SHIFT,
146};
147
148/* uart configurations */
149static struct aux_clk_config uart_synth_config = {
150 .synth_reg = UART_CLK_SYNT,
151 .masks = &aux_masks,
152};
153
154/* aux rate configuration table, in ascending order of rates */
155struct aux_rate_tbl aux_rtbl[] = {
156 /* For PLL1 = 332 MHz */
157 {.xscale = 1, .yscale = 8, .eq = 1}, /* 41.5 MHz */
158 {.xscale = 1, .yscale = 4, .eq = 1}, /* 83 MHz */
159 {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
160};
161
162/* uart synth clock */
163static struct clk uart_synth_clk = {
164 .en_reg = UART_CLK_SYNT,
165 .en_reg_bit = AUX_SYNT_ENB,
166 .pclk = &pll1_clk,
167 .calc_rate = &aux_calc_rate,
168 .recalc = &aux_clk_recalc,
169 .set_rate = &aux_clk_set_rate,
170 .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2},
171 .private_data = &uart_synth_config,
172};
173
174/* uart parents */
175static struct pclk_info uart_pclk_info[] = {
176 {
177 .pclk = &uart_synth_clk,
178 .pclk_val = AUX_CLK_PLL1_VAL,
179 }, {
180 .pclk = &pll3_48m_clk,
181 .pclk_val = AUX_CLK_PLL3_VAL,
182 },
183};
184
185/* uart parent select structure */
186static struct pclk_sel uart_pclk_sel = {
187 .pclk_info = uart_pclk_info,
188 .pclk_count = ARRAY_SIZE(uart_pclk_info),
189 .pclk_sel_reg = PERIP_CLK_CFG,
190 .pclk_sel_mask = UART_CLK_MASK,
191};
192
193/* uart0 clock */
194static struct clk uart0_clk = {
195 .en_reg = PERIP1_CLK_ENB,
196 .en_reg_bit = UART0_CLK_ENB,
197 .pclk_sel = &uart_pclk_sel,
198 .pclk_sel_shift = UART_CLK_SHIFT,
199 .recalc = &follow_parent,
200};
201
202/* uart1 clock */
203static struct clk uart1_clk = {
204 .en_reg = PERIP1_CLK_ENB,
205 .en_reg_bit = UART1_CLK_ENB,
206 .pclk_sel = &uart_pclk_sel,
207 .pclk_sel_shift = UART_CLK_SHIFT,
208 .recalc = &follow_parent,
209};
210
211/* firda configurations */
212static struct aux_clk_config firda_synth_config = {
213 .synth_reg = FIRDA_CLK_SYNT,
214 .masks = &aux_masks,
215};
216
217/* firda synth clock */
218static struct clk firda_synth_clk = {
219 .en_reg = FIRDA_CLK_SYNT,
220 .en_reg_bit = AUX_SYNT_ENB,
221 .pclk = &pll1_clk,
222 .calc_rate = &aux_calc_rate,
223 .recalc = &aux_clk_recalc,
224 .set_rate = &aux_clk_set_rate,
225 .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2},
226 .private_data = &firda_synth_config,
227};
228
229/* firda parents */
230static struct pclk_info firda_pclk_info[] = {
231 {
232 .pclk = &firda_synth_clk,
233 .pclk_val = AUX_CLK_PLL1_VAL,
234 }, {
235 .pclk = &pll3_48m_clk,
236 .pclk_val = AUX_CLK_PLL3_VAL,
237 },
238};
239
240/* firda parent select structure */
241static struct pclk_sel firda_pclk_sel = {
242 .pclk_info = firda_pclk_info,
243 .pclk_count = ARRAY_SIZE(firda_pclk_info),
244 .pclk_sel_reg = PERIP_CLK_CFG,
245 .pclk_sel_mask = FIRDA_CLK_MASK,
246};
247
248/* firda clock */
249static struct clk firda_clk = {
250 .en_reg = PERIP1_CLK_ENB,
251 .en_reg_bit = FIRDA_CLK_ENB,
252 .pclk_sel = &firda_pclk_sel,
253 .pclk_sel_shift = FIRDA_CLK_SHIFT,
254 .recalc = &follow_parent,
255};
256
257/* clcd configurations */
258static struct aux_clk_config clcd_synth_config = {
259 .synth_reg = CLCD_CLK_SYNT,
260 .masks = &aux_masks,
261};
262
263/* firda synth clock */
264static struct clk clcd_synth_clk = {
265 .en_reg = CLCD_CLK_SYNT,
266 .en_reg_bit = AUX_SYNT_ENB,
267 .pclk = &pll1_clk,
268 .calc_rate = &aux_calc_rate,
269 .recalc = &aux_clk_recalc,
270 .set_rate = &aux_clk_set_rate,
271 .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2},
272 .private_data = &clcd_synth_config,
273};
274
275/* clcd parents */
276static struct pclk_info clcd_pclk_info[] = {
277 {
278 .pclk = &clcd_synth_clk,
279 .pclk_val = AUX_CLK_PLL1_VAL,
280 }, {
281 .pclk = &pll3_48m_clk,
282 .pclk_val = AUX_CLK_PLL3_VAL,
283 },
284};
285
286/* clcd parent select structure */
287static struct pclk_sel clcd_pclk_sel = {
288 .pclk_info = clcd_pclk_info,
289 .pclk_count = ARRAY_SIZE(clcd_pclk_info),
290 .pclk_sel_reg = PERIP_CLK_CFG,
291 .pclk_sel_mask = CLCD_CLK_MASK,
292};
293
294/* clcd clock */
295static struct clk clcd_clk = {
296 .en_reg = PERIP1_CLK_ENB,
297 .en_reg_bit = CLCD_CLK_ENB,
298 .pclk_sel = &clcd_pclk_sel,
299 .pclk_sel_shift = CLCD_CLK_SHIFT,
300 .recalc = &follow_parent,
301};
302
303/* gpt synthesizer masks */
304static struct gpt_clk_masks gpt_masks = {
305 .mscale_sel_mask = GPT_MSCALE_MASK,
306 .mscale_sel_shift = GPT_MSCALE_SHIFT,
307 .nscale_sel_mask = GPT_NSCALE_MASK,
308 .nscale_sel_shift = GPT_NSCALE_SHIFT,
309};
310
311/* gpt rate configuration table, in ascending order of rates */
312struct gpt_rate_tbl gpt_rtbl[] = {
313 /* For pll1 = 332 MHz */
314 {.mscale = 4, .nscale = 0}, /* 41.5 MHz */
315 {.mscale = 2, .nscale = 0}, /* 55.3 MHz */
316 {.mscale = 1, .nscale = 0}, /* 83 MHz */
317};
318
319/* gpt0 synth clk config*/
320static struct gpt_clk_config gpt0_synth_config = {
321 .synth_reg = PRSC1_CLK_CFG,
322 .masks = &gpt_masks,
323};
324
325/* gpt synth clock */
326static struct clk gpt0_synth_clk = {
327 .flags = ALWAYS_ENABLED,
328 .pclk = &pll1_clk,
329 .calc_rate = &gpt_calc_rate,
330 .recalc = &gpt_clk_recalc,
331 .set_rate = &gpt_clk_set_rate,
332 .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
333 .private_data = &gpt0_synth_config,
334};
335
336/* gpt parents */
337static struct pclk_info gpt0_pclk_info[] = {
338 {
339 .pclk = &gpt0_synth_clk,
340 .pclk_val = AUX_CLK_PLL1_VAL,
341 }, {
342 .pclk = &pll3_48m_clk,
343 .pclk_val = AUX_CLK_PLL3_VAL,
344 },
345};
346
347/* gpt parent select structure */
348static struct pclk_sel gpt0_pclk_sel = {
349 .pclk_info = gpt0_pclk_info,
350 .pclk_count = ARRAY_SIZE(gpt0_pclk_info),
351 .pclk_sel_reg = PERIP_CLK_CFG,
352 .pclk_sel_mask = GPT_CLK_MASK,
353};
354
355/* gpt0 ARM1 subsystem timer clock */
356static struct clk gpt0_clk = {
357 .flags = ALWAYS_ENABLED,
358 .pclk_sel = &gpt0_pclk_sel,
359 .pclk_sel_shift = GPT0_CLK_SHIFT,
360 .recalc = &follow_parent,
361};
362
363
364/* Note: gpt0 and gpt1 share same parent clocks */
365/* gpt parent select structure */
366static struct pclk_sel gpt1_pclk_sel = {
367 .pclk_info = gpt0_pclk_info,
368 .pclk_count = ARRAY_SIZE(gpt0_pclk_info),
369 .pclk_sel_reg = PERIP_CLK_CFG,
370 .pclk_sel_mask = GPT_CLK_MASK,
371};
372
373/* gpt1 timer clock */
374static struct clk gpt1_clk = {
375 .flags = ALWAYS_ENABLED,
376 .pclk_sel = &gpt1_pclk_sel,
377 .pclk_sel_shift = GPT1_CLK_SHIFT,
378 .recalc = &follow_parent,
379};
380
381/* gpt2 synth clk config*/
382static struct gpt_clk_config gpt2_synth_config = {
383 .synth_reg = PRSC2_CLK_CFG,
384 .masks = &gpt_masks,
385};
386
387/* gpt synth clock */
388static struct clk gpt2_synth_clk = {
389 .flags = ALWAYS_ENABLED,
390 .pclk = &pll1_clk,
391 .calc_rate = &gpt_calc_rate,
392 .recalc = &gpt_clk_recalc,
393 .set_rate = &gpt_clk_set_rate,
394 .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
395 .private_data = &gpt2_synth_config,
396};
397
398/* gpt parents */
399static struct pclk_info gpt2_pclk_info[] = {
400 {
401 .pclk = &gpt2_synth_clk,
402 .pclk_val = AUX_CLK_PLL1_VAL,
403 }, {
404 .pclk = &pll3_48m_clk,
405 .pclk_val = AUX_CLK_PLL3_VAL,
406 },
407};
408
409/* gpt parent select structure */
410static struct pclk_sel gpt2_pclk_sel = {
411 .pclk_info = gpt2_pclk_info,
412 .pclk_count = ARRAY_SIZE(gpt2_pclk_info),
413 .pclk_sel_reg = PERIP_CLK_CFG,
414 .pclk_sel_mask = GPT_CLK_MASK,
415};
416
417/* gpt2 timer clock */
418static struct clk gpt2_clk = {
419 .flags = ALWAYS_ENABLED,
420 .pclk_sel = &gpt2_pclk_sel,
421 .pclk_sel_shift = GPT2_CLK_SHIFT,
422 .recalc = &follow_parent,
423};
424
425/* gpt3 synth clk config*/
426static struct gpt_clk_config gpt3_synth_config = {
427 .synth_reg = PRSC3_CLK_CFG,
428 .masks = &gpt_masks,
429};
430
431/* gpt synth clock */
432static struct clk gpt3_synth_clk = {
433 .flags = ALWAYS_ENABLED,
434 .pclk = &pll1_clk,
435 .calc_rate = &gpt_calc_rate,
436 .recalc = &gpt_clk_recalc,
437 .set_rate = &gpt_clk_set_rate,
438 .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
439 .private_data = &gpt3_synth_config,
440};
441
442/* gpt parents */
443static struct pclk_info gpt3_pclk_info[] = {
444 {
445 .pclk = &gpt3_synth_clk,
446 .pclk_val = AUX_CLK_PLL1_VAL,
447 }, {
448 .pclk = &pll3_48m_clk,
449 .pclk_val = AUX_CLK_PLL3_VAL,
450 },
451};
452
453/* gpt parent select structure */
454static struct pclk_sel gpt3_pclk_sel = {
455 .pclk_info = gpt3_pclk_info,
456 .pclk_count = ARRAY_SIZE(gpt3_pclk_info),
457 .pclk_sel_reg = PERIP_CLK_CFG,
458 .pclk_sel_mask = GPT_CLK_MASK,
459};
460
461/* gpt3 timer clock */
462static struct clk gpt3_clk = {
463 .flags = ALWAYS_ENABLED,
464 .pclk_sel = &gpt3_pclk_sel,
465 .pclk_sel_shift = GPT3_CLK_SHIFT,
466 .recalc = &follow_parent,
467};
468
469/* clock derived from pll3 clk */
470/* usbh0 clock */
471static struct clk usbh0_clk = {
472 .pclk = &pll3_48m_clk,
473 .en_reg = PERIP1_CLK_ENB,
474 .en_reg_bit = USBH0_CLK_ENB,
475 .recalc = &follow_parent,
476};
477
478/* usbh1 clock */
479static struct clk usbh1_clk = {
480 .pclk = &pll3_48m_clk,
481 .en_reg = PERIP1_CLK_ENB,
482 .en_reg_bit = USBH1_CLK_ENB,
483 .recalc = &follow_parent,
484};
485
486/* usbd clock */
487static struct clk usbd_clk = {
488 .pclk = &pll3_48m_clk,
489 .en_reg = PERIP1_CLK_ENB,
490 .en_reg_bit = USBD_CLK_ENB,
491 .recalc = &follow_parent,
492};
493
494/* clock derived from ahb clk */
495/* apb masks structure */
496static struct bus_clk_masks apb_masks = {
497 .mask = HCLK_PCLK_RATIO_MASK,
498 .shift = HCLK_PCLK_RATIO_SHIFT,
499};
500
501/* apb configuration structure */
502static struct bus_clk_config apb_config = {
503 .reg = CORE_CLK_CFG,
504 .masks = &apb_masks,
505};
506
507/* apb clock */
508static struct clk apb_clk = {
509 .flags = ALWAYS_ENABLED,
510 .pclk = &ahb_clk,
511 .calc_rate = &bus_calc_rate,
512 .recalc = &bus_clk_recalc,
513 .set_rate = &bus_clk_set_rate,
514 .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
515 .private_data = &apb_config,
516};
517
518/* i2c clock */
519static struct clk i2c_clk = {
520 .pclk = &ahb_clk,
521 .en_reg = PERIP1_CLK_ENB,
522 .en_reg_bit = I2C_CLK_ENB,
523 .recalc = &follow_parent,
524};
525
526/* dma clock */
527static struct clk dma_clk = {
528 .pclk = &ahb_clk,
529 .en_reg = PERIP1_CLK_ENB,
530 .en_reg_bit = DMA_CLK_ENB,
531 .recalc = &follow_parent,
532};
533
534/* jpeg clock */
535static struct clk jpeg_clk = {
536 .pclk = &ahb_clk,
537 .en_reg = PERIP1_CLK_ENB,
538 .en_reg_bit = JPEG_CLK_ENB,
539 .recalc = &follow_parent,
540};
541
542/* gmac clock */
543static struct clk gmac_clk = {
544 .pclk = &ahb_clk,
545 .en_reg = PERIP1_CLK_ENB,
546 .en_reg_bit = GMAC_CLK_ENB,
547 .recalc = &follow_parent,
548};
549
550/* smi clock */
551static struct clk smi_clk = {
552 .pclk = &ahb_clk,
553 .en_reg = PERIP1_CLK_ENB,
554 .en_reg_bit = SMI_CLK_ENB,
555 .recalc = &follow_parent,
556};
557
558/* fsmc clock */
559static struct clk fsmc_clk = {
560 .pclk = &ahb_clk,
561 .en_reg = PERIP1_CLK_ENB,
562 .en_reg_bit = FSMC_CLK_ENB,
563 .recalc = &follow_parent,
564};
565
566/* clock derived from apb clk */
567/* adc clock */
568static struct clk adc_clk = {
569 .pclk = &apb_clk,
570 .en_reg = PERIP1_CLK_ENB,
571 .en_reg_bit = ADC_CLK_ENB,
572 .recalc = &follow_parent,
573};
574
575/* ssp0 clock */
576static struct clk ssp0_clk = {
577 .pclk = &apb_clk,
578 .en_reg = PERIP1_CLK_ENB,
579 .en_reg_bit = SSP0_CLK_ENB,
580 .recalc = &follow_parent,
581};
582
583/* ssp1 clock */
584static struct clk ssp1_clk = {
585 .pclk = &apb_clk,
586 .en_reg = PERIP1_CLK_ENB,
587 .en_reg_bit = SSP1_CLK_ENB,
588 .recalc = &follow_parent,
589};
590
591/* ssp2 clock */
592static struct clk ssp2_clk = {
593 .pclk = &apb_clk,
594 .en_reg = PERIP1_CLK_ENB,
595 .en_reg_bit = SSP2_CLK_ENB,
596 .recalc = &follow_parent,
597};
598
599/* gpio0 ARM subsystem clock */
600static struct clk gpio0_clk = {
601 .flags = ALWAYS_ENABLED,
602 .pclk = &apb_clk,
603 .recalc = &follow_parent,
604};
605
606/* gpio1 clock */
607static struct clk gpio1_clk = {
608 .pclk = &apb_clk,
609 .en_reg = PERIP1_CLK_ENB,
610 .en_reg_bit = GPIO1_CLK_ENB,
611 .recalc = &follow_parent,
612};
613
614/* gpio2 clock */
615static struct clk gpio2_clk = {
616 .pclk = &apb_clk,
617 .en_reg = PERIP1_CLK_ENB,
618 .en_reg_bit = GPIO2_CLK_ENB,
619 .recalc = &follow_parent,
620};
621
622static struct clk dummy_apb_pclk;
623
624/* array of all spear 6xx clock lookups */
625static struct clk_lookup spear_clk_lookups[] = {
626 { .con_id = "apb_pclk", .clk = &dummy_apb_pclk},
627 /* root clks */
628 { .con_id = "osc_32k_clk", .clk = &osc_32k_clk},
629 { .con_id = "osc_30m_clk", .clk = &osc_30m_clk},
630 /* clock derived from 32 KHz os clk */
631 { .dev_id = "rtc-spear", .clk = &rtc_clk},
632 /* clock derived from 30 MHz os clk */
633 { .con_id = "pll1_clk", .clk = &pll1_clk},
634 { .con_id = "pll3_48m_clk", .clk = &pll3_48m_clk},
635 { .dev_id = "wdt", .clk = &wdt_clk},
636 /* clock derived from pll1 clk */
637 { .con_id = "cpu_clk", .clk = &cpu_clk},
638 { .con_id = "ahb_clk", .clk = &ahb_clk},
639 { .con_id = "uart_synth_clk", .clk = &uart_synth_clk},
640 { .con_id = "firda_synth_clk", .clk = &firda_synth_clk},
641 { .con_id = "clcd_synth_clk", .clk = &clcd_synth_clk},
642 { .con_id = "gpt0_synth_clk", .clk = &gpt0_synth_clk},
643 { .con_id = "gpt2_synth_clk", .clk = &gpt2_synth_clk},
644 { .con_id = "gpt3_synth_clk", .clk = &gpt3_synth_clk},
645 { .dev_id = "d0000000.serial", .clk = &uart0_clk},
646 { .dev_id = "d0080000.serial", .clk = &uart1_clk},
647 { .dev_id = "firda", .clk = &firda_clk},
648 { .dev_id = "clcd", .clk = &clcd_clk},
649 { .dev_id = "gpt0", .clk = &gpt0_clk},
650 { .dev_id = "gpt1", .clk = &gpt1_clk},
651 { .dev_id = "gpt2", .clk = &gpt2_clk},
652 { .dev_id = "gpt3", .clk = &gpt3_clk},
653 /* clock derived from pll3 clk */
654 { .dev_id = "designware_udc", .clk = &usbd_clk},
655 { .con_id = "usbh.0_clk", .clk = &usbh0_clk},
656 { .con_id = "usbh.1_clk", .clk = &usbh1_clk},
657 /* clock derived from ahb clk */
658 { .con_id = "apb_clk", .clk = &apb_clk},
659 { .dev_id = "d0200000.i2c", .clk = &i2c_clk},
660 { .dev_id = "dma", .clk = &dma_clk},
661 { .dev_id = "jpeg", .clk = &jpeg_clk},
662 { .dev_id = "gmac", .clk = &gmac_clk},
663 { .dev_id = "smi", .clk = &smi_clk},
664 { .dev_id = "fsmc-nand", .clk = &fsmc_clk},
665 /* clock derived from apb clk */
666 { .dev_id = "adc", .clk = &adc_clk},
667 { .dev_id = "ssp-pl022.0", .clk = &ssp0_clk},
668 { .dev_id = "ssp-pl022.1", .clk = &ssp1_clk},
669 { .dev_id = "ssp-pl022.2", .clk = &ssp2_clk},
670 { .dev_id = "f0100000.gpio", .clk = &gpio0_clk},
671 { .dev_id = "fc980000.gpio", .clk = &gpio1_clk},
672 { .dev_id = "d8100000.gpio", .clk = &gpio2_clk},
673};
674
675void __init spear6xx_clk_init(void)
676{
677 int i;
678
679 for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
680 clk_register(&spear_clk_lookups[i]);
681
682 clk_init();
683}
diff --git a/arch/arm/mach-spear6xx/include/mach/misc_regs.h b/arch/arm/mach-spear6xx/include/mach/misc_regs.h
index 68c20a007b0d..633074fddf9a 100644
--- a/arch/arm/mach-spear6xx/include/mach/misc_regs.h
+++ b/arch/arm/mach-spear6xx/include/mach/misc_regs.h
@@ -15,160 +15,8 @@
15#define __MACH_MISC_REGS_H 15#define __MACH_MISC_REGS_H
16 16
17#include <mach/hardware.h> 17#include <mach/hardware.h>
18#include <mach/spear.h>
18 19
19#define MISC_BASE IOMEM(VA_SPEAR6XX_ICM3_MISC_REG_BASE) 20#define MISC_BASE IOMEM(VA_SPEAR6XX_ICM3_MISC_REG_BASE)
20 21
21#define SOC_CFG_CTR (MISC_BASE + 0x000)
22#define DIAG_CFG_CTR (MISC_BASE + 0x004)
23#define PLL1_CTR (MISC_BASE + 0x008)
24#define PLL1_FRQ (MISC_BASE + 0x00C)
25#define PLL1_MOD (MISC_BASE + 0x010)
26#define PLL2_CTR (MISC_BASE + 0x014)
27/* PLL_CTR register masks */
28#define PLL_ENABLE 2
29#define PLL_MODE_SHIFT 4
30#define PLL_MODE_MASK 0x3
31#define PLL_MODE_NORMAL 0
32#define PLL_MODE_FRACTION 1
33#define PLL_MODE_DITH_DSB 2
34#define PLL_MODE_DITH_SSB 3
35
36#define PLL2_FRQ (MISC_BASE + 0x018)
37/* PLL FRQ register masks */
38#define PLL_DIV_N_SHIFT 0
39#define PLL_DIV_N_MASK 0xFF
40#define PLL_DIV_P_SHIFT 8
41#define PLL_DIV_P_MASK 0x7
42#define PLL_NORM_FDBK_M_SHIFT 24
43#define PLL_NORM_FDBK_M_MASK 0xFF
44#define PLL_DITH_FDBK_M_SHIFT 16
45#define PLL_DITH_FDBK_M_MASK 0xFFFF
46
47#define PLL2_MOD (MISC_BASE + 0x01C)
48#define PLL_CLK_CFG (MISC_BASE + 0x020)
49#define CORE_CLK_CFG (MISC_BASE + 0x024)
50/* CORE CLK CFG register masks */
51#define PLL_HCLK_RATIO_SHIFT 10
52#define PLL_HCLK_RATIO_MASK 0x3
53#define HCLK_PCLK_RATIO_SHIFT 8
54#define HCLK_PCLK_RATIO_MASK 0x3
55
56#define PERIP_CLK_CFG (MISC_BASE + 0x028)
57/* PERIP_CLK_CFG register masks */
58#define CLCD_CLK_SHIFT 2
59#define CLCD_CLK_MASK 0x3
60#define UART_CLK_SHIFT 4
61#define UART_CLK_MASK 0x1
62#define FIRDA_CLK_SHIFT 5
63#define FIRDA_CLK_MASK 0x3
64#define GPT0_CLK_SHIFT 8
65#define GPT1_CLK_SHIFT 10
66#define GPT2_CLK_SHIFT 11
67#define GPT3_CLK_SHIFT 12
68#define GPT_CLK_MASK 0x1
69#define AUX_CLK_PLL3_VAL 0
70#define AUX_CLK_PLL1_VAL 1
71
72#define PERIP1_CLK_ENB (MISC_BASE + 0x02C)
73/* PERIP1_CLK_ENB register masks */
74#define UART0_CLK_ENB 3
75#define UART1_CLK_ENB 4
76#define SSP0_CLK_ENB 5
77#define SSP1_CLK_ENB 6
78#define I2C_CLK_ENB 7
79#define JPEG_CLK_ENB 8
80#define FSMC_CLK_ENB 9
81#define FIRDA_CLK_ENB 10
82#define GPT2_CLK_ENB 11
83#define GPT3_CLK_ENB 12
84#define GPIO2_CLK_ENB 13
85#define SSP2_CLK_ENB 14
86#define ADC_CLK_ENB 15
87#define GPT1_CLK_ENB 11
88#define RTC_CLK_ENB 17
89#define GPIO1_CLK_ENB 18
90#define DMA_CLK_ENB 19
91#define SMI_CLK_ENB 21
92#define CLCD_CLK_ENB 22
93#define GMAC_CLK_ENB 23
94#define USBD_CLK_ENB 24
95#define USBH0_CLK_ENB 25
96#define USBH1_CLK_ENB 26
97
98#define SOC_CORE_ID (MISC_BASE + 0x030)
99#define RAS_CLK_ENB (MISC_BASE + 0x034)
100#define PERIP1_SOF_RST (MISC_BASE + 0x038)
101/* PERIP1_SOF_RST register masks */
102#define JPEG_SOF_RST 8
103
104#define SOC_USER_ID (MISC_BASE + 0x03C)
105#define RAS_SOF_RST (MISC_BASE + 0x040)
106#define PRSC1_CLK_CFG (MISC_BASE + 0x044)
107#define PRSC2_CLK_CFG (MISC_BASE + 0x048)
108#define PRSC3_CLK_CFG (MISC_BASE + 0x04C)
109/* gpt synthesizer register masks */
110#define GPT_MSCALE_SHIFT 0
111#define GPT_MSCALE_MASK 0xFFF
112#define GPT_NSCALE_SHIFT 12
113#define GPT_NSCALE_MASK 0xF
114
115#define AMEM_CLK_CFG (MISC_BASE + 0x050)
116#define EXPI_CLK_CFG (MISC_BASE + 0x054)
117#define CLCD_CLK_SYNT (MISC_BASE + 0x05C)
118#define FIRDA_CLK_SYNT (MISC_BASE + 0x060)
119#define UART_CLK_SYNT (MISC_BASE + 0x064)
120#define GMAC_CLK_SYNT (MISC_BASE + 0x068)
121#define RAS1_CLK_SYNT (MISC_BASE + 0x06C)
122#define RAS2_CLK_SYNT (MISC_BASE + 0x070)
123#define RAS3_CLK_SYNT (MISC_BASE + 0x074)
124#define RAS4_CLK_SYNT (MISC_BASE + 0x078)
125/* aux clk synthesiser register masks for irda to ras4 */
126#define AUX_SYNT_ENB 31
127#define AUX_EQ_SEL_SHIFT 30
128#define AUX_EQ_SEL_MASK 1
129#define AUX_EQ1_SEL 0
130#define AUX_EQ2_SEL 1
131#define AUX_XSCALE_SHIFT 16
132#define AUX_XSCALE_MASK 0xFFF
133#define AUX_YSCALE_SHIFT 0
134#define AUX_YSCALE_MASK 0xFFF
135
136#define ICM1_ARB_CFG (MISC_BASE + 0x07C)
137#define ICM2_ARB_CFG (MISC_BASE + 0x080)
138#define ICM3_ARB_CFG (MISC_BASE + 0x084)
139#define ICM4_ARB_CFG (MISC_BASE + 0x088)
140#define ICM5_ARB_CFG (MISC_BASE + 0x08C)
141#define ICM6_ARB_CFG (MISC_BASE + 0x090)
142#define ICM7_ARB_CFG (MISC_BASE + 0x094)
143#define ICM8_ARB_CFG (MISC_BASE + 0x098)
144#define ICM9_ARB_CFG (MISC_BASE + 0x09C)
145#define DMA_CHN_CFG (MISC_BASE + 0x0A0)
146#define USB2_PHY_CFG (MISC_BASE + 0x0A4)
147#define GMAC_CFG_CTR (MISC_BASE + 0x0A8)
148#define EXPI_CFG_CTR (MISC_BASE + 0x0AC)
149#define PRC1_LOCK_CTR (MISC_BASE + 0x0C0)
150#define PRC2_LOCK_CTR (MISC_BASE + 0x0C4)
151#define PRC3_LOCK_CTR (MISC_BASE + 0x0C8)
152#define PRC4_LOCK_CTR (MISC_BASE + 0x0CC)
153#define PRC1_IRQ_CTR (MISC_BASE + 0x0D0)
154#define PRC2_IRQ_CTR (MISC_BASE + 0x0D4)
155#define PRC3_IRQ_CTR (MISC_BASE + 0x0D8)
156#define PRC4_IRQ_CTR (MISC_BASE + 0x0DC)
157#define PWRDOWN_CFG_CTR (MISC_BASE + 0x0E0)
158#define COMPSSTL_1V8_CFG (MISC_BASE + 0x0E4)
159#define COMPSSTL_2V5_CFG (MISC_BASE + 0x0E8)
160#define COMPCOR_3V3_CFG (MISC_BASE + 0x0EC)
161#define SSTLPAD_CFG_CTR (MISC_BASE + 0x0F0)
162#define BIST1_CFG_CTR (MISC_BASE + 0x0F4)
163#define BIST2_CFG_CTR (MISC_BASE + 0x0F8)
164#define BIST3_CFG_CTR (MISC_BASE + 0x0FC)
165#define BIST4_CFG_CTR (MISC_BASE + 0x100)
166#define BIST5_CFG_CTR (MISC_BASE + 0x104)
167#define BIST1_STS_RES (MISC_BASE + 0x108)
168#define BIST2_STS_RES (MISC_BASE + 0x10C)
169#define BIST3_STS_RES (MISC_BASE + 0x110)
170#define BIST4_STS_RES (MISC_BASE + 0x114)
171#define BIST5_STS_RES (MISC_BASE + 0x118)
172#define SYSERR_CFG_CTR (MISC_BASE + 0x11C)
173
174#endif /* __MACH_MISC_REGS_H */ 22#endif /* __MACH_MISC_REGS_H */
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index 2ed8b14c82c8..771e19e3c43c 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -56,9 +56,6 @@ static struct map_desc spear6xx_io_desc[] __initdata = {
56void __init spear6xx_map_io(void) 56void __init spear6xx_map_io(void)
57{ 57{
58 iotable_init(spear6xx_io_desc, ARRAY_SIZE(spear6xx_io_desc)); 58 iotable_init(spear6xx_io_desc, ARRAY_SIZE(spear6xx_io_desc));
59
60 /* This will initialize clock framework */
61 spear6xx_clk_init();
62} 59}
63 60
64static void __init spear6xx_timer_init(void) 61static void __init spear6xx_timer_init(void)
@@ -66,6 +63,8 @@ static void __init spear6xx_timer_init(void)
66 char pclk_name[] = "pll3_48m_clk"; 63 char pclk_name[] = "pll3_48m_clk";
67 struct clk *gpt_clk, *pclk; 64 struct clk *gpt_clk, *pclk;
68 65
66 spear6xx_clk_init();
67
69 /* get the system timer clock */ 68 /* get the system timer clock */
70 gpt_clk = clk_get_sys("gpt0", NULL); 69 gpt_clk = clk_get_sys("gpt0", NULL);
71 if (IS_ERR(gpt_clk)) { 70 if (IS_ERR(gpt_clk)) {
diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile
index e0f2e5b9530c..8c0cb6a965a3 100644
--- a/arch/arm/plat-spear/Makefile
+++ b/arch/arm/plat-spear/Makefile
@@ -3,6 +3,6 @@
3# 3#
4 4
5# Common support 5# Common support
6obj-y := clock.o restart.o time.o 6obj-y := restart.o time.o
7 7
8obj-$(CONFIG_ARCH_SPEAR3XX) += shirq.o padmux.o 8obj-$(CONFIG_ARCH_SPEAR3XX) += shirq.o padmux.o
diff --git a/arch/arm/plat-spear/clock.c b/arch/arm/plat-spear/clock.c
deleted file mode 100644
index 67dd00381ea6..000000000000
--- a/arch/arm/plat-spear/clock.c
+++ /dev/null
@@ -1,1005 +0,0 @@
1/*
2 * arch/arm/plat-spear/clock.c
3 *
4 * Clock framework for SPEAr platform
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/bug.h>
15#include <linux/clk.h>
16#include <linux/debugfs.h>
17#include <linux/err.h>
18#include <linux/io.h>
19#include <linux/list.h>
20#include <linux/module.h>
21#include <linux/spinlock.h>
22#include <plat/clock.h>
23
24static DEFINE_SPINLOCK(clocks_lock);
25static LIST_HEAD(root_clks);
26#ifdef CONFIG_DEBUG_FS
27static LIST_HEAD(clocks);
28#endif
29
30static void propagate_rate(struct clk *, int on_init);
31#ifdef CONFIG_DEBUG_FS
32static int clk_debugfs_reparent(struct clk *);
33#endif
34
35static int generic_clk_enable(struct clk *clk)
36{
37 unsigned int val;
38
39 if (!clk->en_reg)
40 return -EFAULT;
41
42 val = readl(clk->en_reg);
43 if (unlikely(clk->flags & RESET_TO_ENABLE))
44 val &= ~(1 << clk->en_reg_bit);
45 else
46 val |= 1 << clk->en_reg_bit;
47
48 writel(val, clk->en_reg);
49
50 return 0;
51}
52
53static void generic_clk_disable(struct clk *clk)
54{
55 unsigned int val;
56
57 if (!clk->en_reg)
58 return;
59
60 val = readl(clk->en_reg);
61 if (unlikely(clk->flags & RESET_TO_ENABLE))
62 val |= 1 << clk->en_reg_bit;
63 else
64 val &= ~(1 << clk->en_reg_bit);
65
66 writel(val, clk->en_reg);
67}
68
69/* generic clk ops */
70static struct clkops generic_clkops = {
71 .enable = generic_clk_enable,
72 .disable = generic_clk_disable,
73};
74
75/* returns current programmed clocks clock info structure */
76static struct pclk_info *pclk_info_get(struct clk *clk)
77{
78 unsigned int val, i;
79 struct pclk_info *info = NULL;
80
81 val = (readl(clk->pclk_sel->pclk_sel_reg) >> clk->pclk_sel_shift)
82 & clk->pclk_sel->pclk_sel_mask;
83
84 for (i = 0; i < clk->pclk_sel->pclk_count; i++) {
85 if (clk->pclk_sel->pclk_info[i].pclk_val == val)
86 info = &clk->pclk_sel->pclk_info[i];
87 }
88
89 return info;
90}
91
92/*
93 * Set Update pclk, and pclk_info of clk and add clock sibling node to current
94 * parents children list
95 */
96static void clk_reparent(struct clk *clk, struct pclk_info *pclk_info)
97{
98 unsigned long flags;
99
100 spin_lock_irqsave(&clocks_lock, flags);
101 list_del(&clk->sibling);
102 list_add(&clk->sibling, &pclk_info->pclk->children);
103
104 clk->pclk = pclk_info->pclk;
105 spin_unlock_irqrestore(&clocks_lock, flags);
106
107#ifdef CONFIG_DEBUG_FS
108 clk_debugfs_reparent(clk);
109#endif
110}
111
112static void do_clk_disable(struct clk *clk)
113{
114 if (!clk)
115 return;
116
117 if (!clk->usage_count) {
118 WARN_ON(1);
119 return;
120 }
121
122 clk->usage_count--;
123
124 if (clk->usage_count == 0) {
125 /*
126 * Surely, there are no active childrens or direct users
127 * of this clock
128 */
129 if (clk->pclk)
130 do_clk_disable(clk->pclk);
131
132 if (clk->ops && clk->ops->disable)
133 clk->ops->disable(clk);
134 }
135}
136
137static int do_clk_enable(struct clk *clk)
138{
139 int ret = 0;
140
141 if (!clk)
142 return -EFAULT;
143
144 if (clk->usage_count == 0) {
145 if (clk->pclk) {
146 ret = do_clk_enable(clk->pclk);
147 if (ret)
148 goto err;
149 }
150 if (clk->ops && clk->ops->enable) {
151 ret = clk->ops->enable(clk);
152 if (ret) {
153 if (clk->pclk)
154 do_clk_disable(clk->pclk);
155 goto err;
156 }
157 }
158 /*
159 * Since the clock is going to be used for the first
160 * time please reclac
161 */
162 if (clk->recalc) {
163 ret = clk->recalc(clk);
164 if (ret)
165 goto err;
166 }
167 }
168 clk->usage_count++;
169err:
170 return ret;
171}
172
173/*
174 * clk_enable - inform the system when the clock source should be running.
175 * @clk: clock source
176 *
177 * If the clock can not be enabled/disabled, this should return success.
178 *
179 * Returns success (0) or negative errno.
180 */
181int clk_enable(struct clk *clk)
182{
183 unsigned long flags;
184 int ret = 0;
185
186 spin_lock_irqsave(&clocks_lock, flags);
187 ret = do_clk_enable(clk);
188 spin_unlock_irqrestore(&clocks_lock, flags);
189 return ret;
190}
191EXPORT_SYMBOL(clk_enable);
192
193/*
194 * clk_disable - inform the system when the clock source is no longer required.
195 * @clk: clock source
196 *
197 * Inform the system that a clock source is no longer required by
198 * a driver and may be shut down.
199 *
200 * Implementation detail: if the clock source is shared between
201 * multiple drivers, clk_enable() calls must be balanced by the
202 * same number of clk_disable() calls for the clock source to be
203 * disabled.
204 */
205void clk_disable(struct clk *clk)
206{
207 unsigned long flags;
208
209 spin_lock_irqsave(&clocks_lock, flags);
210 do_clk_disable(clk);
211 spin_unlock_irqrestore(&clocks_lock, flags);
212}
213EXPORT_SYMBOL(clk_disable);
214
215/**
216 * clk_get_rate - obtain the current clock rate (in Hz) for a clock source.
217 * This is only valid once the clock source has been enabled.
218 * @clk: clock source
219 */
220unsigned long clk_get_rate(struct clk *clk)
221{
222 unsigned long flags, rate;
223
224 spin_lock_irqsave(&clocks_lock, flags);
225 rate = clk->rate;
226 spin_unlock_irqrestore(&clocks_lock, flags);
227
228 return rate;
229}
230EXPORT_SYMBOL(clk_get_rate);
231
232/**
233 * clk_set_parent - set the parent clock source for this clock
234 * @clk: clock source
235 * @parent: parent clock source
236 *
237 * Returns success (0) or negative errno.
238 */
239int clk_set_parent(struct clk *clk, struct clk *parent)
240{
241 int i, found = 0, val = 0;
242 unsigned long flags;
243
244 if (!clk || !parent)
245 return -EFAULT;
246 if (clk->pclk == parent)
247 return 0;
248 if (!clk->pclk_sel)
249 return -EPERM;
250
251 /* check if requested parent is in clk parent list */
252 for (i = 0; i < clk->pclk_sel->pclk_count; i++) {
253 if (clk->pclk_sel->pclk_info[i].pclk == parent) {
254 found = 1;
255 break;
256 }
257 }
258
259 if (!found)
260 return -EINVAL;
261
262 spin_lock_irqsave(&clocks_lock, flags);
263 /* reflect parent change in hardware */
264 val = readl(clk->pclk_sel->pclk_sel_reg);
265 val &= ~(clk->pclk_sel->pclk_sel_mask << clk->pclk_sel_shift);
266 val |= clk->pclk_sel->pclk_info[i].pclk_val << clk->pclk_sel_shift;
267 writel(val, clk->pclk_sel->pclk_sel_reg);
268 spin_unlock_irqrestore(&clocks_lock, flags);
269
270 /* reflect parent change in software */
271 clk_reparent(clk, &clk->pclk_sel->pclk_info[i]);
272
273 propagate_rate(clk, 0);
274 return 0;
275}
276EXPORT_SYMBOL(clk_set_parent);
277
278/**
279 * clk_set_rate - set the clock rate for a clock source
280 * @clk: clock source
281 * @rate: desired clock rate in Hz
282 *
283 * Returns success (0) or negative errno.
284 */
285int clk_set_rate(struct clk *clk, unsigned long rate)
286{
287 unsigned long flags;
288 int ret = -EINVAL;
289
290 if (!clk || !rate)
291 return -EFAULT;
292
293 if (clk->set_rate) {
294 spin_lock_irqsave(&clocks_lock, flags);
295 ret = clk->set_rate(clk, rate);
296 if (!ret)
297 /* if successful -> propagate */
298 propagate_rate(clk, 0);
299 spin_unlock_irqrestore(&clocks_lock, flags);
300 } else if (clk->pclk) {
301 u32 mult = clk->div_factor ? clk->div_factor : 1;
302 ret = clk_set_rate(clk->pclk, mult * rate);
303 }
304
305 return ret;
306}
307EXPORT_SYMBOL(clk_set_rate);
308
309/* registers clock in platform clock framework */
310void clk_register(struct clk_lookup *cl)
311{
312 struct clk *clk;
313 unsigned long flags;
314
315 if (!cl || !cl->clk)
316 return;
317 clk = cl->clk;
318
319 spin_lock_irqsave(&clocks_lock, flags);
320
321 INIT_LIST_HEAD(&clk->children);
322 if (clk->flags & ALWAYS_ENABLED)
323 clk->ops = NULL;
324 else if (!clk->ops)
325 clk->ops = &generic_clkops;
326
327 /* root clock don't have any parents */
328 if (!clk->pclk && !clk->pclk_sel) {
329 list_add(&clk->sibling, &root_clks);
330 } else if (clk->pclk && !clk->pclk_sel) {
331 /* add clocks with only one parent to parent's children list */
332 list_add(&clk->sibling, &clk->pclk->children);
333 } else {
334 /* clocks with more than one parent */
335 struct pclk_info *pclk_info;
336
337 pclk_info = pclk_info_get(clk);
338 if (!pclk_info) {
339 pr_err("CLKDEV: invalid pclk info of clk with"
340 " %s dev_id and %s con_id\n",
341 cl->dev_id, cl->con_id);
342 } else {
343 clk->pclk = pclk_info->pclk;
344 list_add(&clk->sibling, &pclk_info->pclk->children);
345 }
346 }
347
348 spin_unlock_irqrestore(&clocks_lock, flags);
349
350 /* debugfs specific */
351#ifdef CONFIG_DEBUG_FS
352 list_add(&clk->node, &clocks);
353 clk->cl = cl;
354#endif
355
356 /* add clock to arm clockdev framework */
357 clkdev_add(cl);
358}
359
360/**
361 * propagate_rate - recalculate and propagate all clocks to children
362 * @pclk: parent clock required to be propogated
363 * @on_init: flag for enabling clocks which are ENABLED_ON_INIT.
364 *
365 * Recalculates all children clocks
366 */
367void propagate_rate(struct clk *pclk, int on_init)
368{
369 struct clk *clk, *_temp;
370 int ret = 0;
371
372 list_for_each_entry_safe(clk, _temp, &pclk->children, sibling) {
373 if (clk->recalc) {
374 ret = clk->recalc(clk);
375 /*
376 * recalc will return error if clk out is not programmed
377 * In this case configure default rate.
378 */
379 if (ret && clk->set_rate)
380 clk->set_rate(clk, 0);
381 }
382 propagate_rate(clk, on_init);
383
384 if (!on_init)
385 continue;
386
387 /* Enable clks enabled on init, in software view */
388 if (clk->flags & ENABLED_ON_INIT)
389 do_clk_enable(clk);
390 }
391}
392
393/**
394 * round_rate_index - return closest programmable rate index in rate_config tbl
395 * @clk: ptr to clock structure
396 * @drate: desired rate
397 * @rate: final rate will be returned in this variable only.
398 *
399 * Finds index in rate_config for highest clk rate which is less than
400 * requested rate. If there is no clk rate lesser than requested rate then
401 * -EINVAL is returned. This routine assumes that rate_config is written
402 * in incrementing order of clk rates.
403 * If drate passed is zero then default rate is programmed.
404 */
405static int
406round_rate_index(struct clk *clk, unsigned long drate, unsigned long *rate)
407{
408 unsigned long tmp = 0, prev_rate = 0;
409 int index;
410
411 if (!clk->calc_rate)
412 return -EFAULT;
413
414 if (!drate)
415 return -EINVAL;
416
417 /*
418 * This loops ends on two conditions:
419 * - as soon as clk is found with rate greater than requested rate.
420 * - if all clks in rate_config are smaller than requested rate.
421 */
422 for (index = 0; index < clk->rate_config.count; index++) {
423 prev_rate = tmp;
424 tmp = clk->calc_rate(clk, index);
425 if (drate < tmp) {
426 index--;
427 break;
428 }
429 }
430 /* return if can't find suitable clock */
431 if (index < 0) {
432 index = -EINVAL;
433 *rate = 0;
434 } else if (index == clk->rate_config.count) {
435 /* program with highest clk rate possible */
436 index = clk->rate_config.count - 1;
437 *rate = tmp;
438 } else
439 *rate = prev_rate;
440
441 return index;
442}
443
444/**
445 * clk_round_rate - adjust a rate to the exact rate a clock can provide
446 * @clk: clock source
447 * @rate: desired clock rate in Hz
448 *
449 * Returns rounded clock rate in Hz, or negative errno.
450 */
451long clk_round_rate(struct clk *clk, unsigned long drate)
452{
453 long rate = 0;
454 int index;
455
456 /*
457 * propagate call to parent who supports calc_rate. Similar approach is
458 * used in clk_set_rate.
459 */
460 if (!clk->calc_rate) {
461 u32 mult;
462 if (!clk->pclk)
463 return clk->rate;
464
465 mult = clk->div_factor ? clk->div_factor : 1;
466 return clk_round_rate(clk->pclk, mult * drate) / mult;
467 }
468
469 index = round_rate_index(clk, drate, &rate);
470 if (index >= 0)
471 return rate;
472 else
473 return index;
474}
475EXPORT_SYMBOL(clk_round_rate);
476
477/*All below functions are called with lock held */
478
479/*
480 * Calculates pll clk rate for specific value of mode, m, n and p
481 *
482 * In normal mode
483 * rate = (2 * M[15:8] * Fin)/(N * 2^P)
484 *
485 * In Dithered mode
486 * rate = (2 * M[15:0] * Fin)/(256 * N * 2^P)
487 */
488unsigned long pll_calc_rate(struct clk *clk, int index)
489{
490 unsigned long rate = clk->pclk->rate;
491 struct pll_rate_tbl *tbls = clk->rate_config.tbls;
492 unsigned int mode;
493
494 mode = tbls[index].mode ? 256 : 1;
495 return (((2 * rate / 10000) * tbls[index].m) /
496 (mode * tbls[index].n * (1 << tbls[index].p))) * 10000;
497}
498
499/*
500 * calculates current programmed rate of pll1
501 *
502 * In normal mode
503 * rate = (2 * M[15:8] * Fin)/(N * 2^P)
504 *
505 * In Dithered mode
506 * rate = (2 * M[15:0] * Fin)/(256 * N * 2^P)
507 */
508int pll_clk_recalc(struct clk *clk)
509{
510 struct pll_clk_config *config = clk->private_data;
511 unsigned int num = 2, den = 0, val, mode = 0;
512
513 mode = (readl(config->mode_reg) >> config->masks->mode_shift) &
514 config->masks->mode_mask;
515
516 val = readl(config->cfg_reg);
517 /* calculate denominator */
518 den = (val >> config->masks->div_p_shift) & config->masks->div_p_mask;
519 den = 1 << den;
520 den *= (val >> config->masks->div_n_shift) & config->masks->div_n_mask;
521
522 /* calculate numerator & denominator */
523 if (!mode) {
524 /* Normal mode */
525 num *= (val >> config->masks->norm_fdbk_m_shift) &
526 config->masks->norm_fdbk_m_mask;
527 } else {
528 /* Dithered mode */
529 num *= (val >> config->masks->dith_fdbk_m_shift) &
530 config->masks->dith_fdbk_m_mask;
531 den *= 256;
532 }
533
534 if (!den)
535 return -EINVAL;
536
537 clk->rate = (((clk->pclk->rate/10000) * num) / den) * 10000;
538 return 0;
539}
540
541/*
542 * Configures new clock rate of pll
543 */
544int pll_clk_set_rate(struct clk *clk, unsigned long desired_rate)
545{
546 struct pll_rate_tbl *tbls = clk->rate_config.tbls;
547 struct pll_clk_config *config = clk->private_data;
548 unsigned long val, rate;
549 int i;
550
551 i = round_rate_index(clk, desired_rate, &rate);
552 if (i < 0)
553 return i;
554
555 val = readl(config->mode_reg) &
556 ~(config->masks->mode_mask << config->masks->mode_shift);
557 val |= (tbls[i].mode & config->masks->mode_mask) <<
558 config->masks->mode_shift;
559 writel(val, config->mode_reg);
560
561 val = readl(config->cfg_reg) &
562 ~(config->masks->div_p_mask << config->masks->div_p_shift);
563 val |= (tbls[i].p & config->masks->div_p_mask) <<
564 config->masks->div_p_shift;
565 val &= ~(config->masks->div_n_mask << config->masks->div_n_shift);
566 val |= (tbls[i].n & config->masks->div_n_mask) <<
567 config->masks->div_n_shift;
568 val &= ~(config->masks->dith_fdbk_m_mask <<
569 config->masks->dith_fdbk_m_shift);
570 if (tbls[i].mode)
571 val |= (tbls[i].m & config->masks->dith_fdbk_m_mask) <<
572 config->masks->dith_fdbk_m_shift;
573 else
574 val |= (tbls[i].m & config->masks->norm_fdbk_m_mask) <<
575 config->masks->norm_fdbk_m_shift;
576
577 writel(val, config->cfg_reg);
578
579 clk->rate = rate;
580
581 return 0;
582}
583
584/*
585 * Calculates ahb, apb clk rate for specific value of div
586 */
587unsigned long bus_calc_rate(struct clk *clk, int index)
588{
589 unsigned long rate = clk->pclk->rate;
590 struct bus_rate_tbl *tbls = clk->rate_config.tbls;
591
592 return rate / (tbls[index].div + 1);
593}
594
595/* calculates current programmed rate of ahb or apb bus */
596int bus_clk_recalc(struct clk *clk)
597{
598 struct bus_clk_config *config = clk->private_data;
599 unsigned int div;
600
601 div = ((readl(config->reg) >> config->masks->shift) &
602 config->masks->mask) + 1;
603
604 if (!div)
605 return -EINVAL;
606
607 clk->rate = (unsigned long)clk->pclk->rate / div;
608 return 0;
609}
610
611/* Configures new clock rate of AHB OR APB bus */
612int bus_clk_set_rate(struct clk *clk, unsigned long desired_rate)
613{
614 struct bus_rate_tbl *tbls = clk->rate_config.tbls;
615 struct bus_clk_config *config = clk->private_data;
616 unsigned long val, rate;
617 int i;
618
619 i = round_rate_index(clk, desired_rate, &rate);
620 if (i < 0)
621 return i;
622
623 val = readl(config->reg) &
624 ~(config->masks->mask << config->masks->shift);
625 val |= (tbls[i].div & config->masks->mask) << config->masks->shift;
626 writel(val, config->reg);
627
628 clk->rate = rate;
629
630 return 0;
631}
632
633/*
634 * gives rate for different values of eq, x and y
635 *
636 * Fout from synthesizer can be given from two equations:
637 * Fout1 = (Fin * X/Y)/2 EQ1
638 * Fout2 = Fin * X/Y EQ2
639 */
640unsigned long aux_calc_rate(struct clk *clk, int index)
641{
642 unsigned long rate = clk->pclk->rate;
643 struct aux_rate_tbl *tbls = clk->rate_config.tbls;
644 u8 eq = tbls[index].eq ? 1 : 2;
645
646 return (((rate/10000) * tbls[index].xscale) /
647 (tbls[index].yscale * eq)) * 10000;
648}
649
650/*
651 * calculates current programmed rate of auxiliary synthesizers
652 * used by: UART, FIRDA
653 *
654 * Fout from synthesizer can be given from two equations:
655 * Fout1 = (Fin * X/Y)/2
656 * Fout2 = Fin * X/Y
657 *
658 * Selection of eqn 1 or 2 is programmed in register
659 */
660int aux_clk_recalc(struct clk *clk)
661{
662 struct aux_clk_config *config = clk->private_data;
663 unsigned int num = 1, den = 1, val, eqn;
664
665 val = readl(config->synth_reg);
666
667 eqn = (val >> config->masks->eq_sel_shift) &
668 config->masks->eq_sel_mask;
669 if (eqn == config->masks->eq1_mask)
670 den *= 2;
671
672 /* calculate numerator */
673 num = (val >> config->masks->xscale_sel_shift) &
674 config->masks->xscale_sel_mask;
675
676 /* calculate denominator */
677 den *= (val >> config->masks->yscale_sel_shift) &
678 config->masks->yscale_sel_mask;
679
680 if (!den)
681 return -EINVAL;
682
683 clk->rate = (((clk->pclk->rate/10000) * num) / den) * 10000;
684 return 0;
685}
686
687/* Configures new clock rate of auxiliary synthesizers used by: UART, FIRDA*/
688int aux_clk_set_rate(struct clk *clk, unsigned long desired_rate)
689{
690 struct aux_rate_tbl *tbls = clk->rate_config.tbls;
691 struct aux_clk_config *config = clk->private_data;
692 unsigned long val, rate;
693 int i;
694
695 i = round_rate_index(clk, desired_rate, &rate);
696 if (i < 0)
697 return i;
698
699 val = readl(config->synth_reg) &
700 ~(config->masks->eq_sel_mask << config->masks->eq_sel_shift);
701 val |= (tbls[i].eq & config->masks->eq_sel_mask) <<
702 config->masks->eq_sel_shift;
703 val &= ~(config->masks->xscale_sel_mask <<
704 config->masks->xscale_sel_shift);
705 val |= (tbls[i].xscale & config->masks->xscale_sel_mask) <<
706 config->masks->xscale_sel_shift;
707 val &= ~(config->masks->yscale_sel_mask <<
708 config->masks->yscale_sel_shift);
709 val |= (tbls[i].yscale & config->masks->yscale_sel_mask) <<
710 config->masks->yscale_sel_shift;
711 writel(val, config->synth_reg);
712
713 clk->rate = rate;
714
715 return 0;
716}
717
718/*
719 * Calculates gpt clk rate for different values of mscale and nscale
720 *
721 * Fout= Fin/((2 ^ (N+1)) * (M+1))
722 */
723unsigned long gpt_calc_rate(struct clk *clk, int index)
724{
725 unsigned long rate = clk->pclk->rate;
726 struct gpt_rate_tbl *tbls = clk->rate_config.tbls;
727
728 return rate / ((1 << (tbls[index].nscale + 1)) *
729 (tbls[index].mscale + 1));
730}
731
732/*
733 * calculates current programmed rate of gpt synthesizers
734 * Fout from synthesizer can be given from below equations:
735 * Fout= Fin/((2 ^ (N+1)) * (M+1))
736 */
737int gpt_clk_recalc(struct clk *clk)
738{
739 struct gpt_clk_config *config = clk->private_data;
740 unsigned int div = 1, val;
741
742 val = readl(config->synth_reg);
743 div += (val >> config->masks->mscale_sel_shift) &
744 config->masks->mscale_sel_mask;
745 div *= 1 << (((val >> config->masks->nscale_sel_shift) &
746 config->masks->nscale_sel_mask) + 1);
747
748 if (!div)
749 return -EINVAL;
750
751 clk->rate = (unsigned long)clk->pclk->rate / div;
752 return 0;
753}
754
755/* Configures new clock rate of gptiliary synthesizers used by: UART, FIRDA*/
756int gpt_clk_set_rate(struct clk *clk, unsigned long desired_rate)
757{
758 struct gpt_rate_tbl *tbls = clk->rate_config.tbls;
759 struct gpt_clk_config *config = clk->private_data;
760 unsigned long val, rate;
761 int i;
762
763 i = round_rate_index(clk, desired_rate, &rate);
764 if (i < 0)
765 return i;
766
767 val = readl(config->synth_reg) & ~(config->masks->mscale_sel_mask <<
768 config->masks->mscale_sel_shift);
769 val |= (tbls[i].mscale & config->masks->mscale_sel_mask) <<
770 config->masks->mscale_sel_shift;
771 val &= ~(config->masks->nscale_sel_mask <<
772 config->masks->nscale_sel_shift);
773 val |= (tbls[i].nscale & config->masks->nscale_sel_mask) <<
774 config->masks->nscale_sel_shift;
775 writel(val, config->synth_reg);
776
777 clk->rate = rate;
778
779 return 0;
780}
781
782/*
783 * Calculates clcd clk rate for different values of div
784 *
785 * Fout from synthesizer can be given from below equation:
786 * Fout= Fin/2*div (division factor)
787 * div is 17 bits:-
788 * 0-13 (fractional part)
789 * 14-16 (integer part)
790 * To calculate Fout we left shift val by 14 bits and divide Fin by
791 * complete div (including fractional part) and then right shift the
792 * result by 14 places.
793 */
794unsigned long clcd_calc_rate(struct clk *clk, int index)
795{
796 unsigned long rate = clk->pclk->rate;
797 struct clcd_rate_tbl *tbls = clk->rate_config.tbls;
798
799 rate /= 1000;
800 rate <<= 12;
801 rate /= (2 * tbls[index].div);
802 rate >>= 12;
803 rate *= 1000;
804
805 return rate;
806}
807
808/*
809 * calculates current programmed rate of clcd synthesizer
810 * Fout from synthesizer can be given from below equation:
811 * Fout= Fin/2*div (division factor)
812 * div is 17 bits:-
813 * 0-13 (fractional part)
814 * 14-16 (integer part)
815 * To calculate Fout we left shift val by 14 bits and divide Fin by
816 * complete div (including fractional part) and then right shift the
817 * result by 14 places.
818 */
819int clcd_clk_recalc(struct clk *clk)
820{
821 struct clcd_clk_config *config = clk->private_data;
822 unsigned int div = 1;
823 unsigned long prate;
824 unsigned int val;
825
826 val = readl(config->synth_reg);
827 div = (val >> config->masks->div_factor_shift) &
828 config->masks->div_factor_mask;
829
830 if (!div)
831 return -EINVAL;
832
833 prate = clk->pclk->rate / 1000; /* first level division, make it KHz */
834
835 clk->rate = (((unsigned long)prate << 12) / (2 * div)) >> 12;
836 clk->rate *= 1000;
837 return 0;
838}
839
840/* Configures new clock rate of auxiliary synthesizers used by: UART, FIRDA*/
841int clcd_clk_set_rate(struct clk *clk, unsigned long desired_rate)
842{
843 struct clcd_rate_tbl *tbls = clk->rate_config.tbls;
844 struct clcd_clk_config *config = clk->private_data;
845 unsigned long val, rate;
846 int i;
847
848 i = round_rate_index(clk, desired_rate, &rate);
849 if (i < 0)
850 return i;
851
852 val = readl(config->synth_reg) & ~(config->masks->div_factor_mask <<
853 config->masks->div_factor_shift);
854 val |= (tbls[i].div & config->masks->div_factor_mask) <<
855 config->masks->div_factor_shift;
856 writel(val, config->synth_reg);
857
858 clk->rate = rate;
859
860 return 0;
861}
862
863/*
864 * Used for clocks that always have value as the parent clock divided by a
865 * fixed divisor
866 */
867int follow_parent(struct clk *clk)
868{
869 unsigned int div_factor = (clk->div_factor < 1) ? 1 : clk->div_factor;
870
871 clk->rate = clk->pclk->rate/div_factor;
872 return 0;
873}
874
875/**
876 * recalc_root_clocks - recalculate and propagate all root clocks
877 *
878 * Recalculates all root clocks (clocks with no parent), which if the
879 * clock's .recalc is set correctly, should also propagate their rates.
880 */
881void recalc_root_clocks(void)
882{
883 struct clk *pclk;
884 unsigned long flags;
885 int ret = 0;
886
887 spin_lock_irqsave(&clocks_lock, flags);
888 list_for_each_entry(pclk, &root_clks, sibling) {
889 if (pclk->recalc) {
890 ret = pclk->recalc(pclk);
891 /*
892 * recalc will return error if clk out is not programmed
893 * In this case configure default clock.
894 */
895 if (ret && pclk->set_rate)
896 pclk->set_rate(pclk, 0);
897 }
898 propagate_rate(pclk, 1);
899 /* Enable clks enabled on init, in software view */
900 if (pclk->flags & ENABLED_ON_INIT)
901 do_clk_enable(pclk);
902 }
903 spin_unlock_irqrestore(&clocks_lock, flags);
904}
905
906void __init clk_init(void)
907{
908 recalc_root_clocks();
909}
910
911#ifdef CONFIG_DEBUG_FS
912/*
913 * debugfs support to trace clock tree hierarchy and attributes
914 */
915static struct dentry *clk_debugfs_root;
916static int clk_debugfs_register_one(struct clk *c)
917{
918 int err;
919 struct dentry *d;
920 struct clk *pa = c->pclk;
921 char s[255];
922 char *p = s;
923
924 if (c) {
925 if (c->cl->con_id)
926 p += sprintf(p, "%s", c->cl->con_id);
927 if (c->cl->dev_id)
928 p += sprintf(p, "%s", c->cl->dev_id);
929 }
930 d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root);
931 if (!d)
932 return -ENOMEM;
933 c->dent = d;
934
935 d = debugfs_create_u32("usage_count", S_IRUGO, c->dent,
936 (u32 *)&c->usage_count);
937 if (!d) {
938 err = -ENOMEM;
939 goto err_out;
940 }
941 d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
942 if (!d) {
943 err = -ENOMEM;
944 goto err_out;
945 }
946 d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags);
947 if (!d) {
948 err = -ENOMEM;
949 goto err_out;
950 }
951 return 0;
952
953err_out:
954 debugfs_remove_recursive(c->dent);
955 return err;
956}
957
958static int clk_debugfs_register(struct clk *c)
959{
960 int err;
961 struct clk *pa = c->pclk;
962
963 if (pa && !pa->dent) {
964 err = clk_debugfs_register(pa);
965 if (err)
966 return err;
967 }
968
969 if (!c->dent) {
970 err = clk_debugfs_register_one(c);
971 if (err)
972 return err;
973 }
974 return 0;
975}
976
977static int __init clk_debugfs_init(void)
978{
979 struct clk *c;
980 struct dentry *d;
981 int err;
982
983 d = debugfs_create_dir("clock", NULL);
984 if (!d)
985 return -ENOMEM;
986 clk_debugfs_root = d;
987
988 list_for_each_entry(c, &clocks, node) {
989 err = clk_debugfs_register(c);
990 if (err)
991 goto err_out;
992 }
993 return 0;
994err_out:
995 debugfs_remove_recursive(clk_debugfs_root);
996 return err;
997}
998late_initcall(clk_debugfs_init);
999
1000static int clk_debugfs_reparent(struct clk *c)
1001{
1002 debugfs_remove(c->dent);
1003 return clk_debugfs_register_one(c);
1004}
1005#endif /* CONFIG_DEBUG_FS */
diff --git a/arch/arm/plat-spear/include/plat/clock.h b/arch/arm/plat-spear/include/plat/clock.h
deleted file mode 100644
index 0062bafef12d..000000000000
--- a/arch/arm/plat-spear/include/plat/clock.h
+++ /dev/null
@@ -1,249 +0,0 @@
1/*
2 * arch/arm/plat-spear/include/plat/clock.h
3 *
4 * Clock framework definitions for SPEAr platform
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __PLAT_CLOCK_H
15#define __PLAT_CLOCK_H
16
17#include <linux/list.h>
18#include <linux/clkdev.h>
19#include <linux/types.h>
20
21/* clk structure flags */
22#define ALWAYS_ENABLED (1 << 0) /* clock always enabled */
23#define RESET_TO_ENABLE (1 << 1) /* reset register bit to enable clk */
24#define ENABLED_ON_INIT (1 << 2) /* clocks enabled at init */
25
26/**
27 * struct clkops - clock operations
28 * @enable: pointer to clock enable function
29 * @disable: pointer to clock disable function
30 */
31struct clkops {
32 int (*enable) (struct clk *);
33 void (*disable) (struct clk *);
34};
35
36/**
37 * struct pclk_info - parents info
38 * @pclk: pointer to parent clk
39 * @pclk_val: value to be written for selecting this parent
40 */
41struct pclk_info {
42 struct clk *pclk;
43 u8 pclk_val;
44};
45
46/**
47 * struct pclk_sel - parents selection configuration
48 * @pclk_info: pointer to array of parent clock info
49 * @pclk_count: number of parents
50 * @pclk_sel_reg: register for selecting a parent
51 * @pclk_sel_mask: mask for selecting parent (can be used to clear bits also)
52 */
53struct pclk_sel {
54 struct pclk_info *pclk_info;
55 u8 pclk_count;
56 void __iomem *pclk_sel_reg;
57 unsigned int pclk_sel_mask;
58};
59
60/**
61 * struct rate_config - clk rate configurations
62 * @tbls: array of device specific clk rate tables, in ascending order of rates
63 * @count: size of tbls array
64 * @default_index: default setting when originally disabled
65 */
66struct rate_config {
67 void *tbls;
68 u8 count;
69 u8 default_index;
70};
71
72/**
73 * struct clk - clock structure
74 * @usage_count: num of users who enabled this clock
75 * @flags: flags for clock properties
76 * @rate: programmed clock rate in Hz
77 * @en_reg: clk enable/disable reg
78 * @en_reg_bit: clk enable/disable bit
79 * @ops: clk enable/disable ops - generic_clkops selected if NULL
80 * @recalc: pointer to clock rate recalculate function
81 * @set_rate: pointer to clock set rate function
82 * @calc_rate: pointer to clock get rate function for index
83 * @rate_config: rate configuration information, used by set_rate
84 * @div_factor: division factor to parent clock.
85 * @pclk: current parent clk
86 * @pclk_sel: pointer to parent selection structure
87 * @pclk_sel_shift: register shift for selecting parent of this clock
88 * @children: list for childrens or this clock
89 * @sibling: node for list of clocks having same parents
90 * @private_data: clock specific private data
91 * @node: list to maintain clocks linearly
92 * @cl: clocklook up associated with this clock
93 * @dent: object for debugfs
94 */
95struct clk {
96 unsigned int usage_count;
97 unsigned int flags;
98 unsigned long rate;
99 void __iomem *en_reg;
100 u8 en_reg_bit;
101 const struct clkops *ops;
102 int (*recalc) (struct clk *);
103 int (*set_rate) (struct clk *, unsigned long rate);
104 unsigned long (*calc_rate)(struct clk *, int index);
105 struct rate_config rate_config;
106 unsigned int div_factor;
107
108 struct clk *pclk;
109 struct pclk_sel *pclk_sel;
110 unsigned int pclk_sel_shift;
111
112 struct list_head children;
113 struct list_head sibling;
114 void *private_data;
115#ifdef CONFIG_DEBUG_FS
116 struct list_head node;
117 struct clk_lookup *cl;
118 struct dentry *dent;
119#endif
120};
121
122/* pll configuration structure */
123struct pll_clk_masks {
124 u32 mode_mask;
125 u32 mode_shift;
126
127 u32 norm_fdbk_m_mask;
128 u32 norm_fdbk_m_shift;
129 u32 dith_fdbk_m_mask;
130 u32 dith_fdbk_m_shift;
131 u32 div_p_mask;
132 u32 div_p_shift;
133 u32 div_n_mask;
134 u32 div_n_shift;
135};
136
137struct pll_clk_config {
138 void __iomem *mode_reg;
139 void __iomem *cfg_reg;
140 struct pll_clk_masks *masks;
141};
142
143/* pll clk rate config structure */
144struct pll_rate_tbl {
145 u8 mode;
146 u16 m;
147 u8 n;
148 u8 p;
149};
150
151/* ahb and apb bus configuration structure */
152struct bus_clk_masks {
153 u32 mask;
154 u32 shift;
155};
156
157struct bus_clk_config {
158 void __iomem *reg;
159 struct bus_clk_masks *masks;
160};
161
162/* ahb and apb clk bus rate config structure */
163struct bus_rate_tbl {
164 u8 div;
165};
166
167/* Aux clk configuration structure: applicable to UART and FIRDA */
168struct aux_clk_masks {
169 u32 eq_sel_mask;
170 u32 eq_sel_shift;
171 u32 eq1_mask;
172 u32 eq2_mask;
173 u32 xscale_sel_mask;
174 u32 xscale_sel_shift;
175 u32 yscale_sel_mask;
176 u32 yscale_sel_shift;
177};
178
179struct aux_clk_config {
180 void __iomem *synth_reg;
181 struct aux_clk_masks *masks;
182};
183
184/* aux clk rate config structure */
185struct aux_rate_tbl {
186 u16 xscale;
187 u16 yscale;
188 u8 eq;
189};
190
191/* GPT clk configuration structure */
192struct gpt_clk_masks {
193 u32 mscale_sel_mask;
194 u32 mscale_sel_shift;
195 u32 nscale_sel_mask;
196 u32 nscale_sel_shift;
197};
198
199struct gpt_clk_config {
200 void __iomem *synth_reg;
201 struct gpt_clk_masks *masks;
202};
203
204/* gpt clk rate config structure */
205struct gpt_rate_tbl {
206 u16 mscale;
207 u16 nscale;
208};
209
210/* clcd clk configuration structure */
211struct clcd_synth_masks {
212 u32 div_factor_mask;
213 u32 div_factor_shift;
214};
215
216struct clcd_clk_config {
217 void __iomem *synth_reg;
218 struct clcd_synth_masks *masks;
219};
220
221/* clcd clk rate config structure */
222struct clcd_rate_tbl {
223 u16 div;
224};
225
226/* platform specific clock functions */
227void __init clk_init(void);
228void clk_register(struct clk_lookup *cl);
229void recalc_root_clocks(void);
230
231/* clock recalc & set rate functions */
232int follow_parent(struct clk *clk);
233unsigned long pll_calc_rate(struct clk *clk, int index);
234int pll_clk_recalc(struct clk *clk);
235int pll_clk_set_rate(struct clk *clk, unsigned long desired_rate);
236unsigned long bus_calc_rate(struct clk *clk, int index);
237int bus_clk_recalc(struct clk *clk);
238int bus_clk_set_rate(struct clk *clk, unsigned long desired_rate);
239unsigned long gpt_calc_rate(struct clk *clk, int index);
240int gpt_clk_recalc(struct clk *clk);
241int gpt_clk_set_rate(struct clk *clk, unsigned long desired_rate);
242unsigned long aux_calc_rate(struct clk *clk, int index);
243int aux_clk_recalc(struct clk *clk);
244int aux_clk_set_rate(struct clk *clk, unsigned long desired_rate);
245unsigned long clcd_calc_rate(struct clk *clk, int index);
246int clcd_clk_recalc(struct clk *clk);
247int clcd_clk_set_rate(struct clk *clk, unsigned long desired_rate);
248
249#endif /* __PLAT_CLOCK_H */
diff --git a/drivers/clk/spear/Makefile b/drivers/clk/spear/Makefile
index 9e64824a8000..335886049c83 100644
--- a/drivers/clk/spear/Makefile
+++ b/drivers/clk/spear/Makefile
@@ -3,3 +3,6 @@
3# 3#
4 4
5obj-y += clk.o clk-aux-synth.o clk-frac-synth.o clk-gpt-synth.o clk-vco-pll.o 5obj-y += clk.o clk-aux-synth.o clk-frac-synth.o clk-gpt-synth.o clk-vco-pll.o
6
7obj-$(CONFIG_ARCH_SPEAR3XX) += spear3xx_clock.o
8obj-$(CONFIG_ARCH_SPEAR6XX) += spear6xx_clock.o
diff --git a/drivers/clk/spear/spear3xx_clock.c b/drivers/clk/spear/spear3xx_clock.c
new file mode 100644
index 000000000000..440bb3e4c971
--- /dev/null
+++ b/drivers/clk/spear/spear3xx_clock.c
@@ -0,0 +1,612 @@
1/*
2 * SPEAr3xx machines clock framework source file
3 *
4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.kumar@st.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/clk.h>
13#include <linux/clkdev.h>
14#include <linux/err.h>
15#include <linux/io.h>
16#include <linux/of_platform.h>
17#include <linux/spinlock_types.h>
18#include <mach/misc_regs.h>
19#include "clk.h"
20
21static DEFINE_SPINLOCK(_lock);
22
23#define PLL1_CTR (MISC_BASE + 0x008)
24#define PLL1_FRQ (MISC_BASE + 0x00C)
25#define PLL2_CTR (MISC_BASE + 0x014)
26#define PLL2_FRQ (MISC_BASE + 0x018)
27#define PLL_CLK_CFG (MISC_BASE + 0x020)
28 /* PLL_CLK_CFG register masks */
29 #define MCTR_CLK_SHIFT 28
30 #define MCTR_CLK_MASK 3
31
32#define CORE_CLK_CFG (MISC_BASE + 0x024)
33 /* CORE CLK CFG register masks */
34 #define GEN_SYNTH2_3_CLK_SHIFT 18
35 #define GEN_SYNTH2_3_CLK_MASK 1
36
37 #define HCLK_RATIO_SHIFT 10
38 #define HCLK_RATIO_MASK 2
39 #define PCLK_RATIO_SHIFT 8
40 #define PCLK_RATIO_MASK 2
41
42#define PERIP_CLK_CFG (MISC_BASE + 0x028)
43 /* PERIP_CLK_CFG register masks */
44 #define UART_CLK_SHIFT 4
45 #define UART_CLK_MASK 1
46 #define FIRDA_CLK_SHIFT 5
47 #define FIRDA_CLK_MASK 2
48 #define GPT0_CLK_SHIFT 8
49 #define GPT1_CLK_SHIFT 11
50 #define GPT2_CLK_SHIFT 12
51 #define GPT_CLK_MASK 1
52
53#define PERIP1_CLK_ENB (MISC_BASE + 0x02C)
54 /* PERIP1_CLK_ENB register masks */
55 #define UART_CLK_ENB 3
56 #define SSP_CLK_ENB 5
57 #define I2C_CLK_ENB 7
58 #define JPEG_CLK_ENB 8
59 #define FIRDA_CLK_ENB 10
60 #define GPT1_CLK_ENB 11
61 #define GPT2_CLK_ENB 12
62 #define ADC_CLK_ENB 15
63 #define RTC_CLK_ENB 17
64 #define GPIO_CLK_ENB 18
65 #define DMA_CLK_ENB 19
66 #define SMI_CLK_ENB 21
67 #define GMAC_CLK_ENB 23
68 #define USBD_CLK_ENB 24
69 #define USBH_CLK_ENB 25
70 #define C3_CLK_ENB 31
71
72#define RAS_CLK_ENB (MISC_BASE + 0x034)
73 #define RAS_AHB_CLK_ENB 0
74 #define RAS_PLL1_CLK_ENB 1
75 #define RAS_APB_CLK_ENB 2
76 #define RAS_32K_CLK_ENB 3
77 #define RAS_24M_CLK_ENB 4
78 #define RAS_48M_CLK_ENB 5
79 #define RAS_PLL2_CLK_ENB 7
80 #define RAS_SYNT0_CLK_ENB 8
81 #define RAS_SYNT1_CLK_ENB 9
82 #define RAS_SYNT2_CLK_ENB 10
83 #define RAS_SYNT3_CLK_ENB 11
84
85#define PRSC0_CLK_CFG (MISC_BASE + 0x044)
86#define PRSC1_CLK_CFG (MISC_BASE + 0x048)
87#define PRSC2_CLK_CFG (MISC_BASE + 0x04C)
88#define AMEM_CLK_CFG (MISC_BASE + 0x050)
89 #define AMEM_CLK_ENB 0
90
91#define CLCD_CLK_SYNT (MISC_BASE + 0x05C)
92#define FIRDA_CLK_SYNT (MISC_BASE + 0x060)
93#define UART_CLK_SYNT (MISC_BASE + 0x064)
94#define GMAC_CLK_SYNT (MISC_BASE + 0x068)
95#define GEN0_CLK_SYNT (MISC_BASE + 0x06C)
96#define GEN1_CLK_SYNT (MISC_BASE + 0x070)
97#define GEN2_CLK_SYNT (MISC_BASE + 0x074)
98#define GEN3_CLK_SYNT (MISC_BASE + 0x078)
99
100/* pll rate configuration table, in ascending order of rates */
101static struct pll_rate_tbl pll_rtbl[] = {
102 {.mode = 0, .m = 0x53, .n = 0x0C, .p = 0x1}, /* vco 332 & pll 166 MHz */
103 {.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* vco 532 & pll 266 MHz */
104 {.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* vco 664 & pll 332 MHz */
105};
106
107/* aux rate configuration table, in ascending order of rates */
108static struct aux_rate_tbl aux_rtbl[] = {
109 /* For PLL1 = 332 MHz */
110 {.xscale = 2, .yscale = 27, .eq = 0}, /* 12.296 MHz */
111 {.xscale = 2, .yscale = 8, .eq = 0}, /* 41.5 MHz */
112 {.xscale = 2, .yscale = 4, .eq = 0}, /* 83 MHz */
113 {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
114};
115
116/* gpt rate configuration table, in ascending order of rates */
117static struct gpt_rate_tbl gpt_rtbl[] = {
118 /* For pll1 = 332 MHz */
119 {.mscale = 4, .nscale = 0}, /* 41.5 MHz */
120 {.mscale = 2, .nscale = 0}, /* 55.3 MHz */
121 {.mscale = 1, .nscale = 0}, /* 83 MHz */
122};
123
124/* clock parents */
125static const char *uart0_parents[] = { "pll3_48m_clk", "uart_synth_gate_clk", };
126static const char *firda_parents[] = { "pll3_48m_clk", "firda_synth_gate_clk",
127};
128static const char *gpt0_parents[] = { "pll3_48m_clk", "gpt0_synth_clk", };
129static const char *gpt1_parents[] = { "pll3_48m_clk", "gpt1_synth_clk", };
130static const char *gpt2_parents[] = { "pll3_48m_clk", "gpt2_synth_clk", };
131static const char *gen2_3_parents[] = { "pll1_clk", "pll2_clk", };
132static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none",
133 "pll2_clk", };
134
135#ifdef CONFIG_MACH_SPEAR300
136static void __init spear300_clk_init(void)
137{
138 struct clk *clk;
139
140 clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_48m_clk", 0,
141 1, 1);
142 clk_register_clkdev(clk, NULL, "60000000.clcd");
143
144 clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1,
145 1);
146 clk_register_clkdev(clk, NULL, "94000000.flash");
147
148 clk = clk_register_fixed_factor(NULL, "sdhci_clk", "ras_ahb_clk", 0, 1,
149 1);
150 clk_register_clkdev(clk, NULL, "70000000.sdhci");
151
152 clk = clk_register_fixed_factor(NULL, "gpio1_clk", "ras_apb_clk", 0, 1,
153 1);
154 clk_register_clkdev(clk, NULL, "a9000000.gpio");
155
156 clk = clk_register_fixed_factor(NULL, "kbd_clk", "ras_apb_clk", 0, 1,
157 1);
158 clk_register_clkdev(clk, NULL, "a0000000.kbd");
159}
160#endif
161
162/* array of all spear 310 clock lookups */
163#ifdef CONFIG_MACH_SPEAR310
164static void __init spear310_clk_init(void)
165{
166 struct clk *clk;
167
168 clk = clk_register_fixed_factor(NULL, "emi_clk", "ras_ahb_clk", 0, 1,
169 1);
170 clk_register_clkdev(clk, "emi", NULL);
171
172 clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1,
173 1);
174 clk_register_clkdev(clk, NULL, "44000000.flash");
175
176 clk = clk_register_fixed_factor(NULL, "tdm_clk", "ras_ahb_clk", 0, 1,
177 1);
178 clk_register_clkdev(clk, NULL, "tdm");
179
180 clk = clk_register_fixed_factor(NULL, "uart1_clk", "ras_apb_clk", 0, 1,
181 1);
182 clk_register_clkdev(clk, NULL, "b2000000.serial");
183
184 clk = clk_register_fixed_factor(NULL, "uart2_clk", "ras_apb_clk", 0, 1,
185 1);
186 clk_register_clkdev(clk, NULL, "b2080000.serial");
187
188 clk = clk_register_fixed_factor(NULL, "uart3_clk", "ras_apb_clk", 0, 1,
189 1);
190 clk_register_clkdev(clk, NULL, "b2100000.serial");
191
192 clk = clk_register_fixed_factor(NULL, "uart4_clk", "ras_apb_clk", 0, 1,
193 1);
194 clk_register_clkdev(clk, NULL, "b2180000.serial");
195
196 clk = clk_register_fixed_factor(NULL, "uart5_clk", "ras_apb_clk", 0, 1,
197 1);
198 clk_register_clkdev(clk, NULL, "b2200000.serial");
199}
200#endif
201
202/* array of all spear 320 clock lookups */
203#ifdef CONFIG_MACH_SPEAR320
204 #define SMII_PCLK_SHIFT 18
205 #define SMII_PCLK_MASK 2
206 #define SMII_PCLK_VAL_PAD 0x0
207 #define SMII_PCLK_VAL_PLL2 0x1
208 #define SMII_PCLK_VAL_SYNTH0 0x2
209 #define SDHCI_PCLK_SHIFT 15
210 #define SDHCI_PCLK_MASK 1
211 #define SDHCI_PCLK_VAL_48M 0x0
212 #define SDHCI_PCLK_VAL_SYNTH3 0x1
213 #define I2S_REF_PCLK_SHIFT 8
214 #define I2S_REF_PCLK_MASK 1
215 #define I2S_REF_PCLK_SYNTH_VAL 0x1
216 #define I2S_REF_PCLK_PLL2_VAL 0x0
217 #define UART1_PCLK_SHIFT 6
218 #define UART1_PCLK_MASK 1
219 #define SPEAR320_UARTX_PCLK_VAL_SYNTH1 0x0
220 #define SPEAR320_UARTX_PCLK_VAL_APB 0x1
221
222static const char *i2s_ref_parents[] = { "ras_pll2_clk",
223 "ras_gen2_synth_gate_clk", };
224static const char *sdhci_parents[] = { "ras_pll3_48m_clk",
225 "ras_gen3_synth_gate_clk",
226};
227static const char *smii0_parents[] = { "smii_125m_pad", "ras_pll2_clk",
228 "ras_gen0_synth_gate_clk", };
229static const char *uartx_parents[] = { "ras_gen1_synth_gate_clk", "ras_apb_clk",
230};
231
232static void __init spear320_clk_init(void)
233{
234 struct clk *clk;
235
236 clk = clk_register_fixed_rate(NULL, "smii_125m_pad_clk", NULL,
237 CLK_IS_ROOT, 125000000);
238 clk_register_clkdev(clk, "smii_125m_pad", NULL);
239
240 clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_48m_clk", 0,
241 1, 1);
242 clk_register_clkdev(clk, NULL, "90000000.clcd");
243
244 clk = clk_register_fixed_factor(NULL, "emi_clk", "ras_ahb_clk", 0, 1,
245 1);
246 clk_register_clkdev(clk, "emi", NULL);
247
248 clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1,
249 1);
250 clk_register_clkdev(clk, NULL, "4c000000.flash");
251
252 clk = clk_register_fixed_factor(NULL, "i2c1_clk", "ras_ahb_clk", 0, 1,
253 1);
254 clk_register_clkdev(clk, NULL, "a7000000.i2c");
255
256 clk = clk_register_fixed_factor(NULL, "pwm_clk", "ras_ahb_clk", 0, 1,
257 1);
258 clk_register_clkdev(clk, "pwm", NULL);
259
260 clk = clk_register_fixed_factor(NULL, "ssp1_clk", "ras_ahb_clk", 0, 1,
261 1);
262 clk_register_clkdev(clk, NULL, "a5000000.spi");
263
264 clk = clk_register_fixed_factor(NULL, "ssp2_clk", "ras_ahb_clk", 0, 1,
265 1);
266 clk_register_clkdev(clk, NULL, "a6000000.spi");
267
268 clk = clk_register_fixed_factor(NULL, "can0_clk", "ras_apb_clk", 0, 1,
269 1);
270 clk_register_clkdev(clk, NULL, "c_can_platform.0");
271
272 clk = clk_register_fixed_factor(NULL, "can1_clk", "ras_apb_clk", 0, 1,
273 1);
274 clk_register_clkdev(clk, NULL, "c_can_platform.1");
275
276 clk = clk_register_fixed_factor(NULL, "i2s_clk", "ras_apb_clk", 0, 1,
277 1);
278 clk_register_clkdev(clk, NULL, "i2s");
279
280 clk = clk_register_mux(NULL, "i2s_ref_clk", i2s_ref_parents,
281 ARRAY_SIZE(i2s_ref_parents), 0, SPEAR320_CONTROL_REG,
282 I2S_REF_PCLK_SHIFT, I2S_REF_PCLK_MASK, 0, &_lock);
283 clk_register_clkdev(clk, "i2s_ref_clk", NULL);
284
285 clk = clk_register_fixed_factor(NULL, "i2s_sclk", "i2s_ref_clk", 0, 1,
286 4);
287 clk_register_clkdev(clk, "i2s_sclk", NULL);
288
289 clk = clk_register_mux(NULL, "rs485_clk", uartx_parents,
290 ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG,
291 SPEAR320_RS485_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0,
292 &_lock);
293 clk_register_clkdev(clk, NULL, "a9300000.serial");
294
295 clk = clk_register_mux(NULL, "sdhci_clk", sdhci_parents,
296 ARRAY_SIZE(sdhci_parents), 0, SPEAR320_CONTROL_REG,
297 SDHCI_PCLK_SHIFT, SDHCI_PCLK_MASK, 0, &_lock);
298 clk_register_clkdev(clk, NULL, "70000000.sdhci");
299
300 clk = clk_register_mux(NULL, "smii_pclk", smii0_parents,
301 ARRAY_SIZE(smii0_parents), 0, SPEAR320_CONTROL_REG,
302 SMII_PCLK_SHIFT, SMII_PCLK_MASK, 0, &_lock);
303 clk_register_clkdev(clk, NULL, "smii_pclk");
304
305 clk = clk_register_fixed_factor(NULL, "smii_clk", "smii_pclk", 0, 1, 1);
306 clk_register_clkdev(clk, NULL, "smii");
307
308 clk = clk_register_mux(NULL, "uart1_clk", uartx_parents,
309 ARRAY_SIZE(uartx_parents), 0, SPEAR320_CONTROL_REG,
310 UART1_PCLK_SHIFT, UART1_PCLK_MASK, 0, &_lock);
311 clk_register_clkdev(clk, NULL, "a3000000.serial");
312
313 clk = clk_register_mux(NULL, "uart2_clk", uartx_parents,
314 ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG,
315 SPEAR320_UART2_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0,
316 &_lock);
317 clk_register_clkdev(clk, NULL, "a4000000.serial");
318
319 clk = clk_register_mux(NULL, "uart3_clk", uartx_parents,
320 ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG,
321 SPEAR320_UART3_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0,
322 &_lock);
323 clk_register_clkdev(clk, NULL, "a9100000.serial");
324
325 clk = clk_register_mux(NULL, "uart4_clk", uartx_parents,
326 ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG,
327 SPEAR320_UART4_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0,
328 &_lock);
329 clk_register_clkdev(clk, NULL, "a9200000.serial");
330
331 clk = clk_register_mux(NULL, "uart5_clk", uartx_parents,
332 ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG,
333 SPEAR320_UART5_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0,
334 &_lock);
335 clk_register_clkdev(clk, NULL, "60000000.serial");
336
337 clk = clk_register_mux(NULL, "uart6_clk", uartx_parents,
338 ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG,
339 SPEAR320_UART6_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0,
340 &_lock);
341 clk_register_clkdev(clk, NULL, "60100000.serial");
342}
343#endif
344
345void __init spear3xx_clk_init(void)
346{
347 struct clk *clk, *clk1;
348
349 clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
350 clk_register_clkdev(clk, "apb_pclk", NULL);
351
352 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
353 32000);
354 clk_register_clkdev(clk, "osc_32k_clk", NULL);
355
356 clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT,
357 24000000);
358 clk_register_clkdev(clk, "osc_24m_clk", NULL);
359
360 /* clock derived from 32 KHz osc clk */
361 clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0,
362 PERIP1_CLK_ENB, RTC_CLK_ENB, 0, &_lock);
363 clk_register_clkdev(clk, NULL, "fc900000.rtc");
364
365 /* clock derived from 24 MHz osc clk */
366 clk = clk_register_fixed_rate(NULL, "pll3_48m_clk", "osc_24m_clk", 0,
367 48000000);
368 clk_register_clkdev(clk, "pll3_48m_clk", NULL);
369
370 clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_24m_clk", 0, 1,
371 1);
372 clk_register_clkdev(clk, NULL, "fc880000.wdt");
373
374 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL,
375 "osc_24m_clk", 0, PLL1_CTR, PLL1_FRQ, pll_rtbl,
376 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
377 clk_register_clkdev(clk, "vco1_clk", NULL);
378 clk_register_clkdev(clk1, "pll1_clk", NULL);
379
380 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL,
381 "osc_24m_clk", 0, PLL2_CTR, PLL2_FRQ, pll_rtbl,
382 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
383 clk_register_clkdev(clk, "vco2_clk", NULL);
384 clk_register_clkdev(clk1, "pll2_clk", NULL);
385
386 /* clock derived from pll1 clk */
387 clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", 0, 1, 1);
388 clk_register_clkdev(clk, "cpu_clk", NULL);
389
390 clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk",
391 CLK_SET_RATE_PARENT, CORE_CLK_CFG, HCLK_RATIO_SHIFT,
392 HCLK_RATIO_MASK, 0, &_lock);
393 clk_register_clkdev(clk, "ahb_clk", NULL);
394
395 clk = clk_register_aux("uart_synth_clk", "uart_synth_gate_clk",
396 "pll1_clk", 0, UART_CLK_SYNT, NULL, aux_rtbl,
397 ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
398 clk_register_clkdev(clk, "uart_synth_clk", NULL);
399 clk_register_clkdev(clk1, "uart_synth_gate_clk", NULL);
400
401 clk = clk_register_mux(NULL, "uart0_mux_clk", uart0_parents,
402 ARRAY_SIZE(uart0_parents), 0, PERIP_CLK_CFG,
403 UART_CLK_SHIFT, UART_CLK_MASK, 0, &_lock);
404 clk_register_clkdev(clk, "uart0_mux_clk", NULL);
405
406 clk = clk_register_gate(NULL, "uart0", "uart0_mux_clk", 0,
407 PERIP1_CLK_ENB, UART_CLK_ENB, 0, &_lock);
408 clk_register_clkdev(clk, NULL, "d0000000.serial");
409
410 clk = clk_register_aux("firda_synth_clk", "firda_synth_gate_clk",
411 "pll1_clk", 0, FIRDA_CLK_SYNT, NULL, aux_rtbl,
412 ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
413 clk_register_clkdev(clk, "firda_synth_clk", NULL);
414 clk_register_clkdev(clk1, "firda_synth_gate_clk", NULL);
415
416 clk = clk_register_mux(NULL, "firda_mux_clk", firda_parents,
417 ARRAY_SIZE(firda_parents), 0, PERIP_CLK_CFG,
418 FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0, &_lock);
419 clk_register_clkdev(clk, "firda_mux_clk", NULL);
420
421 clk = clk_register_gate(NULL, "firda_clk", "firda_mux_clk", 0,
422 PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, &_lock);
423 clk_register_clkdev(clk, NULL, "firda");
424
425 /* gpt clocks */
426 clk_register_gpt("gpt0_synth_clk", "pll1_clk", 0, PRSC0_CLK_CFG,
427 gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
428 clk = clk_register_mux(NULL, "gpt0_clk", gpt0_parents,
429 ARRAY_SIZE(gpt0_parents), 0, PERIP_CLK_CFG,
430 GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
431 clk_register_clkdev(clk, NULL, "gpt0");
432
433 clk_register_gpt("gpt1_synth_clk", "pll1_clk", 0, PRSC1_CLK_CFG,
434 gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
435 clk = clk_register_mux(NULL, "gpt1_mux_clk", gpt1_parents,
436 ARRAY_SIZE(gpt1_parents), 0, PERIP_CLK_CFG,
437 GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
438 clk_register_clkdev(clk, "gpt1_mux_clk", NULL);
439 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mux_clk", 0,
440 PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, &_lock);
441 clk_register_clkdev(clk, NULL, "gpt1");
442
443 clk_register_gpt("gpt2_synth_clk", "pll1_clk", 0, PRSC2_CLK_CFG,
444 gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
445 clk = clk_register_mux(NULL, "gpt2_mux_clk", gpt2_parents,
446 ARRAY_SIZE(gpt2_parents), 0, PERIP_CLK_CFG,
447 GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
448 clk_register_clkdev(clk, "gpt2_mux_clk", NULL);
449 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mux_clk", 0,
450 PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, &_lock);
451 clk_register_clkdev(clk, NULL, "gpt2");
452
453 /* general synths clocks */
454 clk = clk_register_aux("gen0_synth_clk", "gen0_synth_gate_clk",
455 "pll1_clk", 0, GEN0_CLK_SYNT, NULL, aux_rtbl,
456 ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
457 clk_register_clkdev(clk, "gen0_synth_clk", NULL);
458 clk_register_clkdev(clk1, "gen0_synth_gate_clk", NULL);
459
460 clk = clk_register_aux("gen1_synth_clk", "gen1_synth_gate_clk",
461 "pll1_clk", 0, GEN1_CLK_SYNT, NULL, aux_rtbl,
462 ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
463 clk_register_clkdev(clk, "gen1_synth_clk", NULL);
464 clk_register_clkdev(clk1, "gen1_synth_gate_clk", NULL);
465
466 clk = clk_register_mux(NULL, "gen2_3_parent_clk", gen2_3_parents,
467 ARRAY_SIZE(gen2_3_parents), 0, CORE_CLK_CFG,
468 GEN_SYNTH2_3_CLK_SHIFT, GEN_SYNTH2_3_CLK_MASK, 0,
469 &_lock);
470 clk_register_clkdev(clk, "gen2_3_parent_clk", NULL);
471
472 clk = clk_register_aux("gen2_synth_clk", "gen2_synth_gate_clk",
473 "gen2_3_parent_clk", 0, GEN2_CLK_SYNT, NULL, aux_rtbl,
474 ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
475 clk_register_clkdev(clk, "gen2_synth_clk", NULL);
476 clk_register_clkdev(clk1, "gen2_synth_gate_clk", NULL);
477
478 clk = clk_register_aux("gen3_synth_clk", "gen3_synth_gate_clk",
479 "gen2_3_parent_clk", 0, GEN3_CLK_SYNT, NULL, aux_rtbl,
480 ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
481 clk_register_clkdev(clk, "gen3_synth_clk", NULL);
482 clk_register_clkdev(clk1, "gen3_synth_gate_clk", NULL);
483
484 /* clock derived from pll3 clk */
485 clk = clk_register_gate(NULL, "usbh_clk", "pll3_48m_clk", 0,
486 PERIP1_CLK_ENB, USBH_CLK_ENB, 0, &_lock);
487 clk_register_clkdev(clk, "usbh_clk", NULL);
488
489 clk = clk_register_fixed_factor(NULL, "usbh.0_clk", "usbh_clk", 0, 1,
490 1);
491 clk_register_clkdev(clk, "usbh.0_clk", NULL);
492
493 clk = clk_register_fixed_factor(NULL, "usbh.1_clk", "usbh_clk", 0, 1,
494 1);
495 clk_register_clkdev(clk, "usbh.1_clk", NULL);
496
497 clk = clk_register_gate(NULL, "usbd_clk", "pll3_48m_clk", 0,
498 PERIP1_CLK_ENB, USBD_CLK_ENB, 0, &_lock);
499 clk_register_clkdev(clk, NULL, "designware_udc");
500
501 /* clock derived from ahb clk */
502 clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2,
503 1);
504 clk_register_clkdev(clk, "ahbmult2_clk", NULL);
505
506 clk = clk_register_mux(NULL, "ddr_clk", ddr_parents,
507 ARRAY_SIZE(ddr_parents), 0, PLL_CLK_CFG, MCTR_CLK_SHIFT,
508 MCTR_CLK_MASK, 0, &_lock);
509 clk_register_clkdev(clk, "ddr_clk", NULL);
510
511 clk = clk_register_divider(NULL, "apb_clk", "ahb_clk",
512 CLK_SET_RATE_PARENT, CORE_CLK_CFG, PCLK_RATIO_SHIFT,
513 PCLK_RATIO_MASK, 0, &_lock);
514 clk_register_clkdev(clk, "apb_clk", NULL);
515
516 clk = clk_register_gate(NULL, "amem_clk", "ahb_clk", 0, AMEM_CLK_CFG,
517 AMEM_CLK_ENB, 0, &_lock);
518 clk_register_clkdev(clk, "amem_clk", NULL);
519
520 clk = clk_register_gate(NULL, "c3_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
521 C3_CLK_ENB, 0, &_lock);
522 clk_register_clkdev(clk, NULL, "c3_clk");
523
524 clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
525 DMA_CLK_ENB, 0, &_lock);
526 clk_register_clkdev(clk, NULL, "fc400000.dma");
527
528 clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
529 GMAC_CLK_ENB, 0, &_lock);
530 clk_register_clkdev(clk, NULL, "e0800000.eth");
531
532 clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
533 I2C_CLK_ENB, 0, &_lock);
534 clk_register_clkdev(clk, NULL, "d0180000.i2c");
535
536 clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
537 JPEG_CLK_ENB, 0, &_lock);
538 clk_register_clkdev(clk, NULL, "jpeg");
539
540 clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
541 SMI_CLK_ENB, 0, &_lock);
542 clk_register_clkdev(clk, NULL, "fc000000.flash");
543
544 /* clock derived from apb clk */
545 clk = clk_register_gate(NULL, "adc_clk", "apb_clk", 0, PERIP1_CLK_ENB,
546 ADC_CLK_ENB, 0, &_lock);
547 clk_register_clkdev(clk, NULL, "adc");
548
549 clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0, PERIP1_CLK_ENB,
550 GPIO_CLK_ENB, 0, &_lock);
551 clk_register_clkdev(clk, NULL, "fc980000.gpio");
552
553 clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, PERIP1_CLK_ENB,
554 SSP_CLK_ENB, 0, &_lock);
555 clk_register_clkdev(clk, NULL, "d0100000.spi");
556
557 /* RAS clk enable */
558 clk = clk_register_gate(NULL, "ras_ahb_clk", "ahb_clk", 0, RAS_CLK_ENB,
559 RAS_AHB_CLK_ENB, 0, &_lock);
560 clk_register_clkdev(clk, "ras_ahb_clk", NULL);
561
562 clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0, RAS_CLK_ENB,
563 RAS_APB_CLK_ENB, 0, &_lock);
564 clk_register_clkdev(clk, "ras_apb_clk", NULL);
565
566 clk = clk_register_gate(NULL, "ras_32k_clk", "osc_32k_clk", 0,
567 RAS_CLK_ENB, RAS_32K_CLK_ENB, 0, &_lock);
568 clk_register_clkdev(clk, "ras_32k_clk", NULL);
569
570 clk = clk_register_gate(NULL, "ras_24m_clk", "osc_24m_clk", 0,
571 RAS_CLK_ENB, RAS_24M_CLK_ENB, 0, &_lock);
572 clk_register_clkdev(clk, "ras_24m_clk", NULL);
573
574 clk = clk_register_gate(NULL, "ras_pll1_clk", "pll1_clk", 0,
575 RAS_CLK_ENB, RAS_PLL1_CLK_ENB, 0, &_lock);
576 clk_register_clkdev(clk, "ras_pll1_clk", NULL);
577
578 clk = clk_register_gate(NULL, "ras_pll2_clk", "pll2_clk", 0,
579 RAS_CLK_ENB, RAS_PLL2_CLK_ENB, 0, &_lock);
580 clk_register_clkdev(clk, "ras_pll2_clk", NULL);
581
582 clk = clk_register_gate(NULL, "ras_pll3_48m_clk", "pll3_48m_clk", 0,
583 RAS_CLK_ENB, RAS_48M_CLK_ENB, 0, &_lock);
584 clk_register_clkdev(clk, "ras_pll3_48m_clk", NULL);
585
586 clk = clk_register_gate(NULL, "ras_gen0_synth_gate_clk",
587 "gen0_synth_gate_clk", 0, RAS_CLK_ENB,
588 RAS_SYNT0_CLK_ENB, 0, &_lock);
589 clk_register_clkdev(clk, "ras_gen0_synth_gate_clk", NULL);
590
591 clk = clk_register_gate(NULL, "ras_gen1_synth_gate_clk",
592 "gen1_synth_gate_clk", 0, RAS_CLK_ENB,
593 RAS_SYNT1_CLK_ENB, 0, &_lock);
594 clk_register_clkdev(clk, "ras_gen1_synth_gate_clk", NULL);
595
596 clk = clk_register_gate(NULL, "ras_gen2_synth_gate_clk",
597 "gen2_synth_gate_clk", 0, RAS_CLK_ENB,
598 RAS_SYNT2_CLK_ENB, 0, &_lock);
599 clk_register_clkdev(clk, "ras_gen2_synth_gate_clk", NULL);
600
601 clk = clk_register_gate(NULL, "ras_gen3_synth_gate_clk",
602 "gen3_synth_gate_clk", 0, RAS_CLK_ENB,
603 RAS_SYNT3_CLK_ENB, 0, &_lock);
604 clk_register_clkdev(clk, "ras_gen3_synth_gate_clk", NULL);
605
606 if (of_machine_is_compatible("st,spear300"))
607 spear300_clk_init();
608 else if (of_machine_is_compatible("st,spear310"))
609 spear310_clk_init();
610 else if (of_machine_is_compatible("st,spear320"))
611 spear320_clk_init();
612}
diff --git a/drivers/clk/spear/spear6xx_clock.c b/drivers/clk/spear/spear6xx_clock.c
new file mode 100644
index 000000000000..f9a20b382304
--- /dev/null
+++ b/drivers/clk/spear/spear6xx_clock.c
@@ -0,0 +1,342 @@
1/*
2 * SPEAr6xx machines clock framework source file
3 *
4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.kumar@st.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/clk.h>
13#include <linux/clkdev.h>
14#include <linux/io.h>
15#include <linux/spinlock_types.h>
16#include <mach/misc_regs.h>
17#include "clk.h"
18
19static DEFINE_SPINLOCK(_lock);
20
21#define PLL1_CTR (MISC_BASE + 0x008)
22#define PLL1_FRQ (MISC_BASE + 0x00C)
23#define PLL2_CTR (MISC_BASE + 0x014)
24#define PLL2_FRQ (MISC_BASE + 0x018)
25#define PLL_CLK_CFG (MISC_BASE + 0x020)
26 /* PLL_CLK_CFG register masks */
27 #define MCTR_CLK_SHIFT 28
28 #define MCTR_CLK_MASK 3
29
30#define CORE_CLK_CFG (MISC_BASE + 0x024)
31 /* CORE CLK CFG register masks */
32 #define HCLK_RATIO_SHIFT 10
33 #define HCLK_RATIO_MASK 2
34 #define PCLK_RATIO_SHIFT 8
35 #define PCLK_RATIO_MASK 2
36
37#define PERIP_CLK_CFG (MISC_BASE + 0x028)
38 /* PERIP_CLK_CFG register masks */
39 #define CLCD_CLK_SHIFT 2
40 #define CLCD_CLK_MASK 2
41 #define UART_CLK_SHIFT 4
42 #define UART_CLK_MASK 1
43 #define FIRDA_CLK_SHIFT 5
44 #define FIRDA_CLK_MASK 2
45 #define GPT0_CLK_SHIFT 8
46 #define GPT1_CLK_SHIFT 10
47 #define GPT2_CLK_SHIFT 11
48 #define GPT3_CLK_SHIFT 12
49 #define GPT_CLK_MASK 1
50
51#define PERIP1_CLK_ENB (MISC_BASE + 0x02C)
52 /* PERIP1_CLK_ENB register masks */
53 #define UART0_CLK_ENB 3
54 #define UART1_CLK_ENB 4
55 #define SSP0_CLK_ENB 5
56 #define SSP1_CLK_ENB 6
57 #define I2C_CLK_ENB 7
58 #define JPEG_CLK_ENB 8
59 #define FSMC_CLK_ENB 9
60 #define FIRDA_CLK_ENB 10
61 #define GPT2_CLK_ENB 11
62 #define GPT3_CLK_ENB 12
63 #define GPIO2_CLK_ENB 13
64 #define SSP2_CLK_ENB 14
65 #define ADC_CLK_ENB 15
66 #define GPT1_CLK_ENB 11
67 #define RTC_CLK_ENB 17
68 #define GPIO1_CLK_ENB 18
69 #define DMA_CLK_ENB 19
70 #define SMI_CLK_ENB 21
71 #define CLCD_CLK_ENB 22
72 #define GMAC_CLK_ENB 23
73 #define USBD_CLK_ENB 24
74 #define USBH0_CLK_ENB 25
75 #define USBH1_CLK_ENB 26
76
77#define PRSC0_CLK_CFG (MISC_BASE + 0x044)
78#define PRSC1_CLK_CFG (MISC_BASE + 0x048)
79#define PRSC2_CLK_CFG (MISC_BASE + 0x04C)
80
81#define CLCD_CLK_SYNT (MISC_BASE + 0x05C)
82#define FIRDA_CLK_SYNT (MISC_BASE + 0x060)
83#define UART_CLK_SYNT (MISC_BASE + 0x064)
84
85/* vco rate configuration table, in ascending order of rates */
86static struct pll_rate_tbl pll_rtbl[] = {
87 {.mode = 0, .m = 0x53, .n = 0x0F, .p = 0x1}, /* vco 332 & pll 166 MHz */
88 {.mode = 0, .m = 0x85, .n = 0x0F, .p = 0x1}, /* vco 532 & pll 266 MHz */
89 {.mode = 0, .m = 0xA6, .n = 0x0F, .p = 0x1}, /* vco 664 & pll 332 MHz */
90};
91
92/* aux rate configuration table, in ascending order of rates */
93static struct aux_rate_tbl aux_rtbl[] = {
94 /* For PLL1 = 332 MHz */
95 {.xscale = 2, .yscale = 8, .eq = 0}, /* 41.5 MHz */
96 {.xscale = 2, .yscale = 4, .eq = 0}, /* 83 MHz */
97 {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
98};
99
100static const char *clcd_parents[] = { "pll3_48m_clk", "clcd_synth_gate_clk", };
101static const char *firda_parents[] = { "pll3_48m_clk", "firda_synth_gate_clk",
102};
103static const char *uart_parents[] = { "pll3_48m_clk", "uart_synth_gate_clk", };
104static const char *gpt0_1_parents[] = { "pll3_48m_clk", "gpt0_1_synth_clk", };
105static const char *gpt2_parents[] = { "pll3_48m_clk", "gpt2_synth_clk", };
106static const char *gpt3_parents[] = { "pll3_48m_clk", "gpt3_synth_clk", };
107static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none",
108 "pll2_clk", };
109
110/* gpt rate configuration table, in ascending order of rates */
111static struct gpt_rate_tbl gpt_rtbl[] = {
112 /* For pll1 = 332 MHz */
113 {.mscale = 4, .nscale = 0}, /* 41.5 MHz */
114 {.mscale = 2, .nscale = 0}, /* 55.3 MHz */
115 {.mscale = 1, .nscale = 0}, /* 83 MHz */
116};
117
118void __init spear6xx_clk_init(void)
119{
120 struct clk *clk, *clk1;
121
122 clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
123 clk_register_clkdev(clk, "apb_pclk", NULL);
124
125 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
126 32000);
127 clk_register_clkdev(clk, "osc_32k_clk", NULL);
128
129 clk = clk_register_fixed_rate(NULL, "osc_30m_clk", NULL, CLK_IS_ROOT,
130 30000000);
131 clk_register_clkdev(clk, "osc_30m_clk", NULL);
132
133 /* clock derived from 32 KHz osc clk */
134 clk = clk_register_gate(NULL, "rtc_spear", "osc_32k_clk", 0,
135 PERIP1_CLK_ENB, RTC_CLK_ENB, 0, &_lock);
136 clk_register_clkdev(clk, NULL, "rtc-spear");
137
138 /* clock derived from 30 MHz osc clk */
139 clk = clk_register_fixed_rate(NULL, "pll3_48m_clk", "osc_24m_clk", 0,
140 48000000);
141 clk_register_clkdev(clk, "pll3_48m_clk", NULL);
142
143 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "osc_30m_clk",
144 0, PLL1_CTR, PLL1_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl),
145 &_lock, &clk1, NULL);
146 clk_register_clkdev(clk, "vco1_clk", NULL);
147 clk_register_clkdev(clk1, "pll1_clk", NULL);
148
149 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL,
150 "osc_30m_clk", 0, PLL2_CTR, PLL2_FRQ, pll_rtbl,
151 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
152 clk_register_clkdev(clk, "vco2_clk", NULL);
153 clk_register_clkdev(clk1, "pll2_clk", NULL);
154
155 clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_30m_clk", 0, 1,
156 1);
157 clk_register_clkdev(clk, NULL, "wdt");
158
159 /* clock derived from pll1 clk */
160 clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", 0, 1, 1);
161 clk_register_clkdev(clk, "cpu_clk", NULL);
162
163 clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk",
164 CLK_SET_RATE_PARENT, CORE_CLK_CFG, HCLK_RATIO_SHIFT,
165 HCLK_RATIO_MASK, 0, &_lock);
166 clk_register_clkdev(clk, "ahb_clk", NULL);
167
168 clk = clk_register_aux("uart_synth_clk", "uart_synth_gate_clk",
169 "pll1_clk", 0, UART_CLK_SYNT, NULL, aux_rtbl,
170 ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
171 clk_register_clkdev(clk, "uart_synth_clk", NULL);
172 clk_register_clkdev(clk1, "uart_synth_gate_clk", NULL);
173
174 clk = clk_register_mux(NULL, "uart_mux_clk", uart_parents,
175 ARRAY_SIZE(uart_parents), 0, PERIP_CLK_CFG,
176 UART_CLK_SHIFT, UART_CLK_MASK, 0, &_lock);
177 clk_register_clkdev(clk, "uart_mux_clk", NULL);
178
179 clk = clk_register_gate(NULL, "uart0", "uart_mux_clk", 0,
180 PERIP1_CLK_ENB, UART0_CLK_ENB, 0, &_lock);
181 clk_register_clkdev(clk, NULL, "d0000000.serial");
182
183 clk = clk_register_gate(NULL, "uart1", "uart_mux_clk", 0,
184 PERIP1_CLK_ENB, UART1_CLK_ENB, 0, &_lock);
185 clk_register_clkdev(clk, NULL, "d0080000.serial");
186
187 clk = clk_register_aux("firda_synth_clk", "firda_synth_gate_clk",
188 "pll1_clk", 0, FIRDA_CLK_SYNT, NULL, aux_rtbl,
189 ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
190 clk_register_clkdev(clk, "firda_synth_clk", NULL);
191 clk_register_clkdev(clk1, "firda_synth_gate_clk", NULL);
192
193 clk = clk_register_mux(NULL, "firda_mux_clk", firda_parents,
194 ARRAY_SIZE(firda_parents), 0, PERIP_CLK_CFG,
195 FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0, &_lock);
196 clk_register_clkdev(clk, "firda_mux_clk", NULL);
197
198 clk = clk_register_gate(NULL, "firda_clk", "firda_mux_clk", 0,
199 PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, &_lock);
200 clk_register_clkdev(clk, NULL, "firda");
201
202 clk = clk_register_aux("clcd_synth_clk", "clcd_synth_gate_clk",
203 "pll1_clk", 0, CLCD_CLK_SYNT, NULL, aux_rtbl,
204 ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
205 clk_register_clkdev(clk, "clcd_synth_clk", NULL);
206 clk_register_clkdev(clk1, "clcd_synth_gate_clk", NULL);
207
208 clk = clk_register_mux(NULL, "clcd_mux_clk", clcd_parents,
209 ARRAY_SIZE(clcd_parents), 0, PERIP_CLK_CFG,
210 CLCD_CLK_SHIFT, CLCD_CLK_MASK, 0, &_lock);
211 clk_register_clkdev(clk, "clcd_mux_clk", NULL);
212
213 clk = clk_register_gate(NULL, "clcd_clk", "clcd_mux_clk", 0,
214 PERIP1_CLK_ENB, CLCD_CLK_ENB, 0, &_lock);
215 clk_register_clkdev(clk, NULL, "clcd");
216
217 /* gpt clocks */
218 clk = clk_register_gpt("gpt0_1_synth_clk", "pll1_clk", 0, PRSC0_CLK_CFG,
219 gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
220 clk_register_clkdev(clk, "gpt0_1_synth_clk", NULL);
221
222 clk = clk_register_mux(NULL, "gpt0_mux_clk", gpt0_1_parents,
223 ARRAY_SIZE(gpt0_1_parents), 0, PERIP_CLK_CFG,
224 GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
225 clk_register_clkdev(clk, NULL, "gpt0");
226
227 clk = clk_register_mux(NULL, "gpt1_mux_clk", gpt0_1_parents,
228 ARRAY_SIZE(gpt0_1_parents), 0, PERIP_CLK_CFG,
229 GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
230 clk_register_clkdev(clk, "gpt1_mux_clk", NULL);
231
232 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mux_clk", 0,
233 PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, &_lock);
234 clk_register_clkdev(clk, NULL, "gpt1");
235
236 clk = clk_register_gpt("gpt2_synth_clk", "pll1_clk", 0, PRSC1_CLK_CFG,
237 gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
238 clk_register_clkdev(clk, "gpt2_synth_clk", NULL);
239
240 clk = clk_register_mux(NULL, "gpt2_mux_clk", gpt2_parents,
241 ARRAY_SIZE(gpt2_parents), 0, PERIP_CLK_CFG,
242 GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
243 clk_register_clkdev(clk, "gpt2_mux_clk", NULL);
244
245 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mux_clk", 0,
246 PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, &_lock);
247 clk_register_clkdev(clk, NULL, "gpt2");
248
249 clk = clk_register_gpt("gpt3_synth_clk", "pll1_clk", 0, PRSC2_CLK_CFG,
250 gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
251 clk_register_clkdev(clk, "gpt3_synth_clk", NULL);
252
253 clk = clk_register_mux(NULL, "gpt3_mux_clk", gpt3_parents,
254 ARRAY_SIZE(gpt3_parents), 0, PERIP_CLK_CFG,
255 GPT3_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
256 clk_register_clkdev(clk, "gpt3_mux_clk", NULL);
257
258 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mux_clk", 0,
259 PERIP1_CLK_ENB, GPT3_CLK_ENB, 0, &_lock);
260 clk_register_clkdev(clk, NULL, "gpt3");
261
262 /* clock derived from pll3 clk */
263 clk = clk_register_gate(NULL, "usbh0_clk", "pll3_48m_clk", 0,
264 PERIP1_CLK_ENB, USBH0_CLK_ENB, 0, &_lock);
265 clk_register_clkdev(clk, NULL, "usbh.0_clk");
266
267 clk = clk_register_gate(NULL, "usbh1_clk", "pll3_48m_clk", 0,
268 PERIP1_CLK_ENB, USBH1_CLK_ENB, 0, &_lock);
269 clk_register_clkdev(clk, NULL, "usbh.1_clk");
270
271 clk = clk_register_gate(NULL, "usbd_clk", "pll3_48m_clk", 0,
272 PERIP1_CLK_ENB, USBD_CLK_ENB, 0, &_lock);
273 clk_register_clkdev(clk, NULL, "designware_udc");
274
275 /* clock derived from ahb clk */
276 clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2,
277 1);
278 clk_register_clkdev(clk, "ahbmult2_clk", NULL);
279
280 clk = clk_register_mux(NULL, "ddr_clk", ddr_parents,
281 ARRAY_SIZE(ddr_parents),
282 0, PLL_CLK_CFG, MCTR_CLK_SHIFT, MCTR_CLK_MASK, 0,
283 &_lock);
284 clk_register_clkdev(clk, "ddr_clk", NULL);
285
286 clk = clk_register_divider(NULL, "apb_clk", "ahb_clk",
287 CLK_SET_RATE_PARENT, CORE_CLK_CFG, PCLK_RATIO_SHIFT,
288 PCLK_RATIO_MASK, 0, &_lock);
289 clk_register_clkdev(clk, "apb_clk", NULL);
290
291 clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
292 DMA_CLK_ENB, 0, &_lock);
293 clk_register_clkdev(clk, NULL, "fc400000.dma");
294
295 clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
296 FSMC_CLK_ENB, 0, &_lock);
297 clk_register_clkdev(clk, NULL, "d1800000.flash");
298
299 clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
300 GMAC_CLK_ENB, 0, &_lock);
301 clk_register_clkdev(clk, NULL, "gmac");
302
303 clk = clk_register_gate(NULL, "i2c_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
304 I2C_CLK_ENB, 0, &_lock);
305 clk_register_clkdev(clk, NULL, "d0200000.i2c");
306
307 clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
308 JPEG_CLK_ENB, 0, &_lock);
309 clk_register_clkdev(clk, NULL, "jpeg");
310
311 clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
312 SMI_CLK_ENB, 0, &_lock);
313 clk_register_clkdev(clk, NULL, "fc000000.flash");
314
315 /* clock derived from apb clk */
316 clk = clk_register_gate(NULL, "adc_clk", "apb_clk", 0, PERIP1_CLK_ENB,
317 ADC_CLK_ENB, 0, &_lock);
318 clk_register_clkdev(clk, NULL, "adc");
319
320 clk = clk_register_fixed_factor(NULL, "gpio0_clk", "apb_clk", 0, 1, 1);
321 clk_register_clkdev(clk, NULL, "f0100000.gpio");
322
323 clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0, PERIP1_CLK_ENB,
324 GPIO1_CLK_ENB, 0, &_lock);
325 clk_register_clkdev(clk, NULL, "fc980000.gpio");
326
327 clk = clk_register_gate(NULL, "gpio2_clk", "apb_clk", 0, PERIP1_CLK_ENB,
328 GPIO2_CLK_ENB, 0, &_lock);
329 clk_register_clkdev(clk, NULL, "d8100000.gpio");
330
331 clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, PERIP1_CLK_ENB,
332 SSP0_CLK_ENB, 0, &_lock);
333 clk_register_clkdev(clk, NULL, "ssp-pl022.0");
334
335 clk = clk_register_gate(NULL, "ssp1_clk", "apb_clk", 0, PERIP1_CLK_ENB,
336 SSP1_CLK_ENB, 0, &_lock);
337 clk_register_clkdev(clk, NULL, "ssp-pl022.1");
338
339 clk = clk_register_gate(NULL, "ssp2_clk", "apb_clk", 0, PERIP1_CLK_ENB,
340 SSP2_CLK_ENB, 0, &_lock);
341 clk_register_clkdev(clk, NULL, "ssp-pl022.2");
342}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-21 06:07:22 -0500