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authorLinus Torvalds <torvalds@linux-foundation.org>2010-03-24 19:49:38 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2010-03-24 19:49:38 -0400
commit541e40ee087976ec793c53446099d3f0097e1697 (patch)
treec0f4a9cef122c6bd99e76b26592f745e42090578
parent1147d0f915e3b4c5c4fa279dae2c40016b8f441d (diff)
parent4e1a2594094020bdb41c18681c1765671138d06a (diff)
Merge branch 'sh/for-2.6.34' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6
* 'sh/for-2.6.34' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: sh: Silence unintialized variable warnings in dwarf unwinder. sh: Tidy up a couple of section mismatches. sh: Fix build after dynamic PMB rework sh: Replace unsafe manipulation of MMUCR sh: Flush ITLB too in PTEAEX's flush_tlb_page() sh64: Remove long unused mid_sched macro SH: remove superfluous warning from the serial driver SH: fix SCIFA SCASCR register bit definitions serial: sh-sci: fix SH-Mobile SH breakage sh: Add watch-dog register address for SH7722/SH7723/SH7724 sh: ms7724: Add tiny-document for sound sh: mach-ecovec24: Add i2c_put_adapter on sh_eth_init
-rw-r--r--arch/sh/boards/mach-ecovec24/setup.c2
-rw-r--r--arch/sh/boards/mach-se/7724/setup.c8
-rw-r--r--arch/sh/include/cpu-sh4/cpu/mmu_context.h2
-rw-r--r--arch/sh/include/cpu-sh4/cpu/watchdog.h6
-rw-r--r--arch/sh/kernel/dwarf.c4
-rw-r--r--arch/sh/kernel/idle.c2
-rw-r--r--arch/sh/kernel/perf_event.c2
-rw-r--r--arch/sh/kernel/process_64.c7
-rw-r--r--arch/sh/mm/pmb.c4
-rw-r--r--arch/sh/mm/tlb-pteaex.c2
-rw-r--r--arch/sh/mm/tlbflush_32.c21
-rw-r--r--drivers/serial/sh-sci.c4
-rw-r--r--drivers/serial/sh-sci.h35
13 files changed, 69 insertions, 30 deletions
diff --git a/arch/sh/boards/mach-ecovec24/setup.c b/arch/sh/boards/mach-ecovec24/setup.c
index 39ed8722d11a..6c13b92742e8 100644
--- a/arch/sh/boards/mach-ecovec24/setup.c
+++ b/arch/sh/boards/mach-ecovec24/setup.c
@@ -836,6 +836,8 @@ static void __init sh_eth_init(struct sh_eth_plat_data *pd)
836 pd->mac_addr[i] = mac_read(a, 0x10 + i); 836 pd->mac_addr[i] = mac_read(a, 0x10 + i);
837 msleep(10); 837 msleep(10);
838 } 838 }
839
840 i2c_put_adapter(a);
839} 841}
840#else 842#else
841static void __init sh_eth_init(struct sh_eth_plat_data *pd) 843static void __init sh_eth_init(struct sh_eth_plat_data *pd)
diff --git a/arch/sh/boards/mach-se/7724/setup.c b/arch/sh/boards/mach-se/7724/setup.c
index 66cdbc3c7af9..ccaa290e9aba 100644
--- a/arch/sh/boards/mach-se/7724/setup.c
+++ b/arch/sh/boards/mach-se/7724/setup.c
@@ -52,6 +52,13 @@
52 * and change SW41 to use 720p 52 * and change SW41 to use 720p
53 */ 53 */
54 54
55/*
56 * about sound
57 *
58 * This setup.c supports FSI slave mode.
59 * Please change J20, J21, J22 pin to 1-2 connection.
60 */
61
55/* Heartbeat */ 62/* Heartbeat */
56static struct resource heartbeat_resource = { 63static struct resource heartbeat_resource = {
57 .start = PA_LED, 64 .start = PA_LED,
@@ -276,6 +283,7 @@ static struct clk fsimcka_clk = {
276 .rate = 0, /* unknown */ 283 .rate = 0, /* unknown */
277}; 284};
278 285
286/* change J20, J21, J22 pin to 1-2 connection to use slave mode */
279struct sh_fsi_platform_info fsi_info = { 287struct sh_fsi_platform_info fsi_info = {
280 .porta_flags = SH_FSI_BRS_INV | 288 .porta_flags = SH_FSI_BRS_INV |
281 SH_FSI_OUT_SLAVE_MODE | 289 SH_FSI_OUT_SLAVE_MODE |
diff --git a/arch/sh/include/cpu-sh4/cpu/mmu_context.h b/arch/sh/include/cpu-sh4/cpu/mmu_context.h
index 03ea75c5315d..310ec92f2759 100644
--- a/arch/sh/include/cpu-sh4/cpu/mmu_context.h
+++ b/arch/sh/include/cpu-sh4/cpu/mmu_context.h
@@ -19,6 +19,8 @@
19 19
20#define MMUCR 0xFF000010 /* MMU Control Register */ 20#define MMUCR 0xFF000010 /* MMU Control Register */
21 21
22#define MMU_ITLB_ADDRESS_ARRAY 0xF2000000
23#define MMU_ITLB_ADDRESS_ARRAY2 0xF2800000
22#define MMU_UTLB_ADDRESS_ARRAY 0xF6000000 24#define MMU_UTLB_ADDRESS_ARRAY 0xF6000000
23#define MMU_UTLB_ADDRESS_ARRAY2 0xF6800000 25#define MMU_UTLB_ADDRESS_ARRAY2 0xF6800000
24#define MMU_PAGE_ASSOC_BIT 0x80 26#define MMU_PAGE_ASSOC_BIT 0x80
diff --git a/arch/sh/include/cpu-sh4/cpu/watchdog.h b/arch/sh/include/cpu-sh4/cpu/watchdog.h
index 7672301d0c70..7f62b9380938 100644
--- a/arch/sh/include/cpu-sh4/cpu/watchdog.h
+++ b/arch/sh/include/cpu-sh4/cpu/watchdog.h
@@ -21,6 +21,12 @@
21#define WTCNT 0xffcc0000 /*WDTST*/ 21#define WTCNT 0xffcc0000 /*WDTST*/
22#define WTST WTCNT 22#define WTST WTCNT
23#define WTBST 0xffcc0008 /*WDTBST*/ 23#define WTBST 0xffcc0008 /*WDTBST*/
24/* Register definitions */
25#elif defined(CONFIG_CPU_SUBTYPE_SH7722) || \
26 defined(CONFIG_CPU_SUBTYPE_SH7723) || \
27 defined(CONFIG_CPU_SUBTYPE_SH7724)
28#define WTCNT 0xa4520000
29#define WTCSR 0xa4520004
24#else 30#else
25/* Register definitions */ 31/* Register definitions */
26#define WTCNT 0xffc00008 32#define WTCNT 0xffc00008
diff --git a/arch/sh/kernel/dwarf.c b/arch/sh/kernel/dwarf.c
index bd1c497280a6..94739ee7aa74 100644
--- a/arch/sh/kernel/dwarf.c
+++ b/arch/sh/kernel/dwarf.c
@@ -727,7 +727,7 @@ static int dwarf_parse_cie(void *entry, void *p, unsigned long len,
727 unsigned char *end, struct module *mod) 727 unsigned char *end, struct module *mod)
728{ 728{
729 struct rb_node **rb_node = &cie_root.rb_node; 729 struct rb_node **rb_node = &cie_root.rb_node;
730 struct rb_node *parent; 730 struct rb_node *parent = *rb_node;
731 struct dwarf_cie *cie; 731 struct dwarf_cie *cie;
732 unsigned long flags; 732 unsigned long flags;
733 int count; 733 int count;
@@ -856,7 +856,7 @@ static int dwarf_parse_fde(void *entry, u32 entry_type,
856 unsigned char *end, struct module *mod) 856 unsigned char *end, struct module *mod)
857{ 857{
858 struct rb_node **rb_node = &fde_root.rb_node; 858 struct rb_node **rb_node = &fde_root.rb_node;
859 struct rb_node *parent; 859 struct rb_node *parent = *rb_node;
860 struct dwarf_fde *fde; 860 struct dwarf_fde *fde;
861 struct dwarf_cie *cie; 861 struct dwarf_cie *cie;
862 unsigned long flags; 862 unsigned long flags;
diff --git a/arch/sh/kernel/idle.c b/arch/sh/kernel/idle.c
index 0fd7b41f0a22..273f890b17ae 100644
--- a/arch/sh/kernel/idle.c
+++ b/arch/sh/kernel/idle.c
@@ -112,7 +112,7 @@ void cpu_idle(void)
112 } 112 }
113} 113}
114 114
115void __cpuinit select_idle_routine(void) 115void __init select_idle_routine(void)
116{ 116{
117 /* 117 /*
118 * If a platform has set its own idle routine, leave it alone. 118 * If a platform has set its own idle routine, leave it alone.
diff --git a/arch/sh/kernel/perf_event.c b/arch/sh/kernel/perf_event.c
index 9f253e9cce01..81b6de41ae5d 100644
--- a/arch/sh/kernel/perf_event.c
+++ b/arch/sh/kernel/perf_event.c
@@ -315,7 +315,7 @@ void hw_perf_disable(void)
315 sh_pmu->disable_all(); 315 sh_pmu->disable_all();
316} 316}
317 317
318int register_sh_pmu(struct sh_pmu *pmu) 318int __cpuinit register_sh_pmu(struct sh_pmu *pmu)
319{ 319{
320 if (sh_pmu) 320 if (sh_pmu)
321 return -EBUSY; 321 return -EBUSY;
diff --git a/arch/sh/kernel/process_64.c b/arch/sh/kernel/process_64.c
index c90957a459ac..c0d40f671ecd 100644
--- a/arch/sh/kernel/process_64.c
+++ b/arch/sh/kernel/process_64.c
@@ -504,13 +504,6 @@ out:
504 return error; 504 return error;
505} 505}
506 506
507/*
508 * These bracket the sleeping functions..
509 */
510extern void interruptible_sleep_on(wait_queue_head_t *q);
511
512#define mid_sched ((unsigned long) interruptible_sleep_on)
513
514#ifdef CONFIG_FRAME_POINTER 507#ifdef CONFIG_FRAME_POINTER
515static int in_sh64_switch_to(unsigned long pc) 508static int in_sh64_switch_to(unsigned long pc)
516{ 509{
diff --git a/arch/sh/mm/pmb.c b/arch/sh/mm/pmb.c
index a4662e2782c3..3cc21933063b 100644
--- a/arch/sh/mm/pmb.c
+++ b/arch/sh/mm/pmb.c
@@ -323,6 +323,7 @@ static void __clear_pmb_entry(struct pmb_entry *pmbe)
323 writel_uncached(data_val & ~PMB_V, data); 323 writel_uncached(data_val & ~PMB_V, data);
324} 324}
325 325
326#ifdef CONFIG_PM
326static void set_pmb_entry(struct pmb_entry *pmbe) 327static void set_pmb_entry(struct pmb_entry *pmbe)
327{ 328{
328 unsigned long flags; 329 unsigned long flags;
@@ -331,6 +332,7 @@ static void set_pmb_entry(struct pmb_entry *pmbe)
331 __set_pmb_entry(pmbe); 332 __set_pmb_entry(pmbe);
332 spin_unlock_irqrestore(&pmbe->lock, flags); 333 spin_unlock_irqrestore(&pmbe->lock, flags);
333} 334}
335#endif /* CONFIG_PM */
334 336
335int pmb_bolt_mapping(unsigned long vaddr, phys_addr_t phys, 337int pmb_bolt_mapping(unsigned long vaddr, phys_addr_t phys,
336 unsigned long size, pgprot_t prot) 338 unsigned long size, pgprot_t prot)
@@ -802,7 +804,7 @@ void __init pmb_init(void)
802 writel_uncached(0, PMB_IRMCR); 804 writel_uncached(0, PMB_IRMCR);
803 805
804 /* Flush out the TLB */ 806 /* Flush out the TLB */
805 __raw_writel(__raw_readl(MMUCR) | MMUCR_TI, MMUCR); 807 local_flush_tlb_all();
806 ctrl_barrier(); 808 ctrl_barrier();
807} 809}
808 810
diff --git a/arch/sh/mm/tlb-pteaex.c b/arch/sh/mm/tlb-pteaex.c
index 32dc674c550c..bdd0982b56ee 100644
--- a/arch/sh/mm/tlb-pteaex.c
+++ b/arch/sh/mm/tlb-pteaex.c
@@ -73,5 +73,7 @@ void local_flush_tlb_one(unsigned long asid, unsigned long page)
73 jump_to_uncached(); 73 jump_to_uncached();
74 __raw_writel(page, MMU_UTLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT); 74 __raw_writel(page, MMU_UTLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT);
75 __raw_writel(asid, MMU_UTLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT); 75 __raw_writel(asid, MMU_UTLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT);
76 __raw_writel(page, MMU_ITLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT);
77 __raw_writel(asid, MMU_ITLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT);
76 back_to_cached(); 78 back_to_cached();
77} 79}
diff --git a/arch/sh/mm/tlbflush_32.c b/arch/sh/mm/tlbflush_32.c
index 004bb3f25b5f..77dc5efa7127 100644
--- a/arch/sh/mm/tlbflush_32.c
+++ b/arch/sh/mm/tlbflush_32.c
@@ -123,18 +123,27 @@ void local_flush_tlb_mm(struct mm_struct *mm)
123void local_flush_tlb_all(void) 123void local_flush_tlb_all(void)
124{ 124{
125 unsigned long flags, status; 125 unsigned long flags, status;
126 int i;
126 127
127 /* 128 /*
128 * Flush all the TLB. 129 * Flush all the TLB.
129 *
130 * Write to the MMU control register's bit:
131 * TF-bit for SH-3, TI-bit for SH-4.
132 * It's same position, bit #2.
133 */ 130 */
134 local_irq_save(flags); 131 local_irq_save(flags);
132 jump_to_uncached();
133
135 status = __raw_readl(MMUCR); 134 status = __raw_readl(MMUCR);
136 status |= 0x04; 135 status = ((status & MMUCR_URB) >> MMUCR_URB_SHIFT);
137 __raw_writel(status, MMUCR); 136
137 if (status == 0)
138 status = MMUCR_URB_NENTRIES;
139
140 for (i = 0; i < status; i++)
141 __raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8));
142
143 for (i = 0; i < 4; i++)
144 __raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY | (i << 8));
145
146 back_to_cached();
138 ctrl_barrier(); 147 ctrl_barrier();
139 local_irq_restore(flags); 148 local_irq_restore(flags);
140} 149}
diff --git a/drivers/serial/sh-sci.c b/drivers/serial/sh-sci.c
index f7b9aff88f4a..309de6be8204 100644
--- a/drivers/serial/sh-sci.c
+++ b/drivers/serial/sh-sci.c
@@ -779,10 +779,6 @@ static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
779 if ((ssr_status & SCxSR_BRK(port)) && err_enabled) 779 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
780 ret = sci_br_interrupt(irq, ptr); 780 ret = sci_br_interrupt(irq, ptr);
781 781
782 WARN_ONCE(ret == IRQ_NONE,
783 "%s: %d IRQ %d, status %x, control %x\n", __func__,
784 irq, port->line, ssr_status, scr_status);
785
786 return ret; 782 return ret;
787} 783}
788 784
diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h
index fad67d33b0bd..f70c49f915fa 100644
--- a/drivers/serial/sh-sci.h
+++ b/drivers/serial/sh-sci.h
@@ -31,7 +31,9 @@
31# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0 31# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
32#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 32#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
33 defined(CONFIG_CPU_SUBTYPE_SH7721) || \ 33 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
34 defined(CONFIG_ARCH_SHMOBILE) 34 defined(CONFIG_ARCH_SH7367) || \
35 defined(CONFIG_ARCH_SH7377) || \
36 defined(CONFIG_ARCH_SH7372)
35# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ 37# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
36# define PORT_PTCR 0xA405011EUL 38# define PORT_PTCR 0xA405011EUL
37# define PORT_PVCR 0xA4050122UL 39# define PORT_PVCR 0xA4050122UL
@@ -94,7 +96,9 @@
94# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 96# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
95#elif defined(CONFIG_CPU_SUBTYPE_SH7724) 97#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
96# define SCIF_ORER 0x0001 /* overrun error bit */ 98# define SCIF_ORER 0x0001 /* overrun error bit */
97# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 99# define SCSCR_INIT(port) ((port)->type == PORT_SCIFA ? \
100 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
101 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
98#elif defined(CONFIG_CPU_SUBTYPE_SH4_202) 102#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
99# define SCSPTR2 0xffe80020 /* 16 bit SCIF */ 103# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
100# define SCIF_ORER 0x0001 /* overrun error bit */ 104# define SCIF_ORER 0x0001 /* overrun error bit */
@@ -197,6 +201,8 @@
197 defined(CONFIG_CPU_SUBTYPE_SH7786) || \ 201 defined(CONFIG_CPU_SUBTYPE_SH7786) || \
198 defined(CONFIG_CPU_SUBTYPE_SHX3) 202 defined(CONFIG_CPU_SUBTYPE_SHX3)
199#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */ 203#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
204#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
205#define SCI_CTRL_FLAGS_REIE ((port)->type == PORT_SCIFA ? 0 : 8)
200#else 206#else
201#define SCI_CTRL_FLAGS_REIE 0 207#define SCI_CTRL_FLAGS_REIE 0
202#endif 208#endif
@@ -230,7 +236,9 @@
230#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ 236#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
231 defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 237 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
232 defined(CONFIG_CPU_SUBTYPE_SH7721) || \ 238 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
233 defined(CONFIG_ARCH_SHMOBILE) 239 defined(CONFIG_ARCH_SH7367) || \
240 defined(CONFIG_ARCH_SH7377) || \
241 defined(CONFIG_ARCH_SH7372)
234# define SCIF_ORER 0x0200 242# define SCIF_ORER 0x0200
235# define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER) 243# define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
236# define SCIF_RFDC_MASK 0x007f 244# define SCIF_RFDC_MASK 0x007f
@@ -264,7 +272,9 @@
264#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ 272#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
265 defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 273 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
266 defined(CONFIG_CPU_SUBTYPE_SH7721) || \ 274 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
267 defined(CONFIG_ARCH_SHMOBILE) 275 defined(CONFIG_ARCH_SH7367) || \
276 defined(CONFIG_ARCH_SH7377) || \
277 defined(CONFIG_ARCH_SH7372)
268# define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc) 278# define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc)
269# define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73) 279# define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73)
270# define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf) 280# define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf)
@@ -359,7 +369,10 @@
359 SCI_OUT(sci_size, sci_offset, value); \ 369 SCI_OUT(sci_size, sci_offset, value); \
360 } 370 }
361 371
362#if defined(CONFIG_CPU_SH3) || defined(CONFIG_ARCH_SHMOBILE) 372#if defined(CONFIG_CPU_SH3) || \
373 defined(CONFIG_ARCH_SH7367) || \
374 defined(CONFIG_ARCH_SH7377) || \
375 defined(CONFIG_ARCH_SH7372)
363#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) 376#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
364#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ 377#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
365 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ 378 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
@@ -370,7 +383,9 @@
370#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ 383#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
371 defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 384 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
372 defined(CONFIG_CPU_SUBTYPE_SH7721) || \ 385 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
373 defined(CONFIG_ARCH_SHMOBILE) 386 defined(CONFIG_ARCH_SH7367) || \
387 defined(CONFIG_ARCH_SH7377) || \
388 defined(CONFIG_ARCH_SH7372)
374#define SCIF_FNS(name, scif_offset, scif_size) \ 389#define SCIF_FNS(name, scif_offset, scif_size) \
375 CPU_SCIF_FNS(name, scif_offset, scif_size) 390 CPU_SCIF_FNS(name, scif_offset, scif_size)
376#else 391#else
@@ -406,7 +421,9 @@
406#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ 421#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
407 defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 422 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
408 defined(CONFIG_CPU_SUBTYPE_SH7721) || \ 423 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
409 defined(CONFIG_ARCH_SHMOBILE) 424 defined(CONFIG_ARCH_SH7367) || \
425 defined(CONFIG_ARCH_SH7377) || \
426 defined(CONFIG_ARCH_SH7372)
410 427
411SCIF_FNS(SCSMR, 0x00, 16) 428SCIF_FNS(SCSMR, 0x00, 16)
412SCIF_FNS(SCBRR, 0x04, 8) 429SCIF_FNS(SCBRR, 0x04, 8)
@@ -589,7 +606,9 @@ static inline int sci_rxd_in(struct uart_port *port)
589#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ 606#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
590 defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 607 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
591 defined(CONFIG_CPU_SUBTYPE_SH7721) || \ 608 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
592 defined(CONFIG_ARCH_SHMOBILE) 609 defined(CONFIG_ARCH_SH7367) || \
610 defined(CONFIG_ARCH_SH7377) || \
611 defined(CONFIG_ARCH_SH7372)
593#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) 612#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
594#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\ 613#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
595 defined(CONFIG_CPU_SUBTYPE_SH7724) 614 defined(CONFIG_CPU_SUBTYPE_SH7724)