aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorLaxman Dewangan <ldewangan@nvidia.com>2012-11-13 09:03:57 -0500
committerSamuel Ortiz <sameo@linux.intel.com>2012-11-20 06:21:08 -0500
commit43c1af0f4861b721def8c67ed6af2a69a4efcca3 (patch)
tree2d259472958f085a4cb644c8355ccc833ebfb138
parent10ecb80e8cb450f5b10c9aff168842c9a3c949ef (diff)
mfd: tps65910: Use regmap irq framework for interrupt support
Implement irq support of tps65910 with regmap irq framework in place of implementing locally. This reduces the code size significantly and easy to maintain. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Diffstat
-rw-r--r--drivers/mfd/tps65910-irq.c375
-rw-r--r--include/linux/mfd/tps65910.h139
2 files changed, 278 insertions, 236 deletions
diff --git a/drivers/mfd/tps65910-irq.c b/drivers/mfd/tps65910-irq.c
index 09aab3e4776d..554543a584a1 100644
--- a/drivers/mfd/tps65910-irq.c
+++ b/drivers/mfd/tps65910-irq.c
@@ -24,171 +24,184 @@
24#include <linux/gpio.h> 24#include <linux/gpio.h>
25#include <linux/mfd/tps65910.h> 25#include <linux/mfd/tps65910.h>
26 26
27/*
28 * This is a threaded IRQ handler so can access I2C/SPI. Since all
29 * interrupts are clear on read the IRQ line will be reasserted and
30 * the physical IRQ will be handled again if another interrupt is
31 * asserted while we run - in the normal course of events this is a
32 * rare occurrence so we save I2C/SPI reads. We're also assuming that
33 * it's rare to get lots of interrupts firing simultaneously so try to
34 * minimise I/O.
35 */
36static irqreturn_t tps65910_irq(int irq, void *irq_data)
37{
38 struct tps65910 *tps65910 = irq_data;
39 unsigned int reg;
40 u32 irq_sts;
41 u32 irq_mask;
42 int i;
43
44 tps65910_reg_read(tps65910, TPS65910_INT_STS, &reg);
45 irq_sts = reg;
46 tps65910_reg_read(tps65910, TPS65910_INT_STS2, &reg);
47 irq_sts |= reg << 8;
48 switch (tps65910_chip_id(tps65910)) {
49 case TPS65911:
50 tps65910_reg_read(tps65910, TPS65910_INT_STS3, &reg);
51 irq_sts |= reg << 16;
52 }
53
54 tps65910_reg_read(tps65910, TPS65910_INT_MSK, &reg);
55 irq_mask = reg;
56 tps65910_reg_read(tps65910, TPS65910_INT_MSK2, &reg);
57 irq_mask |= reg << 8;
58 switch (tps65910_chip_id(tps65910)) {
59 case TPS65911:
60 tps65910_reg_read(tps65910, TPS65910_INT_MSK3, &reg);
61 irq_mask |= reg << 16;
62 }
63
64 irq_sts &= ~irq_mask;
65
66 if (!irq_sts)
67 return IRQ_NONE;
68
69 for (i = 0; i < tps65910->irq_num; i++) {
70
71 if (!(irq_sts & (1 << i)))
72 continue;
73
74 handle_nested_irq(irq_find_mapping(tps65910->domain, i));
75 }
76
77 /* Write the STS register back to clear IRQs we handled */
78 reg = irq_sts & 0xFF;
79 irq_sts >>= 8;
80 tps65910_reg_write(tps65910, TPS65910_INT_STS, reg);
81 reg = irq_sts & 0xFF;
82 tps65910_reg_write(tps65910, TPS65910_INT_STS2, reg);
83 switch (tps65910_chip_id(tps65910)) {
84 case TPS65911:
85 reg = irq_sts >> 8;
86 tps65910_reg_write(tps65910, TPS65910_INT_STS3, reg);
87 }
88
89 return IRQ_HANDLED;
90}
91
92static void tps65910_irq_lock(struct irq_data *data)
93{
94 struct tps65910 *tps65910 = irq_data_get_irq_chip_data(data);
95
96 mutex_lock(&tps65910->irq_lock);
97}
98
99static void tps65910_irq_sync_unlock(struct irq_data *data)
100{
101 struct tps65910 *tps65910 = irq_data_get_irq_chip_data(data);
102 u32 reg_mask;
103 unsigned int reg;
104
105 tps65910_reg_read(tps65910, TPS65910_INT_MSK, &reg);
106 reg_mask = reg;
107 tps65910_reg_read(tps65910, TPS65910_INT_MSK2, &reg);
108 reg_mask |= reg << 8;
109 switch (tps65910_chip_id(tps65910)) {
110 case TPS65911:
111 tps65910_reg_read(tps65910, TPS65910_INT_MSK3, &reg);
112 reg_mask |= reg << 16;
113 }
114 27
115 if (tps65910->irq_mask != reg_mask) { 28static const struct regmap_irq tps65911_irqs[] = {
116 reg = tps65910->irq_mask & 0xFF; 29 /* INT_STS */
117 tps65910_reg_write(tps65910, TPS65910_INT_MSK, reg); 30 [TPS65911_IRQ_PWRHOLD_F] = {
118 reg = tps65910->irq_mask >> 8 & 0xFF; 31 .mask = INT_MSK_PWRHOLD_F_IT_MSK_MASK,
119 tps65910_reg_write(tps65910, TPS65910_INT_MSK2, reg); 32 .reg_offset = 0,
120 switch (tps65910_chip_id(tps65910)) { 33 },
121 case TPS65911: 34 [TPS65911_IRQ_VBAT_VMHI] = {
122 reg = tps65910->irq_mask >> 16; 35 .mask = INT_MSK_VMBHI_IT_MSK_MASK,
123 tps65910_reg_write(tps65910, TPS65910_INT_MSK3, reg); 36 .reg_offset = 0,
124 } 37 },
125 } 38 [TPS65911_IRQ_PWRON] = {
126 mutex_unlock(&tps65910->irq_lock); 39 .mask = INT_MSK_PWRON_IT_MSK_MASK,
127} 40 .reg_offset = 0,
128 41 },
129static void tps65910_irq_enable(struct irq_data *data) 42 [TPS65911_IRQ_PWRON_LP] = {
130{ 43 .mask = INT_MSK_PWRON_LP_IT_MSK_MASK,
131 struct tps65910 *tps65910 = irq_data_get_irq_chip_data(data); 44 .reg_offset = 0,
132 45 },
133 tps65910->irq_mask &= ~(1 << data->hwirq); 46 [TPS65911_IRQ_PWRHOLD_R] = {
134} 47 .mask = INT_MSK_PWRHOLD_R_IT_MSK_MASK,
135 48 .reg_offset = 0,
136static void tps65910_irq_disable(struct irq_data *data) 49 },
137{ 50 [TPS65911_IRQ_HOTDIE] = {
138 struct tps65910 *tps65910 = irq_data_get_irq_chip_data(data); 51 .mask = INT_MSK_HOTDIE_IT_MSK_MASK,
139 52 .reg_offset = 0,
140 tps65910->irq_mask |= (1 << data->hwirq); 53 },
141} 54 [TPS65911_IRQ_RTC_ALARM] = {
55 .mask = INT_MSK_RTC_ALARM_IT_MSK_MASK,
56 .reg_offset = 0,
57 },
58 [TPS65911_IRQ_RTC_PERIOD] = {
59 .mask = INT_MSK_RTC_PERIOD_IT_MSK_MASK,
60 .reg_offset = 0,
61 },
62
63 /* INT_STS2 */
64 [TPS65911_IRQ_GPIO0_R] = {
65 .mask = INT_MSK2_GPIO0_R_IT_MSK_MASK,
66 .reg_offset = 1,
67 },
68 [TPS65911_IRQ_GPIO0_F] = {
69 .mask = INT_MSK2_GPIO0_F_IT_MSK_MASK,
70 .reg_offset = 1,
71 },
72 [TPS65911_IRQ_GPIO1_R] = {
73 .mask = INT_MSK2_GPIO1_R_IT_MSK_MASK,
74 .reg_offset = 1,
75 },
76 [TPS65911_IRQ_GPIO1_F] = {
77 .mask = INT_MSK2_GPIO1_F_IT_MSK_MASK,
78 .reg_offset = 1,
79 },
80 [TPS65911_IRQ_GPIO2_R] = {
81 .mask = INT_MSK2_GPIO2_R_IT_MSK_MASK,
82 .reg_offset = 1,
83 },
84 [TPS65911_IRQ_GPIO2_F] = {
85 .mask = INT_MSK2_GPIO2_F_IT_MSK_MASK,
86 .reg_offset = 1,
87 },
88 [TPS65911_IRQ_GPIO3_R] = {
89 .mask = INT_MSK2_GPIO3_R_IT_MSK_MASK,
90 .reg_offset = 1,
91 },
92 [TPS65911_IRQ_GPIO3_F] = {
93 .mask = INT_MSK2_GPIO3_F_IT_MSK_MASK,
94 .reg_offset = 1,
95 },
96
97 /* INT_STS3 */
98 [TPS65911_IRQ_GPIO4_R] = {
99 .mask = INT_MSK3_GPIO4_R_IT_MSK_MASK,
100 .reg_offset = 2,
101 },
102 [TPS65911_IRQ_GPIO4_F] = {
103 .mask = INT_MSK3_GPIO4_F_IT_MSK_MASK,
104 .reg_offset = 2,
105 },
106 [TPS65911_IRQ_GPIO5_R] = {
107 .mask = INT_MSK3_GPIO5_R_IT_MSK_MASK,
108 .reg_offset = 2,
109 },
110 [TPS65911_IRQ_GPIO5_F] = {
111 .mask = INT_MSK3_GPIO5_F_IT_MSK_MASK,
112 .reg_offset = 2,
113 },
114 [TPS65911_IRQ_WTCHDG] = {
115 .mask = INT_MSK3_WTCHDG_IT_MSK_MASK,
116 .reg_offset = 2,
117 },
118 [TPS65911_IRQ_VMBCH2_H] = {
119 .mask = INT_MSK3_VMBCH2_H_IT_MSK_MASK,
120 .reg_offset = 2,
121 },
122 [TPS65911_IRQ_VMBCH2_L] = {
123 .mask = INT_MSK3_VMBCH2_L_IT_MSK_MASK,
124 .reg_offset = 2,
125 },
126 [TPS65911_IRQ_PWRDN] = {
127 .mask = INT_MSK3_PWRDN_IT_MSK_MASK,
128 .reg_offset = 2,
129 },
130};
142 131
143#ifdef CONFIG_PM_SLEEP 132static const struct regmap_irq tps65910_irqs[] = {
144static int tps65910_irq_set_wake(struct irq_data *data, unsigned int enable) 133 /* INT_STS */
145{ 134 [TPS65910_IRQ_VBAT_VMBDCH] = {
146 struct tps65910 *tps65910 = irq_data_get_irq_chip_data(data); 135 .mask = TPS65910_INT_MSK_VMBDCH_IT_MSK_MASK,
147 return irq_set_irq_wake(tps65910->chip_irq, enable); 136 .reg_offset = 0,
148} 137 },
149#else 138 [TPS65910_IRQ_VBAT_VMHI] = {
150#define tps65910_irq_set_wake NULL 139 .mask = TPS65910_INT_MSK_VMBHI_IT_MSK_MASK,
151#endif 140 .reg_offset = 0,
141 },
142 [TPS65910_IRQ_PWRON] = {
143 .mask = TPS65910_INT_MSK_PWRON_IT_MSK_MASK,
144 .reg_offset = 0,
145 },
146 [TPS65910_IRQ_PWRON_LP] = {
147 .mask = TPS65910_INT_MSK_PWRON_LP_IT_MSK_MASK,
148 .reg_offset = 0,
149 },
150 [TPS65910_IRQ_PWRHOLD] = {
151 .mask = TPS65910_INT_MSK_PWRHOLD_IT_MSK_MASK,
152 .reg_offset = 0,
153 },
154 [TPS65910_IRQ_HOTDIE] = {
155 .mask = TPS65910_INT_MSK_HOTDIE_IT_MSK_MASK,
156 .reg_offset = 0,
157 },
158 [TPS65910_IRQ_RTC_ALARM] = {
159 .mask = TPS65910_INT_MSK_RTC_ALARM_IT_MSK_MASK,
160 .reg_offset = 0,
161 },
162 [TPS65910_IRQ_RTC_PERIOD] = {
163 .mask = TPS65910_INT_MSK_RTC_PERIOD_IT_MSK_MASK,
164 .reg_offset = 0,
165 },
166
167 /* INT_STS2 */
168 [TPS65910_IRQ_GPIO_R] = {
169 .mask = TPS65910_INT_MSK2_GPIO0_F_IT_MSK_MASK,
170 .reg_offset = 1,
171 },
172 [TPS65910_IRQ_GPIO_F] = {
173 .mask = TPS65910_INT_MSK2_GPIO0_R_IT_MSK_MASK,
174 .reg_offset = 1,
175 },
176};
152 177
153static struct irq_chip tps65910_irq_chip = { 178static struct regmap_irq_chip tps65911_irq_chip = {
154 .name = "tps65910", 179 .name = "tps65910",
155 .irq_bus_lock = tps65910_irq_lock, 180 .irqs = tps65911_irqs,
156 .irq_bus_sync_unlock = tps65910_irq_sync_unlock, 181 .num_irqs = ARRAY_SIZE(tps65911_irqs),
157 .irq_disable = tps65910_irq_disable, 182 .num_regs = 3,
158 .irq_enable = tps65910_irq_enable, 183 .irq_reg_stride = 2,
159 .irq_set_wake = tps65910_irq_set_wake, 184 .status_base = TPS65910_INT_STS,
185 .mask_base = TPS65910_INT_MSK,
186 .ack_base = TPS65910_INT_MSK,
160}; 187};
161 188
162static int tps65910_irq_map(struct irq_domain *h, unsigned int virq, 189static struct regmap_irq_chip tps65910_irq_chip = {
163 irq_hw_number_t hw) 190 .name = "tps65910",
164{ 191 .irqs = tps65910_irqs,
165 struct tps65910 *tps65910 = h->host_data; 192 .num_irqs = ARRAY_SIZE(tps65910_irqs),
166 193 .num_regs = 2,
167 irq_set_chip_data(virq, tps65910); 194 .irq_reg_stride = 2,
168 irq_set_chip_and_handler(virq, &tps65910_irq_chip, handle_edge_irq); 195 .status_base = TPS65910_INT_STS,
169 irq_set_nested_thread(virq, 1); 196 .mask_base = TPS65910_INT_MSK,
170 197 .ack_base = TPS65910_INT_MSK,
171 /* ARM needs us to explicitly flag the IRQ as valid
172 * and will set them noprobe when we do so. */
173#ifdef CONFIG_ARM
174 set_irq_flags(virq, IRQF_VALID);
175#else
176 irq_set_noprobe(virq);
177#endif
178
179 return 0;
180}
181
182static struct irq_domain_ops tps65910_domain_ops = {
183 .map = tps65910_irq_map,
184 .xlate = irq_domain_xlate_twocell,
185}; 198};
186 199
187int tps65910_irq_init(struct tps65910 *tps65910, int irq, 200int tps65910_irq_init(struct tps65910 *tps65910, int irq,
188 struct tps65910_platform_data *pdata) 201 struct tps65910_platform_data *pdata)
189{ 202{
190 int ret; 203 int ret = 0;
191 int flags = IRQF_ONESHOT; 204 static struct regmap_irq_chip *tps6591x_irqs_chip;
192 205
193 if (!irq) { 206 if (!irq) {
194 dev_warn(tps65910->dev, "No interrupt support, no core IRQ\n"); 207 dev_warn(tps65910->dev, "No interrupt support, no core IRQ\n");
@@ -200,61 +213,31 @@ int tps65910_irq_init(struct tps65910 *tps65910, int irq,
200 return -EINVAL; 213 return -EINVAL;
201 } 214 }
202 215
216
203 switch (tps65910_chip_id(tps65910)) { 217 switch (tps65910_chip_id(tps65910)) {
204 case TPS65910: 218 case TPS65910:
205 tps65910->irq_num = TPS65910_NUM_IRQ; 219 tps6591x_irqs_chip = &tps65910_irq_chip;
206 break; 220 break;
207 case TPS65911: 221 case TPS65911:
208 tps65910->irq_num = TPS65911_NUM_IRQ; 222 tps6591x_irqs_chip = &tps65911_irq_chip;
209 break; 223 break;
210 } 224 }
211 225
212 if (pdata->irq_base > 0) {
213 pdata->irq_base = irq_alloc_descs(pdata->irq_base, 0,
214 tps65910->irq_num, -1);
215 if (pdata->irq_base < 0) {
216 dev_warn(tps65910->dev, "Failed to alloc IRQs: %d\n",
217 pdata->irq_base);
218 return pdata->irq_base;
219 }
220 }
221
222 tps65910->irq_mask = 0xFFFFFF;
223
224 mutex_init(&tps65910->irq_lock);
225 tps65910->chip_irq = irq; 226 tps65910->chip_irq = irq;
226 tps65910->irq_base = pdata->irq_base; 227 ret = regmap_add_irq_chip(tps65910->regmap, tps65910->chip_irq,
227 228 IRQF_ONESHOT, pdata->irq_base,
228 if (pdata->irq_base > 0) 229 tps6591x_irqs_chip, &tps65910->irq_data);
229 tps65910->domain = irq_domain_add_legacy(tps65910->dev->of_node, 230 if (ret < 0) {
230 tps65910->irq_num, 231 dev_warn(tps65910->dev,
231 pdata->irq_base, 232 "Failed to add irq_chip %d\n", ret);
232 0, 233 return ret;
233 &tps65910_domain_ops, tps65910);
234 else
235 tps65910->domain = irq_domain_add_linear(tps65910->dev->of_node,
236 tps65910->irq_num,
237 &tps65910_domain_ops, tps65910);
238
239 if (!tps65910->domain) {
240 dev_err(tps65910->dev, "Failed to create IRQ domain\n");
241 return -ENOMEM;
242 } 234 }
243
244 ret = request_threaded_irq(irq, NULL, tps65910_irq, flags,
245 "tps65910", tps65910);
246
247 irq_set_irq_type(irq, IRQ_TYPE_LEVEL_LOW);
248
249 if (ret != 0)
250 dev_err(tps65910->dev, "Failed to request IRQ: %d\n", ret);
251
252 return ret; 235 return ret;
253} 236}
254 237
255int tps65910_irq_exit(struct tps65910 *tps65910) 238int tps65910_irq_exit(struct tps65910 *tps65910)
256{ 239{
257 if (tps65910->chip_irq) 240 if (tps65910->chip_irq > 0)
258 free_irq(tps65910->chip_irq, tps65910); 241 regmap_del_irq_chip(tps65910->chip_irq, tps65910->irq_data);
259 return 0; 242 return 0;
260} 243}
diff --git a/include/linux/mfd/tps65910.h b/include/linux/mfd/tps65910.h
index 02e894f3ff45..b564ac29590a 100644
--- a/include/linux/mfd/tps65910.h
+++ b/include/linux/mfd/tps65910.h
@@ -572,6 +572,49 @@
572#define SPARE_SPARE_MASK 0xFF 572#define SPARE_SPARE_MASK 0xFF
573#define SPARE_SPARE_SHIFT 0 573#define SPARE_SPARE_SHIFT 0
574 574
575#define TPS65910_INT_STS_RTC_PERIOD_IT_MASK 0x80
576#define TPS65910_INT_STS_RTC_PERIOD_IT_SHIFT 7
577#define TPS65910_INT_STS_RTC_ALARM_IT_MASK 0x40
578#define TPS65910_INT_STS_RTC_ALARM_IT_SHIFT 6
579#define TPS65910_INT_STS_HOTDIE_IT_MASK 0x20
580#define TPS65910_INT_STS_HOTDIE_IT_SHIFT 5
581#define TPS65910_INT_STS_PWRHOLD_F_IT_MASK 0x10
582#define TPS65910_INT_STS_PWRHOLD_F_IT_SHIFT 4
583#define TPS65910_INT_STS_PWRON_LP_IT_MASK 0x08
584#define TPS65910_INT_STS_PWRON_LP_IT_SHIFT 3
585#define TPS65910_INT_STS_PWRON_IT_MASK 0x04
586#define TPS65910_INT_STS_PWRON_IT_SHIFT 2
587#define TPS65910_INT_STS_VMBHI_IT_MASK 0x02
588#define TPS65910_INT_STS_VMBHI_IT_SHIFT 1
589#define TPS65910_INT_STS_VMBDCH_IT_MASK 0x01
590#define TPS65910_INT_STS_VMBDCH_IT_SHIFT 0
591
592#define TPS65910_INT_MSK_RTC_PERIOD_IT_MSK_MASK 0x80
593#define TPS65910_INT_MSK_RTC_PERIOD_IT_MSK_SHIFT 7
594#define TPS65910_INT_MSK_RTC_ALARM_IT_MSK_MASK 0x40
595#define TPS65910_INT_MSK_RTC_ALARM_IT_MSK_SHIFT 6
596#define TPS65910_INT_MSK_HOTDIE_IT_MSK_MASK 0x20
597#define TPS65910_INT_MSK_HOTDIE_IT_MSK_SHIFT 5
598#define TPS65910_INT_MSK_PWRHOLD_IT_MSK_MASK 0x10
599#define TPS65910_INT_MSK_PWRHOLD_IT_MSK_SHIFT 4
600#define TPS65910_INT_MSK_PWRON_LP_IT_MSK_MASK 0x08
601#define TPS65910_INT_MSK_PWRON_LP_IT_MSK_SHIFT 3
602#define TPS65910_INT_MSK_PWRON_IT_MSK_MASK 0x04
603#define TPS65910_INT_MSK_PWRON_IT_MSK_SHIFT 2
604#define TPS65910_INT_MSK_VMBHI_IT_MSK_MASK 0x02
605#define TPS65910_INT_MSK_VMBHI_IT_MSK_SHIFT 1
606#define TPS65910_INT_MSK_VMBDCH_IT_MSK_MASK 0x01
607#define TPS65910_INT_MSK_VMBDCH_IT_MSK_SHIFT 0
608
609#define TPS65910_INT_STS2_GPIO0_F_IT_SHIFT 2
610#define TPS65910_INT_STS2_GPIO0_F_IT_MASK 0x02
611#define TPS65910_INT_STS2_GPIO0_R_IT_SHIFT 1
612#define TPS65910_INT_STS2_GPIO0_R_IT_MASK 0x01
613
614#define TPS65910_INT_MSK2_GPIO0_F_IT_MSK_SHIFT 2
615#define TPS65910_INT_MSK2_GPIO0_F_IT_MSK_MASK 0x02
616#define TPS65910_INT_MSK2_GPIO0_R_IT_MSK_SHIFT 1
617#define TPS65910_INT_MSK2_GPIO0_R_IT_MSK_MASK 0x01
575 618
576/*Register INT_STS (0x80) register.RegisterDescription */ 619/*Register INT_STS (0x80) register.RegisterDescription */
577#define INT_STS_RTC_PERIOD_IT_MASK 0x80 620#define INT_STS_RTC_PERIOD_IT_MASK 0x80
@@ -580,16 +623,16 @@
580#define INT_STS_RTC_ALARM_IT_SHIFT 6 623#define INT_STS_RTC_ALARM_IT_SHIFT 6
581#define INT_STS_HOTDIE_IT_MASK 0x20 624#define INT_STS_HOTDIE_IT_MASK 0x20
582#define INT_STS_HOTDIE_IT_SHIFT 5 625#define INT_STS_HOTDIE_IT_SHIFT 5
583#define INT_STS_PWRHOLD_IT_MASK 0x10 626#define INT_STS_PWRHOLD_R_IT_MASK 0x10
584#define INT_STS_PWRHOLD_IT_SHIFT 4 627#define INT_STS_PWRHOLD_R_IT_SHIFT 4
585#define INT_STS_PWRON_LP_IT_MASK 0x08 628#define INT_STS_PWRON_LP_IT_MASK 0x08
586#define INT_STS_PWRON_LP_IT_SHIFT 3 629#define INT_STS_PWRON_LP_IT_SHIFT 3
587#define INT_STS_PWRON_IT_MASK 0x04 630#define INT_STS_PWRON_IT_MASK 0x04
588#define INT_STS_PWRON_IT_SHIFT 2 631#define INT_STS_PWRON_IT_SHIFT 2
589#define INT_STS_VMBHI_IT_MASK 0x02 632#define INT_STS_VMBHI_IT_MASK 0x02
590#define INT_STS_VMBHI_IT_SHIFT 1 633#define INT_STS_VMBHI_IT_SHIFT 1
591#define INT_STS_VMBDCH_IT_MASK 0x01 634#define INT_STS_PWRHOLD_F_IT_MASK 0x01
592#define INT_STS_VMBDCH_IT_SHIFT 0 635#define INT_STS_PWRHOLD_F_IT_SHIFT 0
593 636
594 637
595/*Register INT_MSK (0x80) register.RegisterDescription */ 638/*Register INT_MSK (0x80) register.RegisterDescription */
@@ -599,16 +642,16 @@
599#define INT_MSK_RTC_ALARM_IT_MSK_SHIFT 6 642#define INT_MSK_RTC_ALARM_IT_MSK_SHIFT 6
600#define INT_MSK_HOTDIE_IT_MSK_MASK 0x20 643#define INT_MSK_HOTDIE_IT_MSK_MASK 0x20
601#define INT_MSK_HOTDIE_IT_MSK_SHIFT 5 644#define INT_MSK_HOTDIE_IT_MSK_SHIFT 5
602#define INT_MSK_PWRHOLD_IT_MSK_MASK 0x10 645#define INT_MSK_PWRHOLD_R_IT_MSK_MASK 0x10
603#define INT_MSK_PWRHOLD_IT_MSK_SHIFT 4 646#define INT_MSK_PWRHOLD_R_IT_MSK_SHIFT 4
604#define INT_MSK_PWRON_LP_IT_MSK_MASK 0x08 647#define INT_MSK_PWRON_LP_IT_MSK_MASK 0x08
605#define INT_MSK_PWRON_LP_IT_MSK_SHIFT 3 648#define INT_MSK_PWRON_LP_IT_MSK_SHIFT 3
606#define INT_MSK_PWRON_IT_MSK_MASK 0x04 649#define INT_MSK_PWRON_IT_MSK_MASK 0x04
607#define INT_MSK_PWRON_IT_MSK_SHIFT 2 650#define INT_MSK_PWRON_IT_MSK_SHIFT 2
608#define INT_MSK_VMBHI_IT_MSK_MASK 0x02 651#define INT_MSK_VMBHI_IT_MSK_MASK 0x02
609#define INT_MSK_VMBHI_IT_MSK_SHIFT 1 652#define INT_MSK_VMBHI_IT_MSK_SHIFT 1
610#define INT_MSK_VMBDCH_IT_MSK_MASK 0x01 653#define INT_MSK_PWRHOLD_F_IT_MSK_MASK 0x01
611#define INT_MSK_VMBDCH_IT_MSK_SHIFT 0 654#define INT_MSK_PWRHOLD_F_IT_MSK_SHIFT 0
612 655
613 656
614/*Register INT_STS2 (0x80) register.RegisterDescription */ 657/*Register INT_STS2 (0x80) register.RegisterDescription */
@@ -650,6 +693,14 @@
650 693
651 694
652/*Register INT_STS3 (0x80) register.RegisterDescription */ 695/*Register INT_STS3 (0x80) register.RegisterDescription */
696#define INT_STS3_PWRDN_IT_MASK 0x80
697#define INT_STS3_PWRDN_IT_SHIFT 7
698#define INT_STS3_VMBCH2_L_IT_MASK 0x40
699#define INT_STS3_VMBCH2_L_IT_SHIFT 6
700#define INT_STS3_VMBCH2_H_IT_MASK 0x20
701#define INT_STS3_VMBCH2_H_IT_SHIFT 5
702#define INT_STS3_WTCHDG_IT_MASK 0x10
703#define INT_STS3_WTCHDG_IT_SHIFT 4
653#define INT_STS3_GPIO5_F_IT_MASK 0x08 704#define INT_STS3_GPIO5_F_IT_MASK 0x08
654#define INT_STS3_GPIO5_F_IT_SHIFT 3 705#define INT_STS3_GPIO5_F_IT_SHIFT 3
655#define INT_STS3_GPIO5_R_IT_MASK 0x04 706#define INT_STS3_GPIO5_R_IT_MASK 0x04
@@ -661,6 +712,14 @@
661 712
662 713
663/*Register INT_MSK3 (0x80) register.RegisterDescription */ 714/*Register INT_MSK3 (0x80) register.RegisterDescription */
715#define INT_MSK3_PWRDN_IT_MSK_MASK 0x80
716#define INT_MSK3_PWRDN_IT_MSK_SHIFT 7
717#define INT_MSK3_VMBCH2_L_IT_MSK_MASK 0x40
718#define INT_MSK3_VMBCH2_L_IT_MSK_SHIFT 6
719#define INT_MSK3_VMBCH2_H_IT_MSK_MASK 0x20
720#define INT_MSK3_VMBCH2_H_IT_MSK_SHIFT 5
721#define INT_MSK3_WTCHDG_IT_MSK_MASK 0x10
722#define INT_MSK3_WTCHDG_IT_MSK_SHIFT 4
664#define INT_MSK3_GPIO5_F_IT_MSK_MASK 0x08 723#define INT_MSK3_GPIO5_F_IT_MSK_MASK 0x08
665#define INT_MSK3_GPIO5_F_IT_MSK_SHIFT 3 724#define INT_MSK3_GPIO5_F_IT_MSK_SHIFT 3
666#define INT_MSK3_GPIO5_R_IT_MSK_MASK 0x04 725#define INT_MSK3_GPIO5_R_IT_MSK_MASK 0x04
@@ -721,34 +780,32 @@
721#define TPS65910_IRQ_GPIO_F 9 780#define TPS65910_IRQ_GPIO_F 9
722#define TPS65910_NUM_IRQ 10 781#define TPS65910_NUM_IRQ 10
723 782
724#define TPS65911_IRQ_VBAT_VMBDCH 0 783#define TPS65911_IRQ_PWRHOLD_F 0
725#define TPS65911_IRQ_VBAT_VMBDCH2L 1 784#define TPS65911_IRQ_VBAT_VMHI 1
726#define TPS65911_IRQ_VBAT_VMBDCH2H 2 785#define TPS65911_IRQ_PWRON 2
727#define TPS65911_IRQ_VBAT_VMHI 3 786#define TPS65911_IRQ_PWRON_LP 3
728#define TPS65911_IRQ_PWRON 4 787#define TPS65911_IRQ_PWRHOLD_R 4
729#define TPS65911_IRQ_PWRON_LP 5 788#define TPS65911_IRQ_HOTDIE 5
730#define TPS65911_IRQ_PWRHOLD_F 6 789#define TPS65911_IRQ_RTC_ALARM 6
731#define TPS65911_IRQ_PWRHOLD_R 7 790#define TPS65911_IRQ_RTC_PERIOD 7
732#define TPS65911_IRQ_HOTDIE 8 791#define TPS65911_IRQ_GPIO0_R 8
733#define TPS65911_IRQ_RTC_ALARM 9 792#define TPS65911_IRQ_GPIO0_F 9
734#define TPS65911_IRQ_RTC_PERIOD 10 793#define TPS65911_IRQ_GPIO1_R 10
735#define TPS65911_IRQ_GPIO0_R 11 794#define TPS65911_IRQ_GPIO1_F 11
736#define TPS65911_IRQ_GPIO0_F 12 795#define TPS65911_IRQ_GPIO2_R 12
737#define TPS65911_IRQ_GPIO1_R 13 796#define TPS65911_IRQ_GPIO2_F 13
738#define TPS65911_IRQ_GPIO1_F 14 797#define TPS65911_IRQ_GPIO3_R 14
739#define TPS65911_IRQ_GPIO2_R 15 798#define TPS65911_IRQ_GPIO3_F 15
740#define TPS65911_IRQ_GPIO2_F 16 799#define TPS65911_IRQ_GPIO4_R 16
741#define TPS65911_IRQ_GPIO3_R 17 800#define TPS65911_IRQ_GPIO4_F 17
742#define TPS65911_IRQ_GPIO3_F 18 801#define TPS65911_IRQ_GPIO5_R 18
743#define TPS65911_IRQ_GPIO4_R 19 802#define TPS65911_IRQ_GPIO5_F 19
744#define TPS65911_IRQ_GPIO4_F 20 803#define TPS65911_IRQ_WTCHDG 20
745#define TPS65911_IRQ_GPIO5_R 21 804#define TPS65911_IRQ_VMBCH2_H 21
746#define TPS65911_IRQ_GPIO5_F 22 805#define TPS65911_IRQ_VMBCH2_L 22
747#define TPS65911_IRQ_WTCHDG 23 806#define TPS65911_IRQ_PWRDN 23
748#define TPS65911_IRQ_PWRDN 24 807
749 808#define TPS65911_NUM_IRQ 24
750#define TPS65911_NUM_IRQ 25
751
752 809
753/* GPIO Register Definitions */ 810/* GPIO Register Definitions */
754#define TPS65910_GPIO_DEB BIT(2) 811#define TPS65910_GPIO_DEB BIT(2)
@@ -848,11 +905,8 @@ struct tps65910 {
848 struct tps65910_board *of_plat_data; 905 struct tps65910_board *of_plat_data;
849 906
850 /* IRQ Handling */ 907 /* IRQ Handling */
851 struct mutex irq_lock;
852 int chip_irq; 908 int chip_irq;
853 int irq_base; 909 struct regmap_irq_chip_data *irq_data;
854 int irq_num;
855 u32 irq_mask;
856 struct irq_domain *domain; 910 struct irq_domain *domain;
857}; 911};
858 912
@@ -900,4 +954,9 @@ static inline int tps65910_reg_update_bits(struct tps65910 *tps65910, u8 reg,
900 return regmap_update_bits(tps65910->regmap, reg, mask, val); 954 return regmap_update_bits(tps65910->regmap, reg, mask, val);
901} 955}
902 956
957static inline int tps65910_irq_get_virq(struct tps65910 *tps65910, int irq)
958{
959 return regmap_irq_get_virq(tps65910->irq_data, irq);
960}
961
903#endif /* __LINUX_MFD_TPS65910_H */ 962#endif /* __LINUX_MFD_TPS65910_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-03 18:25:28 -0500