diff options
author | Greg Kroah-Hartman <gregkh@suse.de> | 2010-05-17 13:33:41 -0400 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@suse.de> | 2010-05-20 16:21:46 -0400 |
commit | 42047699fae79190fd7ebd0b02fa4bde016adc04 (patch) | |
tree | 336e89513a29c0eb862d006703cfb53c5c56e2cc | |
parent | 7f1cccd3ec8789e52897bc34420ca81a5e2edeab (diff) |
USB: mct_u232.h: checkpatch cleanups
Minor whitespace cleanups to make checkpatch happy.
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
-rw-r--r-- | drivers/usb/serial/mct_u232.h | 254 |
1 files changed, 133 insertions, 121 deletions
diff --git a/drivers/usb/serial/mct_u232.h b/drivers/usb/serial/mct_u232.h index 7417d5ce1e23..3a3f5e6b8f96 100644 --- a/drivers/usb/serial/mct_u232.h +++ b/drivers/usb/serial/mct_u232.h | |||
@@ -42,36 +42,44 @@ | |||
42 | #define MCT_U232_SET_REQUEST_TYPE 0x40 | 42 | #define MCT_U232_SET_REQUEST_TYPE 0x40 |
43 | #define MCT_U232_GET_REQUEST_TYPE 0xc0 | 43 | #define MCT_U232_GET_REQUEST_TYPE 0xc0 |
44 | 44 | ||
45 | #define MCT_U232_GET_MODEM_STAT_REQUEST 2 /* Get Modem Status Register (MSR) */ | 45 | /* Get Modem Status Register (MSR) */ |
46 | #define MCT_U232_GET_MODEM_STAT_SIZE 1 | 46 | #define MCT_U232_GET_MODEM_STAT_REQUEST 2 |
47 | #define MCT_U232_GET_MODEM_STAT_SIZE 1 | ||
47 | 48 | ||
48 | #define MCT_U232_GET_LINE_CTRL_REQUEST 6 /* Get Line Control Register (LCR) */ | 49 | /* Get Line Control Register (LCR) */ |
49 | #define MCT_U232_GET_LINE_CTRL_SIZE 1 /* ... not used by this driver */ | 50 | /* ... not used by this driver */ |
51 | #define MCT_U232_GET_LINE_CTRL_REQUEST 6 | ||
52 | #define MCT_U232_GET_LINE_CTRL_SIZE 1 | ||
50 | 53 | ||
51 | #define MCT_U232_SET_BAUD_RATE_REQUEST 5 /* Set Baud Rate Divisor */ | 54 | /* Set Baud Rate Divisor */ |
52 | #define MCT_U232_SET_BAUD_RATE_SIZE 4 | 55 | #define MCT_U232_SET_BAUD_RATE_REQUEST 5 |
56 | #define MCT_U232_SET_BAUD_RATE_SIZE 4 | ||
53 | 57 | ||
54 | #define MCT_U232_SET_LINE_CTRL_REQUEST 7 /* Set Line Control Register (LCR) */ | 58 | /* Set Line Control Register (LCR) */ |
55 | #define MCT_U232_SET_LINE_CTRL_SIZE 1 | 59 | #define MCT_U232_SET_LINE_CTRL_REQUEST 7 |
60 | #define MCT_U232_SET_LINE_CTRL_SIZE 1 | ||
56 | 61 | ||
57 | #define MCT_U232_SET_MODEM_CTRL_REQUEST 10 /* Set Modem Control Register (MCR) */ | 62 | /* Set Modem Control Register (MCR) */ |
58 | #define MCT_U232_SET_MODEM_CTRL_SIZE 1 | 63 | #define MCT_U232_SET_MODEM_CTRL_REQUEST 10 |
64 | #define MCT_U232_SET_MODEM_CTRL_SIZE 1 | ||
59 | 65 | ||
60 | /* This USB device request code is not well understood. It is transmitted by | 66 | /* |
61 | the MCT-supplied Windows driver whenever the baud rate changes. | 67 | * This USB device request code is not well understood. It is transmitted by |
62 | */ | 68 | * the MCT-supplied Windows driver whenever the baud rate changes. |
63 | #define MCT_U232_SET_UNKNOWN1_REQUEST 11 /* Unknown functionality */ | 69 | */ |
64 | #define MCT_U232_SET_UNKNOWN1_SIZE 1 | 70 | #define MCT_U232_SET_UNKNOWN1_REQUEST 11 /* Unknown functionality */ |
71 | #define MCT_U232_SET_UNKNOWN1_SIZE 1 | ||
65 | 72 | ||
66 | /* This USB device request code appears to control whether CTS is required | 73 | /* |
67 | during transmission. | 74 | * This USB device request code appears to control whether CTS is required |
68 | 75 | * during transmission. | |
69 | Sending a zero byte allows data transmission to a device which is not | 76 | * |
70 | asserting CTS. Sending a '1' byte will cause transmission to be deferred | 77 | * Sending a zero byte allows data transmission to a device which is not |
71 | until the device asserts CTS. | 78 | * asserting CTS. Sending a '1' byte will cause transmission to be deferred |
72 | */ | 79 | * until the device asserts CTS. |
73 | #define MCT_U232_SET_CTS_REQUEST 12 | 80 | */ |
74 | #define MCT_U232_SET_CTS_SIZE 1 | 81 | #define MCT_U232_SET_CTS_REQUEST 12 |
82 | #define MCT_U232_SET_CTS_SIZE 1 | ||
75 | 83 | ||
76 | #define MCT_U232_MAX_SIZE 4 /* of MCT_XXX_SIZE */ | 84 | #define MCT_U232_MAX_SIZE 4 /* of MCT_XXX_SIZE */ |
77 | 85 | ||
@@ -81,7 +89,8 @@ | |||
81 | * and "Intel solution". They are the regular MCT and "Sitecom" for us. | 89 | * and "Intel solution". They are the regular MCT and "Sitecom" for us. |
82 | * This is pointless to document in the header, see the code for the bits. | 90 | * This is pointless to document in the header, see the code for the bits. |
83 | */ | 91 | */ |
84 | static int mct_u232_calculate_baud_rate(struct usb_serial *serial, speed_t value, speed_t *result); | 92 | static int mct_u232_calculate_baud_rate(struct usb_serial *serial, |
93 | speed_t value, speed_t *result); | ||
85 | 94 | ||
86 | /* | 95 | /* |
87 | * Line Control Register (LCR) | 96 | * Line Control Register (LCR) |
@@ -125,16 +134,16 @@ static int mct_u232_calculate_baud_rate(struct usb_serial *serial, speed_t value | |||
125 | /* | 134 | /* |
126 | * Line Status Register (LSR) | 135 | * Line Status Register (LSR) |
127 | */ | 136 | */ |
128 | #define MCT_U232_LSR_INDEX 1 /* data[index] */ | 137 | #define MCT_U232_LSR_INDEX 1 /* data[index] */ |
129 | #define MCT_U232_LSR_ERR 0x80 /* OE | PE | FE | BI */ | 138 | #define MCT_U232_LSR_ERR 0x80 /* OE | PE | FE | BI */ |
130 | #define MCT_U232_LSR_TEMT 0x40 /* transmit register empty */ | 139 | #define MCT_U232_LSR_TEMT 0x40 /* transmit register empty */ |
131 | #define MCT_U232_LSR_THRE 0x20 /* transmit holding register empty */ | 140 | #define MCT_U232_LSR_THRE 0x20 /* transmit holding register empty */ |
132 | #define MCT_U232_LSR_BI 0x10 /* break indicator */ | 141 | #define MCT_U232_LSR_BI 0x10 /* break indicator */ |
133 | #define MCT_U232_LSR_FE 0x08 /* framing error */ | 142 | #define MCT_U232_LSR_FE 0x08 /* framing error */ |
134 | #define MCT_U232_LSR_OE 0x02 /* overrun error */ | 143 | #define MCT_U232_LSR_OE 0x02 /* overrun error */ |
135 | #define MCT_U232_LSR_PE 0x04 /* parity error */ | 144 | #define MCT_U232_LSR_PE 0x04 /* parity error */ |
136 | #define MCT_U232_LSR_OE 0x02 /* overrun error */ | 145 | #define MCT_U232_LSR_OE 0x02 /* overrun error */ |
137 | #define MCT_U232_LSR_DR 0x01 /* receive data ready */ | 146 | #define MCT_U232_LSR_DR 0x01 /* receive data ready */ |
138 | 147 | ||
139 | 148 | ||
140 | /* ----------------------------------------------------------------------------- | 149 | /* ----------------------------------------------------------------------------- |
@@ -143,10 +152,10 @@ static int mct_u232_calculate_baud_rate(struct usb_serial *serial, speed_t value | |||
143 | * | 152 | * |
144 | * The technical details of the device have been acquired be using "SniffUSB" | 153 | * The technical details of the device have been acquired be using "SniffUSB" |
145 | * and the vendor-supplied device driver (version 2.3A) under Windows98. To | 154 | * and the vendor-supplied device driver (version 2.3A) under Windows98. To |
146 | * identify the USB vendor-specific requests and to assign them to terminal | 155 | * identify the USB vendor-specific requests and to assign them to terminal |
147 | * settings (flow control, baud rate, etc.) the program "SerialSettings" from | 156 | * settings (flow control, baud rate, etc.) the program "SerialSettings" from |
148 | * William G. Greathouse has been proven to be very useful. I also used the | 157 | * William G. Greathouse has been proven to be very useful. I also used the |
149 | * Win98 "HyperTerminal" and "usb-robot" on Linux for testing. The results and | 158 | * Win98 "HyperTerminal" and "usb-robot" on Linux for testing. The results and |
150 | * observations are summarized below: | 159 | * observations are summarized below: |
151 | * | 160 | * |
152 | * The USB requests seem to be directly mapped to the registers of a 8250, | 161 | * The USB requests seem to be directly mapped to the registers of a 8250, |
@@ -186,33 +195,33 @@ static int mct_u232_calculate_baud_rate(struct usb_serial *serial, speed_t value | |||
186 | * Data: LCR (see below) | 195 | * Data: LCR (see below) |
187 | * | 196 | * |
188 | * Bit 7: Divisor Latch Access Bit (DLAB). When set, access to the data | 197 | * Bit 7: Divisor Latch Access Bit (DLAB). When set, access to the data |
189 | * transmit/receive register (THR/RBR) and the Interrupt Enable Register | 198 | * transmit/receive register (THR/RBR) and the Interrupt Enable Register |
190 | * (IER) is disabled. Any access to these ports is now redirected to the | 199 | * (IER) is disabled. Any access to these ports is now redirected to the |
191 | * Divisor Latch Registers. Setting this bit, loading the Divisor | 200 | * Divisor Latch Registers. Setting this bit, loading the Divisor |
192 | * Registers, and clearing DLAB should be done with interrupts disabled. | 201 | * Registers, and clearing DLAB should be done with interrupts disabled. |
193 | * Bit 6: Set Break. When set to "1", the transmitter begins to transmit | 202 | * Bit 6: Set Break. When set to "1", the transmitter begins to transmit |
194 | * continuous Spacing until this bit is set to "0". This overrides any | 203 | * continuous Spacing until this bit is set to "0". This overrides any |
195 | * bits of characters that are being transmitted. | 204 | * bits of characters that are being transmitted. |
196 | * Bit 5: Stick Parity. When parity is enabled, setting this bit causes parity | 205 | * Bit 5: Stick Parity. When parity is enabled, setting this bit causes parity |
197 | * to always be "1" or "0", based on the value of Bit 4. | 206 | * to always be "1" or "0", based on the value of Bit 4. |
198 | * Bit 4: Even Parity Select (EPS). When parity is enabled and Bit 5 is "0", | 207 | * Bit 4: Even Parity Select (EPS). When parity is enabled and Bit 5 is "0", |
199 | * setting this bit causes even parity to be transmitted and expected. | 208 | * setting this bit causes even parity to be transmitted and expected. |
200 | * Otherwise, odd parity is used. | 209 | * Otherwise, odd parity is used. |
201 | * Bit 3: Parity Enable (PEN). When set to "1", a parity bit is inserted | 210 | * Bit 3: Parity Enable (PEN). When set to "1", a parity bit is inserted |
202 | * between the last bit of the data and the Stop Bit. The UART will also | 211 | * between the last bit of the data and the Stop Bit. The UART will also |
203 | * expect parity to be present in the received data. | 212 | * expect parity to be present in the received data. |
204 | * Bit 2: Number of Stop Bits (STB). If set to "1" and using 5-bit data words, | 213 | * Bit 2: Number of Stop Bits (STB). If set to "1" and using 5-bit data words, |
205 | * 1.5 Stop Bits are transmitted and expected in each data word. For | 214 | * 1.5 Stop Bits are transmitted and expected in each data word. For |
206 | * 6, 7 and 8-bit data words, 2 Stop Bits are transmitted and expected. | 215 | * 6, 7 and 8-bit data words, 2 Stop Bits are transmitted and expected. |
207 | * When this bit is set to "0", one Stop Bit is used on each data word. | 216 | * When this bit is set to "0", one Stop Bit is used on each data word. |
208 | * Bit 1: Word Length Select Bit #1 (WLSB1) | 217 | * Bit 1: Word Length Select Bit #1 (WLSB1) |
209 | * Bit 0: Word Length Select Bit #0 (WLSB0) | 218 | * Bit 0: Word Length Select Bit #0 (WLSB0) |
210 | * Together these bits specify the number of bits in each data word. | 219 | * Together these bits specify the number of bits in each data word. |
211 | * 1 0 Word Length | 220 | * 1 0 Word Length |
212 | * 0 0 5 Data Bits | 221 | * 0 0 5 Data Bits |
213 | * 0 1 6 Data Bits | 222 | * 0 1 6 Data Bits |
214 | * 1 0 7 Data Bits | 223 | * 1 0 7 Data Bits |
215 | * 1 1 8 Data Bits | 224 | * 1 1 8 Data Bits |
216 | * | 225 | * |
217 | * SniffUSB observations: Bit 7 seems not to be used. There seem to be two bugs | 226 | * SniffUSB observations: Bit 7 seems not to be used. There seem to be two bugs |
218 | * in the Win98 driver: the break does not work (bit 6 is not asserted) and the | 227 | * in the Win98 driver: the break does not work (bit 6 is not asserted) and the |
@@ -234,20 +243,20 @@ static int mct_u232_calculate_baud_rate(struct usb_serial *serial, speed_t value | |||
234 | * Bit 6: Reserved, always 0. | 243 | * Bit 6: Reserved, always 0. |
235 | * Bit 5: Reserved, always 0. | 244 | * Bit 5: Reserved, always 0. |
236 | * Bit 4: Loop-Back Enable. When set to "1", the UART transmitter and receiver | 245 | * Bit 4: Loop-Back Enable. When set to "1", the UART transmitter and receiver |
237 | * are internally connected together to allow diagnostic operations. In | 246 | * are internally connected together to allow diagnostic operations. In |
238 | * addition, the UART modem control outputs are connected to the UART | 247 | * addition, the UART modem control outputs are connected to the UART |
239 | * modem control inputs. CTS is connected to RTS, DTR is connected to | 248 | * modem control inputs. CTS is connected to RTS, DTR is connected to |
240 | * DSR, OUT1 is connected to RI, and OUT 2 is connected to DCD. | 249 | * DSR, OUT1 is connected to RI, and OUT 2 is connected to DCD. |
241 | * Bit 3: OUT 2. An auxiliary output that the host processor may set high or | 250 | * Bit 3: OUT 2. An auxiliary output that the host processor may set high or |
242 | * low. In the IBM PC serial adapter (and most clones), OUT 2 is used | 251 | * low. In the IBM PC serial adapter (and most clones), OUT 2 is used |
243 | * to tri-state (disable) the interrupt signal from the | 252 | * to tri-state (disable) the interrupt signal from the |
244 | * 8250/16450/16550 UART. | 253 | * 8250/16450/16550 UART. |
245 | * Bit 2: OUT 1. An auxiliary output that the host processor may set high or | 254 | * Bit 2: OUT 1. An auxiliary output that the host processor may set high or |
246 | * low. This output is not used on the IBM PC serial adapter. | 255 | * low. This output is not used on the IBM PC serial adapter. |
247 | * Bit 1: Request to Send (RTS). When set to "1", the output of the UART -RTS | 256 | * Bit 1: Request to Send (RTS). When set to "1", the output of the UART -RTS |
248 | * line is Low (Active). | 257 | * line is Low (Active). |
249 | * Bit 0: Data Terminal Ready (DTR). When set to "1", the output of the UART | 258 | * Bit 0: Data Terminal Ready (DTR). When set to "1", the output of the UART |
250 | * -DTR line is Low (Active). | 259 | * -DTR line is Low (Active). |
251 | * | 260 | * |
252 | * SniffUSB observations: Bit 2 and 4 seem not to be used but bit 3 has been | 261 | * SniffUSB observations: Bit 2 and 4 seem not to be used but bit 3 has been |
253 | * seen _always_ set. | 262 | * seen _always_ set. |
@@ -264,22 +273,22 @@ static int mct_u232_calculate_baud_rate(struct usb_serial *serial, speed_t value | |||
264 | * Data: MSR (see below) | 273 | * Data: MSR (see below) |
265 | * | 274 | * |
266 | * Bit 7: Data Carrier Detect (CD). Reflects the state of the DCD line on the | 275 | * Bit 7: Data Carrier Detect (CD). Reflects the state of the DCD line on the |
267 | * UART. | 276 | * UART. |
268 | * Bit 6: Ring Indicator (RI). Reflects the state of the RI line on the UART. | 277 | * Bit 6: Ring Indicator (RI). Reflects the state of the RI line on the UART. |
269 | * Bit 5: Data Set Ready (DSR). Reflects the state of the DSR line on the UART. | 278 | * Bit 5: Data Set Ready (DSR). Reflects the state of the DSR line on the UART. |
270 | * Bit 4: Clear To Send (CTS). Reflects the state of the CTS line on the UART. | 279 | * Bit 4: Clear To Send (CTS). Reflects the state of the CTS line on the UART. |
271 | * Bit 3: Delta Data Carrier Detect (DDCD). Set to "1" if the -DCD line has | 280 | * Bit 3: Delta Data Carrier Detect (DDCD). Set to "1" if the -DCD line has |
272 | * changed state one more more times since the last time the MSR was | 281 | * changed state one more more times since the last time the MSR was |
273 | * read by the host. | 282 | * read by the host. |
274 | * Bit 2: Trailing Edge Ring Indicator (TERI). Set to "1" if the -RI line has | 283 | * Bit 2: Trailing Edge Ring Indicator (TERI). Set to "1" if the -RI line has |
275 | * had a low to high transition since the last time the MSR was read by | 284 | * had a low to high transition since the last time the MSR was read by |
276 | * the host. | 285 | * the host. |
277 | * Bit 1: Delta Data Set Ready (DDSR). Set to "1" if the -DSR line has changed | 286 | * Bit 1: Delta Data Set Ready (DDSR). Set to "1" if the -DSR line has changed |
278 | * state one more more times since the last time the MSR was read by the | 287 | * state one more more times since the last time the MSR was read by the |
279 | * host. | 288 | * host. |
280 | * Bit 0: Delta Clear To Send (DCTS). Set to "1" if the -CTS line has changed | 289 | * Bit 0: Delta Clear To Send (DCTS). Set to "1" if the -CTS line has changed |
281 | * state one more times since the last time the MSR was read by the | 290 | * state one more times since the last time the MSR was read by the |
282 | * host. | 291 | * host. |
283 | * | 292 | * |
284 | * SniffUSB observations: the MSR is also returned as first byte on the | 293 | * SniffUSB observations: the MSR is also returned as first byte on the |
285 | * interrupt-in endpoint 0x83 to signal changes of modem status lines. The USB | 294 | * interrupt-in endpoint 0x83 to signal changes of modem status lines. The USB |
@@ -290,31 +299,34 @@ static int mct_u232_calculate_baud_rate(struct usb_serial *serial, speed_t value | |||
290 | * -------------------------- | 299 | * -------------------------- |
291 | * | 300 | * |
292 | * Bit 7 Error in Receiver FIFO. On the 8250/16450 UART, this bit is zero. | 301 | * Bit 7 Error in Receiver FIFO. On the 8250/16450 UART, this bit is zero. |
293 | * This bit is set to "1" when any of the bytes in the FIFO have one or | 302 | * This bit is set to "1" when any of the bytes in the FIFO have one |
294 | * more of the following error conditions: PE, FE, or BI. | 303 | * or more of the following error conditions: PE, FE, or BI. |
295 | * Bit 6 Transmitter Empty (TEMT). When set to "1", there are no words | 304 | * Bit 6 Transmitter Empty (TEMT). When set to "1", there are no words |
296 | * remaining in the transmit FIFO or the transmit shift register. The | 305 | * remaining in the transmit FIFO or the transmit shift register. The |
297 | * transmitter is completely idle. | 306 | * transmitter is completely idle. |
298 | * Bit 5 Transmitter Holding Register Empty (THRE). When set to "1", the FIFO | 307 | * Bit 5 Transmitter Holding Register Empty (THRE). When set to "1", the |
299 | * (or holding register) now has room for at least one additional word | 308 | * FIFO (or holding register) now has room for at least one additional |
300 | * to transmit. The transmitter may still be transmitting when this bit | 309 | * word to transmit. The transmitter may still be transmitting when |
301 | * is set to "1". | 310 | * this bit is set to "1". |
302 | * Bit 4 Break Interrupt (BI). The receiver has detected a Break signal. | 311 | * Bit 4 Break Interrupt (BI). The receiver has detected a Break signal. |
303 | * Bit 3 Framing Error (FE). A Start Bit was detected but the Stop Bit did not | 312 | * Bit 3 Framing Error (FE). A Start Bit was detected but the Stop Bit did |
304 | * appear at the expected time. The received word is probably garbled. | 313 | * not appear at the expected time. The received word is probably |
305 | * Bit 2 Parity Error (PE). The parity bit was incorrect for the word received. | 314 | * garbled. |
306 | * Bit 1 Overrun Error (OE). A new word was received and there was no room in | 315 | * Bit 2 Parity Error (PE). The parity bit was incorrect for the word |
307 | * the receive buffer. The newly-arrived word in the shift register is | 316 | * received. |
308 | * discarded. On 8250/16450 UARTs, the word in the holding register is | 317 | * Bit 1 Overrun Error (OE). A new word was received and there was no room |
309 | * discarded and the newly- arrived word is put in the holding register. | 318 | * in the receive buffer. The newly-arrived word in the shift register |
319 | * is discarded. On 8250/16450 UARTs, the word in the holding register | ||
320 | * is discarded and the newly- arrived word is put in the holding | ||
321 | * register. | ||
310 | * Bit 0 Data Ready (DR). One or more words are in the receive FIFO that the | 322 | * Bit 0 Data Ready (DR). One or more words are in the receive FIFO that the |
311 | * host may read. A word must be completely received and moved from the | 323 | * host may read. A word must be completely received and moved from |
312 | * shift register into the FIFO (or holding register for 8250/16450 | 324 | * the shift register into the FIFO (or holding register for |
313 | * designs) before this bit is set. | 325 | * 8250/16450 designs) before this bit is set. |
314 | * | 326 | * |
315 | * SniffUSB observations: the LSR is returned as second byte on the interrupt-in | 327 | * SniffUSB observations: the LSR is returned as second byte on the |
316 | * endpoint 0x83 to signal error conditions. Such errors have been seen with | 328 | * interrupt-in endpoint 0x83 to signal error conditions. Such errors have |
317 | * minicom/zmodem transfers (CRC errors). | 329 | * been seen with minicom/zmodem transfers (CRC errors). |
318 | * | 330 | * |
319 | * | 331 | * |
320 | * Unknown #1 | 332 | * Unknown #1 |
@@ -364,16 +376,16 @@ static int mct_u232_calculate_baud_rate(struct usb_serial *serial, speed_t value | |||
364 | * -------------- | 376 | * -------------- |
365 | * | 377 | * |
366 | * SniffUSB observations: the bulk-out endpoint 0x1 and interrupt-in endpoint | 378 | * SniffUSB observations: the bulk-out endpoint 0x1 and interrupt-in endpoint |
367 | * 0x81 is used to transmit and receive characters. The second interrupt-in | 379 | * 0x81 is used to transmit and receive characters. The second interrupt-in |
368 | * endpoint 0x83 signals exceptional conditions like modem line changes and | 380 | * endpoint 0x83 signals exceptional conditions like modem line changes and |
369 | * errors. The first byte returned is the MSR and the second byte the LSR. | 381 | * errors. The first byte returned is the MSR and the second byte the LSR. |
370 | * | 382 | * |
371 | * | 383 | * |
372 | * Other observations | 384 | * Other observations |
373 | * ------------------ | 385 | * ------------------ |
374 | * | 386 | * |
375 | * Queued bulk transfers like used in visor.c did not work. | 387 | * Queued bulk transfers like used in visor.c did not work. |
376 | * | 388 | * |
377 | * | 389 | * |
378 | * Properties of the USB device used (as found in /var/log/messages) | 390 | * Properties of the USB device used (as found in /var/log/messages) |
379 | * ----------------------------------------------------------------- | 391 | * ----------------------------------------------------------------- |
@@ -411,26 +423,26 @@ static int mct_u232_calculate_baud_rate(struct usb_serial *serial, speed_t value | |||
411 | * bInterface Class:SubClass:Protocol = 00:00:00 | 423 | * bInterface Class:SubClass:Protocol = 00:00:00 |
412 | * iInterface = 00 | 424 | * iInterface = 00 |
413 | * Endpoint: | 425 | * Endpoint: |
414 | * bLength = 7 | 426 | * bLength = 7 |
415 | * bDescriptorType = 05 | 427 | * bDescriptorType = 05 |
416 | * bEndpointAddress = 81 (in) | 428 | * bEndpointAddress = 81 (in) |
417 | * bmAttributes = 03 (Interrupt) | 429 | * bmAttributes = 03 (Interrupt) |
418 | * wMaxPacketSize = 0040 | 430 | * wMaxPacketSize = 0040 |
419 | * bInterval = 02 | 431 | * bInterval = 02 |
420 | * Endpoint: | 432 | * Endpoint: |
421 | * bLength = 7 | 433 | * bLength = 7 |
422 | * bDescriptorType = 05 | 434 | * bDescriptorType = 05 |
423 | * bEndpointAddress = 01 (out) | 435 | * bEndpointAddress = 01 (out) |
424 | * bmAttributes = 02 (Bulk) | 436 | * bmAttributes = 02 (Bulk) |
425 | * wMaxPacketSize = 0040 | 437 | * wMaxPacketSize = 0040 |
426 | * bInterval = 00 | 438 | * bInterval = 00 |
427 | * Endpoint: | 439 | * Endpoint: |
428 | * bLength = 7 | 440 | * bLength = 7 |
429 | * bDescriptorType = 05 | 441 | * bDescriptorType = 05 |
430 | * bEndpointAddress = 83 (in) | 442 | * bEndpointAddress = 83 (in) |
431 | * bmAttributes = 03 (Interrupt) | 443 | * bmAttributes = 03 (Interrupt) |
432 | * wMaxPacketSize = 0002 | 444 | * wMaxPacketSize = 0002 |
433 | * bInterval = 02 | 445 | * bInterval = 02 |
434 | * | 446 | * |
435 | * | 447 | * |
436 | * Hardware details (added by Martin Hamilton, 2001/12/06) | 448 | * Hardware details (added by Martin Hamilton, 2001/12/06) |
@@ -440,7 +452,7 @@ static int mct_u232_calculate_baud_rate(struct usb_serial *serial, speed_t value | |||
440 | * adaptor, which turns out to simply be a re-badged U232-P9. We | 452 | * adaptor, which turns out to simply be a re-badged U232-P9. We |
441 | * know this because there is a sticky label on the circuit board | 453 | * know this because there is a sticky label on the circuit board |
442 | * which says "U232-P9" ;-) | 454 | * which says "U232-P9" ;-) |
443 | * | 455 | * |
444 | * The circuit board inside the adaptor contains a Philips PDIUSBD12 | 456 | * The circuit board inside the adaptor contains a Philips PDIUSBD12 |
445 | * USB endpoint chip and a Philips P87C52UBAA microcontroller with | 457 | * USB endpoint chip and a Philips P87C52UBAA microcontroller with |
446 | * embedded UART. Exhaustive documentation for these is available at: | 458 | * embedded UART. Exhaustive documentation for these is available at: |
@@ -449,7 +461,7 @@ static int mct_u232_calculate_baud_rate(struct usb_serial *serial, speed_t value | |||
449 | * http://www.semiconductors.philips.com/pip/pdiusbd12 | 461 | * http://www.semiconductors.philips.com/pip/pdiusbd12 |
450 | * | 462 | * |
451 | * Thanks to Julian Highfield for the pointer to the Philips database. | 463 | * Thanks to Julian Highfield for the pointer to the Philips database. |
452 | * | 464 | * |
453 | */ | 465 | */ |
454 | 466 | ||
455 | #endif /* __LINUX_USB_SERIAL_MCT_U232_H */ | 467 | #endif /* __LINUX_USB_SERIAL_MCT_U232_H */ |