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authorTomasz Figa <t.figa@samsung.com>2014-07-02 11:41:01 -0400
committerLinus Walleij <linus.walleij@linaro.org>2014-07-11 08:08:37 -0400
commit2e4a4fda30fcf961f06573336db98cd460d3bf72 (patch)
tree44da78c25e9cf12a3e7b91ca2c9dd7ae386fbcb2
parent6c6ce620e08f8764fd9884094afb274e6e85a47a (diff)
pinctrl: exynos: Consolidate irq_chips of GPIO and WKUP EINTs
Handling of irq_chip operations for GPIO and WKUP external interrupts is mostly the same, with the difference being offset of registers. However currently the driver has all the code duplicated for both EINT types, which is undesirable, because changes in irq_chip operations have to be done to both instances of the same code. This patch fixes this by creating exynos_irq_chip struct that has normal irq_chip struct embedded and contain differences between particular EINT types, which are three register offsets. One instance of code is removed and the new structure is used instead to fetch necessary data instead of samsung_pin_ctrl struct used previously. While at it, the patch removes Exynos-specific fields from aforementioned structure to improve layering of the driver. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat
-rw-r--r--drivers/pinctrl/pinctrl-exynos.c307
-rw-r--r--drivers/pinctrl/pinctrl-samsung.h17
2 files changed, 60 insertions, 264 deletions
diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c
index 9609c23834ce..003bfd874a61 100644
--- a/drivers/pinctrl/pinctrl-exynos.c
+++ b/drivers/pinctrl/pinctrl-exynos.c
@@ -33,6 +33,18 @@
33#include "pinctrl-samsung.h" 33#include "pinctrl-samsung.h"
34#include "pinctrl-exynos.h" 34#include "pinctrl-exynos.h"
35 35
36struct exynos_irq_chip {
37 struct irq_chip chip;
38
39 u32 eint_con;
40 u32 eint_mask;
41 u32 eint_pend;
42};
43
44static inline struct exynos_irq_chip *to_exynos_irq_chip(struct irq_chip *chip)
45{
46 return container_of(chip, struct exynos_irq_chip, chip);
47}
36 48
37static struct samsung_pin_bank_type bank_type_off = { 49static struct samsung_pin_bank_type bank_type_off = {
38 .fld_width = { 4, 1, 2, 2, 2, 2, }, 50 .fld_width = { 4, 1, 2, 2, 2, 2, },
@@ -50,11 +62,13 @@ static const struct of_device_id exynos_wkup_irq_ids[] = {
50 { } 62 { }
51}; 63};
52 64
53static void exynos_gpio_irq_mask(struct irq_data *irqd) 65static void exynos_irq_mask(struct irq_data *irqd)
54{ 66{
67 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
68 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
55 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 69 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
56 struct samsung_pinctrl_drv_data *d = bank->drvdata; 70 struct samsung_pinctrl_drv_data *d = bank->drvdata;
57 unsigned long reg_mask = d->ctrl->geint_mask + bank->eint_offset; 71 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset;
58 unsigned long mask; 72 unsigned long mask;
59 unsigned long flags; 73 unsigned long flags;
60 74
@@ -67,20 +81,24 @@ static void exynos_gpio_irq_mask(struct irq_data *irqd)
67 spin_unlock_irqrestore(&bank->slock, flags); 81 spin_unlock_irqrestore(&bank->slock, flags);
68} 82}
69 83
70static void exynos_gpio_irq_ack(struct irq_data *irqd) 84static void exynos_irq_ack(struct irq_data *irqd)
71{ 85{
86 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
87 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
72 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 88 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
73 struct samsung_pinctrl_drv_data *d = bank->drvdata; 89 struct samsung_pinctrl_drv_data *d = bank->drvdata;
74 unsigned long reg_pend = d->ctrl->geint_pend + bank->eint_offset; 90 unsigned long reg_pend = our_chip->eint_pend + bank->eint_offset;
75 91
76 writel(1 << irqd->hwirq, d->virt_base + reg_pend); 92 writel(1 << irqd->hwirq, d->virt_base + reg_pend);
77} 93}
78 94
79static void exynos_gpio_irq_unmask(struct irq_data *irqd) 95static void exynos_irq_unmask(struct irq_data *irqd)
80{ 96{
97 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
98 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
81 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 99 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
82 struct samsung_pinctrl_drv_data *d = bank->drvdata; 100 struct samsung_pinctrl_drv_data *d = bank->drvdata;
83 unsigned long reg_mask = d->ctrl->geint_mask + bank->eint_offset; 101 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset;
84 unsigned long mask; 102 unsigned long mask;
85 unsigned long flags; 103 unsigned long flags;
86 104
@@ -93,7 +111,7 @@ static void exynos_gpio_irq_unmask(struct irq_data *irqd)
93 * masked. 111 * masked.
94 */ 112 */
95 if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK) 113 if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK)
96 exynos_gpio_irq_ack(irqd); 114 exynos_irq_ack(irqd);
97 115
98 spin_lock_irqsave(&bank->slock, flags); 116 spin_lock_irqsave(&bank->slock, flags);
99 117
@@ -104,16 +122,17 @@ static void exynos_gpio_irq_unmask(struct irq_data *irqd)
104 spin_unlock_irqrestore(&bank->slock, flags); 122 spin_unlock_irqrestore(&bank->slock, flags);
105} 123}
106 124
107static int exynos_gpio_irq_set_type(struct irq_data *irqd, unsigned int type) 125static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type)
108{ 126{
127 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
128 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
109 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 129 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
110 struct samsung_pin_bank_type *bank_type = bank->type; 130 struct samsung_pin_bank_type *bank_type = bank->type;
111 struct samsung_pinctrl_drv_data *d = bank->drvdata; 131 struct samsung_pinctrl_drv_data *d = bank->drvdata;
112 struct samsung_pin_ctrl *ctrl = d->ctrl;
113 unsigned int pin = irqd->hwirq; 132 unsigned int pin = irqd->hwirq;
114 unsigned int shift = EXYNOS_EINT_CON_LEN * pin; 133 unsigned int shift = EXYNOS_EINT_CON_LEN * pin;
115 unsigned int con, trig_type; 134 unsigned int con, trig_type;
116 unsigned long reg_con = ctrl->geint_con + bank->eint_offset; 135 unsigned long reg_con = our_chip->eint_con + bank->eint_offset;
117 unsigned long flags; 136 unsigned long flags;
118 unsigned int mask; 137 unsigned int mask;
119 138
@@ -167,12 +186,17 @@ static int exynos_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
167/* 186/*
168 * irq_chip for gpio interrupts. 187 * irq_chip for gpio interrupts.
169 */ 188 */
170static struct irq_chip exynos_gpio_irq_chip = { 189static struct exynos_irq_chip exynos_gpio_irq_chip = {
171 .name = "exynos_gpio_irq_chip", 190 .chip = {
172 .irq_unmask = exynos_gpio_irq_unmask, 191 .name = "exynos_gpio_irq_chip",
173 .irq_mask = exynos_gpio_irq_mask, 192 .irq_unmask = exynos_irq_unmask,
174 .irq_ack = exynos_gpio_irq_ack, 193 .irq_mask = exynos_irq_mask,
175 .irq_set_type = exynos_gpio_irq_set_type, 194 .irq_ack = exynos_irq_ack,
195 .irq_set_type = exynos_irq_set_type,
196 },
197 .eint_con = EXYNOS_GPIO_ECON_OFFSET,
198 .eint_mask = EXYNOS_GPIO_EMASK_OFFSET,
199 .eint_pend = EXYNOS_GPIO_EPEND_OFFSET,
176}; 200};
177 201
178static int exynos_gpio_irq_map(struct irq_domain *h, unsigned int virq, 202static int exynos_gpio_irq_map(struct irq_domain *h, unsigned int virq,
@@ -181,7 +205,7 @@ static int exynos_gpio_irq_map(struct irq_domain *h, unsigned int virq,
181 struct samsung_pin_bank *b = h->host_data; 205 struct samsung_pin_bank *b = h->host_data;
182 206
183 irq_set_chip_data(virq, b); 207 irq_set_chip_data(virq, b);
184 irq_set_chip_and_handler(virq, &exynos_gpio_irq_chip, 208 irq_set_chip_and_handler(virq, &exynos_gpio_irq_chip.chip,
185 handle_level_irq); 209 handle_level_irq);
186 set_irq_flags(virq, IRQF_VALID); 210 set_irq_flags(virq, IRQF_VALID);
187 return 0; 211 return 0;
@@ -202,7 +226,7 @@ static irqreturn_t exynos_eint_gpio_irq(int irq, void *data)
202 struct samsung_pin_bank *bank = ctrl->pin_banks; 226 struct samsung_pin_bank *bank = ctrl->pin_banks;
203 unsigned int svc, group, pin, virq; 227 unsigned int svc, group, pin, virq;
204 228
205 svc = readl(d->virt_base + ctrl->svc); 229 svc = readl(d->virt_base + EXYNOS_SVC_OFFSET);
206 group = EXYNOS_SVC_GROUP(svc); 230 group = EXYNOS_SVC_GROUP(svc);
207 pin = svc & EXYNOS_SVC_NUM_MASK; 231 pin = svc & EXYNOS_SVC_NUM_MASK;
208 232
@@ -279,119 +303,6 @@ err_domains:
279 return ret; 303 return ret;
280} 304}
281 305
282static void exynos_wkup_irq_mask(struct irq_data *irqd)
283{
284 struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd);
285 struct samsung_pinctrl_drv_data *d = b->drvdata;
286 unsigned long reg_mask = d->ctrl->weint_mask + b->eint_offset;
287 unsigned long mask;
288 unsigned long flags;
289
290 spin_lock_irqsave(&b->slock, flags);
291
292 mask = readl(d->virt_base + reg_mask);
293 mask |= 1 << irqd->hwirq;
294 writel(mask, d->virt_base + reg_mask);
295
296 spin_unlock_irqrestore(&b->slock, flags);
297}
298
299static void exynos_wkup_irq_ack(struct irq_data *irqd)
300{
301 struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd);
302 struct samsung_pinctrl_drv_data *d = b->drvdata;
303 unsigned long pend = d->ctrl->weint_pend + b->eint_offset;
304
305 writel(1 << irqd->hwirq, d->virt_base + pend);
306}
307
308static void exynos_wkup_irq_unmask(struct irq_data *irqd)
309{
310 struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd);
311 struct samsung_pinctrl_drv_data *d = b->drvdata;
312 unsigned long reg_mask = d->ctrl->weint_mask + b->eint_offset;
313 unsigned long mask;
314 unsigned long flags;
315
316 /*
317 * Ack level interrupts right before unmask
318 *
319 * If we don't do this we'll get a double-interrupt. Level triggered
320 * interrupts must not fire an interrupt if the level is not
321 * _currently_ active, even if it was active while the interrupt was
322 * masked.
323 */
324 if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK)
325 exynos_wkup_irq_ack(irqd);
326
327 spin_lock_irqsave(&b->slock, flags);
328
329 mask = readl(d->virt_base + reg_mask);
330 mask &= ~(1 << irqd->hwirq);
331 writel(mask, d->virt_base + reg_mask);
332
333 spin_unlock_irqrestore(&b->slock, flags);
334}
335
336static int exynos_wkup_irq_set_type(struct irq_data *irqd, unsigned int type)
337{
338 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
339 struct samsung_pin_bank_type *bank_type = bank->type;
340 struct samsung_pinctrl_drv_data *d = bank->drvdata;
341 unsigned int pin = irqd->hwirq;
342 unsigned long reg_con = d->ctrl->weint_con + bank->eint_offset;
343 unsigned long shift = EXYNOS_EINT_CON_LEN * pin;
344 unsigned long con, trig_type;
345 unsigned long flags;
346 unsigned int mask;
347
348 switch (type) {
349 case IRQ_TYPE_EDGE_RISING:
350 trig_type = EXYNOS_EINT_EDGE_RISING;
351 break;
352 case IRQ_TYPE_EDGE_FALLING:
353 trig_type = EXYNOS_EINT_EDGE_FALLING;
354 break;
355 case IRQ_TYPE_EDGE_BOTH:
356 trig_type = EXYNOS_EINT_EDGE_BOTH;
357 break;
358 case IRQ_TYPE_LEVEL_HIGH:
359 trig_type = EXYNOS_EINT_LEVEL_HIGH;
360 break;
361 case IRQ_TYPE_LEVEL_LOW:
362 trig_type = EXYNOS_EINT_LEVEL_LOW;
363 break;
364 default:
365 pr_err("unsupported external interrupt type\n");
366 return -EINVAL;
367 }
368
369 if (type & IRQ_TYPE_EDGE_BOTH)
370 __irq_set_handler_locked(irqd->irq, handle_edge_irq);
371 else
372 __irq_set_handler_locked(irqd->irq, handle_level_irq);
373
374 con = readl(d->virt_base + reg_con);
375 con &= ~(EXYNOS_EINT_CON_MASK << shift);
376 con |= trig_type << shift;
377 writel(con, d->virt_base + reg_con);
378
379 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC];
380 shift = pin * bank_type->fld_width[PINCFG_TYPE_FUNC];
381 mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
382
383 spin_lock_irqsave(&bank->slock, flags);
384
385 con = readl(d->virt_base + reg_con);
386 con &= ~(mask << shift);
387 con |= EXYNOS_EINT_FUNC << shift;
388 writel(con, d->virt_base + reg_con);
389
390 spin_unlock_irqrestore(&bank->slock, flags);
391
392 return 0;
393}
394
395static u32 exynos_eint_wake_mask = 0xffffffff; 306static u32 exynos_eint_wake_mask = 0xffffffff;
396 307
397u32 exynos_get_eint_wake_mask(void) 308u32 exynos_get_eint_wake_mask(void)
@@ -417,13 +328,18 @@ static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on)
417/* 328/*
418 * irq_chip for wakeup interrupts 329 * irq_chip for wakeup interrupts
419 */ 330 */
420static struct irq_chip exynos_wkup_irq_chip = { 331static struct exynos_irq_chip exynos_wkup_irq_chip = {
421 .name = "exynos_wkup_irq_chip", 332 .chip = {
422 .irq_unmask = exynos_wkup_irq_unmask, 333 .name = "exynos_wkup_irq_chip",
423 .irq_mask = exynos_wkup_irq_mask, 334 .irq_unmask = exynos_irq_unmask,
424 .irq_ack = exynos_wkup_irq_ack, 335 .irq_mask = exynos_irq_mask,
425 .irq_set_type = exynos_wkup_irq_set_type, 336 .irq_ack = exynos_irq_ack,
426 .irq_set_wake = exynos_wkup_irq_set_wake, 337 .irq_set_type = exynos_irq_set_type,
338 .irq_set_wake = exynos_wkup_irq_set_wake,
339 },
340 .eint_con = EXYNOS_WKUP_ECON_OFFSET,
341 .eint_mask = EXYNOS_WKUP_EMASK_OFFSET,
342 .eint_pend = EXYNOS_WKUP_EPEND_OFFSET,
427}; 343};
428 344
429/* interrupt handler for wakeup interrupts 0..15 */ 345/* interrupt handler for wakeup interrupts 0..15 */
@@ -464,7 +380,6 @@ static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
464 struct irq_chip *chip = irq_get_chip(irq); 380 struct irq_chip *chip = irq_get_chip(irq);
465 struct exynos_muxed_weint_data *eintd = irq_get_handler_data(irq); 381 struct exynos_muxed_weint_data *eintd = irq_get_handler_data(irq);
466 struct samsung_pinctrl_drv_data *d = eintd->banks[0]->drvdata; 382 struct samsung_pinctrl_drv_data *d = eintd->banks[0]->drvdata;
467 struct samsung_pin_ctrl *ctrl = d->ctrl;
468 unsigned long pend; 383 unsigned long pend;
469 unsigned long mask; 384 unsigned long mask;
470 int i; 385 int i;
@@ -473,8 +388,10 @@ static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
473 388
474 for (i = 0; i < eintd->nr_banks; ++i) { 389 for (i = 0; i < eintd->nr_banks; ++i) {
475 struct samsung_pin_bank *b = eintd->banks[i]; 390 struct samsung_pin_bank *b = eintd->banks[i];
476 pend = readl(d->virt_base + ctrl->weint_pend + b->eint_offset); 391 pend = readl(d->virt_base + EXYNOS_WKUP_EPEND_OFFSET
477 mask = readl(d->virt_base + ctrl->weint_mask + b->eint_offset); 392 + b->eint_offset);
393 mask = readl(d->virt_base + EXYNOS_WKUP_EMASK_OFFSET
394 + b->eint_offset);
478 exynos_irq_demux_eint(pend & ~mask, b->irq_domain); 395 exynos_irq_demux_eint(pend & ~mask, b->irq_domain);
479 } 396 }
480 397
@@ -484,7 +401,8 @@ static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
484static int exynos_wkup_irq_map(struct irq_domain *h, unsigned int virq, 401static int exynos_wkup_irq_map(struct irq_domain *h, unsigned int virq,
485 irq_hw_number_t hw) 402 irq_hw_number_t hw)
486{ 403{
487 irq_set_chip_and_handler(virq, &exynos_wkup_irq_chip, handle_level_irq); 404 irq_set_chip_and_handler(virq, &exynos_wkup_irq_chip.chip,
405 handle_level_irq);
488 irq_set_chip_data(virq, h->host_data); 406 irq_set_chip_data(virq, h->host_data);
489 set_irq_flags(virq, IRQF_VALID); 407 set_irq_flags(virq, IRQF_VALID);
490 return 0; 408 return 0;
@@ -703,13 +621,6 @@ struct samsung_pin_ctrl s5pv210_pin_ctrl[] = {
703 /* pin-controller instance 0 data */ 621 /* pin-controller instance 0 data */
704 .pin_banks = s5pv210_pin_bank, 622 .pin_banks = s5pv210_pin_bank,
705 .nr_banks = ARRAY_SIZE(s5pv210_pin_bank), 623 .nr_banks = ARRAY_SIZE(s5pv210_pin_bank),
706 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
707 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
708 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
709 .weint_con = EXYNOS_WKUP_ECON_OFFSET,
710 .weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
711 .weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
712 .svc = EXYNOS_SVC_OFFSET,
713 .eint_gpio_init = exynos_eint_gpio_init, 624 .eint_gpio_init = exynos_eint_gpio_init,
714 .eint_wkup_init = exynos_eint_wkup_init, 625 .eint_wkup_init = exynos_eint_wkup_init,
715 .suspend = exynos_pinctrl_suspend, 626 .suspend = exynos_pinctrl_suspend,
@@ -758,10 +669,6 @@ struct samsung_pin_ctrl exynos3250_pin_ctrl[] = {
758 /* pin-controller instance 0 data */ 669 /* pin-controller instance 0 data */
759 .pin_banks = exynos3250_pin_banks0, 670 .pin_banks = exynos3250_pin_banks0,
760 .nr_banks = ARRAY_SIZE(exynos3250_pin_banks0), 671 .nr_banks = ARRAY_SIZE(exynos3250_pin_banks0),
761 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
762 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
763 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
764 .svc = EXYNOS_SVC_OFFSET,
765 .eint_gpio_init = exynos_eint_gpio_init, 672 .eint_gpio_init = exynos_eint_gpio_init,
766 .suspend = exynos_pinctrl_suspend, 673 .suspend = exynos_pinctrl_suspend,
767 .resume = exynos_pinctrl_resume, 674 .resume = exynos_pinctrl_resume,
@@ -770,13 +677,6 @@ struct samsung_pin_ctrl exynos3250_pin_ctrl[] = {
770 /* pin-controller instance 1 data */ 677 /* pin-controller instance 1 data */
771 .pin_banks = exynos3250_pin_banks1, 678 .pin_banks = exynos3250_pin_banks1,
772 .nr_banks = ARRAY_SIZE(exynos3250_pin_banks1), 679 .nr_banks = ARRAY_SIZE(exynos3250_pin_banks1),
773 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
774 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
775 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
776 .weint_con = EXYNOS_WKUP_ECON_OFFSET,
777 .weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
778 .weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
779 .svc = EXYNOS_SVC_OFFSET,
780 .eint_gpio_init = exynos_eint_gpio_init, 680 .eint_gpio_init = exynos_eint_gpio_init,
781 .eint_wkup_init = exynos_eint_wkup_init, 681 .eint_wkup_init = exynos_eint_wkup_init,
782 .suspend = exynos_pinctrl_suspend, 682 .suspend = exynos_pinctrl_suspend,
@@ -843,10 +743,6 @@ struct samsung_pin_ctrl exynos4210_pin_ctrl[] = {
843 /* pin-controller instance 0 data */ 743 /* pin-controller instance 0 data */
844 .pin_banks = exynos4210_pin_banks0, 744 .pin_banks = exynos4210_pin_banks0,
845 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks0), 745 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks0),
846 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
847 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
848 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
849 .svc = EXYNOS_SVC_OFFSET,
850 .eint_gpio_init = exynos_eint_gpio_init, 746 .eint_gpio_init = exynos_eint_gpio_init,
851 .suspend = exynos_pinctrl_suspend, 747 .suspend = exynos_pinctrl_suspend,
852 .resume = exynos_pinctrl_resume, 748 .resume = exynos_pinctrl_resume,
@@ -855,13 +751,6 @@ struct samsung_pin_ctrl exynos4210_pin_ctrl[] = {
855 /* pin-controller instance 1 data */ 751 /* pin-controller instance 1 data */
856 .pin_banks = exynos4210_pin_banks1, 752 .pin_banks = exynos4210_pin_banks1,
857 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks1), 753 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks1),
858 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
859 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
860 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
861 .weint_con = EXYNOS_WKUP_ECON_OFFSET,
862 .weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
863 .weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
864 .svc = EXYNOS_SVC_OFFSET,
865 .eint_gpio_init = exynos_eint_gpio_init, 754 .eint_gpio_init = exynos_eint_gpio_init,
866 .eint_wkup_init = exynos_eint_wkup_init, 755 .eint_wkup_init = exynos_eint_wkup_init,
867 .suspend = exynos_pinctrl_suspend, 756 .suspend = exynos_pinctrl_suspend,
@@ -942,10 +831,6 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
942 /* pin-controller instance 0 data */ 831 /* pin-controller instance 0 data */
943 .pin_banks = exynos4x12_pin_banks0, 832 .pin_banks = exynos4x12_pin_banks0,
944 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks0), 833 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks0),
945 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
946 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
947 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
948 .svc = EXYNOS_SVC_OFFSET,
949 .eint_gpio_init = exynos_eint_gpio_init, 834 .eint_gpio_init = exynos_eint_gpio_init,
950 .suspend = exynos_pinctrl_suspend, 835 .suspend = exynos_pinctrl_suspend,
951 .resume = exynos_pinctrl_resume, 836 .resume = exynos_pinctrl_resume,
@@ -954,13 +839,6 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
954 /* pin-controller instance 1 data */ 839 /* pin-controller instance 1 data */
955 .pin_banks = exynos4x12_pin_banks1, 840 .pin_banks = exynos4x12_pin_banks1,
956 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks1), 841 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks1),
957 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
958 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
959 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
960 .weint_con = EXYNOS_WKUP_ECON_OFFSET,
961 .weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
962 .weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
963 .svc = EXYNOS_SVC_OFFSET,
964 .eint_gpio_init = exynos_eint_gpio_init, 842 .eint_gpio_init = exynos_eint_gpio_init,
965 .eint_wkup_init = exynos_eint_wkup_init, 843 .eint_wkup_init = exynos_eint_wkup_init,
966 .suspend = exynos_pinctrl_suspend, 844 .suspend = exynos_pinctrl_suspend,
@@ -970,10 +848,6 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
970 /* pin-controller instance 2 data */ 848 /* pin-controller instance 2 data */
971 .pin_banks = exynos4x12_pin_banks2, 849 .pin_banks = exynos4x12_pin_banks2,
972 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks2), 850 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks2),
973 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
974 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
975 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
976 .svc = EXYNOS_SVC_OFFSET,
977 .eint_gpio_init = exynos_eint_gpio_init, 851 .eint_gpio_init = exynos_eint_gpio_init,
978 .suspend = exynos_pinctrl_suspend, 852 .suspend = exynos_pinctrl_suspend,
979 .resume = exynos_pinctrl_resume, 853 .resume = exynos_pinctrl_resume,
@@ -982,10 +856,6 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
982 /* pin-controller instance 3 data */ 856 /* pin-controller instance 3 data */
983 .pin_banks = exynos4x12_pin_banks3, 857 .pin_banks = exynos4x12_pin_banks3,
984 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks3), 858 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks3),
985 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
986 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
987 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
988 .svc = EXYNOS_SVC_OFFSET,
989 .eint_gpio_init = exynos_eint_gpio_init, 859 .eint_gpio_init = exynos_eint_gpio_init,
990 .suspend = exynos_pinctrl_suspend, 860 .suspend = exynos_pinctrl_suspend,
991 .resume = exynos_pinctrl_resume, 861 .resume = exynos_pinctrl_resume,
@@ -1058,13 +928,6 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
1058 /* pin-controller instance 0 data */ 928 /* pin-controller instance 0 data */
1059 .pin_banks = exynos5250_pin_banks0, 929 .pin_banks = exynos5250_pin_banks0,
1060 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks0), 930 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks0),
1061 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
1062 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
1063 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
1064 .weint_con = EXYNOS_WKUP_ECON_OFFSET,
1065 .weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
1066 .weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
1067 .svc = EXYNOS_SVC_OFFSET,
1068 .eint_gpio_init = exynos_eint_gpio_init, 931 .eint_gpio_init = exynos_eint_gpio_init,
1069 .eint_wkup_init = exynos_eint_wkup_init, 932 .eint_wkup_init = exynos_eint_wkup_init,
1070 .suspend = exynos_pinctrl_suspend, 933 .suspend = exynos_pinctrl_suspend,
@@ -1074,10 +937,6 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
1074 /* pin-controller instance 1 data */ 937 /* pin-controller instance 1 data */
1075 .pin_banks = exynos5250_pin_banks1, 938 .pin_banks = exynos5250_pin_banks1,
1076 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks1), 939 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks1),
1077 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
1078 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
1079 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
1080 .svc = EXYNOS_SVC_OFFSET,
1081 .eint_gpio_init = exynos_eint_gpio_init, 940 .eint_gpio_init = exynos_eint_gpio_init,
1082 .suspend = exynos_pinctrl_suspend, 941 .suspend = exynos_pinctrl_suspend,
1083 .resume = exynos_pinctrl_resume, 942 .resume = exynos_pinctrl_resume,
@@ -1086,10 +945,6 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
1086 /* pin-controller instance 2 data */ 945 /* pin-controller instance 2 data */
1087 .pin_banks = exynos5250_pin_banks2, 946 .pin_banks = exynos5250_pin_banks2,
1088 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks2), 947 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks2),
1089 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
1090 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
1091 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
1092 .svc = EXYNOS_SVC_OFFSET,
1093 .eint_gpio_init = exynos_eint_gpio_init, 948 .eint_gpio_init = exynos_eint_gpio_init,
1094 .suspend = exynos_pinctrl_suspend, 949 .suspend = exynos_pinctrl_suspend,
1095 .resume = exynos_pinctrl_resume, 950 .resume = exynos_pinctrl_resume,
@@ -1098,10 +953,6 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
1098 /* pin-controller instance 3 data */ 953 /* pin-controller instance 3 data */
1099 .pin_banks = exynos5250_pin_banks3, 954 .pin_banks = exynos5250_pin_banks3,
1100 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks3), 955 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks3),
1101 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
1102 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
1103 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
1104 .svc = EXYNOS_SVC_OFFSET,
1105 .eint_gpio_init = exynos_eint_gpio_init, 956 .eint_gpio_init = exynos_eint_gpio_init,
1106 .suspend = exynos_pinctrl_suspend, 957 .suspend = exynos_pinctrl_suspend,
1107 .resume = exynos_pinctrl_resume, 958 .resume = exynos_pinctrl_resume,
@@ -1158,13 +1009,6 @@ struct samsung_pin_ctrl exynos5260_pin_ctrl[] = {
1158 /* pin-controller instance 0 data */ 1009 /* pin-controller instance 0 data */
1159 .pin_banks = exynos5260_pin_banks0, 1010 .pin_banks = exynos5260_pin_banks0,
1160 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks0), 1011 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks0),
1161 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
1162 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
1163 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
1164 .weint_con = EXYNOS_WKUP_ECON_OFFSET,
1165 .weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
1166 .weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
1167 .svc = EXYNOS_SVC_OFFSET,
1168 .eint_gpio_init = exynos_eint_gpio_init, 1012 .eint_gpio_init = exynos_eint_gpio_init,
1169 .eint_wkup_init = exynos_eint_wkup_init, 1013 .eint_wkup_init = exynos_eint_wkup_init,
1170 .label = "exynos5260-gpio-ctrl0", 1014 .label = "exynos5260-gpio-ctrl0",
@@ -1172,20 +1016,12 @@ struct samsung_pin_ctrl exynos5260_pin_ctrl[] = {
1172 /* pin-controller instance 1 data */ 1016 /* pin-controller instance 1 data */
1173 .pin_banks = exynos5260_pin_banks1, 1017 .pin_banks = exynos5260_pin_banks1,
1174 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks1), 1018 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks1),
1175 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
1176 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
1177 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
1178 .svc = EXYNOS_SVC_OFFSET,
1179 .eint_gpio_init = exynos_eint_gpio_init, 1019 .eint_gpio_init = exynos_eint_gpio_init,
1180 .label = "exynos5260-gpio-ctrl1", 1020 .label = "exynos5260-gpio-ctrl1",
1181 }, { 1021 }, {
1182 /* pin-controller instance 2 data */ 1022 /* pin-controller instance 2 data */
1183 .pin_banks = exynos5260_pin_banks2, 1023 .pin_banks = exynos5260_pin_banks2,
1184 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks2), 1024 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks2),
1185 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
1186 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
1187 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
1188 .svc = EXYNOS_SVC_OFFSET,
1189 .eint_gpio_init = exynos_eint_gpio_init, 1025 .eint_gpio_init = exynos_eint_gpio_init,
1190 .label = "exynos5260-gpio-ctrl2", 1026 .label = "exynos5260-gpio-ctrl2",
1191 }, 1027 },
@@ -1256,13 +1092,6 @@ struct samsung_pin_ctrl exynos5420_pin_ctrl[] = {
1256 /* pin-controller instance 0 data */ 1092 /* pin-controller instance 0 data */
1257 .pin_banks = exynos5420_pin_banks0, 1093 .pin_banks = exynos5420_pin_banks0,
1258 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks0), 1094 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks0),
1259 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
1260 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
1261 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
1262 .weint_con = EXYNOS_WKUP_ECON_OFFSET,
1263 .weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
1264 .weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
1265 .svc = EXYNOS_SVC_OFFSET,
1266 .eint_gpio_init = exynos_eint_gpio_init, 1095 .eint_gpio_init = exynos_eint_gpio_init,
1267 .eint_wkup_init = exynos_eint_wkup_init, 1096 .eint_wkup_init = exynos_eint_wkup_init,
1268 .label = "exynos5420-gpio-ctrl0", 1097 .label = "exynos5420-gpio-ctrl0",
@@ -1270,40 +1099,24 @@ struct samsung_pin_ctrl exynos5420_pin_ctrl[] = {
1270 /* pin-controller instance 1 data */ 1099 /* pin-controller instance 1 data */
1271 .pin_banks = exynos5420_pin_banks1, 1100 .pin_banks = exynos5420_pin_banks1,
1272 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks1), 1101 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks1),
1273 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
1274 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
1275 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
1276 .svc = EXYNOS_SVC_OFFSET,
1277 .eint_gpio_init = exynos_eint_gpio_init, 1102 .eint_gpio_init = exynos_eint_gpio_init,
1278 .label = "exynos5420-gpio-ctrl1", 1103 .label = "exynos5420-gpio-ctrl1",
1279 }, { 1104 }, {
1280 /* pin-controller instance 2 data */ 1105 /* pin-controller instance 2 data */
1281 .pin_banks = exynos5420_pin_banks2, 1106 .pin_banks = exynos5420_pin_banks2,
1282 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks2), 1107 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks2),
1283 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
1284 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
1285 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
1286 .svc = EXYNOS_SVC_OFFSET,
1287 .eint_gpio_init = exynos_eint_gpio_init, 1108 .eint_gpio_init = exynos_eint_gpio_init,
1288 .label = "exynos5420-gpio-ctrl2", 1109 .label = "exynos5420-gpio-ctrl2",
1289 }, { 1110 }, {
1290 /* pin-controller instance 3 data */ 1111 /* pin-controller instance 3 data */
1291 .pin_banks = exynos5420_pin_banks3, 1112 .pin_banks = exynos5420_pin_banks3,
1292 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks3), 1113 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks3),
1293 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
1294 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
1295 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
1296 .svc = EXYNOS_SVC_OFFSET,
1297 .eint_gpio_init = exynos_eint_gpio_init, 1114 .eint_gpio_init = exynos_eint_gpio_init,
1298 .label = "exynos5420-gpio-ctrl3", 1115 .label = "exynos5420-gpio-ctrl3",
1299 }, { 1116 }, {
1300 /* pin-controller instance 4 data */ 1117 /* pin-controller instance 4 data */
1301 .pin_banks = exynos5420_pin_banks4, 1118 .pin_banks = exynos5420_pin_banks4,
1302 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks4), 1119 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks4),
1303 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
1304 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
1305 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
1306 .svc = EXYNOS_SVC_OFFSET,
1307 .eint_gpio_init = exynos_eint_gpio_init, 1120 .eint_gpio_init = exynos_eint_gpio_init,
1308 .label = "exynos5420-gpio-ctrl4", 1121 .label = "exynos5420-gpio-ctrl4",
1309 }, 1122 },
diff --git a/drivers/pinctrl/pinctrl-samsung.h b/drivers/pinctrl/pinctrl-samsung.h
index b3e41fa5798b..e2dce4731a01 100644
--- a/drivers/pinctrl/pinctrl-samsung.h
+++ b/drivers/pinctrl/pinctrl-samsung.h
@@ -156,13 +156,6 @@ struct samsung_pin_bank {
156 * @nr_banks: number of pin banks. 156 * @nr_banks: number of pin banks.
157 * @base: starting system wide pin number. 157 * @base: starting system wide pin number.
158 * @nr_pins: number of pins supported by the controller. 158 * @nr_pins: number of pins supported by the controller.
159 * @geint_con: offset of the ext-gpio controller registers.
160 * @geint_mask: offset of the ext-gpio interrupt mask registers.
161 * @geint_pend: offset of the ext-gpio interrupt pending registers.
162 * @weint_con: offset of the ext-wakeup controller registers.
163 * @weint_mask: offset of the ext-wakeup interrupt mask registers.
164 * @weint_pend: offset of the ext-wakeup interrupt pending registers.
165 * @svc: offset of the interrupt service register.
166 * @eint_gpio_init: platform specific callback to setup the external gpio 159 * @eint_gpio_init: platform specific callback to setup the external gpio
167 * interrupts for the controller. 160 * interrupts for the controller.
168 * @eint_wkup_init: platform specific callback to setup the external wakeup 161 * @eint_wkup_init: platform specific callback to setup the external wakeup
@@ -176,16 +169,6 @@ struct samsung_pin_ctrl {
176 u32 base; 169 u32 base;
177 u32 nr_pins; 170 u32 nr_pins;
178 171
179 u32 geint_con;
180 u32 geint_mask;
181 u32 geint_pend;
182
183 u32 weint_con;
184 u32 weint_mask;
185 u32 weint_pend;
186
187 u32 svc;
188
189 int (*eint_gpio_init)(struct samsung_pinctrl_drv_data *); 172 int (*eint_gpio_init)(struct samsung_pinctrl_drv_data *);
190 int (*eint_wkup_init)(struct samsung_pinctrl_drv_data *); 173 int (*eint_wkup_init)(struct samsung_pinctrl_drv_data *);
191 void (*suspend)(struct samsung_pinctrl_drv_data *); 174 void (*suspend)(struct samsung_pinctrl_drv_data *);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-30 11:15:27 -0500