aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@linux-foundation.org>2014-01-25 16:20:36 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2014-01-25 16:20:36 -0500
commit2d2e7d195b902c419bc0b69ced026aca444d69a8 (patch)
treea4caa21b9db159873897d64b553042a1ae920ab5
parent15333539a9b3022656f815f643a77f6b054b335f (diff)
parent8b8b773e6b611e6629ac01f85d401c949d153546 (diff)
Merge tag 'spi-v3.14-2' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Pull spi updates from Mark Brown: "A respun version of the merges for the pull request previously sent with a few additional fixes. The last two merges were fixed up by hand since the branches have moved on and currently have the prior merge in them. Quite a busy release for the SPI subsystem, mostly in cleanups big and small scattered through the stack rather than anything else: - New driver for the Broadcom BC63xx HSSPI controller - Fix duplicate device registration for ACPI - Conversion of s3c64xx to DMAEngine (this pulls in platform and DMA changes upon which the transiton depends) - Some small optimisations to reduce the amount of time we hold locks in the datapath, eliminate some redundant checks and the size of a spi_transfer - Lots of fixes, cleanups and general enhancements to drivers, especially the rspi and Atmel drivers" * tag 'spi-v3.14-2' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (112 commits) spi: core: Fix transfer failure when master->transfer_one returns positive value spi: Correct set_cs() documentation spi: Clarify transfer_one() w.r.t. spi_finalize_current_transfer() spi: Spelling s/finised/finished/ spi: sc18is602: Convert to use bits_per_word_mask spi: Remove duplicate code to set default bits_per_word setting spi/pxa2xx: fix compilation warning when !CONFIG_PM_SLEEP spi: clps711x: Add MODULE_ALIAS to support module auto-loading spi: rspi: Add missing clk_disable() calls in error and cleanup paths spi: rspi: Spelling s/transmition/transmission/ spi: rspi: Add support for specifying CPHA/CPOL spi/pxa2xx: initialize DMA channels to -1 to prevent inadvertent match spi: rspi: Add more QSPI register documentation spi: rspi: Add more RSPI register documentation spi: rspi: Remove dependency on DMAE for SHMOBILE spi/s3c64xx: Correct indentation spi: sh: Use spi_sh_clear_bit() instead of open-coded spi: bitbang: Grammar s/make to make/to make/ spi: sh-hspi: Spelling s/recive/receive/ spi: core: Improve tx/rx_nbits check comments ...
Diffstat
-rw-r--r--Documentation/devicetree/bindings/spi/spi-bus.txt2
-rw-r--r--Documentation/devicetree/bindings/spi/ti_qspi.txt8
-rw-r--r--Documentation/spi/spi-summary8
-rw-r--r--arch/arm/plat-samsung/include/plat/fiq.h13
-rw-r--r--drivers/spi/Kconfig14
-rw-r--r--drivers/spi/Makefile1
-rw-r--r--drivers/spi/spi-altera.c2
-rw-r--r--drivers/spi/spi-ath79.c14
-rw-r--r--drivers/spi/spi-atmel.c778
-rw-r--r--drivers/spi/spi-bcm2835.c10
-rw-r--r--drivers/spi/spi-bcm63xx-hsspi.c475
-rw-r--r--drivers/spi/spi-bcm63xx.c48
-rw-r--r--drivers/spi/spi-bitbang-txrx.h2
-rw-r--r--drivers/spi/spi-clps711x.c23
-rw-r--r--drivers/spi/spi-coldfire-qspi.c53
-rw-r--r--drivers/spi/spi-davinci.c49
-rw-r--r--drivers/spi/spi-dw-mmio.c74
-rw-r--r--drivers/spi/spi-dw-pci.c47
-rw-r--r--drivers/spi/spi-dw.c26
-rw-r--r--drivers/spi/spi-dw.h5
-rw-r--r--drivers/spi/spi-falcon.c12
-rw-r--r--drivers/spi/spi-fsl-dspi.c5
-rw-r--r--drivers/spi/spi-fsl-espi.c63
-rw-r--r--drivers/spi/spi-gpio.c8
-rw-r--r--drivers/spi/spi-imx.c27
-rw-r--r--drivers/spi/spi-mpc512x-psc.c18
-rw-r--r--drivers/spi/spi-mxs.c9
-rw-r--r--drivers/spi/spi-nuc900.c56
-rw-r--r--drivers/spi/spi-oc-tiny.c62
-rw-r--r--drivers/spi/spi-omap-100k.c20
-rw-r--r--drivers/spi/spi-omap2-mcspi.c38
-rw-r--r--drivers/spi/spi-orion.c4
-rw-r--r--drivers/spi/spi-pxa2xx-pci.c2
-rw-r--r--drivers/spi/spi-pxa2xx.c4
-rw-r--r--drivers/spi/spi-rspi.c363
-rw-r--r--drivers/spi/spi-s3c24xx.c74
-rw-r--r--drivers/spi/spi-s3c64xx.c5
-rw-r--r--drivers/spi/spi-sc18is602.c24
-rw-r--r--drivers/spi/spi-sh-hspi.c4
-rw-r--r--drivers/spi/spi-sh-msiof.c62
-rw-r--r--drivers/spi/spi-sh.c13
-rw-r--r--drivers/spi/spi-sirf.c7
-rw-r--r--drivers/spi/spi-tegra114.c98
-rw-r--r--drivers/spi/spi-tegra20-sflash.c22
-rw-r--r--drivers/spi/spi-tegra20-slink.c97
-rw-r--r--drivers/spi/spi-ti-qspi.c129
-rw-r--r--drivers/spi/spi-topcliff-pch.c8
-rw-r--r--drivers/spi/spi-txx9.c8
-rw-r--r--drivers/spi/spi-xcomm.c12
-rw-r--r--drivers/spi/spi.c74
-rw-r--r--include/linux/platform_data/spi-nuc900.h8
-rw-r--r--include/linux/spi/s3c24xx.h2
-rw-r--r--include/linux/spi/spi.h20
53 files changed, 1491 insertions, 1519 deletions
diff --git a/Documentation/devicetree/bindings/spi/spi-bus.txt b/Documentation/devicetree/bindings/spi/spi-bus.txt
index 800dafe5b01b..e5a4d1b4acfe 100644
--- a/Documentation/devicetree/bindings/spi/spi-bus.txt
+++ b/Documentation/devicetree/bindings/spi/spi-bus.txt
@@ -67,7 +67,7 @@ only 1(SINGLE), 2(DUAL) and 4(QUAD).
67Dual/Quad mode is not allowed when 3-wire mode is used. 67Dual/Quad mode is not allowed when 3-wire mode is used.
68 68
69If a gpio chipselect is used for the SPI slave the gpio number will be passed 69If a gpio chipselect is used for the SPI slave the gpio number will be passed
70via the cs_gpio 70via the SPI master node cs-gpios property.
71 71
72SPI example for an MPC5200 SPI bus: 72SPI example for an MPC5200 SPI bus:
73 spi@f00 { 73 spi@f00 {
diff --git a/Documentation/devicetree/bindings/spi/ti_qspi.txt b/Documentation/devicetree/bindings/spi/ti_qspi.txt
index 1f9641ade0b5..601a360531a5 100644
--- a/Documentation/devicetree/bindings/spi/ti_qspi.txt
+++ b/Documentation/devicetree/bindings/spi/ti_qspi.txt
@@ -3,6 +3,11 @@ TI QSPI controller.
3Required properties: 3Required properties:
4- compatible : should be "ti,dra7xxx-qspi" or "ti,am4372-qspi". 4- compatible : should be "ti,dra7xxx-qspi" or "ti,am4372-qspi".
5- reg: Should contain QSPI registers location and length. 5- reg: Should contain QSPI registers location and length.
6- reg-names: Should contain the resource reg names.
7 - qspi_base: Qspi configuration register Address space
8 - qspi_mmap: Memory mapped Address space
9 - (optional) qspi_ctrlmod: Control module Address space
10- interrupts: should contain the qspi interrupt number.
6- #address-cells, #size-cells : Must be present if the device has sub-nodes 11- #address-cells, #size-cells : Must be present if the device has sub-nodes
7- ti,hwmods: Name of the hwmod associated to the QSPI 12- ti,hwmods: Name of the hwmod associated to the QSPI
8 13
@@ -14,7 +19,8 @@ Example:
14 19
15qspi: qspi@4b300000 { 20qspi: qspi@4b300000 {
16 compatible = "ti,dra7xxx-qspi"; 21 compatible = "ti,dra7xxx-qspi";
17 reg = <0x4b300000 0x100>; 22 reg = <0x47900000 0x100>, <0x30000000 0x3ffffff>;
23 reg-names = "qspi_base", "qspi_mmap";
18 #address-cells = <1>; 24 #address-cells = <1>;
19 #size-cells = <0>; 25 #size-cells = <0>;
20 spi-max-frequency = <25000000>; 26 spi-max-frequency = <25000000>;
diff --git a/Documentation/spi/spi-summary b/Documentation/spi/spi-summary
index f21edb983413..f72e0d1e0da8 100644
--- a/Documentation/spi/spi-summary
+++ b/Documentation/spi/spi-summary
@@ -34,7 +34,7 @@ SPI slave functions are usually not interoperable between vendors
34 - It may also be used to stream data in either direction (half duplex), 34 - It may also be used to stream data in either direction (half duplex),
35 or both of them at the same time (full duplex). 35 or both of them at the same time (full duplex).
36 36
37 - Some devices may use eight bit words. Others may different word 37 - Some devices may use eight bit words. Others may use different word
38 lengths, such as streams of 12-bit or 20-bit digital samples. 38 lengths, such as streams of 12-bit or 20-bit digital samples.
39 39
40 - Words are usually sent with their most significant bit (MSB) first, 40 - Words are usually sent with their most significant bit (MSB) first,
@@ -121,7 +121,7 @@ active. So the master must set the clock to inactive before selecting
121a slave, and the slave can tell the chosen polarity by sampling the 121a slave, and the slave can tell the chosen polarity by sampling the
122clock level when its select line goes active. That's why many devices 122clock level when its select line goes active. That's why many devices
123support for example both modes 0 and 3: they don't care about polarity, 123support for example both modes 0 and 3: they don't care about polarity,
124and alway clock data in/out on rising clock edges. 124and always clock data in/out on rising clock edges.
125 125
126 126
127How do these driver programming interfaces work? 127How do these driver programming interfaces work?
@@ -139,7 +139,7 @@ a command and then reading its response.
139 139
140There are two types of SPI driver, here called: 140There are two types of SPI driver, here called:
141 141
142 Controller drivers ... controllers may be built in to System-On-Chip 142 Controller drivers ... controllers may be built into System-On-Chip
143 processors, and often support both Master and Slave roles. 143 processors, and often support both Master and Slave roles.
144 These drivers touch hardware registers and may use DMA. 144 These drivers touch hardware registers and may use DMA.
145 Or they can be PIO bitbangers, needing just GPIO pins. 145 Or they can be PIO bitbangers, needing just GPIO pins.
@@ -548,7 +548,7 @@ SPI MASTER METHODS
548 DEPRECATED METHODS 548 DEPRECATED METHODS
549 549
550 master->transfer(struct spi_device *spi, struct spi_message *message) 550 master->transfer(struct spi_device *spi, struct spi_message *message)
551 This must not sleep. Its responsibility is arrange that the 551 This must not sleep. Its responsibility is to arrange that the
552 transfer happens and its complete() callback is issued. The two 552 transfer happens and its complete() callback is issued. The two
553 will normally happen later, after other transfers complete, and 553 will normally happen later, after other transfers complete, and
554 if the controller is idle it will need to be kickstarted. This 554 if the controller is idle it will need to be kickstarted. This
diff --git a/arch/arm/plat-samsung/include/plat/fiq.h b/arch/arm/plat-samsung/include/plat/fiq.h
deleted file mode 100644
index 535d06a35628..000000000000
--- a/arch/arm/plat-samsung/include/plat/fiq.h
+++ /dev/null
@@ -1,13 +0,0 @@
1/* linux/arch/arm/plat-samsung/include/plat/fiq.h
2 *
3 * Copyright (c) 2009 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for S3C24XX CPU FIQ support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13extern int s3c24xx_set_fiq(unsigned int irq, bool on);
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 385602f77cad..ba9310bc9acb 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -118,6 +118,13 @@ config SPI_BCM63XX
118 help 118 help
119 Enable support for the SPI controller on the Broadcom BCM63xx SoCs. 119 Enable support for the SPI controller on the Broadcom BCM63xx SoCs.
120 120
121config SPI_BCM63XX_HSSPI
122 tristate "Broadcom BCM63XX HS SPI controller driver"
123 depends on BCM63XX || COMPILE_TEST
124 help
125 This enables support for the High Speed SPI controller present on
126 newer Broadcom BCM63XX SoCs.
127
121config SPI_BITBANG 128config SPI_BITBANG
122 tristate "Utilities for Bitbanging SPI masters" 129 tristate "Utilities for Bitbanging SPI masters"
123 help 130 help
@@ -159,7 +166,6 @@ config SPI_DAVINCI
159 tristate "Texas Instruments DaVinci/DA8x/OMAP-L/AM1x SoC SPI controller" 166 tristate "Texas Instruments DaVinci/DA8x/OMAP-L/AM1x SoC SPI controller"
160 depends on ARCH_DAVINCI || ARCH_KEYSTONE 167 depends on ARCH_DAVINCI || ARCH_KEYSTONE
161 select SPI_BITBANG 168 select SPI_BITBANG
162 select TI_EDMA
163 help 169 help
164 SPI master controller for DaVinci/DA8x/OMAP-L/AM1x SPI modules. 170 SPI master controller for DaVinci/DA8x/OMAP-L/AM1x SPI modules.
165 171
@@ -301,6 +307,7 @@ config SPI_OMAP_UWIRE
301 307
302config SPI_OMAP24XX 308config SPI_OMAP24XX
303 tristate "McSPI driver for OMAP" 309 tristate "McSPI driver for OMAP"
310 depends on ARM || ARM64 || AVR32 || HEXAGON || MIPS || SH
304 depends on ARCH_OMAP2PLUS || COMPILE_TEST 311 depends on ARCH_OMAP2PLUS || COMPILE_TEST
305 help 312 help
306 SPI master controller for OMAP24XX and later Multichannel SPI 313 SPI master controller for OMAP24XX and later Multichannel SPI
@@ -370,7 +377,7 @@ config SPI_PXA2XX_PCI
370 377
371config SPI_RSPI 378config SPI_RSPI
372 tristate "Renesas RSPI controller" 379 tristate "Renesas RSPI controller"
373 depends on (SUPERH || ARCH_SHMOBILE) && SH_DMAE_BASE 380 depends on (SUPERH && SH_DMAE_BASE) || ARCH_SHMOBILE
374 help 381 help
375 SPI driver for Renesas RSPI blocks. 382 SPI driver for Renesas RSPI blocks.
376 383
@@ -407,7 +414,8 @@ config SPI_SC18IS602
407 414
408config SPI_SH_MSIOF 415config SPI_SH_MSIOF
409 tristate "SuperH MSIOF SPI controller" 416 tristate "SuperH MSIOF SPI controller"
410 depends on (SUPERH || ARCH_SHMOBILE) && HAVE_CLK 417 depends on HAVE_CLK
418 depends on SUPERH || ARCH_SHMOBILE || COMPILE_TEST
411 select SPI_BITBANG 419 select SPI_BITBANG
412 help 420 help
413 SPI driver for SuperH and SH Mobile MSIOF blocks. 421 SPI driver for SuperH and SH Mobile MSIOF blocks.
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index ab8d8644af0e..95af48d2d360 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_SPI_ATH79) += spi-ath79.o
16obj-$(CONFIG_SPI_AU1550) += spi-au1550.o 16obj-$(CONFIG_SPI_AU1550) += spi-au1550.o
17obj-$(CONFIG_SPI_BCM2835) += spi-bcm2835.o 17obj-$(CONFIG_SPI_BCM2835) += spi-bcm2835.o
18obj-$(CONFIG_SPI_BCM63XX) += spi-bcm63xx.o 18obj-$(CONFIG_SPI_BCM63XX) += spi-bcm63xx.o
19obj-$(CONFIG_SPI_BCM63XX_HSSPI) += spi-bcm63xx-hsspi.o
19obj-$(CONFIG_SPI_BFIN5XX) += spi-bfin5xx.o 20obj-$(CONFIG_SPI_BFIN5XX) += spi-bfin5xx.o
20obj-$(CONFIG_SPI_BFIN_V3) += spi-bfin-v3.o 21obj-$(CONFIG_SPI_BFIN_V3) += spi-bfin-v3.o
21obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o 22obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o
diff --git a/drivers/spi/spi-altera.c b/drivers/spi/spi-altera.c
index 595b62cb545d..5d7deaf62867 100644
--- a/drivers/spi/spi-altera.c
+++ b/drivers/spi/spi-altera.c
@@ -220,8 +220,6 @@ static int altera_spi_probe(struct platform_device *pdev)
220 220
221 /* setup the state for the bitbang driver */ 221 /* setup the state for the bitbang driver */
222 hw->bitbang.master = master; 222 hw->bitbang.master = master;
223 if (!hw->bitbang.master)
224 return err;
225 hw->bitbang.chipselect = altera_spi_chipsel; 223 hw->bitbang.chipselect = altera_spi_chipsel;
226 hw->bitbang.txrx_bufs = altera_spi_txrx; 224 hw->bitbang.txrx_bufs = altera_spi_txrx;
227 225
diff --git a/drivers/spi/spi-ath79.c b/drivers/spi/spi-ath79.c
index 821bf7ac218d..31534b51715a 100644
--- a/drivers/spi/spi-ath79.c
+++ b/drivers/spi/spi-ath79.c
@@ -243,21 +243,21 @@ static int ath79_spi_probe(struct platform_device *pdev)
243 goto err_put_master; 243 goto err_put_master;
244 } 244 }
245 245
246 sp->base = ioremap(r->start, resource_size(r)); 246 sp->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
247 if (!sp->base) { 247 if (!sp->base) {
248 ret = -ENXIO; 248 ret = -ENXIO;
249 goto err_put_master; 249 goto err_put_master;
250 } 250 }
251 251
252 sp->clk = clk_get(&pdev->dev, "ahb"); 252 sp->clk = devm_clk_get(&pdev->dev, "ahb");
253 if (IS_ERR(sp->clk)) { 253 if (IS_ERR(sp->clk)) {
254 ret = PTR_ERR(sp->clk); 254 ret = PTR_ERR(sp->clk);
255 goto err_unmap; 255 goto err_put_master;
256 } 256 }
257 257
258 ret = clk_enable(sp->clk); 258 ret = clk_enable(sp->clk);
259 if (ret) 259 if (ret)
260 goto err_clk_put; 260 goto err_put_master;
261 261
262 rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ); 262 rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ);
263 if (!rate) { 263 if (!rate) {
@@ -280,10 +280,6 @@ err_disable:
280 ath79_spi_disable(sp); 280 ath79_spi_disable(sp);
281err_clk_disable: 281err_clk_disable:
282 clk_disable(sp->clk); 282 clk_disable(sp->clk);
283err_clk_put:
284 clk_put(sp->clk);
285err_unmap:
286 iounmap(sp->base);
287err_put_master: 283err_put_master:
288 spi_master_put(sp->bitbang.master); 284 spi_master_put(sp->bitbang.master);
289 285
@@ -297,8 +293,6 @@ static int ath79_spi_remove(struct platform_device *pdev)
297 spi_bitbang_stop(&sp->bitbang); 293 spi_bitbang_stop(&sp->bitbang);
298 ath79_spi_disable(sp); 294 ath79_spi_disable(sp);
299 clk_disable(sp->clk); 295 clk_disable(sp->clk);
300 clk_put(sp->clk);
301 iounmap(sp->base);
302 spi_master_put(sp->bitbang.master); 296 spi_master_put(sp->bitbang.master);
303 297
304 return 0; 298 return 0;
diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
index 273db0beb2b8..b0842f751016 100644
--- a/drivers/spi/spi-atmel.c
+++ b/drivers/spi/spi-atmel.c
@@ -189,6 +189,8 @@
189 */ 189 */
190#define DMA_MIN_BYTES 16 190#define DMA_MIN_BYTES 16
191 191
192#define SPI_DMA_TIMEOUT (msecs_to_jiffies(1000))
193
192struct atmel_spi_dma { 194struct atmel_spi_dma {
193 struct dma_chan *chan_rx; 195 struct dma_chan *chan_rx;
194 struct dma_chan *chan_tx; 196 struct dma_chan *chan_tx;
@@ -220,17 +222,13 @@ struct atmel_spi {
220 int irq; 222 int irq;
221 struct clk *clk; 223 struct clk *clk;
222 struct platform_device *pdev; 224 struct platform_device *pdev;
223 struct spi_device *stay;
224 225
225 u8 stopping;
226 struct list_head queue;
227 struct tasklet_struct tasklet;
228 struct spi_transfer *current_transfer; 226 struct spi_transfer *current_transfer;
229 unsigned long current_remaining_bytes; 227 unsigned long current_remaining_bytes;
230 struct spi_transfer *next_transfer;
231 unsigned long next_remaining_bytes;
232 int done_status; 228 int done_status;
233 229
230 struct completion xfer_completion;
231
234 /* scratch buffer */ 232 /* scratch buffer */
235 void *buffer; 233 void *buffer;
236 dma_addr_t buffer_dma; 234 dma_addr_t buffer_dma;
@@ -241,6 +239,9 @@ struct atmel_spi {
241 bool use_pdc; 239 bool use_pdc;
242 /* dmaengine data */ 240 /* dmaengine data */
243 struct atmel_spi_dma dma; 241 struct atmel_spi_dma dma;
242
243 bool keep_cs;
244 bool cs_active;
244}; 245};
245 246
246/* Controller-specific per-slave state */ 247/* Controller-specific per-slave state */
@@ -376,17 +377,6 @@ static inline bool atmel_spi_use_dma(struct atmel_spi *as,
376 return as->use_dma && xfer->len >= DMA_MIN_BYTES; 377 return as->use_dma && xfer->len >= DMA_MIN_BYTES;
377} 378}
378 379
379static inline int atmel_spi_xfer_is_last(struct spi_message *msg,
380 struct spi_transfer *xfer)
381{
382 return msg->transfers.prev == &xfer->transfer_list;
383}
384
385static inline int atmel_spi_xfer_can_be_chained(struct spi_transfer *xfer)
386{
387 return xfer->delay_usecs == 0 && !xfer->cs_change;
388}
389
390static int atmel_spi_dma_slave_config(struct atmel_spi *as, 380static int atmel_spi_dma_slave_config(struct atmel_spi *as,
391 struct dma_slave_config *slave_config, 381 struct dma_slave_config *slave_config,
392 u8 bits_per_word) 382 u8 bits_per_word)
@@ -513,23 +503,20 @@ static void dma_callback(void *data)
513 struct spi_master *master = data; 503 struct spi_master *master = data;
514 struct atmel_spi *as = spi_master_get_devdata(master); 504 struct atmel_spi *as = spi_master_get_devdata(master);
515 505
516 /* trigger SPI tasklet */ 506 complete(&as->xfer_completion);
517 tasklet_schedule(&as->tasklet);
518} 507}
519 508
520/* 509/*
521 * Next transfer using PIO. 510 * Next transfer using PIO.
522 * lock is held, spi tasklet is blocked
523 */ 511 */
524static void atmel_spi_next_xfer_pio(struct spi_master *master, 512static void atmel_spi_next_xfer_pio(struct spi_master *master,
525 struct spi_transfer *xfer) 513 struct spi_transfer *xfer)
526{ 514{
527 struct atmel_spi *as = spi_master_get_devdata(master); 515 struct atmel_spi *as = spi_master_get_devdata(master);
516 unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
528 517
529 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_pio\n"); 518 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_pio\n");
530 519
531 as->current_remaining_bytes = xfer->len;
532
533 /* Make sure data is not remaining in RDR */ 520 /* Make sure data is not remaining in RDR */
534 spi_readl(as, RDR); 521 spi_readl(as, RDR);
535 while (spi_readl(as, SR) & SPI_BIT(RDRF)) { 522 while (spi_readl(as, SR) & SPI_BIT(RDRF)) {
@@ -537,13 +524,14 @@ static void atmel_spi_next_xfer_pio(struct spi_master *master,
537 cpu_relax(); 524 cpu_relax();
538 } 525 }
539 526
540 if (xfer->tx_buf) 527 if (xfer->tx_buf) {
541 if (xfer->bits_per_word > 8) 528 if (xfer->bits_per_word > 8)
542 spi_writel(as, TDR, *(u16 *)(xfer->tx_buf)); 529 spi_writel(as, TDR, *(u16 *)(xfer->tx_buf + xfer_pos));
543 else 530 else
544 spi_writel(as, TDR, *(u8 *)(xfer->tx_buf)); 531 spi_writel(as, TDR, *(u8 *)(xfer->tx_buf + xfer_pos));
545 else 532 } else {
546 spi_writel(as, TDR, 0); 533 spi_writel(as, TDR, 0);
534 }
547 535
548 dev_dbg(master->dev.parent, 536 dev_dbg(master->dev.parent,
549 " start pio xfer %p: len %u tx %p rx %p bitpw %d\n", 537 " start pio xfer %p: len %u tx %p rx %p bitpw %d\n",
@@ -556,7 +544,6 @@ static void atmel_spi_next_xfer_pio(struct spi_master *master,
556 544
557/* 545/*
558 * Submit next transfer for DMA. 546 * Submit next transfer for DMA.
559 * lock is held, spi tasklet is blocked
560 */ 547 */
561static int atmel_spi_next_xfer_dma_submit(struct spi_master *master, 548static int atmel_spi_next_xfer_dma_submit(struct spi_master *master,
562 struct spi_transfer *xfer, 549 struct spi_transfer *xfer,
@@ -694,74 +681,90 @@ static void atmel_spi_next_xfer_data(struct spi_master *master,
694 *plen = len; 681 *plen = len;
695} 682}
696 683
684static int atmel_spi_set_xfer_speed(struct atmel_spi *as,
685 struct spi_device *spi,
686 struct spi_transfer *xfer)
687{
688 u32 scbr, csr;
689 unsigned long bus_hz;
690
691 /* v1 chips start out at half the peripheral bus speed. */
692 bus_hz = clk_get_rate(as->clk);
693 if (!atmel_spi_is_v2(as))
694 bus_hz /= 2;
695
696 /*
697 * Calculate the lowest divider that satisfies the
698 * constraint, assuming div32/fdiv/mbz == 0.
699 */
700 if (xfer->speed_hz)
701 scbr = DIV_ROUND_UP(bus_hz, xfer->speed_hz);
702 else
703 /*
704 * This can happend if max_speed is null.
705 * In this case, we set the lowest possible speed
706 */
707 scbr = 0xff;
708
709 /*
710 * If the resulting divider doesn't fit into the
711 * register bitfield, we can't satisfy the constraint.
712 */
713 if (scbr >= (1 << SPI_SCBR_SIZE)) {
714 dev_err(&spi->dev,
715 "setup: %d Hz too slow, scbr %u; min %ld Hz\n",
716 xfer->speed_hz, scbr, bus_hz/255);
717 return -EINVAL;
718 }
719 if (scbr == 0) {
720 dev_err(&spi->dev,
721 "setup: %d Hz too high, scbr %u; max %ld Hz\n",
722 xfer->speed_hz, scbr, bus_hz);
723 return -EINVAL;
724 }
725 csr = spi_readl(as, CSR0 + 4 * spi->chip_select);
726 csr = SPI_BFINS(SCBR, scbr, csr);
727 spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
728
729 return 0;
730}
731
697/* 732/*
698 * Submit next transfer for PDC. 733 * Submit next transfer for PDC.
699 * lock is held, spi irq is blocked 734 * lock is held, spi irq is blocked
700 */ 735 */
701static void atmel_spi_pdc_next_xfer(struct spi_master *master, 736static void atmel_spi_pdc_next_xfer(struct spi_master *master,
702 struct spi_message *msg) 737 struct spi_message *msg,
738 struct spi_transfer *xfer)
703{ 739{
704 struct atmel_spi *as = spi_master_get_devdata(master); 740 struct atmel_spi *as = spi_master_get_devdata(master);
705 struct spi_transfer *xfer; 741 u32 len;
706 u32 len, remaining;
707 u32 ieval;
708 dma_addr_t tx_dma, rx_dma; 742 dma_addr_t tx_dma, rx_dma;
709 743
710 if (!as->current_transfer) 744 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
711 xfer = list_entry(msg->transfers.next,
712 struct spi_transfer, transfer_list);
713 else if (!as->next_transfer)
714 xfer = list_entry(as->current_transfer->transfer_list.next,
715 struct spi_transfer, transfer_list);
716 else
717 xfer = NULL;
718
719 if (xfer) {
720 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
721
722 len = xfer->len;
723 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
724 remaining = xfer->len - len;
725
726 spi_writel(as, RPR, rx_dma);
727 spi_writel(as, TPR, tx_dma);
728
729 if (msg->spi->bits_per_word > 8)
730 len >>= 1;
731 spi_writel(as, RCR, len);
732 spi_writel(as, TCR, len);
733
734 dev_dbg(&msg->spi->dev,
735 " start xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
736 xfer, xfer->len, xfer->tx_buf,
737 (unsigned long long)xfer->tx_dma, xfer->rx_buf,
738 (unsigned long long)xfer->rx_dma);
739 } else {
740 xfer = as->next_transfer;
741 remaining = as->next_remaining_bytes;
742 }
743 745
744 as->current_transfer = xfer; 746 len = as->current_remaining_bytes;
745 as->current_remaining_bytes = remaining; 747 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
748 as->current_remaining_bytes -= len;
746 749
747 if (remaining > 0) 750 spi_writel(as, RPR, rx_dma);
748 len = remaining; 751 spi_writel(as, TPR, tx_dma);
749 else if (!atmel_spi_xfer_is_last(msg, xfer)
750 && atmel_spi_xfer_can_be_chained(xfer)) {
751 xfer = list_entry(xfer->transfer_list.next,
752 struct spi_transfer, transfer_list);
753 len = xfer->len;
754 } else
755 xfer = NULL;
756 752
757 as->next_transfer = xfer; 753 if (msg->spi->bits_per_word > 8)
754 len >>= 1;
755 spi_writel(as, RCR, len);
756 spi_writel(as, TCR, len);
758 757
759 if (xfer) { 758 dev_dbg(&msg->spi->dev,
760 u32 total; 759 " start xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
760 xfer, xfer->len, xfer->tx_buf,
761 (unsigned long long)xfer->tx_dma, xfer->rx_buf,
762 (unsigned long long)xfer->rx_dma);
761 763
762 total = len; 764 if (as->current_remaining_bytes) {
765 len = as->current_remaining_bytes;
763 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len); 766 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
764 as->next_remaining_bytes = total - len; 767 as->current_remaining_bytes -= len;
765 768
766 spi_writel(as, RNPR, rx_dma); 769 spi_writel(as, RNPR, rx_dma);
767 spi_writel(as, TNPR, tx_dma); 770 spi_writel(as, TNPR, tx_dma);
@@ -776,11 +779,6 @@ static void atmel_spi_pdc_next_xfer(struct spi_master *master,
776 xfer, xfer->len, xfer->tx_buf, 779 xfer, xfer->len, xfer->tx_buf,
777 (unsigned long long)xfer->tx_dma, xfer->rx_buf, 780 (unsigned long long)xfer->tx_dma, xfer->rx_buf,
778 (unsigned long long)xfer->rx_dma); 781 (unsigned long long)xfer->rx_dma);
779 ieval = SPI_BIT(ENDRX) | SPI_BIT(OVRES);
780 } else {
781 spi_writel(as, RNCR, 0);
782 spi_writel(as, TNCR, 0);
783 ieval = SPI_BIT(RXBUFF) | SPI_BIT(ENDRX) | SPI_BIT(OVRES);
784 } 782 }
785 783
786 /* REVISIT: We're waiting for ENDRX before we start the next 784 /* REVISIT: We're waiting for ENDRX before we start the next
@@ -793,83 +791,11 @@ static void atmel_spi_pdc_next_xfer(struct spi_master *master,
793 * 791 *
794 * It should be doable, though. Just not now... 792 * It should be doable, though. Just not now...
795 */ 793 */
796 spi_writel(as, IER, ieval); 794 spi_writel(as, IER, SPI_BIT(ENDRX) | SPI_BIT(OVRES));
797 spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN)); 795 spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
798} 796}
799 797
800/* 798/*
801 * Choose way to submit next transfer and start it.
802 * lock is held, spi tasklet is blocked
803 */
804static void atmel_spi_dma_next_xfer(struct spi_master *master,
805 struct spi_message *msg)
806{
807 struct atmel_spi *as = spi_master_get_devdata(master);
808 struct spi_transfer *xfer;
809 u32 remaining, len;
810
811 remaining = as->current_remaining_bytes;
812 if (remaining) {
813 xfer = as->current_transfer;
814 len = remaining;
815 } else {
816 if (!as->current_transfer)
817 xfer = list_entry(msg->transfers.next,
818 struct spi_transfer, transfer_list);
819 else
820 xfer = list_entry(
821 as->current_transfer->transfer_list.next,
822 struct spi_transfer, transfer_list);
823
824 as->current_transfer = xfer;
825 len = xfer->len;
826 }
827
828 if (atmel_spi_use_dma(as, xfer)) {
829 u32 total = len;
830 if (!atmel_spi_next_xfer_dma_submit(master, xfer, &len)) {
831 as->current_remaining_bytes = total - len;
832 return;
833 } else {
834 dev_err(&msg->spi->dev, "unable to use DMA, fallback to PIO\n");
835 }
836 }
837
838 /* use PIO if error appened using DMA */
839 atmel_spi_next_xfer_pio(master, xfer);
840}
841
842static void atmel_spi_next_message(struct spi_master *master)
843{
844 struct atmel_spi *as = spi_master_get_devdata(master);
845 struct spi_message *msg;
846 struct spi_device *spi;
847
848 BUG_ON(as->current_transfer);
849
850 msg = list_entry(as->queue.next, struct spi_message, queue);
851 spi = msg->spi;
852
853 dev_dbg(master->dev.parent, "start message %p for %s\n",
854 msg, dev_name(&spi->dev));
855
856 /* select chip if it's not still active */
857 if (as->stay) {
858 if (as->stay != spi) {
859 cs_deactivate(as, as->stay);
860 cs_activate(as, spi);
861 }
862 as->stay = NULL;
863 } else
864 cs_activate(as, spi);
865
866 if (as->use_pdc)
867 atmel_spi_pdc_next_xfer(master, msg);
868 else
869 atmel_spi_dma_next_xfer(master, msg);
870}
871
872/*
873 * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma: 799 * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma:
874 * - The buffer is either valid for CPU access, else NULL 800 * - The buffer is either valid for CPU access, else NULL
875 * - If the buffer is valid, so is its DMA address 801 * - If the buffer is valid, so is its DMA address
@@ -924,41 +850,7 @@ static void atmel_spi_disable_pdc_transfer(struct atmel_spi *as)
924 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); 850 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
925} 851}
926 852
927static void
928atmel_spi_msg_done(struct spi_master *master, struct atmel_spi *as,
929 struct spi_message *msg, int stay)
930{
931 if (!stay || as->done_status < 0)
932 cs_deactivate(as, msg->spi);
933 else
934 as->stay = msg->spi;
935
936 list_del(&msg->queue);
937 msg->status = as->done_status;
938
939 dev_dbg(master->dev.parent,
940 "xfer complete: %u bytes transferred\n",
941 msg->actual_length);
942
943 atmel_spi_unlock(as);
944 msg->complete(msg->context);
945 atmel_spi_lock(as);
946
947 as->current_transfer = NULL;
948 as->next_transfer = NULL;
949 as->done_status = 0;
950
951 /* continue if needed */
952 if (list_empty(&as->queue) || as->stopping) {
953 if (as->use_pdc)
954 atmel_spi_disable_pdc_transfer(as);
955 } else {
956 atmel_spi_next_message(master);
957 }
958}
959
960/* Called from IRQ 853/* Called from IRQ
961 * lock is held
962 * 854 *
963 * Must update "current_remaining_bytes" to keep track of data 855 * Must update "current_remaining_bytes" to keep track of data
964 * to transfer. 856 * to transfer.
@@ -966,9 +858,7 @@ atmel_spi_msg_done(struct spi_master *master, struct atmel_spi *as,
966static void 858static void
967atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer) 859atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer)
968{ 860{
969 u8 *txp;
970 u8 *rxp; 861 u8 *rxp;
971 u16 *txp16;
972 u16 *rxp16; 862 u16 *rxp16;
973 unsigned long xfer_pos = xfer->len - as->current_remaining_bytes; 863 unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
974 864
@@ -990,96 +880,12 @@ atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer)
990 } else { 880 } else {
991 as->current_remaining_bytes--; 881 as->current_remaining_bytes--;
992 } 882 }
993
994 if (as->current_remaining_bytes) {
995 if (xfer->tx_buf) {
996 if (xfer->bits_per_word > 8) {
997 txp16 = (u16 *)(((u8 *)xfer->tx_buf)
998 + xfer_pos + 2);
999 spi_writel(as, TDR, *txp16);
1000 } else {
1001 txp = ((u8 *)xfer->tx_buf) + xfer_pos + 1;
1002 spi_writel(as, TDR, *txp);
1003 }
1004 } else {
1005 spi_writel(as, TDR, 0);
1006 }
1007 }
1008}
1009
1010/* Tasklet
1011 * Called from DMA callback + pio transfer and overrun IRQ.
1012 */
1013static void atmel_spi_tasklet_func(unsigned long data)
1014{
1015 struct spi_master *master = (struct spi_master *)data;
1016 struct atmel_spi *as = spi_master_get_devdata(master);
1017 struct spi_message *msg;
1018 struct spi_transfer *xfer;
1019
1020 dev_vdbg(master->dev.parent, "atmel_spi_tasklet_func\n");
1021
1022 atmel_spi_lock(as);
1023
1024 xfer = as->current_transfer;
1025
1026 if (xfer == NULL)
1027 /* already been there */
1028 goto tasklet_out;
1029
1030 msg = list_entry(as->queue.next, struct spi_message, queue);
1031
1032 if (as->current_remaining_bytes == 0) {
1033 if (as->done_status < 0) {
1034 /* error happened (overrun) */
1035 if (atmel_spi_use_dma(as, xfer))
1036 atmel_spi_stop_dma(as);
1037 } else {
1038 /* only update length if no error */
1039 msg->actual_length += xfer->len;
1040 }
1041
1042 if (atmel_spi_use_dma(as, xfer))
1043 if (!msg->is_dma_mapped)
1044 atmel_spi_dma_unmap_xfer(master, xfer);
1045
1046 if (xfer->delay_usecs)
1047 udelay(xfer->delay_usecs);
1048
1049 if (atmel_spi_xfer_is_last(msg, xfer) || as->done_status < 0) {
1050 /* report completed (or erroneous) message */
1051 atmel_spi_msg_done(master, as, msg, xfer->cs_change);
1052 } else {
1053 if (xfer->cs_change) {
1054 cs_deactivate(as, msg->spi);
1055 udelay(1);
1056 cs_activate(as, msg->spi);
1057 }
1058
1059 /*
1060 * Not done yet. Submit the next transfer.
1061 *
1062 * FIXME handle protocol options for xfer
1063 */
1064 atmel_spi_dma_next_xfer(master, msg);
1065 }
1066 } else {
1067 /*
1068 * Keep going, we still have data to send in
1069 * the current transfer.
1070 */
1071 atmel_spi_dma_next_xfer(master, msg);
1072 }
1073
1074tasklet_out:
1075 atmel_spi_unlock(as);
1076} 883}
1077 884
1078/* Interrupt 885/* Interrupt
1079 * 886 *
1080 * No need for locking in this Interrupt handler: done_status is the 887 * No need for locking in this Interrupt handler: done_status is the
1081 * only information modified. What we need is the update of this field 888 * only information modified.
1082 * before tasklet runs. This is ensured by using barrier.
1083 */ 889 */
1084static irqreturn_t 890static irqreturn_t
1085atmel_spi_pio_interrupt(int irq, void *dev_id) 891atmel_spi_pio_interrupt(int irq, void *dev_id)
@@ -1107,8 +913,6 @@ atmel_spi_pio_interrupt(int irq, void *dev_id)
1107 * 913 *
1108 * We will also not process any remaning transfers in 914 * We will also not process any remaning transfers in
1109 * the message. 915 * the message.
1110 *
1111 * All actions are done in tasklet with done_status indication
1112 */ 916 */
1113 as->done_status = -EIO; 917 as->done_status = -EIO;
1114 smp_wmb(); 918 smp_wmb();
@@ -1116,7 +920,7 @@ atmel_spi_pio_interrupt(int irq, void *dev_id)
1116 /* Clear any overrun happening while cleaning up */ 920 /* Clear any overrun happening while cleaning up */
1117 spi_readl(as, SR); 921 spi_readl(as, SR);
1118 922
1119 tasklet_schedule(&as->tasklet); 923 complete(&as->xfer_completion);
1120 924
1121 } else if (pending & SPI_BIT(RDRF)) { 925 } else if (pending & SPI_BIT(RDRF)) {
1122 atmel_spi_lock(as); 926 atmel_spi_lock(as);
@@ -1125,11 +929,10 @@ atmel_spi_pio_interrupt(int irq, void *dev_id)
1125 ret = IRQ_HANDLED; 929 ret = IRQ_HANDLED;
1126 xfer = as->current_transfer; 930 xfer = as->current_transfer;
1127 atmel_spi_pump_pio_data(as, xfer); 931 atmel_spi_pump_pio_data(as, xfer);
1128 if (!as->current_remaining_bytes) { 932 if (!as->current_remaining_bytes)
1129 /* no more data to xfer, kick tasklet */
1130 spi_writel(as, IDR, pending); 933 spi_writel(as, IDR, pending);
1131 tasklet_schedule(&as->tasklet); 934
1132 } 935 complete(&as->xfer_completion);
1133 } 936 }
1134 937
1135 atmel_spi_unlock(as); 938 atmel_spi_unlock(as);
@@ -1147,116 +950,35 @@ atmel_spi_pdc_interrupt(int irq, void *dev_id)
1147{ 950{
1148 struct spi_master *master = dev_id; 951 struct spi_master *master = dev_id;
1149 struct atmel_spi *as = spi_master_get_devdata(master); 952 struct atmel_spi *as = spi_master_get_devdata(master);
1150 struct spi_message *msg;
1151 struct spi_transfer *xfer;
1152 u32 status, pending, imr; 953 u32 status, pending, imr;
1153 int ret = IRQ_NONE; 954 int ret = IRQ_NONE;
1154 955
1155 atmel_spi_lock(as);
1156
1157 xfer = as->current_transfer;
1158 msg = list_entry(as->queue.next, struct spi_message, queue);
1159
1160 imr = spi_readl(as, IMR); 956 imr = spi_readl(as, IMR);
1161 status = spi_readl(as, SR); 957 status = spi_readl(as, SR);
1162 pending = status & imr; 958 pending = status & imr;
1163 959
1164 if (pending & SPI_BIT(OVRES)) { 960 if (pending & SPI_BIT(OVRES)) {
1165 int timeout;
1166 961
1167 ret = IRQ_HANDLED; 962 ret = IRQ_HANDLED;
1168 963
1169 spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX) 964 spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
1170 | SPI_BIT(OVRES))); 965 | SPI_BIT(OVRES)));
1171 966
1172 /*
1173 * When we get an overrun, we disregard the current
1174 * transfer. Data will not be copied back from any
1175 * bounce buffer and msg->actual_len will not be
1176 * updated with the last xfer.
1177 *
1178 * We will also not process any remaning transfers in
1179 * the message.
1180 *
1181 * First, stop the transfer and unmap the DMA buffers.
1182 */
1183 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
1184 if (!msg->is_dma_mapped)
1185 atmel_spi_dma_unmap_xfer(master, xfer);
1186
1187 /* REVISIT: udelay in irq is unfriendly */
1188 if (xfer->delay_usecs)
1189 udelay(xfer->delay_usecs);
1190
1191 dev_warn(master->dev.parent, "overrun (%u/%u remaining)\n",
1192 spi_readl(as, TCR), spi_readl(as, RCR));
1193
1194 /*
1195 * Clean up DMA registers and make sure the data
1196 * registers are empty.
1197 */
1198 spi_writel(as, RNCR, 0);
1199 spi_writel(as, TNCR, 0);
1200 spi_writel(as, RCR, 0);
1201 spi_writel(as, TCR, 0);
1202 for (timeout = 1000; timeout; timeout--)
1203 if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
1204 break;
1205 if (!timeout)
1206 dev_warn(master->dev.parent,
1207 "timeout waiting for TXEMPTY");
1208 while (spi_readl(as, SR) & SPI_BIT(RDRF))
1209 spi_readl(as, RDR);
1210
1211 /* Clear any overrun happening while cleaning up */ 967 /* Clear any overrun happening while cleaning up */
1212 spi_readl(as, SR); 968 spi_readl(as, SR);
1213 969
1214 as->done_status = -EIO; 970 as->done_status = -EIO;
1215 atmel_spi_msg_done(master, as, msg, 0); 971
972 complete(&as->xfer_completion);
973
1216 } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) { 974 } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) {
1217 ret = IRQ_HANDLED; 975 ret = IRQ_HANDLED;
1218 976
1219 spi_writel(as, IDR, pending); 977 spi_writel(as, IDR, pending);
1220 978
1221 if (as->current_remaining_bytes == 0) { 979 complete(&as->xfer_completion);
1222 msg->actual_length += xfer->len;
1223
1224 if (!msg->is_dma_mapped)
1225 atmel_spi_dma_unmap_xfer(master, xfer);
1226
1227 /* REVISIT: udelay in irq is unfriendly */
1228 if (xfer->delay_usecs)
1229 udelay(xfer->delay_usecs);
1230
1231 if (atmel_spi_xfer_is_last(msg, xfer)) {
1232 /* report completed message */
1233 atmel_spi_msg_done(master, as, msg,
1234 xfer->cs_change);
1235 } else {
1236 if (xfer->cs_change) {
1237 cs_deactivate(as, msg->spi);
1238 udelay(1);
1239 cs_activate(as, msg->spi);
1240 }
1241
1242 /*
1243 * Not done yet. Submit the next transfer.
1244 *
1245 * FIXME handle protocol options for xfer
1246 */
1247 atmel_spi_pdc_next_xfer(master, msg);
1248 }
1249 } else {
1250 /*
1251 * Keep going, we still have data to send in
1252 * the current transfer.
1253 */
1254 atmel_spi_pdc_next_xfer(master, msg);
1255 }
1256 } 980 }
1257 981
1258 atmel_spi_unlock(as);
1259
1260 return ret; 982 return ret;
1261} 983}
1262 984
@@ -1264,17 +986,13 @@ static int atmel_spi_setup(struct spi_device *spi)
1264{ 986{
1265 struct atmel_spi *as; 987 struct atmel_spi *as;
1266 struct atmel_spi_device *asd; 988 struct atmel_spi_device *asd;
1267 u32 scbr, csr; 989 u32 csr;
1268 unsigned int bits = spi->bits_per_word; 990 unsigned int bits = spi->bits_per_word;
1269 unsigned long bus_hz;
1270 unsigned int npcs_pin; 991 unsigned int npcs_pin;
1271 int ret; 992 int ret;
1272 993
1273 as = spi_master_get_devdata(spi->master); 994 as = spi_master_get_devdata(spi->master);
1274 995
1275 if (as->stopping)
1276 return -ESHUTDOWN;
1277
1278 if (spi->chip_select > spi->master->num_chipselect) { 996 if (spi->chip_select > spi->master->num_chipselect) {
1279 dev_dbg(&spi->dev, 997 dev_dbg(&spi->dev,
1280 "setup: invalid chipselect %u (%u defined)\n", 998 "setup: invalid chipselect %u (%u defined)\n",
@@ -1290,33 +1008,7 @@ static int atmel_spi_setup(struct spi_device *spi)
1290 return -EINVAL; 1008 return -EINVAL;
1291 } 1009 }
1292 1010
1293 /* v1 chips start out at half the peripheral bus speed. */ 1011 csr = SPI_BF(BITS, bits - 8);
1294 bus_hz = clk_get_rate(as->clk);
1295 if (!atmel_spi_is_v2(as))
1296 bus_hz /= 2;
1297
1298 if (spi->max_speed_hz) {
1299 /*
1300 * Calculate the lowest divider that satisfies the
1301 * constraint, assuming div32/fdiv/mbz == 0.
1302 */
1303 scbr = DIV_ROUND_UP(bus_hz, spi->max_speed_hz);
1304
1305 /*
1306 * If the resulting divider doesn't fit into the
1307 * register bitfield, we can't satisfy the constraint.
1308 */
1309 if (scbr >= (1 << SPI_SCBR_SIZE)) {
1310 dev_dbg(&spi->dev,
1311 "setup: %d Hz too slow, scbr %u; min %ld Hz\n",
1312 spi->max_speed_hz, scbr, bus_hz/255);
1313 return -EINVAL;
1314 }
1315 } else
1316 /* speed zero means "as slow as possible" */
1317 scbr = 0xff;
1318
1319 csr = SPI_BF(SCBR, scbr) | SPI_BF(BITS, bits - 8);
1320 if (spi->mode & SPI_CPOL) 1012 if (spi->mode & SPI_CPOL)
1321 csr |= SPI_BIT(CPOL); 1013 csr |= SPI_BIT(CPOL);
1322 if (!(spi->mode & SPI_CPHA)) 1014 if (!(spi->mode & SPI_CPHA))
@@ -1352,19 +1044,13 @@ static int atmel_spi_setup(struct spi_device *spi)
1352 asd->npcs_pin = npcs_pin; 1044 asd->npcs_pin = npcs_pin;
1353 spi->controller_state = asd; 1045 spi->controller_state = asd;
1354 gpio_direction_output(npcs_pin, !(spi->mode & SPI_CS_HIGH)); 1046 gpio_direction_output(npcs_pin, !(spi->mode & SPI_CS_HIGH));
1355 } else {
1356 atmel_spi_lock(as);
1357 if (as->stay == spi)
1358 as->stay = NULL;
1359 cs_deactivate(as, spi);
1360 atmel_spi_unlock(as);
1361 } 1047 }
1362 1048
1363 asd->csr = csr; 1049 asd->csr = csr;
1364 1050
1365 dev_dbg(&spi->dev, 1051 dev_dbg(&spi->dev,
1366 "setup: %lu Hz bpw %u mode 0x%x -> csr%d %08x\n", 1052 "setup: bpw %u mode 0x%x -> csr%d %08x\n",
1367 bus_hz / scbr, bits, spi->mode, spi->chip_select, csr); 1053 bits, spi->mode, spi->chip_select, csr);
1368 1054
1369 if (!atmel_spi_is_v2(as)) 1055 if (!atmel_spi_is_v2(as))
1370 spi_writel(as, CSR0 + 4 * spi->chip_select, csr); 1056 spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
@@ -1372,103 +1058,218 @@ static int atmel_spi_setup(struct spi_device *spi)
1372 return 0; 1058 return 0;
1373} 1059}
1374 1060
1375static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg) 1061static int atmel_spi_one_transfer(struct spi_master *master,
1062 struct spi_message *msg,
1063 struct spi_transfer *xfer)
1376{ 1064{
1377 struct atmel_spi *as; 1065 struct atmel_spi *as;
1378 struct spi_transfer *xfer; 1066 struct spi_device *spi = msg->spi;
1379 struct device *controller = spi->master->dev.parent;
1380 u8 bits; 1067 u8 bits;
1068 u32 len;
1381 struct atmel_spi_device *asd; 1069 struct atmel_spi_device *asd;
1070 int timeout;
1071 int ret;
1382 1072
1383 as = spi_master_get_devdata(spi->master); 1073 as = spi_master_get_devdata(master);
1384
1385 dev_dbg(controller, "new message %p submitted for %s\n",
1386 msg, dev_name(&spi->dev));
1387 1074
1388 if (unlikely(list_empty(&msg->transfers))) 1075 if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) {
1076 dev_dbg(&spi->dev, "missing rx or tx buf\n");
1389 return -EINVAL; 1077 return -EINVAL;
1078 }
1390 1079
1391 if (as->stopping) 1080 if (xfer->bits_per_word) {
1392 return -ESHUTDOWN; 1081 asd = spi->controller_state;
1082 bits = (asd->csr >> 4) & 0xf;
1083 if (bits != xfer->bits_per_word - 8) {
1084 dev_dbg(&spi->dev,
1085 "you can't yet change bits_per_word in transfers\n");
1086 return -ENOPROTOOPT;
1087 }
1088 }
1393 1089
1394 list_for_each_entry(xfer, &msg->transfers, transfer_list) { 1090 if (xfer->bits_per_word > 8) {
1395 if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) { 1091 if (xfer->len % 2) {
1396 dev_dbg(&spi->dev, "missing rx or tx buf\n"); 1092 dev_dbg(&spi->dev,
1093 "buffer len should be 16 bits aligned\n");
1397 return -EINVAL; 1094 return -EINVAL;
1398 } 1095 }
1096 }
1399 1097
1400 if (xfer->bits_per_word) { 1098 /*
1401 asd = spi->controller_state; 1099 * DMA map early, for performance (empties dcache ASAP) and
1402 bits = (asd->csr >> 4) & 0xf; 1100 * better fault reporting.
1403 if (bits != xfer->bits_per_word - 8) { 1101 */
1404 dev_dbg(&spi->dev, 1102 if ((!msg->is_dma_mapped)
1405 "you can't yet change bits_per_word in transfers\n"); 1103 && (atmel_spi_use_dma(as, xfer) || as->use_pdc)) {
1406 return -ENOPROTOOPT; 1104 if (atmel_spi_dma_map_xfer(as, xfer) < 0)
1105 return -ENOMEM;
1106 }
1107
1108 atmel_spi_set_xfer_speed(as, msg->spi, xfer);
1109
1110 as->done_status = 0;
1111 as->current_transfer = xfer;
1112 as->current_remaining_bytes = xfer->len;
1113 while (as->current_remaining_bytes) {
1114 reinit_completion(&as->xfer_completion);
1115
1116 if (as->use_pdc) {
1117 atmel_spi_pdc_next_xfer(master, msg, xfer);
1118 } else if (atmel_spi_use_dma(as, xfer)) {
1119 len = as->current_remaining_bytes;
1120 ret = atmel_spi_next_xfer_dma_submit(master,
1121 xfer, &len);
1122 if (ret) {
1123 dev_err(&spi->dev,
1124 "unable to use DMA, fallback to PIO\n");
1125 atmel_spi_next_xfer_pio(master, xfer);
1126 } else {
1127 as->current_remaining_bytes -= len;
1407 } 1128 }
1129 } else {
1130 atmel_spi_next_xfer_pio(master, xfer);
1408 } 1131 }
1409 1132
1410 if (xfer->bits_per_word > 8) { 1133 ret = wait_for_completion_timeout(&as->xfer_completion,
1411 if (xfer->len % 2) { 1134 SPI_DMA_TIMEOUT);
1412 dev_dbg(&spi->dev, "buffer len should be 16 bits aligned\n"); 1135 if (WARN_ON(ret == 0)) {
1413 return -EINVAL; 1136 dev_err(&spi->dev,
1414 } 1137 "spi trasfer timeout, err %d\n", ret);
1138 as->done_status = -EIO;
1139 } else {
1140 ret = 0;
1415 } 1141 }
1416 1142
1417 /* FIXME implement these protocol options!! */ 1143 if (as->done_status)
1418 if (xfer->speed_hz < spi->max_speed_hz) { 1144 break;
1419 dev_dbg(&spi->dev, "can't change speed in transfer\n"); 1145 }
1420 return -ENOPROTOOPT; 1146
1147 if (as->done_status) {
1148 if (as->use_pdc) {
1149 dev_warn(master->dev.parent,
1150 "overrun (%u/%u remaining)\n",
1151 spi_readl(as, TCR), spi_readl(as, RCR));
1152
1153 /*
1154 * Clean up DMA registers and make sure the data
1155 * registers are empty.
1156 */
1157 spi_writel(as, RNCR, 0);
1158 spi_writel(as, TNCR, 0);
1159 spi_writel(as, RCR, 0);
1160 spi_writel(as, TCR, 0);
1161 for (timeout = 1000; timeout; timeout--)
1162 if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
1163 break;
1164 if (!timeout)
1165 dev_warn(master->dev.parent,
1166 "timeout waiting for TXEMPTY");
1167 while (spi_readl(as, SR) & SPI_BIT(RDRF))
1168 spi_readl(as, RDR);
1169
1170 /* Clear any overrun happening while cleaning up */
1171 spi_readl(as, SR);
1172
1173 } else if (atmel_spi_use_dma(as, xfer)) {
1174 atmel_spi_stop_dma(as);
1421 } 1175 }
1422 1176
1423 /* 1177 if (!msg->is_dma_mapped
1424 * DMA map early, for performance (empties dcache ASAP) and 1178 && (atmel_spi_use_dma(as, xfer) || as->use_pdc))
1425 * better fault reporting. 1179 atmel_spi_dma_unmap_xfer(master, xfer);
1426 */ 1180
1427 if ((!msg->is_dma_mapped) && (atmel_spi_use_dma(as, xfer) 1181 return 0;
1428 || as->use_pdc)) { 1182
1429 if (atmel_spi_dma_map_xfer(as, xfer) < 0) 1183 } else {
1430 return -ENOMEM; 1184 /* only update length if no error */
1185 msg->actual_length += xfer->len;
1186 }
1187
1188 if (!msg->is_dma_mapped
1189 && (atmel_spi_use_dma(as, xfer) || as->use_pdc))
1190 atmel_spi_dma_unmap_xfer(master, xfer);
1191
1192 if (xfer->delay_usecs)
1193 udelay(xfer->delay_usecs);
1194
1195 if (xfer->cs_change) {
1196 if (list_is_last(&xfer->transfer_list,
1197 &msg->transfers)) {
1198 as->keep_cs = true;
1199 } else {
1200 as->cs_active = !as->cs_active;
1201 if (as->cs_active)
1202 cs_activate(as, msg->spi);
1203 else
1204 cs_deactivate(as, msg->spi);
1431 } 1205 }
1432 } 1206 }
1433 1207
1434#ifdef VERBOSE 1208 return 0;
1209}
1210
1211static int atmel_spi_transfer_one_message(struct spi_master *master,
1212 struct spi_message *msg)
1213{
1214 struct atmel_spi *as;
1215 struct spi_transfer *xfer;
1216 struct spi_device *spi = msg->spi;
1217 int ret = 0;
1218
1219 as = spi_master_get_devdata(master);
1220
1221 dev_dbg(&spi->dev, "new message %p submitted for %s\n",
1222 msg, dev_name(&spi->dev));
1223
1224 if (unlikely(list_empty(&msg->transfers)))
1225 return -EINVAL;
1226
1227 atmel_spi_lock(as);
1228 cs_activate(as, spi);
1229
1230 as->cs_active = true;
1231 as->keep_cs = false;
1232
1233 msg->status = 0;
1234 msg->actual_length = 0;
1235
1435 list_for_each_entry(xfer, &msg->transfers, transfer_list) { 1236 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1436 dev_dbg(controller, 1237 ret = atmel_spi_one_transfer(master, msg, xfer);
1238 if (ret)
1239 goto msg_done;
1240 }
1241
1242 if (as->use_pdc)
1243 atmel_spi_disable_pdc_transfer(as);
1244
1245 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1246 dev_dbg(&spi->dev,
1437 " xfer %p: len %u tx %p/%08x rx %p/%08x\n", 1247 " xfer %p: len %u tx %p/%08x rx %p/%08x\n",
1438 xfer, xfer->len, 1248 xfer, xfer->len,
1439 xfer->tx_buf, xfer->tx_dma, 1249 xfer->tx_buf, xfer->tx_dma,
1440 xfer->rx_buf, xfer->rx_dma); 1250 xfer->rx_buf, xfer->rx_dma);
1441 } 1251 }
1442#endif
1443 1252
1444 msg->status = -EINPROGRESS; 1253msg_done:
1445 msg->actual_length = 0; 1254 if (!as->keep_cs)
1255 cs_deactivate(as, msg->spi);
1446 1256
1447 atmel_spi_lock(as);
1448 list_add_tail(&msg->queue, &as->queue);
1449 if (!as->current_transfer)
1450 atmel_spi_next_message(spi->master);
1451 atmel_spi_unlock(as); 1257 atmel_spi_unlock(as);
1452 1258
1453 return 0; 1259 msg->status = as->done_status;
1260 spi_finalize_current_message(spi->master);
1261
1262 return ret;
1454} 1263}
1455 1264
1456static void atmel_spi_cleanup(struct spi_device *spi) 1265static void atmel_spi_cleanup(struct spi_device *spi)
1457{ 1266{
1458 struct atmel_spi *as = spi_master_get_devdata(spi->master);
1459 struct atmel_spi_device *asd = spi->controller_state; 1267 struct atmel_spi_device *asd = spi->controller_state;
1460 unsigned gpio = (unsigned) spi->controller_data; 1268 unsigned gpio = (unsigned) spi->controller_data;
1461 1269
1462 if (!asd) 1270 if (!asd)
1463 return; 1271 return;
1464 1272
1465 atmel_spi_lock(as);
1466 if (as->stay == spi) {
1467 as->stay = NULL;
1468 cs_deactivate(as, spi);
1469 }
1470 atmel_spi_unlock(as);
1471
1472 spi->controller_state = NULL; 1273 spi->controller_state = NULL;
1473 gpio_free(gpio); 1274 gpio_free(gpio);
1474 kfree(asd); 1275 kfree(asd);
@@ -1510,7 +1311,7 @@ static int atmel_spi_probe(struct platform_device *pdev)
1510 if (irq < 0) 1311 if (irq < 0)
1511 return irq; 1312 return irq;
1512 1313
1513 clk = clk_get(&pdev->dev, "spi_clk"); 1314 clk = devm_clk_get(&pdev->dev, "spi_clk");
1514 if (IS_ERR(clk)) 1315 if (IS_ERR(clk))
1515 return PTR_ERR(clk); 1316 return PTR_ERR(clk);
1516 1317
@@ -1527,7 +1328,7 @@ static int atmel_spi_probe(struct platform_device *pdev)
1527 master->bus_num = pdev->id; 1328 master->bus_num = pdev->id;
1528 master->num_chipselect = master->dev.of_node ? 0 : 4; 1329 master->num_chipselect = master->dev.of_node ? 0 : 4;
1529 master->setup = atmel_spi_setup; 1330 master->setup = atmel_spi_setup;
1530 master->transfer = atmel_spi_transfer; 1331 master->transfer_one_message = atmel_spi_transfer_one_message;
1531 master->cleanup = atmel_spi_cleanup; 1332 master->cleanup = atmel_spi_cleanup;
1532 platform_set_drvdata(pdev, master); 1333 platform_set_drvdata(pdev, master);
1533 1334
@@ -1543,7 +1344,6 @@ static int atmel_spi_probe(struct platform_device *pdev)
1543 goto out_free; 1344 goto out_free;
1544 1345
1545 spin_lock_init(&as->lock); 1346 spin_lock_init(&as->lock);
1546 INIT_LIST_HEAD(&as->queue);
1547 1347
1548 as->pdev = pdev; 1348 as->pdev = pdev;
1549 as->regs = devm_ioremap_resource(&pdev->dev, regs); 1349 as->regs = devm_ioremap_resource(&pdev->dev, regs);
@@ -1555,6 +1355,8 @@ static int atmel_spi_probe(struct platform_device *pdev)
1555 as->irq = irq; 1355 as->irq = irq;
1556 as->clk = clk; 1356 as->clk = clk;
1557 1357
1358 init_completion(&as->xfer_completion);
1359
1558 atmel_get_caps(as); 1360 atmel_get_caps(as);
1559 1361
1560 as->use_dma = false; 1362 as->use_dma = false;
@@ -1570,14 +1372,11 @@ static int atmel_spi_probe(struct platform_device *pdev)
1570 dev_info(&pdev->dev, "Atmel SPI Controller using PIO only\n"); 1372 dev_info(&pdev->dev, "Atmel SPI Controller using PIO only\n");
1571 1373
1572 if (as->use_pdc) { 1374 if (as->use_pdc) {
1573 ret = request_irq(irq, atmel_spi_pdc_interrupt, 0, 1375 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pdc_interrupt,
1574 dev_name(&pdev->dev), master); 1376 0, dev_name(&pdev->dev), master);
1575 } else { 1377 } else {
1576 tasklet_init(&as->tasklet, atmel_spi_tasklet_func, 1378 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pio_interrupt,
1577 (unsigned long)master); 1379 0, dev_name(&pdev->dev), master);
1578
1579 ret = request_irq(irq, atmel_spi_pio_interrupt, 0,
1580 dev_name(&pdev->dev), master);
1581 } 1380 }
1582 if (ret) 1381 if (ret)
1583 goto out_unmap_regs; 1382 goto out_unmap_regs;
@@ -1603,7 +1402,7 @@ static int atmel_spi_probe(struct platform_device *pdev)
1603 dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n", 1402 dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n",
1604 (unsigned long)regs->start, irq); 1403 (unsigned long)regs->start, irq);
1605 1404
1606 ret = spi_register_master(master); 1405 ret = devm_spi_register_master(&pdev->dev, master);
1607 if (ret) 1406 if (ret)
1608 goto out_free_dma; 1407 goto out_free_dma;
1609 1408
@@ -1617,15 +1416,11 @@ out_free_dma:
1617 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */ 1416 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1618 clk_disable_unprepare(clk); 1417 clk_disable_unprepare(clk);
1619out_free_irq: 1418out_free_irq:
1620 free_irq(irq, master);
1621out_unmap_regs: 1419out_unmap_regs:
1622out_free_buffer: 1420out_free_buffer:
1623 if (!as->use_pdc)
1624 tasklet_kill(&as->tasklet);
1625 dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer, 1421 dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
1626 as->buffer_dma); 1422 as->buffer_dma);
1627out_free: 1423out_free:
1628 clk_put(clk);
1629 spi_master_put(master); 1424 spi_master_put(master);
1630 return ret; 1425 return ret;
1631} 1426}
@@ -1634,12 +1429,9 @@ static int atmel_spi_remove(struct platform_device *pdev)
1634{ 1429{
1635 struct spi_master *master = platform_get_drvdata(pdev); 1430 struct spi_master *master = platform_get_drvdata(pdev);
1636 struct atmel_spi *as = spi_master_get_devdata(master); 1431 struct atmel_spi *as = spi_master_get_devdata(master);
1637 struct spi_message *msg;
1638 struct spi_transfer *xfer;
1639 1432
1640 /* reset the hardware and block queue progress */ 1433 /* reset the hardware and block queue progress */
1641 spin_lock_irq(&as->lock); 1434 spin_lock_irq(&as->lock);
1642 as->stopping = 1;
1643 if (as->use_dma) { 1435 if (as->use_dma) {
1644 atmel_spi_stop_dma(as); 1436 atmel_spi_stop_dma(as);
1645 atmel_spi_release_dma(as); 1437 atmel_spi_release_dma(as);
@@ -1650,28 +1442,10 @@ static int atmel_spi_remove(struct platform_device *pdev)
1650 spi_readl(as, SR); 1442 spi_readl(as, SR);
1651 spin_unlock_irq(&as->lock); 1443 spin_unlock_irq(&as->lock);
1652 1444
1653 /* Terminate remaining queued transfers */
1654 list_for_each_entry(msg, &as->queue, queue) {
1655 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1656 if (!msg->is_dma_mapped
1657 && (atmel_spi_use_dma(as, xfer)
1658 || as->use_pdc))
1659 atmel_spi_dma_unmap_xfer(master, xfer);
1660 }
1661 msg->status = -ESHUTDOWN;
1662 msg->complete(msg->context);
1663 }
1664
1665 if (!as->use_pdc)
1666 tasklet_kill(&as->tasklet);
1667 dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer, 1445 dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
1668 as->buffer_dma); 1446 as->buffer_dma);
1669 1447
1670 clk_disable_unprepare(as->clk); 1448 clk_disable_unprepare(as->clk);
1671 clk_put(as->clk);
1672 free_irq(as->irq, master);
1673
1674 spi_unregister_master(master);
1675 1449
1676 return 0; 1450 return 0;
1677} 1451}
diff --git a/drivers/spi/spi-bcm2835.c b/drivers/spi/spi-bcm2835.c
index 9025edd7dc45..8a89dd1f2654 100644
--- a/drivers/spi/spi-bcm2835.c
+++ b/drivers/spi/spi-bcm2835.c
@@ -347,8 +347,8 @@ static int bcm2835_spi_probe(struct platform_device *pdev)
347 347
348 clk_prepare_enable(bs->clk); 348 clk_prepare_enable(bs->clk);
349 349
350 err = request_irq(bs->irq, bcm2835_spi_interrupt, 0, 350 err = devm_request_irq(&pdev->dev, bs->irq, bcm2835_spi_interrupt, 0,
351 dev_name(&pdev->dev), master); 351 dev_name(&pdev->dev), master);
352 if (err) { 352 if (err) {
353 dev_err(&pdev->dev, "could not request IRQ: %d\n", err); 353 dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
354 goto out_clk_disable; 354 goto out_clk_disable;
@@ -361,13 +361,11 @@ static int bcm2835_spi_probe(struct platform_device *pdev)
361 err = devm_spi_register_master(&pdev->dev, master); 361 err = devm_spi_register_master(&pdev->dev, master);
362 if (err) { 362 if (err) {
363 dev_err(&pdev->dev, "could not register SPI master: %d\n", err); 363 dev_err(&pdev->dev, "could not register SPI master: %d\n", err);
364 goto out_free_irq; 364 goto out_clk_disable;
365 } 365 }
366 366
367 return 0; 367 return 0;
368 368
369out_free_irq:
370 free_irq(bs->irq, master);
371out_clk_disable: 369out_clk_disable:
372 clk_disable_unprepare(bs->clk); 370 clk_disable_unprepare(bs->clk);
373out_master_put: 371out_master_put:
@@ -380,8 +378,6 @@ static int bcm2835_spi_remove(struct platform_device *pdev)
380 struct spi_master *master = platform_get_drvdata(pdev); 378 struct spi_master *master = platform_get_drvdata(pdev);
381 struct bcm2835_spi *bs = spi_master_get_devdata(master); 379 struct bcm2835_spi *bs = spi_master_get_devdata(master);
382 380
383 free_irq(bs->irq, master);
384
385 /* Clear FIFOs, and disable the HW block */ 381 /* Clear FIFOs, and disable the HW block */
386 bcm2835_wr(bs, BCM2835_SPI_CS, 382 bcm2835_wr(bs, BCM2835_SPI_CS,
387 BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX); 383 BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);
diff --git a/drivers/spi/spi-bcm63xx-hsspi.c b/drivers/spi/spi-bcm63xx-hsspi.c
new file mode 100644
index 000000000000..b528f9fc8bc0
--- /dev/null
+++ b/drivers/spi/spi-bcm63xx-hsspi.c
@@ -0,0 +1,475 @@
1/*
2 * Broadcom BCM63XX High Speed SPI Controller driver
3 *
4 * Copyright 2000-2010 Broadcom Corporation
5 * Copyright 2012-2013 Jonas Gorski <jogo@openwrt.org>
6 *
7 * Licensed under the GNU/GPL. See COPYING for details.
8 */
9
10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/io.h>
13#include <linux/clk.h>
14#include <linux/module.h>
15#include <linux/platform_device.h>
16#include <linux/delay.h>
17#include <linux/dma-mapping.h>
18#include <linux/err.h>
19#include <linux/interrupt.h>
20#include <linux/spi/spi.h>
21#include <linux/workqueue.h>
22#include <linux/mutex.h>
23
24#define HSSPI_GLOBAL_CTRL_REG 0x0
25#define GLOBAL_CTRL_CS_POLARITY_SHIFT 0
26#define GLOBAL_CTRL_CS_POLARITY_MASK 0x000000ff
27#define GLOBAL_CTRL_PLL_CLK_CTRL_SHIFT 8
28#define GLOBAL_CTRL_PLL_CLK_CTRL_MASK 0x0000ff00
29#define GLOBAL_CTRL_CLK_GATE_SSOFF BIT(16)
30#define GLOBAL_CTRL_CLK_POLARITY BIT(17)
31#define GLOBAL_CTRL_MOSI_IDLE BIT(18)
32
33#define HSSPI_GLOBAL_EXT_TRIGGER_REG 0x4
34
35#define HSSPI_INT_STATUS_REG 0x8
36#define HSSPI_INT_STATUS_MASKED_REG 0xc
37#define HSSPI_INT_MASK_REG 0x10
38
39#define HSSPI_PINGx_CMD_DONE(i) BIT((i * 8) + 0)
40#define HSSPI_PINGx_RX_OVER(i) BIT((i * 8) + 1)
41#define HSSPI_PINGx_TX_UNDER(i) BIT((i * 8) + 2)
42#define HSSPI_PINGx_POLL_TIMEOUT(i) BIT((i * 8) + 3)
43#define HSSPI_PINGx_CTRL_INVAL(i) BIT((i * 8) + 4)
44
45#define HSSPI_INT_CLEAR_ALL 0xff001f1f
46
47#define HSSPI_PINGPONG_COMMAND_REG(x) (0x80 + (x) * 0x40)
48#define PINGPONG_CMD_COMMAND_MASK 0xf
49#define PINGPONG_COMMAND_NOOP 0
50#define PINGPONG_COMMAND_START_NOW 1
51#define PINGPONG_COMMAND_START_TRIGGER 2
52#define PINGPONG_COMMAND_HALT 3
53#define PINGPONG_COMMAND_FLUSH 4
54#define PINGPONG_CMD_PROFILE_SHIFT 8
55#define PINGPONG_CMD_SS_SHIFT 12
56
57#define HSSPI_PINGPONG_STATUS_REG(x) (0x84 + (x) * 0x40)
58
59#define HSSPI_PROFILE_CLK_CTRL_REG(x) (0x100 + (x) * 0x20)
60#define CLK_CTRL_FREQ_CTRL_MASK 0x0000ffff
61#define CLK_CTRL_SPI_CLK_2X_SEL BIT(14)
62#define CLK_CTRL_ACCUM_RST_ON_LOOP BIT(15)
63
64#define HSSPI_PROFILE_SIGNAL_CTRL_REG(x) (0x104 + (x) * 0x20)
65#define SIGNAL_CTRL_LATCH_RISING BIT(12)
66#define SIGNAL_CTRL_LAUNCH_RISING BIT(13)
67#define SIGNAL_CTRL_ASYNC_INPUT_PATH BIT(16)
68
69#define HSSPI_PROFILE_MODE_CTRL_REG(x) (0x108 + (x) * 0x20)
70#define MODE_CTRL_MULTIDATA_RD_STRT_SHIFT 8
71#define MODE_CTRL_MULTIDATA_WR_STRT_SHIFT 12
72#define MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT 16
73#define MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT 18
74#define MODE_CTRL_MODE_3WIRE BIT(20)
75#define MODE_CTRL_PREPENDBYTE_CNT_SHIFT 24
76
77#define HSSPI_FIFO_REG(x) (0x200 + (x) * 0x200)
78
79
80#define HSSPI_OP_CODE_SHIFT 13
81#define HSSPI_OP_SLEEP (0 << HSSPI_OP_CODE_SHIFT)
82#define HSSPI_OP_READ_WRITE (1 << HSSPI_OP_CODE_SHIFT)
83#define HSSPI_OP_WRITE (2 << HSSPI_OP_CODE_SHIFT)
84#define HSSPI_OP_READ (3 << HSSPI_OP_CODE_SHIFT)
85#define HSSPI_OP_SETIRQ (4 << HSSPI_OP_CODE_SHIFT)
86
87#define HSSPI_BUFFER_LEN 512
88#define HSSPI_OPCODE_LEN 2
89
90#define HSSPI_MAX_PREPEND_LEN 15
91
92#define HSSPI_MAX_SYNC_CLOCK 30000000
93
94#define HSSPI_BUS_NUM 1 /* 0 is legacy SPI */
95
96struct bcm63xx_hsspi {
97 struct completion done;
98 struct mutex bus_mutex;
99
100 struct platform_device *pdev;
101 struct clk *clk;
102 void __iomem *regs;
103 u8 __iomem *fifo;
104
105 u32 speed_hz;
106 u8 cs_polarity;
107};
108
109static void bcm63xx_hsspi_set_cs(struct bcm63xx_hsspi *bs, unsigned cs,
110 bool active)
111{
112 u32 reg;
113
114 mutex_lock(&bs->bus_mutex);
115 reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
116
117 reg &= ~BIT(cs);
118 if (active == !(bs->cs_polarity & BIT(cs)))
119 reg |= BIT(cs);
120
121 __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
122 mutex_unlock(&bs->bus_mutex);
123}
124
125static void bcm63xx_hsspi_set_clk(struct bcm63xx_hsspi *bs,
126 struct spi_device *spi, int hz)
127{
128 unsigned profile = spi->chip_select;
129 u32 reg;
130
131 reg = DIV_ROUND_UP(2048, DIV_ROUND_UP(bs->speed_hz, hz));
132 __raw_writel(CLK_CTRL_ACCUM_RST_ON_LOOP | reg,
133 bs->regs + HSSPI_PROFILE_CLK_CTRL_REG(profile));
134
135 reg = __raw_readl(bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
136 if (hz > HSSPI_MAX_SYNC_CLOCK)
137 reg |= SIGNAL_CTRL_ASYNC_INPUT_PATH;
138 else
139 reg &= ~SIGNAL_CTRL_ASYNC_INPUT_PATH;
140 __raw_writel(reg, bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
141
142 mutex_lock(&bs->bus_mutex);
143 /* setup clock polarity */
144 reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
145 reg &= ~GLOBAL_CTRL_CLK_POLARITY;
146 if (spi->mode & SPI_CPOL)
147 reg |= GLOBAL_CTRL_CLK_POLARITY;
148 __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
149 mutex_unlock(&bs->bus_mutex);
150}
151
152static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t)
153{
154 struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
155 unsigned chip_select = spi->chip_select;
156 u16 opcode = 0;
157 int pending = t->len;
158 int step_size = HSSPI_BUFFER_LEN;
159 const u8 *tx = t->tx_buf;
160 u8 *rx = t->rx_buf;
161
162 bcm63xx_hsspi_set_clk(bs, spi, t->speed_hz);
163 bcm63xx_hsspi_set_cs(bs, spi->chip_select, true);
164
165 if (tx && rx)
166 opcode = HSSPI_OP_READ_WRITE;
167 else if (tx)
168 opcode = HSSPI_OP_WRITE;
169 else if (rx)
170 opcode = HSSPI_OP_READ;
171
172 if (opcode != HSSPI_OP_READ)
173 step_size -= HSSPI_OPCODE_LEN;
174
175 __raw_writel(0 << MODE_CTRL_PREPENDBYTE_CNT_SHIFT |
176 2 << MODE_CTRL_MULTIDATA_WR_STRT_SHIFT |
177 2 << MODE_CTRL_MULTIDATA_RD_STRT_SHIFT | 0xff,
178 bs->regs + HSSPI_PROFILE_MODE_CTRL_REG(chip_select));
179
180 while (pending > 0) {
181 int curr_step = min_t(int, step_size, pending);
182
183 init_completion(&bs->done);
184 if (tx) {
185 memcpy_toio(bs->fifo + HSSPI_OPCODE_LEN, tx, curr_step);
186 tx += curr_step;
187 }
188
189 __raw_writew(opcode | curr_step, bs->fifo);
190
191 /* enable interrupt */
192 __raw_writel(HSSPI_PINGx_CMD_DONE(0),
193 bs->regs + HSSPI_INT_MASK_REG);
194
195 /* start the transfer */
196 __raw_writel(!chip_select << PINGPONG_CMD_SS_SHIFT |
197 chip_select << PINGPONG_CMD_PROFILE_SHIFT |
198 PINGPONG_COMMAND_START_NOW,
199 bs->regs + HSSPI_PINGPONG_COMMAND_REG(0));
200
201 if (wait_for_completion_timeout(&bs->done, HZ) == 0) {
202 dev_err(&bs->pdev->dev, "transfer timed out!\n");
203 return -ETIMEDOUT;
204 }
205
206 if (rx) {
207 memcpy_fromio(rx, bs->fifo, curr_step);
208 rx += curr_step;
209 }
210
211 pending -= curr_step;
212 }
213
214 return 0;
215}
216
217static int bcm63xx_hsspi_setup(struct spi_device *spi)
218{
219 struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
220 u32 reg;
221
222 reg = __raw_readl(bs->regs +
223 HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
224 reg &= ~(SIGNAL_CTRL_LAUNCH_RISING | SIGNAL_CTRL_LATCH_RISING);
225 if (spi->mode & SPI_CPHA)
226 reg |= SIGNAL_CTRL_LAUNCH_RISING;
227 else
228 reg |= SIGNAL_CTRL_LATCH_RISING;
229 __raw_writel(reg, bs->regs +
230 HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
231
232 mutex_lock(&bs->bus_mutex);
233 reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
234
235 /* only change actual polarities if there is no transfer */
236 if ((reg & GLOBAL_CTRL_CS_POLARITY_MASK) == bs->cs_polarity) {
237 if (spi->mode & SPI_CS_HIGH)
238 reg |= BIT(spi->chip_select);
239 else
240 reg &= ~BIT(spi->chip_select);
241 __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
242 }
243
244 if (spi->mode & SPI_CS_HIGH)
245 bs->cs_polarity |= BIT(spi->chip_select);
246 else
247 bs->cs_polarity &= ~BIT(spi->chip_select);
248
249 mutex_unlock(&bs->bus_mutex);
250
251 return 0;
252}
253
254static int bcm63xx_hsspi_transfer_one(struct spi_master *master,
255 struct spi_message *msg)
256{
257 struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
258 struct spi_transfer *t;
259 struct spi_device *spi = msg->spi;
260 int status = -EINVAL;
261 int dummy_cs;
262 u32 reg;
263
264 /* This controller does not support keeping CS active during idle.
265 * To work around this, we use the following ugly hack:
266 *
267 * a. Invert the target chip select's polarity so it will be active.
268 * b. Select a "dummy" chip select to use as the hardware target.
269 * c. Invert the dummy chip select's polarity so it will be inactive
270 * during the actual transfers.
271 * d. Tell the hardware to send to the dummy chip select. Thanks to
272 * the multiplexed nature of SPI the actual target will receive
273 * the transfer and we see its response.
274 *
275 * e. At the end restore the polarities again to their default values.
276 */
277
278 dummy_cs = !spi->chip_select;
279 bcm63xx_hsspi_set_cs(bs, dummy_cs, true);
280
281 list_for_each_entry(t, &msg->transfers, transfer_list) {
282 status = bcm63xx_hsspi_do_txrx(spi, t);
283 if (status)
284 break;
285
286 msg->actual_length += t->len;
287
288 if (t->delay_usecs)
289 udelay(t->delay_usecs);
290
291 if (t->cs_change)
292 bcm63xx_hsspi_set_cs(bs, spi->chip_select, false);
293 }
294
295 mutex_lock(&bs->bus_mutex);
296 reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
297 reg &= ~GLOBAL_CTRL_CS_POLARITY_MASK;
298 reg |= bs->cs_polarity;
299 __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
300 mutex_unlock(&bs->bus_mutex);
301
302 msg->status = status;
303 spi_finalize_current_message(master);
304
305 return 0;
306}
307
308static irqreturn_t bcm63xx_hsspi_interrupt(int irq, void *dev_id)
309{
310 struct bcm63xx_hsspi *bs = (struct bcm63xx_hsspi *)dev_id;
311
312 if (__raw_readl(bs->regs + HSSPI_INT_STATUS_MASKED_REG) == 0)
313 return IRQ_NONE;
314
315 __raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);
316 __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
317
318 complete(&bs->done);
319
320 return IRQ_HANDLED;
321}
322
323static int bcm63xx_hsspi_probe(struct platform_device *pdev)
324{
325 struct spi_master *master;
326 struct bcm63xx_hsspi *bs;
327 struct resource *res_mem;
328 void __iomem *regs;
329 struct device *dev = &pdev->dev;
330 struct clk *clk;
331 int irq, ret;
332 u32 reg, rate;
333
334 irq = platform_get_irq(pdev, 0);
335 if (irq < 0) {
336 dev_err(dev, "no irq\n");
337 return -ENXIO;
338 }
339
340 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
341 regs = devm_ioremap_resource(dev, res_mem);
342 if (IS_ERR(regs))
343 return PTR_ERR(regs);
344
345 clk = devm_clk_get(dev, "hsspi");
346
347 if (IS_ERR(clk))
348 return PTR_ERR(clk);
349
350 rate = clk_get_rate(clk);
351 if (!rate)
352 return -EINVAL;
353
354 ret = clk_prepare_enable(clk);
355 if (ret)
356 return ret;
357
358 master = spi_alloc_master(&pdev->dev, sizeof(*bs));
359 if (!master) {
360 ret = -ENOMEM;
361 goto out_disable_clk;
362 }
363
364 bs = spi_master_get_devdata(master);
365 bs->pdev = pdev;
366 bs->clk = clk;
367 bs->regs = regs;
368 bs->speed_hz = rate;
369 bs->fifo = (u8 __iomem *)(bs->regs + HSSPI_FIFO_REG(0));
370
371 mutex_init(&bs->bus_mutex);
372
373 master->bus_num = HSSPI_BUS_NUM;
374 master->num_chipselect = 8;
375 master->setup = bcm63xx_hsspi_setup;
376 master->transfer_one_message = bcm63xx_hsspi_transfer_one;
377 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
378 master->bits_per_word_mask = SPI_BPW_MASK(8);
379 master->auto_runtime_pm = true;
380
381 platform_set_drvdata(pdev, master);
382
383 /* Initialize the hardware */
384 __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
385
386 /* clean up any pending interrupts */
387 __raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);
388
389 /* read out default CS polarities */
390 reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
391 bs->cs_polarity = reg & GLOBAL_CTRL_CS_POLARITY_MASK;
392 __raw_writel(reg | GLOBAL_CTRL_CLK_GATE_SSOFF,
393 bs->regs + HSSPI_GLOBAL_CTRL_REG);
394
395 ret = devm_request_irq(dev, irq, bcm63xx_hsspi_interrupt, IRQF_SHARED,
396 pdev->name, bs);
397
398 if (ret)
399 goto out_put_master;
400
401 /* register and we are done */
402 ret = devm_spi_register_master(dev, master);
403 if (ret)
404 goto out_put_master;
405
406 return 0;
407
408out_put_master:
409 spi_master_put(master);
410out_disable_clk:
411 clk_disable_unprepare(clk);
412 return ret;
413}
414
415
416static int bcm63xx_hsspi_remove(struct platform_device *pdev)
417{
418 struct spi_master *master = platform_get_drvdata(pdev);
419 struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
420
421 /* reset the hardware and block queue progress */
422 __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
423 clk_disable_unprepare(bs->clk);
424
425 return 0;
426}
427
428#ifdef CONFIG_PM_SLEEP
429static int bcm63xx_hsspi_suspend(struct device *dev)
430{
431 struct spi_master *master = dev_get_drvdata(dev);
432 struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
433
434 spi_master_suspend(master);
435 clk_disable_unprepare(bs->clk);
436
437 return 0;
438}
439
440static int bcm63xx_hsspi_resume(struct device *dev)
441{
442 struct spi_master *master = dev_get_drvdata(dev);
443 struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
444 int ret;
445
446 ret = clk_prepare_enable(bs->clk);
447 if (ret)
448 return ret;
449
450 spi_master_resume(master);
451
452 return 0;
453}
454#endif
455
456static const struct dev_pm_ops bcm63xx_hsspi_pm_ops = {
457 SET_SYSTEM_SLEEP_PM_OPS(bcm63xx_hsspi_suspend, bcm63xx_hsspi_resume)
458};
459
460static struct platform_driver bcm63xx_hsspi_driver = {
461 .driver = {
462 .name = "bcm63xx-hsspi",
463 .owner = THIS_MODULE,
464 .pm = &bcm63xx_hsspi_pm_ops,
465 },
466 .probe = bcm63xx_hsspi_probe,
467 .remove = bcm63xx_hsspi_remove,
468};
469
470module_platform_driver(bcm63xx_hsspi_driver);
471
472MODULE_ALIAS("platform:bcm63xx_hsspi");
473MODULE_DESCRIPTION("Broadcom BCM63xx High Speed SPI Controller driver");
474MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
475MODULE_LICENSE("GPL");
diff --git a/drivers/spi/spi-bcm63xx.c b/drivers/spi/spi-bcm63xx.c
index 469ecd876358..77286aef2adf 100644
--- a/drivers/spi/spi-bcm63xx.c
+++ b/drivers/spi/spi-bcm63xx.c
@@ -169,8 +169,6 @@ static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *first,
169 transfer_list); 169 transfer_list);
170 } 170 }
171 171
172 len -= prepend_len;
173
174 init_completion(&bs->done); 172 init_completion(&bs->done);
175 173
176 /* Fill in the Message control register */ 174 /* Fill in the Message control register */
@@ -205,13 +203,7 @@ static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *first,
205 if (!timeout) 203 if (!timeout)
206 return -ETIMEDOUT; 204 return -ETIMEDOUT;
207 205
208 /* read out all data */ 206 if (!do_rx)
209 rx_tail = bcm_spi_readb(bs, SPI_RX_TAIL);
210
211 if (do_rx && rx_tail != len)
212 return -EIO;
213
214 if (!rx_tail)
215 return 0; 207 return 0;
216 208
217 len = 0; 209 len = 0;
@@ -345,22 +337,19 @@ static int bcm63xx_spi_probe(struct platform_device *pdev)
345 irq = platform_get_irq(pdev, 0); 337 irq = platform_get_irq(pdev, 0);
346 if (irq < 0) { 338 if (irq < 0) {
347 dev_err(dev, "no irq\n"); 339 dev_err(dev, "no irq\n");
348 ret = -ENXIO; 340 return -ENXIO;
349 goto out;
350 } 341 }
351 342
352 clk = clk_get(dev, "spi"); 343 clk = devm_clk_get(dev, "spi");
353 if (IS_ERR(clk)) { 344 if (IS_ERR(clk)) {
354 dev_err(dev, "no clock for device\n"); 345 dev_err(dev, "no clock for device\n");
355 ret = PTR_ERR(clk); 346 return PTR_ERR(clk);
356 goto out;
357 } 347 }
358 348
359 master = spi_alloc_master(dev, sizeof(*bs)); 349 master = spi_alloc_master(dev, sizeof(*bs));
360 if (!master) { 350 if (!master) {
361 dev_err(dev, "out of memory\n"); 351 dev_err(dev, "out of memory\n");
362 ret = -ENOMEM; 352 return -ENOMEM;
363 goto out_clk;
364 } 353 }
365 354
366 bs = spi_master_get_devdata(master); 355 bs = spi_master_get_devdata(master);
@@ -408,7 +397,10 @@ static int bcm63xx_spi_probe(struct platform_device *pdev)
408 } 397 }
409 398
410 /* Initialize hardware */ 399 /* Initialize hardware */
411 clk_prepare_enable(bs->clk); 400 ret = clk_prepare_enable(bs->clk);
401 if (ret)
402 goto out_err;
403
412 bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS); 404 bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
413 405
414 /* register and we are done */ 406 /* register and we are done */
@@ -427,9 +419,6 @@ out_clk_disable:
427 clk_disable_unprepare(clk); 419 clk_disable_unprepare(clk);
428out_err: 420out_err:
429 spi_master_put(master); 421 spi_master_put(master);
430out_clk:
431 clk_put(clk);
432out:
433 return ret; 422 return ret;
434} 423}
435 424
@@ -443,12 +432,11 @@ static int bcm63xx_spi_remove(struct platform_device *pdev)
443 432
444 /* HW shutdown */ 433 /* HW shutdown */
445 clk_disable_unprepare(bs->clk); 434 clk_disable_unprepare(bs->clk);
446 clk_put(bs->clk);
447 435
448 return 0; 436 return 0;
449} 437}
450 438
451#ifdef CONFIG_PM 439#ifdef CONFIG_PM_SLEEP
452static int bcm63xx_spi_suspend(struct device *dev) 440static int bcm63xx_spi_suspend(struct device *dev)
453{ 441{
454 struct spi_master *master = dev_get_drvdata(dev); 442 struct spi_master *master = dev_get_drvdata(dev);
@@ -465,29 +453,27 @@ static int bcm63xx_spi_resume(struct device *dev)
465{ 453{
466 struct spi_master *master = dev_get_drvdata(dev); 454 struct spi_master *master = dev_get_drvdata(dev);
467 struct bcm63xx_spi *bs = spi_master_get_devdata(master); 455 struct bcm63xx_spi *bs = spi_master_get_devdata(master);
456 int ret;
468 457
469 clk_prepare_enable(bs->clk); 458 ret = clk_prepare_enable(bs->clk);
459 if (ret)
460 return ret;
470 461
471 spi_master_resume(master); 462 spi_master_resume(master);
472 463
473 return 0; 464 return 0;
474} 465}
466#endif
475 467
476static const struct dev_pm_ops bcm63xx_spi_pm_ops = { 468static const struct dev_pm_ops bcm63xx_spi_pm_ops = {
477 .suspend = bcm63xx_spi_suspend, 469 SET_SYSTEM_SLEEP_PM_OPS(bcm63xx_spi_suspend, bcm63xx_spi_resume)
478 .resume = bcm63xx_spi_resume,
479}; 470};
480 471
481#define BCM63XX_SPI_PM_OPS (&bcm63xx_spi_pm_ops)
482#else
483#define BCM63XX_SPI_PM_OPS NULL
484#endif
485
486static struct platform_driver bcm63xx_spi_driver = { 472static struct platform_driver bcm63xx_spi_driver = {
487 .driver = { 473 .driver = {
488 .name = "bcm63xx-spi", 474 .name = "bcm63xx-spi",
489 .owner = THIS_MODULE, 475 .owner = THIS_MODULE,
490 .pm = BCM63XX_SPI_PM_OPS, 476 .pm = &bcm63xx_spi_pm_ops,
491 }, 477 },
492 .probe = bcm63xx_spi_probe, 478 .probe = bcm63xx_spi_probe,
493 .remove = bcm63xx_spi_remove, 479 .remove = bcm63xx_spi_remove,
diff --git a/drivers/spi/spi-bitbang-txrx.h b/drivers/spi/spi-bitbang-txrx.h
index c16bf853c3eb..c616e41521be 100644
--- a/drivers/spi/spi-bitbang-txrx.h
+++ b/drivers/spi/spi-bitbang-txrx.h
@@ -38,7 +38,7 @@
38 * 38 *
39 * Since this is software, the timings may not be exactly what your board's 39 * Since this is software, the timings may not be exactly what your board's
40 * chips need ... there may be several reasons you'd need to tweak timings 40 * chips need ... there may be several reasons you'd need to tweak timings
41 * in these routines, not just make to make it faster or slower to match a 41 * in these routines, not just to make it faster or slower to match a
42 * particular CPU clock rate. 42 * particular CPU clock rate.
43 */ 43 */
44 44
diff --git a/drivers/spi/spi-clps711x.c b/drivers/spi/spi-clps711x.c
index 6f03d7e6435d..374ba4a48a9e 100644
--- a/drivers/spi/spi-clps711x.c
+++ b/drivers/spi/spi-clps711x.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * CLPS711X SPI bus driver 2 * CLPS711X SPI bus driver
3 * 3 *
4 * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru> 4 * Copyright (C) 2012-2014 Alexander Shiyan <shc_work@mail.ru>
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by 7 * it under the terms of the GNU General Public License as published by
@@ -198,7 +198,7 @@ static int spi_clps711x_probe(struct platform_device *pdev)
198 ret = -EINVAL; 198 ret = -EINVAL;
199 goto err_out; 199 goto err_out;
200 } 200 }
201 if (gpio_request(hw->chipselect[i], DRIVER_NAME)) { 201 if (devm_gpio_request(&pdev->dev, hw->chipselect[i], NULL)) {
202 dev_err(&pdev->dev, "Can't get CS GPIO %i\n", i); 202 dev_err(&pdev->dev, "Can't get CS GPIO %i\n", i);
203 ret = -EINVAL; 203 ret = -EINVAL;
204 goto err_out; 204 goto err_out;
@@ -240,38 +240,21 @@ static int spi_clps711x_probe(struct platform_device *pdev)
240 dev_err(&pdev->dev, "Failed to register master\n"); 240 dev_err(&pdev->dev, "Failed to register master\n");
241 241
242err_out: 242err_out:
243 while (--i >= 0)
244 if (gpio_is_valid(hw->chipselect[i]))
245 gpio_free(hw->chipselect[i]);
246
247 spi_master_put(master); 243 spi_master_put(master);
248 244
249 return ret; 245 return ret;
250} 246}
251 247
252static int spi_clps711x_remove(struct platform_device *pdev)
253{
254 int i;
255 struct spi_master *master = platform_get_drvdata(pdev);
256 struct spi_clps711x_data *hw = spi_master_get_devdata(master);
257
258 for (i = 0; i < master->num_chipselect; i++)
259 if (gpio_is_valid(hw->chipselect[i]))
260 gpio_free(hw->chipselect[i]);
261
262 return 0;
263}
264
265static struct platform_driver clps711x_spi_driver = { 248static struct platform_driver clps711x_spi_driver = {
266 .driver = { 249 .driver = {
267 .name = DRIVER_NAME, 250 .name = DRIVER_NAME,
268 .owner = THIS_MODULE, 251 .owner = THIS_MODULE,
269 }, 252 },
270 .probe = spi_clps711x_probe, 253 .probe = spi_clps711x_probe,
271 .remove = spi_clps711x_remove,
272}; 254};
273module_platform_driver(clps711x_spi_driver); 255module_platform_driver(clps711x_spi_driver);
274 256
275MODULE_LICENSE("GPL"); 257MODULE_LICENSE("GPL");
276MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>"); 258MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
277MODULE_DESCRIPTION("CLPS711X SPI bus driver"); 259MODULE_DESCRIPTION("CLPS711X SPI bus driver");
260MODULE_ALIAS("platform:" DRIVER_NAME);
diff --git a/drivers/spi/spi-coldfire-qspi.c b/drivers/spi/spi-coldfire-qspi.c
index cc5b75d10c38..cabed8f9119e 100644
--- a/drivers/spi/spi-coldfire-qspi.c
+++ b/drivers/spi/spi-coldfire-qspi.c
@@ -397,44 +397,31 @@ static int mcfqspi_probe(struct platform_device *pdev)
397 mcfqspi = spi_master_get_devdata(master); 397 mcfqspi = spi_master_get_devdata(master);
398 398
399 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 399 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
400 if (!res) { 400 mcfqspi->iobase = devm_ioremap_resource(&pdev->dev, res);
401 dev_dbg(&pdev->dev, "platform_get_resource failed\n"); 401 if (IS_ERR(mcfqspi->iobase)) {
402 status = -ENXIO; 402 status = PTR_ERR(mcfqspi->iobase);
403 goto fail0; 403 goto fail0;
404 } 404 }
405 405
406 if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
407 dev_dbg(&pdev->dev, "request_mem_region failed\n");
408 status = -EBUSY;
409 goto fail0;
410 }
411
412 mcfqspi->iobase = ioremap(res->start, resource_size(res));
413 if (!mcfqspi->iobase) {
414 dev_dbg(&pdev->dev, "ioremap failed\n");
415 status = -ENOMEM;
416 goto fail1;
417 }
418
419 mcfqspi->irq = platform_get_irq(pdev, 0); 406 mcfqspi->irq = platform_get_irq(pdev, 0);
420 if (mcfqspi->irq < 0) { 407 if (mcfqspi->irq < 0) {
421 dev_dbg(&pdev->dev, "platform_get_irq failed\n"); 408 dev_dbg(&pdev->dev, "platform_get_irq failed\n");
422 status = -ENXIO; 409 status = -ENXIO;
423 goto fail2; 410 goto fail0;
424 } 411 }
425 412
426 status = request_irq(mcfqspi->irq, mcfqspi_irq_handler, 0, 413 status = devm_request_irq(&pdev->dev, mcfqspi->irq, mcfqspi_irq_handler,
427 pdev->name, mcfqspi); 414 0, pdev->name, mcfqspi);
428 if (status) { 415 if (status) {
429 dev_dbg(&pdev->dev, "request_irq failed\n"); 416 dev_dbg(&pdev->dev, "request_irq failed\n");
430 goto fail2; 417 goto fail0;
431 } 418 }
432 419
433 mcfqspi->clk = clk_get(&pdev->dev, "qspi_clk"); 420 mcfqspi->clk = devm_clk_get(&pdev->dev, "qspi_clk");
434 if (IS_ERR(mcfqspi->clk)) { 421 if (IS_ERR(mcfqspi->clk)) {
435 dev_dbg(&pdev->dev, "clk_get failed\n"); 422 dev_dbg(&pdev->dev, "clk_get failed\n");
436 status = PTR_ERR(mcfqspi->clk); 423 status = PTR_ERR(mcfqspi->clk);
437 goto fail3; 424 goto fail0;
438 } 425 }
439 clk_enable(mcfqspi->clk); 426 clk_enable(mcfqspi->clk);
440 427
@@ -445,7 +432,7 @@ static int mcfqspi_probe(struct platform_device *pdev)
445 status = mcfqspi_cs_setup(mcfqspi); 432 status = mcfqspi_cs_setup(mcfqspi);
446 if (status) { 433 if (status) {
447 dev_dbg(&pdev->dev, "error initializing cs_control\n"); 434 dev_dbg(&pdev->dev, "error initializing cs_control\n");
448 goto fail4; 435 goto fail1;
449 } 436 }
450 437
451 init_waitqueue_head(&mcfqspi->waitq); 438 init_waitqueue_head(&mcfqspi->waitq);
@@ -459,10 +446,10 @@ static int mcfqspi_probe(struct platform_device *pdev)
459 446
460 platform_set_drvdata(pdev, master); 447 platform_set_drvdata(pdev, master);
461 448
462 status = spi_register_master(master); 449 status = devm_spi_register_master(&pdev->dev, master);
463 if (status) { 450 if (status) {
464 dev_dbg(&pdev->dev, "spi_register_master failed\n"); 451 dev_dbg(&pdev->dev, "spi_register_master failed\n");
465 goto fail5; 452 goto fail2;
466 } 453 }
467 pm_runtime_enable(mcfqspi->dev); 454 pm_runtime_enable(mcfqspi->dev);
468 455
@@ -470,17 +457,10 @@ static int mcfqspi_probe(struct platform_device *pdev)
470 457
471 return 0; 458 return 0;
472 459
473fail5:
474 mcfqspi_cs_teardown(mcfqspi);
475fail4:
476 clk_disable(mcfqspi->clk);
477 clk_put(mcfqspi->clk);
478fail3:
479 free_irq(mcfqspi->irq, mcfqspi);
480fail2: 460fail2:
481 iounmap(mcfqspi->iobase); 461 mcfqspi_cs_teardown(mcfqspi);
482fail1: 462fail1:
483 release_mem_region(res->start, resource_size(res)); 463 clk_disable(mcfqspi->clk);
484fail0: 464fail0:
485 spi_master_put(master); 465 spi_master_put(master);
486 466
@@ -501,11 +481,6 @@ static int mcfqspi_remove(struct platform_device *pdev)
501 481
502 mcfqspi_cs_teardown(mcfqspi); 482 mcfqspi_cs_teardown(mcfqspi);
503 clk_disable(mcfqspi->clk); 483 clk_disable(mcfqspi->clk);
504 clk_put(mcfqspi->clk);
505 free_irq(mcfqspi->irq, mcfqspi);
506 iounmap(mcfqspi->iobase);
507 release_mem_region(res->start, resource_size(res));
508 spi_unregister_master(master);
509 484
510 return 0; 485 return 0;
511} 486}
diff --git a/drivers/spi/spi-davinci.c b/drivers/spi/spi-davinci.c
index 50b2d88c8190..5e7389faa2a0 100644
--- a/drivers/spi/spi-davinci.c
+++ b/drivers/spi/spi-davinci.c
@@ -396,10 +396,6 @@ static int davinci_spi_setup(struct spi_device *spi)
396 dspi = spi_master_get_devdata(spi->master); 396 dspi = spi_master_get_devdata(spi->master);
397 pdata = &dspi->pdata; 397 pdata = &dspi->pdata;
398 398
399 /* if bits per word length is zero then set it default 8 */
400 if (!spi->bits_per_word)
401 spi->bits_per_word = 8;
402
403 if (!(spi->mode & SPI_NO_CS)) { 399 if (!(spi->mode & SPI_NO_CS)) {
404 if ((pdata->chip_sel == NULL) || 400 if ((pdata->chip_sel == NULL) ||
405 (pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS)) 401 (pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS))
@@ -853,7 +849,7 @@ static int davinci_spi_probe(struct platform_device *pdev)
853 struct spi_master *master; 849 struct spi_master *master;
854 struct davinci_spi *dspi; 850 struct davinci_spi *dspi;
855 struct davinci_spi_platform_data *pdata; 851 struct davinci_spi_platform_data *pdata;
856 struct resource *r, *mem; 852 struct resource *r;
857 resource_size_t dma_rx_chan = SPI_NO_RESOURCE; 853 resource_size_t dma_rx_chan = SPI_NO_RESOURCE;
858 resource_size_t dma_tx_chan = SPI_NO_RESOURCE; 854 resource_size_t dma_tx_chan = SPI_NO_RESOURCE;
859 int i = 0, ret = 0; 855 int i = 0, ret = 0;
@@ -894,39 +890,33 @@ static int davinci_spi_probe(struct platform_device *pdev)
894 890
895 dspi->pbase = r->start; 891 dspi->pbase = r->start;
896 892
897 mem = request_mem_region(r->start, resource_size(r), pdev->name); 893 dspi->base = devm_ioremap_resource(&pdev->dev, r);
898 if (mem == NULL) { 894 if (IS_ERR(dspi->base)) {
899 ret = -EBUSY; 895 ret = PTR_ERR(dspi->base);
900 goto free_master; 896 goto free_master;
901 } 897 }
902 898
903 dspi->base = ioremap(r->start, resource_size(r));
904 if (dspi->base == NULL) {
905 ret = -ENOMEM;
906 goto release_region;
907 }
908
909 dspi->irq = platform_get_irq(pdev, 0); 899 dspi->irq = platform_get_irq(pdev, 0);
910 if (dspi->irq <= 0) { 900 if (dspi->irq <= 0) {
911 ret = -EINVAL; 901 ret = -EINVAL;
912 goto unmap_io; 902 goto free_master;
913 } 903 }
914 904
915 ret = request_threaded_irq(dspi->irq, davinci_spi_irq, dummy_thread_fn, 905 ret = devm_request_threaded_irq(&pdev->dev, dspi->irq, davinci_spi_irq,
916 0, dev_name(&pdev->dev), dspi); 906 dummy_thread_fn, 0, dev_name(&pdev->dev), dspi);
917 if (ret) 907 if (ret)
918 goto unmap_io; 908 goto free_master;
919 909
920 dspi->bitbang.master = master; 910 dspi->bitbang.master = master;
921 if (dspi->bitbang.master == NULL) { 911 if (dspi->bitbang.master == NULL) {
922 ret = -ENODEV; 912 ret = -ENODEV;
923 goto irq_free; 913 goto free_master;
924 } 914 }
925 915
926 dspi->clk = clk_get(&pdev->dev, NULL); 916 dspi->clk = devm_clk_get(&pdev->dev, NULL);
927 if (IS_ERR(dspi->clk)) { 917 if (IS_ERR(dspi->clk)) {
928 ret = -ENODEV; 918 ret = -ENODEV;
929 goto irq_free; 919 goto free_master;
930 } 920 }
931 clk_prepare_enable(dspi->clk); 921 clk_prepare_enable(dspi->clk);
932 922
@@ -963,8 +953,8 @@ static int davinci_spi_probe(struct platform_device *pdev)
963 goto free_clk; 953 goto free_clk;
964 954
965 dev_info(&pdev->dev, "DMA: supported\n"); 955 dev_info(&pdev->dev, "DMA: supported\n");
966 dev_info(&pdev->dev, "DMA: RX channel: %d, TX channel: %d, " 956 dev_info(&pdev->dev, "DMA: RX channel: %pa, TX channel: %pa, "
967 "event queue: %d\n", dma_rx_chan, dma_tx_chan, 957 "event queue: %d\n", &dma_rx_chan, &dma_tx_chan,
968 pdata->dma_event_q); 958 pdata->dma_event_q);
969 } 959 }
970 960
@@ -1015,13 +1005,6 @@ free_dma:
1015 dma_release_channel(dspi->dma_tx); 1005 dma_release_channel(dspi->dma_tx);
1016free_clk: 1006free_clk:
1017 clk_disable_unprepare(dspi->clk); 1007 clk_disable_unprepare(dspi->clk);
1018 clk_put(dspi->clk);
1019irq_free:
1020 free_irq(dspi->irq, dspi);
1021unmap_io:
1022 iounmap(dspi->base);
1023release_region:
1024 release_mem_region(dspi->pbase, resource_size(r));
1025free_master: 1008free_master:
1026 spi_master_put(master); 1009 spi_master_put(master);
1027err: 1010err:
@@ -1041,7 +1024,6 @@ static int davinci_spi_remove(struct platform_device *pdev)
1041{ 1024{
1042 struct davinci_spi *dspi; 1025 struct davinci_spi *dspi;
1043 struct spi_master *master; 1026 struct spi_master *master;
1044 struct resource *r;
1045 1027
1046 master = platform_get_drvdata(pdev); 1028 master = platform_get_drvdata(pdev);
1047 dspi = spi_master_get_devdata(master); 1029 dspi = spi_master_get_devdata(master);
@@ -1049,11 +1031,6 @@ static int davinci_spi_remove(struct platform_device *pdev)
1049 spi_bitbang_stop(&dspi->bitbang); 1031 spi_bitbang_stop(&dspi->bitbang);
1050 1032
1051 clk_disable_unprepare(dspi->clk); 1033 clk_disable_unprepare(dspi->clk);
1052 clk_put(dspi->clk);
1053 free_irq(dspi->irq, dspi);
1054 iounmap(dspi->base);
1055 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1056 release_mem_region(dspi->pbase, resource_size(r));
1057 spi_master_put(master); 1034 spi_master_put(master);
1058 1035
1059 return 0; 1036 return 0;
diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c
index 168c620947f4..9af56cdf1540 100644
--- a/drivers/spi/spi-dw-mmio.c
+++ b/drivers/spi/spi-dw-mmio.c
@@ -30,14 +30,13 @@ static int dw_spi_mmio_probe(struct platform_device *pdev)
30{ 30{
31 struct dw_spi_mmio *dwsmmio; 31 struct dw_spi_mmio *dwsmmio;
32 struct dw_spi *dws; 32 struct dw_spi *dws;
33 struct resource *mem, *ioarea; 33 struct resource *mem;
34 int ret; 34 int ret;
35 35
36 dwsmmio = kzalloc(sizeof(struct dw_spi_mmio), GFP_KERNEL); 36 dwsmmio = devm_kzalloc(&pdev->dev, sizeof(struct dw_spi_mmio),
37 if (!dwsmmio) { 37 GFP_KERNEL);
38 ret = -ENOMEM; 38 if (!dwsmmio)
39 goto err_end; 39 return -ENOMEM;
40 }
41 40
42 dws = &dwsmmio->dws; 41 dws = &dwsmmio->dws;
43 42
@@ -45,80 +44,51 @@ static int dw_spi_mmio_probe(struct platform_device *pdev)
45 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 44 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
46 if (!mem) { 45 if (!mem) {
47 dev_err(&pdev->dev, "no mem resource?\n"); 46 dev_err(&pdev->dev, "no mem resource?\n");
48 ret = -EINVAL; 47 return -EINVAL;
49 goto err_kfree;
50 } 48 }
51 49
52 ioarea = request_mem_region(mem->start, resource_size(mem), 50 dws->regs = devm_ioremap_resource(&pdev->dev, mem);
53 pdev->name); 51 if (IS_ERR(dws->regs)) {
54 if (!ioarea) { 52 dev_err(&pdev->dev, "SPI region map failed\n");
55 dev_err(&pdev->dev, "SPI region already claimed\n"); 53 return PTR_ERR(dws->regs);
56 ret = -EBUSY;
57 goto err_kfree;
58 }
59
60 dws->regs = ioremap_nocache(mem->start, resource_size(mem));
61 if (!dws->regs) {
62 dev_err(&pdev->dev, "SPI region already mapped\n");
63 ret = -ENOMEM;
64 goto err_release_reg;
65 } 54 }
66 55
67 dws->irq = platform_get_irq(pdev, 0); 56 dws->irq = platform_get_irq(pdev, 0);
68 if (dws->irq < 0) { 57 if (dws->irq < 0) {
69 dev_err(&pdev->dev, "no irq resource?\n"); 58 dev_err(&pdev->dev, "no irq resource?\n");
70 ret = dws->irq; /* -ENXIO */ 59 return dws->irq; /* -ENXIO */
71 goto err_unmap;
72 } 60 }
73 61
74 dwsmmio->clk = clk_get(&pdev->dev, NULL); 62 dwsmmio->clk = devm_clk_get(&pdev->dev, NULL);
75 if (IS_ERR(dwsmmio->clk)) { 63 if (IS_ERR(dwsmmio->clk))
76 ret = PTR_ERR(dwsmmio->clk); 64 return PTR_ERR(dwsmmio->clk);
77 goto err_unmap; 65 ret = clk_prepare_enable(dwsmmio->clk);
78 } 66 if (ret)
79 clk_enable(dwsmmio->clk); 67 return ret;
80 68
81 dws->parent_dev = &pdev->dev;
82 dws->bus_num = 0; 69 dws->bus_num = 0;
83 dws->num_cs = 4; 70 dws->num_cs = 4;
84 dws->max_freq = clk_get_rate(dwsmmio->clk); 71 dws->max_freq = clk_get_rate(dwsmmio->clk);
85 72
86 ret = dw_spi_add_host(dws); 73 ret = dw_spi_add_host(&pdev->dev, dws);
87 if (ret) 74 if (ret)
88 goto err_clk; 75 goto out;
89 76
90 platform_set_drvdata(pdev, dwsmmio); 77 platform_set_drvdata(pdev, dwsmmio);
91 return 0; 78 return 0;
92 79
93err_clk: 80out:
94 clk_disable(dwsmmio->clk); 81 clk_disable_unprepare(dwsmmio->clk);
95 clk_put(dwsmmio->clk);
96 dwsmmio->clk = NULL;
97err_unmap:
98 iounmap(dws->regs);
99err_release_reg:
100 release_mem_region(mem->start, resource_size(mem));
101err_kfree:
102 kfree(dwsmmio);
103err_end:
104 return ret; 82 return ret;
105} 83}
106 84
107static int dw_spi_mmio_remove(struct platform_device *pdev) 85static int dw_spi_mmio_remove(struct platform_device *pdev)
108{ 86{
109 struct dw_spi_mmio *dwsmmio = platform_get_drvdata(pdev); 87 struct dw_spi_mmio *dwsmmio = platform_get_drvdata(pdev);
110 struct resource *mem;
111
112 clk_disable(dwsmmio->clk);
113 clk_put(dwsmmio->clk);
114 dwsmmio->clk = NULL;
115 88
89 clk_disable_unprepare(dwsmmio->clk);
116 dw_spi_remove_host(&dwsmmio->dws); 90 dw_spi_remove_host(&dwsmmio->dws);
117 iounmap(dwsmmio->dws.regs);
118 kfree(dwsmmio);
119 91
120 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
121 release_mem_region(mem->start, resource_size(mem));
122 return 0; 92 return 0;
123} 93}
124 94
diff --git a/drivers/spi/spi-dw-pci.c b/drivers/spi/spi-dw-pci.c
index 66fa9955ea14..3f3dc1226edf 100644
--- a/drivers/spi/spi-dw-pci.c
+++ b/drivers/spi/spi-dw-pci.c
@@ -43,35 +43,25 @@ static int spi_pci_probe(struct pci_dev *pdev,
43 dev_info(&pdev->dev, "found PCI SPI controller(ID: %04x:%04x)\n", 43 dev_info(&pdev->dev, "found PCI SPI controller(ID: %04x:%04x)\n",
44 pdev->vendor, pdev->device); 44 pdev->vendor, pdev->device);
45 45
46 ret = pci_enable_device(pdev); 46 ret = pcim_enable_device(pdev);
47 if (ret) 47 if (ret)
48 return ret; 48 return ret;
49 49
50 dwpci = kzalloc(sizeof(struct dw_spi_pci), GFP_KERNEL); 50 dwpci = devm_kzalloc(&pdev->dev, sizeof(struct dw_spi_pci),
51 if (!dwpci) { 51 GFP_KERNEL);
52 ret = -ENOMEM; 52 if (!dwpci)
53 goto err_disable; 53 return -ENOMEM;
54 }
55 54
56 dwpci->pdev = pdev; 55 dwpci->pdev = pdev;
57 dws = &dwpci->dws; 56 dws = &dwpci->dws;
58 57
59 /* Get basic io resource and map it */ 58 /* Get basic io resource and map it */
60 dws->paddr = pci_resource_start(pdev, pci_bar); 59 dws->paddr = pci_resource_start(pdev, pci_bar);
61 dws->iolen = pci_resource_len(pdev, pci_bar);
62 60
63 ret = pci_request_region(pdev, pci_bar, dev_name(&pdev->dev)); 61 ret = pcim_iomap_regions(pdev, 1, dev_name(&pdev->dev));
64 if (ret) 62 if (ret)
65 goto err_kfree; 63 return ret;
66
67 dws->regs = ioremap_nocache((unsigned long)dws->paddr,
68 pci_resource_len(pdev, pci_bar));
69 if (!dws->regs) {
70 ret = -ENOMEM;
71 goto err_release_reg;
72 }
73 64
74 dws->parent_dev = &pdev->dev;
75 dws->bus_num = 0; 65 dws->bus_num = 0;
76 dws->num_cs = 4; 66 dws->num_cs = 4;
77 dws->irq = pdev->irq; 67 dws->irq = pdev->irq;
@@ -83,26 +73,17 @@ static int spi_pci_probe(struct pci_dev *pdev,
83 if (pdev->device == 0x0800) { 73 if (pdev->device == 0x0800) {
84 ret = dw_spi_mid_init(dws); 74 ret = dw_spi_mid_init(dws);
85 if (ret) 75 if (ret)
86 goto err_unmap; 76 return ret;
87 } 77 }
88 78
89 ret = dw_spi_add_host(dws); 79 ret = dw_spi_add_host(&pdev->dev, dws);
90 if (ret) 80 if (ret)
91 goto err_unmap; 81 return ret;
92 82
93 /* PCI hook and SPI hook use the same drv data */ 83 /* PCI hook and SPI hook use the same drv data */
94 pci_set_drvdata(pdev, dwpci); 84 pci_set_drvdata(pdev, dwpci);
95 return 0;
96 85
97err_unmap: 86 return 0;
98 iounmap(dws->regs);
99err_release_reg:
100 pci_release_region(pdev, pci_bar);
101err_kfree:
102 kfree(dwpci);
103err_disable:
104 pci_disable_device(pdev);
105 return ret;
106} 87}
107 88
108static void spi_pci_remove(struct pci_dev *pdev) 89static void spi_pci_remove(struct pci_dev *pdev)
@@ -110,10 +91,6 @@ static void spi_pci_remove(struct pci_dev *pdev)
110 struct dw_spi_pci *dwpci = pci_get_drvdata(pdev); 91 struct dw_spi_pci *dwpci = pci_get_drvdata(pdev);
111 92
112 dw_spi_remove_host(&dwpci->dws); 93 dw_spi_remove_host(&dwpci->dws);
113 iounmap(dwpci->dws.regs);
114 pci_release_region(pdev, 0);
115 kfree(dwpci);
116 pci_disable_device(pdev);
117} 94}
118 95
119#ifdef CONFIG_PM 96#ifdef CONFIG_PM
@@ -148,7 +125,7 @@ static int spi_resume(struct pci_dev *pdev)
148#define spi_resume NULL 125#define spi_resume NULL
149#endif 126#endif
150 127
151static DEFINE_PCI_DEVICE_TABLE(pci_ids) = { 128static const struct pci_device_id pci_ids[] = {
152 /* Intel MID platform SPI controller 0 */ 129 /* Intel MID platform SPI controller 0 */
153 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0800) }, 130 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0800) },
154 {}, 131 {},
diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c
index b897c4adb39d..bf98d63d92b3 100644
--- a/drivers/spi/spi-dw.c
+++ b/drivers/spi/spi-dw.c
@@ -427,7 +427,6 @@ static void pump_transfers(unsigned long data)
427 dws->tx_end = dws->tx + transfer->len; 427 dws->tx_end = dws->tx + transfer->len;
428 dws->rx = transfer->rx_buf; 428 dws->rx = transfer->rx_buf;
429 dws->rx_end = dws->rx + transfer->len; 429 dws->rx_end = dws->rx + transfer->len;
430 dws->cs_change = transfer->cs_change;
431 dws->len = dws->cur_transfer->len; 430 dws->len = dws->cur_transfer->len;
432 if (chip != dws->prev_chip) 431 if (chip != dws->prev_chip)
433 cs_change = 1; 432 cs_change = 1;
@@ -620,9 +619,11 @@ static int dw_spi_setup(struct spi_device *spi)
620 /* Only alloc on first setup */ 619 /* Only alloc on first setup */
621 chip = spi_get_ctldata(spi); 620 chip = spi_get_ctldata(spi);
622 if (!chip) { 621 if (!chip) {
623 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); 622 chip = devm_kzalloc(&spi->dev, sizeof(struct chip_data),
623 GFP_KERNEL);
624 if (!chip) 624 if (!chip)
625 return -ENOMEM; 625 return -ENOMEM;
626 spi_set_ctldata(spi, chip);
626 } 627 }
627 628
628 /* 629 /*
@@ -667,7 +668,6 @@ static int dw_spi_setup(struct spi_device *spi)
667 | (spi->mode << SPI_MODE_OFFSET) 668 | (spi->mode << SPI_MODE_OFFSET)
668 | (chip->tmode << SPI_TMOD_OFFSET); 669 | (chip->tmode << SPI_TMOD_OFFSET);
669 670
670 spi_set_ctldata(spi, chip);
671 return 0; 671 return 0;
672} 672}
673 673
@@ -776,18 +776,16 @@ static void spi_hw_init(struct dw_spi *dws)
776 } 776 }
777} 777}
778 778
779int dw_spi_add_host(struct dw_spi *dws) 779int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
780{ 780{
781 struct spi_master *master; 781 struct spi_master *master;
782 int ret; 782 int ret;
783 783
784 BUG_ON(dws == NULL); 784 BUG_ON(dws == NULL);
785 785
786 master = spi_alloc_master(dws->parent_dev, 0); 786 master = spi_alloc_master(dev, 0);
787 if (!master) { 787 if (!master)
788 ret = -ENOMEM; 788 return -ENOMEM;
789 goto exit;
790 }
791 789
792 dws->master = master; 790 dws->master = master;
793 dws->type = SSI_MOTO_SPI; 791 dws->type = SSI_MOTO_SPI;
@@ -797,7 +795,7 @@ int dw_spi_add_host(struct dw_spi *dws)
797 snprintf(dws->name, sizeof(dws->name), "dw_spi%d", 795 snprintf(dws->name, sizeof(dws->name), "dw_spi%d",
798 dws->bus_num); 796 dws->bus_num);
799 797
800 ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED, 798 ret = devm_request_irq(dev, dws->irq, dw_spi_irq, IRQF_SHARED,
801 dws->name, dws); 799 dws->name, dws);
802 if (ret < 0) { 800 if (ret < 0) {
803 dev_err(&master->dev, "can not get IRQ\n"); 801 dev_err(&master->dev, "can not get IRQ\n");
@@ -836,7 +834,7 @@ int dw_spi_add_host(struct dw_spi *dws)
836 } 834 }
837 835
838 spi_master_set_devdata(master, dws); 836 spi_master_set_devdata(master, dws);
839 ret = spi_register_master(master); 837 ret = devm_spi_register_master(dev, master);
840 if (ret) { 838 if (ret) {
841 dev_err(&master->dev, "problem registering spi master\n"); 839 dev_err(&master->dev, "problem registering spi master\n");
842 goto err_queue_alloc; 840 goto err_queue_alloc;
@@ -851,10 +849,8 @@ err_queue_alloc:
851 dws->dma_ops->dma_exit(dws); 849 dws->dma_ops->dma_exit(dws);
852err_diable_hw: 850err_diable_hw:
853 spi_enable_chip(dws, 0); 851 spi_enable_chip(dws, 0);
854 free_irq(dws->irq, dws);
855err_free_master: 852err_free_master:
856 spi_master_put(master); 853 spi_master_put(master);
857exit:
858 return ret; 854 return ret;
859} 855}
860EXPORT_SYMBOL_GPL(dw_spi_add_host); 856EXPORT_SYMBOL_GPL(dw_spi_add_host);
@@ -878,10 +874,6 @@ void dw_spi_remove_host(struct dw_spi *dws)
878 spi_enable_chip(dws, 0); 874 spi_enable_chip(dws, 0);
879 /* Disable clk */ 875 /* Disable clk */
880 spi_set_clk(dws, 0); 876 spi_set_clk(dws, 0);
881 free_irq(dws->irq, dws);
882
883 /* Disconnect from the SPI framework */
884 spi_unregister_master(dws->master);
885} 877}
886EXPORT_SYMBOL_GPL(dw_spi_remove_host); 878EXPORT_SYMBOL_GPL(dw_spi_remove_host);
887 879
diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
index 9c57c078031e..587643dae11e 100644
--- a/drivers/spi/spi-dw.h
+++ b/drivers/spi/spi-dw.h
@@ -92,13 +92,11 @@ struct dw_spi_dma_ops {
92struct dw_spi { 92struct dw_spi {
93 struct spi_master *master; 93 struct spi_master *master;
94 struct spi_device *cur_dev; 94 struct spi_device *cur_dev;
95 struct device *parent_dev;
96 enum dw_ssi_type type; 95 enum dw_ssi_type type;
97 char name[16]; 96 char name[16];
98 97
99 void __iomem *regs; 98 void __iomem *regs;
100 unsigned long paddr; 99 unsigned long paddr;
101 u32 iolen;
102 int irq; 100 int irq;
103 u32 fifo_len; /* depth of the FIFO buffer */ 101 u32 fifo_len; /* depth of the FIFO buffer */
104 u32 max_freq; /* max bus freq supported */ 102 u32 max_freq; /* max bus freq supported */
@@ -135,7 +133,6 @@ struct dw_spi {
135 u8 n_bytes; /* current is a 1/2 bytes op */ 133 u8 n_bytes; /* current is a 1/2 bytes op */
136 u8 max_bits_per_word; /* maxim is 16b */ 134 u8 max_bits_per_word; /* maxim is 16b */
137 u32 dma_width; 135 u32 dma_width;
138 int cs_change;
139 irqreturn_t (*transfer_handler)(struct dw_spi *dws); 136 irqreturn_t (*transfer_handler)(struct dw_spi *dws);
140 void (*cs_control)(u32 command); 137 void (*cs_control)(u32 command);
141 138
@@ -231,7 +228,7 @@ struct dw_spi_chip {
231 void (*cs_control)(u32 command); 228 void (*cs_control)(u32 command);
232}; 229};
233 230
234extern int dw_spi_add_host(struct dw_spi *dws); 231extern int dw_spi_add_host(struct device *dev, struct dw_spi *dws);
235extern void dw_spi_remove_host(struct dw_spi *dws); 232extern void dw_spi_remove_host(struct dw_spi *dws);
236extern int dw_spi_suspend_host(struct dw_spi *dws); 233extern int dw_spi_suspend_host(struct dw_spi *dws);
237extern int dw_spi_resume_host(struct dw_spi *dws); 234extern int dw_spi_resume_host(struct dw_spi *dws);
diff --git a/drivers/spi/spi-falcon.c b/drivers/spi/spi-falcon.c
index c7a74f0ef892..dd5bd468e962 100644
--- a/drivers/spi/spi-falcon.c
+++ b/drivers/spi/spi-falcon.c
@@ -433,21 +433,12 @@ static int falcon_sflash_probe(struct platform_device *pdev)
433 433
434 platform_set_drvdata(pdev, priv); 434 platform_set_drvdata(pdev, priv);
435 435
436 ret = spi_register_master(master); 436 ret = devm_spi_register_master(&pdev->dev, master);
437 if (ret) 437 if (ret)
438 spi_master_put(master); 438 spi_master_put(master);
439 return ret; 439 return ret;
440} 440}
441 441
442static int falcon_sflash_remove(struct platform_device *pdev)
443{
444 struct falcon_sflash *priv = platform_get_drvdata(pdev);
445
446 spi_unregister_master(priv->master);
447
448 return 0;
449}
450
451static const struct of_device_id falcon_sflash_match[] = { 442static const struct of_device_id falcon_sflash_match[] = {
452 { .compatible = "lantiq,sflash-falcon" }, 443 { .compatible = "lantiq,sflash-falcon" },
453 {}, 444 {},
@@ -456,7 +447,6 @@ MODULE_DEVICE_TABLE(of, falcon_sflash_match);
456 447
457static struct platform_driver falcon_sflash_driver = { 448static struct platform_driver falcon_sflash_driver = {
458 .probe = falcon_sflash_probe, 449 .probe = falcon_sflash_probe,
459 .remove = falcon_sflash_remove,
460 .driver = { 450 .driver = {
461 .name = DRV_NAME, 451 .name = DRV_NAME,
462 .owner = THIS_MODULE, 452 .owner = THIS_MODULE,
diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c
index 8641b03bdd7a..ec79f726672a 100644
--- a/drivers/spi/spi-fsl-dspi.c
+++ b/drivers/spi/spi-fsl-dspi.c
@@ -320,8 +320,10 @@ static void dspi_chipselect(struct spi_device *spi, int value)
320 switch (value) { 320 switch (value) {
321 case BITBANG_CS_ACTIVE: 321 case BITBANG_CS_ACTIVE:
322 pushr |= SPI_PUSHR_CONT; 322 pushr |= SPI_PUSHR_CONT;
323 break;
323 case BITBANG_CS_INACTIVE: 324 case BITBANG_CS_INACTIVE:
324 pushr &= ~SPI_PUSHR_CONT; 325 pushr &= ~SPI_PUSHR_CONT;
326 break;
325 } 327 }
326 328
327 writel(pushr, dspi->base + SPI_PUSHR); 329 writel(pushr, dspi->base + SPI_PUSHR);
@@ -373,9 +375,6 @@ static int dspi_setup(struct spi_device *spi)
373 if (!spi->max_speed_hz) 375 if (!spi->max_speed_hz)
374 return -EINVAL; 376 return -EINVAL;
375 377
376 if (!spi->bits_per_word)
377 spi->bits_per_word = 8;
378
379 return dspi_setup_transfer(spi, NULL); 378 return dspi_setup_transfer(spi, NULL);
380} 379}
381 380
diff --git a/drivers/spi/spi-fsl-espi.c b/drivers/spi/spi-fsl-espi.c
index 80d8f40f7e05..428dc7a6b62e 100644
--- a/drivers/spi/spi-fsl-espi.c
+++ b/drivers/spi/spi-fsl-espi.c
@@ -705,7 +705,7 @@ static int of_fsl_espi_probe(struct platform_device *ofdev)
705 goto err; 705 goto err;
706 706
707 irq = irq_of_parse_and_map(np, 0); 707 irq = irq_of_parse_and_map(np, 0);
708 if (!ret) { 708 if (!irq) {
709 ret = -EINVAL; 709 ret = -EINVAL;
710 goto err; 710 goto err;
711 } 711 }
@@ -727,6 +727,66 @@ static int of_fsl_espi_remove(struct platform_device *dev)
727 return mpc8xxx_spi_remove(&dev->dev); 727 return mpc8xxx_spi_remove(&dev->dev);
728} 728}
729 729
730#ifdef CONFIG_PM_SLEEP
731static int of_fsl_espi_suspend(struct device *dev)
732{
733 struct spi_master *master = dev_get_drvdata(dev);
734 struct mpc8xxx_spi *mpc8xxx_spi;
735 struct fsl_espi_reg *reg_base;
736 u32 regval;
737 int ret;
738
739 mpc8xxx_spi = spi_master_get_devdata(master);
740 reg_base = mpc8xxx_spi->reg_base;
741
742 ret = spi_master_suspend(master);
743 if (ret) {
744 dev_warn(dev, "cannot suspend master\n");
745 return ret;
746 }
747
748 regval = mpc8xxx_spi_read_reg(&reg_base->mode);
749 regval &= ~SPMODE_ENABLE;
750 mpc8xxx_spi_write_reg(&reg_base->mode, regval);
751
752 return 0;
753}
754
755static int of_fsl_espi_resume(struct device *dev)
756{
757 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
758 struct spi_master *master = dev_get_drvdata(dev);
759 struct mpc8xxx_spi *mpc8xxx_spi;
760 struct fsl_espi_reg *reg_base;
761 u32 regval;
762 int i;
763
764 mpc8xxx_spi = spi_master_get_devdata(master);
765 reg_base = mpc8xxx_spi->reg_base;
766
767 /* SPI controller initializations */
768 mpc8xxx_spi_write_reg(&reg_base->mode, 0);
769 mpc8xxx_spi_write_reg(&reg_base->mask, 0);
770 mpc8xxx_spi_write_reg(&reg_base->command, 0);
771 mpc8xxx_spi_write_reg(&reg_base->event, 0xffffffff);
772
773 /* Init eSPI CS mode register */
774 for (i = 0; i < pdata->max_chipselect; i++)
775 mpc8xxx_spi_write_reg(&reg_base->csmode[i], CSMODE_INIT_VAL);
776
777 /* Enable SPI interface */
778 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
779
780 mpc8xxx_spi_write_reg(&reg_base->mode, regval);
781
782 return spi_master_resume(master);
783}
784#endif /* CONFIG_PM_SLEEP */
785
786static const struct dev_pm_ops espi_pm = {
787 SET_SYSTEM_SLEEP_PM_OPS(of_fsl_espi_suspend, of_fsl_espi_resume)
788};
789
730static const struct of_device_id of_fsl_espi_match[] = { 790static const struct of_device_id of_fsl_espi_match[] = {
731 { .compatible = "fsl,mpc8536-espi" }, 791 { .compatible = "fsl,mpc8536-espi" },
732 {} 792 {}
@@ -738,6 +798,7 @@ static struct platform_driver fsl_espi_driver = {
738 .name = "fsl_espi", 798 .name = "fsl_espi",
739 .owner = THIS_MODULE, 799 .owner = THIS_MODULE,
740 .of_match_table = of_fsl_espi_match, 800 .of_match_table = of_fsl_espi_match,
801 .pm = &espi_pm,
741 }, 802 },
742 .probe = of_fsl_espi_probe, 803 .probe = of_fsl_espi_probe,
743 .remove = of_fsl_espi_remove, 804 .remove = of_fsl_espi_remove,
diff --git a/drivers/spi/spi-gpio.c b/drivers/spi/spi-gpio.c
index 3fb09f981980..7beeb29472ac 100644
--- a/drivers/spi/spi-gpio.c
+++ b/drivers/spi/spi-gpio.c
@@ -115,17 +115,17 @@ spi_to_pdata(const struct spi_device *spi)
115 115
116static inline void setsck(const struct spi_device *spi, int is_on) 116static inline void setsck(const struct spi_device *spi, int is_on)
117{ 117{
118 gpio_set_value(SPI_SCK_GPIO, is_on); 118 gpio_set_value_cansleep(SPI_SCK_GPIO, is_on);
119} 119}
120 120
121static inline void setmosi(const struct spi_device *spi, int is_on) 121static inline void setmosi(const struct spi_device *spi, int is_on)
122{ 122{
123 gpio_set_value(SPI_MOSI_GPIO, is_on); 123 gpio_set_value_cansleep(SPI_MOSI_GPIO, is_on);
124} 124}
125 125
126static inline int getmiso(const struct spi_device *spi) 126static inline int getmiso(const struct spi_device *spi)
127{ 127{
128 return !!gpio_get_value(SPI_MISO_GPIO); 128 return !!gpio_get_value_cansleep(SPI_MISO_GPIO);
129} 129}
130 130
131#undef pdata 131#undef pdata
@@ -229,7 +229,7 @@ static void spi_gpio_chipselect(struct spi_device *spi, int is_active)
229 229
230 if (cs != SPI_GPIO_NO_CHIPSELECT) { 230 if (cs != SPI_GPIO_NO_CHIPSELECT) {
231 /* SPI is normally active-low */ 231 /* SPI is normally active-low */
232 gpio_set_value(cs, (spi->mode & SPI_CS_HIGH) ? is_active : !is_active); 232 gpio_set_value_cansleep(cs, (spi->mode & SPI_CS_HIGH) ? is_active : !is_active);
233 } 233 }
234} 234}
235 235
diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
index b80f2f70fef7..a5474ef9d2a0 100644
--- a/drivers/spi/spi-imx.c
+++ b/drivers/spi/spi-imx.c
@@ -206,7 +206,8 @@ static unsigned int spi_imx_clkdiv_2(unsigned int fin,
206#define MX51_ECSPI_STAT_RR (1 << 3) 206#define MX51_ECSPI_STAT_RR (1 << 3)
207 207
208/* MX51 eCSPI */ 208/* MX51 eCSPI */
209static unsigned int mx51_ecspi_clkdiv(unsigned int fin, unsigned int fspi) 209static unsigned int mx51_ecspi_clkdiv(unsigned int fin, unsigned int fspi,
210 unsigned int *fres)
210{ 211{
211 /* 212 /*
212 * there are two 4-bit dividers, the pre-divider divides by 213 * there are two 4-bit dividers, the pre-divider divides by
@@ -234,6 +235,10 @@ static unsigned int mx51_ecspi_clkdiv(unsigned int fin, unsigned int fspi)
234 235
235 pr_debug("%s: fin: %u, fspi: %u, post: %u, pre: %u\n", 236 pr_debug("%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
236 __func__, fin, fspi, post, pre); 237 __func__, fin, fspi, post, pre);
238
239 /* Resulting frequency for the SCLK line. */
240 *fres = (fin / (pre + 1)) >> post;
241
237 return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) | 242 return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
238 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET); 243 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
239} 244}
@@ -264,6 +269,7 @@ static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx,
264 struct spi_imx_config *config) 269 struct spi_imx_config *config)
265{ 270{
266 u32 ctrl = MX51_ECSPI_CTRL_ENABLE, cfg = 0; 271 u32 ctrl = MX51_ECSPI_CTRL_ENABLE, cfg = 0;
272 u32 clk = config->speed_hz, delay;
267 273
268 /* 274 /*
269 * The hardware seems to have a race condition when changing modes. The 275 * The hardware seems to have a race condition when changing modes. The
@@ -275,7 +281,7 @@ static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx,
275 ctrl |= MX51_ECSPI_CTRL_MODE_MASK; 281 ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
276 282
277 /* set clock speed */ 283 /* set clock speed */
278 ctrl |= mx51_ecspi_clkdiv(spi_imx->spi_clk, config->speed_hz); 284 ctrl |= mx51_ecspi_clkdiv(spi_imx->spi_clk, config->speed_hz, &clk);
279 285
280 /* set chip select to use */ 286 /* set chip select to use */
281 ctrl |= MX51_ECSPI_CTRL_CS(config->cs); 287 ctrl |= MX51_ECSPI_CTRL_CS(config->cs);
@@ -297,6 +303,23 @@ static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx,
297 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); 303 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
298 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG); 304 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
299 305
306 /*
307 * Wait until the changes in the configuration register CONFIGREG
308 * propagate into the hardware. It takes exactly one tick of the
309 * SCLK clock, but we will wait two SCLK clock just to be sure. The
310 * effect of the delay it takes for the hardware to apply changes
311 * is noticable if the SCLK clock run very slow. In such a case, if
312 * the polarity of SCLK should be inverted, the GPIO ChipSelect might
313 * be asserted before the SCLK polarity changes, which would disrupt
314 * the SPI communication as the device on the other end would consider
315 * the change of SCLK polarity as a clock tick already.
316 */
317 delay = (2 * 1000000) / clk;
318 if (likely(delay < 10)) /* SCLK is faster than 100 kHz */
319 udelay(delay);
320 else /* SCLK is _very_ slow */
321 usleep_range(delay, delay + 10);
322
300 return 0; 323 return 0;
301} 324}
302 325
diff --git a/drivers/spi/spi-mpc512x-psc.c b/drivers/spi/spi-mpc512x-psc.c
index 87676587d783..46d2313f7c6f 100644
--- a/drivers/spi/spi-mpc512x-psc.c
+++ b/drivers/spi/spi-mpc512x-psc.c
@@ -504,7 +504,7 @@ static int mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr,
504 master->cleanup = mpc512x_psc_spi_cleanup; 504 master->cleanup = mpc512x_psc_spi_cleanup;
505 master->dev.of_node = dev->of_node; 505 master->dev.of_node = dev->of_node;
506 506
507 tempp = ioremap(regaddr, size); 507 tempp = devm_ioremap(dev, regaddr, size);
508 if (!tempp) { 508 if (!tempp) {
509 dev_err(dev, "could not ioremap I/O port range\n"); 509 dev_err(dev, "could not ioremap I/O port range\n");
510 ret = -EFAULT; 510 ret = -EFAULT;
@@ -513,9 +513,8 @@ static int mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr,
513 mps->psc = tempp; 513 mps->psc = tempp;
514 mps->fifo = 514 mps->fifo =
515 (struct mpc512x_psc_fifo *)(tempp + sizeof(struct mpc52xx_psc)); 515 (struct mpc512x_psc_fifo *)(tempp + sizeof(struct mpc52xx_psc));
516 516 ret = devm_request_irq(dev, mps->irq, mpc512x_psc_spi_isr, IRQF_SHARED,
517 ret = request_irq(mps->irq, mpc512x_psc_spi_isr, IRQF_SHARED, 517 "mpc512x-psc-spi", mps);
518 "mpc512x-psc-spi", mps);
519 if (ret) 518 if (ret)
520 goto free_master; 519 goto free_master;
521 init_completion(&mps->txisrdone); 520 init_completion(&mps->txisrdone);
@@ -525,11 +524,11 @@ static int mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr,
525 clk = devm_clk_get(dev, clk_name); 524 clk = devm_clk_get(dev, clk_name);
526 if (IS_ERR(clk)) { 525 if (IS_ERR(clk)) {
527 ret = PTR_ERR(clk); 526 ret = PTR_ERR(clk);
528 goto free_irq; 527 goto free_master;
529 } 528 }
530 ret = clk_prepare_enable(clk); 529 ret = clk_prepare_enable(clk);
531 if (ret) 530 if (ret)
532 goto free_irq; 531 goto free_master;
533 mps->clk_mclk = clk; 532 mps->clk_mclk = clk;
534 mps->mclk_rate = clk_get_rate(clk); 533 mps->mclk_rate = clk_get_rate(clk);
535 534
@@ -545,11 +544,7 @@ static int mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr,
545 544
546free_clock: 545free_clock:
547 clk_disable_unprepare(mps->clk_mclk); 546 clk_disable_unprepare(mps->clk_mclk);
548free_irq:
549 free_irq(mps->irq, mps);
550free_master: 547free_master:
551 if (mps->psc)
552 iounmap(mps->psc);
553 spi_master_put(master); 548 spi_master_put(master);
554 549
555 return ret; 550 return ret;
@@ -561,9 +556,6 @@ static int mpc512x_psc_spi_do_remove(struct device *dev)
561 struct mpc512x_psc_spi *mps = spi_master_get_devdata(master); 556 struct mpc512x_psc_spi *mps = spi_master_get_devdata(master);
562 557
563 clk_disable_unprepare(mps->clk_mclk); 558 clk_disable_unprepare(mps->clk_mclk);
564 free_irq(mps->irq, mps);
565 if (mps->psc)
566 iounmap(mps->psc);
567 559
568 return 0; 560 return 0;
569} 561}
diff --git a/drivers/spi/spi-mxs.c b/drivers/spi/spi-mxs.c
index 3adebfa22e3d..79e5aa2250c8 100644
--- a/drivers/spi/spi-mxs.c
+++ b/drivers/spi/spi-mxs.c
@@ -111,14 +111,6 @@ static int mxs_spi_setup_transfer(struct spi_device *dev,
111 return 0; 111 return 0;
112} 112}
113 113
114static int mxs_spi_setup(struct spi_device *dev)
115{
116 if (!dev->bits_per_word)
117 dev->bits_per_word = 8;
118
119 return 0;
120}
121
122static u32 mxs_spi_cs_to_reg(unsigned cs) 114static u32 mxs_spi_cs_to_reg(unsigned cs)
123{ 115{
124 u32 select = 0; 116 u32 select = 0;
@@ -502,7 +494,6 @@ static int mxs_spi_probe(struct platform_device *pdev)
502 return -ENOMEM; 494 return -ENOMEM;
503 495
504 master->transfer_one_message = mxs_spi_transfer_one; 496 master->transfer_one_message = mxs_spi_transfer_one;
505 master->setup = mxs_spi_setup;
506 master->bits_per_word_mask = SPI_BPW_MASK(8); 497 master->bits_per_word_mask = SPI_BPW_MASK(8);
507 master->mode_bits = SPI_CPOL | SPI_CPHA; 498 master->mode_bits = SPI_CPOL | SPI_CPHA;
508 master->num_chipselect = 3; 499 master->num_chipselect = 3;
diff --git a/drivers/spi/spi-nuc900.c b/drivers/spi/spi-nuc900.c
index e0c32bc69ee2..50406306bc20 100644
--- a/drivers/spi/spi-nuc900.c
+++ b/drivers/spi/spi-nuc900.c
@@ -57,7 +57,6 @@ struct nuc900_spi {
57 const unsigned char *tx; 57 const unsigned char *tx;
58 unsigned char *rx; 58 unsigned char *rx;
59 struct clk *clk; 59 struct clk *clk;
60 struct resource *ioarea;
61 struct spi_master *master; 60 struct spi_master *master;
62 struct spi_device *curdev; 61 struct spi_device *curdev;
63 struct device *dev; 62 struct device *dev;
@@ -344,8 +343,7 @@ static int nuc900_spi_probe(struct platform_device *pdev)
344 master = spi_alloc_master(&pdev->dev, sizeof(struct nuc900_spi)); 343 master = spi_alloc_master(&pdev->dev, sizeof(struct nuc900_spi));
345 if (master == NULL) { 344 if (master == NULL) {
346 dev_err(&pdev->dev, "No memory for spi_master\n"); 345 dev_err(&pdev->dev, "No memory for spi_master\n");
347 err = -ENOMEM; 346 return -ENOMEM;
348 goto err_nomem;
349 } 347 }
350 348
351 hw = spi_master_get_devdata(master); 349 hw = spi_master_get_devdata(master);
@@ -370,46 +368,31 @@ static int nuc900_spi_probe(struct platform_device *pdev)
370 hw->bitbang.txrx_bufs = nuc900_spi_txrx; 368 hw->bitbang.txrx_bufs = nuc900_spi_txrx;
371 369
372 hw->res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 370 hw->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
373 if (hw->res == NULL) { 371 hw->regs = devm_ioremap_resource(&pdev->dev, hw->res);
374 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n"); 372 if (IS_ERR(hw->regs)) {
375 err = -ENOENT; 373 err = PTR_ERR(hw->regs);
376 goto err_pdata;
377 }
378
379 hw->ioarea = request_mem_region(hw->res->start,
380 resource_size(hw->res), pdev->name);
381
382 if (hw->ioarea == NULL) {
383 dev_err(&pdev->dev, "Cannot reserve region\n");
384 err = -ENXIO;
385 goto err_pdata; 374 goto err_pdata;
386 } 375 }
387 376
388 hw->regs = ioremap(hw->res->start, resource_size(hw->res));
389 if (hw->regs == NULL) {
390 dev_err(&pdev->dev, "Cannot map IO\n");
391 err = -ENXIO;
392 goto err_iomap;
393 }
394
395 hw->irq = platform_get_irq(pdev, 0); 377 hw->irq = platform_get_irq(pdev, 0);
396 if (hw->irq < 0) { 378 if (hw->irq < 0) {
397 dev_err(&pdev->dev, "No IRQ specified\n"); 379 dev_err(&pdev->dev, "No IRQ specified\n");
398 err = -ENOENT; 380 err = -ENOENT;
399 goto err_irq; 381 goto err_pdata;
400 } 382 }
401 383
402 err = request_irq(hw->irq, nuc900_spi_irq, 0, pdev->name, hw); 384 err = devm_request_irq(&pdev->dev, hw->irq, nuc900_spi_irq, 0,
385 pdev->name, hw);
403 if (err) { 386 if (err) {
404 dev_err(&pdev->dev, "Cannot claim IRQ\n"); 387 dev_err(&pdev->dev, "Cannot claim IRQ\n");
405 goto err_irq; 388 goto err_pdata;
406 } 389 }
407 390
408 hw->clk = clk_get(&pdev->dev, "spi"); 391 hw->clk = devm_clk_get(&pdev->dev, "spi");
409 if (IS_ERR(hw->clk)) { 392 if (IS_ERR(hw->clk)) {
410 dev_err(&pdev->dev, "No clock for device\n"); 393 dev_err(&pdev->dev, "No clock for device\n");
411 err = PTR_ERR(hw->clk); 394 err = PTR_ERR(hw->clk);
412 goto err_clk; 395 goto err_pdata;
413 } 396 }
414 397
415 mfp_set_groupg(&pdev->dev, NULL); 398 mfp_set_groupg(&pdev->dev, NULL);
@@ -425,17 +408,8 @@ static int nuc900_spi_probe(struct platform_device *pdev)
425 408
426err_register: 409err_register:
427 clk_disable(hw->clk); 410 clk_disable(hw->clk);
428 clk_put(hw->clk);
429err_clk:
430 free_irq(hw->irq, hw);
431err_irq:
432 iounmap(hw->regs);
433err_iomap:
434 release_mem_region(hw->res->start, resource_size(hw->res));
435 kfree(hw->ioarea);
436err_pdata: 411err_pdata:
437 spi_master_put(hw->master); 412 spi_master_put(hw->master);
438err_nomem:
439 return err; 413 return err;
440} 414}
441 415
@@ -443,18 +417,8 @@ static int nuc900_spi_remove(struct platform_device *dev)
443{ 417{
444 struct nuc900_spi *hw = platform_get_drvdata(dev); 418 struct nuc900_spi *hw = platform_get_drvdata(dev);
445 419
446 free_irq(hw->irq, hw);
447
448 spi_bitbang_stop(&hw->bitbang); 420 spi_bitbang_stop(&hw->bitbang);
449
450 clk_disable(hw->clk); 421 clk_disable(hw->clk);
451 clk_put(hw->clk);
452
453 iounmap(hw->regs);
454
455 release_mem_region(hw->res->start, resource_size(hw->res));
456 kfree(hw->ioarea);
457
458 spi_master_put(hw->master); 422 spi_master_put(hw->master);
459 return 0; 423 return 0;
460} 424}
diff --git a/drivers/spi/spi-oc-tiny.c b/drivers/spi/spi-oc-tiny.c
index 91c668596202..f7c896e2981e 100644
--- a/drivers/spi/spi-oc-tiny.c
+++ b/drivers/spi/spi-oc-tiny.c
@@ -153,62 +153,22 @@ static int tiny_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
153 } 153 }
154 154
155 wait_for_completion(&hw->done); 155 wait_for_completion(&hw->done);
156 } else if (txp && rxp) {
157 /* we need to tighten the transfer loop */
158 writeb(*txp++, hw->base + TINY_SPI_TXDATA);
159 if (t->len > 1) {
160 writeb(*txp++, hw->base + TINY_SPI_TXDATA);
161 for (i = 2; i < t->len; i++) {
162 u8 rx, tx = *txp++;
163 tiny_spi_wait_txr(hw);
164 rx = readb(hw->base + TINY_SPI_TXDATA);
165 writeb(tx, hw->base + TINY_SPI_TXDATA);
166 *rxp++ = rx;
167 }
168 tiny_spi_wait_txr(hw);
169 *rxp++ = readb(hw->base + TINY_SPI_TXDATA);
170 }
171 tiny_spi_wait_txe(hw);
172 *rxp++ = readb(hw->base + TINY_SPI_RXDATA);
173 } else if (rxp) {
174 writeb(0, hw->base + TINY_SPI_TXDATA);
175 if (t->len > 1) {
176 writeb(0,
177 hw->base + TINY_SPI_TXDATA);
178 for (i = 2; i < t->len; i++) {
179 u8 rx;
180 tiny_spi_wait_txr(hw);
181 rx = readb(hw->base + TINY_SPI_TXDATA);
182 writeb(0, hw->base + TINY_SPI_TXDATA);
183 *rxp++ = rx;
184 }
185 tiny_spi_wait_txr(hw);
186 *rxp++ = readb(hw->base + TINY_SPI_TXDATA);
187 }
188 tiny_spi_wait_txe(hw);
189 *rxp++ = readb(hw->base + TINY_SPI_RXDATA);
190 } else if (txp) {
191 writeb(*txp++, hw->base + TINY_SPI_TXDATA);
192 if (t->len > 1) {
193 writeb(*txp++, hw->base + TINY_SPI_TXDATA);
194 for (i = 2; i < t->len; i++) {
195 u8 tx = *txp++;
196 tiny_spi_wait_txr(hw);
197 writeb(tx, hw->base + TINY_SPI_TXDATA);
198 }
199 }
200 tiny_spi_wait_txe(hw);
201 } else { 156 } else {
202 writeb(0, hw->base + TINY_SPI_TXDATA); 157 /* we need to tighten the transfer loop */
203 if (t->len > 1) { 158 writeb(txp ? *txp++ : 0, hw->base + TINY_SPI_TXDATA);
204 writeb(0, hw->base + TINY_SPI_TXDATA); 159 for (i = 1; i < t->len; i++) {
205 for (i = 2; i < t->len; i++) { 160 writeb(txp ? *txp++ : 0, hw->base + TINY_SPI_TXDATA);
161
162 if (rxp || (i != t->len - 1))
206 tiny_spi_wait_txr(hw); 163 tiny_spi_wait_txr(hw);
207 writeb(0, hw->base + TINY_SPI_TXDATA); 164 if (rxp)
208 } 165 *rxp++ = readb(hw->base + TINY_SPI_TXDATA);
209 } 166 }
210 tiny_spi_wait_txe(hw); 167 tiny_spi_wait_txe(hw);
168 if (rxp)
169 *rxp++ = readb(hw->base + TINY_SPI_RXDATA);
211 } 170 }
171
212 return t->len; 172 return t->len;
213} 173}
214 174
diff --git a/drivers/spi/spi-omap-100k.c b/drivers/spi/spi-omap-100k.c
index b6ed82beb01d..0d32054bfc0d 100644
--- a/drivers/spi/spi-omap-100k.c
+++ b/drivers/spi/spi-omap-100k.c
@@ -470,31 +470,12 @@ err:
470 return status; 470 return status;
471} 471}
472 472
473static int omap1_spi100k_remove(struct platform_device *pdev)
474{
475 struct spi_master *master;
476 struct omap1_spi100k *spi100k;
477 struct resource *r;
478 int status = 0;
479
480 master = platform_get_drvdata(pdev);
481 spi100k = spi_master_get_devdata(master);
482
483 if (status != 0)
484 return status;
485
486 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
487
488 return 0;
489}
490
491static struct platform_driver omap1_spi100k_driver = { 473static struct platform_driver omap1_spi100k_driver = {
492 .driver = { 474 .driver = {
493 .name = "omap1_spi100k", 475 .name = "omap1_spi100k",
494 .owner = THIS_MODULE, 476 .owner = THIS_MODULE,
495 }, 477 },
496 .probe = omap1_spi100k_probe, 478 .probe = omap1_spi100k_probe,
497 .remove = omap1_spi100k_remove,
498}; 479};
499 480
500module_platform_driver(omap1_spi100k_driver); 481module_platform_driver(omap1_spi100k_driver);
@@ -502,4 +483,3 @@ module_platform_driver(omap1_spi100k_driver);
502MODULE_DESCRIPTION("OMAP7xx SPI 100k controller driver"); 483MODULE_DESCRIPTION("OMAP7xx SPI 100k controller driver");
503MODULE_AUTHOR("Fabrice Crohas <fcrohas@gmail.com>"); 484MODULE_AUTHOR("Fabrice Crohas <fcrohas@gmail.com>");
504MODULE_LICENSE("GPL"); 485MODULE_LICENSE("GPL");
505
diff --git a/drivers/spi/spi-omap2-mcspi.c b/drivers/spi/spi-omap2-mcspi.c
index 443df39840bc..a72127f08e39 100644
--- a/drivers/spi/spi-omap2-mcspi.c
+++ b/drivers/spi/spi-omap2-mcspi.c
@@ -157,14 +157,14 @@ static inline void mcspi_write_reg(struct spi_master *master,
157{ 157{
158 struct omap2_mcspi *mcspi = spi_master_get_devdata(master); 158 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
159 159
160 __raw_writel(val, mcspi->base + idx); 160 writel_relaxed(val, mcspi->base + idx);
161} 161}
162 162
163static inline u32 mcspi_read_reg(struct spi_master *master, int idx) 163static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
164{ 164{
165 struct omap2_mcspi *mcspi = spi_master_get_devdata(master); 165 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
166 166
167 return __raw_readl(mcspi->base + idx); 167 return readl_relaxed(mcspi->base + idx);
168} 168}
169 169
170static inline void mcspi_write_cs_reg(const struct spi_device *spi, 170static inline void mcspi_write_cs_reg(const struct spi_device *spi,
@@ -172,14 +172,14 @@ static inline void mcspi_write_cs_reg(const struct spi_device *spi,
172{ 172{
173 struct omap2_mcspi_cs *cs = spi->controller_state; 173 struct omap2_mcspi_cs *cs = spi->controller_state;
174 174
175 __raw_writel(val, cs->base + idx); 175 writel_relaxed(val, cs->base + idx);
176} 176}
177 177
178static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx) 178static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
179{ 179{
180 struct omap2_mcspi_cs *cs = spi->controller_state; 180 struct omap2_mcspi_cs *cs = spi->controller_state;
181 181
182 return __raw_readl(cs->base + idx); 182 return readl_relaxed(cs->base + idx);
183} 183}
184 184
185static inline u32 mcspi_cached_chconf0(const struct spi_device *spi) 185static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
@@ -338,7 +338,7 @@ static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
338 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable); 338 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
339 339
340 list_for_each_entry(cs, &ctx->cs, node) 340 list_for_each_entry(cs, &ctx->cs, node)
341 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); 341 writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
342} 342}
343 343
344static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit) 344static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
@@ -346,9 +346,9 @@ static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
346 unsigned long timeout; 346 unsigned long timeout;
347 347
348 timeout = jiffies + msecs_to_jiffies(1000); 348 timeout = jiffies + msecs_to_jiffies(1000);
349 while (!(__raw_readl(reg) & bit)) { 349 while (!(readl_relaxed(reg) & bit)) {
350 if (time_after(jiffies, timeout)) { 350 if (time_after(jiffies, timeout)) {
351 if (!(__raw_readl(reg) & bit)) 351 if (!(readl_relaxed(reg) & bit))
352 return -ETIMEDOUT; 352 return -ETIMEDOUT;
353 else 353 else
354 return 0; 354 return 0;
@@ -675,7 +675,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
675 } 675 }
676 dev_vdbg(&spi->dev, "write-%d %02x\n", 676 dev_vdbg(&spi->dev, "write-%d %02x\n",
677 word_len, *tx); 677 word_len, *tx);
678 __raw_writel(*tx++, tx_reg); 678 writel_relaxed(*tx++, tx_reg);
679 } 679 }
680 if (rx != NULL) { 680 if (rx != NULL) {
681 if (mcspi_wait_for_reg_bit(chstat_reg, 681 if (mcspi_wait_for_reg_bit(chstat_reg,
@@ -687,7 +687,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
687 if (c == 1 && tx == NULL && 687 if (c == 1 && tx == NULL &&
688 (l & OMAP2_MCSPI_CHCONF_TURBO)) { 688 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
689 omap2_mcspi_set_enable(spi, 0); 689 omap2_mcspi_set_enable(spi, 0);
690 *rx++ = __raw_readl(rx_reg); 690 *rx++ = readl_relaxed(rx_reg);
691 dev_vdbg(&spi->dev, "read-%d %02x\n", 691 dev_vdbg(&spi->dev, "read-%d %02x\n",
692 word_len, *(rx - 1)); 692 word_len, *(rx - 1));
693 if (mcspi_wait_for_reg_bit(chstat_reg, 693 if (mcspi_wait_for_reg_bit(chstat_reg,
@@ -701,7 +701,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
701 omap2_mcspi_set_enable(spi, 0); 701 omap2_mcspi_set_enable(spi, 0);
702 } 702 }
703 703
704 *rx++ = __raw_readl(rx_reg); 704 *rx++ = readl_relaxed(rx_reg);
705 dev_vdbg(&spi->dev, "read-%d %02x\n", 705 dev_vdbg(&spi->dev, "read-%d %02x\n",
706 word_len, *(rx - 1)); 706 word_len, *(rx - 1));
707 } 707 }
@@ -722,7 +722,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
722 } 722 }
723 dev_vdbg(&spi->dev, "write-%d %04x\n", 723 dev_vdbg(&spi->dev, "write-%d %04x\n",
724 word_len, *tx); 724 word_len, *tx);
725 __raw_writel(*tx++, tx_reg); 725 writel_relaxed(*tx++, tx_reg);
726 } 726 }
727 if (rx != NULL) { 727 if (rx != NULL) {
728 if (mcspi_wait_for_reg_bit(chstat_reg, 728 if (mcspi_wait_for_reg_bit(chstat_reg,
@@ -734,7 +734,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
734 if (c == 2 && tx == NULL && 734 if (c == 2 && tx == NULL &&
735 (l & OMAP2_MCSPI_CHCONF_TURBO)) { 735 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
736 omap2_mcspi_set_enable(spi, 0); 736 omap2_mcspi_set_enable(spi, 0);
737 *rx++ = __raw_readl(rx_reg); 737 *rx++ = readl_relaxed(rx_reg);
738 dev_vdbg(&spi->dev, "read-%d %04x\n", 738 dev_vdbg(&spi->dev, "read-%d %04x\n",
739 word_len, *(rx - 1)); 739 word_len, *(rx - 1));
740 if (mcspi_wait_for_reg_bit(chstat_reg, 740 if (mcspi_wait_for_reg_bit(chstat_reg,
@@ -748,7 +748,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
748 omap2_mcspi_set_enable(spi, 0); 748 omap2_mcspi_set_enable(spi, 0);
749 } 749 }
750 750
751 *rx++ = __raw_readl(rx_reg); 751 *rx++ = readl_relaxed(rx_reg);
752 dev_vdbg(&spi->dev, "read-%d %04x\n", 752 dev_vdbg(&spi->dev, "read-%d %04x\n",
753 word_len, *(rx - 1)); 753 word_len, *(rx - 1));
754 } 754 }
@@ -769,7 +769,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
769 } 769 }
770 dev_vdbg(&spi->dev, "write-%d %08x\n", 770 dev_vdbg(&spi->dev, "write-%d %08x\n",
771 word_len, *tx); 771 word_len, *tx);
772 __raw_writel(*tx++, tx_reg); 772 writel_relaxed(*tx++, tx_reg);
773 } 773 }
774 if (rx != NULL) { 774 if (rx != NULL) {
775 if (mcspi_wait_for_reg_bit(chstat_reg, 775 if (mcspi_wait_for_reg_bit(chstat_reg,
@@ -781,7 +781,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
781 if (c == 4 && tx == NULL && 781 if (c == 4 && tx == NULL &&
782 (l & OMAP2_MCSPI_CHCONF_TURBO)) { 782 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
783 omap2_mcspi_set_enable(spi, 0); 783 omap2_mcspi_set_enable(spi, 0);
784 *rx++ = __raw_readl(rx_reg); 784 *rx++ = readl_relaxed(rx_reg);
785 dev_vdbg(&spi->dev, "read-%d %08x\n", 785 dev_vdbg(&spi->dev, "read-%d %08x\n",
786 word_len, *(rx - 1)); 786 word_len, *(rx - 1));
787 if (mcspi_wait_for_reg_bit(chstat_reg, 787 if (mcspi_wait_for_reg_bit(chstat_reg,
@@ -795,7 +795,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
795 omap2_mcspi_set_enable(spi, 0); 795 omap2_mcspi_set_enable(spi, 0);
796 } 796 }
797 797
798 *rx++ = __raw_readl(rx_reg); 798 *rx++ = readl_relaxed(rx_reg);
799 dev_vdbg(&spi->dev, "read-%d %08x\n", 799 dev_vdbg(&spi->dev, "read-%d %08x\n",
800 word_len, *(rx - 1)); 800 word_len, *(rx - 1));
801 } 801 }
@@ -1107,7 +1107,7 @@ static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m)
1107 1107
1108 /* RX_ONLY mode needs dummy data in TX reg */ 1108 /* RX_ONLY mode needs dummy data in TX reg */
1109 if (t->tx_buf == NULL) 1109 if (t->tx_buf == NULL)
1110 __raw_writel(0, cs->base 1110 writel_relaxed(0, cs->base
1111 + OMAP2_MCSPI_TX0); 1111 + OMAP2_MCSPI_TX0);
1112 1112
1113 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && 1113 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
@@ -1470,9 +1470,9 @@ static int omap2_mcspi_resume(struct device *dev)
1470 * change in account. 1470 * change in account.
1471 */ 1471 */
1472 cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE; 1472 cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE;
1473 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); 1473 writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1474 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE; 1474 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1475 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); 1475 writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1476 } 1476 }
1477 } 1477 }
1478 pm_runtime_mark_last_busy(mcspi->dev); 1478 pm_runtime_mark_last_busy(mcspi->dev);
diff --git a/drivers/spi/spi-orion.c b/drivers/spi/spi-orion.c
index 744841e095e4..7f2121fe2622 100644
--- a/drivers/spi/spi-orion.c
+++ b/drivers/spi/spi-orion.c
@@ -434,7 +434,7 @@ static int orion_spi_probe(struct platform_device *pdev)
434 spi = spi_master_get_devdata(master); 434 spi = spi_master_get_devdata(master);
435 spi->master = master; 435 spi->master = master;
436 436
437 spi->clk = clk_get(&pdev->dev, NULL); 437 spi->clk = devm_clk_get(&pdev->dev, NULL);
438 if (IS_ERR(spi->clk)) { 438 if (IS_ERR(spi->clk)) {
439 status = PTR_ERR(spi->clk); 439 status = PTR_ERR(spi->clk);
440 goto out; 440 goto out;
@@ -465,7 +465,6 @@ static int orion_spi_probe(struct platform_device *pdev)
465 465
466out_rel_clk: 466out_rel_clk:
467 clk_disable_unprepare(spi->clk); 467 clk_disable_unprepare(spi->clk);
468 clk_put(spi->clk);
469out: 468out:
470 spi_master_put(master); 469 spi_master_put(master);
471 return status; 470 return status;
@@ -481,7 +480,6 @@ static int orion_spi_remove(struct platform_device *pdev)
481 spi = spi_master_get_devdata(master); 480 spi = spi_master_get_devdata(master);
482 481
483 clk_disable_unprepare(spi->clk); 482 clk_disable_unprepare(spi->clk);
484 clk_put(spi->clk);
485 483
486 return 0; 484 return 0;
487} 485}
diff --git a/drivers/spi/spi-pxa2xx-pci.c b/drivers/spi/spi-pxa2xx-pci.c
index 74bc18775658..3f006d3ed2a8 100644
--- a/drivers/spi/spi-pxa2xx-pci.c
+++ b/drivers/spi/spi-pxa2xx-pci.c
@@ -62,7 +62,7 @@ static void ce4100_spi_remove(struct pci_dev *dev)
62 platform_device_unregister(pdev); 62 platform_device_unregister(pdev);
63} 63}
64 64
65static DEFINE_PCI_DEVICE_TABLE(ce4100_spi_devices) = { 65static const struct pci_device_id ce4100_spi_devices[] = {
66 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2e6a) }, 66 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2e6a) },
67 { }, 67 { },
68}; 68};
diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
index 7765b1999537..c702fc536a77 100644
--- a/drivers/spi/spi-pxa2xx.c
+++ b/drivers/spi/spi-pxa2xx.c
@@ -1066,6 +1066,8 @@ pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev)
1066 1066
1067 pdata->num_chipselect = 1; 1067 pdata->num_chipselect = 1;
1068 pdata->enable_dma = true; 1068 pdata->enable_dma = true;
1069 pdata->tx_chan_id = -1;
1070 pdata->rx_chan_id = -1;
1069 1071
1070 return pdata; 1072 return pdata;
1071} 1073}
@@ -1266,7 +1268,7 @@ static void pxa2xx_spi_shutdown(struct platform_device *pdev)
1266 dev_err(&pdev->dev, "shutdown failed with %d\n", status); 1268 dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1267} 1269}
1268 1270
1269#ifdef CONFIG_PM 1271#ifdef CONFIG_PM_SLEEP
1270static int pxa2xx_spi_suspend(struct device *dev) 1272static int pxa2xx_spi_suspend(struct device *dev)
1271{ 1273{
1272 struct driver_data *drv_data = dev_get_drvdata(dev); 1274 struct driver_data *drv_data = dev_get_drvdata(dev);
diff --git a/drivers/spi/spi-rspi.c b/drivers/spi/spi-rspi.c
index 9e829cee7357..28987d9fcfe5 100644
--- a/drivers/spi/spi-rspi.c
+++ b/drivers/spi/spi-rspi.c
@@ -37,117 +37,145 @@
37#include <linux/spi/spi.h> 37#include <linux/spi/spi.h>
38#include <linux/spi/rspi.h> 38#include <linux/spi/rspi.h>
39 39
40#define RSPI_SPCR 0x00 40#define RSPI_SPCR 0x00 /* Control Register */
41#define RSPI_SSLP 0x01 41#define RSPI_SSLP 0x01 /* Slave Select Polarity Register */
42#define RSPI_SPPCR 0x02 42#define RSPI_SPPCR 0x02 /* Pin Control Register */
43#define RSPI_SPSR 0x03 43#define RSPI_SPSR 0x03 /* Status Register */
44#define RSPI_SPDR 0x04 44#define RSPI_SPDR 0x04 /* Data Register */
45#define RSPI_SPSCR 0x08 45#define RSPI_SPSCR 0x08 /* Sequence Control Register */
46#define RSPI_SPSSR 0x09 46#define RSPI_SPSSR 0x09 /* Sequence Status Register */
47#define RSPI_SPBR 0x0a 47#define RSPI_SPBR 0x0a /* Bit Rate Register */
48#define RSPI_SPDCR 0x0b 48#define RSPI_SPDCR 0x0b /* Data Control Register */
49#define RSPI_SPCKD 0x0c 49#define RSPI_SPCKD 0x0c /* Clock Delay Register */
50#define RSPI_SSLND 0x0d 50#define RSPI_SSLND 0x0d /* Slave Select Negation Delay Register */
51#define RSPI_SPND 0x0e 51#define RSPI_SPND 0x0e /* Next-Access Delay Register */
52#define RSPI_SPCR2 0x0f 52#define RSPI_SPCR2 0x0f /* Control Register 2 */
53#define RSPI_SPCMD0 0x10 53#define RSPI_SPCMD0 0x10 /* Command Register 0 */
54#define RSPI_SPCMD1 0x12 54#define RSPI_SPCMD1 0x12 /* Command Register 1 */
55#define RSPI_SPCMD2 0x14 55#define RSPI_SPCMD2 0x14 /* Command Register 2 */
56#define RSPI_SPCMD3 0x16 56#define RSPI_SPCMD3 0x16 /* Command Register 3 */
57#define RSPI_SPCMD4 0x18 57#define RSPI_SPCMD4 0x18 /* Command Register 4 */
58#define RSPI_SPCMD5 0x1a 58#define RSPI_SPCMD5 0x1a /* Command Register 5 */
59#define RSPI_SPCMD6 0x1c 59#define RSPI_SPCMD6 0x1c /* Command Register 6 */
60#define RSPI_SPCMD7 0x1e 60#define RSPI_SPCMD7 0x1e /* Command Register 7 */
61#define RSPI_SPBFCR 0x20 /* Buffer Control Register */
62#define RSPI_SPBFDR 0x22 /* Buffer Data Count Setting Register */
61 63
62/*qspi only */ 64/*qspi only */
63#define QSPI_SPBFCR 0x18 65#define QSPI_SPBFCR 0x18 /* Buffer Control Register */
64#define QSPI_SPBDCR 0x1a 66#define QSPI_SPBDCR 0x1a /* Buffer Data Count Register */
65#define QSPI_SPBMUL0 0x1c 67#define QSPI_SPBMUL0 0x1c /* Transfer Data Length Multiplier Setting Register 0 */
66#define QSPI_SPBMUL1 0x20 68#define QSPI_SPBMUL1 0x20 /* Transfer Data Length Multiplier Setting Register 1 */
67#define QSPI_SPBMUL2 0x24 69#define QSPI_SPBMUL2 0x24 /* Transfer Data Length Multiplier Setting Register 2 */
68#define QSPI_SPBMUL3 0x28 70#define QSPI_SPBMUL3 0x28 /* Transfer Data Length Multiplier Setting Register 3 */
69 71
70/* SPCR */ 72/* SPCR - Control Register */
71#define SPCR_SPRIE 0x80 73#define SPCR_SPRIE 0x80 /* Receive Interrupt Enable */
72#define SPCR_SPE 0x40 74#define SPCR_SPE 0x40 /* Function Enable */
73#define SPCR_SPTIE 0x20 75#define SPCR_SPTIE 0x20 /* Transmit Interrupt Enable */
74#define SPCR_SPEIE 0x10 76#define SPCR_SPEIE 0x10 /* Error Interrupt Enable */
75#define SPCR_MSTR 0x08 77#define SPCR_MSTR 0x08 /* Master/Slave Mode Select */
76#define SPCR_MODFEN 0x04 78#define SPCR_MODFEN 0x04 /* Mode Fault Error Detection Enable */
77#define SPCR_TXMD 0x02 79/* RSPI on SH only */
78#define SPCR_SPMS 0x01 80#define SPCR_TXMD 0x02 /* TX Only Mode (vs. Full Duplex) */
79 81#define SPCR_SPMS 0x01 /* 3-wire Mode (vs. 4-wire) */
80/* SSLP */ 82/* QSPI on R-Car M2 only */
81#define SSLP_SSL1P 0x02 83#define SPCR_WSWAP 0x02 /* Word Swap of read-data for DMAC */
82#define SSLP_SSL0P 0x01 84#define SPCR_BSWAP 0x01 /* Byte Swap of read-data for DMAC */
83 85
84/* SPPCR */ 86/* SSLP - Slave Select Polarity Register */
85#define SPPCR_MOIFE 0x20 87#define SSLP_SSL1P 0x02 /* SSL1 Signal Polarity Setting */
86#define SPPCR_MOIFV 0x10 88#define SSLP_SSL0P 0x01 /* SSL0 Signal Polarity Setting */
89
90/* SPPCR - Pin Control Register */
91#define SPPCR_MOIFE 0x20 /* MOSI Idle Value Fixing Enable */
92#define SPPCR_MOIFV 0x10 /* MOSI Idle Fixed Value */
87#define SPPCR_SPOM 0x04 93#define SPPCR_SPOM 0x04
88#define SPPCR_SPLP2 0x02 94#define SPPCR_SPLP2 0x02 /* Loopback Mode 2 (non-inverting) */
89#define SPPCR_SPLP 0x01 95#define SPPCR_SPLP 0x01 /* Loopback Mode (inverting) */
90 96
91/* SPSR */ 97#define SPPCR_IO3FV 0x04 /* Single-/Dual-SPI Mode IO3 Output Fixed Value */
92#define SPSR_SPRF 0x80 98#define SPPCR_IO2FV 0x04 /* Single-/Dual-SPI Mode IO2 Output Fixed Value */
93#define SPSR_SPTEF 0x20 99
94#define SPSR_PERF 0x08 100/* SPSR - Status Register */
95#define SPSR_MODF 0x04 101#define SPSR_SPRF 0x80 /* Receive Buffer Full Flag */
96#define SPSR_IDLNF 0x02 102#define SPSR_TEND 0x40 /* Transmit End */
97#define SPSR_OVRF 0x01 103#define SPSR_SPTEF 0x20 /* Transmit Buffer Empty Flag */
98 104#define SPSR_PERF 0x08 /* Parity Error Flag */
99/* SPSCR */ 105#define SPSR_MODF 0x04 /* Mode Fault Error Flag */
100#define SPSCR_SPSLN_MASK 0x07 106#define SPSR_IDLNF 0x02 /* RSPI Idle Flag */
101 107#define SPSR_OVRF 0x01 /* Overrun Error Flag */
102/* SPSSR */ 108
103#define SPSSR_SPECM_MASK 0x70 109/* SPSCR - Sequence Control Register */
104#define SPSSR_SPCP_MASK 0x07 110#define SPSCR_SPSLN_MASK 0x07 /* Sequence Length Specification */
105 111
106/* SPDCR */ 112/* SPSSR - Sequence Status Register */
107#define SPDCR_SPLW 0x20 113#define SPSSR_SPECM_MASK 0x70 /* Command Error Mask */
108#define SPDCR_SPRDTD 0x10 114#define SPSSR_SPCP_MASK 0x07 /* Command Pointer Mask */
115
116/* SPDCR - Data Control Register */
117#define SPDCR_TXDMY 0x80 /* Dummy Data Transmission Enable */
118#define SPDCR_SPLW1 0x40 /* Access Width Specification (RZ) */
119#define SPDCR_SPLW0 0x20 /* Access Width Specification (RZ) */
120#define SPDCR_SPLLWORD (SPDCR_SPLW1 | SPDCR_SPLW0)
121#define SPDCR_SPLWORD SPDCR_SPLW1
122#define SPDCR_SPLBYTE SPDCR_SPLW0
123#define SPDCR_SPLW 0x20 /* Access Width Specification (SH) */
124#define SPDCR_SPRDTD 0x10 /* Receive Transmit Data Select */
109#define SPDCR_SLSEL1 0x08 125#define SPDCR_SLSEL1 0x08
110#define SPDCR_SLSEL0 0x04 126#define SPDCR_SLSEL0 0x04
111#define SPDCR_SLSEL_MASK 0x0c 127#define SPDCR_SLSEL_MASK 0x0c /* SSL1 Output Select */
112#define SPDCR_SPFC1 0x02 128#define SPDCR_SPFC1 0x02
113#define SPDCR_SPFC0 0x01 129#define SPDCR_SPFC0 0x01
130#define SPDCR_SPFC_MASK 0x03 /* Frame Count Setting (1-4) */
114 131
115/* SPCKD */ 132/* SPCKD - Clock Delay Register */
116#define SPCKD_SCKDL_MASK 0x07 133#define SPCKD_SCKDL_MASK 0x07 /* Clock Delay Setting (1-8) */
117 134
118/* SSLND */ 135/* SSLND - Slave Select Negation Delay Register */
119#define SSLND_SLNDL_MASK 0x07 136#define SSLND_SLNDL_MASK 0x07 /* SSL Negation Delay Setting (1-8) */
120 137
121/* SPND */ 138/* SPND - Next-Access Delay Register */
122#define SPND_SPNDL_MASK 0x07 139#define SPND_SPNDL_MASK 0x07 /* Next-Access Delay Setting (1-8) */
123 140
124/* SPCR2 */ 141/* SPCR2 - Control Register 2 */
125#define SPCR2_PTE 0x08 142#define SPCR2_PTE 0x08 /* Parity Self-Test Enable */
126#define SPCR2_SPIE 0x04 143#define SPCR2_SPIE 0x04 /* Idle Interrupt Enable */
127#define SPCR2_SPOE 0x02 144#define SPCR2_SPOE 0x02 /* Odd Parity Enable (vs. Even) */
128#define SPCR2_SPPE 0x01 145#define SPCR2_SPPE 0x01 /* Parity Enable */
129 146
130/* SPCMDn */ 147/* SPCMDn - Command Registers */
131#define SPCMD_SCKDEN 0x8000 148#define SPCMD_SCKDEN 0x8000 /* Clock Delay Setting Enable */
132#define SPCMD_SLNDEN 0x4000 149#define SPCMD_SLNDEN 0x4000 /* SSL Negation Delay Setting Enable */
133#define SPCMD_SPNDEN 0x2000 150#define SPCMD_SPNDEN 0x2000 /* Next-Access Delay Enable */
134#define SPCMD_LSBF 0x1000 151#define SPCMD_LSBF 0x1000 /* LSB First */
135#define SPCMD_SPB_MASK 0x0f00 152#define SPCMD_SPB_MASK 0x0f00 /* Data Length Setting */
136#define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK) 153#define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK)
137#define SPCMD_SPB_8BIT 0x0000 /* qspi only */ 154#define SPCMD_SPB_8BIT 0x0000 /* qspi only */
138#define SPCMD_SPB_16BIT 0x0100 155#define SPCMD_SPB_16BIT 0x0100
139#define SPCMD_SPB_20BIT 0x0000 156#define SPCMD_SPB_20BIT 0x0000
140#define SPCMD_SPB_24BIT 0x0100 157#define SPCMD_SPB_24BIT 0x0100
141#define SPCMD_SPB_32BIT 0x0200 158#define SPCMD_SPB_32BIT 0x0200
142#define SPCMD_SSLKP 0x0080 159#define SPCMD_SSLKP 0x0080 /* SSL Signal Level Keeping */
143#define SPCMD_SSLA_MASK 0x0030 160#define SPCMD_SPIMOD_MASK 0x0060 /* SPI Operating Mode (QSPI only) */
144#define SPCMD_BRDV_MASK 0x000c 161#define SPCMD_SPIMOD1 0x0040
145#define SPCMD_CPOL 0x0002 162#define SPCMD_SPIMOD0 0x0020
146#define SPCMD_CPHA 0x0001 163#define SPCMD_SPIMOD_SINGLE 0
147 164#define SPCMD_SPIMOD_DUAL SPCMD_SPIMOD0
148/* SPBFCR */ 165#define SPCMD_SPIMOD_QUAD SPCMD_SPIMOD1
149#define SPBFCR_TXRST 0x80 /* qspi only */ 166#define SPCMD_SPRW 0x0010 /* SPI Read/Write Access (Dual/Quad) */
150#define SPBFCR_RXRST 0x40 /* qspi only */ 167#define SPCMD_SSLA_MASK 0x0030 /* SSL Assert Signal Setting (RSPI) */
168#define SPCMD_BRDV_MASK 0x000c /* Bit Rate Division Setting */
169#define SPCMD_CPOL 0x0002 /* Clock Polarity Setting */
170#define SPCMD_CPHA 0x0001 /* Clock Phase Setting */
171
172/* SPBFCR - Buffer Control Register */
173#define SPBFCR_TXRST 0x80 /* Transmit Buffer Data Reset (qspi only) */
174#define SPBFCR_RXRST 0x40 /* Receive Buffer Data Reset (qspi only) */
175#define SPBFCR_TXTRG_MASK 0x30 /* Transmit Buffer Data Triggering Number */
176#define SPBFCR_RXTRG_MASK 0x07 /* Receive Buffer Data Triggering Number */
177
178#define DUMMY_DATA 0x00
151 179
152struct rspi_data { 180struct rspi_data {
153 void __iomem *addr; 181 void __iomem *addr;
@@ -158,7 +186,8 @@ struct rspi_data {
158 wait_queue_head_t wait; 186 wait_queue_head_t wait;
159 spinlock_t lock; 187 spinlock_t lock;
160 struct clk *clk; 188 struct clk *clk;
161 unsigned char spsr; 189 u8 spsr;
190 u16 spcmd;
162 const struct spi_ops *ops; 191 const struct spi_ops *ops;
163 192
164 /* for dmaengine */ 193 /* for dmaengine */
@@ -170,34 +199,35 @@ struct rspi_data {
170 unsigned dma_callbacked:1; 199 unsigned dma_callbacked:1;
171}; 200};
172 201
173static void rspi_write8(struct rspi_data *rspi, u8 data, u16 offset) 202static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset)
174{ 203{
175 iowrite8(data, rspi->addr + offset); 204 iowrite8(data, rspi->addr + offset);
176} 205}
177 206
178static void rspi_write16(struct rspi_data *rspi, u16 data, u16 offset) 207static void rspi_write16(const struct rspi_data *rspi, u16 data, u16 offset)
179{ 208{
180 iowrite16(data, rspi->addr + offset); 209 iowrite16(data, rspi->addr + offset);
181} 210}
182 211
183static void rspi_write32(struct rspi_data *rspi, u32 data, u16 offset) 212static void rspi_write32(const struct rspi_data *rspi, u32 data, u16 offset)
184{ 213{
185 iowrite32(data, rspi->addr + offset); 214 iowrite32(data, rspi->addr + offset);
186} 215}
187 216
188static u8 rspi_read8(struct rspi_data *rspi, u16 offset) 217static u8 rspi_read8(const struct rspi_data *rspi, u16 offset)
189{ 218{
190 return ioread8(rspi->addr + offset); 219 return ioread8(rspi->addr + offset);
191} 220}
192 221
193static u16 rspi_read16(struct rspi_data *rspi, u16 offset) 222static u16 rspi_read16(const struct rspi_data *rspi, u16 offset)
194{ 223{
195 return ioread16(rspi->addr + offset); 224 return ioread16(rspi->addr + offset);
196} 225}
197 226
198/* optional functions */ 227/* optional functions */
199struct spi_ops { 228struct spi_ops {
200 int (*set_config_register)(struct rspi_data *rspi, int access_size); 229 int (*set_config_register)(const struct rspi_data *rspi,
230 int access_size);
201 int (*send_pio)(struct rspi_data *rspi, struct spi_message *mesg, 231 int (*send_pio)(struct rspi_data *rspi, struct spi_message *mesg,
202 struct spi_transfer *t); 232 struct spi_transfer *t);
203 int (*receive_pio)(struct rspi_data *rspi, struct spi_message *mesg, 233 int (*receive_pio)(struct rspi_data *rspi, struct spi_message *mesg,
@@ -208,7 +238,8 @@ struct spi_ops {
208/* 238/*
209 * functions for RSPI 239 * functions for RSPI
210 */ 240 */
211static int rspi_set_config_register(struct rspi_data *rspi, int access_size) 241static int rspi_set_config_register(const struct rspi_data *rspi,
242 int access_size)
212{ 243{
213 int spbr; 244 int spbr;
214 245
@@ -231,7 +262,7 @@ static int rspi_set_config_register(struct rspi_data *rspi, int access_size)
231 rspi_write8(rspi, 0x00, RSPI_SPCR2); 262 rspi_write8(rspi, 0x00, RSPI_SPCR2);
232 263
233 /* Sets SPCMD */ 264 /* Sets SPCMD */
234 rspi_write16(rspi, SPCMD_SPB_8_TO_16(access_size) | SPCMD_SSLKP, 265 rspi_write16(rspi, SPCMD_SPB_8_TO_16(access_size) | rspi->spcmd,
235 RSPI_SPCMD0); 266 RSPI_SPCMD0);
236 267
237 /* Sets RSPI mode */ 268 /* Sets RSPI mode */
@@ -243,7 +274,8 @@ static int rspi_set_config_register(struct rspi_data *rspi, int access_size)
243/* 274/*
244 * functions for QSPI 275 * functions for QSPI
245 */ 276 */
246static int qspi_set_config_register(struct rspi_data *rspi, int access_size) 277static int qspi_set_config_register(const struct rspi_data *rspi,
278 int access_size)
247{ 279{
248 u16 spcmd; 280 u16 spcmd;
249 int spbr; 281 int spbr;
@@ -268,10 +300,10 @@ static int qspi_set_config_register(struct rspi_data *rspi, int access_size)
268 spcmd = SPCMD_SPB_8BIT; 300 spcmd = SPCMD_SPB_8BIT;
269 else if (access_size == 16) 301 else if (access_size == 16)
270 spcmd = SPCMD_SPB_16BIT; 302 spcmd = SPCMD_SPB_16BIT;
271 else if (access_size == 32) 303 else
272 spcmd = SPCMD_SPB_32BIT; 304 spcmd = SPCMD_SPB_32BIT;
273 305
274 spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | SPCMD_SSLKP | SPCMD_SPNDEN; 306 spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | rspi->spcmd | SPCMD_SPNDEN;
275 307
276 /* Resets transfer data length */ 308 /* Resets transfer data length */
277 rspi_write32(rspi, 0, QSPI_SPBMUL0); 309 rspi_write32(rspi, 0, QSPI_SPBMUL0);
@@ -292,12 +324,12 @@ static int qspi_set_config_register(struct rspi_data *rspi, int access_size)
292 324
293#define set_config_register(spi, n) spi->ops->set_config_register(spi, n) 325#define set_config_register(spi, n) spi->ops->set_config_register(spi, n)
294 326
295static void rspi_enable_irq(struct rspi_data *rspi, u8 enable) 327static void rspi_enable_irq(const struct rspi_data *rspi, u8 enable)
296{ 328{
297 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR); 329 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR);
298} 330}
299 331
300static void rspi_disable_irq(struct rspi_data *rspi, u8 disable) 332static void rspi_disable_irq(const struct rspi_data *rspi, u8 disable)
301{ 333{
302 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR); 334 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR);
303} 335}
@@ -316,12 +348,12 @@ static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask,
316 return 0; 348 return 0;
317} 349}
318 350
319static void rspi_assert_ssl(struct rspi_data *rspi) 351static void rspi_assert_ssl(const struct rspi_data *rspi)
320{ 352{
321 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR); 353 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR);
322} 354}
323 355
324static void rspi_negate_ssl(struct rspi_data *rspi) 356static void rspi_negate_ssl(const struct rspi_data *rspi)
325{ 357{
326 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR); 358 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR);
327} 359}
@@ -330,9 +362,7 @@ static int rspi_send_pio(struct rspi_data *rspi, struct spi_message *mesg,
330 struct spi_transfer *t) 362 struct spi_transfer *t)
331{ 363{
332 int remain = t->len; 364 int remain = t->len;
333 u8 *data; 365 const u8 *data = t->tx_buf;
334
335 data = (u8 *)t->tx_buf;
336 while (remain > 0) { 366 while (remain > 0) {
337 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_TXMD, 367 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_TXMD,
338 RSPI_SPCR); 368 RSPI_SPCR);
@@ -348,7 +378,7 @@ static int rspi_send_pio(struct rspi_data *rspi, struct spi_message *mesg,
348 remain--; 378 remain--;
349 } 379 }
350 380
351 /* Waiting for the last transmition */ 381 /* Waiting for the last transmission */
352 rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE); 382 rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
353 383
354 return 0; 384 return 0;
@@ -358,12 +388,11 @@ static int qspi_send_pio(struct rspi_data *rspi, struct spi_message *mesg,
358 struct spi_transfer *t) 388 struct spi_transfer *t)
359{ 389{
360 int remain = t->len; 390 int remain = t->len;
361 u8 *data; 391 const u8 *data = t->tx_buf;
362 392
363 rspi_write8(rspi, SPBFCR_TXRST, QSPI_SPBFCR); 393 rspi_write8(rspi, SPBFCR_TXRST, QSPI_SPBFCR);
364 rspi_write8(rspi, 0x00, QSPI_SPBFCR); 394 rspi_write8(rspi, 0x00, QSPI_SPBFCR);
365 395
366 data = (u8 *)t->tx_buf;
367 while (remain > 0) { 396 while (remain > 0) {
368 397
369 if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) { 398 if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) {
@@ -383,7 +412,7 @@ static int qspi_send_pio(struct rspi_data *rspi, struct spi_message *mesg,
383 remain--; 412 remain--;
384 } 413 }
385 414
386 /* Waiting for the last transmition */ 415 /* Waiting for the last transmission */
387 rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE); 416 rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
388 417
389 return 0; 418 return 0;
@@ -399,8 +428,8 @@ static void rspi_dma_complete(void *arg)
399 wake_up_interruptible(&rspi->wait); 428 wake_up_interruptible(&rspi->wait);
400} 429}
401 430
402static int rspi_dma_map_sg(struct scatterlist *sg, void *buf, unsigned len, 431static int rspi_dma_map_sg(struct scatterlist *sg, const void *buf,
403 struct dma_chan *chan, 432 unsigned len, struct dma_chan *chan,
404 enum dma_transfer_direction dir) 433 enum dma_transfer_direction dir)
405{ 434{
406 sg_init_table(sg, 1); 435 sg_init_table(sg, 1);
@@ -440,12 +469,13 @@ static void rspi_memory_from_8bit(void *buf, const void *data, unsigned len)
440static int rspi_send_dma(struct rspi_data *rspi, struct spi_transfer *t) 469static int rspi_send_dma(struct rspi_data *rspi, struct spi_transfer *t)
441{ 470{
442 struct scatterlist sg; 471 struct scatterlist sg;
443 void *buf = NULL; 472 const void *buf = NULL;
444 struct dma_async_tx_descriptor *desc; 473 struct dma_async_tx_descriptor *desc;
445 unsigned len; 474 unsigned len;
446 int ret = 0; 475 int ret = 0;
447 476
448 if (rspi->dma_width_16bit) { 477 if (rspi->dma_width_16bit) {
478 void *tmp;
449 /* 479 /*
450 * If DMAC bus width is 16-bit, the driver allocates a dummy 480 * If DMAC bus width is 16-bit, the driver allocates a dummy
451 * buffer. And, the driver converts original data into the 481 * buffer. And, the driver converts original data into the
@@ -454,13 +484,14 @@ static int rspi_send_dma(struct rspi_data *rspi, struct spi_transfer *t)
454 * DMAC data: 1st byte, dummy, 2nd byte, dummy ... 484 * DMAC data: 1st byte, dummy, 2nd byte, dummy ...
455 */ 485 */
456 len = t->len * 2; 486 len = t->len * 2;
457 buf = kmalloc(len, GFP_KERNEL); 487 tmp = kmalloc(len, GFP_KERNEL);
458 if (!buf) 488 if (!tmp)
459 return -ENOMEM; 489 return -ENOMEM;
460 rspi_memory_to_8bit(buf, t->tx_buf, t->len); 490 rspi_memory_to_8bit(tmp, t->tx_buf, t->len);
491 buf = tmp;
461 } else { 492 } else {
462 len = t->len; 493 len = t->len;
463 buf = (void *)t->tx_buf; 494 buf = t->tx_buf;
464 } 495 }
465 496
466 if (!rspi_dma_map_sg(&sg, buf, len, rspi->chan_tx, DMA_TO_DEVICE)) { 497 if (!rspi_dma_map_sg(&sg, buf, len, rspi->chan_tx, DMA_TO_DEVICE)) {
@@ -508,16 +539,16 @@ end_nomap:
508 return ret; 539 return ret;
509} 540}
510 541
511static void rspi_receive_init(struct rspi_data *rspi) 542static void rspi_receive_init(const struct rspi_data *rspi)
512{ 543{
513 unsigned char spsr; 544 u8 spsr;
514 545
515 spsr = rspi_read8(rspi, RSPI_SPSR); 546 spsr = rspi_read8(rspi, RSPI_SPSR);
516 if (spsr & SPSR_SPRF) 547 if (spsr & SPSR_SPRF)
517 rspi_read16(rspi, RSPI_SPDR); /* dummy read */ 548 rspi_read16(rspi, RSPI_SPDR); /* dummy read */
518 if (spsr & SPSR_OVRF) 549 if (spsr & SPSR_OVRF)
519 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF, 550 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF,
520 RSPI_SPCR); 551 RSPI_SPSR);
521} 552}
522 553
523static int rspi_receive_pio(struct rspi_data *rspi, struct spi_message *mesg, 554static int rspi_receive_pio(struct rspi_data *rspi, struct spi_message *mesg,
@@ -528,7 +559,7 @@ static int rspi_receive_pio(struct rspi_data *rspi, struct spi_message *mesg,
528 559
529 rspi_receive_init(rspi); 560 rspi_receive_init(rspi);
530 561
531 data = (u8 *)t->rx_buf; 562 data = t->rx_buf;
532 while (remain > 0) { 563 while (remain > 0) {
533 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_TXMD, 564 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_TXMD,
534 RSPI_SPCR); 565 RSPI_SPCR);
@@ -539,7 +570,7 @@ static int rspi_receive_pio(struct rspi_data *rspi, struct spi_message *mesg,
539 return -ETIMEDOUT; 570 return -ETIMEDOUT;
540 } 571 }
541 /* dummy write for generate clock */ 572 /* dummy write for generate clock */
542 rspi_write16(rspi, 0x00, RSPI_SPDR); 573 rspi_write16(rspi, DUMMY_DATA, RSPI_SPDR);
543 574
544 if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) { 575 if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) {
545 dev_err(&rspi->master->dev, 576 dev_err(&rspi->master->dev,
@@ -556,9 +587,9 @@ static int rspi_receive_pio(struct rspi_data *rspi, struct spi_message *mesg,
556 return 0; 587 return 0;
557} 588}
558 589
559static void qspi_receive_init(struct rspi_data *rspi) 590static void qspi_receive_init(const struct rspi_data *rspi)
560{ 591{
561 unsigned char spsr; 592 u8 spsr;
562 593
563 spsr = rspi_read8(rspi, RSPI_SPSR); 594 spsr = rspi_read8(rspi, RSPI_SPSR);
564 if (spsr & SPSR_SPRF) 595 if (spsr & SPSR_SPRF)
@@ -575,7 +606,7 @@ static int qspi_receive_pio(struct rspi_data *rspi, struct spi_message *mesg,
575 606
576 qspi_receive_init(rspi); 607 qspi_receive_init(rspi);
577 608
578 data = (u8 *)t->rx_buf; 609 data = t->rx_buf;
579 while (remain > 0) { 610 while (remain > 0) {
580 611
581 if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) { 612 if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) {
@@ -584,7 +615,7 @@ static int qspi_receive_pio(struct rspi_data *rspi, struct spi_message *mesg,
584 return -ETIMEDOUT; 615 return -ETIMEDOUT;
585 } 616 }
586 /* dummy write for generate clock */ 617 /* dummy write for generate clock */
587 rspi_write8(rspi, 0x00, RSPI_SPDR); 618 rspi_write8(rspi, DUMMY_DATA, RSPI_SPDR);
588 619
589 if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) { 620 if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) {
590 dev_err(&rspi->master->dev, 621 dev_err(&rspi->master->dev,
@@ -704,7 +735,7 @@ end_nomap:
704 return ret; 735 return ret;
705} 736}
706 737
707static int rspi_is_dma(struct rspi_data *rspi, struct spi_transfer *t) 738static int rspi_is_dma(const struct rspi_data *rspi, struct spi_transfer *t)
708{ 739{
709 if (t->tx_buf && rspi->chan_tx) 740 if (t->tx_buf && rspi->chan_tx)
710 return 1; 741 return 1;
@@ -771,10 +802,14 @@ static int rspi_setup(struct spi_device *spi)
771{ 802{
772 struct rspi_data *rspi = spi_master_get_devdata(spi->master); 803 struct rspi_data *rspi = spi_master_get_devdata(spi->master);
773 804
774 if (!spi->bits_per_word)
775 spi->bits_per_word = 8;
776 rspi->max_speed_hz = spi->max_speed_hz; 805 rspi->max_speed_hz = spi->max_speed_hz;
777 806
807 rspi->spcmd = SPCMD_SSLKP;
808 if (spi->mode & SPI_CPOL)
809 rspi->spcmd |= SPCMD_CPOL;
810 if (spi->mode & SPI_CPHA)
811 rspi->spcmd |= SPCMD_CPHA;
812
778 set_config_register(rspi, 8); 813 set_config_register(rspi, 8);
779 814
780 return 0; 815 return 0;
@@ -802,10 +837,10 @@ static void rspi_cleanup(struct spi_device *spi)
802 837
803static irqreturn_t rspi_irq(int irq, void *_sr) 838static irqreturn_t rspi_irq(int irq, void *_sr)
804{ 839{
805 struct rspi_data *rspi = (struct rspi_data *)_sr; 840 struct rspi_data *rspi = _sr;
806 unsigned long spsr; 841 u8 spsr;
807 irqreturn_t ret = IRQ_NONE; 842 irqreturn_t ret = IRQ_NONE;
808 unsigned char disable_irq = 0; 843 u8 disable_irq = 0;
809 844
810 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); 845 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
811 if (spsr & SPSR_SPRF) 846 if (spsr & SPSR_SPRF)
@@ -825,7 +860,7 @@ static irqreturn_t rspi_irq(int irq, void *_sr)
825static int rspi_request_dma(struct rspi_data *rspi, 860static int rspi_request_dma(struct rspi_data *rspi,
826 struct platform_device *pdev) 861 struct platform_device *pdev)
827{ 862{
828 struct rspi_plat_data *rspi_pd = dev_get_platdata(&pdev->dev); 863 const struct rspi_plat_data *rspi_pd = dev_get_platdata(&pdev->dev);
829 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 864 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
830 dma_cap_mask_t mask; 865 dma_cap_mask_t mask;
831 struct dma_slave_config cfg; 866 struct dma_slave_config cfg;
@@ -887,11 +922,8 @@ static int rspi_remove(struct platform_device *pdev)
887{ 922{
888 struct rspi_data *rspi = platform_get_drvdata(pdev); 923 struct rspi_data *rspi = platform_get_drvdata(pdev);
889 924
890 spi_unregister_master(rspi->master);
891 rspi_release_dma(rspi); 925 rspi_release_dma(rspi);
892 free_irq(platform_get_irq(pdev, 0), rspi); 926 clk_disable(rspi->clk);
893 clk_put(rspi->clk);
894 iounmap(rspi->addr);
895 927
896 return 0; 928 return 0;
897} 929}
@@ -903,7 +935,7 @@ static int rspi_probe(struct platform_device *pdev)
903 struct rspi_data *rspi; 935 struct rspi_data *rspi;
904 int ret, irq; 936 int ret, irq;
905 char clk_name[16]; 937 char clk_name[16];
906 struct rspi_plat_data *rspi_pd = pdev->dev.platform_data; 938 const struct rspi_plat_data *rspi_pd = dev_get_platdata(&pdev->dev);
907 const struct spi_ops *ops; 939 const struct spi_ops *ops;
908 const struct platform_device_id *id_entry = pdev->id_entry; 940 const struct platform_device_id *id_entry = pdev->id_entry;
909 941
@@ -913,12 +945,6 @@ static int rspi_probe(struct platform_device *pdev)
913 dev_err(&pdev->dev, "there is no set_config_register\n"); 945 dev_err(&pdev->dev, "there is no set_config_register\n");
914 return -ENODEV; 946 return -ENODEV;
915 } 947 }
916 /* get base addr */
917 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
918 if (unlikely(res == NULL)) {
919 dev_err(&pdev->dev, "invalid resource\n");
920 return -EINVAL;
921 }
922 948
923 irq = platform_get_irq(pdev, 0); 949 irq = platform_get_irq(pdev, 0);
924 if (irq < 0) { 950 if (irq < 0) {
@@ -936,19 +962,20 @@ static int rspi_probe(struct platform_device *pdev)
936 platform_set_drvdata(pdev, rspi); 962 platform_set_drvdata(pdev, rspi);
937 rspi->ops = ops; 963 rspi->ops = ops;
938 rspi->master = master; 964 rspi->master = master;
939 rspi->addr = ioremap(res->start, resource_size(res)); 965
940 if (rspi->addr == NULL) { 966 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
941 dev_err(&pdev->dev, "ioremap error.\n"); 967 rspi->addr = devm_ioremap_resource(&pdev->dev, res);
942 ret = -ENOMEM; 968 if (IS_ERR(rspi->addr)) {
969 ret = PTR_ERR(rspi->addr);
943 goto error1; 970 goto error1;
944 } 971 }
945 972
946 snprintf(clk_name, sizeof(clk_name), "%s%d", id_entry->name, pdev->id); 973 snprintf(clk_name, sizeof(clk_name), "%s%d", id_entry->name, pdev->id);
947 rspi->clk = clk_get(&pdev->dev, clk_name); 974 rspi->clk = devm_clk_get(&pdev->dev, clk_name);
948 if (IS_ERR(rspi->clk)) { 975 if (IS_ERR(rspi->clk)) {
949 dev_err(&pdev->dev, "cannot get clock\n"); 976 dev_err(&pdev->dev, "cannot get clock\n");
950 ret = PTR_ERR(rspi->clk); 977 ret = PTR_ERR(rspi->clk);
951 goto error2; 978 goto error1;
952 } 979 }
953 clk_enable(rspi->clk); 980 clk_enable(rspi->clk);
954 981
@@ -957,45 +984,45 @@ static int rspi_probe(struct platform_device *pdev)
957 INIT_WORK(&rspi->ws, rspi_work); 984 INIT_WORK(&rspi->ws, rspi_work);
958 init_waitqueue_head(&rspi->wait); 985 init_waitqueue_head(&rspi->wait);
959 986
960 master->num_chipselect = rspi_pd->num_chipselect; 987 if (rspi_pd && rspi_pd->num_chipselect)
961 if (!master->num_chipselect) 988 master->num_chipselect = rspi_pd->num_chipselect;
989 else
962 master->num_chipselect = 2; /* default */ 990 master->num_chipselect = 2; /* default */
963 991
964 master->bus_num = pdev->id; 992 master->bus_num = pdev->id;
965 master->setup = rspi_setup; 993 master->setup = rspi_setup;
966 master->transfer = rspi_transfer; 994 master->transfer = rspi_transfer;
967 master->cleanup = rspi_cleanup; 995 master->cleanup = rspi_cleanup;
996 master->mode_bits = SPI_CPHA | SPI_CPOL;
968 997
969 ret = request_irq(irq, rspi_irq, 0, dev_name(&pdev->dev), rspi); 998 ret = devm_request_irq(&pdev->dev, irq, rspi_irq, 0,
999 dev_name(&pdev->dev), rspi);
970 if (ret < 0) { 1000 if (ret < 0) {
971 dev_err(&pdev->dev, "request_irq error\n"); 1001 dev_err(&pdev->dev, "request_irq error\n");
972 goto error3; 1002 goto error2;
973 } 1003 }
974 1004
975 rspi->irq = irq; 1005 rspi->irq = irq;
976 ret = rspi_request_dma(rspi, pdev); 1006 ret = rspi_request_dma(rspi, pdev);
977 if (ret < 0) { 1007 if (ret < 0) {
978 dev_err(&pdev->dev, "rspi_request_dma failed.\n"); 1008 dev_err(&pdev->dev, "rspi_request_dma failed.\n");
979 goto error4; 1009 goto error3;
980 } 1010 }
981 1011
982 ret = spi_register_master(master); 1012 ret = devm_spi_register_master(&pdev->dev, master);
983 if (ret < 0) { 1013 if (ret < 0) {
984 dev_err(&pdev->dev, "spi_register_master error.\n"); 1014 dev_err(&pdev->dev, "spi_register_master error.\n");
985 goto error4; 1015 goto error3;
986 } 1016 }
987 1017
988 dev_info(&pdev->dev, "probed\n"); 1018 dev_info(&pdev->dev, "probed\n");
989 1019
990 return 0; 1020 return 0;
991 1021
992error4:
993 rspi_release_dma(rspi);
994 free_irq(irq, rspi);
995error3: 1022error3:
996 clk_put(rspi->clk); 1023 rspi_release_dma(rspi);
997error2: 1024error2:
998 iounmap(rspi->addr); 1025 clk_disable(rspi->clk);
999error1: 1026error1:
1000 spi_master_put(master); 1027 spi_master_put(master);
1001 1028
diff --git a/drivers/spi/spi-s3c24xx.c b/drivers/spi/spi-s3c24xx.c
index 0dc32a11bd3c..746424aa5353 100644
--- a/drivers/spi/spi-s3c24xx.c
+++ b/drivers/spi/spi-s3c24xx.c
@@ -29,7 +29,6 @@
29 29
30#include <plat/regs-spi.h> 30#include <plat/regs-spi.h>
31 31
32#include <plat/fiq.h>
33#include <asm/fiq.h> 32#include <asm/fiq.h>
34 33
35#include "spi-s3c24xx-fiq.h" 34#include "spi-s3c24xx-fiq.h"
@@ -78,14 +77,12 @@ struct s3c24xx_spi {
78 unsigned char *rx; 77 unsigned char *rx;
79 78
80 struct clk *clk; 79 struct clk *clk;
81 struct resource *ioarea;
82 struct spi_master *master; 80 struct spi_master *master;
83 struct spi_device *curdev; 81 struct spi_device *curdev;
84 struct device *dev; 82 struct device *dev;
85 struct s3c2410_spi_info *pdata; 83 struct s3c2410_spi_info *pdata;
86}; 84};
87 85
88
89#define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT) 86#define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT)
90#define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP) 87#define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP)
91 88
@@ -517,8 +514,7 @@ static int s3c24xx_spi_probe(struct platform_device *pdev)
517 master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi)); 514 master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi));
518 if (master == NULL) { 515 if (master == NULL) {
519 dev_err(&pdev->dev, "No memory for spi_master\n"); 516 dev_err(&pdev->dev, "No memory for spi_master\n");
520 err = -ENOMEM; 517 return -ENOMEM;
521 goto err_nomem;
522 } 518 }
523 519
524 hw = spi_master_get_devdata(master); 520 hw = spi_master_get_devdata(master);
@@ -562,48 +558,32 @@ static int s3c24xx_spi_probe(struct platform_device *pdev)
562 dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang); 558 dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
563 559
564 /* find and map our resources */ 560 /* find and map our resources */
565
566 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 561 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
567 if (res == NULL) { 562 hw->regs = devm_ioremap_resource(&pdev->dev, res);
568 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n"); 563 if (IS_ERR(hw->regs)) {
569 err = -ENOENT; 564 err = PTR_ERR(hw->regs);
570 goto err_no_iores; 565 goto err_no_pdata;
571 }
572
573 hw->ioarea = request_mem_region(res->start, resource_size(res),
574 pdev->name);
575
576 if (hw->ioarea == NULL) {
577 dev_err(&pdev->dev, "Cannot reserve region\n");
578 err = -ENXIO;
579 goto err_no_iores;
580 }
581
582 hw->regs = ioremap(res->start, resource_size(res));
583 if (hw->regs == NULL) {
584 dev_err(&pdev->dev, "Cannot map IO\n");
585 err = -ENXIO;
586 goto err_no_iomap;
587 } 566 }
588 567
589 hw->irq = platform_get_irq(pdev, 0); 568 hw->irq = platform_get_irq(pdev, 0);
590 if (hw->irq < 0) { 569 if (hw->irq < 0) {
591 dev_err(&pdev->dev, "No IRQ specified\n"); 570 dev_err(&pdev->dev, "No IRQ specified\n");
592 err = -ENOENT; 571 err = -ENOENT;
593 goto err_no_irq; 572 goto err_no_pdata;
594 } 573 }
595 574
596 err = request_irq(hw->irq, s3c24xx_spi_irq, 0, pdev->name, hw); 575 err = devm_request_irq(&pdev->dev, hw->irq, s3c24xx_spi_irq, 0,
576 pdev->name, hw);
597 if (err) { 577 if (err) {
598 dev_err(&pdev->dev, "Cannot claim IRQ\n"); 578 dev_err(&pdev->dev, "Cannot claim IRQ\n");
599 goto err_no_irq; 579 goto err_no_pdata;
600 } 580 }
601 581
602 hw->clk = clk_get(&pdev->dev, "spi"); 582 hw->clk = devm_clk_get(&pdev->dev, "spi");
603 if (IS_ERR(hw->clk)) { 583 if (IS_ERR(hw->clk)) {
604 dev_err(&pdev->dev, "No clock for device\n"); 584 dev_err(&pdev->dev, "No clock for device\n");
605 err = PTR_ERR(hw->clk); 585 err = PTR_ERR(hw->clk);
606 goto err_no_clk; 586 goto err_no_pdata;
607 } 587 }
608 588
609 /* setup any gpio we can */ 589 /* setup any gpio we can */
@@ -615,7 +595,8 @@ static int s3c24xx_spi_probe(struct platform_device *pdev)
615 goto err_register; 595 goto err_register;
616 } 596 }
617 597
618 err = gpio_request(pdata->pin_cs, dev_name(&pdev->dev)); 598 err = devm_gpio_request(&pdev->dev, pdata->pin_cs,
599 dev_name(&pdev->dev));
619 if (err) { 600 if (err) {
620 dev_err(&pdev->dev, "Failed to get gpio for cs\n"); 601 dev_err(&pdev->dev, "Failed to get gpio for cs\n");
621 goto err_register; 602 goto err_register;
@@ -639,27 +620,10 @@ static int s3c24xx_spi_probe(struct platform_device *pdev)
639 return 0; 620 return 0;
640 621
641 err_register: 622 err_register:
642 if (hw->set_cs == s3c24xx_spi_gpiocs)
643 gpio_free(pdata->pin_cs);
644
645 clk_disable(hw->clk); 623 clk_disable(hw->clk);
646 clk_put(hw->clk);
647
648 err_no_clk:
649 free_irq(hw->irq, hw);
650 624
651 err_no_irq:
652 iounmap(hw->regs);
653
654 err_no_iomap:
655 release_resource(hw->ioarea);
656 kfree(hw->ioarea);
657
658 err_no_iores:
659 err_no_pdata: 625 err_no_pdata:
660 spi_master_put(hw->master); 626 spi_master_put(hw->master);
661
662 err_nomem:
663 return err; 627 return err;
664} 628}
665 629
@@ -668,19 +632,7 @@ static int s3c24xx_spi_remove(struct platform_device *dev)
668 struct s3c24xx_spi *hw = platform_get_drvdata(dev); 632 struct s3c24xx_spi *hw = platform_get_drvdata(dev);
669 633
670 spi_bitbang_stop(&hw->bitbang); 634 spi_bitbang_stop(&hw->bitbang);
671
672 clk_disable(hw->clk); 635 clk_disable(hw->clk);
673 clk_put(hw->clk);
674
675 free_irq(hw->irq, hw);
676 iounmap(hw->regs);
677
678 if (hw->set_cs == s3c24xx_spi_gpiocs)
679 gpio_free(hw->pdata->pin_cs);
680
681 release_resource(hw->ioarea);
682 kfree(hw->ioarea);
683
684 spi_master_put(hw->master); 636 spi_master_put(hw->master);
685 return 0; 637 return 0;
686} 638}
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index 4c4b0a1219a7..ae907dde1371 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -890,7 +890,7 @@ static int s3c64xx_spi_transfer_one(struct spi_master *master,
890 unsigned long flags; 890 unsigned long flags;
891 int use_dma; 891 int use_dma;
892 892
893 reinit_completion(&sdd->xfer_completion); 893 reinit_completion(&sdd->xfer_completion);
894 894
895 /* Only BPW and Speed may change across transfers */ 895 /* Only BPW and Speed may change across transfers */
896 bpw = xfer->bits_per_word; 896 bpw = xfer->bits_per_word;
@@ -927,9 +927,6 @@ static int s3c64xx_spi_transfer_one(struct spi_master *master,
927 /* Start the signals */ 927 /* Start the signals */
928 writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL); 928 writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
929 929
930 /* Start the signals */
931 writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
932
933 spin_unlock_irqrestore(&sdd->lock, flags); 930 spin_unlock_irqrestore(&sdd->lock, flags);
934 931
935 status = wait_for_xfer(sdd, xfer, use_dma); 932 status = wait_for_xfer(sdd, xfer, use_dma);
diff --git a/drivers/spi/spi-sc18is602.c b/drivers/spi/spi-sc18is602.c
index 9eda21d739c6..121c2e1dea36 100644
--- a/drivers/spi/spi-sc18is602.c
+++ b/drivers/spi/spi-sc18is602.c
@@ -183,18 +183,11 @@ static int sc18is602_setup_transfer(struct sc18is602 *hw, u32 hz, u8 mode)
183static int sc18is602_check_transfer(struct spi_device *spi, 183static int sc18is602_check_transfer(struct spi_device *spi,
184 struct spi_transfer *t, int tlen) 184 struct spi_transfer *t, int tlen)
185{ 185{
186 int bpw;
187 uint32_t hz; 186 uint32_t hz;
188 187
189 if (t && t->len + tlen > SC18IS602_BUFSIZ) 188 if (t && t->len + tlen > SC18IS602_BUFSIZ)
190 return -EINVAL; 189 return -EINVAL;
191 190
192 bpw = spi->bits_per_word;
193 if (t && t->bits_per_word)
194 bpw = t->bits_per_word;
195 if (bpw != 8)
196 return -EINVAL;
197
198 hz = spi->max_speed_hz; 191 hz = spi->max_speed_hz;
199 if (t && t->speed_hz) 192 if (t && t->speed_hz)
200 hz = t->speed_hz; 193 hz = t->speed_hz;
@@ -254,9 +247,6 @@ error:
254 247
255static int sc18is602_setup(struct spi_device *spi) 248static int sc18is602_setup(struct spi_device *spi)
256{ 249{
257 if (!spi->bits_per_word)
258 spi->bits_per_word = 8;
259
260 if (spi->mode & ~(SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST)) 250 if (spi->mode & ~(SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST))
261 return -EINVAL; 251 return -EINVAL;
262 252
@@ -315,11 +305,12 @@ static int sc18is602_probe(struct i2c_client *client,
315 } 305 }
316 master->bus_num = client->adapter->nr; 306 master->bus_num = client->adapter->nr;
317 master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST; 307 master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST;
308 master->bits_per_word_mask = SPI_BPW_MASK(8);
318 master->setup = sc18is602_setup; 309 master->setup = sc18is602_setup;
319 master->transfer_one_message = sc18is602_transfer_one; 310 master->transfer_one_message = sc18is602_transfer_one;
320 master->dev.of_node = np; 311 master->dev.of_node = np;
321 312
322 error = spi_register_master(master); 313 error = devm_spi_register_master(dev, master);
323 if (error) 314 if (error)
324 goto error_reg; 315 goto error_reg;
325 316
@@ -330,16 +321,6 @@ error_reg:
330 return error; 321 return error;
331} 322}
332 323
333static int sc18is602_remove(struct i2c_client *client)
334{
335 struct sc18is602 *hw = i2c_get_clientdata(client);
336 struct spi_master *master = hw->master;
337
338 spi_unregister_master(master);
339
340 return 0;
341}
342
343static const struct i2c_device_id sc18is602_id[] = { 324static const struct i2c_device_id sc18is602_id[] = {
344 { "sc18is602", sc18is602 }, 325 { "sc18is602", sc18is602 },
345 { "sc18is602b", sc18is602b }, 326 { "sc18is602b", sc18is602b },
@@ -353,7 +334,6 @@ static struct i2c_driver sc18is602_driver = {
353 .name = "sc18is602", 334 .name = "sc18is602",
354 }, 335 },
355 .probe = sc18is602_probe, 336 .probe = sc18is602_probe,
356 .remove = sc18is602_remove,
357 .id_table = sc18is602_id, 337 .id_table = sc18is602_id,
358}; 338};
359 339
diff --git a/drivers/spi/spi-sh-hspi.c b/drivers/spi/spi-sh-hspi.c
index 292567ab4c6c..82d2f922ffa0 100644
--- a/drivers/spi/spi-sh-hspi.c
+++ b/drivers/spi/spi-sh-hspi.c
@@ -197,7 +197,7 @@ static int hspi_transfer_one_message(struct spi_master *master,
197 197
198 hspi_write(hspi, SPTBR, tx); 198 hspi_write(hspi, SPTBR, tx);
199 199
200 /* wait recive */ 200 /* wait receive */
201 ret = hspi_status_check_timeout(hspi, 0x4, 0x4); 201 ret = hspi_status_check_timeout(hspi, 0x4, 0x4);
202 if (ret < 0) 202 if (ret < 0)
203 break; 203 break;
@@ -353,4 +353,4 @@ module_platform_driver(hspi_driver);
353MODULE_DESCRIPTION("SuperH HSPI bus driver"); 353MODULE_DESCRIPTION("SuperH HSPI bus driver");
354MODULE_LICENSE("GPL"); 354MODULE_LICENSE("GPL");
355MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"); 355MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");
356MODULE_ALIAS("platform:sh_spi"); 356MODULE_ALIAS("platform:sh-hspi");
diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c
index c74298cf70e2..81cc02f5f9b0 100644
--- a/drivers/spi/spi-sh-msiof.c
+++ b/drivers/spi/spi-sh-msiof.c
@@ -152,7 +152,7 @@ static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
152 size_t k; 152 size_t k;
153 153
154 if (!WARN_ON(!spi_hz || !parent_rate)) 154 if (!WARN_ON(!spi_hz || !parent_rate))
155 div = parent_rate / spi_hz; 155 div = DIV_ROUND_UP(parent_rate, spi_hz);
156 156
157 /* TODO: make more fine grained */ 157 /* TODO: make more fine grained */
158 158
@@ -169,7 +169,7 @@ static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
169 169
170static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, 170static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p,
171 u32 cpol, u32 cpha, 171 u32 cpol, u32 cpha,
172 u32 tx_hi_z, u32 lsb_first) 172 u32 tx_hi_z, u32 lsb_first, u32 cs_high)
173{ 173{
174 u32 tmp; 174 u32 tmp;
175 int edge; 175 int edge;
@@ -182,8 +182,12 @@ static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p,
182 * 1 1 11 11 1 1 182 * 1 1 11 11 1 1
183 */ 183 */
184 sh_msiof_write(p, FCTR, 0); 184 sh_msiof_write(p, FCTR, 0);
185 sh_msiof_write(p, TMDR1, 0xe2000005 | (lsb_first << 24)); 185
186 sh_msiof_write(p, RMDR1, 0x22000005 | (lsb_first << 24)); 186 tmp = 0;
187 tmp |= !cs_high << 25;
188 tmp |= lsb_first << 24;
189 sh_msiof_write(p, TMDR1, 0xe0000005 | tmp);
190 sh_msiof_write(p, RMDR1, 0x20000005 | tmp);
187 191
188 tmp = 0xa0000000; 192 tmp = 0xa0000000;
189 tmp |= cpol << 30; /* TSCKIZ */ 193 tmp |= cpol << 30; /* TSCKIZ */
@@ -417,11 +421,12 @@ static void sh_msiof_spi_chipselect(struct spi_device *spi, int is_on)
417 sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL), 421 sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL),
418 !!(spi->mode & SPI_CPHA), 422 !!(spi->mode & SPI_CPHA),
419 !!(spi->mode & SPI_3WIRE), 423 !!(spi->mode & SPI_3WIRE),
420 !!(spi->mode & SPI_LSB_FIRST)); 424 !!(spi->mode & SPI_LSB_FIRST),
425 !!(spi->mode & SPI_CS_HIGH));
421 } 426 }
422 427
423 /* use spi->controller data for CS (same strategy as spi_gpio) */ 428 /* use spi->controller data for CS (same strategy as spi_gpio) */
424 gpio_set_value((unsigned)spi->controller_data, value); 429 gpio_set_value((uintptr_t)spi->controller_data, value);
425 430
426 if (is_on == BITBANG_CS_INACTIVE) { 431 if (is_on == BITBANG_CS_INACTIVE) {
427 if (test_and_clear_bit(0, &p->flags)) { 432 if (test_and_clear_bit(0, &p->flags)) {
@@ -635,8 +640,7 @@ static int sh_msiof_spi_probe(struct platform_device *pdev)
635 master = spi_alloc_master(&pdev->dev, sizeof(struct sh_msiof_spi_priv)); 640 master = spi_alloc_master(&pdev->dev, sizeof(struct sh_msiof_spi_priv));
636 if (master == NULL) { 641 if (master == NULL) {
637 dev_err(&pdev->dev, "failed to allocate spi master\n"); 642 dev_err(&pdev->dev, "failed to allocate spi master\n");
638 ret = -ENOMEM; 643 return -ENOMEM;
639 goto err0;
640 } 644 }
641 645
642 p = spi_master_get_devdata(master); 646 p = spi_master_get_devdata(master);
@@ -655,32 +659,38 @@ static int sh_msiof_spi_probe(struct platform_device *pdev)
655 659
656 init_completion(&p->done); 660 init_completion(&p->done);
657 661
658 p->clk = clk_get(&pdev->dev, NULL); 662 p->clk = devm_clk_get(&pdev->dev, NULL);
659 if (IS_ERR(p->clk)) { 663 if (IS_ERR(p->clk)) {
660 dev_err(&pdev->dev, "cannot get clock\n"); 664 dev_err(&pdev->dev, "cannot get clock\n");
661 ret = PTR_ERR(p->clk); 665 ret = PTR_ERR(p->clk);
662 goto err1; 666 goto err1;
663 } 667 }
664 668
665 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
666 i = platform_get_irq(pdev, 0); 669 i = platform_get_irq(pdev, 0);
667 if (!r || i < 0) { 670 if (i < 0) {
668 dev_err(&pdev->dev, "cannot get platform resources\n"); 671 dev_err(&pdev->dev, "cannot get platform IRQ\n");
669 ret = -ENOENT; 672 ret = -ENOENT;
670 goto err2; 673 goto err1;
671 } 674 }
672 p->mapbase = ioremap_nocache(r->start, resource_size(r)); 675
673 if (!p->mapbase) { 676 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
674 dev_err(&pdev->dev, "unable to ioremap\n"); 677 p->mapbase = devm_ioremap_resource(&pdev->dev, r);
675 ret = -ENXIO; 678 if (IS_ERR(p->mapbase)) {
676 goto err2; 679 ret = PTR_ERR(p->mapbase);
680 goto err1;
677 } 681 }
678 682
679 ret = request_irq(i, sh_msiof_spi_irq, 0, 683 ret = devm_request_irq(&pdev->dev, i, sh_msiof_spi_irq, 0,
680 dev_name(&pdev->dev), p); 684 dev_name(&pdev->dev), p);
681 if (ret) { 685 if (ret) {
682 dev_err(&pdev->dev, "unable to request irq\n"); 686 dev_err(&pdev->dev, "unable to request irq\n");
683 goto err3; 687 goto err1;
688 }
689
690 ret = clk_prepare(p->clk);
691 if (ret < 0) {
692 dev_err(&pdev->dev, "unable to prepare clock\n");
693 goto err1;
684 } 694 }
685 695
686 p->pdev = pdev; 696 p->pdev = pdev;
@@ -719,13 +729,9 @@ static int sh_msiof_spi_probe(struct platform_device *pdev)
719 return 0; 729 return 0;
720 730
721 pm_runtime_disable(&pdev->dev); 731 pm_runtime_disable(&pdev->dev);
722 err3: 732 clk_unprepare(p->clk);
723 iounmap(p->mapbase);
724 err2:
725 clk_put(p->clk);
726 err1: 733 err1:
727 spi_master_put(master); 734 spi_master_put(master);
728 err0:
729 return ret; 735 return ret;
730} 736}
731 737
@@ -737,9 +743,7 @@ static int sh_msiof_spi_remove(struct platform_device *pdev)
737 ret = spi_bitbang_stop(&p->bitbang); 743 ret = spi_bitbang_stop(&p->bitbang);
738 if (!ret) { 744 if (!ret) {
739 pm_runtime_disable(&pdev->dev); 745 pm_runtime_disable(&pdev->dev);
740 free_irq(platform_get_irq(pdev, 0), p); 746 clk_unprepare(p->clk);
741 iounmap(p->mapbase);
742 clk_put(p->clk);
743 spi_master_put(p->bitbang.master); 747 spi_master_put(p->bitbang.master);
744 } 748 }
745 return ret; 749 return ret;
diff --git a/drivers/spi/spi-sh.c b/drivers/spi/spi-sh.c
index c120a70094f2..f6f2c7010177 100644
--- a/drivers/spi/spi-sh.c
+++ b/drivers/spi/spi-sh.c
@@ -171,7 +171,6 @@ static int spi_sh_send(struct spi_sh_data *ss, struct spi_message *mesg,
171 int remain = t->len; 171 int remain = t->len;
172 int cur_len; 172 int cur_len;
173 unsigned char *data; 173 unsigned char *data;
174 unsigned long tmp;
175 long ret; 174 long ret;
176 175
177 if (t->len) 176 if (t->len)
@@ -213,9 +212,7 @@ static int spi_sh_send(struct spi_sh_data *ss, struct spi_message *mesg,
213 } 212 }
214 213
215 if (list_is_last(&t->transfer_list, &mesg->transfers)) { 214 if (list_is_last(&t->transfer_list, &mesg->transfers)) {
216 tmp = spi_sh_read(ss, SPI_SH_CR1); 215 spi_sh_clear_bit(ss, SPI_SH_SSD | SPI_SH_SSDB, SPI_SH_CR1);
217 tmp = tmp & ~(SPI_SH_SSD | SPI_SH_SSDB);
218 spi_sh_write(ss, tmp, SPI_SH_CR1);
219 spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1); 216 spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
220 217
221 ss->cr1 &= ~SPI_SH_TBE; 218 ss->cr1 &= ~SPI_SH_TBE;
@@ -239,7 +236,6 @@ static int spi_sh_receive(struct spi_sh_data *ss, struct spi_message *mesg,
239 int remain = t->len; 236 int remain = t->len;
240 int cur_len; 237 int cur_len;
241 unsigned char *data; 238 unsigned char *data;
242 unsigned long tmp;
243 long ret; 239 long ret;
244 240
245 if (t->len > SPI_SH_MAX_BYTE) 241 if (t->len > SPI_SH_MAX_BYTE)
@@ -247,9 +243,7 @@ static int spi_sh_receive(struct spi_sh_data *ss, struct spi_message *mesg,
247 else 243 else
248 spi_sh_write(ss, t->len, SPI_SH_CR3); 244 spi_sh_write(ss, t->len, SPI_SH_CR3);
249 245
250 tmp = spi_sh_read(ss, SPI_SH_CR1); 246 spi_sh_clear_bit(ss, SPI_SH_SSD | SPI_SH_SSDB, SPI_SH_CR1);
251 tmp = tmp & ~(SPI_SH_SSD | SPI_SH_SSDB);
252 spi_sh_write(ss, tmp, SPI_SH_CR1);
253 spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1); 247 spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
254 248
255 spi_sh_wait_write_buffer_empty(ss); 249 spi_sh_wait_write_buffer_empty(ss);
@@ -358,9 +352,6 @@ static int spi_sh_setup(struct spi_device *spi)
358{ 352{
359 struct spi_sh_data *ss = spi_master_get_devdata(spi->master); 353 struct spi_sh_data *ss = spi_master_get_devdata(spi->master);
360 354
361 if (!spi->bits_per_word)
362 spi->bits_per_word = 8;
363
364 pr_debug("%s: enter\n", __func__); 355 pr_debug("%s: enter\n", __func__);
365 356
366 spi_sh_write(ss, 0xfe, SPI_SH_CR1); /* SPI sycle stop */ 357 spi_sh_write(ss, 0xfe, SPI_SH_CR1); /* SPI sycle stop */
diff --git a/drivers/spi/spi-sirf.c b/drivers/spi/spi-sirf.c
index ed5e501c4652..e430689c3837 100644
--- a/drivers/spi/spi-sirf.c
+++ b/drivers/spi/spi-sirf.c
@@ -536,16 +536,9 @@ spi_sirfsoc_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
536 536
537static int spi_sirfsoc_setup(struct spi_device *spi) 537static int spi_sirfsoc_setup(struct spi_device *spi)
538{ 538{
539 struct sirfsoc_spi *sspi;
540
541 if (!spi->max_speed_hz) 539 if (!spi->max_speed_hz)
542 return -EINVAL; 540 return -EINVAL;
543 541
544 sspi = spi_master_get_devdata(spi->master);
545
546 if (!spi->bits_per_word)
547 spi->bits_per_word = 8;
548
549 return spi_sirfsoc_setup_transfer(spi, NULL); 542 return spi_sirfsoc_setup_transfer(spi, NULL);
550} 543}
551 544
diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
index c8604981a058..413c71843492 100644
--- a/drivers/spi/spi-tegra114.c
+++ b/drivers/spi/spi-tegra114.c
@@ -54,11 +54,8 @@
54#define SPI_CS_SS_VAL (1 << 20) 54#define SPI_CS_SS_VAL (1 << 20)
55#define SPI_CS_SW_HW (1 << 21) 55#define SPI_CS_SW_HW (1 << 21)
56/* SPI_CS_POL_INACTIVE bits are default high */ 56/* SPI_CS_POL_INACTIVE bits are default high */
57#define SPI_CS_POL_INACTIVE 22 57 /* n from 0 to 3 */
58#define SPI_CS_POL_INACTIVE_0 (1 << 22) 58#define SPI_CS_POL_INACTIVE(n) (1 << (22 + (n)))
59#define SPI_CS_POL_INACTIVE_1 (1 << 23)
60#define SPI_CS_POL_INACTIVE_2 (1 << 24)
61#define SPI_CS_POL_INACTIVE_3 (1 << 25)
62#define SPI_CS_POL_INACTIVE_MASK (0xF << 22) 59#define SPI_CS_POL_INACTIVE_MASK (0xF << 22)
63 60
64#define SPI_CS_SEL_0 (0 << 26) 61#define SPI_CS_SEL_0 (0 << 26)
@@ -165,9 +162,6 @@
165#define MAX_HOLD_CYCLES 16 162#define MAX_HOLD_CYCLES 16
166#define SPI_DEFAULT_SPEED 25000000 163#define SPI_DEFAULT_SPEED 25000000
167 164
168#define MAX_CHIP_SELECT 4
169#define SPI_FIFO_DEPTH 64
170
171struct tegra_spi_data { 165struct tegra_spi_data {
172 struct device *dev; 166 struct device *dev;
173 struct spi_master *master; 167 struct spi_master *master;
@@ -184,7 +178,6 @@ struct tegra_spi_data {
184 struct spi_device *cur_spi; 178 struct spi_device *cur_spi;
185 struct spi_device *cs_control; 179 struct spi_device *cs_control;
186 unsigned cur_pos; 180 unsigned cur_pos;
187 unsigned cur_len;
188 unsigned words_per_32bit; 181 unsigned words_per_32bit;
189 unsigned bytes_per_word; 182 unsigned bytes_per_word;
190 unsigned curr_dma_words; 183 unsigned curr_dma_words;
@@ -204,12 +197,10 @@ struct tegra_spi_data {
204 u32 rx_status; 197 u32 rx_status;
205 u32 status_reg; 198 u32 status_reg;
206 bool is_packed; 199 bool is_packed;
207 unsigned long packed_size;
208 200
209 u32 command1_reg; 201 u32 command1_reg;
210 u32 dma_control_reg; 202 u32 dma_control_reg;
211 u32 def_command1_reg; 203 u32 def_command1_reg;
212 u32 spi_cs_timing;
213 204
214 struct completion xfer_completion; 205 struct completion xfer_completion;
215 struct spi_transfer *curr_xfer; 206 struct spi_transfer *curr_xfer;
@@ -227,14 +218,14 @@ struct tegra_spi_data {
227static int tegra_spi_runtime_suspend(struct device *dev); 218static int tegra_spi_runtime_suspend(struct device *dev);
228static int tegra_spi_runtime_resume(struct device *dev); 219static int tegra_spi_runtime_resume(struct device *dev);
229 220
230static inline unsigned long tegra_spi_readl(struct tegra_spi_data *tspi, 221static inline u32 tegra_spi_readl(struct tegra_spi_data *tspi,
231 unsigned long reg) 222 unsigned long reg)
232{ 223{
233 return readl(tspi->base + reg); 224 return readl(tspi->base + reg);
234} 225}
235 226
236static inline void tegra_spi_writel(struct tegra_spi_data *tspi, 227static inline void tegra_spi_writel(struct tegra_spi_data *tspi,
237 unsigned long val, unsigned long reg) 228 u32 val, unsigned long reg)
238{ 229{
239 writel(val, tspi->base + reg); 230 writel(val, tspi->base + reg);
240 231
@@ -245,7 +236,7 @@ static inline void tegra_spi_writel(struct tegra_spi_data *tspi,
245 236
246static void tegra_spi_clear_status(struct tegra_spi_data *tspi) 237static void tegra_spi_clear_status(struct tegra_spi_data *tspi)
247{ 238{
248 unsigned long val; 239 u32 val;
249 240
250 /* Write 1 to clear status register */ 241 /* Write 1 to clear status register */
251 val = tegra_spi_readl(tspi, SPI_TRANS_STATUS); 242 val = tegra_spi_readl(tspi, SPI_TRANS_STATUS);
@@ -296,10 +287,9 @@ static unsigned tegra_spi_fill_tx_fifo_from_client_txbuf(
296{ 287{
297 unsigned nbytes; 288 unsigned nbytes;
298 unsigned tx_empty_count; 289 unsigned tx_empty_count;
299 unsigned long fifo_status; 290 u32 fifo_status;
300 unsigned max_n_32bit; 291 unsigned max_n_32bit;
301 unsigned i, count; 292 unsigned i, count;
302 unsigned long x;
303 unsigned int written_words; 293 unsigned int written_words;
304 unsigned fifo_words_left; 294 unsigned fifo_words_left;
305 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos; 295 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
@@ -313,9 +303,9 @@ static unsigned tegra_spi_fill_tx_fifo_from_client_txbuf(
313 nbytes = written_words * tspi->bytes_per_word; 303 nbytes = written_words * tspi->bytes_per_word;
314 max_n_32bit = DIV_ROUND_UP(nbytes, 4); 304 max_n_32bit = DIV_ROUND_UP(nbytes, 4);
315 for (count = 0; count < max_n_32bit; count++) { 305 for (count = 0; count < max_n_32bit; count++) {
316 x = 0; 306 u32 x = 0;
317 for (i = 0; (i < 4) && nbytes; i++, nbytes--) 307 for (i = 0; (i < 4) && nbytes; i++, nbytes--)
318 x |= (*tx_buf++) << (i*8); 308 x |= (u32)(*tx_buf++) << (i * 8);
319 tegra_spi_writel(tspi, x, SPI_TX_FIFO); 309 tegra_spi_writel(tspi, x, SPI_TX_FIFO);
320 } 310 }
321 } else { 311 } else {
@@ -323,10 +313,10 @@ static unsigned tegra_spi_fill_tx_fifo_from_client_txbuf(
323 written_words = max_n_32bit; 313 written_words = max_n_32bit;
324 nbytes = written_words * tspi->bytes_per_word; 314 nbytes = written_words * tspi->bytes_per_word;
325 for (count = 0; count < max_n_32bit; count++) { 315 for (count = 0; count < max_n_32bit; count++) {
326 x = 0; 316 u32 x = 0;
327 for (i = 0; nbytes && (i < tspi->bytes_per_word); 317 for (i = 0; nbytes && (i < tspi->bytes_per_word);
328 i++, nbytes--) 318 i++, nbytes--)
329 x |= ((*tx_buf++) << i*8); 319 x |= (u32)(*tx_buf++) << (i * 8);
330 tegra_spi_writel(tspi, x, SPI_TX_FIFO); 320 tegra_spi_writel(tspi, x, SPI_TX_FIFO);
331 } 321 }
332 } 322 }
@@ -338,9 +328,8 @@ static unsigned int tegra_spi_read_rx_fifo_to_client_rxbuf(
338 struct tegra_spi_data *tspi, struct spi_transfer *t) 328 struct tegra_spi_data *tspi, struct spi_transfer *t)
339{ 329{
340 unsigned rx_full_count; 330 unsigned rx_full_count;
341 unsigned long fifo_status; 331 u32 fifo_status;
342 unsigned i, count; 332 unsigned i, count;
343 unsigned long x;
344 unsigned int read_words = 0; 333 unsigned int read_words = 0;
345 unsigned len; 334 unsigned len;
346 u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos; 335 u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos;
@@ -350,20 +339,16 @@ static unsigned int tegra_spi_read_rx_fifo_to_client_rxbuf(
350 if (tspi->is_packed) { 339 if (tspi->is_packed) {
351 len = tspi->curr_dma_words * tspi->bytes_per_word; 340 len = tspi->curr_dma_words * tspi->bytes_per_word;
352 for (count = 0; count < rx_full_count; count++) { 341 for (count = 0; count < rx_full_count; count++) {
353 x = tegra_spi_readl(tspi, SPI_RX_FIFO); 342 u32 x = tegra_spi_readl(tspi, SPI_RX_FIFO);
354 for (i = 0; len && (i < 4); i++, len--) 343 for (i = 0; len && (i < 4); i++, len--)
355 *rx_buf++ = (x >> i*8) & 0xFF; 344 *rx_buf++ = (x >> i*8) & 0xFF;
356 } 345 }
357 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word; 346 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
358 read_words += tspi->curr_dma_words; 347 read_words += tspi->curr_dma_words;
359 } else { 348 } else {
360 unsigned int rx_mask; 349 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
361 unsigned int bits_per_word = t->bits_per_word;
362
363 rx_mask = (1 << bits_per_word) - 1;
364 for (count = 0; count < rx_full_count; count++) { 350 for (count = 0; count < rx_full_count; count++) {
365 x = tegra_spi_readl(tspi, SPI_RX_FIFO); 351 u32 x = tegra_spi_readl(tspi, SPI_RX_FIFO) & rx_mask;
366 x &= rx_mask;
367 for (i = 0; (i < tspi->bytes_per_word); i++) 352 for (i = 0; (i < tspi->bytes_per_word); i++)
368 *rx_buf++ = (x >> (i*8)) & 0xFF; 353 *rx_buf++ = (x >> (i*8)) & 0xFF;
369 } 354 }
@@ -376,27 +361,24 @@ static unsigned int tegra_spi_read_rx_fifo_to_client_rxbuf(
376static void tegra_spi_copy_client_txbuf_to_spi_txbuf( 361static void tegra_spi_copy_client_txbuf_to_spi_txbuf(
377 struct tegra_spi_data *tspi, struct spi_transfer *t) 362 struct tegra_spi_data *tspi, struct spi_transfer *t)
378{ 363{
379 unsigned len;
380
381 /* Make the dma buffer to read by cpu */ 364 /* Make the dma buffer to read by cpu */
382 dma_sync_single_for_cpu(tspi->dev, tspi->tx_dma_phys, 365 dma_sync_single_for_cpu(tspi->dev, tspi->tx_dma_phys,
383 tspi->dma_buf_size, DMA_TO_DEVICE); 366 tspi->dma_buf_size, DMA_TO_DEVICE);
384 367
385 if (tspi->is_packed) { 368 if (tspi->is_packed) {
386 len = tspi->curr_dma_words * tspi->bytes_per_word; 369 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word;
387 memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len); 370 memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len);
388 } else { 371 } else {
389 unsigned int i; 372 unsigned int i;
390 unsigned int count; 373 unsigned int count;
391 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos; 374 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
392 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word; 375 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word;
393 unsigned int x;
394 376
395 for (count = 0; count < tspi->curr_dma_words; count++) { 377 for (count = 0; count < tspi->curr_dma_words; count++) {
396 x = 0; 378 u32 x = 0;
397 for (i = 0; consume && (i < tspi->bytes_per_word); 379 for (i = 0; consume && (i < tspi->bytes_per_word);
398 i++, consume--) 380 i++, consume--)
399 x |= ((*tx_buf++) << i * 8); 381 x |= (u32)(*tx_buf++) << (i * 8);
400 tspi->tx_dma_buf[count] = x; 382 tspi->tx_dma_buf[count] = x;
401 } 383 }
402 } 384 }
@@ -410,27 +392,21 @@ static void tegra_spi_copy_client_txbuf_to_spi_txbuf(
410static void tegra_spi_copy_spi_rxbuf_to_client_rxbuf( 392static void tegra_spi_copy_spi_rxbuf_to_client_rxbuf(
411 struct tegra_spi_data *tspi, struct spi_transfer *t) 393 struct tegra_spi_data *tspi, struct spi_transfer *t)
412{ 394{
413 unsigned len;
414
415 /* Make the dma buffer to read by cpu */ 395 /* Make the dma buffer to read by cpu */
416 dma_sync_single_for_cpu(tspi->dev, tspi->rx_dma_phys, 396 dma_sync_single_for_cpu(tspi->dev, tspi->rx_dma_phys,
417 tspi->dma_buf_size, DMA_FROM_DEVICE); 397 tspi->dma_buf_size, DMA_FROM_DEVICE);
418 398
419 if (tspi->is_packed) { 399 if (tspi->is_packed) {
420 len = tspi->curr_dma_words * tspi->bytes_per_word; 400 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word;
421 memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len); 401 memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len);
422 } else { 402 } else {
423 unsigned int i; 403 unsigned int i;
424 unsigned int count; 404 unsigned int count;
425 unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos; 405 unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos;
426 unsigned int x; 406 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
427 unsigned int rx_mask;
428 unsigned int bits_per_word = t->bits_per_word;
429 407
430 rx_mask = (1 << bits_per_word) - 1;
431 for (count = 0; count < tspi->curr_dma_words; count++) { 408 for (count = 0; count < tspi->curr_dma_words; count++) {
432 x = tspi->rx_dma_buf[count]; 409 u32 x = tspi->rx_dma_buf[count] & rx_mask;
433 x &= rx_mask;
434 for (i = 0; (i < tspi->bytes_per_word); i++) 410 for (i = 0; (i < tspi->bytes_per_word); i++)
435 *rx_buf++ = (x >> (i*8)) & 0xFF; 411 *rx_buf++ = (x >> (i*8)) & 0xFF;
436 } 412 }
@@ -490,16 +466,16 @@ static int tegra_spi_start_rx_dma(struct tegra_spi_data *tspi, int len)
490static int tegra_spi_start_dma_based_transfer( 466static int tegra_spi_start_dma_based_transfer(
491 struct tegra_spi_data *tspi, struct spi_transfer *t) 467 struct tegra_spi_data *tspi, struct spi_transfer *t)
492{ 468{
493 unsigned long val; 469 u32 val;
494 unsigned int len; 470 unsigned int len;
495 int ret = 0; 471 int ret = 0;
496 unsigned long status; 472 u32 status;
497 473
498 /* Make sure that Rx and Tx fifo are empty */ 474 /* Make sure that Rx and Tx fifo are empty */
499 status = tegra_spi_readl(tspi, SPI_FIFO_STATUS); 475 status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
500 if ((status & SPI_FIFO_EMPTY) != SPI_FIFO_EMPTY) { 476 if ((status & SPI_FIFO_EMPTY) != SPI_FIFO_EMPTY) {
501 dev_err(tspi->dev, 477 dev_err(tspi->dev, "Rx/Tx fifo are not empty status 0x%08x\n",
502 "Rx/Tx fifo are not empty status 0x%08lx\n", status); 478 (unsigned)status);
503 return -EIO; 479 return -EIO;
504 } 480 }
505 481
@@ -564,7 +540,7 @@ static int tegra_spi_start_dma_based_transfer(
564static int tegra_spi_start_cpu_based_transfer( 540static int tegra_spi_start_cpu_based_transfer(
565 struct tegra_spi_data *tspi, struct spi_transfer *t) 541 struct tegra_spi_data *tspi, struct spi_transfer *t)
566{ 542{
567 unsigned long val; 543 u32 val;
568 unsigned cur_words; 544 unsigned cur_words;
569 545
570 if (tspi->cur_direction & DATA_DIR_TX) 546 if (tspi->cur_direction & DATA_DIR_TX)
@@ -676,13 +652,13 @@ static void tegra_spi_deinit_dma_param(struct tegra_spi_data *tspi,
676 dma_release_channel(dma_chan); 652 dma_release_channel(dma_chan);
677} 653}
678 654
679static unsigned long tegra_spi_setup_transfer_one(struct spi_device *spi, 655static u32 tegra_spi_setup_transfer_one(struct spi_device *spi,
680 struct spi_transfer *t, bool is_first_of_msg) 656 struct spi_transfer *t, bool is_first_of_msg)
681{ 657{
682 struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master); 658 struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
683 u32 speed = t->speed_hz; 659 u32 speed = t->speed_hz;
684 u8 bits_per_word = t->bits_per_word; 660 u8 bits_per_word = t->bits_per_word;
685 unsigned long command1; 661 u32 command1;
686 int req_mode; 662 int req_mode;
687 663
688 if (speed != tspi->cur_speed) { 664 if (speed != tspi->cur_speed) {
@@ -737,7 +713,7 @@ static unsigned long tegra_spi_setup_transfer_one(struct spi_device *spi,
737} 713}
738 714
739static int tegra_spi_start_transfer_one(struct spi_device *spi, 715static int tegra_spi_start_transfer_one(struct spi_device *spi,
740 struct spi_transfer *t, unsigned long command1) 716 struct spi_transfer *t, u32 command1)
741{ 717{
742 struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master); 718 struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
743 unsigned total_fifo_words; 719 unsigned total_fifo_words;
@@ -762,8 +738,8 @@ static int tegra_spi_start_transfer_one(struct spi_device *spi,
762 tegra_spi_writel(tspi, command1, SPI_COMMAND1); 738 tegra_spi_writel(tspi, command1, SPI_COMMAND1);
763 tspi->command1_reg = command1; 739 tspi->command1_reg = command1;
764 740
765 dev_dbg(tspi->dev, "The def 0x%x and written 0x%lx\n", 741 dev_dbg(tspi->dev, "The def 0x%x and written 0x%x\n",
766 tspi->def_command1_reg, command1); 742 tspi->def_command1_reg, (unsigned)command1);
767 743
768 if (total_fifo_words > SPI_FIFO_DEPTH) 744 if (total_fifo_words > SPI_FIFO_DEPTH)
769 ret = tegra_spi_start_dma_based_transfer(tspi, t); 745 ret = tegra_spi_start_dma_based_transfer(tspi, t);
@@ -775,15 +751,9 @@ static int tegra_spi_start_transfer_one(struct spi_device *spi,
775static int tegra_spi_setup(struct spi_device *spi) 751static int tegra_spi_setup(struct spi_device *spi)
776{ 752{
777 struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master); 753 struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
778 unsigned long val; 754 u32 val;
779 unsigned long flags; 755 unsigned long flags;
780 int ret; 756 int ret;
781 unsigned int cs_pol_bit[MAX_CHIP_SELECT] = {
782 SPI_CS_POL_INACTIVE_0,
783 SPI_CS_POL_INACTIVE_1,
784 SPI_CS_POL_INACTIVE_2,
785 SPI_CS_POL_INACTIVE_3,
786 };
787 757
788 dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n", 758 dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n",
789 spi->bits_per_word, 759 spi->bits_per_word,
@@ -805,9 +775,9 @@ static int tegra_spi_setup(struct spi_device *spi)
805 spin_lock_irqsave(&tspi->lock, flags); 775 spin_lock_irqsave(&tspi->lock, flags);
806 val = tspi->def_command1_reg; 776 val = tspi->def_command1_reg;
807 if (spi->mode & SPI_CS_HIGH) 777 if (spi->mode & SPI_CS_HIGH)
808 val &= ~cs_pol_bit[spi->chip_select]; 778 val &= ~SPI_CS_POL_INACTIVE(spi->chip_select);
809 else 779 else
810 val |= cs_pol_bit[spi->chip_select]; 780 val |= SPI_CS_POL_INACTIVE(spi->chip_select);
811 tspi->def_command1_reg = val; 781 tspi->def_command1_reg = val;
812 tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1); 782 tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
813 spin_unlock_irqrestore(&tspi->lock, flags); 783 spin_unlock_irqrestore(&tspi->lock, flags);
@@ -841,7 +811,7 @@ static int tegra_spi_transfer_one_message(struct spi_master *master,
841 msg->actual_length = 0; 811 msg->actual_length = 0;
842 812
843 list_for_each_entry(xfer, &msg->transfers, transfer_list) { 813 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
844 unsigned long cmd1; 814 u32 cmd1;
845 815
846 reinit_completion(&tspi->xfer_completion); 816 reinit_completion(&tspi->xfer_completion);
847 817
diff --git a/drivers/spi/spi-tegra20-sflash.c b/drivers/spi/spi-tegra20-sflash.c
index e6f382b33818..08794977f21a 100644
--- a/drivers/spi/spi-tegra20-sflash.c
+++ b/drivers/spi/spi-tegra20-sflash.c
@@ -149,14 +149,14 @@ struct tegra_sflash_data {
149static int tegra_sflash_runtime_suspend(struct device *dev); 149static int tegra_sflash_runtime_suspend(struct device *dev);
150static int tegra_sflash_runtime_resume(struct device *dev); 150static int tegra_sflash_runtime_resume(struct device *dev);
151 151
152static inline unsigned long tegra_sflash_readl(struct tegra_sflash_data *tsd, 152static inline u32 tegra_sflash_readl(struct tegra_sflash_data *tsd,
153 unsigned long reg) 153 unsigned long reg)
154{ 154{
155 return readl(tsd->base + reg); 155 return readl(tsd->base + reg);
156} 156}
157 157
158static inline void tegra_sflash_writel(struct tegra_sflash_data *tsd, 158static inline void tegra_sflash_writel(struct tegra_sflash_data *tsd,
159 unsigned long val, unsigned long reg) 159 u32 val, unsigned long reg)
160{ 160{
161 writel(val, tsd->base + reg); 161 writel(val, tsd->base + reg);
162} 162}
@@ -186,7 +186,7 @@ static unsigned tegra_sflash_fill_tx_fifo_from_client_txbuf(
186 struct tegra_sflash_data *tsd, struct spi_transfer *t) 186 struct tegra_sflash_data *tsd, struct spi_transfer *t)
187{ 187{
188 unsigned nbytes; 188 unsigned nbytes;
189 unsigned long status; 189 u32 status;
190 unsigned max_n_32bit = tsd->curr_xfer_words; 190 unsigned max_n_32bit = tsd->curr_xfer_words;
191 u8 *tx_buf = (u8 *)t->tx_buf + tsd->cur_tx_pos; 191 u8 *tx_buf = (u8 *)t->tx_buf + tsd->cur_tx_pos;
192 192
@@ -197,11 +197,11 @@ static unsigned tegra_sflash_fill_tx_fifo_from_client_txbuf(
197 status = tegra_sflash_readl(tsd, SPI_STATUS); 197 status = tegra_sflash_readl(tsd, SPI_STATUS);
198 while (!(status & SPI_TXF_FULL)) { 198 while (!(status & SPI_TXF_FULL)) {
199 int i; 199 int i;
200 unsigned int x = 0; 200 u32 x = 0;
201 201
202 for (i = 0; nbytes && (i < tsd->bytes_per_word); 202 for (i = 0; nbytes && (i < tsd->bytes_per_word);
203 i++, nbytes--) 203 i++, nbytes--)
204 x |= ((*tx_buf++) << i*8); 204 x |= (u32)(*tx_buf++) << (i * 8);
205 tegra_sflash_writel(tsd, x, SPI_TX_FIFO); 205 tegra_sflash_writel(tsd, x, SPI_TX_FIFO);
206 if (!nbytes) 206 if (!nbytes)
207 break; 207 break;
@@ -215,16 +215,14 @@ static unsigned tegra_sflash_fill_tx_fifo_from_client_txbuf(
215static int tegra_sflash_read_rx_fifo_to_client_rxbuf( 215static int tegra_sflash_read_rx_fifo_to_client_rxbuf(
216 struct tegra_sflash_data *tsd, struct spi_transfer *t) 216 struct tegra_sflash_data *tsd, struct spi_transfer *t)
217{ 217{
218 unsigned long status; 218 u32 status;
219 unsigned int read_words = 0; 219 unsigned int read_words = 0;
220 u8 *rx_buf = (u8 *)t->rx_buf + tsd->cur_rx_pos; 220 u8 *rx_buf = (u8 *)t->rx_buf + tsd->cur_rx_pos;
221 221
222 status = tegra_sflash_readl(tsd, SPI_STATUS); 222 status = tegra_sflash_readl(tsd, SPI_STATUS);
223 while (!(status & SPI_RXF_EMPTY)) { 223 while (!(status & SPI_RXF_EMPTY)) {
224 int i; 224 int i;
225 unsigned long x; 225 u32 x = tegra_sflash_readl(tsd, SPI_RX_FIFO);
226
227 x = tegra_sflash_readl(tsd, SPI_RX_FIFO);
228 for (i = 0; (i < tsd->bytes_per_word); i++) 226 for (i = 0; (i < tsd->bytes_per_word); i++)
229 *rx_buf++ = (x >> (i*8)) & 0xFF; 227 *rx_buf++ = (x >> (i*8)) & 0xFF;
230 read_words++; 228 read_words++;
@@ -237,7 +235,7 @@ static int tegra_sflash_read_rx_fifo_to_client_rxbuf(
237static int tegra_sflash_start_cpu_based_transfer( 235static int tegra_sflash_start_cpu_based_transfer(
238 struct tegra_sflash_data *tsd, struct spi_transfer *t) 236 struct tegra_sflash_data *tsd, struct spi_transfer *t)
239{ 237{
240 unsigned long val = 0; 238 u32 val = 0;
241 unsigned cur_words; 239 unsigned cur_words;
242 240
243 if (tsd->cur_direction & DATA_DIR_TX) 241 if (tsd->cur_direction & DATA_DIR_TX)
@@ -267,7 +265,7 @@ static int tegra_sflash_start_transfer_one(struct spi_device *spi,
267{ 265{
268 struct tegra_sflash_data *tsd = spi_master_get_devdata(spi->master); 266 struct tegra_sflash_data *tsd = spi_master_get_devdata(spi->master);
269 u32 speed; 267 u32 speed;
270 unsigned long command; 268 u32 command;
271 269
272 speed = t->speed_hz; 270 speed = t->speed_hz;
273 if (speed != tsd->cur_speed) { 271 if (speed != tsd->cur_speed) {
@@ -314,7 +312,7 @@ static int tegra_sflash_start_transfer_one(struct spi_device *spi,
314 tegra_sflash_writel(tsd, command, SPI_COMMAND); 312 tegra_sflash_writel(tsd, command, SPI_COMMAND);
315 tsd->command_reg = command; 313 tsd->command_reg = command;
316 314
317 return tegra_sflash_start_cpu_based_transfer(tsd, t); 315 return tegra_sflash_start_cpu_based_transfer(tsd, t);
318} 316}
319 317
320static int tegra_sflash_setup(struct spi_device *spi) 318static int tegra_sflash_setup(struct spi_device *spi)
diff --git a/drivers/spi/spi-tegra20-slink.c b/drivers/spi/spi-tegra20-slink.c
index a728bb82090f..be3a069879c3 100644
--- a/drivers/spi/spi-tegra20-slink.c
+++ b/drivers/spi/spi-tegra20-slink.c
@@ -196,7 +196,7 @@ struct tegra_slink_data {
196 u32 rx_status; 196 u32 rx_status;
197 u32 status_reg; 197 u32 status_reg;
198 bool is_packed; 198 bool is_packed;
199 unsigned long packed_size; 199 u32 packed_size;
200 200
201 u32 command_reg; 201 u32 command_reg;
202 u32 command2_reg; 202 u32 command2_reg;
@@ -220,14 +220,14 @@ struct tegra_slink_data {
220static int tegra_slink_runtime_suspend(struct device *dev); 220static int tegra_slink_runtime_suspend(struct device *dev);
221static int tegra_slink_runtime_resume(struct device *dev); 221static int tegra_slink_runtime_resume(struct device *dev);
222 222
223static inline unsigned long tegra_slink_readl(struct tegra_slink_data *tspi, 223static inline u32 tegra_slink_readl(struct tegra_slink_data *tspi,
224 unsigned long reg) 224 unsigned long reg)
225{ 225{
226 return readl(tspi->base + reg); 226 return readl(tspi->base + reg);
227} 227}
228 228
229static inline void tegra_slink_writel(struct tegra_slink_data *tspi, 229static inline void tegra_slink_writel(struct tegra_slink_data *tspi,
230 unsigned long val, unsigned long reg) 230 u32 val, unsigned long reg)
231{ 231{
232 writel(val, tspi->base + reg); 232 writel(val, tspi->base + reg);
233 233
@@ -238,38 +238,30 @@ static inline void tegra_slink_writel(struct tegra_slink_data *tspi,
238 238
239static void tegra_slink_clear_status(struct tegra_slink_data *tspi) 239static void tegra_slink_clear_status(struct tegra_slink_data *tspi)
240{ 240{
241 unsigned long val; 241 u32 val_write;
242 unsigned long val_write = 0;
243 242
244 val = tegra_slink_readl(tspi, SLINK_STATUS); 243 tegra_slink_readl(tspi, SLINK_STATUS);
245 244
246 /* Write 1 to clear status register */ 245 /* Write 1 to clear status register */
247 val_write = SLINK_RDY | SLINK_FIFO_ERROR; 246 val_write = SLINK_RDY | SLINK_FIFO_ERROR;
248 tegra_slink_writel(tspi, val_write, SLINK_STATUS); 247 tegra_slink_writel(tspi, val_write, SLINK_STATUS);
249} 248}
250 249
251static unsigned long tegra_slink_get_packed_size(struct tegra_slink_data *tspi, 250static u32 tegra_slink_get_packed_size(struct tegra_slink_data *tspi,
252 struct spi_transfer *t) 251 struct spi_transfer *t)
253{ 252{
254 unsigned long val;
255
256 switch (tspi->bytes_per_word) { 253 switch (tspi->bytes_per_word) {
257 case 0: 254 case 0:
258 val = SLINK_PACK_SIZE_4; 255 return SLINK_PACK_SIZE_4;
259 break;
260 case 1: 256 case 1:
261 val = SLINK_PACK_SIZE_8; 257 return SLINK_PACK_SIZE_8;
262 break;
263 case 2: 258 case 2:
264 val = SLINK_PACK_SIZE_16; 259 return SLINK_PACK_SIZE_16;
265 break;
266 case 4: 260 case 4:
267 val = SLINK_PACK_SIZE_32; 261 return SLINK_PACK_SIZE_32;
268 break;
269 default: 262 default:
270 val = 0; 263 return 0;
271 } 264 }
272 return val;
273} 265}
274 266
275static unsigned tegra_slink_calculate_curr_xfer_param( 267static unsigned tegra_slink_calculate_curr_xfer_param(
@@ -312,10 +304,9 @@ static unsigned tegra_slink_fill_tx_fifo_from_client_txbuf(
312{ 304{
313 unsigned nbytes; 305 unsigned nbytes;
314 unsigned tx_empty_count; 306 unsigned tx_empty_count;
315 unsigned long fifo_status; 307 u32 fifo_status;
316 unsigned max_n_32bit; 308 unsigned max_n_32bit;
317 unsigned i, count; 309 unsigned i, count;
318 unsigned long x;
319 unsigned int written_words; 310 unsigned int written_words;
320 unsigned fifo_words_left; 311 unsigned fifo_words_left;
321 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos; 312 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
@@ -329,9 +320,9 @@ static unsigned tegra_slink_fill_tx_fifo_from_client_txbuf(
329 nbytes = written_words * tspi->bytes_per_word; 320 nbytes = written_words * tspi->bytes_per_word;
330 max_n_32bit = DIV_ROUND_UP(nbytes, 4); 321 max_n_32bit = DIV_ROUND_UP(nbytes, 4);
331 for (count = 0; count < max_n_32bit; count++) { 322 for (count = 0; count < max_n_32bit; count++) {
332 x = 0; 323 u32 x = 0;
333 for (i = 0; (i < 4) && nbytes; i++, nbytes--) 324 for (i = 0; (i < 4) && nbytes; i++, nbytes--)
334 x |= (*tx_buf++) << (i*8); 325 x |= (u32)(*tx_buf++) << (i * 8);
335 tegra_slink_writel(tspi, x, SLINK_TX_FIFO); 326 tegra_slink_writel(tspi, x, SLINK_TX_FIFO);
336 } 327 }
337 } else { 328 } else {
@@ -339,10 +330,10 @@ static unsigned tegra_slink_fill_tx_fifo_from_client_txbuf(
339 written_words = max_n_32bit; 330 written_words = max_n_32bit;
340 nbytes = written_words * tspi->bytes_per_word; 331 nbytes = written_words * tspi->bytes_per_word;
341 for (count = 0; count < max_n_32bit; count++) { 332 for (count = 0; count < max_n_32bit; count++) {
342 x = 0; 333 u32 x = 0;
343 for (i = 0; nbytes && (i < tspi->bytes_per_word); 334 for (i = 0; nbytes && (i < tspi->bytes_per_word);
344 i++, nbytes--) 335 i++, nbytes--)
345 x |= ((*tx_buf++) << i*8); 336 x |= (u32)(*tx_buf++) << (i * 8);
346 tegra_slink_writel(tspi, x, SLINK_TX_FIFO); 337 tegra_slink_writel(tspi, x, SLINK_TX_FIFO);
347 } 338 }
348 } 339 }
@@ -354,9 +345,8 @@ static unsigned int tegra_slink_read_rx_fifo_to_client_rxbuf(
354 struct tegra_slink_data *tspi, struct spi_transfer *t) 345 struct tegra_slink_data *tspi, struct spi_transfer *t)
355{ 346{
356 unsigned rx_full_count; 347 unsigned rx_full_count;
357 unsigned long fifo_status; 348 u32 fifo_status;
358 unsigned i, count; 349 unsigned i, count;
359 unsigned long x;
360 unsigned int read_words = 0; 350 unsigned int read_words = 0;
361 unsigned len; 351 unsigned len;
362 u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos; 352 u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos;
@@ -366,7 +356,7 @@ static unsigned int tegra_slink_read_rx_fifo_to_client_rxbuf(
366 if (tspi->is_packed) { 356 if (tspi->is_packed) {
367 len = tspi->curr_dma_words * tspi->bytes_per_word; 357 len = tspi->curr_dma_words * tspi->bytes_per_word;
368 for (count = 0; count < rx_full_count; count++) { 358 for (count = 0; count < rx_full_count; count++) {
369 x = tegra_slink_readl(tspi, SLINK_RX_FIFO); 359 u32 x = tegra_slink_readl(tspi, SLINK_RX_FIFO);
370 for (i = 0; len && (i < 4); i++, len--) 360 for (i = 0; len && (i < 4); i++, len--)
371 *rx_buf++ = (x >> i*8) & 0xFF; 361 *rx_buf++ = (x >> i*8) & 0xFF;
372 } 362 }
@@ -374,7 +364,7 @@ static unsigned int tegra_slink_read_rx_fifo_to_client_rxbuf(
374 read_words += tspi->curr_dma_words; 364 read_words += tspi->curr_dma_words;
375 } else { 365 } else {
376 for (count = 0; count < rx_full_count; count++) { 366 for (count = 0; count < rx_full_count; count++) {
377 x = tegra_slink_readl(tspi, SLINK_RX_FIFO); 367 u32 x = tegra_slink_readl(tspi, SLINK_RX_FIFO);
378 for (i = 0; (i < tspi->bytes_per_word); i++) 368 for (i = 0; (i < tspi->bytes_per_word); i++)
379 *rx_buf++ = (x >> (i*8)) & 0xFF; 369 *rx_buf++ = (x >> (i*8)) & 0xFF;
380 } 370 }
@@ -387,27 +377,24 @@ static unsigned int tegra_slink_read_rx_fifo_to_client_rxbuf(
387static void tegra_slink_copy_client_txbuf_to_spi_txbuf( 377static void tegra_slink_copy_client_txbuf_to_spi_txbuf(
388 struct tegra_slink_data *tspi, struct spi_transfer *t) 378 struct tegra_slink_data *tspi, struct spi_transfer *t)
389{ 379{
390 unsigned len;
391
392 /* Make the dma buffer to read by cpu */ 380 /* Make the dma buffer to read by cpu */
393 dma_sync_single_for_cpu(tspi->dev, tspi->tx_dma_phys, 381 dma_sync_single_for_cpu(tspi->dev, tspi->tx_dma_phys,
394 tspi->dma_buf_size, DMA_TO_DEVICE); 382 tspi->dma_buf_size, DMA_TO_DEVICE);
395 383
396 if (tspi->is_packed) { 384 if (tspi->is_packed) {
397 len = tspi->curr_dma_words * tspi->bytes_per_word; 385 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word;
398 memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len); 386 memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len);
399 } else { 387 } else {
400 unsigned int i; 388 unsigned int i;
401 unsigned int count; 389 unsigned int count;
402 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos; 390 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
403 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word; 391 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word;
404 unsigned int x;
405 392
406 for (count = 0; count < tspi->curr_dma_words; count++) { 393 for (count = 0; count < tspi->curr_dma_words; count++) {
407 x = 0; 394 u32 x = 0;
408 for (i = 0; consume && (i < tspi->bytes_per_word); 395 for (i = 0; consume && (i < tspi->bytes_per_word);
409 i++, consume--) 396 i++, consume--)
410 x |= ((*tx_buf++) << i * 8); 397 x |= (u32)(*tx_buf++) << (i * 8);
411 tspi->tx_dma_buf[count] = x; 398 tspi->tx_dma_buf[count] = x;
412 } 399 }
413 } 400 }
@@ -434,14 +421,10 @@ static void tegra_slink_copy_spi_rxbuf_to_client_rxbuf(
434 unsigned int i; 421 unsigned int i;
435 unsigned int count; 422 unsigned int count;
436 unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos; 423 unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos;
437 unsigned int x; 424 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
438 unsigned int rx_mask, bits_per_word;
439 425
440 bits_per_word = t->bits_per_word;
441 rx_mask = (1 << bits_per_word) - 1;
442 for (count = 0; count < tspi->curr_dma_words; count++) { 426 for (count = 0; count < tspi->curr_dma_words; count++) {
443 x = tspi->rx_dma_buf[count]; 427 u32 x = tspi->rx_dma_buf[count] & rx_mask;
444 x &= rx_mask;
445 for (i = 0; (i < tspi->bytes_per_word); i++) 428 for (i = 0; (i < tspi->bytes_per_word); i++)
446 *rx_buf++ = (x >> (i*8)) & 0xFF; 429 *rx_buf++ = (x >> (i*8)) & 0xFF;
447 } 430 }
@@ -501,17 +484,16 @@ static int tegra_slink_start_rx_dma(struct tegra_slink_data *tspi, int len)
501static int tegra_slink_start_dma_based_transfer( 484static int tegra_slink_start_dma_based_transfer(
502 struct tegra_slink_data *tspi, struct spi_transfer *t) 485 struct tegra_slink_data *tspi, struct spi_transfer *t)
503{ 486{
504 unsigned long val; 487 u32 val;
505 unsigned long test_val;
506 unsigned int len; 488 unsigned int len;
507 int ret = 0; 489 int ret = 0;
508 unsigned long status; 490 u32 status;
509 491
510 /* Make sure that Rx and Tx fifo are empty */ 492 /* Make sure that Rx and Tx fifo are empty */
511 status = tegra_slink_readl(tspi, SLINK_STATUS); 493 status = tegra_slink_readl(tspi, SLINK_STATUS);
512 if ((status & SLINK_FIFO_EMPTY) != SLINK_FIFO_EMPTY) { 494 if ((status & SLINK_FIFO_EMPTY) != SLINK_FIFO_EMPTY) {
513 dev_err(tspi->dev, 495 dev_err(tspi->dev, "Rx/Tx fifo are not empty status 0x%08x\n",
514 "Rx/Tx fifo are not empty status 0x%08lx\n", status); 496 (unsigned)status);
515 return -EIO; 497 return -EIO;
516 } 498 }
517 499
@@ -551,9 +533,9 @@ static int tegra_slink_start_dma_based_transfer(
551 } 533 }
552 534
553 /* Wait for tx fifo to be fill before starting slink */ 535 /* Wait for tx fifo to be fill before starting slink */
554 test_val = tegra_slink_readl(tspi, SLINK_STATUS); 536 status = tegra_slink_readl(tspi, SLINK_STATUS);
555 while (!(test_val & SLINK_TX_FULL)) 537 while (!(status & SLINK_TX_FULL))
556 test_val = tegra_slink_readl(tspi, SLINK_STATUS); 538 status = tegra_slink_readl(tspi, SLINK_STATUS);
557 } 539 }
558 540
559 if (tspi->cur_direction & DATA_DIR_RX) { 541 if (tspi->cur_direction & DATA_DIR_RX) {
@@ -587,7 +569,7 @@ static int tegra_slink_start_dma_based_transfer(
587static int tegra_slink_start_cpu_based_transfer( 569static int tegra_slink_start_cpu_based_transfer(
588 struct tegra_slink_data *tspi, struct spi_transfer *t) 570 struct tegra_slink_data *tspi, struct spi_transfer *t)
589{ 571{
590 unsigned long val; 572 u32 val;
591 unsigned cur_words; 573 unsigned cur_words;
592 574
593 val = tspi->packed_size; 575 val = tspi->packed_size;
@@ -713,8 +695,8 @@ static int tegra_slink_start_transfer_one(struct spi_device *spi,
713 u8 bits_per_word; 695 u8 bits_per_word;
714 unsigned total_fifo_words; 696 unsigned total_fifo_words;
715 int ret; 697 int ret;
716 unsigned long command; 698 u32 command;
717 unsigned long command2; 699 u32 command2;
718 700
719 bits_per_word = t->bits_per_word; 701 bits_per_word = t->bits_per_word;
720 speed = t->speed_hz; 702 speed = t->speed_hz;
@@ -761,17 +743,18 @@ static int tegra_slink_start_transfer_one(struct spi_device *spi,
761 743
762static int tegra_slink_setup(struct spi_device *spi) 744static int tegra_slink_setup(struct spi_device *spi)
763{ 745{
764 struct tegra_slink_data *tspi = spi_master_get_devdata(spi->master); 746 static const u32 cs_pol_bit[MAX_CHIP_SELECT] = {
765 unsigned long val;
766 unsigned long flags;
767 int ret;
768 unsigned int cs_pol_bit[MAX_CHIP_SELECT] = {
769 SLINK_CS_POLARITY, 747 SLINK_CS_POLARITY,
770 SLINK_CS_POLARITY1, 748 SLINK_CS_POLARITY1,
771 SLINK_CS_POLARITY2, 749 SLINK_CS_POLARITY2,
772 SLINK_CS_POLARITY3, 750 SLINK_CS_POLARITY3,
773 }; 751 };
774 752
753 struct tegra_slink_data *tspi = spi_master_get_devdata(spi->master);
754 u32 val;
755 unsigned long flags;
756 int ret;
757
775 dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n", 758 dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n",
776 spi->bits_per_word, 759 spi->bits_per_word,
777 spi->mode & SPI_CPOL ? "" : "~", 760 spi->mode & SPI_CPOL ? "" : "~",
diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
index 4396bd448540..3d09265b5133 100644
--- a/drivers/spi/spi-ti-qspi.c
+++ b/drivers/spi/spi-ti-qspi.c
@@ -46,6 +46,8 @@ struct ti_qspi {
46 46
47 struct spi_master *master; 47 struct spi_master *master;
48 void __iomem *base; 48 void __iomem *base;
49 void __iomem *ctrl_base;
50 void __iomem *mmap_base;
49 struct clk *fclk; 51 struct clk *fclk;
50 struct device *dev; 52 struct device *dev;
51 53
@@ -54,6 +56,8 @@ struct ti_qspi {
54 u32 spi_max_frequency; 56 u32 spi_max_frequency;
55 u32 cmd; 57 u32 cmd;
56 u32 dc; 58 u32 dc;
59
60 bool ctrl_mod;
57}; 61};
58 62
59#define QSPI_PID (0x0) 63#define QSPI_PID (0x0)
@@ -204,53 +208,36 @@ static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t)
204 txbuf = t->tx_buf; 208 txbuf = t->tx_buf;
205 cmd = qspi->cmd | QSPI_WR_SNGL; 209 cmd = qspi->cmd | QSPI_WR_SNGL;
206 count = t->len; 210 count = t->len;
207 wlen = t->bits_per_word; 211 wlen = t->bits_per_word >> 3; /* in bytes */
208 212
209 while (count) { 213 while (count) {
210 switch (wlen) { 214 switch (wlen) {
211 case 8: 215 case 1:
212 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n", 216 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n",
213 cmd, qspi->dc, *txbuf); 217 cmd, qspi->dc, *txbuf);
214 writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG); 218 writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG);
215 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
216 ret = wait_for_completion_timeout(&qspi->transfer_complete,
217 QSPI_COMPLETION_TIMEOUT);
218 if (ret == 0) {
219 dev_err(qspi->dev, "write timed out\n");
220 return -ETIMEDOUT;
221 }
222 txbuf += 1;
223 count -= 1;
224 break; 219 break;
225 case 16: 220 case 2:
226 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n", 221 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n",
227 cmd, qspi->dc, *txbuf); 222 cmd, qspi->dc, *txbuf);
228 writew(*((u16 *)txbuf), qspi->base + QSPI_SPI_DATA_REG); 223 writew(*((u16 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
229 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
230 ret = wait_for_completion_timeout(&qspi->transfer_complete,
231 QSPI_COMPLETION_TIMEOUT);
232 if (ret == 0) {
233 dev_err(qspi->dev, "write timed out\n");
234 return -ETIMEDOUT;
235 }
236 txbuf += 2;
237 count -= 2;
238 break; 224 break;
239 case 32: 225 case 4:
240 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n", 226 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n",
241 cmd, qspi->dc, *txbuf); 227 cmd, qspi->dc, *txbuf);
242 writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG); 228 writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
243 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
244 ret = wait_for_completion_timeout(&qspi->transfer_complete,
245 QSPI_COMPLETION_TIMEOUT);
246 if (ret == 0) {
247 dev_err(qspi->dev, "write timed out\n");
248 return -ETIMEDOUT;
249 }
250 txbuf += 4;
251 count -= 4;
252 break; 229 break;
253 } 230 }
231
232 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
233 ret = wait_for_completion_timeout(&qspi->transfer_complete,
234 QSPI_COMPLETION_TIMEOUT);
235 if (ret == 0) {
236 dev_err(qspi->dev, "write timed out\n");
237 return -ETIMEDOUT;
238 }
239 txbuf += wlen;
240 count -= wlen;
254 } 241 }
255 242
256 return 0; 243 return 0;
@@ -276,7 +263,7 @@ static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t)
276 break; 263 break;
277 } 264 }
278 count = t->len; 265 count = t->len;
279 wlen = t->bits_per_word; 266 wlen = t->bits_per_word >> 3; /* in bytes */
280 267
281 while (count) { 268 while (count) {
282 dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc); 269 dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc);
@@ -288,22 +275,18 @@ static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t)
288 return -ETIMEDOUT; 275 return -ETIMEDOUT;
289 } 276 }
290 switch (wlen) { 277 switch (wlen) {
291 case 8: 278 case 1:
292 *rxbuf = readb(qspi->base + QSPI_SPI_DATA_REG); 279 *rxbuf = readb(qspi->base + QSPI_SPI_DATA_REG);
293 rxbuf += 1;
294 count -= 1;
295 break; 280 break;
296 case 16: 281 case 2:
297 *((u16 *)rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG); 282 *((u16 *)rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG);
298 rxbuf += 2;
299 count -= 2;
300 break; 283 break;
301 case 32: 284 case 4:
302 *((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG); 285 *((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG);
303 rxbuf += 4;
304 count -= 4;
305 break; 286 break;
306 } 287 }
288 rxbuf += wlen;
289 count -= wlen;
307 } 290 }
308 291
309 return 0; 292 return 0;
@@ -417,10 +400,8 @@ out:
417static int ti_qspi_runtime_resume(struct device *dev) 400static int ti_qspi_runtime_resume(struct device *dev)
418{ 401{
419 struct ti_qspi *qspi; 402 struct ti_qspi *qspi;
420 struct spi_master *master;
421 403
422 master = dev_get_drvdata(dev); 404 qspi = dev_get_drvdata(dev);
423 qspi = spi_master_get_devdata(master);
424 ti_qspi_restore_ctx(qspi); 405 ti_qspi_restore_ctx(qspi);
425 406
426 return 0; 407 return 0;
@@ -437,7 +418,7 @@ static int ti_qspi_probe(struct platform_device *pdev)
437{ 418{
438 struct ti_qspi *qspi; 419 struct ti_qspi *qspi;
439 struct spi_master *master; 420 struct spi_master *master;
440 struct resource *r; 421 struct resource *r, *res_ctrl, *res_mmap;
441 struct device_node *np = pdev->dev.of_node; 422 struct device_node *np = pdev->dev.of_node;
442 u32 max_freq; 423 u32 max_freq;
443 int ret = 0, num_cs, irq; 424 int ret = 0, num_cs, irq;
@@ -464,7 +445,35 @@ static int ti_qspi_probe(struct platform_device *pdev)
464 qspi->dev = &pdev->dev; 445 qspi->dev = &pdev->dev;
465 platform_set_drvdata(pdev, qspi); 446 platform_set_drvdata(pdev, qspi);
466 447
467 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 448 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
449 if (r == NULL) {
450 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
451 if (r == NULL) {
452 dev_err(&pdev->dev, "missing platform data\n");
453 return -ENODEV;
454 }
455 }
456
457 res_mmap = platform_get_resource_byname(pdev,
458 IORESOURCE_MEM, "qspi_mmap");
459 if (res_mmap == NULL) {
460 res_mmap = platform_get_resource(pdev, IORESOURCE_MEM, 1);
461 if (res_mmap == NULL) {
462 dev_err(&pdev->dev,
463 "memory mapped resource not required\n");
464 return -ENODEV;
465 }
466 }
467
468 res_ctrl = platform_get_resource_byname(pdev,
469 IORESOURCE_MEM, "qspi_ctrlmod");
470 if (res_ctrl == NULL) {
471 res_ctrl = platform_get_resource(pdev, IORESOURCE_MEM, 2);
472 if (res_ctrl == NULL) {
473 dev_dbg(&pdev->dev,
474 "control module resources not required\n");
475 }
476 }
468 477
469 irq = platform_get_irq(pdev, 0); 478 irq = platform_get_irq(pdev, 0);
470 if (irq < 0) { 479 if (irq < 0) {
@@ -480,6 +489,23 @@ static int ti_qspi_probe(struct platform_device *pdev)
480 goto free_master; 489 goto free_master;
481 } 490 }
482 491
492 if (res_ctrl) {
493 qspi->ctrl_mod = true;
494 qspi->ctrl_base = devm_ioremap_resource(&pdev->dev, res_ctrl);
495 if (IS_ERR(qspi->ctrl_base)) {
496 ret = PTR_ERR(qspi->ctrl_base);
497 goto free_master;
498 }
499 }
500
501 if (res_mmap) {
502 qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap);
503 if (IS_ERR(qspi->mmap_base)) {
504 ret = PTR_ERR(qspi->mmap_base);
505 goto free_master;
506 }
507 }
508
483 ret = devm_request_irq(&pdev->dev, irq, ti_qspi_isr, 0, 509 ret = devm_request_irq(&pdev->dev, irq, ti_qspi_isr, 0,
484 dev_name(&pdev->dev), qspi); 510 dev_name(&pdev->dev), qspi);
485 if (ret < 0) { 511 if (ret < 0) {
@@ -516,13 +542,9 @@ free_master:
516 542
517static int ti_qspi_remove(struct platform_device *pdev) 543static int ti_qspi_remove(struct platform_device *pdev)
518{ 544{
519 struct spi_master *master; 545 struct ti_qspi *qspi = platform_get_drvdata(pdev);
520 struct ti_qspi *qspi;
521 int ret; 546 int ret;
522 547
523 master = platform_get_drvdata(pdev);
524 qspi = spi_master_get_devdata(master);
525
526 ret = pm_runtime_get_sync(qspi->dev); 548 ret = pm_runtime_get_sync(qspi->dev);
527 if (ret < 0) { 549 if (ret < 0) {
528 dev_err(qspi->dev, "pm_runtime_get_sync() failed\n"); 550 dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
@@ -534,8 +556,6 @@ static int ti_qspi_remove(struct platform_device *pdev)
534 pm_runtime_put(qspi->dev); 556 pm_runtime_put(qspi->dev);
535 pm_runtime_disable(&pdev->dev); 557 pm_runtime_disable(&pdev->dev);
536 558
537 spi_unregister_master(master);
538
539 return 0; 559 return 0;
540} 560}
541 561
@@ -547,7 +567,7 @@ static struct platform_driver ti_qspi_driver = {
547 .probe = ti_qspi_probe, 567 .probe = ti_qspi_probe,
548 .remove = ti_qspi_remove, 568 .remove = ti_qspi_remove,
549 .driver = { 569 .driver = {
550 .name = "ti,dra7xxx-qspi", 570 .name = "ti-qspi",
551 .owner = THIS_MODULE, 571 .owner = THIS_MODULE,
552 .pm = &ti_qspi_pm_ops, 572 .pm = &ti_qspi_pm_ops,
553 .of_match_table = ti_qspi_match, 573 .of_match_table = ti_qspi_match,
@@ -559,3 +579,4 @@ module_platform_driver(ti_qspi_driver);
559MODULE_AUTHOR("Sourav Poddar <sourav.poddar@ti.com>"); 579MODULE_AUTHOR("Sourav Poddar <sourav.poddar@ti.com>");
560MODULE_LICENSE("GPL v2"); 580MODULE_LICENSE("GPL v2");
561MODULE_DESCRIPTION("TI QSPI controller driver"); 581MODULE_DESCRIPTION("TI QSPI controller driver");
582MODULE_ALIAS("platform:ti-qspi");
diff --git a/drivers/spi/spi-topcliff-pch.c b/drivers/spi/spi-topcliff-pch.c
index 446131308acb..2e7f38c7a961 100644
--- a/drivers/spi/spi-topcliff-pch.c
+++ b/drivers/spi/spi-topcliff-pch.c
@@ -217,7 +217,7 @@ struct pch_pd_dev_save {
217 struct pch_spi_board_data *board_dat; 217 struct pch_spi_board_data *board_dat;
218}; 218};
219 219
220static DEFINE_PCI_DEVICE_TABLE(pch_spi_pcidev_id) = { 220static const struct pci_device_id pch_spi_pcidev_id[] = {
221 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_GE_SPI), 1, }, 221 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_GE_SPI), 1, },
222 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_SPI), 2, }, 222 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_SPI), 2, },
223 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_SPI), 1, }, 223 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_SPI), 1, },
@@ -466,12 +466,6 @@ static void pch_spi_reset(struct spi_master *master)
466 466
467static int pch_spi_setup(struct spi_device *pspi) 467static int pch_spi_setup(struct spi_device *pspi)
468{ 468{
469 /* check bits per word */
470 if (pspi->bits_per_word == 0) {
471 pspi->bits_per_word = 8;
472 dev_dbg(&pspi->dev, "%s 8 bits per word\n", __func__);
473 }
474
475 /* Check baud rate setting */ 469 /* Check baud rate setting */
476 /* if baud rate of chip is greater than 470 /* if baud rate of chip is greater than
477 max we can support,return error */ 471 max we can support,return error */
diff --git a/drivers/spi/spi-txx9.c b/drivers/spi/spi-txx9.c
index 18c9bb2b5f39..6191ced514b2 100644
--- a/drivers/spi/spi-txx9.c
+++ b/drivers/spi/spi-txx9.c
@@ -348,7 +348,7 @@ static int txx9spi_probe(struct platform_device *dev)
348 INIT_LIST_HEAD(&c->queue); 348 INIT_LIST_HEAD(&c->queue);
349 init_waitqueue_head(&c->waitq); 349 init_waitqueue_head(&c->waitq);
350 350
351 c->clk = clk_get(&dev->dev, "spi-baseclk"); 351 c->clk = devm_clk_get(&dev->dev, "spi-baseclk");
352 if (IS_ERR(c->clk)) { 352 if (IS_ERR(c->clk)) {
353 ret = PTR_ERR(c->clk); 353 ret = PTR_ERR(c->clk);
354 c->clk = NULL; 354 c->clk = NULL;
@@ -356,7 +356,6 @@ static int txx9spi_probe(struct platform_device *dev)
356 } 356 }
357 ret = clk_enable(c->clk); 357 ret = clk_enable(c->clk);
358 if (ret) { 358 if (ret) {
359 clk_put(c->clk);
360 c->clk = NULL; 359 c->clk = NULL;
361 goto exit; 360 goto exit;
362 } 361 }
@@ -415,10 +414,8 @@ exit_busy:
415exit: 414exit:
416 if (c->workqueue) 415 if (c->workqueue)
417 destroy_workqueue(c->workqueue); 416 destroy_workqueue(c->workqueue);
418 if (c->clk) { 417 if (c->clk)
419 clk_disable(c->clk); 418 clk_disable(c->clk);
420 clk_put(c->clk);
421 }
422 spi_master_put(master); 419 spi_master_put(master);
423 return ret; 420 return ret;
424} 421}
@@ -430,7 +427,6 @@ static int txx9spi_remove(struct platform_device *dev)
430 427
431 destroy_workqueue(c->workqueue); 428 destroy_workqueue(c->workqueue);
432 clk_disable(c->clk); 429 clk_disable(c->clk);
433 clk_put(c->clk);
434 return 0; 430 return 0;
435} 431}
436 432
diff --git a/drivers/spi/spi-xcomm.c b/drivers/spi/spi-xcomm.c
index 4258c712ad3c..24c40b13dab1 100644
--- a/drivers/spi/spi-xcomm.c
+++ b/drivers/spi/spi-xcomm.c
@@ -231,22 +231,13 @@ static int spi_xcomm_probe(struct i2c_client *i2c,
231 master->dev.of_node = i2c->dev.of_node; 231 master->dev.of_node = i2c->dev.of_node;
232 i2c_set_clientdata(i2c, master); 232 i2c_set_clientdata(i2c, master);
233 233
234 ret = spi_register_master(master); 234 ret = devm_spi_register_master(&i2c->dev, master);
235 if (ret < 0) 235 if (ret < 0)
236 spi_master_put(master); 236 spi_master_put(master);
237 237
238 return ret; 238 return ret;
239} 239}
240 240
241static int spi_xcomm_remove(struct i2c_client *i2c)
242{
243 struct spi_master *master = i2c_get_clientdata(i2c);
244
245 spi_unregister_master(master);
246
247 return 0;
248}
249
250static const struct i2c_device_id spi_xcomm_ids[] = { 241static const struct i2c_device_id spi_xcomm_ids[] = {
251 { "spi-xcomm" }, 242 { "spi-xcomm" },
252 { }, 243 { },
@@ -259,7 +250,6 @@ static struct i2c_driver spi_xcomm_driver = {
259 }, 250 },
260 .id_table = spi_xcomm_ids, 251 .id_table = spi_xcomm_ids,
261 .probe = spi_xcomm_probe, 252 .probe = spi_xcomm_probe,
262 .remove = spi_xcomm_remove,
263}; 253};
264module_i2c_driver(spi_xcomm_driver); 254module_i2c_driver(spi_xcomm_driver);
265 255
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index 827ff49d3d4f..23756b0f9036 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -380,6 +380,17 @@ static void spi_dev_set_name(struct spi_device *spi)
380 spi->chip_select); 380 spi->chip_select);
381} 381}
382 382
383static int spi_dev_check(struct device *dev, void *data)
384{
385 struct spi_device *spi = to_spi_device(dev);
386 struct spi_device *new_spi = data;
387
388 if (spi->master == new_spi->master &&
389 spi->chip_select == new_spi->chip_select)
390 return -EBUSY;
391 return 0;
392}
393
383/** 394/**
384 * spi_add_device - Add spi_device allocated with spi_alloc_device 395 * spi_add_device - Add spi_device allocated with spi_alloc_device
385 * @spi: spi_device to register 396 * @spi: spi_device to register
@@ -394,7 +405,6 @@ int spi_add_device(struct spi_device *spi)
394 static DEFINE_MUTEX(spi_add_lock); 405 static DEFINE_MUTEX(spi_add_lock);
395 struct spi_master *master = spi->master; 406 struct spi_master *master = spi->master;
396 struct device *dev = master->dev.parent; 407 struct device *dev = master->dev.parent;
397 struct device *d;
398 int status; 408 int status;
399 409
400 /* Chipselects are numbered 0..max; validate. */ 410 /* Chipselects are numbered 0..max; validate. */
@@ -414,12 +424,10 @@ int spi_add_device(struct spi_device *spi)
414 */ 424 */
415 mutex_lock(&spi_add_lock); 425 mutex_lock(&spi_add_lock);
416 426
417 d = bus_find_device_by_name(&spi_bus_type, NULL, dev_name(&spi->dev)); 427 status = bus_for_each_dev(&spi_bus_type, NULL, spi, spi_dev_check);
418 if (d != NULL) { 428 if (status) {
419 dev_err(dev, "chipselect %d already in use\n", 429 dev_err(dev, "chipselect %d already in use\n",
420 spi->chip_select); 430 spi->chip_select);
421 put_device(d);
422 status = -EBUSY;
423 goto done; 431 goto done;
424 } 432 }
425 433
@@ -601,8 +609,10 @@ static int spi_transfer_one_message(struct spi_master *master,
601 goto out; 609 goto out;
602 } 610 }
603 611
604 if (ret > 0) 612 if (ret > 0) {
613 ret = 0;
605 wait_for_completion(&master->xfer_completion); 614 wait_for_completion(&master->xfer_completion);
615 }
606 616
607 trace_spi_transfer_stop(msg, xfer); 617 trace_spi_transfer_stop(msg, xfer);
608 618
@@ -642,7 +652,7 @@ out:
642 * 652 *
643 * Called by SPI drivers using the core transfer_one_message() 653 * Called by SPI drivers using the core transfer_one_message()
644 * implementation to notify it that the current interrupt driven 654 * implementation to notify it that the current interrupt driven
645 * transfer has finised and the next one may be scheduled. 655 * transfer has finished and the next one may be scheduled.
646 */ 656 */
647void spi_finalize_current_transfer(struct spi_master *master) 657void spi_finalize_current_transfer(struct spi_master *master)
648{ 658{
@@ -695,7 +705,7 @@ static void spi_pump_messages(struct kthread_work *work)
695 } 705 }
696 /* Extract head of queue */ 706 /* Extract head of queue */
697 master->cur_msg = 707 master->cur_msg =
698 list_entry(master->queue.next, struct spi_message, queue); 708 list_first_entry(&master->queue, struct spi_message, queue);
699 709
700 list_del_init(&master->cur_msg->queue); 710 list_del_init(&master->cur_msg->queue);
701 if (master->busy) 711 if (master->busy)
@@ -745,7 +755,9 @@ static void spi_pump_messages(struct kthread_work *work)
745 ret = master->transfer_one_message(master, master->cur_msg); 755 ret = master->transfer_one_message(master, master->cur_msg);
746 if (ret) { 756 if (ret) {
747 dev_err(&master->dev, 757 dev_err(&master->dev,
748 "failed to transfer one message from queue\n"); 758 "failed to transfer one message from queue: %d\n", ret);
759 master->cur_msg->status = ret;
760 spi_finalize_current_message(master);
749 return; 761 return;
750 } 762 }
751} 763}
@@ -801,11 +813,8 @@ struct spi_message *spi_get_next_queued_message(struct spi_master *master)
801 813
802 /* get a pointer to the next message, if any */ 814 /* get a pointer to the next message, if any */
803 spin_lock_irqsave(&master->queue_lock, flags); 815 spin_lock_irqsave(&master->queue_lock, flags);
804 if (list_empty(&master->queue)) 816 next = list_first_entry_or_null(&master->queue, struct spi_message,
805 next = NULL; 817 queue);
806 else
807 next = list_entry(master->queue.next,
808 struct spi_message, queue);
809 spin_unlock_irqrestore(&master->queue_lock, flags); 818 spin_unlock_irqrestore(&master->queue_lock, flags);
810 819
811 return next; 820 return next;
@@ -1606,15 +1615,11 @@ int spi_setup(struct spi_device *spi)
1606} 1615}
1607EXPORT_SYMBOL_GPL(spi_setup); 1616EXPORT_SYMBOL_GPL(spi_setup);
1608 1617
1609static int __spi_async(struct spi_device *spi, struct spi_message *message) 1618static int __spi_validate(struct spi_device *spi, struct spi_message *message)
1610{ 1619{
1611 struct spi_master *master = spi->master; 1620 struct spi_master *master = spi->master;
1612 struct spi_transfer *xfer; 1621 struct spi_transfer *xfer;
1613 1622
1614 message->spi = spi;
1615
1616 trace_spi_message_submit(message);
1617
1618 if (list_empty(&message->transfers)) 1623 if (list_empty(&message->transfers))
1619 return -EINVAL; 1624 return -EINVAL;
1620 if (!message->complete) 1625 if (!message->complete)
@@ -1677,9 +1682,8 @@ static int __spi_async(struct spi_device *spi, struct spi_message *message)
1677 if (xfer->rx_buf && !xfer->rx_nbits) 1682 if (xfer->rx_buf && !xfer->rx_nbits)
1678 xfer->rx_nbits = SPI_NBITS_SINGLE; 1683 xfer->rx_nbits = SPI_NBITS_SINGLE;
1679 /* check transfer tx/rx_nbits: 1684 /* check transfer tx/rx_nbits:
1680 * 1. keep the value is not out of single, dual and quad 1685 * 1. check the value matches one of single, dual and quad
1681 * 2. keep tx/rx_nbits is contained by mode in spi_device 1686 * 2. check tx/rx_nbits match the mode in spi_device
1682 * 3. if SPI_3WIRE, tx/rx_nbits should be in single
1683 */ 1687 */
1684 if (xfer->tx_buf) { 1688 if (xfer->tx_buf) {
1685 if (xfer->tx_nbits != SPI_NBITS_SINGLE && 1689 if (xfer->tx_nbits != SPI_NBITS_SINGLE &&
@@ -1692,9 +1696,6 @@ static int __spi_async(struct spi_device *spi, struct spi_message *message)
1692 if ((xfer->tx_nbits == SPI_NBITS_QUAD) && 1696 if ((xfer->tx_nbits == SPI_NBITS_QUAD) &&
1693 !(spi->mode & SPI_TX_QUAD)) 1697 !(spi->mode & SPI_TX_QUAD))
1694 return -EINVAL; 1698 return -EINVAL;
1695 if ((spi->mode & SPI_3WIRE) &&
1696 (xfer->tx_nbits != SPI_NBITS_SINGLE))
1697 return -EINVAL;
1698 } 1699 }
1699 /* check transfer rx_nbits */ 1700 /* check transfer rx_nbits */
1700 if (xfer->rx_buf) { 1701 if (xfer->rx_buf) {
@@ -1708,13 +1709,22 @@ static int __spi_async(struct spi_device *spi, struct spi_message *message)
1708 if ((xfer->rx_nbits == SPI_NBITS_QUAD) && 1709 if ((xfer->rx_nbits == SPI_NBITS_QUAD) &&
1709 !(spi->mode & SPI_RX_QUAD)) 1710 !(spi->mode & SPI_RX_QUAD))
1710 return -EINVAL; 1711 return -EINVAL;
1711 if ((spi->mode & SPI_3WIRE) &&
1712 (xfer->rx_nbits != SPI_NBITS_SINGLE))
1713 return -EINVAL;
1714 } 1712 }
1715 } 1713 }
1716 1714
1717 message->status = -EINPROGRESS; 1715 message->status = -EINPROGRESS;
1716
1717 return 0;
1718}
1719
1720static int __spi_async(struct spi_device *spi, struct spi_message *message)
1721{
1722 struct spi_master *master = spi->master;
1723
1724 message->spi = spi;
1725
1726 trace_spi_message_submit(message);
1727
1718 return master->transfer(spi, message); 1728 return master->transfer(spi, message);
1719} 1729}
1720 1730
@@ -1753,6 +1763,10 @@ int spi_async(struct spi_device *spi, struct spi_message *message)
1753 int ret; 1763 int ret;
1754 unsigned long flags; 1764 unsigned long flags;
1755 1765
1766 ret = __spi_validate(spi, message);
1767 if (ret != 0)
1768 return ret;
1769
1756 spin_lock_irqsave(&master->bus_lock_spinlock, flags); 1770 spin_lock_irqsave(&master->bus_lock_spinlock, flags);
1757 1771
1758 if (master->bus_lock_flag) 1772 if (master->bus_lock_flag)
@@ -1801,6 +1815,10 @@ int spi_async_locked(struct spi_device *spi, struct spi_message *message)
1801 int ret; 1815 int ret;
1802 unsigned long flags; 1816 unsigned long flags;
1803 1817
1818 ret = __spi_validate(spi, message);
1819 if (ret != 0)
1820 return ret;
1821
1804 spin_lock_irqsave(&master->bus_lock_spinlock, flags); 1822 spin_lock_irqsave(&master->bus_lock_spinlock, flags);
1805 1823
1806 ret = __spi_async(spi, message); 1824 ret = __spi_async(spi, message);
diff --git a/include/linux/platform_data/spi-nuc900.h b/include/linux/platform_data/spi-nuc900.h
index 2c4e0c128501..4b3f46832e19 100644
--- a/include/linux/platform_data/spi-nuc900.h
+++ b/include/linux/platform_data/spi-nuc900.h
@@ -1,6 +1,4 @@
1/* 1/*
2 * arch/arm/mach-w90x900/include/mach/nuc900_spi.h
3 *
4 * Copyright (c) 2009 Nuvoton technology corporation. 2 * Copyright (c) 2009 Nuvoton technology corporation.
5 * 3 *
6 * Wan ZongShun <mcuos.com@gmail.com> 4 * Wan ZongShun <mcuos.com@gmail.com>
@@ -11,8 +9,8 @@
11 * 9 *
12 */ 10 */
13 11
14#ifndef __ASM_ARCH_SPI_H 12#ifndef __SPI_NUC900_H
15#define __ASM_ARCH_SPI_H 13#define __SPI_NUC900_H
16 14
17extern void mfp_set_groupg(struct device *dev, const char *subname); 15extern void mfp_set_groupg(struct device *dev, const char *subname);
18 16
@@ -32,4 +30,4 @@ struct nuc900_spi_chip {
32 unsigned char bits_per_word; 30 unsigned char bits_per_word;
33}; 31};
34 32
35#endif /* __ASM_ARCH_SPI_H */ 33#endif /* __SPI_NUC900_H */
diff --git a/include/linux/spi/s3c24xx.h b/include/linux/spi/s3c24xx.h
index c23b923e493b..ca271c06c591 100644
--- a/include/linux/spi/s3c24xx.h
+++ b/include/linux/spi/s3c24xx.h
@@ -23,4 +23,6 @@ struct s3c2410_spi_info {
23 void (*set_cs)(struct s3c2410_spi_info *spi, int cs, int pol); 23 void (*set_cs)(struct s3c2410_spi_info *spi, int cs, int pol);
24}; 24};
25 25
26extern int s3c24xx_set_fiq(unsigned int irq, bool on);
27
26#endif /* __LINUX_SPI_S3C24XX_H */ 28#endif /* __LINUX_SPI_S3C24XX_H */
diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index 8c62ba74dd91..a1d4ca290862 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -75,6 +75,7 @@ struct spi_device {
75 struct spi_master *master; 75 struct spi_master *master;
76 u32 max_speed_hz; 76 u32 max_speed_hz;
77 u8 chip_select; 77 u8 chip_select;
78 u8 bits_per_word;
78 u16 mode; 79 u16 mode;
79#define SPI_CPHA 0x01 /* clock phase */ 80#define SPI_CPHA 0x01 /* clock phase */
80#define SPI_CPOL 0x02 /* clock polarity */ 81#define SPI_CPOL 0x02 /* clock polarity */
@@ -92,7 +93,6 @@ struct spi_device {
92#define SPI_TX_QUAD 0x200 /* transmit with 4 wires */ 93#define SPI_TX_QUAD 0x200 /* transmit with 4 wires */
93#define SPI_RX_DUAL 0x400 /* receive with 2 wires */ 94#define SPI_RX_DUAL 0x400 /* receive with 2 wires */
94#define SPI_RX_QUAD 0x800 /* receive with 4 wires */ 95#define SPI_RX_QUAD 0x800 /* receive with 4 wires */
95 u8 bits_per_word;
96 int irq; 96 int irq;
97 void *controller_state; 97 void *controller_state;
98 void *controller_data; 98 void *controller_data;
@@ -277,15 +277,17 @@ static inline void spi_unregister_driver(struct spi_driver *sdrv)
277 * @unprepare_transfer_hardware: there are currently no more messages on the 277 * @unprepare_transfer_hardware: there are currently no more messages on the
278 * queue so the subsystem notifies the driver that it may relax the 278 * queue so the subsystem notifies the driver that it may relax the
279 * hardware by issuing this call 279 * hardware by issuing this call
280 * @set_cs: assert or deassert chip select, true to assert. May be called 280 * @set_cs: set the logic level of the chip select line. May be called
281 * from interrupt context. 281 * from interrupt context.
282 * @prepare_message: set up the controller to transfer a single message, 282 * @prepare_message: set up the controller to transfer a single message,
283 * for example doing DMA mapping. Called from threaded 283 * for example doing DMA mapping. Called from threaded
284 * context. 284 * context.
285 * @transfer_one: transfer a single spi_transfer. When the 285 * @transfer_one: transfer a single spi_transfer.
286 * driver is finished with this transfer it must call 286 * - return 0 if the transfer is finished,
287 * spi_finalize_current_transfer() so the subsystem can issue 287 * - return 1 if the transfer is still in progress. When
288 * the next transfer 288 * the driver is finished with this transfer it must
289 * call spi_finalize_current_transfer() so the subsystem
290 * can issue the next transfer
289 * @unprepare_message: undo any work done by prepare_message(). 291 * @unprepare_message: undo any work done by prepare_message().
290 * @cs_gpios: Array of GPIOs to use as chip select lines; one per CS 292 * @cs_gpios: Array of GPIOs to use as chip select lines; one per CS
291 * number. Any individual value may be -ENOENT for CS lines that 293 * number. Any individual value may be -ENOENT for CS lines that
@@ -576,8 +578,8 @@ struct spi_transfer {
576 dma_addr_t rx_dma; 578 dma_addr_t rx_dma;
577 579
578 unsigned cs_change:1; 580 unsigned cs_change:1;
579 u8 tx_nbits; 581 unsigned tx_nbits:3;
580 u8 rx_nbits; 582 unsigned rx_nbits:3;
581#define SPI_NBITS_SINGLE 0x01 /* 1bit transfer */ 583#define SPI_NBITS_SINGLE 0x01 /* 1bit transfer */
582#define SPI_NBITS_DUAL 0x02 /* 2bits transfer */ 584#define SPI_NBITS_DUAL 0x02 /* 2bits transfer */
583#define SPI_NBITS_QUAD 0x04 /* 4bits transfer */ 585#define SPI_NBITS_QUAD 0x04 /* 4bits transfer */
@@ -847,7 +849,7 @@ static inline ssize_t spi_w8r16(struct spi_device *spi, u8 cmd)
847 ssize_t status; 849 ssize_t status;
848 u16 result; 850 u16 result;
849 851
850 status = spi_write_then_read(spi, &cmd, 1, (u8 *) &result, 2); 852 status = spi_write_then_read(spi, &cmd, 1, &result, 2);
851 853
852 /* return negative errno or unsigned value */ 854 /* return negative errno or unsigned value */
853 return (status < 0) ? status : result; 855 return (status < 0) ? status : result;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-12 01:38:09 -0500