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authorJason Cooper <jason@lakedaemon.net>2012-11-21 14:53:48 -0500
committerJason Cooper <jason@lakedaemon.net>2012-11-21 14:53:48 -0500
commit23f4f6020edca3d44f13df95738996cf7b622e13 (patch)
tree676eed95640597d9c87d1ece74b57ddc1aacd26d
parente3899fc7ce3340e379eadc30231845e227143f54 (diff)
parent70eeaf98453191e5aede957c0c2ece05cf1a0f23 (diff)
Merge tag 'marvell-mvneta-fix-and-clk-support-3.8' of git://github.com/MISL-EBU-System-SW/mainline-public into mvebu/everything
Marvell Ethernet driver fix + clk support
-rw-r--r--Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt4
-rw-r--r--drivers/net/ethernet/marvell/mvneta.c33
2 files changed, 23 insertions, 14 deletions
diff --git a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
index c4e87f0e450e..859a6fa7569c 100644
--- a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
+++ b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
@@ -8,7 +8,7 @@ Required properties:
8 property, a single integer). 8 property, a single integer).
9- phy-mode: The interface between the SoC and the PHY (a string that 9- phy-mode: The interface between the SoC and the PHY (a string that
10 of_get_phy_mode() can understand) 10 of_get_phy_mode() can understand)
11- clock-frequency: frequency of the peripheral clock of the SoC. 11- clocks: a pointer to the reference clock for this device.
12 12
13Example: 13Example:
14 14
@@ -16,7 +16,7 @@ ethernet@d0070000 {
16 compatible = "marvell,armada-370-neta"; 16 compatible = "marvell,armada-370-neta";
17 reg = <0xd0070000 0x2500>; 17 reg = <0xd0070000 0x2500>;
18 interrupts = <8>; 18 interrupts = <8>;
19 clock-frequency = <250000000>; 19 clocks = <&gate_clk 4>;
20 status = "okay"; 20 status = "okay";
21 phy = <&phy0>; 21 phy = <&phy0>;
22 phy-mode = "rgmii-id"; 22 phy-mode = "rgmii-id";
diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c
index d9dadee6ab79..3f8086b9f5e5 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -29,6 +29,7 @@
29#include <linux/of_net.h> 29#include <linux/of_net.h>
30#include <linux/of_address.h> 30#include <linux/of_address.h>
31#include <linux/phy.h> 31#include <linux/phy.h>
32#include <linux/clk.h>
32 33
33/* Registers */ 34/* Registers */
34#define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2)) 35#define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
@@ -242,7 +243,7 @@ struct mvneta_port {
242 int weight; 243 int weight;
243 244
244 /* Core clock */ 245 /* Core clock */
245 unsigned int clk_rate_hz; 246 struct clk *clk;
246 u8 mcast_count[256]; 247 u8 mcast_count[256];
247 u16 tx_ring_size; 248 u16 tx_ring_size;
248 u16 rx_ring_size; 249 u16 rx_ring_size;
@@ -1029,7 +1030,11 @@ static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp,
1029static void mvneta_rx_time_coal_set(struct mvneta_port *pp, 1030static void mvneta_rx_time_coal_set(struct mvneta_port *pp,
1030 struct mvneta_rx_queue *rxq, u32 value) 1031 struct mvneta_rx_queue *rxq, u32 value)
1031{ 1032{
1032 u32 val = (pp->clk_rate_hz / 1000000) * value; 1033 u32 val;
1034 unsigned long clk_rate;
1035
1036 clk_rate = clk_get_rate(pp->clk);
1037 val = (clk_rate / 1000000) * value;
1033 1038
1034 mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val); 1039 mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val);
1035 rxq->time_coal = value; 1040 rxq->time_coal = value;
@@ -2601,7 +2606,7 @@ static int __devinit mvneta_init(struct mvneta_port *pp, int phy_addr)
2601 return 0; 2606 return 0;
2602} 2607}
2603 2608
2604static void __devexit mvneta_deinit(struct mvneta_port *pp) 2609static void mvneta_deinit(struct mvneta_port *pp)
2605{ 2610{
2606 kfree(pp->txqs); 2611 kfree(pp->txqs);
2607 kfree(pp->rxqs); 2612 kfree(pp->rxqs);
@@ -2671,7 +2676,7 @@ static int __devinit mvneta_probe(struct platform_device *pdev)
2671 const struct mbus_dram_target_info *dram_target_info; 2676 const struct mbus_dram_target_info *dram_target_info;
2672 struct device_node *dn = pdev->dev.of_node; 2677 struct device_node *dn = pdev->dev.of_node;
2673 struct device_node *phy_node; 2678 struct device_node *phy_node;
2674 u32 phy_addr, clk_rate_hz; 2679 u32 phy_addr;
2675 struct mvneta_port *pp; 2680 struct mvneta_port *pp;
2676 struct net_device *dev; 2681 struct net_device *dev;
2677 const char *mac_addr; 2682 const char *mac_addr;
@@ -2710,12 +2715,6 @@ static int __devinit mvneta_probe(struct platform_device *pdev)
2710 goto err_free_irq; 2715 goto err_free_irq;
2711 } 2716 }
2712 2717
2713 if (of_property_read_u32(dn, "clock-frequency", &clk_rate_hz) != 0) {
2714 dev_err(&pdev->dev, "could not read clock-frequency\n");
2715 err = -EINVAL;
2716 goto err_free_irq;
2717 }
2718
2719 mac_addr = of_get_mac_address(dn); 2718 mac_addr = of_get_mac_address(dn);
2720 2719
2721 if (!mac_addr || !is_valid_ether_addr(mac_addr)) 2720 if (!mac_addr || !is_valid_ether_addr(mac_addr))
@@ -2736,7 +2735,6 @@ static int __devinit mvneta_probe(struct platform_device *pdev)
2736 clear_bit(MVNETA_F_TX_DONE_TIMER_BIT, &pp->flags); 2735 clear_bit(MVNETA_F_TX_DONE_TIMER_BIT, &pp->flags);
2737 2736
2738 pp->weight = MVNETA_RX_POLL_WEIGHT; 2737 pp->weight = MVNETA_RX_POLL_WEIGHT;
2739 pp->clk_rate_hz = clk_rate_hz;
2740 pp->phy_node = phy_node; 2738 pp->phy_node = phy_node;
2741 pp->phy_interface = phy_mode; 2739 pp->phy_interface = phy_mode;
2742 2740
@@ -2746,6 +2744,14 @@ static int __devinit mvneta_probe(struct platform_device *pdev)
2746 goto err_free_irq; 2744 goto err_free_irq;
2747 } 2745 }
2748 2746
2747 pp->clk = devm_clk_get(&pdev->dev, NULL);
2748 if (IS_ERR(pp->clk)) {
2749 err = PTR_ERR(pp->clk);
2750 goto err_unmap;
2751 }
2752
2753 clk_prepare_enable(pp->clk);
2754
2749 pp->tx_done_timer.data = (unsigned long)dev; 2755 pp->tx_done_timer.data = (unsigned long)dev;
2750 2756
2751 pp->tx_ring_size = MVNETA_MAX_TXD; 2757 pp->tx_ring_size = MVNETA_MAX_TXD;
@@ -2757,7 +2763,7 @@ static int __devinit mvneta_probe(struct platform_device *pdev)
2757 err = mvneta_init(pp, phy_addr); 2763 err = mvneta_init(pp, phy_addr);
2758 if (err < 0) { 2764 if (err < 0) {
2759 dev_err(&pdev->dev, "can't init eth hal\n"); 2765 dev_err(&pdev->dev, "can't init eth hal\n");
2760 goto err_unmap; 2766 goto err_clk;
2761 } 2767 }
2762 mvneta_port_power_up(pp, phy_mode); 2768 mvneta_port_power_up(pp, phy_mode);
2763 2769
@@ -2785,6 +2791,8 @@ static int __devinit mvneta_probe(struct platform_device *pdev)
2785 2791
2786err_deinit: 2792err_deinit:
2787 mvneta_deinit(pp); 2793 mvneta_deinit(pp);
2794err_clk:
2795 clk_disable_unprepare(pp->clk);
2788err_unmap: 2796err_unmap:
2789 iounmap(pp->base); 2797 iounmap(pp->base);
2790err_free_irq: 2798err_free_irq:
@@ -2802,6 +2810,7 @@ static int __devexit mvneta_remove(struct platform_device *pdev)
2802 2810
2803 unregister_netdev(dev); 2811 unregister_netdev(dev);
2804 mvneta_deinit(pp); 2812 mvneta_deinit(pp);
2813 clk_disable_unprepare(pp->clk);
2805 iounmap(pp->base); 2814 iounmap(pp->base);
2806 irq_dispose_mapping(dev->irq); 2815 irq_dispose_mapping(dev->irq);
2807 free_netdev(dev); 2816 free_netdev(dev);