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authorWu Zhangjin <wuzhangjin@gmail.com>2009-11-09 11:06:13 -0500
committerRalf Baechle <ralf@linux-mips.org>2009-12-16 20:57:12 -0500
commit1032bce3ef81cb31fc85233ca668c17288e7884c (patch)
treec4a3118fa507830ca40f06d599dd09bdca73ab67
parent22c21003a91b543d82e87ef2e5195b888b5b9575 (diff)
MIPS: Lemote 2F: Add PCI support
PCI support for the Fuloong 2E and Lemote Loongson 2F family machines is mostly identical with the exception of CS5536 support. Rename ops-fuloong2e.c to ops-loongson2.c then add the CS5536 support to share most of the source code among Loongson machines. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: zhangfx@lemote.com Cc: yanh@lemote.com Cc: huhb@lemote.com Cc: Nicholas Mc Guire <hofrat@hofr.at> Cc: Arnaud Patard <apatard@mandriva.com> Cc: loongson-dev@googlegroups.com Cc: linux-mips@linux-mips.org Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat
-rw-r--r--arch/mips/pci/Makefile3
-rw-r--r--arch/mips/pci/fixup-lemote2f.c160
-rw-r--r--arch/mips/pci/ops-loongson2.c (renamed from arch/mips/pci/ops-fuloong2e.c)54
3 files changed, 216 insertions, 1 deletions
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index 0610c869852d..c9a0dc122237 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -28,7 +28,8 @@ obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o
28obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o 28obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o
29obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o 29obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o
30obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o 30obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o
31obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-fuloong2e.o 31obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-loongson2.o
32obj-$(CONFIG_LEMOTE_MACH2F) += fixup-lemote2f.o ops-loongson2.o
32obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o 33obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o
33obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o 34obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o
34obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o 35obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o
diff --git a/arch/mips/pci/fixup-lemote2f.c b/arch/mips/pci/fixup-lemote2f.c
new file mode 100644
index 000000000000..caf2edeb02f0
--- /dev/null
+++ b/arch/mips/pci/fixup-lemote2f.c
@@ -0,0 +1,160 @@
1/*
2 * Copyright (C) 2008 Lemote Technology
3 * Copyright (C) 2004 ICT CAS
4 * Author: Li xiaoyu, lixy@ict.ac.cn
5 *
6 * Copyright (C) 2007 Lemote, Inc.
7 * Author: Fuxin Zhang, zhangfx@lemote.com
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14#include <linux/init.h>
15#include <linux/pci.h>
16
17#include <loongson.h>
18#include <cs5536/cs5536.h>
19#include <cs5536/cs5536_pci.h>
20
21/* PCI interrupt pins
22 *
23 * These should not be changed, or you should consider loongson2f interrupt
24 * register and your pci card dispatch
25 */
26
27#define PCIA 4
28#define PCIB 5
29#define PCIC 6
30#define PCID 7
31
32/* all the pci device has the PCIA pin, check the datasheet. */
33static char irq_tab[][5] __initdata = {
34 /* INTA INTB INTC INTD */
35 {0, 0, 0, 0, 0}, /* 11: Unused */
36 {0, 0, 0, 0, 0}, /* 12: Unused */
37 {0, 0, 0, 0, 0}, /* 13: Unused */
38 {0, 0, 0, 0, 0}, /* 14: Unused */
39 {0, 0, 0, 0, 0}, /* 15: Unused */
40 {0, 0, 0, 0, 0}, /* 16: Unused */
41 {0, PCIA, 0, 0, 0}, /* 17: RTL8110-0 */
42 {0, PCIB, 0, 0, 0}, /* 18: RTL8110-1 */
43 {0, PCIC, 0, 0, 0}, /* 19: SiI3114 */
44 {0, PCID, 0, 0, 0}, /* 20: 3-ports nec usb */
45 {0, PCIA, PCIB, PCIC, PCID}, /* 21: PCI-SLOT */
46 {0, 0, 0, 0, 0}, /* 22: Unused */
47 {0, 0, 0, 0, 0}, /* 23: Unused */
48 {0, 0, 0, 0, 0}, /* 24: Unused */
49 {0, 0, 0, 0, 0}, /* 25: Unused */
50 {0, 0, 0, 0, 0}, /* 26: Unused */
51 {0, 0, 0, 0, 0}, /* 27: Unused */
52};
53
54int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
55{
56 int virq;
57
58 if ((PCI_SLOT(dev->devfn) != PCI_IDSEL_CS5536)
59 && (PCI_SLOT(dev->devfn) < 32)) {
60 virq = irq_tab[slot][pin];
61 printk(KERN_INFO "slot: %d, pin: %d, irq: %d\n", slot, pin,
62 virq + LOONGSON_IRQ_BASE);
63 if (virq != 0)
64 return LOONGSON_IRQ_BASE + virq;
65 else
66 return 0;
67 } else if (PCI_SLOT(dev->devfn) == PCI_IDSEL_CS5536) { /* cs5536 */
68 switch (PCI_FUNC(dev->devfn)) {
69 case 2:
70 pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
71 CS5536_IDE_INTR);
72 return CS5536_IDE_INTR; /* for IDE */
73 case 3:
74 pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
75 CS5536_ACC_INTR);
76 return CS5536_ACC_INTR; /* for AUDIO */
77 case 4: /* for OHCI */
78 case 5: /* for EHCI */
79 case 6: /* for UDC */
80 case 7: /* for OTG */
81 pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
82 CS5536_USB_INTR);
83 return CS5536_USB_INTR;
84 }
85 return dev->irq;
86 } else {
87 printk(KERN_INFO " strange pci slot number.\n");
88 return 0;
89 }
90}
91
92/* Do platform specific device initialization at pci_enable_device() time */
93int pcibios_plat_dev_init(struct pci_dev *dev)
94{
95 return 0;
96}
97
98/* CS5536 SPEC. fixup */
99static void __init loongson_cs5536_isa_fixup(struct pci_dev *pdev)
100{
101 /* the uart1 and uart2 interrupt in PIC is enabled as default */
102 pci_write_config_dword(pdev, PCI_UART1_INT_REG, 1);
103 pci_write_config_dword(pdev, PCI_UART2_INT_REG, 1);
104}
105
106static void __init loongson_cs5536_ide_fixup(struct pci_dev *pdev)
107{
108 /* setting the mutex pin as IDE function */
109 pci_write_config_dword(pdev, PCI_IDE_CFG_REG,
110 CS5536_IDE_FLASH_SIGNATURE);
111}
112
113static void __init loongson_cs5536_acc_fixup(struct pci_dev *pdev)
114{
115 /* enable the AUDIO interrupt in PIC */
116 pci_write_config_dword(pdev, PCI_ACC_INT_REG, 1);
117
118 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xc0);
119}
120
121static void __init loongson_cs5536_ohci_fixup(struct pci_dev *pdev)
122{
123 /* enable the OHCI interrupt in PIC */
124 /* THE OHCI, EHCI, UDC, OTG are shared with interrupt in PIC */
125 pci_write_config_dword(pdev, PCI_OHCI_INT_REG, 1);
126}
127
128static void __init loongson_cs5536_ehci_fixup(struct pci_dev *pdev)
129{
130 u32 hi, lo;
131
132 /* Serial short detect enable */
133 _rdmsr(USB_MSR_REG(USB_CONFIG), &hi, &lo);
134 _wrmsr(USB_MSR_REG(USB_CONFIG), (1 << 1) | (1 << 2) | (1 << 3), lo);
135
136 /* setting the USB2.0 micro frame length */
137 pci_write_config_dword(pdev, PCI_EHCI_FLADJ_REG, 0x2000);
138}
139
140static void __init loongson_nec_fixup(struct pci_dev *pdev)
141{
142 unsigned int val;
143
144 pci_read_config_dword(pdev, 0xe0, &val);
145 /* Only 2 port be used */
146 pci_write_config_dword(pdev, 0xe0, (val & ~3) | 0x2);
147}
148
149DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA,
150 loongson_cs5536_isa_fixup);
151DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_OHC,
152 loongson_cs5536_ohci_fixup);
153DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_EHC,
154 loongson_cs5536_ehci_fixup);
155DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_AUDIO,
156 loongson_cs5536_acc_fixup);
157DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_IDE,
158 loongson_cs5536_ide_fixup);
159DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB,
160 loongson_nec_fixup);
diff --git a/arch/mips/pci/ops-fuloong2e.c b/arch/mips/pci/ops-loongson2.c
index 171f65c99ca1..aa5d3da27212 100644
--- a/arch/mips/pci/ops-fuloong2e.c
+++ b/arch/mips/pci/ops-loongson2.c
@@ -20,6 +20,11 @@
20 20
21#include <loongson.h> 21#include <loongson.h>
22 22
23#ifdef CONFIG_CS5536
24#include <cs5536/cs5536_pci.h>
25#include <cs5536/cs5536.h>
26#endif
27
23#define PCI_ACCESS_READ 0 28#define PCI_ACCESS_READ 0
24#define PCI_ACCESS_WRITE 1 29#define PCI_ACCESS_WRITE 1
25 30
@@ -43,6 +48,29 @@ static int loongson_pcibios_config_access(unsigned char access_type,
43 int reg = where & ~3; 48 int reg = where & ~3;
44 49
45 if (busnum == 0) { 50 if (busnum == 0) {
51 /* board-specific part,currently,only fuloong2f,yeeloong2f
52 * use CS5536, fuloong2e use via686b, gdium has no
53 * south bridge
54 */
55#ifdef CONFIG_CS5536
56 /* cs5536_pci_conf_read4/write4() will call _rdmsr/_wrmsr() to
57 * access the regsters PCI_MSR_ADDR, PCI_MSR_DATA_LO,
58 * PCI_MSR_DATA_HI, which is bigger than PCI_MSR_CTRL, so, it
59 * will not go this branch, but the others. so, no calling dead
60 * loop here.
61 */
62 if ((PCI_IDSEL_CS5536 == device) && (reg < PCI_MSR_CTRL)) {
63 switch (access_type) {
64 case PCI_ACCESS_READ:
65 *data = cs5536_pci_conf_read4(function, reg);
66 break;
67 case PCI_ACCESS_WRITE:
68 cs5536_pci_conf_write4(function, reg, *data);
69 break;
70 }
71 return 0;
72 }
73#endif
46 /* Type 0 configuration for onboard PCI bus */ 74 /* Type 0 configuration for onboard PCI bus */
47 if (device > MAX_DEV_NUM) 75 if (device > MAX_DEV_NUM)
48 return -1; 76 return -1;
@@ -152,3 +180,29 @@ struct pci_ops loongson_pci_ops = {
152 .read = loongson_pcibios_read, 180 .read = loongson_pcibios_read,
153 .write = loongson_pcibios_write 181 .write = loongson_pcibios_write
154}; 182};
183
184#ifdef CONFIG_CS5536
185void _rdmsr(u32 msr, u32 *hi, u32 *lo)
186{
187 struct pci_bus bus = {
188 .number = PCI_BUS_CS5536
189 };
190 u32 devfn = PCI_DEVFN(PCI_IDSEL_CS5536, 0);
191 loongson_pcibios_write(&bus, devfn, PCI_MSR_ADDR, 4, msr);
192 loongson_pcibios_read(&bus, devfn, PCI_MSR_DATA_LO, 4, lo);
193 loongson_pcibios_read(&bus, devfn, PCI_MSR_DATA_HI, 4, hi);
194}
195EXPORT_SYMBOL(_rdmsr);
196
197void _wrmsr(u32 msr, u32 hi, u32 lo)
198{
199 struct pci_bus bus = {
200 .number = PCI_BUS_CS5536
201 };
202 u32 devfn = PCI_DEVFN(PCI_IDSEL_CS5536, 0);
203 loongson_pcibios_write(&bus, devfn, PCI_MSR_ADDR, 4, msr);
204 loongson_pcibios_write(&bus, devfn, PCI_MSR_DATA_LO, 4, lo);
205 loongson_pcibios_write(&bus, devfn, PCI_MSR_DATA_HI, 4, hi);
206}
207EXPORT_SYMBOL(_wrmsr);
208#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-18 15:48:48 -0500