Merge branch 'spear/13xx' into next/soc2

* spear/13xx:
  pinctrl: SPEAr1310: Fix pin numbers for clcd_high_res
  SPEAr: Update MAINTAINERS and Documentation
  SPEAr13xx: Add defconfig
  SPEAr13xx: Add compilation support
  SPEAr13xx: Add dts and dtsi files
  pinctrl: Add SPEAr13xx pinctrl drivers
  pinctrl: SPEAr: Create macro for declaring GPIO PINS
  SPEAr13xx: Add common clock framework support
  SPEAr13xx: Add source files
  SPEAr13xx: Add header files

Depends on clock, pinctrl and dt branches to go first.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

160 files changed, 28867 insertions, 6354 deletions

diff --git a/Documentation/arm/SPEAr/overview.txt b/Documentation/arm/SPEAr/overview.txt
index 253a35c6f782..57aae7765c74 100644
--- a/Documentation/arm/SPEAr/overview.txt
+++ b/Documentation/arm/SPEAr/overview.txt
@@ -8,53 +8,56 @@ Introduction
   weblink : http://www.st.com/spear
 
   The ST Microelectronics SPEAr range of ARM9/CortexA9 System-on-Chip CPUs are
-  supported by the 'spear' platform of ARM Linux. Currently SPEAr300,
-  SPEAr310, SPEAr320 and SPEAr600 SOCs are supported. Support for the SPEAr13XX
-  series is in progress.
+  supported by the 'spear' platform of ARM Linux. Currently SPEAr1310,
+  SPEAr1340, SPEAr300, SPEAr310, SPEAr320 and SPEAr600 SOCs are supported.
 
   Hierarchy in SPEAr is as follows:
 
   SPEAr (Platform)
         - SPEAr3XX (3XX SOC series, based on ARM9)
                 - SPEAr300 (SOC)
-                        - SPEAr300_EVB (Evaluation Board)
+                        - SPEAr300 Evaluation Board
                 - SPEAr310 (SOC)
-                        - SPEAr310_EVB (Evaluation Board)
+                        - SPEAr310 Evaluation Board
                 - SPEAr320 (SOC)
-                        - SPEAr320_EVB (Evaluation Board)
+                        - SPEAr320 Evaluation Board
         - SPEAr6XX (6XX SOC series, based on ARM9)
                 - SPEAr600 (SOC)
-                        - SPEAr600_EVB (Evaluation Board)
+                        - SPEAr600 Evaluation Board
         - SPEAr13XX (13XX SOC series, based on ARM CORTEXA9)
-                - SPEAr1300 (SOC)
+                - SPEAr1310 (SOC)
+                        - SPEAr1310 Evaluation Board
+                - SPEAr1340 (SOC)
+                        - SPEAr1340 Evaluation Board
 
   Configuration
   -------------
 
   A generic configuration is provided for each machine, and can be used as the
   default by
-        make spear600_defconfig
-        make spear300_defconfig
-        make spear310_defconfig
-        make spear320_defconfig
+        make spear13xx_defconfig
+        make spear3xx_defconfig
+        make spear6xx_defconfig
 
   Layout
   ------
 
-  The common files for multiple machine families (SPEAr3XX, SPEAr6XX and
-  SPEAr13XX) are located in the platform code contained in arch/arm/plat-spear
+  The common files for multiple machine families (SPEAr3xx, SPEAr6xx and
+  SPEAr13xx) are located in the platform code contained in arch/arm/plat-spear
   with headers in plat/.
 
   Each machine series have a directory with name arch/arm/mach-spear followed by
   series name. Like mach-spear3xx, mach-spear6xx and mach-spear13xx.
 
-  Common file for machines of spear3xx family is mach-spear3xx/spear3xx.c and for
-  spear6xx is mach-spear6xx/spear6xx.c. mach-spear* also contain soc/machine
-  specific files, like spear300.c, spear310.c, spear320.c and spear600.c.
-  mach-spear* also contains board specific files for each machine type.
+  Common file for machines of spear3xx family is mach-spear3xx/spear3xx.c, for
+  spear6xx is mach-spear6xx/spear6xx.c and for spear13xx family is
+  mach-spear13xx/spear13xx.c. mach-spear* also contain soc/machine specific
+  files, like spear1310.c, spear1340.c spear300.c, spear310.c, spear320.c and
+  spear600.c.  mach-spear* doesn't contains board specific files as they fully
+  support Flattened Device Tree.
 
 
   Document Author
   ---------------
 
-  Viresh Kumar, (c) 2010 ST Microelectronics
+  Viresh Kumar <viresh.kumar@st.com>, (c) 2010-2012 ST Microelectronics
diff --git a/Documentation/devicetree/bindings/arm/spear-timer.txt b/Documentation/devicetree/bindings/arm/spear-timer.txt
new file mode 100644
index 000000000000..c0017221cf55
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/spear-timer.txt
@@ -0,0 +1,18 @@
+* SPEAr ARM Timer
+
+** Timer node required properties:
+
+- compatible : Should be:
+        "st,spear-timer"
+- reg: Address range of the timer registers
+- interrupt-parent: Should be the phandle for the interrupt controller
+  that services interrupts for this device
+- interrupt: Should contain the timer interrupt number
+
+Example:
+
+        timer@f0000000 {
+                compatible = "st,spear-timer";
+                reg = <0xf0000000 0x400>;
+                interrupts = <2>;
+        };
diff --git a/Documentation/devicetree/bindings/arm/spear.txt b/Documentation/devicetree/bindings/arm/spear.txt
index f8e54f092328..0d42949df6c2 100644
--- a/Documentation/devicetree/bindings/arm/spear.txt
+++ b/Documentation/devicetree/bindings/arm/spear.txt
@@ -2,7 +2,25 @@ ST SPEAr Platforms Device Tree Bindings
 ---------------------------------------
 
 Boards with the ST SPEAr600 SoC shall have the following properties:
+Required root node property:
+compatible = "st,spear600";
 
+Boards with the ST SPEAr300 SoC shall have the following properties:
 Required root node property:
+compatible = "st,spear300";
 
-compatible = "st,spear600";
+Boards with the ST SPEAr310 SoC shall have the following properties:
+Required root node property:
+compatible = "st,spear310";
+
+Boards with the ST SPEAr320 SoC shall have the following properties:
+Required root node property:
+compatible = "st,spear320";
+
+Boards with the ST SPEAr1310 SoC shall have the following properties:
+Required root node property:
+compatible = "st,spear1310";
+
+Boards with the ST SPEAr1340 SoC shall have the following properties:
+Required root node property:
+compatible = "st,spear1340";
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
new file mode 100644
index 000000000000..ab19e6bc7d3b
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
@@ -0,0 +1,95 @@
+* Freescale IOMUX Controller (IOMUXC) for i.MX
+
+The IOMUX Controller (IOMUXC), together with the IOMUX, enables the IC
+to share one PAD to several functional blocks. The sharing is done by
+multiplexing the PAD input/output signals. For each PAD there are up to
+8 muxing options (called ALT modes). Since different modules require
+different PAD settings (like pull up, keeper, etc) the IOMUXC controls
+also the PAD settings parameters.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+Freescale IMX pin configuration node is a node of a group of pins which can be
+used for a specific device or function. This node represents both mux and config
+of the pins in that group. The 'mux' selects the function mode(also named mux
+mode) this pin can work on and the 'config' configures various pad settings
+such as pull-up, open drain, drive strength, etc.
+
+Required properties for iomux controller:
+- compatible: "fsl,<soc>-iomuxc"
+  Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs.
+
+Required properties for pin configuration node:
+- fsl,pins: two integers array, represents a group of pins mux and config
+  setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
+  pin working on a specific function, CONFIG is the pad setting value like
+  pull-up on this pin. Please refer to fsl,<soc>-pinctrl.txt for the valid
+  pins and functions of each SoC.
+
+Bits used for CONFIG:
+NO_PAD_CTL(1 << 31): indicate this pin does not need config.
+
+SION(1 << 30): Software Input On Field.
+Force the selected mux mode input path no matter of MUX_MODE functionality.
+By default the input path is determined by functionality of the selected
+mux mode (regular).
+
+Other bits are used for PAD setting.
+Please refer to each fsl,<soc>-pinctrl,txt binding doc for SoC specific part
+of bits definitions.
+
+NOTE:
+Some requirements for using fsl,imx-pinctrl binding:
+1. We have pin function node defined under iomux controller node to represent
+   what pinmux functions this SoC supports.
+2. The pin configuration node intends to work on a specific function should
+   to be defined under that specific function node.
+   The function node's name should represent well about what function
+   this group of pins in this pin configuration node are working on.
+3. The driver can use the function node's name and pin configuration node's
+   name describe the pin function and group hierarchy.
+   For example, Linux IMX pinctrl driver takes the function node's name
+   as the function name and pin configuration node's name as group name to
+   create the map table.
+4. Each pin configuration node should have a phandle, devices can set pins
+   configurations by referring to the phandle of that pin configuration node.
+
+Examples:
+usdhc@0219c000 { /* uSDHC4 */
+        fsl,card-wired;
+        vmmc-supply = <&reg_3p3v>;
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc4_1>;
+};
+
+iomuxc@020e0000 {
+        compatible = "fsl,imx6q-iomuxc";
+        reg = <0x020e0000 0x4000>;
+
+        /* shared pinctrl settings */
+        usdhc4 {
+                pinctrl_usdhc4_1: usdhc4grp-1 {
+                        fsl,pins = <1386 0x17059        /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
+                                    1392 0x10059        /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
+                                    1462 0x17059        /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
+                                    1470 0x17059        /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
+                                    1478 0x17059        /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
+                                    1486 0x17059        /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
+                                    1493 0x17059        /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
+                                    1501 0x17059        /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
+                                    1509 0x17059        /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
+                                    1517 0x17059>;      /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
+                };
+        };
+        ....
+};
+Refer to the IOMUXC controller chapter in imx6q datasheet,
+0x17059 means enable hysteresis, 47KOhm Pull Up, 50Mhz speed,
+80Ohm driver strength and Fast Slew Rate.
+User should refer to each SoC spec to set the correct value.
+
+TODO: when dtc macro support is available, we can change above raw data
+to dt macro which can get better readability in dts file.
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt
new file mode 100644
index 000000000000..82b43f915857
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt
@@ -0,0 +1,1628 @@
+* Freescale IMX6Q IOMUX Controller
+
+Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
+and usage.
+
+Required properties:
+- compatible: "fsl,imx6q-iomuxc"
+- fsl,pins: two integers array, represents a group of pins mux and config
+  setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
+  pin working on a specific function, CONFIG is the pad setting value like
+  pull-up for this pin. Please refer to imx6q datasheet for the valid pad
+  config settings.
+
+CONFIG bits definition:
+PAD_CTL_HYS                     (1 << 16)
+PAD_CTL_PUS_100K_DOWN           (0 << 14)
+PAD_CTL_PUS_47K_UP              (1 << 14)
+PAD_CTL_PUS_100K_UP             (2 << 14)
+PAD_CTL_PUS_22K_UP              (3 << 14)
+PAD_CTL_PUE                     (1 << 13)
+PAD_CTL_PKE                     (1 << 12)
+PAD_CTL_ODE                     (1 << 11)
+PAD_CTL_SPEED_LOW               (1 << 6)
+PAD_CTL_SPEED_MED               (2 << 6)
+PAD_CTL_SPEED_HIGH              (3 << 6)
+PAD_CTL_DSE_DISABLE             (0 << 3)
+PAD_CTL_DSE_240ohm              (1 << 3)
+PAD_CTL_DSE_120ohm              (2 << 3)
+PAD_CTL_DSE_80ohm               (3 << 3)
+PAD_CTL_DSE_60ohm               (4 << 3)
+PAD_CTL_DSE_48ohm               (5 << 3)
+PAD_CTL_DSE_40ohm               (6 << 3)
+PAD_CTL_DSE_34ohm               (7 << 3)
+PAD_CTL_SRE_FAST                (1 << 0)
+PAD_CTL_SRE_SLOW                (0 << 0)
+
+See below for available PIN_FUNC_ID for imx6q:
+MX6Q_PAD_SD2_DAT1__USDHC2_DAT1                  0
+MX6Q_PAD_SD2_DAT1__ECSPI5_SS0                   1
+MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2               2
+MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS             3
+MX6Q_PAD_SD2_DAT1__KPP_COL_7                    4
+MX6Q_PAD_SD2_DAT1__GPIO_1_14                    5
+MX6Q_PAD_SD2_DAT1__CCM_WAIT                     6
+MX6Q_PAD_SD2_DAT1__ANATOP_TESTO_0               7
+MX6Q_PAD_SD2_DAT2__USDHC2_DAT2                  8
+MX6Q_PAD_SD2_DAT2__ECSPI5_SS1                   9
+MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3               10
+MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD              11
+MX6Q_PAD_SD2_DAT2__KPP_ROW_6                    12
+MX6Q_PAD_SD2_DAT2__GPIO_1_13                    13
+MX6Q_PAD_SD2_DAT2__CCM_STOP                     14
+MX6Q_PAD_SD2_DAT2__ANATOP_TESTO_1               15
+MX6Q_PAD_SD2_DAT0__USDHC2_DAT0                  16
+MX6Q_PAD_SD2_DAT0__ECSPI5_MISO                  17
+MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD              18
+MX6Q_PAD_SD2_DAT0__KPP_ROW_7                    19
+MX6Q_PAD_SD2_DAT0__GPIO_1_15                    20
+MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT               21
+MX6Q_PAD_SD2_DAT0__TESTO_2                      22
+MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA              23
+MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC              24
+MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK          25
+MX6Q_PAD_RGMII_TXC__GPIO_6_19                   26
+MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_IN_0         27
+MX6Q_PAD_RGMII_TXC__ANATOP_24M_OUT              28
+MX6Q_PAD_RGMII_TD0__MIPI_HSI_CRL_TX_RDY         29
+MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0              30
+MX6Q_PAD_RGMII_TD0__GPIO_6_20                   31
+MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_IN_1         32
+MX6Q_PAD_RGMII_TD1__MIPI_HSI_CRL_RX_FLG         33
+MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1              34
+MX6Q_PAD_RGMII_TD1__GPIO_6_21                   35
+MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_IN_2         36
+MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP                37
+MX6Q_PAD_RGMII_TD2__MIPI_HSI_CRL_RX_DTA         38
+MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2              39
+MX6Q_PAD_RGMII_TD2__GPIO_6_22                   40
+MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_IN_3         41
+MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP                42
+MX6Q_PAD_RGMII_TD3__MIPI_HSI_CRL_RX_WAK         43
+MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3              44
+MX6Q_PAD_RGMII_TD3__GPIO_6_23                   45
+MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_IN_4         46
+MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA           47
+MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL             48
+MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24                49
+MX6Q_PAD_RGMII_RX_CTL__MIPI_DPHY_IN_5           50
+MX6Q_PAD_RGMII_RD0__MIPI_HSI_CRL_RX_RDY         51
+MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0              52
+MX6Q_PAD_RGMII_RD0__GPIO_6_25                   53
+MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_IN_6         54
+MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE         55
+MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL             56
+MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26                57
+MX6Q_PAD_RGMII_TX_CTL__CORE_DPHY_IN_7           58
+MX6Q_PAD_RGMII_TX_CTL__ANATOP_REF_OUT           59
+MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FL         60
+MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1              61
+MX6Q_PAD_RGMII_RD1__GPIO_6_27                   62
+MX6Q_PAD_RGMII_RD1__CORE_DPHY_TEST_IN_8         63
+MX6Q_PAD_RGMII_RD1__SJC_FAIL                    64
+MX6Q_PAD_RGMII_RD2__MIPI_HSI_CRL_TX_DTA         65
+MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2              66
+MX6Q_PAD_RGMII_RD2__GPIO_6_28                   67
+MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_IN_9         68
+MX6Q_PAD_RGMII_RD3__MIPI_HSI_CRL_TX_WAK         69
+MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3              70
+MX6Q_PAD_RGMII_RD3__GPIO_6_29                   71
+MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_IN10         72
+MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE            73
+MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC              74
+MX6Q_PAD_RGMII_RXC__GPIO_6_30                   75
+MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_IN11         76
+MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25                77
+MX6Q_PAD_EIM_A25__ECSPI4_SS1                    78
+MX6Q_PAD_EIM_A25__ECSPI2_RDY                    79
+MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12                80
+MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS                81
+MX6Q_PAD_EIM_A25__GPIO_5_2                      82
+MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE              83
+MX6Q_PAD_EIM_A25__PL301_PER1_HBURST_0           84
+MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2                85
+MX6Q_PAD_EIM_EB2__ECSPI1_SS0                    86
+MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK               87
+MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19                88
+MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL               89
+MX6Q_PAD_EIM_EB2__GPIO_2_30                     90
+MX6Q_PAD_EIM_EB2__I2C2_SCL                      91
+MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30                 92
+MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16                93
+MX6Q_PAD_EIM_D16__ECSPI1_SCLK                   94
+MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5                 95
+MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18                96
+MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA               97
+MX6Q_PAD_EIM_D16__GPIO_3_16                     98
+MX6Q_PAD_EIM_D16__I2C2_SDA                      99
+MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17                100
+MX6Q_PAD_EIM_D17__ECSPI1_MISO                   101
+MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6                 102
+MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK              103
+MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT                104
+MX6Q_PAD_EIM_D17__GPIO_3_17                     105
+MX6Q_PAD_EIM_D17__I2C3_SCL                      106
+MX6Q_PAD_EIM_D17__PL301_PER1_HBURST_1           107
+MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18                108
+MX6Q_PAD_EIM_D18__ECSPI1_MOSI                   109
+MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7                 110
+MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17                111
+MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS                112
+MX6Q_PAD_EIM_D18__GPIO_3_18                     113
+MX6Q_PAD_EIM_D18__I2C3_SDA                      114
+MX6Q_PAD_EIM_D18__PL301_PER1_HBURST_2           115
+MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19                116
+MX6Q_PAD_EIM_D19__ECSPI1_SS1                    117
+MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8                 118
+MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16                119
+MX6Q_PAD_EIM_D19__UART1_CTS                     120
+MX6Q_PAD_EIM_D19__GPIO_3_19                     121
+MX6Q_PAD_EIM_D19__EPIT1_EPITO                   122
+MX6Q_PAD_EIM_D19__PL301_PER1_HRESP              123
+MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20                124
+MX6Q_PAD_EIM_D20__ECSPI4_SS0                    125
+MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16                126
+MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15                127
+MX6Q_PAD_EIM_D20__UART1_RTS                     128
+MX6Q_PAD_EIM_D20__GPIO_3_20                     129
+MX6Q_PAD_EIM_D20__EPIT2_EPITO                   130
+MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21                131
+MX6Q_PAD_EIM_D21__ECSPI4_SCLK                   132
+MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17                133
+MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11                134
+MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC              135
+MX6Q_PAD_EIM_D21__GPIO_3_21                     136
+MX6Q_PAD_EIM_D21__I2C1_SCL                      137
+MX6Q_PAD_EIM_D21__SPDIF_IN1                     138
+MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22                139
+MX6Q_PAD_EIM_D22__ECSPI4_MISO                   140
+MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1                 141
+MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10                142
+MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR             143
+MX6Q_PAD_EIM_D22__GPIO_3_22                     144
+MX6Q_PAD_EIM_D22__SPDIF_OUT1                    145
+MX6Q_PAD_EIM_D22__PL301_PER1_HWRITE             146
+MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23                147
+MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS                148
+MX6Q_PAD_EIM_D23__UART3_CTS                     149
+MX6Q_PAD_EIM_D23__UART1_DCD                     150
+MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN             151
+MX6Q_PAD_EIM_D23__GPIO_3_23                     152
+MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2                 153
+MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14                154
+MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3                155
+MX6Q_PAD_EIM_EB3__ECSPI4_RDY                    156
+MX6Q_PAD_EIM_EB3__UART3_RTS                     157
+MX6Q_PAD_EIM_EB3__UART1_RI                      158
+MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC               159
+MX6Q_PAD_EIM_EB3__GPIO_2_31                     160
+MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3                 161
+MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31                 162
+MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24                163
+MX6Q_PAD_EIM_D24__ECSPI4_SS2                    164
+MX6Q_PAD_EIM_D24__UART3_TXD                     165
+MX6Q_PAD_EIM_D24__ECSPI1_SS2                    166
+MX6Q_PAD_EIM_D24__ECSPI2_SS2                    167
+MX6Q_PAD_EIM_D24__GPIO_3_24                     168
+MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS              169
+MX6Q_PAD_EIM_D24__UART1_DTR                     170
+MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25                171
+MX6Q_PAD_EIM_D25__ECSPI4_SS3                    172
+MX6Q_PAD_EIM_D25__UART3_RXD                     173
+MX6Q_PAD_EIM_D25__ECSPI1_SS3                    174
+MX6Q_PAD_EIM_D25__ECSPI2_SS3                    175
+MX6Q_PAD_EIM_D25__GPIO_3_25                     176
+MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC               177
+MX6Q_PAD_EIM_D25__UART1_DSR                     178
+MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26                179
+MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11                180
+MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1                 181
+MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14                182
+MX6Q_PAD_EIM_D26__UART2_TXD                     183
+MX6Q_PAD_EIM_D26__GPIO_3_26                     184
+MX6Q_PAD_EIM_D26__IPU1_SISG_2                   185
+MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22             186
+MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27                187
+MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13                188
+MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0                 189
+MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13                190
+MX6Q_PAD_EIM_D27__UART2_RXD                     191
+MX6Q_PAD_EIM_D27__GPIO_3_27                     192
+MX6Q_PAD_EIM_D27__IPU1_SISG_3                   193
+MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23             194
+MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28                195
+MX6Q_PAD_EIM_D28__I2C1_SDA                      196
+MX6Q_PAD_EIM_D28__ECSPI4_MOSI                   197
+MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12                198
+MX6Q_PAD_EIM_D28__UART2_CTS                     199
+MX6Q_PAD_EIM_D28__GPIO_3_28                     200
+MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG                 201
+MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13                202
+MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29                203
+MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15                204
+MX6Q_PAD_EIM_D29__ECSPI4_SS0                    205
+MX6Q_PAD_EIM_D29__UART2_RTS                     206
+MX6Q_PAD_EIM_D29__GPIO_3_29                     207
+MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC               208
+MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14                209
+MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30                210
+MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21             211
+MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11                212
+MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3                 213
+MX6Q_PAD_EIM_D30__UART3_CTS                     214
+MX6Q_PAD_EIM_D30__GPIO_3_30                     215
+MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC               216
+MX6Q_PAD_EIM_D30__PL301_PER1_HPROT_0            217
+MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31                218
+MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20             219
+MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12                220
+MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2                 221
+MX6Q_PAD_EIM_D31__UART3_RTS                     222
+MX6Q_PAD_EIM_D31__GPIO_3_31                     223
+MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR              224
+MX6Q_PAD_EIM_D31__PL301_PER1_HPROT_1            225
+MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24                226
+MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19             227
+MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19                228
+MX6Q_PAD_EIM_A24__IPU2_SISG_2                   229
+MX6Q_PAD_EIM_A24__IPU1_SISG_2                   230
+MX6Q_PAD_EIM_A24__GPIO_5_4                      231
+MX6Q_PAD_EIM_A24__PL301_PER1_HPROT_2            232
+MX6Q_PAD_EIM_A24__SRC_BT_CFG_24                 233
+MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23                234
+MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18             235
+MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18                236
+MX6Q_PAD_EIM_A23__IPU2_SISG_3                   237
+MX6Q_PAD_EIM_A23__IPU1_SISG_3                   238
+MX6Q_PAD_EIM_A23__GPIO_6_6                      239
+MX6Q_PAD_EIM_A23__PL301_PER1_HPROT_3            240
+MX6Q_PAD_EIM_A23__SRC_BT_CFG_23                 241
+MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22                242
+MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17             243
+MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17                244
+MX6Q_PAD_EIM_A22__GPIO_2_16                     245
+MX6Q_PAD_EIM_A22__TPSMP_HDATA_0                 246
+MX6Q_PAD_EIM_A22__SRC_BT_CFG_22                 247
+MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21                248
+MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16             249
+MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16                250
+MX6Q_PAD_EIM_A21__RESERVED_RESERVED             251
+MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_OUT_18         252
+MX6Q_PAD_EIM_A21__GPIO_2_17                     253
+MX6Q_PAD_EIM_A21__TPSMP_HDATA_1                 254
+MX6Q_PAD_EIM_A21__SRC_BT_CFG_21                 255
+MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20                256
+MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15             257
+MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15                258
+MX6Q_PAD_EIM_A20__RESERVED_RESERVED             259
+MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_OUT_19         260
+MX6Q_PAD_EIM_A20__GPIO_2_18                     261
+MX6Q_PAD_EIM_A20__TPSMP_HDATA_2                 262
+MX6Q_PAD_EIM_A20__SRC_BT_CFG_20                 263
+MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19                264
+MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14             265
+MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14                266
+MX6Q_PAD_EIM_A19__RESERVED_RESERVED             267
+MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_OUT_20         268
+MX6Q_PAD_EIM_A19__GPIO_2_19                     269
+MX6Q_PAD_EIM_A19__TPSMP_HDATA_3                 270
+MX6Q_PAD_EIM_A19__SRC_BT_CFG_19                 271
+MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18                272
+MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13             273
+MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13                274
+MX6Q_PAD_EIM_A18__RESERVED_RESERVED             275
+MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_OUT_21         276
+MX6Q_PAD_EIM_A18__GPIO_2_20                     277
+MX6Q_PAD_EIM_A18__TPSMP_HDATA_4                 278
+MX6Q_PAD_EIM_A18__SRC_BT_CFG_18                 279
+MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17                280
+MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12             281
+MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12                282
+MX6Q_PAD_EIM_A17__RESERVED_RESERVED             283
+MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_OUT_22         284
+MX6Q_PAD_EIM_A17__GPIO_2_21                     285
+MX6Q_PAD_EIM_A17__TPSMP_HDATA_5                 286
+MX6Q_PAD_EIM_A17__SRC_BT_CFG_17                 287
+MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16                288
+MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK             289
+MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK              290
+MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_OUT_23         291
+MX6Q_PAD_EIM_A16__GPIO_2_22                     292
+MX6Q_PAD_EIM_A16__TPSMP_HDATA_6                 293
+MX6Q_PAD_EIM_A16__SRC_BT_CFG_16                 294
+MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0                295
+MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5                 296
+MX6Q_PAD_EIM_CS0__ECSPI2_SCLK                   297
+MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_OUT_24         298
+MX6Q_PAD_EIM_CS0__GPIO_2_23                     299
+MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7                 300
+MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1                301
+MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6                 302
+MX6Q_PAD_EIM_CS1__ECSPI2_MOSI                   303
+MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_OUT_25         304
+MX6Q_PAD_EIM_CS1__GPIO_2_24                     305
+MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8                 306
+MX6Q_PAD_EIM_OE__WEIM_WEIM_OE                   307
+MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7                  308
+MX6Q_PAD_EIM_OE__ECSPI2_MISO                    309
+MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_OUT_26          310
+MX6Q_PAD_EIM_OE__GPIO_2_25                      311
+MX6Q_PAD_EIM_OE__TPSMP_HDATA_9                  312
+MX6Q_PAD_EIM_RW__WEIM_WEIM_RW                   313
+MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8                  314
+MX6Q_PAD_EIM_RW__ECSPI2_SS0                     315
+MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_OUT_27          316
+MX6Q_PAD_EIM_RW__GPIO_2_26                      317
+MX6Q_PAD_EIM_RW__TPSMP_HDATA_10                 318
+MX6Q_PAD_EIM_RW__SRC_BT_CFG_29                  319
+MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA                 320
+MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17                321
+MX6Q_PAD_EIM_LBA__ECSPI2_SS1                    322
+MX6Q_PAD_EIM_LBA__GPIO_2_27                     323
+MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11                324
+MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26                 325
+MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0                326
+MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11             327
+MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11                328
+MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_OUT_0          329
+MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY                  330
+MX6Q_PAD_EIM_EB0__GPIO_2_28                     331
+MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12                332
+MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27                 333
+MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1                334
+MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10             335
+MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10                336
+MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY__OUT_1         337
+MX6Q_PAD_EIM_EB1__GPIO_2_29                     338
+MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13                339
+MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28                 340
+MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0              341
+MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9              342
+MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9                 343
+MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY__OUT_2         344
+MX6Q_PAD_EIM_DA0__GPIO_3_0                      345
+MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14                346
+MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0                  347
+MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1              348
+MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8              349
+MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8                 350
+MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_OUT_3          351
+MX6Q_PAD_EIM_DA1__USBPHY1_TX_LS_MODE            352
+MX6Q_PAD_EIM_DA1__GPIO_3_1                      353
+MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15                354
+MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1                  355
+MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2              356
+MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7              357
+MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7                 358
+MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_OUT_4          359
+MX6Q_PAD_EIM_DA2__USBPHY1_TX_HS_MODE            360
+MX6Q_PAD_EIM_DA2__GPIO_3_2                      361
+MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16                362
+MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2                  363
+MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3              364
+MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6              365
+MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6                 366
+MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_OUT_5          367
+MX6Q_PAD_EIM_DA3__USBPHY1_TX_HIZ                368
+MX6Q_PAD_EIM_DA3__GPIO_3_3                      369
+MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17                370
+MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3                  371
+MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4              372
+MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5              373
+MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5                 374
+MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_OUT_6          375
+MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TX_EN          376
+MX6Q_PAD_EIM_DA4__GPIO_3_4                      377
+MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18                378
+MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4                  379
+MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5              380
+MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4              381
+MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4                 382
+MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_OUT_7          383
+MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TX_DP          384
+MX6Q_PAD_EIM_DA5__GPIO_3_5                      385
+MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19                386
+MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5                  387
+MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6              388
+MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3              389
+MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3                 390
+MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_OUT_8          391
+MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TX_DN          392
+MX6Q_PAD_EIM_DA6__GPIO_3_6                      393
+MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20                394
+MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6                  395
+MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7              396
+MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2              397
+MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2                 398
+MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_OUT_9          399
+MX6Q_PAD_EIM_DA7__GPIO_3_7                      400
+MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21                401
+MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7                  402
+MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8              403
+MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1              404
+MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1                 405
+MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_OUT_10         406
+MX6Q_PAD_EIM_DA8__GPIO_3_8                      407
+MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22                408
+MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8                  409
+MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9              410
+MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0              411
+MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0                 412
+MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_OUT_11         413
+MX6Q_PAD_EIM_DA9__GPIO_3_9                      414
+MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23                415
+MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9                  416
+MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10            417
+MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15               418
+MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN            419
+MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_OUT12         420
+MX6Q_PAD_EIM_DA10__GPIO_3_10                    421
+MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24               422
+MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10                423
+MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11            424
+MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2                425
+MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC              426
+MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_OUT13         427
+MX6Q_PAD_EIM_DA11__SDMA_DBG_EVT_CHN_6           428
+MX6Q_PAD_EIM_DA11__GPIO_3_11                    429
+MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25               430
+MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11                431
+MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12            432
+MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3                433
+MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC              434
+MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_OUT14         435
+MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_3         436
+MX6Q_PAD_EIM_DA12__GPIO_3_12                    437
+MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26               438
+MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12                439
+MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13            440
+MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS               441
+MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK              442
+MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_OUT15         443
+MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_4         444
+MX6Q_PAD_EIM_DA13__GPIO_3_13                    445
+MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27               446
+MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13                447
+MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14            448
+MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS               449
+MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK              450
+MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_OUT16         451
+MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_5         452
+MX6Q_PAD_EIM_DA14__GPIO_3_14                    453
+MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28               454
+MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14                455
+MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15            456
+MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1                457
+MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4                458
+MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_OUT17         459
+MX6Q_PAD_EIM_DA15__GPIO_3_15                    460
+MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29               461
+MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15                462
+MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT               463
+MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B            464
+MX6Q_PAD_EIM_WAIT__GPIO_5_0                     465
+MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30               466
+MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25                467
+MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK               468
+MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16               469
+MX6Q_PAD_EIM_BCLK__GPIO_6_31                    470
+MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31               471
+MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DSP_CLK         472
+MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DSP_CLK         473
+MX6Q_PAD_DI0_DISP_CLK__MIPI_CR_DPY_OT28         474
+MX6Q_PAD_DI0_DISP_CLK__SDMA_DBG_CR_STA0         475
+MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16                476
+MX6Q_PAD_DI0_DISP_CLK__MMDC_DEBUG_0             477
+MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15              478
+MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15              479
+MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC             480
+MX6Q_PAD_DI0_PIN15__MIPI_CR_DPHY_OUT_29         481
+MX6Q_PAD_DI0_PIN15__SDMA_DBG_CORE_STA_1         482
+MX6Q_PAD_DI0_PIN15__GPIO_4_17                   483
+MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1           484
+MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2                485
+MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2                486
+MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD              487
+MX6Q_PAD_DI0_PIN2__MIPI_CR_DPHY_OUT_30          488
+MX6Q_PAD_DI0_PIN2__SDMA_DBG_CORE_STA_2          489
+MX6Q_PAD_DI0_PIN2__GPIO_4_18                    490
+MX6Q_PAD_DI0_PIN2__MMDC_DEBUG_2                 491
+MX6Q_PAD_DI0_PIN2__PL301_PER1_HADDR_9           492
+MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3                493
+MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3                494
+MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS             495
+MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_OUT31         496
+MX6Q_PAD_DI0_PIN3__SDMA_DBG_CORE_STA_3          497
+MX6Q_PAD_DI0_PIN3__GPIO_4_19                    498
+MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3            499
+MX6Q_PAD_DI0_PIN3__PL301_PER1_HADDR_10          500
+MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4                501
+MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4                502
+MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD              503
+MX6Q_PAD_DI0_PIN4__USDHC1_WP                    504
+MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD             505
+MX6Q_PAD_DI0_PIN4__GPIO_4_20                    506
+MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4            507
+MX6Q_PAD_DI0_PIN4__PL301_PER1_HADDR_11          508
+MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0           509
+MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0           510
+MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK                511
+MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DBG_0         512
+MX6Q_PAD_DISP0_DAT0__SDMA_DBG_CORE_RUN          513
+MX6Q_PAD_DISP0_DAT0__GPIO_4_21                  514
+MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5          515
+MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1           516
+MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1           517
+MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI                518
+MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DBG_1         519
+MX6Q_PAD_DISP0_DAT1__SDMA_DBG_EVT_CHNSL         520
+MX6Q_PAD_DISP0_DAT1__GPIO_4_22                  521
+MX6Q_PAD_DISP0_DAT1__MMDC_DEBUG_6               522
+MX6Q_PAD_DISP0_DAT1__PL301_PER1_HADR_12         523
+MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2           524
+MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2           525
+MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO                526
+MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DBG_2         527
+MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE            528
+MX6Q_PAD_DISP0_DAT2__GPIO_4_23                  529
+MX6Q_PAD_DISP0_DAT2__MMDC_DEBUG_7               530
+MX6Q_PAD_DISP0_DAT2__PL301_PER1_HADR_13         531
+MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3           532
+MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3           533
+MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0                 534
+MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DBG_3         535
+MX6Q_PAD_DISP0_DAT3__SDMA_DBG_BUS_ERROR         536
+MX6Q_PAD_DISP0_DAT3__GPIO_4_24                  537
+MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DBG_8            538
+MX6Q_PAD_DISP0_DAT3__PL301_PER1_HADR_14         539
+MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4           540
+MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4           541
+MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1                 542
+MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DBG_4         543
+MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB         544
+MX6Q_PAD_DISP0_DAT4__GPIO_4_25                  545
+MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9          546
+MX6Q_PAD_DISP0_DAT4__PL301_PER1_HADR_15         547
+MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5           548
+MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5           549
+MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2                 550
+MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS           551
+MX6Q_PAD_DISP0_DAT5__SDMA_DBG_MCH_DMBUS         552
+MX6Q_PAD_DISP0_DAT5__GPIO_4_26                  553
+MX6Q_PAD_DISP0_DAT5__MMDC_DEBUG_10              554
+MX6Q_PAD_DISP0_DAT5__PL301_PER1_HADR_16         555
+MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6           556
+MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6           557
+MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3                 558
+MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC            559
+MX6Q_PAD_DISP0_DAT6__SDMA_DBG_RTBUF_WRT         560
+MX6Q_PAD_DISP0_DAT6__GPIO_4_27                  561
+MX6Q_PAD_DISP0_DAT6__MMDC_DEBUG_11              562
+MX6Q_PAD_DISP0_DAT6__PL301_PER1_HADR_17         563
+MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7           564
+MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7           565
+MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY                 566
+MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DBG_5         567
+MX6Q_PAD_DISP0_DAT7__SDMA_DBG_EVT_CHN_0         568
+MX6Q_PAD_DISP0_DAT7__GPIO_4_28                  569
+MX6Q_PAD_DISP0_DAT7__MMDC_DEBUG_12              570
+MX6Q_PAD_DISP0_DAT7__PL301_PER1_HADR_18         571
+MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8           572
+MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8           573
+MX6Q_PAD_DISP0_DAT8__PWM1_PWMO                  574
+MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B               575
+MX6Q_PAD_DISP0_DAT8__SDMA_DBG_EVT_CHN_1         576
+MX6Q_PAD_DISP0_DAT8__GPIO_4_29                  577
+MX6Q_PAD_DISP0_DAT8__MMDC_DEBUG_13              578
+MX6Q_PAD_DISP0_DAT8__PL301_PER1_HADR_19         579
+MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9           580
+MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9           581
+MX6Q_PAD_DISP0_DAT9__PWM2_PWMO                  582
+MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B               583
+MX6Q_PAD_DISP0_DAT9__SDMA_DBG_EVT_CHN_2         584
+MX6Q_PAD_DISP0_DAT9__GPIO_4_30                  585
+MX6Q_PAD_DISP0_DAT9__MMDC_DEBUG_14              586
+MX6Q_PAD_DISP0_DAT9__PL301_PER1_HADR_20         587
+MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10         588
+MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10         589
+MX6Q_PAD_DISP0_DAT10__USDHC1_DBG_6              590
+MX6Q_PAD_DISP0_DAT10__SDMA_DBG_EVT_CHN3         591
+MX6Q_PAD_DISP0_DAT10__GPIO_4_31                 592
+MX6Q_PAD_DISP0_DAT10__MMDC_DEBUG_15             593
+MX6Q_PAD_DISP0_DAT10__PL301_PER1_HADR21         594
+MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11         595
+MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11         596
+MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DBG7         597
+MX6Q_PAD_DISP0_DAT11__SDMA_DBG_EVT_CHN4         598
+MX6Q_PAD_DISP0_DAT11__GPIO_5_5                  599
+MX6Q_PAD_DISP0_DAT11__MMDC_DEBUG_16             600
+MX6Q_PAD_DISP0_DAT11__PL301_PER1_HADR22         601
+MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12         602
+MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12         603
+MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED         604
+MX6Q_PAD_DISP0_DAT12__SDMA_DBG_EVT_CHN5         605
+MX6Q_PAD_DISP0_DAT12__GPIO_5_6                  606
+MX6Q_PAD_DISP0_DAT12__MMDC_DEBUG_17             607
+MX6Q_PAD_DISP0_DAT12__PL301_PER1_HADR23         608
+MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13         609
+MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13         610
+MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS          611
+MX6Q_PAD_DISP0_DAT13__SDMA_DBG_EVT_CHN0         612
+MX6Q_PAD_DISP0_DAT13__GPIO_5_7                  613
+MX6Q_PAD_DISP0_DAT13__MMDC_DEBUG_18             614
+MX6Q_PAD_DISP0_DAT13__PL301_PER1_HADR24         615
+MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14         616
+MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14         617
+MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC           618
+MX6Q_PAD_DISP0_DAT14__SDMA_DBG_EVT_CHN1         619
+MX6Q_PAD_DISP0_DAT14__GPIO_5_8                  620
+MX6Q_PAD_DISP0_DAT14__MMDC_DEBUG_19             621
+MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15         622
+MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15         623
+MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1                624
+MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1                625
+MX6Q_PAD_DISP0_DAT15__SDMA_DBG_EVT_CHN2         626
+MX6Q_PAD_DISP0_DAT15__GPIO_5_9                  627
+MX6Q_PAD_DISP0_DAT15__MMDC_DEBUG_20             628
+MX6Q_PAD_DISP0_DAT15__PL301_PER1_HADR25         629
+MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16         630
+MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16         631
+MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI               632
+MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC           633
+MX6Q_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0          634
+MX6Q_PAD_DISP0_DAT16__GPIO_5_10                 635
+MX6Q_PAD_DISP0_DAT16__MMDC_DEBUG_21             636
+MX6Q_PAD_DISP0_DAT16__PL301_PER1_HADR26         637
+MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17         638
+MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17         639
+MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO               640
+MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD           641
+MX6Q_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1          642
+MX6Q_PAD_DISP0_DAT17__GPIO_5_11                 643
+MX6Q_PAD_DISP0_DAT17__MMDC_DEBUG_22             644
+MX6Q_PAD_DISP0_DAT17__PL301_PER1_HADR27         645
+MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18         646
+MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18         647
+MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0                648
+MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS          649
+MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS          650
+MX6Q_PAD_DISP0_DAT18__GPIO_5_12                 651
+MX6Q_PAD_DISP0_DAT18__MMDC_DEBUG_23             652
+MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2            653
+MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19         654
+MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19         655
+MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK               656
+MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD           657
+MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC           658
+MX6Q_PAD_DISP0_DAT19__GPIO_5_13                 659
+MX6Q_PAD_DISP0_DAT19__MMDC_DEBUG_24             660
+MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3            661
+MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20         662
+MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20         663
+MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK               664
+MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC           665
+MX6Q_PAD_DISP0_DAT20__SDMA_DBG_EVT_CHN7         666
+MX6Q_PAD_DISP0_DAT20__GPIO_5_14                 667
+MX6Q_PAD_DISP0_DAT20__MMDC_DEBUG_25             668
+MX6Q_PAD_DISP0_DAT20__PL301_PER1_HADR28         669
+MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21         670
+MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21         671
+MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI               672
+MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD           673
+MX6Q_PAD_DISP0_DAT21__SDMA_DBG_BUS_DEV0         674
+MX6Q_PAD_DISP0_DAT21__GPIO_5_15                 675
+MX6Q_PAD_DISP0_DAT21__MMDC_DEBUG_26             676
+MX6Q_PAD_DISP0_DAT21__PL301_PER1_HADR29         677
+MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22         678
+MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22         679
+MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO               680
+MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS          681
+MX6Q_PAD_DISP0_DAT22__SDMA_DBG_BUS_DEV1         682
+MX6Q_PAD_DISP0_DAT22__GPIO_5_16                 683
+MX6Q_PAD_DISP0_DAT22__MMDC_DEBUG_27             684
+MX6Q_PAD_DISP0_DAT22__PL301_PER1_HADR30         685
+MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23         686
+MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23         687
+MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0                688
+MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD           689
+MX6Q_PAD_DISP0_DAT23__SDMA_DBG_BUS_DEV2         690
+MX6Q_PAD_DISP0_DAT23__GPIO_5_17                 691
+MX6Q_PAD_DISP0_DAT23__MMDC_DEBUG_28             692
+MX6Q_PAD_DISP0_DAT23__PL301_PER1_HADR31         693
+MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED           694
+MX6Q_PAD_ENET_MDIO__ENET_MDIO                   695
+MX6Q_PAD_ENET_MDIO__ESAI1_SCKR                  696
+MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEV3         697
+MX6Q_PAD_ENET_MDIO__ENET_1588_EVT1_OUT          698
+MX6Q_PAD_ENET_MDIO__GPIO_1_22                   699
+MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK                 700
+MX6Q_PAD_ENET_REF_CLK__RESERVED_RSRVED          701
+MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK              702
+MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR                703
+MX6Q_PAD_ENET_REF_CLK__SDMA_DBGBUS_DEV4         704
+MX6Q_PAD_ENET_REF_CLK__GPIO_1_23                705
+MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK              706
+MX6Q_PAD_ENET_REF_CLK__USBPHY1_RX_SQH           707
+MX6Q_PAD_ENET_RX_ER__ENET_RX_ER                 708
+MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR                 709
+MX6Q_PAD_ENET_RX_ER__SPDIF_IN1                  710
+MX6Q_PAD_ENET_RX_ER__ENET_1588_EVT2_OUT         711
+MX6Q_PAD_ENET_RX_ER__GPIO_1_24                  712
+MX6Q_PAD_ENET_RX_ER__PHY_TDI                    713
+MX6Q_PAD_ENET_RX_ER__USBPHY1_RX_HS_RXD          714
+MX6Q_PAD_ENET_CRS_DV__RESERVED_RSRVED           715
+MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN                716
+MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT                717
+MX6Q_PAD_ENET_CRS_DV__SPDIF_EXTCLK              718
+MX6Q_PAD_ENET_CRS_DV__GPIO_1_25                 719
+MX6Q_PAD_ENET_CRS_DV__PHY_TDO                   720
+MX6Q_PAD_ENET_CRS_DV__USBPHY1_RX_FS_RXD         721
+MX6Q_PAD_ENET_RXD1__MLB_MLBSIG                  722
+MX6Q_PAD_ENET_RXD1__ENET_RDATA_1                723
+MX6Q_PAD_ENET_RXD1__ESAI1_FST                   724
+MX6Q_PAD_ENET_RXD1__ENET_1588_EVT3_OUT          725
+MX6Q_PAD_ENET_RXD1__GPIO_1_26                   726
+MX6Q_PAD_ENET_RXD1__PHY_TCK                     727
+MX6Q_PAD_ENET_RXD1__USBPHY1_RX_DISCON           728
+MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT              729
+MX6Q_PAD_ENET_RXD0__ENET_RDATA_0                730
+MX6Q_PAD_ENET_RXD0__ESAI1_HCKT                  731
+MX6Q_PAD_ENET_RXD0__SPDIF_OUT1                  732
+MX6Q_PAD_ENET_RXD0__GPIO_1_27                   733
+MX6Q_PAD_ENET_RXD0__PHY_TMS                     734
+MX6Q_PAD_ENET_RXD0__USBPHY1_PLL_CK20DIV         735
+MX6Q_PAD_ENET_TX_EN__RESERVED_RSRVED            736
+MX6Q_PAD_ENET_TX_EN__ENET_TX_EN                 737
+MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2              738
+MX6Q_PAD_ENET_TX_EN__GPIO_1_28                  739
+MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI               740
+MX6Q_PAD_ENET_TX_EN__USBPHY2_RX_SQH             741
+MX6Q_PAD_ENET_TXD1__MLB_MLBCLK                  742
+MX6Q_PAD_ENET_TXD1__ENET_TDATA_1                743
+MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3               744
+MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN         745
+MX6Q_PAD_ENET_TXD1__GPIO_1_29                   746
+MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO                747
+MX6Q_PAD_ENET_TXD1__USBPHY2_RX_HS_RXD           748
+MX6Q_PAD_ENET_TXD0__RESERVED_RSRVED             749
+MX6Q_PAD_ENET_TXD0__ENET_TDATA_0                750
+MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1               751
+MX6Q_PAD_ENET_TXD0__GPIO_1_30                   752
+MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK                753
+MX6Q_PAD_ENET_TXD0__USBPHY2_RX_FS_RXD           754
+MX6Q_PAD_ENET_MDC__MLB_MLBDAT                   755
+MX6Q_PAD_ENET_MDC__ENET_MDC                     756
+MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0                757
+MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN          758
+MX6Q_PAD_ENET_MDC__GPIO_1_31                    759
+MX6Q_PAD_ENET_MDC__SATA_PHY_TMS                 760
+MX6Q_PAD_ENET_MDC__USBPHY2_RX_DISCON            761
+MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40               762
+MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41               763
+MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42               764
+MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43               765
+MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44               766
+MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45               767
+MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46               768
+MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47               769
+MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5           770
+MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5             771
+MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32               772
+MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33               773
+MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34               774
+MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35               775
+MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36               776
+MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37               777
+MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38               778
+MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39               779
+MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4             780
+MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4           781
+MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24               782
+MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25               783
+MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26               784
+MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27               785
+MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28               786
+MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29               787
+MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3           788
+MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30               789
+MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31               790
+MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3             791
+MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16               792
+MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17               793
+MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18               794
+MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19               795
+MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20               796
+MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21               797
+MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22               798
+MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2           799
+MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23               800
+MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2             801
+MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0                 802
+MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1                 803
+MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2                 804
+MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3                 805
+MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4                 806
+MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5                 807
+MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6                 808
+MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7                 809
+MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8                 810
+MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9                 811
+MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10               812
+MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11               813
+MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12               814
+MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13               815
+MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14               816
+MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15               817
+MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS                818
+MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0               819
+MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1               820
+MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS                821
+MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET            822
+MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0           823
+MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1           824
+MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0         825
+MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2           826
+MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0         827
+MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1         828
+MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1         829
+MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0           830
+MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1           831
+MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE              832
+MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0                 833
+MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1                 834
+MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2                 835
+MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3                 836
+MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4                 837
+MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5                 838
+MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0           839
+MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6                 840
+MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7                 841
+MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0             842
+MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8                 843
+MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9                 844
+MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10               845
+MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11               846
+MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12               847
+MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13               848
+MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14               849
+MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1           850
+MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15               851
+MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1             852
+MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48               853
+MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49               854
+MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50               855
+MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51               856
+MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52               857
+MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53               858
+MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54               859
+MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55               860
+MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6           861
+MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6             862
+MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56               863
+MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7           864
+MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57               865
+MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58               866
+MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59               867
+MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60               868
+MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7             869
+MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61               870
+MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62               871
+MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63               872
+MX6Q_PAD_KEY_COL0__ECSPI1_SCLK                  873
+MX6Q_PAD_KEY_COL0__ENET_RDATA_3                 874
+MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC              875
+MX6Q_PAD_KEY_COL0__KPP_COL_0                    876
+MX6Q_PAD_KEY_COL0__UART4_TXD                    877
+MX6Q_PAD_KEY_COL0__GPIO_4_6                     878
+MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT               879
+MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST               880
+MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI                  881
+MX6Q_PAD_KEY_ROW0__ENET_TDATA_3                 882
+MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD              883
+MX6Q_PAD_KEY_ROW0__KPP_ROW_0                    884
+MX6Q_PAD_KEY_ROW0__UART4_RXD                    885
+MX6Q_PAD_KEY_ROW0__GPIO_4_7                     886
+MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT               887
+MX6Q_PAD_KEY_ROW0__PL301_PER1_HADR_0            888
+MX6Q_PAD_KEY_COL1__ECSPI1_MISO                  889
+MX6Q_PAD_KEY_COL1__ENET_MDIO                    890
+MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS             891
+MX6Q_PAD_KEY_COL1__KPP_COL_1                    892
+MX6Q_PAD_KEY_COL1__UART5_TXD                    893
+MX6Q_PAD_KEY_COL1__GPIO_4_8                     894
+MX6Q_PAD_KEY_COL1__USDHC1_VSELECT               895
+MX6Q_PAD_KEY_COL1__PL301MX_PER1_HADR_1          896
+MX6Q_PAD_KEY_ROW1__ECSPI1_SS0                   897
+MX6Q_PAD_KEY_ROW1__ENET_COL                     898
+MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD              899
+MX6Q_PAD_KEY_ROW1__KPP_ROW_1                    900
+MX6Q_PAD_KEY_ROW1__UART5_RXD                    901
+MX6Q_PAD_KEY_ROW1__GPIO_4_9                     902
+MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT               903
+MX6Q_PAD_KEY_ROW1__PL301_PER1_HADDR_2           904
+MX6Q_PAD_KEY_COL2__ECSPI1_SS1                   905
+MX6Q_PAD_KEY_COL2__ENET_RDATA_2                 906
+MX6Q_PAD_KEY_COL2__CAN1_TXCAN                   907
+MX6Q_PAD_KEY_COL2__KPP_COL_2                    908
+MX6Q_PAD_KEY_COL2__ENET_MDC                     909
+MX6Q_PAD_KEY_COL2__GPIO_4_10                    910
+MX6Q_PAD_KEY_COL2__USBOH3_H1_PWRCTL_WKP         911
+MX6Q_PAD_KEY_COL2__PL301_PER1_HADDR_3           912
+MX6Q_PAD_KEY_ROW2__ECSPI1_SS2                   913
+MX6Q_PAD_KEY_ROW2__ENET_TDATA_2                 914
+MX6Q_PAD_KEY_ROW2__CAN1_RXCAN                   915
+MX6Q_PAD_KEY_ROW2__KPP_ROW_2                    916
+MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT               917
+MX6Q_PAD_KEY_ROW2__GPIO_4_11                    918
+MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE             919
+MX6Q_PAD_KEY_ROW2__PL301_PER1_HADR_4            920
+MX6Q_PAD_KEY_COL3__ECSPI1_SS3                   921
+MX6Q_PAD_KEY_COL3__ENET_CRS                     922
+MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL              923
+MX6Q_PAD_KEY_COL3__KPP_COL_3                    924
+MX6Q_PAD_KEY_COL3__I2C2_SCL                     925
+MX6Q_PAD_KEY_COL3__GPIO_4_12                    926
+MX6Q_PAD_KEY_COL3__SPDIF_IN1                    927
+MX6Q_PAD_KEY_COL3__PL301_PER1_HADR_5            928
+MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT               929
+MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK            930
+MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA              931
+MX6Q_PAD_KEY_ROW3__KPP_ROW_3                    932
+MX6Q_PAD_KEY_ROW3__I2C2_SDA                     933
+MX6Q_PAD_KEY_ROW3__GPIO_4_13                    934
+MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT               935
+MX6Q_PAD_KEY_ROW3__PL301_PER1_HADR_6            936
+MX6Q_PAD_KEY_COL4__CAN2_TXCAN                   937
+MX6Q_PAD_KEY_COL4__IPU1_SISG_4                  938
+MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC             939
+MX6Q_PAD_KEY_COL4__KPP_COL_4                    940
+MX6Q_PAD_KEY_COL4__UART5_RTS                    941
+MX6Q_PAD_KEY_COL4__GPIO_4_14                    942
+MX6Q_PAD_KEY_COL4__MMDC_DEBUG_49                943
+MX6Q_PAD_KEY_COL4__PL301_PER1_HADDR_7           944
+MX6Q_PAD_KEY_ROW4__CAN2_RXCAN                   945
+MX6Q_PAD_KEY_ROW4__IPU1_SISG_5                  946
+MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR            947
+MX6Q_PAD_KEY_ROW4__KPP_ROW_4                    948
+MX6Q_PAD_KEY_ROW4__UART5_CTS                    949
+MX6Q_PAD_KEY_ROW4__GPIO_4_15                    950
+MX6Q_PAD_KEY_ROW4__MMDC_DEBUG_50                951
+MX6Q_PAD_KEY_ROW4__PL301_PER1_HADR_8            952
+MX6Q_PAD_GPIO_0__CCM_CLKO                       953
+MX6Q_PAD_GPIO_0__KPP_COL_5                      954
+MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK              955
+MX6Q_PAD_GPIO_0__EPIT1_EPITO                    956
+MX6Q_PAD_GPIO_0__GPIO_1_0                       957
+MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR               958
+MX6Q_PAD_GPIO_0__SNVS_HP_WRAP_SNVS_VIO5         959
+MX6Q_PAD_GPIO_1__ESAI1_SCKR                     960
+MX6Q_PAD_GPIO_1__WDOG2_WDOG_B                   961
+MX6Q_PAD_GPIO_1__KPP_ROW_5                      962
+MX6Q_PAD_GPIO_1__PWM2_PWMO                      963
+MX6Q_PAD_GPIO_1__GPIO_1_1                       964
+MX6Q_PAD_GPIO_1__USDHC1_CD                      965
+MX6Q_PAD_GPIO_1__SRC_TESTER_ACK                 966
+MX6Q_PAD_GPIO_9__ESAI1_FSR                      967
+MX6Q_PAD_GPIO_9__WDOG1_WDOG_B                   968
+MX6Q_PAD_GPIO_9__KPP_COL_6                      969
+MX6Q_PAD_GPIO_9__CCM_REF_EN_B                   970
+MX6Q_PAD_GPIO_9__PWM1_PWMO                      971
+MX6Q_PAD_GPIO_9__GPIO_1_9                       972
+MX6Q_PAD_GPIO_9__USDHC1_WP                      973
+MX6Q_PAD_GPIO_9__SRC_EARLY_RST                  974
+MX6Q_PAD_GPIO_3__ESAI1_HCKR                     975
+MX6Q_PAD_GPIO_3__OBSERVE_MUX_INT_OUT0           976
+MX6Q_PAD_GPIO_3__I2C3_SCL                       977
+MX6Q_PAD_GPIO_3__ANATOP_24M_OUT                 978
+MX6Q_PAD_GPIO_3__CCM_CLKO2                      979
+MX6Q_PAD_GPIO_3__GPIO_1_3                       980
+MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC                981
+MX6Q_PAD_GPIO_3__MLB_MLBCLK                     982
+MX6Q_PAD_GPIO_6__ESAI1_SCKT                     983
+MX6Q_PAD_GPIO_6__OBSERVE_MUX_INT_OUT1           984
+MX6Q_PAD_GPIO_6__I2C3_SDA                       985
+MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0                  986
+MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB                987
+MX6Q_PAD_GPIO_6__GPIO_1_6                       988
+MX6Q_PAD_GPIO_6__USDHC2_LCTL                    989
+MX6Q_PAD_GPIO_6__MLB_MLBSIG                     990
+MX6Q_PAD_GPIO_2__ESAI1_FST                      991
+MX6Q_PAD_GPIO_2__OBSERVE_MUX_INT_OUT2           992
+MX6Q_PAD_GPIO_2__KPP_ROW_6                      993
+MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1                  994
+MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0            995
+MX6Q_PAD_GPIO_2__GPIO_1_2                       996
+MX6Q_PAD_GPIO_2__USDHC2_WP                      997
+MX6Q_PAD_GPIO_2__MLB_MLBDAT                     998
+MX6Q_PAD_GPIO_4__ESAI1_HCKT                     999
+MX6Q_PAD_GPIO_4__OBSERVE_MUX_INT_OUT3           1000
+MX6Q_PAD_GPIO_4__KPP_COL_7                      1001
+MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2                  1002
+MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1            1003
+MX6Q_PAD_GPIO_4__GPIO_1_4                       1004
+MX6Q_PAD_GPIO_4__USDHC2_CD                      1005
+MX6Q_PAD_GPIO_4__OCOTP_CRL_WRAR_FUSE_LA         1006
+MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3                  1007
+MX6Q_PAD_GPIO_5__OBSERVE_MUX_INT_OUT4           1008
+MX6Q_PAD_GPIO_5__KPP_ROW_7                      1009
+MX6Q_PAD_GPIO_5__CCM_CLKO                       1010
+MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2            1011
+MX6Q_PAD_GPIO_5__GPIO_1_5                       1012
+MX6Q_PAD_GPIO_5__I2C3_SCL                       1013
+MX6Q_PAD_GPIO_5__CHEETAH_EVENTI                 1014
+MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1                  1015
+MX6Q_PAD_GPIO_7__ECSPI5_RDY                     1016
+MX6Q_PAD_GPIO_7__EPIT1_EPITO                    1017
+MX6Q_PAD_GPIO_7__CAN1_TXCAN                     1018
+MX6Q_PAD_GPIO_7__UART2_TXD                      1019
+MX6Q_PAD_GPIO_7__GPIO_1_7                       1020
+MX6Q_PAD_GPIO_7__SPDIF_PLOCK                    1021
+MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HST_MODE         1022
+MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0                  1023
+MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT          1024
+MX6Q_PAD_GPIO_8__EPIT2_EPITO                    1025
+MX6Q_PAD_GPIO_8__CAN1_RXCAN                     1026
+MX6Q_PAD_GPIO_8__UART2_RXD                      1027
+MX6Q_PAD_GPIO_8__GPIO_1_8                       1028
+MX6Q_PAD_GPIO_8__SPDIF_SRCLK                    1029
+MX6Q_PAD_GPIO_8__USBOH3_OTG_PWRCTL_WAK          1030
+MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2                 1031
+MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN           1032
+MX6Q_PAD_GPIO_16__ENET_ETHERNET_REF_OUT         1033
+MX6Q_PAD_GPIO_16__USDHC1_LCTL                   1034
+MX6Q_PAD_GPIO_16__SPDIF_IN1                     1035
+MX6Q_PAD_GPIO_16__GPIO_7_11                     1036
+MX6Q_PAD_GPIO_16__I2C3_SDA                      1037
+MX6Q_PAD_GPIO_16__SJC_DE_B                      1038
+MX6Q_PAD_GPIO_17__ESAI1_TX0                     1039
+MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN           1040
+MX6Q_PAD_GPIO_17__CCM_PMIC_RDY                  1041
+MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0         1042
+MX6Q_PAD_GPIO_17__SPDIF_OUT1                    1043
+MX6Q_PAD_GPIO_17__GPIO_7_12                     1044
+MX6Q_PAD_GPIO_17__SJC_JTAG_ACT                  1045
+MX6Q_PAD_GPIO_18__ESAI1_TX1                     1046
+MX6Q_PAD_GPIO_18__ENET_RX_CLK                   1047
+MX6Q_PAD_GPIO_18__USDHC3_VSELECT                1048
+MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1         1049
+MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK             1050
+MX6Q_PAD_GPIO_18__GPIO_7_13                     1051
+MX6Q_PAD_GPIO_18__SNVS_HP_WRA_SNVS_VIO5         1052
+MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST                1053
+MX6Q_PAD_GPIO_19__KPP_COL_5                     1054
+MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT          1055
+MX6Q_PAD_GPIO_19__SPDIF_OUT1                    1056
+MX6Q_PAD_GPIO_19__CCM_CLKO                      1057
+MX6Q_PAD_GPIO_19__ECSPI1_RDY                    1058
+MX6Q_PAD_GPIO_19__GPIO_4_5                      1059
+MX6Q_PAD_GPIO_19__ENET_TX_ER                    1060
+MX6Q_PAD_GPIO_19__SRC_INT_BOOT                  1061
+MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK          1062
+MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_MUX_12          1063
+MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0           1064
+MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18                 1065
+MX6Q_PAD_CSI0_PIXCLK___MMDC_DEBUG_29            1066
+MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO            1067
+MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC             1068
+MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_MUX_13            1069
+MX6Q_PAD_CSI0_MCLK__CCM_CLKO                    1070
+MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1             1071
+MX6Q_PAD_CSI0_MCLK__GPIO_5_19                   1072
+MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30          1073
+MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL               1074
+MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DA_EN          1075
+MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0            1076
+MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_MUX_14         1077
+MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2          1078
+MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20                1079
+MX6Q_PAD_CSI0_DATA_EN__MMDC_DEBUG_31            1080
+MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK            1081
+MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC            1082
+MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1              1083
+MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_MUX_15           1084
+MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3            1085
+MX6Q_PAD_CSI0_VSYNC__GPIO_5_21                  1086
+MX6Q_PAD_CSI0_VSYNC__MMDC_DEBUG_32              1087
+MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0            1088
+MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4               1089
+MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2               1090
+MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK                 1091
+MX6Q_PAD_CSI0_DAT4__KPP_COL_5                   1092
+MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC             1093
+MX6Q_PAD_CSI0_DAT4__GPIO_5_22                   1094
+MX6Q_PAD_CSI0_DAT4__MMDC_DEBUG_43               1095
+MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1             1096
+MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5               1097
+MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3               1098
+MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI                 1099
+MX6Q_PAD_CSI0_DAT5__KPP_ROW_5                   1100
+MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD             1101
+MX6Q_PAD_CSI0_DAT5__GPIO_5_23                   1102
+MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44          1103
+MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2             1104
+MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6               1105
+MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4               1106
+MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO                 1107
+MX6Q_PAD_CSI0_DAT6__KPP_COL_6                   1108
+MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS            1109
+MX6Q_PAD_CSI0_DAT6__GPIO_5_24                   1110
+MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45          1111
+MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3             1112
+MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7               1113
+MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5               1114
+MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0                  1115
+MX6Q_PAD_CSI0_DAT7__KPP_ROW_6                   1116
+MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD             1117
+MX6Q_PAD_CSI0_DAT7__GPIO_5_25                   1118
+MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46          1119
+MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4             1120
+MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8               1121
+MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6               1122
+MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK                 1123
+MX6Q_PAD_CSI0_DAT8__KPP_COL_7                   1124
+MX6Q_PAD_CSI0_DAT8__I2C1_SDA                    1125
+MX6Q_PAD_CSI0_DAT8__GPIO_5_26                   1126
+MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47          1127
+MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5             1128
+MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9               1129
+MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7               1130
+MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI                 1131
+MX6Q_PAD_CSI0_DAT9__KPP_ROW_7                   1132
+MX6Q_PAD_CSI0_DAT9__I2C1_SCL                    1133
+MX6Q_PAD_CSI0_DAT9__GPIO_5_27                   1134
+MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48          1135
+MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6             1136
+MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10             1137
+MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC            1138
+MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO                1139
+MX6Q_PAD_CSI0_DAT10__UART1_TXD                  1140
+MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4            1141
+MX6Q_PAD_CSI0_DAT10__GPIO_5_28                  1142
+MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33         1143
+MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7            1144
+MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11             1145
+MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS           1146
+MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0                 1147
+MX6Q_PAD_CSI0_DAT11__UART1_RXD                  1148
+MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5            1149
+MX6Q_PAD_CSI0_DAT11__GPIO_5_29                  1150
+MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34         1151
+MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8            1152
+MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12             1153
+MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8              1154
+MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_MUX_16           1155
+MX6Q_PAD_CSI0_DAT12__UART4_TXD                  1156
+MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6            1157
+MX6Q_PAD_CSI0_DAT12__GPIO_5_30                  1158
+MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35         1159
+MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9            1160
+MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13             1161
+MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9              1162
+MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_MUX_17           1163
+MX6Q_PAD_CSI0_DAT13__UART4_RXD                  1164
+MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7            1165
+MX6Q_PAD_CSI0_DAT13__GPIO_5_31                  1166
+MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36         1167
+MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10           1168
+MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14             1169
+MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10             1170
+MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_MUX_18           1171
+MX6Q_PAD_CSI0_DAT14__UART5_TXD                  1172
+MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8            1173
+MX6Q_PAD_CSI0_DAT14__GPIO_6_0                   1174
+MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37         1175
+MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11           1176
+MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15             1177
+MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11             1178
+MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_MUX_19           1179
+MX6Q_PAD_CSI0_DAT15__UART5_RXD                  1180
+MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9            1181
+MX6Q_PAD_CSI0_DAT15__GPIO_6_1                   1182
+MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38         1183
+MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12           1184
+MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16             1185
+MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12             1186
+MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_MUX_20           1187
+MX6Q_PAD_CSI0_DAT16__UART4_RTS                  1188
+MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10           1189
+MX6Q_PAD_CSI0_DAT16__GPIO_6_2                   1190
+MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39         1191
+MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13           1192
+MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17             1193
+MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13             1194
+MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_MUX_21           1195
+MX6Q_PAD_CSI0_DAT17__UART4_CTS                  1196
+MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11           1197
+MX6Q_PAD_CSI0_DAT17__GPIO_6_3                   1198
+MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40         1199
+MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14           1200
+MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18             1201
+MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14             1202
+MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_MUX_22           1203
+MX6Q_PAD_CSI0_DAT18__UART5_RTS                  1204
+MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12           1205
+MX6Q_PAD_CSI0_DAT18__GPIO_6_4                   1206
+MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41         1207
+MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15           1208
+MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19             1209
+MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15             1210
+MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_MUX_23           1211
+MX6Q_PAD_CSI0_DAT19__UART5_CTS                  1212
+MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13           1213
+MX6Q_PAD_CSI0_DAT19__GPIO_6_5                   1214
+MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42         1215
+MX6Q_PAD_CSI0_DAT19__ANATOP_TESTO_9             1216
+MX6Q_PAD_JTAG_TMS__SJC_TMS                      1217
+MX6Q_PAD_JTAG_MOD__SJC_MOD                      1218
+MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB                  1219
+MX6Q_PAD_JTAG_TDI__SJC_TDI                      1220
+MX6Q_PAD_JTAG_TCK__SJC_TCK                      1221
+MX6Q_PAD_JTAG_TDO__SJC_TDO                      1222
+MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3             1223
+MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2             1224
+MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK             1225
+MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1             1226
+MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0             1227
+MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3             1228
+MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK             1229
+MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2             1230
+MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1             1231
+MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0             1232
+MX6Q_PAD_TAMPER__SNVS_LP_WRAP_SNVS_TD1          1233
+MX6Q_PAD_PMIC_ON_REQ__SNVS_LPWRAP_WKALM         1234
+MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_STBYRQ         1235
+MX6Q_PAD_POR_B__SRC_POR_B                       1236
+MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1            1237
+MX6Q_PAD_RESET_IN_B__SRC_RESET_B                1238
+MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0            1239
+MX6Q_PAD_TEST_MODE__TCU_TEST_MODE               1240
+MX6Q_PAD_SD3_DAT7__USDHC3_DAT7                  1241
+MX6Q_PAD_SD3_DAT7__UART1_TXD                    1242
+MX6Q_PAD_SD3_DAT7__PCIE_CTRL_MUX_24             1243
+MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0         1244
+MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0         1245
+MX6Q_PAD_SD3_DAT7__GPIO_6_17                    1246
+MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_IN_12         1247
+MX6Q_PAD_SD3_DAT7__USBPHY2_CLK20DIV             1248
+MX6Q_PAD_SD3_DAT6__USDHC3_DAT6                  1249
+MX6Q_PAD_SD3_DAT6__UART1_RXD                    1250
+MX6Q_PAD_SD3_DAT6__PCIE_CTRL_MUX_25             1251
+MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1         1252
+MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1         1253
+MX6Q_PAD_SD3_DAT6__GPIO_6_18                    1254
+MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_IN_13         1255
+MX6Q_PAD_SD3_DAT6__ANATOP_TESTO_10              1256
+MX6Q_PAD_SD3_DAT5__USDHC3_DAT5                  1257
+MX6Q_PAD_SD3_DAT5__UART2_TXD                    1258
+MX6Q_PAD_SD3_DAT5__PCIE_CTRL_MUX_26             1259
+MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2         1260
+MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2         1261
+MX6Q_PAD_SD3_DAT5__GPIO_7_0                     1262
+MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_IN_14         1263
+MX6Q_PAD_SD3_DAT5__ANATOP_TESTO_11              1264
+MX6Q_PAD_SD3_DAT4__USDHC3_DAT4                  1265
+MX6Q_PAD_SD3_DAT4__UART2_RXD                    1266
+MX6Q_PAD_SD3_DAT4__PCIE_CTRL_MUX_27             1267
+MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3         1268
+MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3         1269
+MX6Q_PAD_SD3_DAT4__GPIO_7_1                     1270
+MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_IN_15         1271
+MX6Q_PAD_SD3_DAT4__ANATOP_TESTO_12              1272
+MX6Q_PAD_SD3_CMD__USDHC3_CMD                    1273
+MX6Q_PAD_SD3_CMD__UART2_CTS                     1274
+MX6Q_PAD_SD3_CMD__CAN1_TXCAN                    1275
+MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4          1276
+MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4          1277
+MX6Q_PAD_SD3_CMD__GPIO_7_2                      1278
+MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_IN_16          1279
+MX6Q_PAD_SD3_CMD__ANATOP_TESTO_13               1280
+MX6Q_PAD_SD3_CLK__USDHC3_CLK                    1281
+MX6Q_PAD_SD3_CLK__UART2_RTS                     1282
+MX6Q_PAD_SD3_CLK__CAN1_RXCAN                    1283
+MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5          1284
+MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5          1285
+MX6Q_PAD_SD3_CLK__GPIO_7_3                      1286
+MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_IN_17          1287
+MX6Q_PAD_SD3_CLK__ANATOP_TESTO_14               1288
+MX6Q_PAD_SD3_DAT0__USDHC3_DAT0                  1289
+MX6Q_PAD_SD3_DAT0__UART1_CTS                    1290
+MX6Q_PAD_SD3_DAT0__CAN2_TXCAN                   1291
+MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6         1292
+MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6         1293
+MX6Q_PAD_SD3_DAT0__GPIO_7_4                     1294
+MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_IN_18         1295
+MX6Q_PAD_SD3_DAT0__ANATOP_TESTO_15              1296
+MX6Q_PAD_SD3_DAT1__USDHC3_DAT1                  1297
+MX6Q_PAD_SD3_DAT1__UART1_RTS                    1298
+MX6Q_PAD_SD3_DAT1__CAN2_RXCAN                   1299
+MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7         1300
+MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7         1301
+MX6Q_PAD_SD3_DAT1__GPIO_7_5                     1302
+MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_IN_19         1303
+MX6Q_PAD_SD3_DAT1__ANATOP_TESTI_0               1304
+MX6Q_PAD_SD3_DAT2__USDHC3_DAT2                  1305
+MX6Q_PAD_SD3_DAT2__PCIE_CTRL_MUX_28             1306
+MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8         1307
+MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8         1308
+MX6Q_PAD_SD3_DAT2__GPIO_7_6                     1309
+MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_IN_20         1310
+MX6Q_PAD_SD3_DAT2__ANATOP_TESTI_1               1311
+MX6Q_PAD_SD3_DAT3__USDHC3_DAT3                  1312
+MX6Q_PAD_SD3_DAT3__UART3_CTS                    1313
+MX6Q_PAD_SD3_DAT3__PCIE_CTRL_MUX_29             1314
+MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9         1315
+MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9         1316
+MX6Q_PAD_SD3_DAT3__GPIO_7_7                     1317
+MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_IN_21         1318
+MX6Q_PAD_SD3_DAT3__ANATOP_TESTI_2               1319
+MX6Q_PAD_SD3_RST__USDHC3_RST                    1320
+MX6Q_PAD_SD3_RST__UART3_RTS                     1321
+MX6Q_PAD_SD3_RST__PCIE_CTRL_MUX_30              1322
+MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10         1323
+MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10         1324
+MX6Q_PAD_SD3_RST__GPIO_7_8                      1325
+MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_IN_22          1326
+MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3         1327
+MX6Q_PAD_NANDF_CLE__RAWNAND_CLE                 1328
+MX6Q_PAD_NANDF_CLE__IPU2_SISG_4                 1329
+MX6Q_PAD_NANDF_CLE__PCIE_CTRL_MUX_31            1330
+MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OT11         1331
+MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OT11         1332
+MX6Q_PAD_NANDF_CLE__GPIO_6_7                    1333
+MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_IN23         1334
+MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0              1335
+MX6Q_PAD_NANDF_ALE__RAWNAND_ALE                 1336
+MX6Q_PAD_NANDF_ALE__USDHC4_RST                  1337
+MX6Q_PAD_NANDF_ALE__PCIE_CTRL_MUX_0             1338
+MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OT12         1339
+MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OT12         1340
+MX6Q_PAD_NANDF_ALE__GPIO_6_8                    1341
+MX6Q_PAD_NANDF_ALE__MIPI_CR_DPHY_IN_24          1342
+MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1              1343
+MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN             1344
+MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5                1345
+MX6Q_PAD_NANDF_WP_B__PCIE_CTRL__MUX_1           1346
+MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFDOT13         1347
+MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFDOT13         1348
+MX6Q_PAD_NANDF_WP_B__GPIO_6_9                   1349
+MX6Q_PAD_NANDF_WP_B__MIPI_CR_DPHY_OUT32         1350
+MX6Q_PAD_NANDF_WP_B__PL301_PER1_HSIZE_0         1351
+MX6Q_PAD_NANDF_RB0__RAWNAND_READY0              1352
+MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1               1353
+MX6Q_PAD_NANDF_RB0__PCIE_CTRL_MUX_2             1354
+MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OT14         1355
+MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OT14         1356
+MX6Q_PAD_NANDF_RB0__GPIO_6_10                   1357
+MX6Q_PAD_NANDF_RB0__MIPI_CR_DPHY_OUT_33         1358
+MX6Q_PAD_NANDF_RB0__PL301_PER1_HSIZE_1          1359
+MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N                1360
+MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OT15         1361
+MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OT15         1362
+MX6Q_PAD_NANDF_CS0__GPIO_6_11                   1363
+MX6Q_PAD_NANDF_CS0__PL301_PER1_HSIZE_2          1364
+MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N                1365
+MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT              1366
+MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT              1367
+MX6Q_PAD_NANDF_CS1__PCIE_CTRL_MUX_3             1368
+MX6Q_PAD_NANDF_CS1__GPIO_6_14                   1369
+MX6Q_PAD_NANDF_CS1__PL301_PER1_HRDYOUT          1370
+MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N                1371
+MX6Q_PAD_NANDF_CS2__IPU1_SISG_0                 1372
+MX6Q_PAD_NANDF_CS2__ESAI1_TX0                   1373
+MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE               1374
+MX6Q_PAD_NANDF_CS2__CCM_CLKO2                   1375
+MX6Q_PAD_NANDF_CS2__GPIO_6_15                   1376
+MX6Q_PAD_NANDF_CS2__IPU2_SISG_0                 1377
+MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N                1378
+MX6Q_PAD_NANDF_CS3__IPU1_SISG_1                 1379
+MX6Q_PAD_NANDF_CS3__ESAI1_TX1                   1380
+MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26              1381
+MX6Q_PAD_NANDF_CS3__PCIE_CTRL_MUX_4             1382
+MX6Q_PAD_NANDF_CS3__GPIO_6_16                   1383
+MX6Q_PAD_NANDF_CS3__IPU2_SISG_1                 1384
+MX6Q_PAD_NANDF_CS3__TPSMP_CLK                   1385
+MX6Q_PAD_SD4_CMD__USDHC4_CMD                    1386
+MX6Q_PAD_SD4_CMD__RAWNAND_RDN                   1387
+MX6Q_PAD_SD4_CMD__UART3_TXD                     1388
+MX6Q_PAD_SD4_CMD__PCIE_CTRL_MUX_5               1389
+MX6Q_PAD_SD4_CMD__GPIO_7_9                      1390
+MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR               1391
+MX6Q_PAD_SD4_CLK__USDHC4_CLK                    1392
+MX6Q_PAD_SD4_CLK__RAWNAND_WRN                   1393
+MX6Q_PAD_SD4_CLK__UART3_RXD                     1394
+MX6Q_PAD_SD4_CLK__PCIE_CTRL_MUX_6               1395
+MX6Q_PAD_SD4_CLK__GPIO_7_10                     1396
+MX6Q_PAD_NANDF_D0__RAWNAND_D0                   1397
+MX6Q_PAD_NANDF_D0__USDHC1_DAT4                  1398
+MX6Q_PAD_NANDF_D0__GPU3D_GPU_DBG_OUT_0          1399
+MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT16         1400
+MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT16         1401
+MX6Q_PAD_NANDF_D0__GPIO_2_0                     1402
+MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0          1403
+MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0          1404
+MX6Q_PAD_NANDF_D1__RAWNAND_D1                   1405
+MX6Q_PAD_NANDF_D1__USDHC1_DAT5                  1406
+MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT1         1407
+MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT17         1408
+MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT17         1409
+MX6Q_PAD_NANDF_D1__GPIO_2_1                     1410
+MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1          1411
+MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1          1412
+MX6Q_PAD_NANDF_D2__RAWNAND_D2                   1413
+MX6Q_PAD_NANDF_D2__USDHC1_DAT6                  1414
+MX6Q_PAD_NANDF_D2__GPU3D_GPU_DBG_OUT_2          1415
+MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT18         1416
+MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT18         1417
+MX6Q_PAD_NANDF_D2__GPIO_2_2                     1418
+MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2          1419
+MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2          1420
+MX6Q_PAD_NANDF_D3__RAWNAND_D3                   1421
+MX6Q_PAD_NANDF_D3__USDHC1_DAT7                  1422
+MX6Q_PAD_NANDF_D3__GPU3D_GPU_DBG_OUT_3          1423
+MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT19         1424
+MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT19         1425
+MX6Q_PAD_NANDF_D3__GPIO_2_3                     1426
+MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3          1427
+MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3          1428
+MX6Q_PAD_NANDF_D4__RAWNAND_D4                   1429
+MX6Q_PAD_NANDF_D4__USDHC2_DAT4                  1430
+MX6Q_PAD_NANDF_D4__GPU3D_GPU_DBG_OUT_4          1431
+MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT20         1432
+MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT20         1433
+MX6Q_PAD_NANDF_D4__GPIO_2_4                     1434
+MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4          1435
+MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4          1436
+MX6Q_PAD_NANDF_D5__RAWNAND_D5                   1437
+MX6Q_PAD_NANDF_D5__USDHC2_DAT5                  1438
+MX6Q_PAD_NANDF_D5__GPU3D_GPU_DBG_OUT_5          1439
+MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT21         1440
+MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT21         1441
+MX6Q_PAD_NANDF_D5__GPIO_2_5                     1442
+MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5          1443
+MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5          1444
+MX6Q_PAD_NANDF_D6__RAWNAND_D6                   1445
+MX6Q_PAD_NANDF_D6__USDHC2_DAT6                  1446
+MX6Q_PAD_NANDF_D6__GPU3D_GPU_DBG_OUT_6          1447
+MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT22         1448
+MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT22         1449
+MX6Q_PAD_NANDF_D6__GPIO_2_6                     1450
+MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6          1451
+MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6          1452
+MX6Q_PAD_NANDF_D7__RAWNAND_D7                   1453
+MX6Q_PAD_NANDF_D7__USDHC2_DAT7                  1454
+MX6Q_PAD_NANDF_D7__GPU3D_GPU_DBG_OUT_7          1455
+MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT23         1456
+MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT23         1457
+MX6Q_PAD_NANDF_D7__GPIO_2_7                     1458
+MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7          1459
+MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7          1460
+MX6Q_PAD_SD4_DAT0__RAWNAND_D8                   1461
+MX6Q_PAD_SD4_DAT0__USDHC4_DAT0                  1462
+MX6Q_PAD_SD4_DAT0__RAWNAND_DQS                  1463
+MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT24         1464
+MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT24         1465
+MX6Q_PAD_SD4_DAT0__GPIO_2_8                     1466
+MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8          1467
+MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8          1468
+MX6Q_PAD_SD4_DAT1__RAWNAND_D9                   1469
+MX6Q_PAD_SD4_DAT1__USDHC4_DAT1                  1470
+MX6Q_PAD_SD4_DAT1__PWM3_PWMO                    1471
+MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT25         1472
+MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT25         1473
+MX6Q_PAD_SD4_DAT1__GPIO_2_9                     1474
+MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9          1475
+MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9          1476
+MX6Q_PAD_SD4_DAT2__RAWNAND_D10                  1477
+MX6Q_PAD_SD4_DAT2__USDHC4_DAT2                  1478
+MX6Q_PAD_SD4_DAT2__PWM4_PWMO                    1479
+MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT26         1480
+MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT26         1481
+MX6Q_PAD_SD4_DAT2__GPIO_2_10                    1482
+MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10         1483
+MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10         1484
+MX6Q_PAD_SD4_DAT3__RAWNAND_D11                  1485
+MX6Q_PAD_SD4_DAT3__USDHC4_DAT3                  1486
+MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT27         1487
+MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT27         1488
+MX6Q_PAD_SD4_DAT3__GPIO_2_11                    1489
+MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11         1490
+MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11         1491
+MX6Q_PAD_SD4_DAT4__RAWNAND_D12                  1492
+MX6Q_PAD_SD4_DAT4__USDHC4_DAT4                  1493
+MX6Q_PAD_SD4_DAT4__UART2_RXD                    1494
+MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT28         1495
+MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT28         1496
+MX6Q_PAD_SD4_DAT4__GPIO_2_12                    1497
+MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12         1498
+MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12         1499
+MX6Q_PAD_SD4_DAT5__RAWNAND_D13                  1500
+MX6Q_PAD_SD4_DAT5__USDHC4_DAT5                  1501
+MX6Q_PAD_SD4_DAT5__UART2_RTS                    1502
+MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT29         1503
+MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT29         1504
+MX6Q_PAD_SD4_DAT5__GPIO_2_13                    1505
+MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13         1506
+MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13         1507
+MX6Q_PAD_SD4_DAT6__RAWNAND_D14                  1508
+MX6Q_PAD_SD4_DAT6__USDHC4_DAT6                  1509
+MX6Q_PAD_SD4_DAT6__UART2_CTS                    1510
+MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT30         1511
+MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT30         1512
+MX6Q_PAD_SD4_DAT6__GPIO_2_14                    1513
+MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14         1514
+MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14         1515
+MX6Q_PAD_SD4_DAT7__RAWNAND_D15                  1516
+MX6Q_PAD_SD4_DAT7__USDHC4_DAT7                  1517
+MX6Q_PAD_SD4_DAT7__UART2_TXD                    1518
+MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT31         1519
+MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT31         1520
+MX6Q_PAD_SD4_DAT7__GPIO_2_15                    1521
+MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15         1522
+MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15         1523
+MX6Q_PAD_SD1_DAT1__USDHC1_DAT1                  1524
+MX6Q_PAD_SD1_DAT1__ECSPI5_SS0                   1525
+MX6Q_PAD_SD1_DAT1__PWM3_PWMO                    1526
+MX6Q_PAD_SD1_DAT1__GPT_CAPIN2                   1527
+MX6Q_PAD_SD1_DAT1__PCIE_CTRL_MUX_7              1528
+MX6Q_PAD_SD1_DAT1__GPIO_1_17                    1529
+MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0            1530
+MX6Q_PAD_SD1_DAT1__ANATOP_TESTO_8               1531
+MX6Q_PAD_SD1_DAT0__USDHC1_DAT0                  1532
+MX6Q_PAD_SD1_DAT0__ECSPI5_MISO                  1533
+MX6Q_PAD_SD1_DAT0__CAAM_WRAP_RNG_OSCOBS         1534
+MX6Q_PAD_SD1_DAT0__GPT_CAPIN1                   1535
+MX6Q_PAD_SD1_DAT0__PCIE_CTRL_MUX_8              1536
+MX6Q_PAD_SD1_DAT0__GPIO_1_16                    1537
+MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1            1538
+MX6Q_PAD_SD1_DAT0__ANATOP_TESTO_7               1539
+MX6Q_PAD_SD1_DAT3__USDHC1_DAT3                  1540
+MX6Q_PAD_SD1_DAT3__ECSPI5_SS2                   1541
+MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3                  1542
+MX6Q_PAD_SD1_DAT3__PWM1_PWMO                    1543
+MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B                 1544
+MX6Q_PAD_SD1_DAT3__GPIO_1_21                    1545
+MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB         1546
+MX6Q_PAD_SD1_DAT3__ANATOP_TESTO_6               1547
+MX6Q_PAD_SD1_CMD__USDHC1_CMD                    1548
+MX6Q_PAD_SD1_CMD__ECSPI5_MOSI                   1549
+MX6Q_PAD_SD1_CMD__PWM4_PWMO                     1550
+MX6Q_PAD_SD1_CMD__GPT_CMPOUT1                   1551
+MX6Q_PAD_SD1_CMD__GPIO_1_18                     1552
+MX6Q_PAD_SD1_CMD__ANATOP_TESTO_5                1553
+MX6Q_PAD_SD1_DAT2__USDHC1_DAT2                  1554
+MX6Q_PAD_SD1_DAT2__ECSPI5_SS1                   1555
+MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2                  1556
+MX6Q_PAD_SD1_DAT2__PWM2_PWMO                    1557
+MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B                 1558
+MX6Q_PAD_SD1_DAT2__GPIO_1_19                    1559
+MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB         1560
+MX6Q_PAD_SD1_DAT2__ANATOP_TESTO_4               1561
+MX6Q_PAD_SD1_CLK__USDHC1_CLK                    1562
+MX6Q_PAD_SD1_CLK__ECSPI5_SCLK                   1563
+MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT                1564
+MX6Q_PAD_SD1_CLK__GPT_CLKIN                     1565
+MX6Q_PAD_SD1_CLK__GPIO_1_20                     1566
+MX6Q_PAD_SD1_CLK__PHY_DTB_0                     1567
+MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0                1568
+MX6Q_PAD_SD2_CLK__USDHC2_CLK                    1569
+MX6Q_PAD_SD2_CLK__ECSPI5_SCLK                   1570
+MX6Q_PAD_SD2_CLK__KPP_COL_5                     1571
+MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS              1572
+MX6Q_PAD_SD2_CLK__PCIE_CTRL_MUX_9               1573
+MX6Q_PAD_SD2_CLK__GPIO_1_10                     1574
+MX6Q_PAD_SD2_CLK__PHY_DTB_1                     1575
+MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1                1576
+MX6Q_PAD_SD2_CMD__USDHC2_CMD                    1577
+MX6Q_PAD_SD2_CMD__ECSPI5_MOSI                   1578
+MX6Q_PAD_SD2_CMD__KPP_ROW_5                     1579
+MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC               1580
+MX6Q_PAD_SD2_CMD__PCIE_CTRL_MUX_10              1581
+MX6Q_PAD_SD2_CMD__GPIO_1_11                     1582
+MX6Q_PAD_SD2_DAT3__USDHC2_DAT3                  1583
+MX6Q_PAD_SD2_DAT3__ECSPI5_SS3                   1584
+MX6Q_PAD_SD2_DAT3__KPP_COL_6                    1585
+MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC              1586
+MX6Q_PAD_SD2_DAT3__PCIE_CTRL_MUX_11             1587
+MX6Q_PAD_SD2_DAT3__GPIO_1_12                    1588
+MX6Q_PAD_SD2_DAT3__SJC_DONE                     1589
+MX6Q_PAD_SD2_DAT3__ANATOP_TESTO_3               1590
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt
new file mode 100644
index 000000000000..f7e8e8f4d9a3
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt
@@ -0,0 +1,918 @@
+* Freescale MXS Pin Controller
+
+The pins controlled by mxs pin controller are organized in banks, each bank
+has 32 pins.  Each pin has 4 multiplexing functions, and generally, the 4th
+function is GPIO.  The configuration on the pins includes drive strength,
+voltage and pull-up.
+
+Required properties:
+- compatible: "fsl,imx23-pinctrl" or "fsl,imx28-pinctrl"
+- reg: Should contain the register physical address and length for the
+  pin controller.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices.
+
+The node of mxs pin controller acts as a container for an arbitrary number of
+subnodes.  Each of these subnodes represents some desired configuration for
+a group of pins, and only affects those parameters that are explicitly listed.
+In other words, a subnode that describes a drive strength parameter implies no
+information about pull-up. For this reason, even seemingly boolean values are
+actually tristates in this binding: unspecified, off, or on. Unspecified is
+represented as an absent property, and off/on are represented as integer
+values 0 and 1.
+
+Those subnodes under mxs pin controller node will fall into two categories.
+One is to set up a group of pins for a function, both mux selection and pin
+configurations, and it's called group node in the binding document.   The other
+one is to adjust the pin configuration for some particular pins that need a
+different configuration than what is defined in group node.  The binding
+document calls this type of node config node.
+
+On mxs, there is no hardware pin group. The pin group in this binding only
+means a group of pins put together for particular peripheral to work in
+particular function, like SSP0 functioning as mmc0-8bit.  That said, the
+group node should include all the pins needed for one function rather than
+having these pins defined in several group nodes.  It also means each of
+"pinctrl-*" phandle in client device node should only have one group node
+pointed in there, while the phandle can have multiple config node referenced
+there to adjust configurations for some pins in the group.
+
+Required subnode-properties:
+- fsl,pinmux-ids: An integer array.  Each integer in the array specify a pin
+  with given mux function, with bank, pin and mux packed as below.
+
+    [15..12] : bank number
+    [11..4]  : pin number
+    [3..0]   : mux selection
+
+  This integer with mux selection packed is used as an entity by both group
+  and config nodes to identify a pin.  The mux selection in the integer takes
+  effects only on group node, and will get ignored by driver with config node,
+  since config node is only meant to set up pin configurations.
+
+  Valid values for these integers are listed below.
+
+- reg: Should be the index of the group nodes for same function.  This property
+  is required only for group nodes, and should not be present in any config
+  nodes.
+
+Optional subnode-properties:
+- fsl,drive-strength: Integer.
+    0: 4 mA
+    1: 8 mA
+    2: 12 mA
+    3: 16 mA
+- fsl,voltage: Integer.
+    0: 1.8 V
+    1: 3.3 V
+- fsl,pull-up: Integer.
+    0: Disable the internal pull-up
+    1: Enable the internal pull-up
+
+Examples:
+
+pinctrl@80018000 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        compatible = "fsl,imx28-pinctrl";
+        reg = <0x80018000 2000>;
+
+        mmc0_8bit_pins_a: mmc0-8bit@0 {
+                reg = <0>;
+                fsl,pinmux-ids = <
+                        0x2000 0x2010 0x2020 0x2030
+                        0x2040 0x2050 0x2060 0x2070
+                        0x2080 0x2090 0x20a0>;
+                fsl,drive-strength = <1>;
+                fsl,voltage = <1>;
+                fsl,pull-up = <1>;
+        };
+
+        mmc_cd_cfg: mmc-cd-cfg {
+                fsl,pinmux-ids = <0x2090>;
+                fsl,pull-up = <0>;
+        };
+
+        mmc_sck_cfg: mmc-sck-cfg {
+                fsl,pinmux-ids = <0x20a0>;
+                fsl,drive-strength = <2>;
+                fsl,pull-up = <0>;
+        };
+};
+
+In this example, group node mmc0-8bit defines a group of pins for mxs SSP0
+to function as a 8-bit mmc device, with 8mA, 3.3V and pull-up configurations
+applied on all these pins.  And config nodes mmc-cd-cfg and mmc-sck-cfg are
+adjusting the configuration for pins card-detection and clock from what group
+node mmc0-8bit defines.  Only the configuration properties to be adjusted need
+to be listed in the config nodes.
+
+Valid values for i.MX28 pinmux-id:
+
+pinmux                                          id
+------                                          --
+MX28_PAD_GPMI_D00__GPMI_D0                      0x0000
+MX28_PAD_GPMI_D01__GPMI_D1                      0x0010
+MX28_PAD_GPMI_D02__GPMI_D2                      0x0020
+MX28_PAD_GPMI_D03__GPMI_D3                      0x0030
+MX28_PAD_GPMI_D04__GPMI_D4                      0x0040
+MX28_PAD_GPMI_D05__GPMI_D5                      0x0050
+MX28_PAD_GPMI_D06__GPMI_D6                      0x0060
+MX28_PAD_GPMI_D07__GPMI_D7                      0x0070
+MX28_PAD_GPMI_CE0N__GPMI_CE0N                   0x0100
+MX28_PAD_GPMI_CE1N__GPMI_CE1N                   0x0110
+MX28_PAD_GPMI_CE2N__GPMI_CE2N                   0x0120
+MX28_PAD_GPMI_CE3N__GPMI_CE3N                   0x0130
+MX28_PAD_GPMI_RDY0__GPMI_READY0                 0x0140
+MX28_PAD_GPMI_RDY1__GPMI_READY1                 0x0150
+MX28_PAD_GPMI_RDY2__GPMI_READY2                 0x0160
+MX28_PAD_GPMI_RDY3__GPMI_READY3                 0x0170
+MX28_PAD_GPMI_RDN__GPMI_RDN                     0x0180
+MX28_PAD_GPMI_WRN__GPMI_WRN                     0x0190
+MX28_PAD_GPMI_ALE__GPMI_ALE                     0x01a0
+MX28_PAD_GPMI_CLE__GPMI_CLE                     0x01b0
+MX28_PAD_GPMI_RESETN__GPMI_RESETN               0x01c0
+MX28_PAD_LCD_D00__LCD_D0                        0x1000
+MX28_PAD_LCD_D01__LCD_D1                        0x1010
+MX28_PAD_LCD_D02__LCD_D2                        0x1020
+MX28_PAD_LCD_D03__LCD_D3                        0x1030
+MX28_PAD_LCD_D04__LCD_D4                        0x1040
+MX28_PAD_LCD_D05__LCD_D5                        0x1050
+MX28_PAD_LCD_D06__LCD_D6                        0x1060
+MX28_PAD_LCD_D07__LCD_D7                        0x1070
+MX28_PAD_LCD_D08__LCD_D8                        0x1080
+MX28_PAD_LCD_D09__LCD_D9                        0x1090
+MX28_PAD_LCD_D10__LCD_D10                       0x10a0
+MX28_PAD_LCD_D11__LCD_D11                       0x10b0
+MX28_PAD_LCD_D12__LCD_D12                       0x10c0
+MX28_PAD_LCD_D13__LCD_D13                       0x10d0
+MX28_PAD_LCD_D14__LCD_D14                       0x10e0
+MX28_PAD_LCD_D15__LCD_D15                       0x10f0
+MX28_PAD_LCD_D16__LCD_D16                       0x1100
+MX28_PAD_LCD_D17__LCD_D17                       0x1110
+MX28_PAD_LCD_D18__LCD_D18                       0x1120
+MX28_PAD_LCD_D19__LCD_D19                       0x1130
+MX28_PAD_LCD_D20__LCD_D20                       0x1140
+MX28_PAD_LCD_D21__LCD_D21                       0x1150
+MX28_PAD_LCD_D22__LCD_D22                       0x1160
+MX28_PAD_LCD_D23__LCD_D23                       0x1170
+MX28_PAD_LCD_RD_E__LCD_RD_E                     0x1180
+MX28_PAD_LCD_WR_RWN__LCD_WR_RWN                 0x1190
+MX28_PAD_LCD_RS__LCD_RS                         0x11a0
+MX28_PAD_LCD_CS__LCD_CS                         0x11b0
+MX28_PAD_LCD_VSYNC__LCD_VSYNC                   0x11c0
+MX28_PAD_LCD_HSYNC__LCD_HSYNC                   0x11d0
+MX28_PAD_LCD_DOTCLK__LCD_DOTCLK                 0x11e0
+MX28_PAD_LCD_ENABLE__LCD_ENABLE                 0x11f0
+MX28_PAD_SSP0_DATA0__SSP0_D0                    0x2000
+MX28_PAD_SSP0_DATA1__SSP0_D1                    0x2010
+MX28_PAD_SSP0_DATA2__SSP0_D2                    0x2020
+MX28_PAD_SSP0_DATA3__SSP0_D3                    0x2030
+MX28_PAD_SSP0_DATA4__SSP0_D4                    0x2040
+MX28_PAD_SSP0_DATA5__SSP0_D5                    0x2050
+MX28_PAD_SSP0_DATA6__SSP0_D6                    0x2060
+MX28_PAD_SSP0_DATA7__SSP0_D7                    0x2070
+MX28_PAD_SSP0_CMD__SSP0_CMD                     0x2080
+MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT          0x2090
+MX28_PAD_SSP0_SCK__SSP0_SCK                     0x20a0
+MX28_PAD_SSP1_SCK__SSP1_SCK                     0x20c0
+MX28_PAD_SSP1_CMD__SSP1_CMD                     0x20d0
+MX28_PAD_SSP1_DATA0__SSP1_D0                    0x20e0
+MX28_PAD_SSP1_DATA3__SSP1_D3                    0x20f0
+MX28_PAD_SSP2_SCK__SSP2_SCK                     0x2100
+MX28_PAD_SSP2_MOSI__SSP2_CMD                    0x2110
+MX28_PAD_SSP2_MISO__SSP2_D0                     0x2120
+MX28_PAD_SSP2_SS0__SSP2_D3                      0x2130
+MX28_PAD_SSP2_SS1__SSP2_D4                      0x2140
+MX28_PAD_SSP2_SS2__SSP2_D5                      0x2150
+MX28_PAD_SSP3_SCK__SSP3_SCK                     0x2180
+MX28_PAD_SSP3_MOSI__SSP3_CMD                    0x2190
+MX28_PAD_SSP3_MISO__SSP3_D0                     0x21a0
+MX28_PAD_SSP3_SS0__SSP3_D3                      0x21b0
+MX28_PAD_AUART0_RX__AUART0_RX                   0x3000
+MX28_PAD_AUART0_TX__AUART0_TX                   0x3010
+MX28_PAD_AUART0_CTS__AUART0_CTS                 0x3020
+MX28_PAD_AUART0_RTS__AUART0_RTS                 0x3030
+MX28_PAD_AUART1_RX__AUART1_RX                   0x3040
+MX28_PAD_AUART1_TX__AUART1_TX                   0x3050
+MX28_PAD_AUART1_CTS__AUART1_CTS                 0x3060
+MX28_PAD_AUART1_RTS__AUART1_RTS                 0x3070
+MX28_PAD_AUART2_RX__AUART2_RX                   0x3080
+MX28_PAD_AUART2_TX__AUART2_TX                   0x3090
+MX28_PAD_AUART2_CTS__AUART2_CTS                 0x30a0
+MX28_PAD_AUART2_RTS__AUART2_RTS                 0x30b0
+MX28_PAD_AUART3_RX__AUART3_RX                   0x30c0
+MX28_PAD_AUART3_TX__AUART3_TX                   0x30d0
+MX28_PAD_AUART3_CTS__AUART3_CTS                 0x30e0
+MX28_PAD_AUART3_RTS__AUART3_RTS                 0x30f0
+MX28_PAD_PWM0__PWM_0                            0x3100
+MX28_PAD_PWM1__PWM_1                            0x3110
+MX28_PAD_PWM2__PWM_2                            0x3120
+MX28_PAD_SAIF0_MCLK__SAIF0_MCLK                 0x3140
+MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK               0x3150
+MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK             0x3160
+MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0             0x3170
+MX28_PAD_I2C0_SCL__I2C0_SCL                     0x3180
+MX28_PAD_I2C0_SDA__I2C0_SDA                     0x3190
+MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0             0x31a0
+MX28_PAD_SPDIF__SPDIF_TX                        0x31b0
+MX28_PAD_PWM3__PWM_3                            0x31c0
+MX28_PAD_PWM4__PWM_4                            0x31d0
+MX28_PAD_LCD_RESET__LCD_RESET                   0x31e0
+MX28_PAD_ENET0_MDC__ENET0_MDC                   0x4000
+MX28_PAD_ENET0_MDIO__ENET0_MDIO                 0x4010
+MX28_PAD_ENET0_RX_EN__ENET0_RX_EN               0x4020
+MX28_PAD_ENET0_RXD0__ENET0_RXD0                 0x4030
+MX28_PAD_ENET0_RXD1__ENET0_RXD1                 0x4040
+MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK             0x4050
+MX28_PAD_ENET0_TX_EN__ENET0_TX_EN               0x4060
+MX28_PAD_ENET0_TXD0__ENET0_TXD0                 0x4070
+MX28_PAD_ENET0_TXD1__ENET0_TXD1                 0x4080
+MX28_PAD_ENET0_RXD2__ENET0_RXD2                 0x4090
+MX28_PAD_ENET0_RXD3__ENET0_RXD3                 0x40a0
+MX28_PAD_ENET0_TXD2__ENET0_TXD2                 0x40b0
+MX28_PAD_ENET0_TXD3__ENET0_TXD3                 0x40c0
+MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK             0x40d0
+MX28_PAD_ENET0_COL__ENET0_COL                   0x40e0
+MX28_PAD_ENET0_CRS__ENET0_CRS                   0x40f0
+MX28_PAD_ENET_CLK__CLKCTRL_ENET                 0x4100
+MX28_PAD_JTAG_RTCK__JTAG_RTCK                   0x4140
+MX28_PAD_EMI_D00__EMI_DATA0                     0x5000
+MX28_PAD_EMI_D01__EMI_DATA1                     0x5010
+MX28_PAD_EMI_D02__EMI_DATA2                     0x5020
+MX28_PAD_EMI_D03__EMI_DATA3                     0x5030
+MX28_PAD_EMI_D04__EMI_DATA4                     0x5040
+MX28_PAD_EMI_D05__EMI_DATA5                     0x5050
+MX28_PAD_EMI_D06__EMI_DATA6                     0x5060
+MX28_PAD_EMI_D07__EMI_DATA7                     0x5070
+MX28_PAD_EMI_D08__EMI_DATA8                     0x5080
+MX28_PAD_EMI_D09__EMI_DATA9                     0x5090
+MX28_PAD_EMI_D10__EMI_DATA10                    0x50a0
+MX28_PAD_EMI_D11__EMI_DATA11                    0x50b0
+MX28_PAD_EMI_D12__EMI_DATA12                    0x50c0
+MX28_PAD_EMI_D13__EMI_DATA13                    0x50d0
+MX28_PAD_EMI_D14__EMI_DATA14                    0x50e0
+MX28_PAD_EMI_D15__EMI_DATA15                    0x50f0
+MX28_PAD_EMI_ODT0__EMI_ODT0                     0x5100
+MX28_PAD_EMI_DQM0__EMI_DQM0                     0x5110
+MX28_PAD_EMI_ODT1__EMI_ODT1                     0x5120
+MX28_PAD_EMI_DQM1__EMI_DQM1                     0x5130
+MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK 0x5140
+MX28_PAD_EMI_CLK__EMI_CLK                       0x5150
+MX28_PAD_EMI_DQS0__EMI_DQS0                     0x5160
+MX28_PAD_EMI_DQS1__EMI_DQS1                     0x5170
+MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN             0x51a0
+MX28_PAD_EMI_A00__EMI_ADDR0                     0x6000
+MX28_PAD_EMI_A01__EMI_ADDR1                     0x6010
+MX28_PAD_EMI_A02__EMI_ADDR2                     0x6020
+MX28_PAD_EMI_A03__EMI_ADDR3                     0x6030
+MX28_PAD_EMI_A04__EMI_ADDR4                     0x6040
+MX28_PAD_EMI_A05__EMI_ADDR5                     0x6050
+MX28_PAD_EMI_A06__EMI_ADDR6                     0x6060
+MX28_PAD_EMI_A07__EMI_ADDR7                     0x6070
+MX28_PAD_EMI_A08__EMI_ADDR8                     0x6080
+MX28_PAD_EMI_A09__EMI_ADDR9                     0x6090
+MX28_PAD_EMI_A10__EMI_ADDR10                    0x60a0
+MX28_PAD_EMI_A11__EMI_ADDR11                    0x60b0
+MX28_PAD_EMI_A12__EMI_ADDR12                    0x60c0
+MX28_PAD_EMI_A13__EMI_ADDR13                    0x60d0
+MX28_PAD_EMI_A14__EMI_ADDR14                    0x60e0
+MX28_PAD_EMI_BA0__EMI_BA0                       0x6100
+MX28_PAD_EMI_BA1__EMI_BA1                       0x6110
+MX28_PAD_EMI_BA2__EMI_BA2                       0x6120
+MX28_PAD_EMI_CASN__EMI_CASN                     0x6130
+MX28_PAD_EMI_RASN__EMI_RASN                     0x6140
+MX28_PAD_EMI_WEN__EMI_WEN                       0x6150
+MX28_PAD_EMI_CE0N__EMI_CE0N                     0x6160
+MX28_PAD_EMI_CE1N__EMI_CE1N                     0x6170
+MX28_PAD_EMI_CKE__EMI_CKE                       0x6180
+MX28_PAD_GPMI_D00__SSP1_D0                      0x0001
+MX28_PAD_GPMI_D01__SSP1_D1                      0x0011
+MX28_PAD_GPMI_D02__SSP1_D2                      0x0021
+MX28_PAD_GPMI_D03__SSP1_D3                      0x0031
+MX28_PAD_GPMI_D04__SSP1_D4                      0x0041
+MX28_PAD_GPMI_D05__SSP1_D5                      0x0051
+MX28_PAD_GPMI_D06__SSP1_D6                      0x0061
+MX28_PAD_GPMI_D07__SSP1_D7                      0x0071
+MX28_PAD_GPMI_CE0N__SSP3_D0                     0x0101
+MX28_PAD_GPMI_CE1N__SSP3_D3                     0x0111
+MX28_PAD_GPMI_CE2N__CAN1_TX                     0x0121
+MX28_PAD_GPMI_CE3N__CAN1_RX                     0x0131
+MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT            0x0141
+MX28_PAD_GPMI_RDY1__SSP1_CMD                    0x0151
+MX28_PAD_GPMI_RDY2__CAN0_TX                     0x0161
+MX28_PAD_GPMI_RDY3__CAN0_RX                     0x0171
+MX28_PAD_GPMI_RDN__SSP3_SCK                     0x0181
+MX28_PAD_GPMI_WRN__SSP1_SCK                     0x0191
+MX28_PAD_GPMI_ALE__SSP3_D1                      0x01a1
+MX28_PAD_GPMI_CLE__SSP3_D2                      0x01b1
+MX28_PAD_GPMI_RESETN__SSP3_CMD                  0x01c1
+MX28_PAD_LCD_D03__ETM_DA8                       0x1031
+MX28_PAD_LCD_D04__ETM_DA9                       0x1041
+MX28_PAD_LCD_D08__ETM_DA3                       0x1081
+MX28_PAD_LCD_D09__ETM_DA4                       0x1091
+MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT         0x1141
+MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN          0x1151
+MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT         0x1161
+MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN          0x1171
+MX28_PAD_LCD_RD_E__LCD_VSYNC                    0x1181
+MX28_PAD_LCD_WR_RWN__LCD_HSYNC                  0x1191
+MX28_PAD_LCD_RS__LCD_DOTCLK                     0x11a1
+MX28_PAD_LCD_CS__LCD_ENABLE                     0x11b1
+MX28_PAD_LCD_VSYNC__SAIF1_SDATA0                0x11c1
+MX28_PAD_LCD_HSYNC__SAIF1_SDATA1                0x11d1
+MX28_PAD_LCD_DOTCLK__SAIF1_MCLK                 0x11e1
+MX28_PAD_SSP0_DATA4__SSP2_D0                    0x2041
+MX28_PAD_SSP0_DATA5__SSP2_D3                    0x2051
+MX28_PAD_SSP0_DATA6__SSP2_CMD                   0x2061
+MX28_PAD_SSP0_DATA7__SSP2_SCK                   0x2071
+MX28_PAD_SSP1_SCK__SSP2_D1                      0x20c1
+MX28_PAD_SSP1_CMD__SSP2_D2                      0x20d1
+MX28_PAD_SSP1_DATA0__SSP2_D6                    0x20e1
+MX28_PAD_SSP1_DATA3__SSP2_D7                    0x20f1
+MX28_PAD_SSP2_SCK__AUART2_RX                    0x2101
+MX28_PAD_SSP2_MOSI__AUART2_TX                   0x2111
+MX28_PAD_SSP2_MISO__AUART3_RX                   0x2121
+MX28_PAD_SSP2_SS0__AUART3_TX                    0x2131
+MX28_PAD_SSP2_SS1__SSP2_D1                      0x2141
+MX28_PAD_SSP2_SS2__SSP2_D2                      0x2151
+MX28_PAD_SSP3_SCK__AUART4_TX                    0x2181
+MX28_PAD_SSP3_MOSI__AUART4_RX                   0x2191
+MX28_PAD_SSP3_MISO__AUART4_RTS                  0x21a1
+MX28_PAD_SSP3_SS0__AUART4_CTS                   0x21b1
+MX28_PAD_AUART0_RX__I2C0_SCL                    0x3001
+MX28_PAD_AUART0_TX__I2C0_SDA                    0x3011
+MX28_PAD_AUART0_CTS__AUART4_RX                  0x3021
+MX28_PAD_AUART0_RTS__AUART4_TX                  0x3031
+MX28_PAD_AUART1_RX__SSP2_CARD_DETECT            0x3041
+MX28_PAD_AUART1_TX__SSP3_CARD_DETECT            0x3051
+MX28_PAD_AUART1_CTS__USB0_OVERCURRENT           0x3061
+MX28_PAD_AUART1_RTS__USB0_ID                    0x3071
+MX28_PAD_AUART2_RX__SSP3_D1                     0x3081
+MX28_PAD_AUART2_TX__SSP3_D2                     0x3091
+MX28_PAD_AUART2_CTS__I2C1_SCL                   0x30a1
+MX28_PAD_AUART2_RTS__I2C1_SDA                   0x30b1
+MX28_PAD_AUART3_RX__CAN0_TX                     0x30c1
+MX28_PAD_AUART3_TX__CAN0_RX                     0x30d1
+MX28_PAD_AUART3_CTS__CAN1_TX                    0x30e1
+MX28_PAD_AUART3_RTS__CAN1_RX                    0x30f1
+MX28_PAD_PWM0__I2C1_SCL                         0x3101
+MX28_PAD_PWM1__I2C1_SDA                         0x3111
+MX28_PAD_PWM2__USB0_ID                          0x3121
+MX28_PAD_SAIF0_MCLK__PWM_3                      0x3141
+MX28_PAD_SAIF0_LRCLK__PWM_4                     0x3151
+MX28_PAD_SAIF0_BITCLK__PWM_5                    0x3161
+MX28_PAD_SAIF0_SDATA0__PWM_6                    0x3171
+MX28_PAD_I2C0_SCL__TIMROT_ROTARYA               0x3181
+MX28_PAD_I2C0_SDA__TIMROT_ROTARYB               0x3191
+MX28_PAD_SAIF1_SDATA0__PWM_7                    0x31a1
+MX28_PAD_LCD_RESET__LCD_VSYNC                   0x31e1
+MX28_PAD_ENET0_MDC__GPMI_CE4N                   0x4001
+MX28_PAD_ENET0_MDIO__GPMI_CE5N                  0x4011
+MX28_PAD_ENET0_RX_EN__GPMI_CE6N                 0x4021
+MX28_PAD_ENET0_RXD0__GPMI_CE7N                  0x4031
+MX28_PAD_ENET0_RXD1__GPMI_READY4                0x4041
+MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER            0x4051
+MX28_PAD_ENET0_TX_EN__GPMI_READY5               0x4061
+MX28_PAD_ENET0_TXD0__GPMI_READY6                0x4071
+MX28_PAD_ENET0_TXD1__GPMI_READY7                0x4081
+MX28_PAD_ENET0_RXD2__ENET1_RXD0                 0x4091
+MX28_PAD_ENET0_RXD3__ENET1_RXD1                 0x40a1
+MX28_PAD_ENET0_TXD2__ENET1_TXD0                 0x40b1
+MX28_PAD_ENET0_TXD3__ENET1_TXD1                 0x40c1
+MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER              0x40d1
+MX28_PAD_ENET0_COL__ENET1_TX_EN                 0x40e1
+MX28_PAD_ENET0_CRS__ENET1_RX_EN                 0x40f1
+MX28_PAD_GPMI_CE2N__ENET0_RX_ER                 0x0122
+MX28_PAD_GPMI_CE3N__SAIF1_MCLK                  0x0132
+MX28_PAD_GPMI_RDY0__USB0_ID                     0x0142
+MX28_PAD_GPMI_RDY2__ENET0_TX_ER                 0x0162
+MX28_PAD_GPMI_RDY3__HSADC_TRIGGER               0x0172
+MX28_PAD_GPMI_ALE__SSP3_D4                      0x01a2
+MX28_PAD_GPMI_CLE__SSP3_D5                      0x01b2
+MX28_PAD_LCD_D00__ETM_DA0                       0x1002
+MX28_PAD_LCD_D01__ETM_DA1                       0x1012
+MX28_PAD_LCD_D02__ETM_DA2                       0x1022
+MX28_PAD_LCD_D03__ETM_DA3                       0x1032
+MX28_PAD_LCD_D04__ETM_DA4                       0x1042
+MX28_PAD_LCD_D05__ETM_DA5                       0x1052
+MX28_PAD_LCD_D06__ETM_DA6                       0x1062
+MX28_PAD_LCD_D07__ETM_DA7                       0x1072
+MX28_PAD_LCD_D08__ETM_DA8                       0x1082
+MX28_PAD_LCD_D09__ETM_DA9                       0x1092
+MX28_PAD_LCD_D10__ETM_DA10                      0x10a2
+MX28_PAD_LCD_D11__ETM_DA11                      0x10b2
+MX28_PAD_LCD_D12__ETM_DA12                      0x10c2
+MX28_PAD_LCD_D13__ETM_DA13                      0x10d2
+MX28_PAD_LCD_D14__ETM_DA14                      0x10e2
+MX28_PAD_LCD_D15__ETM_DA15                      0x10f2
+MX28_PAD_LCD_D16__ETM_DA7                       0x1102
+MX28_PAD_LCD_D17__ETM_DA6                       0x1112
+MX28_PAD_LCD_D18__ETM_DA5                       0x1122
+MX28_PAD_LCD_D19__ETM_DA4                       0x1132
+MX28_PAD_LCD_D20__ETM_DA3                       0x1142
+MX28_PAD_LCD_D21__ETM_DA2                       0x1152
+MX28_PAD_LCD_D22__ETM_DA1                       0x1162
+MX28_PAD_LCD_D23__ETM_DA0                       0x1172
+MX28_PAD_LCD_RD_E__ETM_TCTL                     0x1182
+MX28_PAD_LCD_WR_RWN__ETM_TCLK                   0x1192
+MX28_PAD_LCD_HSYNC__ETM_TCTL                    0x11d2
+MX28_PAD_LCD_DOTCLK__ETM_TCLK                   0x11e2
+MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT        0x20c2
+MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN         0x20d2
+MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT      0x20e2
+MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN       0x20f2
+MX28_PAD_SSP2_SCK__SAIF0_SDATA1                 0x2102
+MX28_PAD_SSP2_MOSI__SAIF0_SDATA2                0x2112
+MX28_PAD_SSP2_MISO__SAIF1_SDATA1                0x2122
+MX28_PAD_SSP2_SS0__SAIF1_SDATA2                 0x2132
+MX28_PAD_SSP2_SS1__USB1_OVERCURRENT             0x2142
+MX28_PAD_SSP2_SS2__USB0_OVERCURRENT             0x2152
+MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT        0x2182
+MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN        0x2192
+MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT       0x21a2
+MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN         0x21b2
+MX28_PAD_AUART0_RX__DUART_CTS                   0x3002
+MX28_PAD_AUART0_TX__DUART_RTS                   0x3012
+MX28_PAD_AUART0_CTS__DUART_RX                   0x3022
+MX28_PAD_AUART0_RTS__DUART_TX                   0x3032
+MX28_PAD_AUART1_RX__PWM_0                       0x3042
+MX28_PAD_AUART1_TX__PWM_1                       0x3052
+MX28_PAD_AUART1_CTS__TIMROT_ROTARYA             0x3062
+MX28_PAD_AUART1_RTS__TIMROT_ROTARYB             0x3072
+MX28_PAD_AUART2_RX__SSP3_D4                     0x3082
+MX28_PAD_AUART2_TX__SSP3_D5                     0x3092
+MX28_PAD_AUART2_CTS__SAIF1_BITCLK               0x30a2
+MX28_PAD_AUART2_RTS__SAIF1_LRCLK                0x30b2
+MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT       0x30c2
+MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN        0x30d2
+MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT      0x30e2
+MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN       0x30f2
+MX28_PAD_PWM0__DUART_RX                         0x3102
+MX28_PAD_PWM1__DUART_TX                         0x3112
+MX28_PAD_PWM2__USB1_OVERCURRENT                 0x3122
+MX28_PAD_SAIF0_MCLK__AUART4_CTS                 0x3142
+MX28_PAD_SAIF0_LRCLK__AUART4_RTS                0x3152
+MX28_PAD_SAIF0_BITCLK__AUART4_RX                0x3162
+MX28_PAD_SAIF0_SDATA0__AUART4_TX                0x3172
+MX28_PAD_I2C0_SCL__DUART_RX                     0x3182
+MX28_PAD_I2C0_SDA__DUART_TX                     0x3192
+MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1             0x31a2
+MX28_PAD_SPDIF__ENET1_RX_ER                     0x31b2
+MX28_PAD_ENET0_MDC__SAIF0_SDATA1                0x4002
+MX28_PAD_ENET0_MDIO__SAIF0_SDATA2               0x4012
+MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1              0x4022
+MX28_PAD_ENET0_RXD0__SAIF1_SDATA2               0x4032
+MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT    0x4052
+MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT      0x4092
+MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN       0x40a2
+MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT      0x40b2
+MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN       0x40c2
+MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN     0x40d2
+MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT       0x40e2
+MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN        0x40f2
+MX28_PAD_GPMI_D00__GPIO_0_0                     0x0003
+MX28_PAD_GPMI_D01__GPIO_0_1                     0x0013
+MX28_PAD_GPMI_D02__GPIO_0_2                     0x0023
+MX28_PAD_GPMI_D03__GPIO_0_3                     0x0033
+MX28_PAD_GPMI_D04__GPIO_0_4                     0x0043
+MX28_PAD_GPMI_D05__GPIO_0_5                     0x0053
+MX28_PAD_GPMI_D06__GPIO_0_6                     0x0063
+MX28_PAD_GPMI_D07__GPIO_0_7                     0x0073
+MX28_PAD_GPMI_CE0N__GPIO_0_16                   0x0103
+MX28_PAD_GPMI_CE1N__GPIO_0_17                   0x0113
+MX28_PAD_GPMI_CE2N__GPIO_0_18                   0x0123
+MX28_PAD_GPMI_CE3N__GPIO_0_19                   0x0133
+MX28_PAD_GPMI_RDY0__GPIO_0_20                   0x0143
+MX28_PAD_GPMI_RDY1__GPIO_0_21                   0x0153
+MX28_PAD_GPMI_RDY2__GPIO_0_22                   0x0163
+MX28_PAD_GPMI_RDY3__GPIO_0_23                   0x0173
+MX28_PAD_GPMI_RDN__GPIO_0_24                    0x0183
+MX28_PAD_GPMI_WRN__GPIO_0_25                    0x0193
+MX28_PAD_GPMI_ALE__GPIO_0_26                    0x01a3
+MX28_PAD_GPMI_CLE__GPIO_0_27                    0x01b3
+MX28_PAD_GPMI_RESETN__GPIO_0_28                 0x01c3
+MX28_PAD_LCD_D00__GPIO_1_0                      0x1003
+MX28_PAD_LCD_D01__GPIO_1_1                      0x1013
+MX28_PAD_LCD_D02__GPIO_1_2                      0x1023
+MX28_PAD_LCD_D03__GPIO_1_3                      0x1033
+MX28_PAD_LCD_D04__GPIO_1_4                      0x1043
+MX28_PAD_LCD_D05__GPIO_1_5                      0x1053
+MX28_PAD_LCD_D06__GPIO_1_6                      0x1063
+MX28_PAD_LCD_D07__GPIO_1_7                      0x1073
+MX28_PAD_LCD_D08__GPIO_1_8                      0x1083
+MX28_PAD_LCD_D09__GPIO_1_9                      0x1093
+MX28_PAD_LCD_D10__GPIO_1_10                     0x10a3
+MX28_PAD_LCD_D11__GPIO_1_11                     0x10b3
+MX28_PAD_LCD_D12__GPIO_1_12                     0x10c3
+MX28_PAD_LCD_D13__GPIO_1_13                     0x10d3
+MX28_PAD_LCD_D14__GPIO_1_14                     0x10e3
+MX28_PAD_LCD_D15__GPIO_1_15                     0x10f3
+MX28_PAD_LCD_D16__GPIO_1_16                     0x1103
+MX28_PAD_LCD_D17__GPIO_1_17                     0x1113
+MX28_PAD_LCD_D18__GPIO_1_18                     0x1123
+MX28_PAD_LCD_D19__GPIO_1_19                     0x1133
+MX28_PAD_LCD_D20__GPIO_1_20                     0x1143
+MX28_PAD_LCD_D21__GPIO_1_21                     0x1153
+MX28_PAD_LCD_D22__GPIO_1_22                     0x1163
+MX28_PAD_LCD_D23__GPIO_1_23                     0x1173
+MX28_PAD_LCD_RD_E__GPIO_1_24                    0x1183
+MX28_PAD_LCD_WR_RWN__GPIO_1_25                  0x1193
+MX28_PAD_LCD_RS__GPIO_1_26                      0x11a3
+MX28_PAD_LCD_CS__GPIO_1_27                      0x11b3
+MX28_PAD_LCD_VSYNC__GPIO_1_28                   0x11c3
+MX28_PAD_LCD_HSYNC__GPIO_1_29                   0x11d3
+MX28_PAD_LCD_DOTCLK__GPIO_1_30                  0x11e3
+MX28_PAD_LCD_ENABLE__GPIO_1_31                  0x11f3
+MX28_PAD_SSP0_DATA0__GPIO_2_0                   0x2003
+MX28_PAD_SSP0_DATA1__GPIO_2_1                   0x2013
+MX28_PAD_SSP0_DATA2__GPIO_2_2                   0x2023
+MX28_PAD_SSP0_DATA3__GPIO_2_3                   0x2033
+MX28_PAD_SSP0_DATA4__GPIO_2_4                   0x2043
+MX28_PAD_SSP0_DATA5__GPIO_2_5                   0x2053
+MX28_PAD_SSP0_DATA6__GPIO_2_6                   0x2063
+MX28_PAD_SSP0_DATA7__GPIO_2_7                   0x2073
+MX28_PAD_SSP0_CMD__GPIO_2_8                     0x2083
+MX28_PAD_SSP0_DETECT__GPIO_2_9                  0x2093
+MX28_PAD_SSP0_SCK__GPIO_2_10                    0x20a3
+MX28_PAD_SSP1_SCK__GPIO_2_12                    0x20c3
+MX28_PAD_SSP1_CMD__GPIO_2_13                    0x20d3
+MX28_PAD_SSP1_DATA0__GPIO_2_14                  0x20e3
+MX28_PAD_SSP1_DATA3__GPIO_2_15                  0x20f3
+MX28_PAD_SSP2_SCK__GPIO_2_16                    0x2103
+MX28_PAD_SSP2_MOSI__GPIO_2_17                   0x2113
+MX28_PAD_SSP2_MISO__GPIO_2_18                   0x2123
+MX28_PAD_SSP2_SS0__GPIO_2_19                    0x2133
+MX28_PAD_SSP2_SS1__GPIO_2_20                    0x2143
+MX28_PAD_SSP2_SS2__GPIO_2_21                    0x2153
+MX28_PAD_SSP3_SCK__GPIO_2_24                    0x2183
+MX28_PAD_SSP3_MOSI__GPIO_2_25                   0x2193
+MX28_PAD_SSP3_MISO__GPIO_2_26                   0x21a3
+MX28_PAD_SSP3_SS0__GPIO_2_27                    0x21b3
+MX28_PAD_AUART0_RX__GPIO_3_0                    0x3003
+MX28_PAD_AUART0_TX__GPIO_3_1                    0x3013
+MX28_PAD_AUART0_CTS__GPIO_3_2                   0x3023
+MX28_PAD_AUART0_RTS__GPIO_3_3                   0x3033
+MX28_PAD_AUART1_RX__GPIO_3_4                    0x3043
+MX28_PAD_AUART1_TX__GPIO_3_5                    0x3053
+MX28_PAD_AUART1_CTS__GPIO_3_6                   0x3063
+MX28_PAD_AUART1_RTS__GPIO_3_7                   0x3073
+MX28_PAD_AUART2_RX__GPIO_3_8                    0x3083
+MX28_PAD_AUART2_TX__GPIO_3_9                    0x3093
+MX28_PAD_AUART2_CTS__GPIO_3_10                  0x30a3
+MX28_PAD_AUART2_RTS__GPIO_3_11                  0x30b3
+MX28_PAD_AUART3_RX__GPIO_3_12                   0x30c3
+MX28_PAD_AUART3_TX__GPIO_3_13                   0x30d3
+MX28_PAD_AUART3_CTS__GPIO_3_14                  0x30e3
+MX28_PAD_AUART3_RTS__GPIO_3_15                  0x30f3
+MX28_PAD_PWM0__GPIO_3_16                        0x3103
+MX28_PAD_PWM1__GPIO_3_17                        0x3113
+MX28_PAD_PWM2__GPIO_3_18                        0x3123
+MX28_PAD_SAIF0_MCLK__GPIO_3_20                  0x3143
+MX28_PAD_SAIF0_LRCLK__GPIO_3_21                 0x3153
+MX28_PAD_SAIF0_BITCLK__GPIO_3_22                0x3163
+MX28_PAD_SAIF0_SDATA0__GPIO_3_23                0x3173
+MX28_PAD_I2C0_SCL__GPIO_3_24                    0x3183
+MX28_PAD_I2C0_SDA__GPIO_3_25                    0x3193
+MX28_PAD_SAIF1_SDATA0__GPIO_3_26                0x31a3
+MX28_PAD_SPDIF__GPIO_3_27                       0x31b3
+MX28_PAD_PWM3__GPIO_3_28                        0x31c3
+MX28_PAD_PWM4__GPIO_3_29                        0x31d3
+MX28_PAD_LCD_RESET__GPIO_3_30                   0x31e3
+MX28_PAD_ENET0_MDC__GPIO_4_0                    0x4003
+MX28_PAD_ENET0_MDIO__GPIO_4_1                   0x4013
+MX28_PAD_ENET0_RX_EN__GPIO_4_2                  0x4023
+MX28_PAD_ENET0_RXD0__GPIO_4_3                   0x4033
+MX28_PAD_ENET0_RXD1__GPIO_4_4                   0x4043
+MX28_PAD_ENET0_TX_CLK__GPIO_4_5                 0x4053
+MX28_PAD_ENET0_TX_EN__GPIO_4_6                  0x4063
+MX28_PAD_ENET0_TXD0__GPIO_4_7                   0x4073
+MX28_PAD_ENET0_TXD1__GPIO_4_8                   0x4083
+MX28_PAD_ENET0_RXD2__GPIO_4_9                   0x4093
+MX28_PAD_ENET0_RXD3__GPIO_4_10                  0x40a3
+MX28_PAD_ENET0_TXD2__GPIO_4_11                  0x40b3
+MX28_PAD_ENET0_TXD3__GPIO_4_12                  0x40c3
+MX28_PAD_ENET0_RX_CLK__GPIO_4_13                0x40d3
+MX28_PAD_ENET0_COL__GPIO_4_14                   0x40e3
+MX28_PAD_ENET0_CRS__GPIO_4_15                   0x40f3
+MX28_PAD_ENET_CLK__GPIO_4_16                    0x4103
+MX28_PAD_JTAG_RTCK__GPIO_4_20                   0x4143
+
+Valid values for i.MX23 pinmux-id:
+
+pinmux                                          id
+------                                          --
+MX23_PAD_GPMI_D00__GPMI_D00                     0x0000
+MX23_PAD_GPMI_D01__GPMI_D01                     0x0010
+MX23_PAD_GPMI_D02__GPMI_D02                     0x0020
+MX23_PAD_GPMI_D03__GPMI_D03                     0x0030
+MX23_PAD_GPMI_D04__GPMI_D04                     0x0040
+MX23_PAD_GPMI_D05__GPMI_D05                     0x0050
+MX23_PAD_GPMI_D06__GPMI_D06                     0x0060
+MX23_PAD_GPMI_D07__GPMI_D07                     0x0070
+MX23_PAD_GPMI_D08__GPMI_D08                     0x0080
+MX23_PAD_GPMI_D09__GPMI_D09                     0x0090
+MX23_PAD_GPMI_D10__GPMI_D10                     0x00a0
+MX23_PAD_GPMI_D11__GPMI_D11                     0x00b0
+MX23_PAD_GPMI_D12__GPMI_D12                     0x00c0
+MX23_PAD_GPMI_D13__GPMI_D13                     0x00d0
+MX23_PAD_GPMI_D14__GPMI_D14                     0x00e0
+MX23_PAD_GPMI_D15__GPMI_D15                     0x00f0
+MX23_PAD_GPMI_CLE__GPMI_CLE                     0x0100
+MX23_PAD_GPMI_ALE__GPMI_ALE                     0x0110
+MX23_PAD_GPMI_CE2N__GPMI_CE2N                   0x0120
+MX23_PAD_GPMI_RDY0__GPMI_RDY0                   0x0130
+MX23_PAD_GPMI_RDY1__GPMI_RDY1                   0x0140
+MX23_PAD_GPMI_RDY2__GPMI_RDY2                   0x0150
+MX23_PAD_GPMI_RDY3__GPMI_RDY3                   0x0160
+MX23_PAD_GPMI_WPN__GPMI_WPN                     0x0170
+MX23_PAD_GPMI_WRN__GPMI_WRN                     0x0180
+MX23_PAD_GPMI_RDN__GPMI_RDN                     0x0190
+MX23_PAD_AUART1_CTS__AUART1_CTS                 0x01a0
+MX23_PAD_AUART1_RTS__AUART1_RTS                 0x01b0
+MX23_PAD_AUART1_RX__AUART1_RX                   0x01c0
+MX23_PAD_AUART1_TX__AUART1_TX                   0x01d0
+MX23_PAD_I2C_SCL__I2C_SCL                       0x01e0
+MX23_PAD_I2C_SDA__I2C_SDA                       0x01f0
+MX23_PAD_LCD_D00__LCD_D00                       0x1000
+MX23_PAD_LCD_D01__LCD_D01                       0x1010
+MX23_PAD_LCD_D02__LCD_D02                       0x1020
+MX23_PAD_LCD_D03__LCD_D03                       0x1030
+MX23_PAD_LCD_D04__LCD_D04                       0x1040
+MX23_PAD_LCD_D05__LCD_D05                       0x1050
+MX23_PAD_LCD_D06__LCD_D06                       0x1060
+MX23_PAD_LCD_D07__LCD_D07                       0x1070
+MX23_PAD_LCD_D08__LCD_D08                       0x1080
+MX23_PAD_LCD_D09__LCD_D09                       0x1090
+MX23_PAD_LCD_D10__LCD_D10                       0x10a0
+MX23_PAD_LCD_D11__LCD_D11                       0x10b0
+MX23_PAD_LCD_D12__LCD_D12                       0x10c0
+MX23_PAD_LCD_D13__LCD_D13                       0x10d0
+MX23_PAD_LCD_D14__LCD_D14                       0x10e0
+MX23_PAD_LCD_D15__LCD_D15                       0x10f0
+MX23_PAD_LCD_D16__LCD_D16                       0x1100
+MX23_PAD_LCD_D17__LCD_D17                       0x1110
+MX23_PAD_LCD_RESET__LCD_RESET                   0x1120
+MX23_PAD_LCD_RS__LCD_RS                         0x1130
+MX23_PAD_LCD_WR__LCD_WR                         0x1140
+MX23_PAD_LCD_CS__LCD_CS                         0x1150
+MX23_PAD_LCD_DOTCK__LCD_DOTCK                   0x1160
+MX23_PAD_LCD_ENABLE__LCD_ENABLE                 0x1170
+MX23_PAD_LCD_HSYNC__LCD_HSYNC                   0x1180
+MX23_PAD_LCD_VSYNC__LCD_VSYNC                   0x1190
+MX23_PAD_PWM0__PWM0                             0x11a0
+MX23_PAD_PWM1__PWM1                             0x11b0
+MX23_PAD_PWM2__PWM2                             0x11c0
+MX23_PAD_PWM3__PWM3                             0x11d0
+MX23_PAD_PWM4__PWM4                             0x11e0
+MX23_PAD_SSP1_CMD__SSP1_CMD                     0x2000
+MX23_PAD_SSP1_DETECT__SSP1_DETECT               0x2010
+MX23_PAD_SSP1_DATA0__SSP1_DATA0                 0x2020
+MX23_PAD_SSP1_DATA1__SSP1_DATA1                 0x2030
+MX23_PAD_SSP1_DATA2__SSP1_DATA2                 0x2040
+MX23_PAD_SSP1_DATA3__SSP1_DATA3                 0x2050
+MX23_PAD_SSP1_SCK__SSP1_SCK                     0x2060
+MX23_PAD_ROTARYA__ROTARYA                       0x2070
+MX23_PAD_ROTARYB__ROTARYB                       0x2080
+MX23_PAD_EMI_A00__EMI_A00                       0x2090
+MX23_PAD_EMI_A01__EMI_A01                       0x20a0
+MX23_PAD_EMI_A02__EMI_A02                       0x20b0
+MX23_PAD_EMI_A03__EMI_A03                       0x20c0
+MX23_PAD_EMI_A04__EMI_A04                       0x20d0
+MX23_PAD_EMI_A05__EMI_A05                       0x20e0
+MX23_PAD_EMI_A06__EMI_A06                       0x20f0
+MX23_PAD_EMI_A07__EMI_A07                       0x2100
+MX23_PAD_EMI_A08__EMI_A08                       0x2110
+MX23_PAD_EMI_A09__EMI_A09                       0x2120
+MX23_PAD_EMI_A10__EMI_A10                       0x2130
+MX23_PAD_EMI_A11__EMI_A11                       0x2140
+MX23_PAD_EMI_A12__EMI_A12                       0x2150
+MX23_PAD_EMI_BA0__EMI_BA0                       0x2160
+MX23_PAD_EMI_BA1__EMI_BA1                       0x2170
+MX23_PAD_EMI_CASN__EMI_CASN                     0x2180
+MX23_PAD_EMI_CE0N__EMI_CE0N                     0x2190
+MX23_PAD_EMI_CE1N__EMI_CE1N                     0x21a0
+MX23_PAD_GPMI_CE1N__GPMI_CE1N                   0x21b0
+MX23_PAD_GPMI_CE0N__GPMI_CE0N                   0x21c0
+MX23_PAD_EMI_CKE__EMI_CKE                       0x21d0
+MX23_PAD_EMI_RASN__EMI_RASN                     0x21e0
+MX23_PAD_EMI_WEN__EMI_WEN                       0x21f0
+MX23_PAD_EMI_D00__EMI_D00                       0x3000
+MX23_PAD_EMI_D01__EMI_D01                       0x3010
+MX23_PAD_EMI_D02__EMI_D02                       0x3020
+MX23_PAD_EMI_D03__EMI_D03                       0x3030
+MX23_PAD_EMI_D04__EMI_D04                       0x3040
+MX23_PAD_EMI_D05__EMI_D05                       0x3050
+MX23_PAD_EMI_D06__EMI_D06                       0x3060
+MX23_PAD_EMI_D07__EMI_D07                       0x3070
+MX23_PAD_EMI_D08__EMI_D08                       0x3080
+MX23_PAD_EMI_D09__EMI_D09                       0x3090
+MX23_PAD_EMI_D10__EMI_D10                       0x30a0
+MX23_PAD_EMI_D11__EMI_D11                       0x30b0
+MX23_PAD_EMI_D12__EMI_D12                       0x30c0
+MX23_PAD_EMI_D13__EMI_D13                       0x30d0
+MX23_PAD_EMI_D14__EMI_D14                       0x30e0
+MX23_PAD_EMI_D15__EMI_D15                       0x30f0
+MX23_PAD_EMI_DQM0__EMI_DQM0                     0x3100
+MX23_PAD_EMI_DQM1__EMI_DQM1                     0x3110
+MX23_PAD_EMI_DQS0__EMI_DQS0                     0x3120
+MX23_PAD_EMI_DQS1__EMI_DQS1                     0x3130
+MX23_PAD_EMI_CLK__EMI_CLK                       0x3140
+MX23_PAD_EMI_CLKN__EMI_CLKN                     0x3150
+MX23_PAD_GPMI_D00__LCD_D8                       0x0001
+MX23_PAD_GPMI_D01__LCD_D9                       0x0011
+MX23_PAD_GPMI_D02__LCD_D10                      0x0021
+MX23_PAD_GPMI_D03__LCD_D11                      0x0031
+MX23_PAD_GPMI_D04__LCD_D12                      0x0041
+MX23_PAD_GPMI_D05__LCD_D13                      0x0051
+MX23_PAD_GPMI_D06__LCD_D14                      0x0061
+MX23_PAD_GPMI_D07__LCD_D15                      0x0071
+MX23_PAD_GPMI_D08__LCD_D18                      0x0081
+MX23_PAD_GPMI_D09__LCD_D19                      0x0091
+MX23_PAD_GPMI_D10__LCD_D20                      0x00a1
+MX23_PAD_GPMI_D11__LCD_D21                      0x00b1
+MX23_PAD_GPMI_D12__LCD_D22                      0x00c1
+MX23_PAD_GPMI_D13__LCD_D23                      0x00d1
+MX23_PAD_GPMI_D14__AUART2_RX                    0x00e1
+MX23_PAD_GPMI_D15__AUART2_TX                    0x00f1
+MX23_PAD_GPMI_CLE__LCD_D16                      0x0101
+MX23_PAD_GPMI_ALE__LCD_D17                      0x0111
+MX23_PAD_GPMI_CE2N__ATA_A2                      0x0121
+MX23_PAD_AUART1_RTS__IR_CLK                     0x01b1
+MX23_PAD_AUART1_RX__IR_RX                       0x01c1
+MX23_PAD_AUART1_TX__IR_TX                       0x01d1
+MX23_PAD_I2C_SCL__GPMI_RDY2                     0x01e1
+MX23_PAD_I2C_SDA__GPMI_CE2N                     0x01f1
+MX23_PAD_LCD_D00__ETM_DA8                       0x1001
+MX23_PAD_LCD_D01__ETM_DA9                       0x1011
+MX23_PAD_LCD_D02__ETM_DA10                      0x1021
+MX23_PAD_LCD_D03__ETM_DA11                      0x1031
+MX23_PAD_LCD_D04__ETM_DA12                      0x1041
+MX23_PAD_LCD_D05__ETM_DA13                      0x1051
+MX23_PAD_LCD_D06__ETM_DA14                      0x1061
+MX23_PAD_LCD_D07__ETM_DA15                      0x1071
+MX23_PAD_LCD_D08__ETM_DA0                       0x1081
+MX23_PAD_LCD_D09__ETM_DA1                       0x1091
+MX23_PAD_LCD_D10__ETM_DA2                       0x10a1
+MX23_PAD_LCD_D11__ETM_DA3                       0x10b1
+MX23_PAD_LCD_D12__ETM_DA4                       0x10c1
+MX23_PAD_LCD_D13__ETM_DA5                       0x10d1
+MX23_PAD_LCD_D14__ETM_DA6                       0x10e1
+MX23_PAD_LCD_D15__ETM_DA7                       0x10f1
+MX23_PAD_LCD_RESET__ETM_TCTL                    0x1121
+MX23_PAD_LCD_RS__ETM_TCLK                       0x1131
+MX23_PAD_LCD_DOTCK__GPMI_RDY3                   0x1161
+MX23_PAD_LCD_ENABLE__I2C_SCL                    0x1171
+MX23_PAD_LCD_HSYNC__I2C_SDA                     0x1181
+MX23_PAD_LCD_VSYNC__LCD_BUSY                    0x1191
+MX23_PAD_PWM0__ROTARYA                          0x11a1
+MX23_PAD_PWM1__ROTARYB                          0x11b1
+MX23_PAD_PWM2__GPMI_RDY3                        0x11c1
+MX23_PAD_PWM3__ETM_TCTL                         0x11d1
+MX23_PAD_PWM4__ETM_TCLK                         0x11e1
+MX23_PAD_SSP1_DETECT__GPMI_CE3N                 0x2011
+MX23_PAD_SSP1_DATA1__I2C_SCL                    0x2031
+MX23_PAD_SSP1_DATA2__I2C_SDA                    0x2041
+MX23_PAD_ROTARYA__AUART2_RTS                    0x2071
+MX23_PAD_ROTARYB__AUART2_CTS                    0x2081
+MX23_PAD_GPMI_D00__SSP2_DATA0                   0x0002
+MX23_PAD_GPMI_D01__SSP2_DATA1                   0x0012
+MX23_PAD_GPMI_D02__SSP2_DATA2                   0x0022
+MX23_PAD_GPMI_D03__SSP2_DATA3                   0x0032
+MX23_PAD_GPMI_D04__SSP2_DATA4                   0x0042
+MX23_PAD_GPMI_D05__SSP2_DATA5                   0x0052
+MX23_PAD_GPMI_D06__SSP2_DATA6                   0x0062
+MX23_PAD_GPMI_D07__SSP2_DATA7                   0x0072
+MX23_PAD_GPMI_D08__SSP1_DATA4                   0x0082
+MX23_PAD_GPMI_D09__SSP1_DATA5                   0x0092
+MX23_PAD_GPMI_D10__SSP1_DATA6                   0x00a2
+MX23_PAD_GPMI_D11__SSP1_DATA7                   0x00b2
+MX23_PAD_GPMI_D15__GPMI_CE3N                    0x00f2
+MX23_PAD_GPMI_RDY0__SSP2_DETECT                 0x0132
+MX23_PAD_GPMI_RDY1__SSP2_CMD                    0x0142
+MX23_PAD_GPMI_WRN__SSP2_SCK                     0x0182
+MX23_PAD_AUART1_CTS__SSP1_DATA4                 0x01a2
+MX23_PAD_AUART1_RTS__SSP1_DATA5                 0x01b2
+MX23_PAD_AUART1_RX__SSP1_DATA6                  0x01c2
+MX23_PAD_AUART1_TX__SSP1_DATA7                  0x01d2
+MX23_PAD_I2C_SCL__AUART1_TX                     0x01e2
+MX23_PAD_I2C_SDA__AUART1_RX                     0x01f2
+MX23_PAD_LCD_D08__SAIF2_SDATA0                  0x1082
+MX23_PAD_LCD_D09__SAIF1_SDATA0                  0x1092
+MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK              0x10a2
+MX23_PAD_LCD_D11__SAIF_LRCLK                    0x10b2
+MX23_PAD_LCD_D12__SAIF2_SDATA1                  0x10c2
+MX23_PAD_LCD_D13__SAIF2_SDATA2                  0x10d2
+MX23_PAD_LCD_D14__SAIF1_SDATA2                  0x10e2
+MX23_PAD_LCD_D15__SAIF1_SDATA1                  0x10f2
+MX23_PAD_LCD_D16__SAIF_ALT_BITCLK               0x1102
+MX23_PAD_LCD_RESET__GPMI_CE3N                   0x1122
+MX23_PAD_PWM0__DUART_RX                         0x11a2
+MX23_PAD_PWM1__DUART_TX                         0x11b2
+MX23_PAD_PWM3__AUART1_CTS                       0x11d2
+MX23_PAD_PWM4__AUART1_RTS                       0x11e2
+MX23_PAD_SSP1_CMD__JTAG_TDO                     0x2002
+MX23_PAD_SSP1_DETECT__USB_OTG_ID                0x2012
+MX23_PAD_SSP1_DATA0__JTAG_TDI                   0x2022
+MX23_PAD_SSP1_DATA1__JTAG_TCLK                  0x2032
+MX23_PAD_SSP1_DATA2__JTAG_RTCK                  0x2042
+MX23_PAD_SSP1_DATA3__JTAG_TMS                   0x2052
+MX23_PAD_SSP1_SCK__JTAG_TRST                    0x2062
+MX23_PAD_ROTARYA__SPDIF                         0x2072
+MX23_PAD_ROTARYB__GPMI_CE3N                     0x2082
+MX23_PAD_GPMI_D00__GPIO_0_0                     0x0003
+MX23_PAD_GPMI_D01__GPIO_0_1                     0x0013
+MX23_PAD_GPMI_D02__GPIO_0_2                     0x0023
+MX23_PAD_GPMI_D03__GPIO_0_3                     0x0033
+MX23_PAD_GPMI_D04__GPIO_0_4                     0x0043
+MX23_PAD_GPMI_D05__GPIO_0_5                     0x0053
+MX23_PAD_GPMI_D06__GPIO_0_6                     0x0063
+MX23_PAD_GPMI_D07__GPIO_0_7                     0x0073
+MX23_PAD_GPMI_D08__GPIO_0_8                     0x0083
+MX23_PAD_GPMI_D09__GPIO_0_9                     0x0093
+MX23_PAD_GPMI_D10__GPIO_0_10                    0x00a3
+MX23_PAD_GPMI_D11__GPIO_0_11                    0x00b3
+MX23_PAD_GPMI_D12__GPIO_0_12                    0x00c3
+MX23_PAD_GPMI_D13__GPIO_0_13                    0x00d3
+MX23_PAD_GPMI_D14__GPIO_0_14                    0x00e3
+MX23_PAD_GPMI_D15__GPIO_0_15                    0x00f3
+MX23_PAD_GPMI_CLE__GPIO_0_16                    0x0103
+MX23_PAD_GPMI_ALE__GPIO_0_17                    0x0113
+MX23_PAD_GPMI_CE2N__GPIO_0_18                   0x0123
+MX23_PAD_GPMI_RDY0__GPIO_0_19                   0x0133
+MX23_PAD_GPMI_RDY1__GPIO_0_20                   0x0143
+MX23_PAD_GPMI_RDY2__GPIO_0_21                   0x0153
+MX23_PAD_GPMI_RDY3__GPIO_0_22                   0x0163
+MX23_PAD_GPMI_WPN__GPIO_0_23                    0x0173
+MX23_PAD_GPMI_WRN__GPIO_0_24                    0x0183
+MX23_PAD_GPMI_RDN__GPIO_0_25                    0x0193
+MX23_PAD_AUART1_CTS__GPIO_0_26                  0x01a3
+MX23_PAD_AUART1_RTS__GPIO_0_27                  0x01b3
+MX23_PAD_AUART1_RX__GPIO_0_28                   0x01c3
+MX23_PAD_AUART1_TX__GPIO_0_29                   0x01d3
+MX23_PAD_I2C_SCL__GPIO_0_30                     0x01e3
+MX23_PAD_I2C_SDA__GPIO_0_31                     0x01f3
+MX23_PAD_LCD_D00__GPIO_1_0                      0x1003
+MX23_PAD_LCD_D01__GPIO_1_1                      0x1013
+MX23_PAD_LCD_D02__GPIO_1_2                      0x1023
+MX23_PAD_LCD_D03__GPIO_1_3                      0x1033
+MX23_PAD_LCD_D04__GPIO_1_4                      0x1043
+MX23_PAD_LCD_D05__GPIO_1_5                      0x1053
+MX23_PAD_LCD_D06__GPIO_1_6                      0x1063
+MX23_PAD_LCD_D07__GPIO_1_7                      0x1073
+MX23_PAD_LCD_D08__GPIO_1_8                      0x1083
+MX23_PAD_LCD_D09__GPIO_1_9                      0x1093
+MX23_PAD_LCD_D10__GPIO_1_10                     0x10a3
+MX23_PAD_LCD_D11__GPIO_1_11                     0x10b3
+MX23_PAD_LCD_D12__GPIO_1_12                     0x10c3
+MX23_PAD_LCD_D13__GPIO_1_13                     0x10d3
+MX23_PAD_LCD_D14__GPIO_1_14                     0x10e3
+MX23_PAD_LCD_D15__GPIO_1_15                     0x10f3
+MX23_PAD_LCD_D16__GPIO_1_16                     0x1103
+MX23_PAD_LCD_D17__GPIO_1_17                     0x1113
+MX23_PAD_LCD_RESET__GPIO_1_18                   0x1123
+MX23_PAD_LCD_RS__GPIO_1_19                      0x1133
+MX23_PAD_LCD_WR__GPIO_1_20                      0x1143
+MX23_PAD_LCD_CS__GPIO_1_21                      0x1153
+MX23_PAD_LCD_DOTCK__GPIO_1_22                   0x1163
+MX23_PAD_LCD_ENABLE__GPIO_1_23                  0x1173
+MX23_PAD_LCD_HSYNC__GPIO_1_24                   0x1183
+MX23_PAD_LCD_VSYNC__GPIO_1_25                   0x1193
+MX23_PAD_PWM0__GPIO_1_26                        0x11a3
+MX23_PAD_PWM1__GPIO_1_27                        0x11b3
+MX23_PAD_PWM2__GPIO_1_28                        0x11c3
+MX23_PAD_PWM3__GPIO_1_29                        0x11d3
+MX23_PAD_PWM4__GPIO_1_30                        0x11e3
+MX23_PAD_SSP1_CMD__GPIO_2_0                     0x2003
+MX23_PAD_SSP1_DETECT__GPIO_2_1                  0x2013
+MX23_PAD_SSP1_DATA0__GPIO_2_2                   0x2023
+MX23_PAD_SSP1_DATA1__GPIO_2_3                   0x2033
+MX23_PAD_SSP1_DATA2__GPIO_2_4                   0x2043
+MX23_PAD_SSP1_DATA3__GPIO_2_5                   0x2053
+MX23_PAD_SSP1_SCK__GPIO_2_6                     0x2063
+MX23_PAD_ROTARYA__GPIO_2_7                      0x2073
+MX23_PAD_ROTARYB__GPIO_2_8                      0x2083
+MX23_PAD_EMI_A00__GPIO_2_9                      0x2093
+MX23_PAD_EMI_A01__GPIO_2_10                     0x20a3
+MX23_PAD_EMI_A02__GPIO_2_11                     0x20b3
+MX23_PAD_EMI_A03__GPIO_2_12                     0x20c3
+MX23_PAD_EMI_A04__GPIO_2_13                     0x20d3
+MX23_PAD_EMI_A05__GPIO_2_14                     0x20e3
+MX23_PAD_EMI_A06__GPIO_2_15                     0x20f3
+MX23_PAD_EMI_A07__GPIO_2_16                     0x2103
+MX23_PAD_EMI_A08__GPIO_2_17                     0x2113
+MX23_PAD_EMI_A09__GPIO_2_18                     0x2123
+MX23_PAD_EMI_A10__GPIO_2_19                     0x2133
+MX23_PAD_EMI_A11__GPIO_2_20                     0x2143
+MX23_PAD_EMI_A12__GPIO_2_21                     0x2153
+MX23_PAD_EMI_BA0__GPIO_2_22                     0x2163
+MX23_PAD_EMI_BA1__GPIO_2_23                     0x2173
+MX23_PAD_EMI_CASN__GPIO_2_24                    0x2183
+MX23_PAD_EMI_CE0N__GPIO_2_25                    0x2193
+MX23_PAD_EMI_CE1N__GPIO_2_26                    0x21a3
+MX23_PAD_GPMI_CE1N__GPIO_2_27                   0x21b3
+MX23_PAD_GPMI_CE0N__GPIO_2_28                   0x21c3
+MX23_PAD_EMI_CKE__GPIO_2_29                     0x21d3
+MX23_PAD_EMI_RASN__GPIO_2_30                    0x21e3
+MX23_PAD_EMI_WEN__GPIO_2_31                     0x21f3
diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt
new file mode 100644
index 000000000000..c8e578263ce2
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt
@@ -0,0 +1,132 @@
+NVIDIA Tegra20 pinmux controller
+
+Required properties:
+- compatible: "nvidia,tegra20-pinmux"
+- reg: Should contain the register physical address and length for each of
+  the tri-state, mux, pull-up/down, and pad control register sets.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+Tegra's pin configuration nodes act as a container for an abitrary number of
+subnodes. Each of these subnodes represents some desired configuration for a
+pin, a group, or a list of pins or groups. This configuration can include the
+mux function to select on those pin(s)/group(s), and various pin configuration
+parameters, such as pull-up, tristate, drive strength, etc.
+
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content.
+
+Each subnode only affects those parameters that are explicitly listed. In
+other words, a subnode that lists a mux function but no pin configuration
+parameters implies no information about any pin configuration parameters.
+Similarly, a pin subnode that describes a pullup parameter implies no
+information about e.g. the mux function or tristate parameter. For this
+reason, even seemingly boolean values are actually tristates in this binding:
+unspecified, off, or on. Unspecified is represented as an absent property,
+and off/on are represented as integer values 0 and 1.
+
+Required subnode-properties:
+- nvidia,pins : An array of strings. Each string contains the name of a pin or
+    group. Valid values for these names are listed below.
+
+Optional subnode-properties:
+- nvidia,function: A string containing the name of the function to mux to the
+  pin or group. Valid values for function names are listed below. See the Tegra
+  TRM to determine which are valid for each pin or group.
+- nvidia,pull: Integer, representing the pull-down/up to apply to the pin.
+    0: none, 1: down, 2: up.
+- nvidia,tristate: Integer.
+    0: drive, 1: tristate.
+- nvidia,high-speed-mode: Integer. Enable high speed mode the pins.
+    0: no, 1: yes.
+- nvidia,schmitt: Integer. Enables Schmitt Trigger on the input.
+    0: no, 1: yes.
+- nvidia,low-power-mode: Integer. Valid values 0-3. 0 is least power, 3 is
+    most power. Controls the drive power or current. See "Low Power Mode"
+    or "LPMD1" and "LPMD0" in the Tegra TRM.
+- nvidia,pull-down-strength: Integer. Controls drive strength. 0 is weakest.
+    The range of valid values depends on the pingroup. See "CAL_DRVDN" in the
+    Tegra TRM.
+- nvidia,pull-up-strength: Integer. Controls drive strength. 0 is weakest.
+    The range of valid values depends on the pingroup. See "CAL_DRVUP" in the
+    Tegra TRM.
+- nvidia,slew-rate-rising: Integer. Controls rising signal slew rate. 0 is
+    fastest. The range of valid values depends on the pingroup. See
+    "DRVDN_SLWR" in the Tegra TRM.
+- nvidia,slew-rate-falling: Integer. Controls falling signal slew rate. 0 is
+    fastest. The range of valid values depends on the pingroup. See
+    "DRVUP_SLWF" in the Tegra TRM.
+
+Note that many of these properties are only valid for certain specific pins
+or groups. See the Tegra TRM and various pinmux spreadsheets for complete
+details regarding which groups support which functionality. The Linux pinctrl
+driver may also be a useful reference, since it consolidates, disambiguates,
+and corrects data from all those sources.
+
+Valid values for pin and group names are:
+
+  mux groups:
+
+    These all support nvidia,function, nvidia,tristate, and many support
+    nvidia,pull.
+
+    ata, atb, atc, atd, ate, cdev1, cdev2, crtp, csus, dap1, dap2, dap3, dap4,
+    ddc, dta, dtb, dtc, dtd, dte, dtf, gma, gmb, gmc, gmd, gme, gpu, gpu7,
+    gpv, hdint, i2cp, irrx, irtx, kbca, kbcb, kbcc, kbcd, kbce, kbcf, lcsn,
+    ld0, ld1, ld2, ld3, ld4, ld5, ld6, ld7, ld8, ld9, ld10, ld11, ld12, ld13,
+    ld14, ld15, ld16, ld17, ldc, ldi, lhp0, lhp1, lhp2, lhs, lm0, lm1, lpp,
+    lpw0, lpw1, lpw2, lsc0, lsc1, lsck, lsda, lsdi, lspi, lvp0, lvp1, lvs,
+    owc, pmc, pta, rm, sdb, sdc, sdd, sdio1, slxa, slxc, slxd, slxk, spdi,
+    spdo, spia, spib, spic, spid, spie, spif, spig, spih, uaa, uab, uac, uad,
+    uca, ucb, uda.
+
+  tristate groups:
+
+    These only support nvidia,pull.
+
+    ck32, ddrc, pmca, pmcb, pmcc, pmcd, pmce, xm2c, xm2d, ls, lc, ld17_0,
+    ld19_18, ld21_20, ld23_22.
+
+  drive groups:
+
+    With some exceptions, these support nvidia,high-speed-mode,
+    nvidia,schmitt, nvidia,low-power-mode, nvidia,pull-down-strength,
+    nvidia,pull-up-strength, nvidia,slew_rate-rising, nvidia,slew_rate-falling.
+
+    drive_ao1, drive_ao2, drive_at1, drive_at2, drive_cdev1, drive_cdev2,
+    drive_csus, drive_dap1, drive_dap2, drive_dap3, drive_dap4, drive_dbg,
+    drive_lcd1, drive_lcd2, drive_sdmmc2, drive_sdmmc3, drive_spi, drive_uaa,
+    drive_uab, drive_uart2, drive_uart3, drive_vi1, drive_vi2, drive_xm2a,
+    drive_xm2c, drive_xm2d, drive_xm2clk, drive_sdio1, drive_crt, drive_ddc,
+    drive_gma, drive_gmb, drive_gmc, drive_gmd, drive_gme, drive_owr,
+    drive_uda.
+
+Example:
+
+        pinctrl@70000000 {
+                compatible = "nvidia,tegra20-pinmux";
+                reg = < 0x70000014 0x10    /* Tri-state registers */
+                        0x70000080 0x20    /* Mux registers */
+                        0x700000a0 0x14    /* Pull-up/down registers */
+                        0x70000868 0xa8 >; /* Pad control registers */
+        };
+
+Example board file extract:
+
+        pinctrl@70000000 {
+                sdio4_default: sdio4_default {
+                        atb {
+                                nvidia,pins = "atb", "gma", "gme";
+                                nvidia,function = "sdio4";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
+                };
+        };
+
+        sdhci@c8000600 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&sdio4_default>;
+        };
diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt
new file mode 100644
index 000000000000..c275b70349c1
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt
@@ -0,0 +1,132 @@
+NVIDIA Tegra30 pinmux controller
+
+The Tegra30 pinctrl binding is very similar to the Tegra20 pinctrl binding,
+as described in nvidia,tegra20-pinmux.txt. In fact, this document assumes
+that binding as a baseline, and only documents the differences between the
+two bindings.
+
+Required properties:
+- compatible: "nvidia,tegra30-pinmux"
+- reg: Should contain the register physical address and length for each of
+  the pad control and mux registers.
+
+Tegra30 adds the following optional properties for pin configuration subnodes:
+- nvidia,enable-input: Integer. Enable the pin's input path. 0: no, 1: yes.
+- nvidia,open-drain: Integer. Enable open drain mode. 0: no, 1: yes.
+- nvidia,lock: Integer. Lock the pin configuration against further changes
+    until reset. 0: no, 1: yes.
+- nvidia,io-reset: Integer. Reset the IO path. 0: no, 1: yes.
+
+As with Tegra20, see the Tegra TRM for complete details regarding which groups
+support which functionality.
+
+Valid values for pin and group names are:
+
+  per-pin mux groups:
+
+    These all support nvidia,function, nvidia,tristate, nvidia,pull,
+    nvidia,enable-input, nvidia,lock. Some support nvidia,open-drain,
+    nvidia,io-reset.
+
+    clk_32k_out_pa0, uart3_cts_n_pa1, dap2_fs_pa2, dap2_sclk_pa3,
+    dap2_din_pa4, dap2_dout_pa5, sdmmc3_clk_pa6, sdmmc3_cmd_pa7, gmi_a17_pb0,
+    gmi_a18_pb1, lcd_pwr0_pb2, lcd_pclk_pb3, sdmmc3_dat3_pb4, sdmmc3_dat2_pb5,
+    sdmmc3_dat1_pb6, sdmmc3_dat0_pb7, uart3_rts_n_pc0, lcd_pwr1_pc1,
+    uart2_txd_pc2, uart2_rxd_pc3, gen1_i2c_scl_pc4, gen1_i2c_sda_pc5,
+    lcd_pwr2_pc6, gmi_wp_n_pc7, sdmmc3_dat5_pd0, sdmmc3_dat4_pd1, lcd_dc1_pd2,
+    sdmmc3_dat6_pd3, sdmmc3_dat7_pd4, vi_d1_pd5, vi_vsync_pd6, vi_hsync_pd7,
+    lcd_d0_pe0, lcd_d1_pe1, lcd_d2_pe2, lcd_d3_pe3, lcd_d4_pe4, lcd_d5_pe5,
+    lcd_d6_pe6, lcd_d7_pe7, lcd_d8_pf0, lcd_d9_pf1, lcd_d10_pf2, lcd_d11_pf3,
+    lcd_d12_pf4, lcd_d13_pf5, lcd_d14_pf6, lcd_d15_pf7, gmi_ad0_pg0,
+    gmi_ad1_pg1, gmi_ad2_pg2, gmi_ad3_pg3, gmi_ad4_pg4, gmi_ad5_pg5,
+    gmi_ad6_pg6, gmi_ad7_pg7, gmi_ad8_ph0, gmi_ad9_ph1, gmi_ad10_ph2,
+    gmi_ad11_ph3, gmi_ad12_ph4, gmi_ad13_ph5, gmi_ad14_ph6, gmi_ad15_ph7,
+    gmi_wr_n_pi0, gmi_oe_n_pi1, gmi_dqs_pi2, gmi_cs6_n_pi3, gmi_rst_n_pi4,
+    gmi_iordy_pi5, gmi_cs7_n_pi6, gmi_wait_pi7, gmi_cs0_n_pj0, lcd_de_pj1,
+    gmi_cs1_n_pj2, lcd_hsync_pj3, lcd_vsync_pj4, uart2_cts_n_pj5,
+    uart2_rts_n_pj6, gmi_a16_pj7, gmi_adv_n_pk0, gmi_clk_pk1, gmi_cs4_n_pk2,
+    gmi_cs2_n_pk3, gmi_cs3_n_pk4, spdif_out_pk5, spdif_in_pk6, gmi_a19_pk7,
+    vi_d2_pl0, vi_d3_pl1, vi_d4_pl2, vi_d5_pl3, vi_d6_pl4, vi_d7_pl5,
+    vi_d8_pl6, vi_d9_pl7, lcd_d16_pm0, lcd_d17_pm1, lcd_d18_pm2, lcd_d19_pm3,
+    lcd_d20_pm4, lcd_d21_pm5, lcd_d22_pm6, lcd_d23_pm7, dap1_fs_pn0,
+    dap1_din_pn1, dap1_dout_pn2, dap1_sclk_pn3, lcd_cs0_n_pn4, lcd_sdout_pn5,
+    lcd_dc0_pn6, hdmi_int_pn7, ulpi_data7_po0, ulpi_data0_po1, ulpi_data1_po2,
+    ulpi_data2_po3, ulpi_data3_po4, ulpi_data4_po5, ulpi_data5_po6,
+    ulpi_data6_po7, dap3_fs_pp0, dap3_din_pp1, dap3_dout_pp2, dap3_sclk_pp3,
+    dap4_fs_pp4, dap4_din_pp5, dap4_dout_pp6, dap4_sclk_pp7, kb_col0_pq0,
+    kb_col1_pq1, kb_col2_pq2, kb_col3_pq3, kb_col4_pq4, kb_col5_pq5,
+    kb_col6_pq6, kb_col7_pq7, kb_row0_pr0, kb_row1_pr1, kb_row2_pr2,
+    kb_row3_pr3, kb_row4_pr4, kb_row5_pr5, kb_row6_pr6, kb_row7_pr7,
+    kb_row8_ps0, kb_row9_ps1, kb_row10_ps2, kb_row11_ps3, kb_row12_ps4,
+    kb_row13_ps5, kb_row14_ps6, kb_row15_ps7, vi_pclk_pt0, vi_mclk_pt1,
+    vi_d10_pt2, vi_d11_pt3, vi_d0_pt4, gen2_i2c_scl_pt5, gen2_i2c_sda_pt6,
+    sdmmc4_cmd_pt7, pu0, pu1, pu2, pu3, pu4, pu5, pu6, jtag_rtck_pu7, pv0,
+    pv1, pv2, pv3, ddc_scl_pv4, ddc_sda_pv5, crt_hsync_pv6, crt_vsync_pv7,
+    lcd_cs1_n_pw0, lcd_m1_pw1, spi2_cs1_n_pw2, spi2_cs2_n_pw3, clk1_out_pw4,
+    clk2_out_pw5, uart3_txd_pw6, uart3_rxd_pw7, spi2_mosi_px0, spi2_miso_px1,
+    spi2_sck_px2, spi2_cs0_n_px3, spi1_mosi_px4, spi1_sck_px5, spi1_cs0_n_px6,
+    spi1_miso_px7, ulpi_clk_py0, ulpi_dir_py1, ulpi_nxt_py2, ulpi_stp_py3,
+    sdmmc1_dat3_py4, sdmmc1_dat2_py5, sdmmc1_dat1_py6, sdmmc1_dat0_py7,
+    sdmmc1_clk_pz0, sdmmc1_cmd_pz1, lcd_sdin_pz2, lcd_wr_n_pz3, lcd_sck_pz4,
+    sys_clk_req_pz5, pwr_i2c_scl_pz6, pwr_i2c_sda_pz7, sdmmc4_dat0_paa0,
+    sdmmc4_dat1_paa1, sdmmc4_dat2_paa2, sdmmc4_dat3_paa3, sdmmc4_dat4_paa4,
+    sdmmc4_dat5_paa5, sdmmc4_dat6_paa6, sdmmc4_dat7_paa7, pbb0,
+    cam_i2c_scl_pbb1, cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6, pbb7,
+    cam_mclk_pcc0, pcc1, pcc2, sdmmc4_rst_n_pcc3, sdmmc4_clk_pcc4,
+    clk2_req_pcc5, pex_l2_rst_n_pcc6, pex_l2_clkreq_n_pcc7,
+    pex_l0_prsnt_n_pdd0, pex_l0_rst_n_pdd1, pex_l0_clkreq_n_pdd2,
+    pex_wake_n_pdd3, pex_l1_prsnt_n_pdd4, pex_l1_rst_n_pdd5,
+    pex_l1_clkreq_n_pdd6, pex_l2_prsnt_n_pdd7, clk3_out_pee0, clk3_req_pee1,
+    clk1_req_pee2, hdmi_cec_pee3, clk_32k_in, core_pwr_req, cpu_pwr_req, owr,
+    pwr_int_n.
+
+  drive groups:
+
+    These all support nvidia,pull-down-strength, nvidia,pull-up-strength,
+    nvidia,slew_rate-rising, nvidia,slew_rate-falling. Most but not all
+    support nvidia,high-speed-mode, nvidia,schmitt, nvidia,low-power-mode.
+
+    ao1, ao2, at1, at2, at3, at4, at5, cdev1, cdev2, cec, crt, csus, dap1,
+    dap2, dap3, dap4, dbg, ddc, dev3, gma, gmb, gmc, gmd, gme, gmf, gmg,
+    gmh, gpv, lcd1, lcd2, owr, sdio1, sdio2, sdio3, spi, uaa, uab, uart2,
+    uart3, uda, vi1.
+
+Example:
+
+        pinctrl@70000000 {
+                compatible = "nvidia,tegra30-pinmux";
+                reg = < 0x70000868 0xd0     /* Pad control registers */
+                        0x70003000 0x3e0 >; /* Mux registers */
+        };
+
+Example board file extract:
+
+        pinctrl@70000000 {
+                sdmmc4_default: pinmux {
+                        sdmmc4_clk_pcc4 {
+                                nvidia,pins =   "sdmmc4_clk_pcc4",
+                                                "sdmmc4_rst_n_pcc3";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
+                        sdmmc4_dat0_paa0 {
+                                nvidia,pins =   "sdmmc4_dat0_paa0",
+                                                "sdmmc4_dat1_paa1",
+                                                "sdmmc4_dat2_paa2",
+                                                "sdmmc4_dat3_paa3",
+                                                "sdmmc4_dat4_paa4",
+                                                "sdmmc4_dat5_paa5",
+                                                "sdmmc4_dat6_paa6",
+                                                "sdmmc4_dat7_paa7";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <2>;
+                                nvidia,tristate = <0>;
+                        };
+                };
+        };
+
+        sdhci@78000400 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&sdmmc4_default>;
+        };
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
new file mode 100644
index 000000000000..c95ea8278f87
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
@@ -0,0 +1,128 @@
+== Introduction ==
+
+Hardware modules that control pin multiplexing or configuration parameters
+such as pull-up/down, tri-state, drive-strength etc are designated as pin
+controllers. Each pin controller must be represented as a node in device tree,
+just like any other hardware module.
+
+Hardware modules whose signals are affected by pin configuration are
+designated client devices. Again, each client device must be represented as a
+node in device tree, just like any other hardware module.
+
+For a client device to operate correctly, certain pin controllers must
+set up certain specific pin configurations. Some client devices need a
+single static pin configuration, e.g. set up during initialization. Others
+need to reconfigure pins at run-time, for example to tri-state pins when the
+device is inactive. Hence, each client device can define a set of named
+states. The number and names of those states is defined by the client device's
+own binding.
+
+The common pinctrl bindings defined in this file provide an infrastructure
+for client device device tree nodes to map those state names to the pin
+configuration used by those states.
+
+Note that pin controllers themselves may also be client devices of themselves.
+For example, a pin controller may set up its own "active" state when the
+driver loads. This would allow representing a board's static pin configuration
+in a single place, rather than splitting it across multiple client device
+nodes. The decision to do this or not somewhat rests with the author of
+individual board device tree files, and any requirements imposed by the
+bindings for the individual client devices in use by that board, i.e. whether
+they require certain specific named states for dynamic pin configuration.
+
+== Pinctrl client devices ==
+
+For each client device individually, every pin state is assigned an integer
+ID. These numbers start at 0, and are contiguous. For each state ID, a unique
+property exists to define the pin configuration. Each state may also be
+assigned a name. When names are used, another property exists to map from
+those names to the integer IDs.
+
+Each client device's own binding determines the set of states the must be
+defined in its device tree node, and whether to define the set of state
+IDs that must be provided, or whether to define the set of state names that
+must be provided.
+
+Required properties:
+pinctrl-0:      List of phandles, each pointing at a pin configuration
+                node. These referenced pin configuration nodes must be child
+                nodes of the pin controller that they configure. Multiple
+                entries may exist in this list so that multiple pin
+                controllers may be configured, or so that a state may be built
+                from multiple nodes for a single pin controller, each
+                contributing part of the overall configuration. See the next
+                section of this document for details of the format of these
+                pin configuration nodes.
+
+                In some cases, it may be useful to define a state, but for it
+                to be empty. This may be required when a common IP block is
+                used in an SoC either without a pin controller, or where the
+                pin controller does not affect the HW module in question. If
+                the binding for that IP block requires certain pin states to
+                exist, they must still be defined, but may be left empty.
+
+Optional properties:
+pinctrl-1:      List of phandles, each pointing at a pin configuration
+                node within a pin controller.
+...
+pinctrl-n:      List of phandles, each pointing at a pin configuration
+                node within a pin controller.
+pinctrl-names:  The list of names to assign states. List entry 0 defines the
+                name for integer state ID 0, list entry 1 for state ID 1, and
+                so on.
+
+For example:
+
+        /* For a client device requiring named states */
+        device {
+                pinctrl-names = "active", "idle";
+                pinctrl-0 = <&state_0_node_a>;
+                pinctrl-1 = <&state_1_node_a &state_1_node_b>;
+        };
+
+        /* For the same device if using state IDs */
+        device {
+                pinctrl-0 = <&state_0_node_a>;
+                pinctrl-1 = <&state_1_node_a &state_1_node_b>;
+        };
+
+        /*
+         * For an IP block whose binding supports pin configuration,
+         * but in use on an SoC that doesn't have any pin control hardware
+         */
+        device {
+                pinctrl-names = "active", "idle";
+                pinctrl-0 = <>;
+                pinctrl-1 = <>;
+        };
+
+== Pin controller devices ==
+
+Pin controller devices should contain the pin configuration nodes that client
+devices reference.
+
+For example:
+
+        pincontroller {
+                ... /* Standard DT properties for the device itself elided */
+
+                state_0_node_a {
+                        ...
+                };
+                state_1_node_a {
+                        ...
+                };
+                state_1_node_b {
+                        ...
+                };
+        }
+
+The contents of each of those pin configuration child nodes is defined
+entirely by the binding for the individual pin controller device. There
+exists no common standard for this content.
+
+The pin configuration nodes need not be direct children of the pin controller
+device; they may be grandchildren, for example. Whether this is legal, and
+whether there is any interaction between the child and intermediate parent
+nodes, is again defined entirely by the binding for the individual pin
+controller device.
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt
new file mode 100644
index 000000000000..b4480d5c3aca
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt
@@ -0,0 +1,155 @@
+ST Microelectronics, SPEAr pinmux controller
+
+Required properties:
+- compatible    : "st,spear300-pinmux"
+                : "st,spear310-pinmux"
+                : "st,spear320-pinmux"
+                : "st,spear1310-pinmux"
+                : "st,spear1340-pinmux"
+- reg           : Address range of the pinctrl registers
+- st,pinmux-mode: Mandatory for SPEAr300 and SPEAr320 and invalid for others.
+        - Its values for SPEAr300:
+                - NAND_MODE             : <0>
+                - NOR_MODE              : <1>
+                - PHOTO_FRAME_MODE      : <2>
+                - LEND_IP_PHONE_MODE    : <3>
+                - HEND_IP_PHONE_MODE    : <4>
+                - LEND_WIFI_PHONE_MODE  : <5>
+                - HEND_WIFI_PHONE_MODE  : <6>
+                - ATA_PABX_WI2S_MODE    : <7>
+                - ATA_PABX_I2S_MODE     : <8>
+                - CAML_LCDW_MODE        : <9>
+                - CAMU_LCD_MODE         : <10>
+                - CAMU_WLCD_MODE        : <11>
+                - CAML_LCD_MODE         : <12>
+        - Its values for SPEAr320:
+                - AUTO_NET_SMII_MODE    : <0>
+                - AUTO_NET_MII_MODE     : <1>
+                - AUTO_EXP_MODE         : <2>
+                - SMALL_PRINTERS_MODE   : <3>
+                - EXTENDED_MODE         : <4>
+
+Please refer to pinctrl-bindings.txt in this directory for details of the common
+pinctrl bindings used by client devices.
+
+SPEAr's pinmux nodes act as a container for an abitrary number of subnodes. Each
+of these subnodes represents muxing for a pin, a group, or a list of pins or
+groups.
+
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content.
+
+Required subnode-properties:
+- st,pins : An array of strings. Each string contains the name of a pin or
+  group.
+- st,function: A string containing the name of the function to mux to the pin or
+  group. See the SPEAr's TRM to determine which are valid for each pin or group.
+
+  Valid values for group and function names can be found from looking at the
+  group and function arrays in driver files:
+  drivers/pinctrl/spear/pinctrl-spear3*0.c
+
+Valid values for group names are:
+For All SPEAr3xx machines:
+        "firda_grp", "i2c0_grp", "ssp_cs_grp", "ssp0_grp", "mii0_grp",
+        "gpio0_pin0_grp", "gpio0_pin1_grp", "gpio0_pin2_grp", "gpio0_pin3_grp",
+        "gpio0_pin4_grp", "gpio0_pin5_grp", "uart0_ext_grp", "uart0_grp",
+        "timer_0_1_grp", timer_0_1_pins, "timer_2_3_grp"
+
+For SPEAr300 machines:
+        "fsmc_2chips_grp", "fsmc_4chips_grp", "clcd_lcdmode_grp",
+        "clcd_pfmode_grp", "tdm_grp", "i2c_clk_grp_grp", "caml_grp", "camu_grp",
+        "dac_grp", "i2s_grp", "sdhci_4bit_grp", "sdhci_8bit_grp",
+        "gpio1_0_to_3_grp", "gpio1_4_to_7_grp"
+
+For SPEAr310 machines:
+        "emi_cs_0_to_5_grp", "uart1_grp", "uart2_grp", "uart3_grp", "uart4_grp",
+        "uart5_grp", "fsmc_grp", "rs485_0_grp", "rs485_1_grp", "tdm_grp"
+
+For SPEAr320 machines:
+        "clcd_grp", "emi_grp", "fsmc_8bit_grp", "fsmc_16bit_grp", "spp_grp",
+        "sdhci_led_grp", "sdhci_cd_12_grp", "sdhci_cd_51_grp", "i2s_grp",
+        "uart1_grp", "uart1_modem_2_to_7_grp", "uart1_modem_31_to_36_grp",
+        "uart1_modem_34_to_45_grp", "uart1_modem_80_to_85_grp", "uart2_grp",
+        "uart3_8_9_grp", "uart3_15_16_grp", "uart3_41_42_grp",
+        "uart3_52_53_grp", "uart3_73_74_grp", "uart3_94_95_grp",
+        "uart3_98_99_grp", "uart4_6_7_grp", "uart4_13_14_grp",
+        "uart4_39_40_grp", "uart4_71_72_grp", "uart4_92_93_grp",
+        "uart4_100_101_grp", "uart5_4_5_grp", "uart5_37_38_grp",
+        "uart5_69_70_grp", "uart5_90_91_grp", "uart6_2_3_grp",
+        "uart6_88_89_grp", "rs485_grp", "touchscreen_grp", "can0_grp",
+        "can1_grp", "pwm0_1_pin_8_9_grp", "pwm0_1_pin_14_15_grp",
+        "pwm0_1_pin_30_31_grp", "pwm0_1_pin_37_38_grp", "pwm0_1_pin_42_43_grp",
+        "pwm0_1_pin_59_60_grp", "pwm0_1_pin_88_89_grp", "pwm2_pin_7_grp",
+        "pwm2_pin_13_grp", "pwm2_pin_29_grp", "pwm2_pin_34_grp",
+        "pwm2_pin_41_grp", "pwm2_pin_58_grp", "pwm2_pin_87_grp",
+        "pwm3_pin_6_grp", "pwm3_pin_12_grp", "pwm3_pin_28_grp",
+        "pwm3_pin_40_grp", "pwm3_pin_57_grp", "pwm3_pin_86_grp",
+        "ssp1_17_20_grp", "ssp1_36_39_grp", "ssp1_48_51_grp", "ssp1_65_68_grp",
+        "ssp1_94_97_grp", "ssp2_13_16_grp", "ssp2_32_35_grp", "ssp2_44_47_grp",
+        "ssp2_61_64_grp", "ssp2_90_93_grp", "mii2_grp", "smii0_1_grp",
+        "rmii0_1_grp", "i2c1_8_9_grp", "i2c1_98_99_grp", "i2c2_0_1_grp",
+        "i2c2_2_3_grp", "i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp"
+
+For SPEAr1310 machines:
+        "i2c0_grp", "ssp0_grp", "ssp0_cs0_grp", "ssp0_cs1_2_grp", "i2s0_grp",
+        "i2s1_grp", "clcd_grp", "clcd_high_res_grp", "arm_gpio_grp",
+        "smi_2_chips_grp", "smi_4_chips_grp", "gmii_grp", "rgmii_grp",
+        "smii_0_1_2_grp", "ras_mii_txclk_grp", "nand_8bit_grp",
+        "nand_16bit_grp", "nand_4_chips_grp", "keyboard_6x6_grp",
+        "keyboard_rowcol6_8_grp", "uart0_grp", "uart0_modem_grp",
+        "gpt0_tmr0_grp", "gpt0_tmr1_grp", "gpt1_tmr0_grp", "gpt1_tmr1_grp",
+        "sdhci_grp", "cf_grp", "xd_grp", "touch_xy_grp",
+        "uart1_disable_i2c_grp", "uart1_disable_sd_grp", "uart2_3_grp",
+        "uart4_grp", "uart5_grp", "rs485_0_1_tdm_0_1_grp", "i2c_1_2_grp",
+        "i2c3_dis_smi_clcd_grp", "i2c3_dis_sd_i2s0_grp", "i2c_4_5_dis_smi_grp",
+        "i2c4_dis_sd_grp", "i2c5_dis_sd_grp", "i2c_6_7_dis_kbd_grp",
+        "i2c6_dis_sd_grp", "i2c7_dis_sd_grp", "can0_dis_nor_grp",
+        "can0_dis_sd_grp", "can1_dis_sd_grp", "can1_dis_kbd_grp", "pcie0_grp",
+        "pcie1_grp", "pcie2_grp", "sata0_grp", "sata1_grp", "sata2_grp",
+        "ssp1_dis_kbd_grp", "ssp1_dis_sd_grp", "gpt64_grp"
+
+For SPEAr1340 machines:
+        "pads_as_gpio_grp", "fsmc_8bit_grp", "fsmc_16bit_grp", "fsmc_pnor_grp",
+        "keyboard_row_col_grp", "keyboard_col5_grp", "spdif_in_grp",
+        "spdif_out_grp", "gpt_0_1_grp", "pwm0_grp", "pwm1_grp", "pwm2_grp",
+        "pwm3_grp", "vip_mux_grp", "vip_mux_cam0_grp", "vip_mux_cam1_grp",
+        "vip_mux_cam2_grp", "vip_mux_cam3_grp", "cam0_grp", "cam1_grp",
+        "cam2_grp", "cam3_grp", "smi_grp", "ssp0_grp", "ssp0_cs1_grp",
+        "ssp0_cs2_grp", "ssp0_cs3_grp", "uart0_grp", "uart0_enh_grp",
+        "uart1_grp", "i2s_in_grp", "i2s_out_grp", "gmii_grp", "rgmii_grp",
+        "rmii_grp", "sgmii_grp", "i2c0_grp", "i2c1_grp", "cec0_grp", "cec1_grp",
+        "sdhci_grp", "cf_grp", "xd_grp", "clcd_grp", "arm_trace_grp",
+        "miphy_dbg_grp", "pcie_grp", "sata_grp"
+
+Valid values for function names are:
+For All SPEAr3xx machines:
+        "firda", "i2c0", "ssp_cs", "ssp0", "mii0", "gpio0", "uart0_ext",
+        "uart0", "timer_0_1", "timer_2_3"
+
+For SPEAr300 machines:
+        "fsmc", "clcd", "tdm", "i2c1", "cam", "dac", "i2s", "sdhci", "gpio1"
+
+For SPEAr310 machines:
+        "emi", "uart1", "uart2", "uart3", "uart4", "uart5", "fsmc", "rs485_0",
+        "rs485_1", "tdm"
+
+For SPEAr320 machines:
+        "clcd", "emi", "fsmc", "spp", "sdhci", "i2s", "uart1", "uart1_modem",
+        "uart2", "uart3", "uart4", "uart5", "uart6", "rs485", "touchscreen",
+        "can0", "can1", "pwm0_1", "pwm2", "pwm3", "ssp1", "ssp2", "mii2",
+        "mii0_1", "i2c1", "i2c2"
+
+
+For SPEAr1310 machines:
+        "i2c0", "ssp0", "i2s0", "i2s1", "clcd", "arm_gpio", "smi", "gmii",
+        "rgmii", "smii_0_1_2", "ras_mii_txclk", "nand", "keyboard", "uart0",
+        "gpt0", "gpt1", "sdhci", "cf", "xd", "touchscreen", "uart1", "uart2_3",
+        "uart4", "uart5", "rs485_0_1_tdm_0_1", "i2c_1_2", "i2c3_i2s1",
+        "i2c_4_5", "i2c_6_7", "can0", "can1", "pci", "sata", "ssp1", "gpt64"
+
+For SPEAr1340 machines:
+        "pads_as_gpio", "fsmc", "keyboard", "spdif_in", "spdif_out", "gpt_0_1",
+        "pwm", "vip", "cam0", "cam1", "cam2", "cam3", "smi", "ssp0", "uart0",
+        "uart1", "i2s", "gmac", "i2c0", "i2c1", "cec0", "cec1", "sdhci", "cf",
+        "xd", "clcd", "arm_trace", "miphy_dbg", "pcie", "sata"
diff --git a/Documentation/devicetree/bindings/pinmux/pinmux_nvidia.txt b/Documentation/devicetree/bindings/pinmux/pinmux_nvidia.txt
deleted file mode 100644
index 36f82dbdd14d..000000000000
--- a/Documentation/devicetree/bindings/pinmux/pinmux_nvidia.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-NVIDIA Tegra 2 pinmux controller
-
-Required properties:
-- compatible : "nvidia,tegra20-pinmux"
-
diff --git a/Documentation/driver-model/devres.txt b/Documentation/driver-model/devres.txt
index 2a596a4fc23e..950856bd2e39 100644
--- a/Documentation/driver-model/devres.txt
+++ b/Documentation/driver-model/devres.txt
@@ -276,3 +276,11 @@ REGULATOR
   devm_regulator_get()
   devm_regulator_put()
   devm_regulator_bulk_get()
+
+CLOCK
+  devm_clk_get()
+  devm_clk_put()
+
+PINCTRL
+  devm_pinctrl_get()
+  devm_pinctrl_put()
diff --git a/Documentation/pinctrl.txt b/Documentation/pinctrl.txt
index d97bccf46147..e40f4b4e1977 100644
--- a/Documentation/pinctrl.txt
+++ b/Documentation/pinctrl.txt
@@ -152,11 +152,9 @@ static const struct foo_group foo_groups[] = {
 };
 
 
-static int foo_list_groups(struct pinctrl_dev *pctldev, unsigned selector)
+static int foo_get_groups_count(struct pinctrl_dev *pctldev)
 {
-        if (selector >= ARRAY_SIZE(foo_groups))
-                return -EINVAL;
-        return 0;
+        return ARRAY_SIZE(foo_groups);
 }
 
 static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
@@ -175,7 +173,7 @@ static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
 }
 
 static struct pinctrl_ops foo_pctrl_ops = {
-        .list_groups = foo_list_groups,
+        .get_groups_count = foo_get_groups_count,
         .get_group_name = foo_get_group_name,
         .get_group_pins = foo_get_group_pins,
 };
@@ -186,13 +184,12 @@ static struct pinctrl_desc foo_desc = {
        .pctlops = &foo_pctrl_ops,
 };
 
-The pin control subsystem will call the .list_groups() function repeatedly
-beginning on 0 until it returns non-zero to determine legal selectors, then
-it will call the other functions to retrieve the name and pins of the group.
-Maintaining the data structure of the groups is up to the driver, this is
-just a simple example - in practice you may need more entries in your group
-structure, for example specific register ranges associated with each group
-and so on.
+The pin control subsystem will call the .get_groups_count() function to
+determine total number of legal selectors, then it will call the other functions
+to retrieve the name and pins of the group. Maintaining the data structure of
+the groups is up to the driver, this is just a simple example - in practice you
+may need more entries in your group structure, for example specific register
+ranges associated with each group and so on.
 
 
 Pin configuration
@@ -606,11 +603,9 @@ static const struct foo_group foo_groups[] = {
 };
 
 
-static int foo_list_groups(struct pinctrl_dev *pctldev, unsigned selector)
+static int foo_get_groups_count(struct pinctrl_dev *pctldev)
 {
-        if (selector >= ARRAY_SIZE(foo_groups))
-                return -EINVAL;
-        return 0;
+        return ARRAY_SIZE(foo_groups);
 }
 
 static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
@@ -629,7 +624,7 @@ static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
 }
 
 static struct pinctrl_ops foo_pctrl_ops = {
-        .list_groups = foo_list_groups,
+        .get_groups_count = foo_get_groups_count,
         .get_group_name = foo_get_group_name,
         .get_group_pins = foo_get_group_pins,
 };
@@ -640,7 +635,7 @@ struct foo_pmx_func {
         const unsigned num_groups;
 };
 
-static const char * const spi0_groups[] = { "spi0_1_grp" };
+static const char * const spi0_groups[] = { "spi0_0_grp", "spi0_1_grp" };
 static const char * const i2c0_groups[] = { "i2c0_grp" };
 static const char * const mmc0_groups[] = { "mmc0_1_grp", "mmc0_2_grp",
                                         "mmc0_3_grp" };
@@ -663,11 +658,9 @@ static const struct foo_pmx_func foo_functions[] = {
         },
 };
 
-int foo_list_funcs(struct pinctrl_dev *pctldev, unsigned selector)
+int foo_get_functions_count(struct pinctrl_dev *pctldev)
 {
-        if (selector >= ARRAY_SIZE(foo_functions))
-                return -EINVAL;
-        return 0;
+        return ARRAY_SIZE(foo_functions);
 }
 
 const char *foo_get_fname(struct pinctrl_dev *pctldev, unsigned selector)
@@ -703,7 +696,7 @@ void foo_disable(struct pinctrl_dev *pctldev, unsigned selector,
 }
 
 struct pinmux_ops foo_pmxops = {
-        .list_functions = foo_list_funcs,
+        .get_functions_count = foo_get_functions_count,
         .get_function_name = foo_get_fname,
         .get_function_groups = foo_get_groups,
         .enable = foo_enable,
@@ -786,7 +779,7 @@ and spi on the second function mapping:
 
 #include <linux/pinctrl/machine.h>
 
-static const struct pinctrl_map __initdata mapping[] = {
+static const struct pinctrl_map mapping[] __initconst = {
         {
                 .dev_name = "foo-spi.0",
                 .name = PINCTRL_STATE_DEFAULT,
@@ -952,13 +945,13 @@ case), we define a mapping like this:
 The result of grabbing this mapping from the device with something like
 this (see next paragraph):
 
-        p = pinctrl_get(dev);
+        p = devm_pinctrl_get(dev);
         s = pinctrl_lookup_state(p, "8bit");
         ret = pinctrl_select_state(p, s);
 
 or more simply:
 
-        p = pinctrl_get_select(dev, "8bit");
+        p = devm_pinctrl_get_select(dev, "8bit");
 
 Will be that you activate all the three bottom records in the mapping at
 once. Since they share the same name, pin controller device, function and
@@ -992,7 +985,7 @@ foo_probe()
         /* Allocate a state holder named "foo" etc */
         struct foo_state *foo = ...;
 
-        foo->p = pinctrl_get(&device);
+        foo->p = devm_pinctrl_get(&device);
         if (IS_ERR(foo->p)) {
                 /* FIXME: clean up "foo" here */
                 return PTR_ERR(foo->p);
@@ -1000,24 +993,17 @@ foo_probe()
 
         foo->s = pinctrl_lookup_state(foo->p, PINCTRL_STATE_DEFAULT);
         if (IS_ERR(foo->s)) {
-                pinctrl_put(foo->p);
                 /* FIXME: clean up "foo" here */
                 return PTR_ERR(s);
         }
 
         ret = pinctrl_select_state(foo->s);
         if (ret < 0) {
-                pinctrl_put(foo->p);
                 /* FIXME: clean up "foo" here */
                 return ret;
         }
 }
 
-foo_remove()
-{
-        pinctrl_put(state->p);
-}
-
 This get/lookup/select/put sequence can just as well be handled by bus drivers
 if you don't want each and every driver to handle it and you know the
 arrangement on your bus.
@@ -1029,6 +1015,11 @@ The semantics of the pinctrl APIs are:
   kernel memory to hold the pinmux state. All mapping table parsing or similar
   slow operations take place within this API.
 
+- devm_pinctrl_get() is a variant of pinctrl_get() that causes pinctrl_put()
+  to be called automatically on the retrieved pointer when the associated
+  device is removed. It is recommended to use this function over plain
+  pinctrl_get().
+
 - pinctrl_lookup_state() is called in process context to obtain a handle to a
   specific state for a the client device. This operation may be slow too.
 
@@ -1041,14 +1032,30 @@ The semantics of the pinctrl APIs are:
 
 - pinctrl_put() frees all information associated with a pinctrl handle.
 
+- devm_pinctrl_put() is a variant of pinctrl_put() that may be used to
+  explicitly destroy a pinctrl object returned by devm_pinctrl_get().
+  However, use of this function will be rare, due to the automatic cleanup
+  that will occur even without calling it.
+
+  pinctrl_get() must be paired with a plain pinctrl_put().
+  pinctrl_get() may not be paired with devm_pinctrl_put().
+  devm_pinctrl_get() can optionally be paired with devm_pinctrl_put().
+  devm_pinctrl_get() may not be paired with plain pinctrl_put().
+
 Usually the pin control core handled the get/put pair and call out to the
 device drivers bookkeeping operations, like checking available functions and
 the associated pins, whereas the enable/disable pass on to the pin controller
 driver which takes care of activating and/or deactivating the mux setting by
 quickly poking some registers.
 
-The pins are allocated for your device when you issue the pinctrl_get() call,
-after this you should be able to see this in the debugfs listing of all pins.
+The pins are allocated for your device when you issue the devm_pinctrl_get()
+call, after this you should be able to see this in the debugfs listing of all
+pins.
+
+NOTE: the pinctrl system will return -EPROBE_DEFER if it cannot find the
+requested pinctrl handles, for example if the pinctrl driver has not yet
+registered. Thus make sure that the error path in your driver gracefully
+cleans up and is ready to retry the probing later in the startup process.
 
 
 System pin control hogging
@@ -1094,13 +1101,13 @@ it, disables and releases it, and muxes it in on the pins defined by group B:
 
 #include <linux/pinctrl/consumer.h>
 
-foo_switch()
-{
-        struct pinctrl *p;
-        struct pinctrl_state *s1, *s2;
+struct pinctrl *p;
+struct pinctrl_state *s1, *s2;
 
+foo_probe()
+{
         /* Setup */
-        p = pinctrl_get(&device);
+        p = devm_pinctrl_get(&device);
         if (IS_ERR(p))
                 ...
 
@@ -1111,7 +1118,10 @@ foo_switch()
         s2 = pinctrl_lookup_state(foo->p, "pos-B");
         if (IS_ERR(s2))
                 ...
+}
 
+foo_switch()
+{
         /* Enable on position A */
         ret = pinctrl_select_state(s1);
         if (ret < 0)
@@ -1125,8 +1135,6 @@ foo_switch()
             ...
 
         ...
-
-        pinctrl_put(p);
 }
 
 The above has to be done from process context.
diff --git a/MAINTAINERS b/MAINTAINERS
index b36270986501..fa81a16e4641 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1882,6 +1882,16 @@ F:	Documentation/filesystems/coda.txt
 F:      fs/coda/
 F:      include/linux/coda*.h
 
+COMMON CLK FRAMEWORK
+M:      Mike Turquette <mturquette@ti.com>
+M:      Mike Turquette <mturquette@linaro.org>
+L:      linux-arm-kernel@lists.infradead.org (same as CLK API & CLKDEV)
+T:      git git://git.linaro.org/people/mturquette/linux.git
+S:      Maintained
+F:      drivers/clk/clk.c
+F:      drivers/clk/clk-*
+F:      include/linux/clk-pr*
+
 COMMON INTERNET FILE SYSTEM (CIFS)
 M:      Steve French <sfrench@samba.org>
 L:      linux-cifs@vger.kernel.org
@@ -5235,6 +5245,14 @@ M:	Linus Walleij <linus.walleij@linaro.org>
 S:      Maintained
 F:      drivers/pinctrl/
 
+PIN CONTROLLER - ST SPEAR
+M:      Viresh Kumar <viresh.kumar@st.com>
+L:      spear-devel@list.st.com
+L:      linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+W:      http://www.st.com/spear
+S:      Maintained
+F:      driver/pinctrl/spear/
+
 PKTCDVD DRIVER
 M:      Peter Osterlund <petero2@telia.com>
 S:      Maintained
@@ -6299,52 +6317,48 @@ F:	include/linux/compiler.h
 
 SPEAR PLATFORM SUPPORT
 M:      Viresh Kumar <viresh.kumar@st.com>
+M:      Shiraz Hashim <shiraz.hashim@st.com>
 L:      spear-devel@list.st.com
 L:      linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 W:      http://www.st.com/spear
 S:      Maintained
 F:      arch/arm/plat-spear/
 
-SPEAR3XX MACHINE SUPPORT
+SPEAR13XX MACHINE SUPPORT
 M:      Viresh Kumar <viresh.kumar@st.com>
+M:      Shiraz Hashim <shiraz.hashim@st.com>
 L:      spear-devel@list.st.com
 L:      linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 W:      http://www.st.com/spear
 S:      Maintained
-F:      arch/arm/mach-spear3xx/
+F:      arch/arm/mach-spear13xx/
 
-SPEAR6XX MACHINE SUPPORT
-M:      Rajeev Kumar <rajeev-dlh.kumar@st.com>
+SPEAR3XX MACHINE SUPPORT
+M:      Viresh Kumar <viresh.kumar@st.com>
+M:      Shiraz Hashim <shiraz.hashim@st.com>
 L:      spear-devel@list.st.com
 L:      linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 W:      http://www.st.com/spear
 S:      Maintained
-F:      arch/arm/mach-spear6xx/
+F:      arch/arm/mach-spear3xx/
 
-SPEAR CLOCK FRAMEWORK SUPPORT
+SPEAR6XX MACHINE SUPPORT
+M:      Rajeev Kumar <rajeev-dlh.kumar@st.com>
+M:      Shiraz Hashim <shiraz.hashim@st.com>
 M:      Viresh Kumar <viresh.kumar@st.com>
 L:      spear-devel@list.st.com
 L:      linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 W:      http://www.st.com/spear
 S:      Maintained
-F:      arch/arm/mach-spear*/clock.c
-F:      arch/arm/plat-spear/clock.c
-F:      arch/arm/plat-spear/include/plat/clock.h
+F:      arch/arm/mach-spear6xx/
 
-SPEAR PAD MULTIPLEXING SUPPORT
+SPEAR CLOCK FRAMEWORK SUPPORT
 M:      Viresh Kumar <viresh.kumar@st.com>
 L:      spear-devel@list.st.com
 L:      linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 W:      http://www.st.com/spear
 S:      Maintained
-F:      arch/arm/plat-spear/include/plat/padmux.h
-F:      arch/arm/plat-spear/padmux.c
-F:      arch/arm/mach-spear*/spear*xx.c
-F:      arch/arm/mach-spear*/include/mach/generic.h
-F:      arch/arm/mach-spear3xx/spear3*0.c
-F:      arch/arm/mach-spear3xx/spear3*0_evb.c
-F:      arch/arm/mach-spear6xx/spear600.c
-F:      arch/arm/mach-spear6xx/spear600_evb.c
+F:      drivers/clk/spear/
 
 SPI SUBSYSTEM
 M:      Grant Likely <grant.likely@secretlab.ca>
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 36586dba6fa6..75066ed1f649 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -980,6 +980,7 @@ config PLAT_SPEAR
         select ARM_AMBA
         select ARCH_REQUIRE_GPIOLIB
         select CLKDEV_LOOKUP
+        select COMMON_CLK
         select CLKSRC_MMIO
         select GENERIC_CLOCKEVENTS
         select HAVE_CLK
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 047a20780fc1..2aa75b58bf12 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -192,6 +192,8 @@ machine-$(CONFIG_ARCH_VEXPRESS)		:= vexpress
 machine-$(CONFIG_ARCH_VT8500)           := vt8500
 machine-$(CONFIG_ARCH_W90X900)          := w90x900
 machine-$(CONFIG_FOOTBRIDGE)            := footbridge
+machine-$(CONFIG_MACH_SPEAR1310)        := spear13xx
+machine-$(CONFIG_MACH_SPEAR1340)        := spear13xx
 machine-$(CONFIG_MACH_SPEAR300)         := spear3xx
 machine-$(CONFIG_MACH_SPEAR310)         := spear3xx
 machine-$(CONFIG_MACH_SPEAR320)         := spear3xx
diff --git a/arch/arm/boot/dts/spear1310-evb.dts b/arch/arm/boot/dts/spear1310-evb.dts
new file mode 100644
index 000000000000..8314e4171884
--- /dev/null
+++ b/arch/arm/boot/dts/spear1310-evb.dts
@@ -0,0 +1,292 @@
+/*
+ * DTS file for SPEAr1310 Evaluation Baord
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "spear1310.dtsi"
+
+/ {
+        model = "ST SPEAr1310 Evaluation Board";
+        compatible = "st,spear1310-evb", "st,spear1310";
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        memory {
+                reg = <0 0x40000000>;
+        };
+
+        ahb {
+                pinmux@e0700000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&state_default>;
+
+                        state_default: pinmux {
+                                i2c0-pmx {
+                                        st,pins = "i2c0_grp";
+                                        st,function = "i2c0";
+                                };
+                                i2s1 {
+                                        st,pins = "i2s1_grp";
+                                        st,function = "i2s1";
+                                };
+                                gpio {
+                                        st,pins = "arm_gpio_grp";
+                                        st,function = "arm_gpio";
+                                };
+                                eth {
+                                        st,pins = "gmii_grp";
+                                        st,function = "gmii";
+                                };
+                                ssp0 {
+                                        st,pins = "ssp0_grp";
+                                        st,function = "ssp0";
+                                };
+                                kbd {
+                                        st,pins = "keyboard_6x6_grp";
+                                        st,function = "keyboard";
+                                };
+                                sdhci {
+                                        st,pins = "sdhci_grp";
+                                        st,function = "sdhci";
+                                };
+                                smi-pmx {
+                                        st,pins = "smi_2_chips_grp";
+                                        st,function = "smi";
+                                };
+                                uart0 {
+                                        st,pins = "uart0_grp";
+                                        st,function = "uart0";
+                                };
+                                rs485 {
+                                        st,pins = "rs485_0_1_tdm_0_1_grp";
+                                        st,function = "rs485_0_1_tdm_0_1";
+                                };
+                                i2c1_2 {
+                                        st,pins = "i2c_1_2_grp";
+                                        st,function = "i2c_1_2";
+                                };
+                                pci {
+                                        st,pins = "pcie0_grp","pcie1_grp",
+                                                "pcie2_grp";
+                                        st,function = "pci";
+                                };
+                                smii {
+                                        st,pins = "smii_0_1_2_grp";
+                                        st,function = "smii_0_1_2";
+                                };
+                                nand {
+                                        st,pins = "nand_8bit_grp",
+                                                "nand_16bit_grp";
+                                        st,function = "nand";
+                                };
+                        };
+                };
+
+                ahci@b1000000 {
+                        status = "okay";
+                };
+
+                cf@b2800000 {
+                        status = "okay";
+                };
+
+                dma@ea800000 {
+                        status = "okay";
+                };
+
+                dma@eb000000 {
+                        status = "okay";
+                };
+
+                fsmc: flash@b0000000 {
+                        status = "okay";
+                };
+
+                gmac0: eth@e2000000 {
+                        status = "okay";
+                };
+
+                sdhci@b3000000 {
+                        status = "okay";
+                };
+
+                smi: flash@ea000000 {
+                        status = "okay";
+                        clock-rate=<50000000>;
+
+                        flash@e6000000 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                reg = <0xe6000000 0x800000>;
+                                st,smi-fast-mode;
+
+                                partition@0 {
+                                        label = "xloader";
+                                        reg = <0x0 0x10000>;
+                                };
+                                partition@10000 {
+                                        label = "u-boot";
+                                        reg = <0x10000 0x40000>;
+                                };
+                                partition@50000 {
+                                        label = "linux";
+                                        reg = <0x50000 0x2c0000>;
+                                };
+                                partition@310000 {
+                                        label = "rootfs";
+                                        reg = <0x310000 0x4f0000>;
+                                };
+                        };
+                };
+
+                spi0: spi@e0100000 {
+                        status = "okay";
+                };
+
+                ehci@e4800000 {
+                        status = "okay";
+                };
+
+                ehci@e5800000 {
+                        status = "okay";
+                };
+
+                ohci@e4000000 {
+                        status = "okay";
+                };
+
+                ohci@e5000000 {
+                        status = "okay";
+                };
+
+                apb {
+                        adc@e0080000 {
+                                status = "okay";
+                        };
+
+                        gpio0: gpio@e0600000 {
+                               status = "okay";
+                        };
+
+                        gpio1: gpio@e0680000 {
+                               status = "okay";
+                        };
+
+                        i2c0: i2c@e0280000 {
+                               status = "okay";
+                        };
+
+                        i2c1: i2c@5cd00000 {
+                               status = "okay";
+                        };
+
+                        kbd@e0300000 {
+                                linux,keymap = < 0x00000001
+                                                 0x00010002
+                                                 0x00020003
+                                                 0x00030004
+                                                 0x00040005
+                                                 0x00050006
+                                                 0x00060007
+                                                 0x00070008
+                                                 0x00080009
+                                                 0x0100000a
+                                                 0x0101000c
+                                                 0x0102000d
+                                                 0x0103000e
+                                                 0x0104000f
+                                                 0x01050010
+                                                 0x01060011
+                                                 0x01070012
+                                                 0x01080013
+                                                 0x02000014
+                                                 0x02010015
+                                                 0x02020016
+                                                 0x02030017
+                                                 0x02040018
+                                                 0x02050019
+                                                 0x0206001a
+                                                 0x0207001b
+                                                 0x0208001c
+                                                 0x0300001d
+                                                 0x0301001e
+                                                 0x0302001f
+                                                 0x03030020
+                                                 0x03040021
+                                                 0x03050022
+                                                 0x03060023
+                                                 0x03070024
+                                                 0x03080025
+                                                 0x04000026
+                                                 0x04010027
+                                                 0x04020028
+                                                 0x04030029
+                                                 0x0404002a
+                                                 0x0405002b
+                                                 0x0406002c
+                                                 0x0407002d
+                                                 0x0408002e
+                                                 0x0500002f
+                                                 0x05010030
+                                                 0x05020031
+                                                 0x05030032
+                                                 0x05040033
+                                                 0x05050034
+                                                 0x05060035
+                                                 0x05070036
+                                                 0x05080037
+                                                 0x06000038
+                                                 0x06010039
+                                                 0x0602003a
+                                                 0x0603003b
+                                                 0x0604003c
+                                                 0x0605003d
+                                                 0x0606003e
+                                                 0x0607003f
+                                                 0x06080040
+                                                 0x07000041
+                                                 0x07010042
+                                                 0x07020043
+                                                 0x07030044
+                                                 0x07040045
+                                                 0x07050046
+                                                 0x07060047
+                                                 0x07070048
+                                                 0x07080049
+                                                 0x0800004a
+                                                 0x0801004b
+                                                 0x0802004c
+                                                 0x0803004d
+                                                 0x0804004e
+                                                 0x0805004f
+                                                 0x08060050
+                                                 0x08070051
+                                                 0x08080052 >;
+                               autorepeat;
+                               st,mode = <0>;
+                               status = "okay";
+                        };
+
+                        rtc@e0580000 {
+                               status = "okay";
+                        };
+
+                        serial@e0000000 {
+                               status = "okay";
+                        };
+
+                        wdt@ec800620 {
+                               status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/spear1310.dtsi
new file mode 100644
index 000000000000..9e61da404d57
--- /dev/null
+++ b/arch/arm/boot/dts/spear1310.dtsi
@@ -0,0 +1,184 @@
+/*
+ * DTS file for all SPEAr1310 SoCs
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "spear13xx.dtsi"
+
+/ {
+        compatible = "st,spear1310";
+
+        ahb {
+                ahci@b1000000 {
+                        compatible = "snps,spear-ahci";
+                        reg = <0xb1000000 0x10000>;
+                        interrupts = <0 68 0x4>;
+                        status = "disabled";
+                };
+
+                ahci@b1800000 {
+                        compatible = "snps,spear-ahci";
+                        reg = <0xb1800000 0x10000>;
+                        interrupts = <0 69 0x4>;
+                        status = "disabled";
+                };
+
+                ahci@b4000000 {
+                        compatible = "snps,spear-ahci";
+                        reg = <0xb4000000 0x10000>;
+                        interrupts = <0 70 0x4>;
+                        status = "disabled";
+                };
+
+                gmac1: eth@5c400000 {
+                        compatible = "st,spear600-gmac";
+                        reg = <0x5c400000 0x8000>;
+                        interrupts = <0 95 0x4>;
+                        interrupt-names = "macirq";
+                        status = "disabled";
+                };
+
+                gmac2: eth@5c500000 {
+                        compatible = "st,spear600-gmac";
+                        reg = <0x5c500000 0x8000>;
+                        interrupts = <0 96 0x4>;
+                        interrupt-names = "macirq";
+                        status = "disabled";
+                };
+
+                gmac3: eth@5c600000 {
+                        compatible = "st,spear600-gmac";
+                        reg = <0x5c600000 0x8000>;
+                        interrupts = <0 97 0x4>;
+                        interrupt-names = "macirq";
+                        status = "disabled";
+                };
+
+                gmac4: eth@5c700000 {
+                        compatible = "st,spear600-gmac";
+                        reg = <0x5c700000 0x8000>;
+                        interrupts = <0 98 0x4>;
+                        interrupt-names = "macirq";
+                        status = "disabled";
+                };
+
+                spi1: spi@5d400000 {
+                        compatible = "arm,pl022", "arm,primecell";
+                        reg = <0x5d400000 0x1000>;
+                        interrupts = <0 99 0x4>;
+                        status = "disabled";
+                };
+
+                apb {
+                        i2c1: i2c@5cd00000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "snps,designware-i2c";
+                                reg = <0x5cd00000 0x1000>;
+                                interrupts = <0 87 0x4>;
+                                status = "disabled";
+                        };
+
+                        i2c2: i2c@5ce00000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "snps,designware-i2c";
+                                reg = <0x5ce00000 0x1000>;
+                                interrupts = <0 88 0x4>;
+                                status = "disabled";
+                        };
+
+                        i2c3: i2c@5cf00000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "snps,designware-i2c";
+                                reg = <0x5cf00000 0x1000>;
+                                interrupts = <0 89 0x4>;
+                                status = "disabled";
+                        };
+
+                        i2c4: i2c@5d000000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "snps,designware-i2c";
+                                reg = <0x5d000000 0x1000>;
+                                interrupts = <0 90 0x4>;
+                                status = "disabled";
+                        };
+
+                        i2c5: i2c@5d100000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "snps,designware-i2c";
+                                reg = <0x5d100000 0x1000>;
+                                interrupts = <0 91 0x4>;
+                                status = "disabled";
+                        };
+
+                        i2c6: i2c@5d200000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "snps,designware-i2c";
+                                reg = <0x5d200000 0x1000>;
+                                interrupts = <0 92 0x4>;
+                                status = "disabled";
+                        };
+
+                        i2c7: i2c@5d300000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "snps,designware-i2c";
+                                reg = <0x5d300000 0x1000>;
+                                interrupts = <0 93 0x4>;
+                                status = "disabled";
+                        };
+
+                        serial@5c800000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0x5c800000 0x1000>;
+                                interrupts = <0 82 0x4>;
+                                status = "disabled";
+                        };
+
+                        serial@5c900000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0x5c900000 0x1000>;
+                                interrupts = <0 83 0x4>;
+                                status = "disabled";
+                        };
+
+                        serial@5ca00000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0x5ca00000 0x1000>;
+                                interrupts = <0 84 0x4>;
+                                status = "disabled";
+                        };
+
+                        serial@5cb00000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0x5cb00000 0x1000>;
+                                interrupts = <0 85 0x4>;
+                                status = "disabled";
+                        };
+
+                        serial@5cc00000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0x5cc00000 0x1000>;
+                                interrupts = <0 86 0x4>;
+                                status = "disabled";
+                        };
+
+                        thermal@e07008c4 {
+                                st,thermal-flags = <0x7000>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/spear1340-evb.dts b/arch/arm/boot/dts/spear1340-evb.dts
new file mode 100644
index 000000000000..0d8472e5ab9f
--- /dev/null
+++ b/arch/arm/boot/dts/spear1340-evb.dts
@@ -0,0 +1,308 @@
+/*
+ * DTS file for SPEAr1340 Evaluation Baord
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "spear1340.dtsi"
+
+/ {
+        model = "ST SPEAr1340 Evaluation Board";
+        compatible = "st,spear1340-evb", "st,spear1340";
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        memory {
+                reg = <0 0x40000000>;
+        };
+
+        ahb {
+                pinmux@e0700000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&state_default>;
+
+                        state_default: pinmux {
+                                pads_as_gpio {
+                                        st,pins = "pads_as_gpio_grp";
+                                        st,function = "pads_as_gpio";
+                                };
+                                fsmc {
+                                        st,pins = "fsmc_8bit_grp";
+                                        st,function = "fsmc";
+                                };
+                                kbd {
+                                        st,pins = "keyboard_row_col_grp",
+                                                "keyboard_col5_grp";
+                                        st,function = "keyboard";
+                                };
+                                uart0 {
+                                        st,pins = "uart0_grp", "uart0_enh_grp";
+                                        st,function = "uart0";
+                                };
+                                i2c0-pmx {
+                                        st,pins = "i2c0_grp";
+                                        st,function = "i2c0";
+                                };
+                                i2c1-pmx {
+                                        st,pins = "i2c1_grp";
+                                        st,function = "i2c1";
+                                };
+                                spdif-in {
+                                        st,pins = "spdif_in_grp";
+                                        st,function = "spdif_in";
+                                };
+                                spdif-out {
+                                        st,pins = "spdif_out_grp";
+                                        st,function = "spdif_out";
+                                };
+                                ssp0 {
+                                        st,pins = "ssp0_grp", "ssp0_cs1_grp",
+                                                "ssp0_cs3_grp";
+                                        st,function = "ssp0";
+                                };
+                                pwm {
+                                        st,pins = "pwm2_grp", "pwm3_grp";
+                                        st,function = "pwm";
+                                };
+                                smi-pmx {
+                                        st,pins = "smi_grp";
+                                        st,function = "smi";
+                                };
+                                i2s {
+                                        st,pins = "i2s_in_grp", "i2s_out_grp";
+                                        st,function = "i2s";
+                                };
+                                gmac {
+                                        st,pins = "gmii_grp", "rgmii_grp";
+                                        st,function = "gmac";
+                                };
+                                cam3 {
+                                        st,pins = "cam3_grp";
+                                        st,function = "cam3";
+                                };
+                                cec0 {
+                                        st,pins = "cec0_grp";
+                                        st,function = "cec0";
+                                };
+                                cec1 {
+                                        st,pins = "cec1_grp";
+                                        st,function = "cec1";
+                                };
+                                sdhci {
+                                        st,pins = "sdhci_grp";
+                                        st,function = "sdhci";
+                                };
+                                clcd {
+                                        st,pins = "clcd_grp";
+                                        st,function = "clcd";
+                                };
+                                sata {
+                                        st,pins = "sata_grp";
+                                        st,function = "sata";
+                                };
+                        };
+                };
+
+                dma@ea800000 {
+                        status = "okay";
+                };
+
+                dma@eb000000 {
+                        status = "okay";
+                };
+
+                fsmc: flash@b0000000 {
+                        status = "okay";
+                };
+
+                gmac0: eth@e2000000 {
+                        status = "okay";
+                };
+
+                sdhci@b3000000 {
+                        status = "okay";
+                };
+
+                smi: flash@ea000000 {
+                        status = "okay";
+                        clock-rate=<50000000>;
+
+                        flash@e6000000 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                reg = <0xe6000000 0x800000>;
+                                st,smi-fast-mode;
+
+                                partition@0 {
+                                        label = "xloader";
+                                        reg = <0x0 0x10000>;
+                                };
+                                partition@10000 {
+                                        label = "u-boot";
+                                        reg = <0x10000 0x40000>;
+                                };
+                                partition@50000 {
+                                        label = "linux";
+                                        reg = <0x50000 0x2c0000>;
+                                };
+                                partition@310000 {
+                                        label = "rootfs";
+                                        reg = <0x310000 0x4f0000>;
+                                };
+                        };
+                };
+
+                spi0: spi@e0100000 {
+                        status = "okay";
+                };
+
+                ehci@e4800000 {
+                        status = "okay";
+                };
+
+                ehci@e5800000 {
+                        status = "okay";
+                };
+
+                ohci@e4000000 {
+                        status = "okay";
+                };
+
+                ohci@e5000000 {
+                        status = "okay";
+                };
+
+                apb {
+                        adc@e0080000 {
+                                status = "okay";
+                        };
+
+                        gpio0: gpio@e0600000 {
+                               status = "okay";
+                        };
+
+                        gpio1: gpio@e0680000 {
+                               status = "okay";
+                        };
+
+                        i2c0: i2c@e0280000 {
+                               status = "okay";
+                        };
+
+                        i2c1: i2c@b4000000 {
+                               status = "okay";
+                        };
+
+                        kbd@e0300000 {
+                                linux,keymap = < 0x00000001
+                                                 0x00010002
+                                                 0x00020003
+                                                 0x00030004
+                                                 0x00040005
+                                                 0x00050006
+                                                 0x00060007
+                                                 0x00070008
+                                                 0x00080009
+                                                 0x0100000a
+                                                 0x0101000c
+                                                 0x0102000d
+                                                 0x0103000e
+                                                 0x0104000f
+                                                 0x01050010
+                                                 0x01060011
+                                                 0x01070012
+                                                 0x01080013
+                                                 0x02000014
+                                                 0x02010015
+                                                 0x02020016
+                                                 0x02030017
+                                                 0x02040018
+                                                 0x02050019
+                                                 0x0206001a
+                                                 0x0207001b
+                                                 0x0208001c
+                                                 0x0300001d
+                                                 0x0301001e
+                                                 0x0302001f
+                                                 0x03030020
+                                                 0x03040021
+                                                 0x03050022
+                                                 0x03060023
+                                                 0x03070024
+                                                 0x03080025
+                                                 0x04000026
+                                                 0x04010027
+                                                 0x04020028
+                                                 0x04030029
+                                                 0x0404002a
+                                                 0x0405002b
+                                                 0x0406002c
+                                                 0x0407002d
+                                                 0x0408002e
+                                                 0x0500002f
+                                                 0x05010030
+                                                 0x05020031
+                                                 0x05030032
+                                                 0x05040033
+                                                 0x05050034
+                                                 0x05060035
+                                                 0x05070036
+                                                 0x05080037
+                                                 0x06000038
+                                                 0x06010039
+                                                 0x0602003a
+                                                 0x0603003b
+                                                 0x0604003c
+                                                 0x0605003d
+                                                 0x0606003e
+                                                 0x0607003f
+                                                 0x06080040
+                                                 0x07000041
+                                                 0x07010042
+                                                 0x07020043
+                                                 0x07030044
+                                                 0x07040045
+                                                 0x07050046
+                                                 0x07060047
+                                                 0x07070048
+                                                 0x07080049
+                                                 0x0800004a
+                                                 0x0801004b
+                                                 0x0802004c
+                                                 0x0803004d
+                                                 0x0804004e
+                                                 0x0805004f
+                                                 0x08060050
+                                                 0x08070051
+                                                 0x08080052 >;
+                               autorepeat;
+                               st,mode = <0>;
+                               status = "okay";
+                        };
+
+                        rtc@e0580000 {
+                               status = "okay";
+                        };
+
+                        serial@e0000000 {
+                               status = "okay";
+                        };
+
+                        serial@b4100000 {
+                               status = "okay";
+                        };
+
+                        wdt@ec800620 {
+                               status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi
new file mode 100644
index 000000000000..a26fc47a55e8
--- /dev/null
+++ b/arch/arm/boot/dts/spear1340.dtsi
@@ -0,0 +1,56 @@
+/*
+ * DTS file for all SPEAr1340 SoCs
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "spear13xx.dtsi"
+
+/ {
+        compatible = "st,spear1340";
+
+        ahb {
+                ahci@b1000000 {
+                        compatible = "snps,spear-ahci";
+                        reg = <0xb1000000 0x10000>;
+                        interrupts = <0 72 0x4>;
+                        status = "disabled";
+                };
+
+                spi1: spi@5d400000 {
+                        compatible = "arm,pl022", "arm,primecell";
+                        reg = <0x5d400000 0x1000>;
+                        interrupts = <0 99 0x4>;
+                        status = "disabled";
+                };
+
+                apb {
+                        i2c1: i2c@b4000000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "snps,designware-i2c";
+                                reg = <0xb4000000 0x1000>;
+                                interrupts = <0 104 0x4>;
+                                status = "disabled";
+                        };
+
+                        serial@b4100000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0xb4100000 0x1000>;
+                                interrupts = <0 105 0x4>;
+                                status = "disabled";
+                        };
+
+                        thermal@e07008c4 {
+                                st,thermal-flags = <0x2a00>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
new file mode 100644
index 000000000000..1f8e1e1481df
--- /dev/null
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -0,0 +1,262 @@
+/*
+ * DTS file for all SPEAr13xx SoCs
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        interrupt-parent = <&gic>;
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        compatible = "arm,cortex-a9";
+                        reg = <0>;
+                        next-level-cache = <&L2>;
+                };
+
+                cpu@1 {
+                        compatible = "arm,cortex-a9";
+                        reg = <1>;
+                        next-level-cache = <&L2>;
+                };
+        };
+
+        gic: interrupt-controller@ec801000 {
+                compatible = "arm,cortex-a9-gic";
+                interrupt-controller;
+                #interrupt-cells = <3>;
+                reg = < 0xec801000 0x1000 >,
+                      < 0xec800100 0x0100 >;
+        };
+
+        pmu {
+                compatible = "arm,cortex-a9-pmu";
+                interrupts = <0 8 0x04
+                              0 9 0x04>;
+        };
+
+        L2: l2-cache {
+                    compatible = "arm,pl310-cache";
+                    reg = <0xed000000 0x1000>;
+                    cache-unified;
+                    cache-level = <2>;
+        };
+
+        memory {
+                name = "memory";
+                device_type = "memory";
+                reg = <0 0x40000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyAMA0,115200";
+        };
+
+        ahb {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges = <0x50000000 0x50000000 0x10000000
+                          0xb0000000 0xb0000000 0x10000000
+                          0xe0000000 0xe0000000 0x10000000>;
+
+                sdhci@b3000000 {
+                        compatible = "st,sdhci-spear";
+                        reg = <0xb3000000 0x100>;
+                        interrupts = <0 28 0x4>;
+                        status = "disabled";
+                };
+
+                cf@b2800000 {
+                        compatible = "arasan,cf-spear1340";
+                        reg = <0xb2800000 0x100>;
+                        interrupts = <0 29 0x4>;
+                        status = "disabled";
+                };
+
+                dma@ea800000 {
+                        compatible = "snps,dma-spear1340";
+                        reg = <0xea800000 0x1000>;
+                        interrupts = <0 19 0x4>;
+                        status = "disabled";
+                };
+
+                dma@eb000000 {
+                        compatible = "snps,dma-spear1340";
+                        reg = <0xeb000000 0x1000>;
+                        interrupts = <0 59 0x4>;
+                        status = "disabled";
+                };
+
+                fsmc: flash@b0000000 {
+                        compatible = "st,spear600-fsmc-nand";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0xb0000000 0x1000        /* FSMC Register */
+                               0xb0800000 0x0010>;      /* NAND Base */
+                        reg-names = "fsmc_regs", "nand_data";
+                        interrupts = <0 20 0x4
+                                      0 21 0x4
+                                      0 22 0x4
+                                      0 23 0x4>;
+                        st,ale-off = <0x20000>;
+                        st,cle-off = <0x10000>;
+                        status = "disabled";
+                };
+
+                gmac0: eth@e2000000 {
+                        compatible = "st,spear600-gmac";
+                        reg = <0xe2000000 0x8000>;
+                        interrupts = <0 23 0x4
+                                      0 24 0x4>;
+                        interrupt-names = "macirq", "eth_wake_irq";
+                        status = "disabled";
+                };
+
+                smi: flash@ea000000 {
+                        compatible = "st,spear600-smi";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0xea000000 0x1000>;
+                        interrupts = <0 30 0x4>;
+                        status = "disabled";
+                };
+
+                spi0: spi@e0100000 {
+                        compatible = "arm,pl022", "arm,primecell";
+                        reg = <0xe0100000 0x1000>;
+                        interrupts = <0 31 0x4>;
+                        status = "disabled";
+                };
+
+                ehci@e4800000 {
+                        compatible = "st,spear600-ehci", "usb-ehci";
+                        reg = <0xe4800000 0x1000>;
+                        interrupts = <0 64 0x4>;
+                        status = "disabled";
+                };
+
+                ehci@e5800000 {
+                        compatible = "st,spear600-ehci", "usb-ehci";
+                        reg = <0xe5800000 0x1000>;
+                        interrupts = <0 66 0x4>;
+                        status = "disabled";
+                };
+
+                ohci@e4000000 {
+                        compatible = "st,spear600-ohci", "usb-ohci";
+                        reg = <0xe4000000 0x1000>;
+                        interrupts = <0 65 0x4>;
+                        status = "disabled";
+                };
+
+                ohci@e5000000 {
+                        compatible = "st,spear600-ohci", "usb-ohci";
+                        reg = <0xe5000000 0x1000>;
+                        interrupts = <0 67 0x4>;
+                        status = "disabled";
+                };
+
+                apb {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "simple-bus";
+                        ranges = <0x50000000 0x50000000 0x10000000
+                                  0xb0000000 0xb0000000 0x10000000
+                                  0xe0000000 0xe0000000 0x10000000>;
+
+                        gpio0: gpio@e0600000 {
+                                compatible = "arm,pl061", "arm,primecell";
+                                reg = <0xe0600000 0x1000>;
+                                interrupts = <0 24 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                status = "disabled";
+                        };
+
+                        gpio1: gpio@e0680000 {
+                                compatible = "arm,pl061", "arm,primecell";
+                                reg = <0xe0680000 0x1000>;
+                                interrupts = <0 25 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                status = "disabled";
+                        };
+
+                        kbd@e0300000 {
+                                compatible = "st,spear300-kbd";
+                                reg = <0xe0300000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        i2c0: i2c@e0280000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "snps,designware-i2c";
+                                reg = <0xe0280000 0x1000>;
+                                interrupts = <0 41 0x4>;
+                                status = "disabled";
+                        };
+
+                        rtc@e0580000 {
+                                compatible = "st,spear-rtc";
+                                reg = <0xe0580000 0x1000>;
+                                interrupts = <0 36 0x4>;
+                                status = "disabled";
+                        };
+
+                        serial@e0000000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0xe0000000 0x1000>;
+                                interrupts = <0 36 0x4>;
+                                status = "disabled";
+                        };
+
+                        adc@e0080000 {
+                                compatible = "st,spear600-adc";
+                                reg = <0xe0080000 0x1000>;
+                                interrupts = <0 44 0x4>;
+                                status = "disabled";
+                        };
+
+                        timer@e0380000 {
+                                compatible = "st,spear-timer";
+                                reg = <0xe0380000 0x400>;
+                                interrupts = <0 37 0x4>;
+                        };
+
+                        timer@ec800600 {
+                                compatible = "arm,cortex-a9-twd-timer";
+                                reg = <0xec800600 0x20>;
+                                interrupts = <1 13 0x301>;
+                        };
+
+                        wdt@ec800620 {
+                                compatible = "arm,cortex-a9-twd-wdt";
+                                reg = <0xec800620 0x20>;
+                                status = "disabled";
+                        };
+
+                        thermal@e07008c4 {
+                                compatible = "st,thermal-spear1340";
+                                reg = <0xe07008c4 0x4>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/spear300-evb.dts b/arch/arm/boot/dts/spear300-evb.dts
new file mode 100644
index 000000000000..fc82b1a26458
--- /dev/null
+++ b/arch/arm/boot/dts/spear300-evb.dts
@@ -0,0 +1,246 @@
+/*
+ * DTS file for SPEAr300 Evaluation Baord
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "spear300.dtsi"
+
+/ {
+        model = "ST SPEAr300 Evaluation Board";
+        compatible = "st,spear300-evb", "st,spear300";
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        memory {
+                reg = <0 0x40000000>;
+        };
+
+        ahb {
+                pinmux@99000000 {
+                        st,pinmux-mode = <2>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&state_default>;
+
+                        state_default: pinmux {
+                                i2c0 {
+                                        st,pins = "i2c0_grp";
+                                        st,function = "i2c0";
+                                };
+                                ssp0 {
+                                        st,pins = "ssp0_grp";
+                                        st,function = "ssp0";
+                                };
+                                mii0 {
+                                        st,pins = "mii0_grp";
+                                        st,function = "mii0";
+                                };
+                                uart0 {
+                                        st,pins = "uart0_grp";
+                                        st,function = "uart0";
+                                };
+                                clcd {
+                                        st,pins = "clcd_pfmode_grp";
+                                        st,function = "clcd";
+                                };
+                                sdhci {
+                                        st,pins = "sdhci_4bit_grp";
+                                        st,function = "sdhci";
+                                };
+                                gpio1 {
+                                        st,pins = "gpio1_4_to_7_grp",
+                                                "gpio1_0_to_3_grp";
+                                        st,function = "gpio1";
+                                };
+                        };
+                };
+
+                clcd@60000000 {
+                        status = "okay";
+                };
+
+                dma@fc400000 {
+                        status = "okay";
+                };
+
+                fsmc: flash@94000000 {
+                        status = "okay";
+                };
+
+                gmac: eth@e0800000 {
+                        status = "okay";
+                };
+
+                sdhci@70000000 {
+                        int-gpio = <&gpio1 0 0>;
+                        power-gpio = <&gpio1 2 1>;
+                        status = "okay";
+                };
+
+                smi: flash@fc000000 {
+                        status = "okay";
+                        clock-rate=<50000000>;
+
+                        flash@f8000000 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                reg = <0xf8000000 0x800000>;
+                                st,smi-fast-mode;
+
+                                partition@0 {
+                                        label = "xloader";
+                                        reg = <0x0 0x10000>;
+                                };
+                                partition@10000 {
+                                        label = "u-boot";
+                                        reg = <0x10000 0x40000>;
+                                };
+                                partition@50000 {
+                                        label = "linux";
+                                        reg = <0x50000 0x2c0000>;
+                                };
+                                partition@310000 {
+                                        label = "rootfs";
+                                        reg = <0x310000 0x4f0000>;
+                                };
+                        };
+                };
+
+                spi0: spi@d0100000 {
+                        status = "okay";
+                };
+
+                ehci@e1800000 {
+                        status = "okay";
+                };
+
+                ohci@e1900000 {
+                        status = "okay";
+                };
+
+                ohci@e2100000 {
+                        status = "okay";
+                };
+
+                apb {
+                        gpio0: gpio@fc980000 {
+                               status = "okay";
+                        };
+
+                        gpio1: gpio@a9000000 {
+                               status = "okay";
+                        };
+
+                        i2c0: i2c@d0180000 {
+                               status = "okay";
+                        };
+
+                        kbd@a0000000 {
+                                linux,keymap = < 0x00000001
+                                                 0x00010002
+                                                 0x00020003
+                                                 0x00030004
+                                                 0x00040005
+                                                 0x00050006
+                                                 0x00060007
+                                                 0x00070008
+                                                 0x00080009
+                                                 0x0100000a
+                                                 0x0101000c
+                                                 0x0102000d
+                                                 0x0103000e
+                                                 0x0104000f
+                                                 0x01050010
+                                                 0x01060011
+                                                 0x01070012
+                                                 0x01080013
+                                                 0x02000014
+                                                 0x02010015
+                                                 0x02020016
+                                                 0x02030017
+                                                 0x02040018
+                                                 0x02050019
+                                                 0x0206001a
+                                                 0x0207001b
+                                                 0x0208001c
+                                                 0x0300001d
+                                                 0x0301001e
+                                                 0x0302001f
+                                                 0x03030020
+                                                 0x03040021
+                                                 0x03050022
+                                                 0x03060023
+                                                 0x03070024
+                                                 0x03080025
+                                                 0x04000026
+                                                 0x04010027
+                                                 0x04020028
+                                                 0x04030029
+                                                 0x0404002a
+                                                 0x0405002b
+                                                 0x0406002c
+                                                 0x0407002d
+                                                 0x0408002e
+                                                 0x0500002f
+                                                 0x05010030
+                                                 0x05020031
+                                                 0x05030032
+                                                 0x05040033
+                                                 0x05050034
+                                                 0x05060035
+                                                 0x05070036
+                                                 0x05080037
+                                                 0x06000038
+                                                 0x06010039
+                                                 0x0602003a
+                                                 0x0603003b
+                                                 0x0604003c
+                                                 0x0605003d
+                                                 0x0606003e
+                                                 0x0607003f
+                                                 0x06080040
+                                                 0x07000041
+                                                 0x07010042
+                                                 0x07020043
+                                                 0x07030044
+                                                 0x07040045
+                                                 0x07050046
+                                                 0x07060047
+                                                 0x07070048
+                                                 0x07080049
+                                                 0x0800004a
+                                                 0x0801004b
+                                                 0x0802004c
+                                                 0x0803004d
+                                                 0x0804004e
+                                                 0x0805004f
+                                                 0x08060050
+                                                 0x08070051
+                                                 0x08080052 >;
+                               autorepeat;
+                               st,mode = <0>;
+                               status = "okay";
+                        };
+
+                        rtc@fc900000 {
+                               status = "okay";
+                        };
+
+                        serial@d0000000 {
+                               status = "okay";
+                        };
+
+                        wdt@fc880000 {
+                               status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/spear300.dtsi b/arch/arm/boot/dts/spear300.dtsi
new file mode 100644
index 000000000000..01c5e358fdb2
--- /dev/null
+++ b/arch/arm/boot/dts/spear300.dtsi
@@ -0,0 +1,77 @@
+/*
+ * DTS file for SPEAr300 SoC
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "spear3xx.dtsi"
+
+/ {
+        ahb {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges = <0x60000000 0x60000000 0x50000000
+                          0xd0000000 0xd0000000 0x30000000>;
+
+                pinmux@99000000 {
+                        compatible = "st,spear300-pinmux";
+                        reg = <0x99000000 0x1000>;
+                };
+
+                clcd@60000000 {
+                        compatible = "arm,clcd-pl110", "arm,primecell";
+                        reg = <0x60000000 0x1000>;
+                        interrupts = <30>;
+                        status = "disabled";
+                };
+
+                fsmc: flash@94000000 {
+                        compatible = "st,spear600-fsmc-nand";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x94000000 0x1000        /* FSMC Register */
+                               0x80000000 0x0010>;      /* NAND Base */
+                        reg-names = "fsmc_regs", "nand_data";
+                        st,ale-off = <0x20000>;
+                        st,cle-off = <0x10000>;
+                        status = "disabled";
+                };
+
+                sdhci@70000000 {
+                        compatible = "st,sdhci-spear";
+                        reg = <0x70000000 0x100>;
+                        interrupts = <1>;
+                        status = "disabled";
+                };
+
+                apb {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "simple-bus";
+                        ranges = <0xa0000000 0xa0000000 0x10000000
+                                  0xd0000000 0xd0000000 0x30000000>;
+
+                        gpio1: gpio@a9000000 {
+                                #gpio-cells = <2>;
+                                compatible = "arm,pl061", "arm,primecell";
+                                gpio-controller;
+                                reg = <0xa9000000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        kbd@a0000000 {
+                                compatible = "st,spear300-kbd";
+                                reg = <0xa0000000 0x1000>;
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/spear310-evb.dts b/arch/arm/boot/dts/spear310-evb.dts
new file mode 100644
index 000000000000..dc5e2d445a93
--- /dev/null
+++ b/arch/arm/boot/dts/spear310-evb.dts
@@ -0,0 +1,188 @@
+/*
+ * DTS file for SPEAr310 Evaluation Baord
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "spear310.dtsi"
+
+/ {
+        model = "ST SPEAr310 Evaluation Board";
+        compatible = "st,spear310-evb", "st,spear310";
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        memory {
+                reg = <0 0x40000000>;
+        };
+
+        ahb {
+                pinmux@b4000000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&state_default>;
+
+                        state_default: pinmux {
+                                gpio0 {
+                                        st,pins = "gpio0_pin0_grp",
+                                                "gpio0_pin1_grp",
+                                                "gpio0_pin2_grp",
+                                                "gpio0_pin3_grp",
+                                                "gpio0_pin4_grp",
+                                                "gpio0_pin5_grp";
+                                        st,function = "gpio0";
+                                };
+                                i2c0 {
+                                        st,pins = "i2c0_grp";
+                                        st,function = "i2c0";
+                                };
+                                mii0 {
+                                        st,pins = "mii0_grp";
+                                        st,function = "mii0";
+                                };
+                                ssp0 {
+                                        st,pins = "ssp0_grp";
+                                        st,function = "ssp0";
+                                };
+                                uart0 {
+                                        st,pins = "uart0_grp";
+                                        st,function = "uart0";
+                                };
+                                emi {
+                                        st,pins = "emi_cs_0_to_5_grp";
+                                        st,function = "emi";
+                                };
+                                fsmc {
+                                        st,pins = "fsmc_grp";
+                                        st,function = "fsmc";
+                                };
+                                uart1 {
+                                        st,pins = "uart1_grp";
+                                        st,function = "uart1";
+                                };
+                                uart2 {
+                                        st,pins = "uart2_grp";
+                                        st,function = "uart2";
+                                };
+                                uart3 {
+                                        st,pins = "uart3_grp";
+                                        st,function = "uart3";
+                                };
+                                uart4 {
+                                        st,pins = "uart4_grp";
+                                        st,function = "uart4";
+                                };
+                                uart5 {
+                                        st,pins = "uart5_grp";
+                                        st,function = "uart5";
+                                };
+                        };
+                };
+
+                dma@fc400000 {
+                        status = "okay";
+                };
+
+                fsmc: flash@44000000 {
+                        status = "okay";
+                };
+
+                gmac: eth@e0800000 {
+                        status = "okay";
+                };
+
+                smi: flash@fc000000 {
+                        status = "okay";
+                        clock-rate=<50000000>;
+
+                        flash@f8000000 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                reg = <0xf8000000 0x800000>;
+                                st,smi-fast-mode;
+
+                                partition@0 {
+                                        label = "xloader";
+                                        reg = <0x0 0x10000>;
+                                };
+                                partition@10000 {
+                                        label = "u-boot";
+                                        reg = <0x10000 0x40000>;
+                                };
+                                partition@50000 {
+                                        label = "linux";
+                                        reg = <0x50000 0x2c0000>;
+                                };
+                                partition@310000 {
+                                        label = "rootfs";
+                                        reg = <0x310000 0x4f0000>;
+                                };
+                        };
+                };
+
+                spi0: spi@d0100000 {
+                        status = "okay";
+                };
+
+                ehci@e1800000 {
+                        status = "okay";
+                };
+
+                ohci@e1900000 {
+                        status = "okay";
+                };
+
+                ohci@e2100000 {
+                        status = "okay";
+                };
+
+                apb {
+                        gpio0: gpio@fc980000 {
+                               status = "okay";
+                        };
+
+                        i2c0: i2c@d0180000 {
+                               status = "okay";
+                        };
+
+                        rtc@fc900000 {
+                               status = "okay";
+                        };
+
+                        serial@d0000000 {
+                               status = "okay";
+                        };
+
+                        serial@b2000000 {
+                               status = "okay";
+                        };
+
+                        serial@b2080000 {
+                               status = "okay";
+                        };
+
+                        serial@b2100000 {
+                               status = "okay";
+                        };
+
+                        serial@b2180000 {
+                               status = "okay";
+                        };
+
+                        serial@b2200000 {
+                               status = "okay";
+                        };
+
+                        wdt@fc880000 {
+                               status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/spear310.dtsi b/arch/arm/boot/dts/spear310.dtsi
new file mode 100644
index 000000000000..e47081c494d9
--- /dev/null
+++ b/arch/arm/boot/dts/spear310.dtsi
@@ -0,0 +1,80 @@
+/*
+ * DTS file for SPEAr310 SoC
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "spear3xx.dtsi"
+
+/ {
+        ahb {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges = <0x40000000 0x40000000 0x10000000
+                          0xb0000000 0xb0000000 0x10000000
+                          0xd0000000 0xd0000000 0x30000000>;
+
+                pinmux@b4000000 {
+                        compatible = "st,spear310-pinmux";
+                        reg = <0xb4000000 0x1000>;
+                };
+
+                fsmc: flash@44000000 {
+                        compatible = "st,spear600-fsmc-nand";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x44000000 0x1000        /* FSMC Register */
+                               0x40000000 0x0010>;      /* NAND Base */
+                        reg-names = "fsmc_regs", "nand_data";
+                        st,ale-off = <0x10000>;
+                        st,cle-off = <0x20000>;
+                        status = "disabled";
+                };
+
+                apb {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "simple-bus";
+                        ranges = <0xb0000000 0xb0000000 0x10000000
+                                  0xd0000000 0xd0000000 0x30000000>;
+
+                        serial@b2000000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0xb2000000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        serial@b2080000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0xb2080000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        serial@b2100000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0xb2100000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        serial@b2180000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0xb2180000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        serial@b2200000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0xb2200000 0x1000>;
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/spear320-evb.dts b/arch/arm/boot/dts/spear320-evb.dts
new file mode 100644
index 000000000000..6308fa3bec1e
--- /dev/null
+++ b/arch/arm/boot/dts/spear320-evb.dts
@@ -0,0 +1,198 @@
+/*
+ * DTS file for SPEAr320 Evaluation Baord
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "spear320.dtsi"
+
+/ {
+        model = "ST SPEAr300 Evaluation Board";
+        compatible = "st,spear300-evb", "st,spear300";
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        memory {
+                reg = <0 0x40000000>;
+        };
+
+        ahb {
+                pinmux@b3000000 {
+                        st,pinmux-mode = <3>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&state_default>;
+
+                        state_default: pinmux {
+                                i2c0 {
+                                        st,pins = "i2c0_grp";
+                                        st,function = "i2c0";
+                                };
+                                mii0 {
+                                        st,pins = "mii0_grp";
+                                        st,function = "mii0";
+                                };
+                                ssp0 {
+                                        st,pins = "ssp0_grp";
+                                        st,function = "ssp0";
+                                };
+                                uart0 {
+                                        st,pins = "uart0_grp";
+                                        st,function = "uart0";
+                                };
+                                sdhci {
+                                        st,pins = "sdhci_cd_51_grp";
+                                        st,function = "sdhci";
+                                };
+                                i2s {
+                                        st,pins = "i2s_grp";
+                                        st,function = "i2s";
+                                };
+                                uart1 {
+                                        st,pins = "uart1_grp";
+                                        st,function = "uart1";
+                                };
+                                uart2 {
+                                        st,pins = "uart2_grp";
+                                        st,function = "uart2";
+                                };
+                                can0 {
+                                        st,pins = "can0_grp";
+                                        st,function = "can0";
+                                };
+                                can1 {
+                                        st,pins = "can1_grp";
+                                        st,function = "can1";
+                                };
+                                mii2 {
+                                        st,pins = "mii2_grp";
+                                        st,function = "mii2";
+                                };
+                                pwm0_1 {
+                                        st,pins = "pwm0_1_pin_14_15_grp";
+                                        st,function = "pwm0_1";
+                                };
+                                pwm2 {
+                                        st,pins = "pwm2_pin_13_grp";
+                                        st,function = "pwm2";
+                                };
+                        };
+                };
+
+                clcd@90000000 {
+                        status = "okay";
+                };
+
+                dma@fc400000 {
+                        status = "okay";
+                };
+
+                fsmc: flash@4c000000 {
+                        status = "okay";
+                };
+
+                gmac: eth@e0800000 {
+                        status = "okay";
+                };
+
+                sdhci@70000000 {
+                        power-gpio = <&gpio0 2 1>;
+                        power_always_enb;
+                        status = "okay";
+                };
+
+                smi: flash@fc000000 {
+                        status = "okay";
+                        clock-rate=<50000000>;
+
+                        flash@f8000000 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                reg = <0xf8000000 0x800000>;
+                                st,smi-fast-mode;
+
+                                partition@0 {
+                                        label = "xloader";
+                                        reg = <0x0 0x10000>;
+                                };
+                                partition@10000 {
+                                        label = "u-boot";
+                                        reg = <0x10000 0x40000>;
+                                };
+                                partition@50000 {
+                                        label = "linux";
+                                        reg = <0x50000 0x2c0000>;
+                                };
+                                partition@310000 {
+                                        label = "rootfs";
+                                        reg = <0x310000 0x4f0000>;
+                                };
+                        };
+                };
+
+                spi0: spi@d0100000 {
+                        status = "okay";
+                };
+
+                spi1: spi@a5000000 {
+                        status = "okay";
+                };
+
+                spi2: spi@a6000000 {
+                        status = "okay";
+                };
+
+                ehci@e1800000 {
+                        status = "okay";
+                };
+
+                ohci@e1900000 {
+                        status = "okay";
+                };
+
+                ohci@e2100000 {
+                        status = "okay";
+                };
+
+                apb {
+                        gpio0: gpio@fc980000 {
+                               status = "okay";
+                        };
+
+                        i2c0: i2c@d0180000 {
+                               status = "okay";
+                        };
+
+                        i2c1: i2c@a7000000 {
+                               status = "okay";
+                        };
+
+                        rtc@fc900000 {
+                               status = "okay";
+                        };
+
+                        serial@d0000000 {
+                               status = "okay";
+                        };
+
+                        serial@a3000000 {
+                               status = "okay";
+                        };
+
+                        serial@a4000000 {
+                               status = "okay";
+                        };
+
+                        wdt@fc880000 {
+                               status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/spear320.dtsi b/arch/arm/boot/dts/spear320.dtsi
new file mode 100644
index 000000000000..5372ca399b1f
--- /dev/null
+++ b/arch/arm/boot/dts/spear320.dtsi
@@ -0,0 +1,95 @@
+/*
+ * DTS file for SPEAr320 SoC
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "spear3xx.dtsi"
+
+/ {
+        ahb {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges = <0x40000000 0x40000000 0x80000000
+                          0xd0000000 0xd0000000 0x30000000>;
+
+                pinmux@b3000000 {
+                        compatible = "st,spear320-pinmux";
+                        reg = <0xb3000000 0x1000>;
+                };
+
+                clcd@90000000 {
+                        compatible = "arm,clcd-pl110", "arm,primecell";
+                        reg = <0x90000000 0x1000>;
+                        interrupts = <33>;
+                        status = "disabled";
+                };
+
+                fsmc: flash@4c000000 {
+                        compatible = "st,spear600-fsmc-nand";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x4c000000 0x1000        /* FSMC Register */
+                               0x50000000 0x0010>;      /* NAND Base */
+                        reg-names = "fsmc_regs", "nand_data";
+                        st,ale-off = <0x20000>;
+                        st,cle-off = <0x10000>;
+                        status = "disabled";
+                };
+
+                sdhci@70000000 {
+                        compatible = "st,sdhci-spear";
+                        reg = <0x70000000 0x100>;
+                        interrupts = <29>;
+                        status = "disabled";
+                };
+
+                spi1: spi@a5000000 {
+                        compatible = "arm,pl022", "arm,primecell";
+                        reg = <0xa5000000 0x1000>;
+                        status = "disabled";
+                };
+
+                spi2: spi@a6000000 {
+                        compatible = "arm,pl022", "arm,primecell";
+                        reg = <0xa6000000 0x1000>;
+                        status = "disabled";
+                };
+
+                apb {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "simple-bus";
+                        ranges = <0xa0000000 0xa0000000 0x10000000
+                                  0xd0000000 0xd0000000 0x30000000>;
+
+                        i2c1: i2c@a7000000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "snps,designware-i2c";
+                                reg = <0xa7000000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        serial@a3000000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0xa3000000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        serial@a4000000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0xa4000000 0x1000>;
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/spear3xx.dtsi b/arch/arm/boot/dts/spear3xx.dtsi
new file mode 100644
index 000000000000..91072553963f
--- /dev/null
+++ b/arch/arm/boot/dts/spear3xx.dtsi
@@ -0,0 +1,150 @@
+/*
+ * DTS file for all SPEAr3xx SoCs
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        interrupt-parent = <&vic>;
+
+        cpus {
+                cpu@0 {
+                        compatible = "arm,arm926ejs";
+                };
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0 0x40000000>;
+        };
+
+        ahb {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges = <0xd0000000 0xd0000000 0x30000000>;
+
+                vic: interrupt-controller@f1100000 {
+                        compatible = "arm,pl190-vic";
+                        interrupt-controller;
+                        reg = <0xf1100000 0x1000>;
+                        #interrupt-cells = <1>;
+                };
+
+                dma@fc400000 {
+                        compatible = "arm,pl080", "arm,primecell";
+                        reg = <0xfc400000 0x1000>;
+                        interrupt-parent = <&vic>;
+                        interrupts = <8>;
+                        status = "disabled";
+                };
+
+                gmac: eth@e0800000 {
+                        compatible = "st,spear600-gmac";
+                        reg = <0xe0800000 0x8000>;
+                        interrupts = <23 22>;
+                        interrupt-names = "macirq", "eth_wake_irq";
+                        status = "disabled";
+                };
+
+                smi: flash@fc000000 {
+                        compatible = "st,spear600-smi";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0xfc000000 0x1000>;
+                        interrupts = <9>;
+                        status = "disabled";
+                };
+
+                spi0: spi@d0100000 {
+                        compatible = "arm,pl022", "arm,primecell";
+                        reg = <0xd0100000 0x1000>;
+                        interrupts = <20>;
+                        status = "disabled";
+                };
+
+                ehci@e1800000 {
+                        compatible = "st,spear600-ehci", "usb-ehci";
+                        reg = <0xe1800000 0x1000>;
+                        interrupts = <26>;
+                        status = "disabled";
+                };
+
+                ohci@e1900000 {
+                        compatible = "st,spear600-ohci", "usb-ohci";
+                        reg = <0xe1900000 0x1000>;
+                        interrupts = <25>;
+                        status = "disabled";
+                };
+
+                ohci@e2100000 {
+                        compatible = "st,spear600-ohci", "usb-ohci";
+                        reg = <0xe2100000 0x1000>;
+                        interrupts = <27>;
+                        status = "disabled";
+                };
+
+                apb {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "simple-bus";
+                        ranges = <0xd0000000 0xd0000000 0x30000000>;
+
+                        gpio0: gpio@fc980000 {
+                                compatible = "arm,pl061", "arm,primecell";
+                                reg = <0xfc980000 0x1000>;
+                                interrupts = <11>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                status = "disabled";
+                        };
+
+                        i2c0: i2c@d0180000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "snps,designware-i2c";
+                                reg = <0xd0180000 0x1000>;
+                                interrupts = <21>;
+                                status = "disabled";
+                        };
+
+                        rtc@fc900000 {
+                                compatible = "st,spear-rtc";
+                                reg = <0xfc900000 0x1000>;
+                                interrupts = <10>;
+                                status = "disabled";
+                        };
+
+                        serial@d0000000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0xd0000000 0x1000>;
+                                interrupts = <19>;
+                                status = "disabled";
+                        };
+
+                        wdt@fc880000 {
+                                compatible = "arm,sp805", "arm,primecell";
+                                reg = <0xfc880000 0x1000>;
+                                interrupts = <12>;
+                                status = "disabled";
+                        };
+
+                        timer@f0000000 {
+                                compatible = "st,spear-timer";
+                                reg = <0xf0000000 0x400>;
+                                interrupts = <2>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/spear600-evb.dts b/arch/arm/boot/dts/spear600-evb.dts
index 636292e18c90..1119c22c9a82 100644
--- a/arch/arm/boot/dts/spear600-evb.dts
+++ b/arch/arm/boot/dts/spear600-evb.dts
@@ -24,11 +24,44 @@
         };
 
         ahb {
+                dma@fc400000 {
+                        status = "okay";
+                };
+
                 gmac: ethernet@e0800000 {
                         phy-mode = "gmii";
                         status = "okay";
                 };
 
+                smi: flash@fc000000 {
+                        status = "okay";
+                        clock-rate=<50000000>;
+
+                        flash@f8000000 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                reg = <0xf8000000 0x800000>;
+                                st,smi-fast-mode;
+
+                                partition@0 {
+                                        label = "xloader";
+                                        reg = <0x0 0x10000>;
+                                };
+                                partition@10000 {
+                                        label = "u-boot";
+                                        reg = <0x10000 0x40000>;
+                                };
+                                partition@50000 {
+                                        label = "linux";
+                                        reg = <0x50000 0x2c0000>;
+                                };
+                                partition@310000 {
+                                        label = "rootfs";
+                                        reg = <0x310000 0x4f0000>;
+                                };
+                        };
+                };
+
                 apb {
                         serial@d0000000 {
                                 status = "okay";
diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi
index ebe0885a2b98..089f0a42c50e 100644
--- a/arch/arm/boot/dts/spear600.dtsi
+++ b/arch/arm/boot/dts/spear600.dtsi
@@ -45,6 +45,14 @@
                         #interrupt-cells = <1>;
                 };
 
+                dma@fc400000 {
+                        compatible = "arm,pl080", "arm,primecell";
+                        reg = <0xfc400000 0x1000>;
+                        interrupt-parent = <&vic1>;
+                        interrupts = <10>;
+                        status = "disabled";
+                };
+
                 gmac: ethernet@e0800000 {
                         compatible = "st,spear600-gmac";
                         reg = <0xe0800000 0x8000>;
@@ -169,6 +177,12 @@
                                 interrupts = <28>;
                                 status = "disabled";
                         };
+
+                        timer@f0000000 {
+                                compatible = "st,spear-timer";
+                                reg = <0xf0000000 0x400>;
+                                interrupts = <16>;
+                        };
                 };
         };
 };
diff --git a/arch/arm/configs/spear13xx_defconfig b/arch/arm/configs/spear13xx_defconfig
new file mode 100644
index 000000000000..1fdb82694ca2
--- /dev/null
+++ b/arch/arm/configs/spear13xx_defconfig
@@ -0,0 +1,95 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_PLAT_SPEAR=y
+CONFIG_ARCH_SPEAR13XX=y
+CONFIG_MACH_SPEAR1310=y
+CONFIG_MACH_SPEAR1340=y
+# CONFIG_SWP_EMULATE is not set
+CONFIG_SMP=y
+# CONFIG_SMP_ON_UP is not set
+# CONFIG_ARM_CPU_TOPOLOGY is not set
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_BINFMT_MISC=y
+CONFIG_NET=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_OF_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_FSMC=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_ATA=y
+# CONFIG_SATA_PMP is not set
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_PATA_ARASAN_CF=y
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+CONFIG_STMMAC_ETH=y
+# CONFIG_WLAN is not set
+CONFIG_INPUT_FF_MEMLESS=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_SPEAR=y
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_RAW_DRIVER=y
+CONFIG_MAX_RAW_DEVS=8192
+CONFIG_I2C=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_SPI=y
+CONFIG_SPI_PL022=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_PL061=y
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_MPCORE_WATCHDOG=y
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB=y
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SPEAR=y
+CONFIG_RTC_CLASS=y
+CONFIG_DMADEVICES=y
+CONFIG_DW_DMAC=y
+CONFIG_DMATEST=m
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_AUTOFS4_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ASCII=m
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_SPINLOCK=y
+CONFIG_DEBUG_INFO=y
diff --git a/arch/arm/configs/spear3xx_defconfig b/arch/arm/configs/spear3xx_defconfig
index fea7e1f026a3..865980c5f212 100644
--- a/arch/arm/configs/spear3xx_defconfig
+++ b/arch/arm/configs/spear3xx_defconfig
@@ -2,33 +2,70 @@ CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_BLK_DEV_INITRD=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODVERSIONS=y
+CONFIG_PARTITION_ADVANCED=y
 CONFIG_PLAT_SPEAR=y
-CONFIG_BOARD_SPEAR300_EVB=y
-CONFIG_BOARD_SPEAR310_EVB=y
-CONFIG_BOARD_SPEAR320_EVB=y
+CONFIG_MACH_SPEAR300=y
+CONFIG_MACH_SPEAR310=y
+CONFIG_MACH_SPEAR320=y
 CONFIG_BINFMT_MISC=y
+CONFIG_NET=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_OF_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_FSMC=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+CONFIG_STMMAC_ETH=y
+# CONFIG_WLAN is not set
 CONFIG_INPUT_FF_MEMLESS=y
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_SPEAR=y
 # CONFIG_INPUT_MOUSE is not set
+# CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
 # CONFIG_HW_RANDOM is not set
 CONFIG_RAW_DRIVER=y
 CONFIG_MAX_RAW_DEVS=8192
+CONFIG_I2C=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_SPI=y
+CONFIG_SPI_PL022=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_PL061=y
 # CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_ARM_SP805_WATCHDOG=y
+CONFIG_FB=y
+CONFIG_FB_ARMCLCD=y
 # CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
+CONFIG_USB=y
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SPEAR=y
+CONFIG_RTC_CLASS=y
+CONFIG_DMADEVICES=y
+CONFIG_AMBA_PL08X=y
+CONFIG_DMATEST=m
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_SECURITY=y
@@ -39,8 +76,7 @@ CONFIG_MSDOS_FS=m
 CONFIG_VFAT_FS=m
 CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
 CONFIG_TMPFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS=y
+CONFIG_JFFS2_FS=y
 CONFIG_NLS_DEFAULT="utf8"
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ASCII=m
@@ -48,6 +84,4 @@ CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_FS=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_SPINLOCK=y
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
 CONFIG_DEBUG_INFO=y
-# CONFIG_CRC32 is not set
diff --git a/arch/arm/configs/spear6xx_defconfig b/arch/arm/configs/spear6xx_defconfig
index cef2e836afd2..a2a1265f86b6 100644
--- a/arch/arm/configs/spear6xx_defconfig
+++ b/arch/arm/configs/spear6xx_defconfig
@@ -2,29 +2,60 @@ CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_BLK_DEV_INITRD=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODVERSIONS=y
+CONFIG_PARTITION_ADVANCED=y
 CONFIG_PLAT_SPEAR=y
 CONFIG_ARCH_SPEAR6XX=y
-CONFIG_BOARD_SPEAR600_EVB=y
 CONFIG_BINFMT_MISC=y
+CONFIG_NET=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_OF_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_FSMC=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+CONFIG_STMMAC_ETH=y
+# CONFIG_WLAN is not set
 CONFIG_INPUT_FF_MEMLESS=y
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
 CONFIG_RAW_DRIVER=y
 CONFIG_MAX_RAW_DEVS=8192
+CONFIG_I2C=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_SPI=y
+CONFIG_SPI_PL022=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_PL061=y
 # CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_ARM_SP805_WATCHDOG=y
 # CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_RTC_CLASS=y
+CONFIG_DMADEVICES=y
+CONFIG_AMBA_PL08X=y
+CONFIG_DMATEST=m
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_SECURITY=y
@@ -35,8 +66,7 @@ CONFIG_MSDOS_FS=m
 CONFIG_VFAT_FS=m
 CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
 CONFIG_TMPFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS=y
+CONFIG_JFFS2_FS=y
 CONFIG_NLS_DEFAULT="utf8"
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ASCII=m
@@ -44,6 +74,4 @@ CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_FS=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_SPINLOCK=y
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
 CONFIG_DEBUG_INFO=y
-# CONFIG_CRC32 is not set
diff --git a/arch/arm/mach-spear13xx/Kconfig b/arch/arm/mach-spear13xx/Kconfig
new file mode 100644
index 000000000000..eaadc66d96b3
--- /dev/null
+++ b/arch/arm/mach-spear13xx/Kconfig
@@ -0,0 +1,20 @@
+#
+# SPEAr13XX Machine configuration file
+#
+
+if ARCH_SPEAR13XX
+
+menu "SPEAr13xx Implementations"
+config MACH_SPEAR1310
+        bool "SPEAr1310 Machine support with Device Tree"
+        select PINCTRL_SPEAR1310
+        help
+          Supports ST SPEAr1310 machine configured via the device-tree
+
+config MACH_SPEAR1340
+        bool "SPEAr1340 Machine support with Device Tree"
+        select PINCTRL_SPEAR1340
+        help
+          Supports ST SPEAr1340 machine configured via the device-tree
+endmenu
+endif #ARCH_SPEAR13XX
diff --git a/arch/arm/mach-spear13xx/Makefile b/arch/arm/mach-spear13xx/Makefile
new file mode 100644
index 000000000000..3435ea78c15d
--- /dev/null
+++ b/arch/arm/mach-spear13xx/Makefile
@@ -0,0 +1,10 @@
+#
+# Makefile for SPEAr13XX machine series
+#
+
+obj-$(CONFIG_SMP)               += headsmp.o platsmp.o
+obj-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
+
+obj-$(CONFIG_ARCH_SPEAR13XX)    += spear13xx.o
+obj-$(CONFIG_MACH_SPEAR1310)    += spear1310.o
+obj-$(CONFIG_MACH_SPEAR1340)    += spear1340.o
diff --git a/arch/arm/mach-spear13xx/Makefile.boot b/arch/arm/mach-spear13xx/Makefile.boot
new file mode 100644
index 000000000000..403efd7e6d27
--- /dev/null
+++ b/arch/arm/mach-spear13xx/Makefile.boot
@@ -0,0 +1,6 @@
+zreladdr-y      += 0x00008000
+params_phys-y   := 0x00000100
+initrd_phys-y   := 0x00800000
+
+dtb-$(CONFIG_MACH_SPEAR1310)    += spear1310-evb.dtb
+dtb-$(CONFIG_MACH_SPEAR1340)    += spear1340-evb.dtb
diff --git a/arch/arm/mach-spear13xx/headsmp.S b/arch/arm/mach-spear13xx/headsmp.S
new file mode 100644
index 000000000000..ed85473a047f
--- /dev/null
+++ b/arch/arm/mach-spear13xx/headsmp.S
@@ -0,0 +1,47 @@
+/*
+ * arch/arm/mach-spear13XX/headsmp.S
+ *
+ * Picked from realview
+ * Copyright (c) 2012 ST Microelectronics Limited
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+        __INIT
+
+/*
+ * spear13xx specific entry point for secondary CPUs. This provides
+ * a "holding pen" into which all secondary cores are held until we're
+ * ready for them to initialise.
+ */
+ENTRY(spear13xx_secondary_startup)
+        mrc     p15, 0, r0, c0, c0, 5
+        and     r0, r0, #15
+        adr     r4, 1f
+        ldmia   r4, {r5, r6}
+        sub     r4, r4, r5
+        add     r6, r6, r4
+pen:    ldr     r7, [r6]
+        cmp     r7, r0
+        bne     pen
+
+        /* re-enable coherency */
+        mrc     p15, 0, r0, c1, c0, 1
+        orr     r0, r0, #(1 << 6) | (1 << 0)
+        mcr     p15, 0, r0, c1, c0, 1
+        /*
+         * we've been released from the holding pen: secondary_stack
+         * should now contain the SVC stack for this core
+         */
+        b       secondary_startup
+
+        .align
+1:      .long   .
+        .long   pen_release
+ENDPROC(spear13xx_secondary_startup)
diff --git a/arch/arm/mach-spear13xx/hotplug.c b/arch/arm/mach-spear13xx/hotplug.c
new file mode 100644
index 000000000000..5c6867b46d09
--- /dev/null
+++ b/arch/arm/mach-spear13xx/hotplug.c
@@ -0,0 +1,119 @@
+/*
+ * linux/arch/arm/mach-spear13xx/hotplug.c
+ *
+ * Copyright (C) 2012 ST Microelectronics Ltd.
+ * Deepak Sikri <deepak.sikri@st.com>
+ *
+ * based upon linux/arch/arm/mach-realview/hotplug.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/smp.h>
+#include <asm/cacheflush.h>
+#include <asm/cp15.h>
+#include <asm/smp_plat.h>
+
+extern volatile int pen_release;
+
+static inline void cpu_enter_lowpower(void)
+{
+        unsigned int v;
+
+        flush_cache_all();
+        asm volatile(
+        "       mcr     p15, 0, %1, c7, c5, 0\n"
+        "       dsb\n"
+        /*
+         * Turn off coherency
+         */
+        "       mrc     p15, 0, %0, c1, c0, 1\n"
+        "       bic     %0, %0, #0x20\n"
+        "       mcr     p15, 0, %0, c1, c0, 1\n"
+        "       mrc     p15, 0, %0, c1, c0, 0\n"
+        "       bic     %0, %0, %2\n"
+        "       mcr     p15, 0, %0, c1, c0, 0\n"
+        : "=&r" (v)
+        : "r" (0), "Ir" (CR_C)
+        : "cc", "memory");
+}
+
+static inline void cpu_leave_lowpower(void)
+{
+        unsigned int v;
+
+        asm volatile("mrc       p15, 0, %0, c1, c0, 0\n"
+        "       orr     %0, %0, %1\n"
+        "       mcr     p15, 0, %0, c1, c0, 0\n"
+        "       mrc     p15, 0, %0, c1, c0, 1\n"
+        "       orr     %0, %0, #0x20\n"
+        "       mcr     p15, 0, %0, c1, c0, 1\n"
+        : "=&r" (v)
+        : "Ir" (CR_C)
+        : "cc");
+}
+
+static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
+{
+        for (;;) {
+                wfi();
+
+                if (pen_release == cpu) {
+                        /*
+                         * OK, proper wakeup, we're done
+                         */
+                        break;
+                }
+
+                /*
+                 * Getting here, means that we have come out of WFI without
+                 * having been woken up - this shouldn't happen
+                 *
+                 * Just note it happening - when we're woken, we can report
+                 * its occurrence.
+                 */
+                (*spurious)++;
+        }
+}
+
+int platform_cpu_kill(unsigned int cpu)
+{
+        return 1;
+}
+
+/*
+ * platform-specific code to shutdown a CPU
+ *
+ * Called with IRQs disabled
+ */
+void __cpuinit platform_cpu_die(unsigned int cpu)
+{
+        int spurious = 0;
+
+        /*
+         * we're ready for shutdown now, so do it
+         */
+        cpu_enter_lowpower();
+        platform_do_lowpower(cpu, &spurious);
+
+        /*
+         * bring this CPU back into the world of cache
+         * coherency, and then restore interrupts
+         */
+        cpu_leave_lowpower();
+
+        if (spurious)
+                pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
+}
+
+int platform_cpu_disable(unsigned int cpu)
+{
+        /*
+         * we don't allow CPU 0 to be shutdown (it is still too special
+         * e.g. clock tick interrupts)
+         */
+        return cpu == 0 ? -EPERM : 0;
+}
diff --git a/arch/arm/mach-spear13xx/include/mach/debug-macro.S b/arch/arm/mach-spear13xx/include/mach/debug-macro.S
new file mode 100644
index 000000000000..ea1564609bd4
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/debug-macro.S
@@ -0,0 +1,14 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/debug-macro.S
+ *
+ * Debugging macro include header spear13xx machine family
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-spear13xx/include/mach/dma.h b/arch/arm/mach-spear13xx/include/mach/dma.h
new file mode 100644
index 000000000000..383ab04dc6c9
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/dma.h
@@ -0,0 +1,128 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/dma.h
+ *
+ * DMA information for SPEAr13xx machine family
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_DMA_H
+#define __MACH_DMA_H
+
+/* request id of all the peripherals */
+enum dma_master_info {
+        /* Accessible from only one master */
+        DMA_MASTER_MCIF = 0,
+        DMA_MASTER_FSMC = 1,
+        /* Accessible from both 0 & 1 */
+        DMA_MASTER_MEMORY = 0,
+        DMA_MASTER_ADC = 0,
+        DMA_MASTER_UART0 = 0,
+        DMA_MASTER_SSP0 = 0,
+        DMA_MASTER_I2C0 = 0,
+
+#ifdef CONFIG_MACH_SPEAR1310
+        /* Accessible from only one master */
+        SPEAR1310_DMA_MASTER_JPEG = 1,
+
+        /* Accessible from both 0 & 1 */
+        SPEAR1310_DMA_MASTER_I2S = 0,
+        SPEAR1310_DMA_MASTER_UART1 = 0,
+        SPEAR1310_DMA_MASTER_UART2 = 0,
+        SPEAR1310_DMA_MASTER_UART3 = 0,
+        SPEAR1310_DMA_MASTER_UART4 = 0,
+        SPEAR1310_DMA_MASTER_UART5 = 0,
+        SPEAR1310_DMA_MASTER_I2C1 = 0,
+        SPEAR1310_DMA_MASTER_I2C2 = 0,
+        SPEAR1310_DMA_MASTER_I2C3 = 0,
+        SPEAR1310_DMA_MASTER_I2C4 = 0,
+        SPEAR1310_DMA_MASTER_I2C5 = 0,
+        SPEAR1310_DMA_MASTER_I2C6 = 0,
+        SPEAR1310_DMA_MASTER_I2C7 = 0,
+        SPEAR1310_DMA_MASTER_SSP1 = 0,
+#endif
+
+#ifdef CONFIG_MACH_SPEAR1340
+        /* Accessible from only one master */
+        SPEAR1340_DMA_MASTER_I2S_PLAY = 1,
+        SPEAR1340_DMA_MASTER_I2S_REC = 1,
+        SPEAR1340_DMA_MASTER_I2C1 = 1,
+        SPEAR1340_DMA_MASTER_UART1 = 1,
+
+        /* following are accessible from both master 0 & 1 */
+        SPEAR1340_DMA_MASTER_SPDIF = 0,
+        SPEAR1340_DMA_MASTER_CAM = 1,
+        SPEAR1340_DMA_MASTER_VIDEO_IN = 0,
+        SPEAR1340_DMA_MASTER_MALI = 0,
+#endif
+};
+
+enum request_id {
+        DMA_REQ_ADC = 0,
+        DMA_REQ_SSP0_TX = 4,
+        DMA_REQ_SSP0_RX = 5,
+        DMA_REQ_UART0_TX = 6,
+        DMA_REQ_UART0_RX = 7,
+        DMA_REQ_I2C0_TX = 8,
+        DMA_REQ_I2C0_RX = 9,
+
+#ifdef CONFIG_MACH_SPEAR1310
+        SPEAR1310_DMA_REQ_FROM_JPEG = 2,
+        SPEAR1310_DMA_REQ_TO_JPEG = 3,
+        SPEAR1310_DMA_REQ_I2S_TX = 10,
+        SPEAR1310_DMA_REQ_I2S_RX = 11,
+
+        SPEAR1310_DMA_REQ_I2C1_RX = 0,
+        SPEAR1310_DMA_REQ_I2C1_TX = 1,
+        SPEAR1310_DMA_REQ_I2C2_RX = 2,
+        SPEAR1310_DMA_REQ_I2C2_TX = 3,
+        SPEAR1310_DMA_REQ_I2C3_RX = 4,
+        SPEAR1310_DMA_REQ_I2C3_TX = 5,
+        SPEAR1310_DMA_REQ_I2C4_RX = 6,
+        SPEAR1310_DMA_REQ_I2C4_TX = 7,
+        SPEAR1310_DMA_REQ_I2C5_RX = 8,
+        SPEAR1310_DMA_REQ_I2C5_TX = 9,
+        SPEAR1310_DMA_REQ_I2C6_RX = 10,
+        SPEAR1310_DMA_REQ_I2C6_TX = 11,
+        SPEAR1310_DMA_REQ_UART1_RX = 12,
+        SPEAR1310_DMA_REQ_UART1_TX = 13,
+        SPEAR1310_DMA_REQ_UART2_RX = 14,
+        SPEAR1310_DMA_REQ_UART2_TX = 15,
+        SPEAR1310_DMA_REQ_UART5_RX = 16,
+        SPEAR1310_DMA_REQ_UART5_TX = 17,
+        SPEAR1310_DMA_REQ_SSP1_RX = 18,
+        SPEAR1310_DMA_REQ_SSP1_TX = 19,
+        SPEAR1310_DMA_REQ_I2C7_RX = 20,
+        SPEAR1310_DMA_REQ_I2C7_TX = 21,
+        SPEAR1310_DMA_REQ_UART3_RX = 28,
+        SPEAR1310_DMA_REQ_UART3_TX = 29,
+        SPEAR1310_DMA_REQ_UART4_RX = 30,
+        SPEAR1310_DMA_REQ_UART4_TX = 31,
+#endif
+
+#ifdef CONFIG_MACH_SPEAR1340
+        SPEAR1340_DMA_REQ_SPDIF_TX = 2,
+        SPEAR1340_DMA_REQ_SPDIF_RX = 3,
+        SPEAR1340_DMA_REQ_I2S_TX = 10,
+        SPEAR1340_DMA_REQ_I2S_RX = 11,
+        SPEAR1340_DMA_REQ_UART1_TX = 12,
+        SPEAR1340_DMA_REQ_UART1_RX = 13,
+        SPEAR1340_DMA_REQ_I2C1_TX = 14,
+        SPEAR1340_DMA_REQ_I2C1_RX = 15,
+        SPEAR1340_DMA_REQ_CAM0_EVEN = 0,
+        SPEAR1340_DMA_REQ_CAM0_ODD = 1,
+        SPEAR1340_DMA_REQ_CAM1_EVEN = 2,
+        SPEAR1340_DMA_REQ_CAM1_ODD = 3,
+        SPEAR1340_DMA_REQ_CAM2_EVEN = 4,
+        SPEAR1340_DMA_REQ_CAM2_ODD = 5,
+        SPEAR1340_DMA_REQ_CAM3_EVEN = 6,
+        SPEAR1340_DMA_REQ_CAM3_ODD = 7,
+#endif
+};
+
+#endif /* __MACH_DMA_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/generic.h b/arch/arm/mach-spear13xx/include/mach/generic.h
new file mode 100644
index 000000000000..6d8c45b9f298
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/generic.h
@@ -0,0 +1,49 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/generic.h
+ *
+ * spear13xx machine family generic header file
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_GENERIC_H
+#define __MACH_GENERIC_H
+
+#include <linux/dmaengine.h>
+#include <asm/mach/time.h>
+
+/* Add spear13xx structure declarations here */
+extern struct sys_timer spear13xx_timer;
+extern struct pl022_ssp_controller pl022_plat_data;
+extern struct dw_dma_platform_data dmac_plat_data;
+extern struct dw_dma_slave cf_dma_priv;
+extern struct dw_dma_slave nand_read_dma_priv;
+extern struct dw_dma_slave nand_write_dma_priv;
+
+/* Add spear13xx family function declarations here */
+void __init spear_setup_of_timer(void);
+void __init spear13xx_map_io(void);
+void __init spear13xx_dt_init_irq(void);
+void __init spear13xx_l2x0_init(void);
+bool dw_dma_filter(struct dma_chan *chan, void *slave);
+void spear_restart(char, const char *);
+void spear13xx_secondary_startup(void);
+
+#ifdef CONFIG_MACH_SPEAR1310
+void __init spear1310_clk_init(void);
+#else
+static inline void spear1310_clk_init(void) {}
+#endif
+
+#ifdef CONFIG_MACH_SPEAR1340
+void __init spear1340_clk_init(void);
+#else
+static inline void spear1340_clk_init(void) {}
+#endif
+
+#endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/gpio.h b/arch/arm/mach-spear13xx/include/mach/gpio.h
new file mode 100644
index 000000000000..cd6f4f86a56b
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/gpio.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/gpio.h
+ *
+ * GPIO macros for SPEAr13xx machine family
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_GPIO_H
+#define __MACH_GPIO_H
+
+#include <plat/gpio.h>
+
+#endif /* __MACH_GPIO_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/hardware.h b/arch/arm/mach-spear13xx/include/mach/hardware.h
new file mode 100644
index 000000000000..40a8c178f10d
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/hardware.h
@@ -0,0 +1 @@
+/* empty */
diff --git a/arch/arm/mach-spear13xx/include/mach/irqs.h b/arch/arm/mach-spear13xx/include/mach/irqs.h
new file mode 100644
index 000000000000..f542a24aa5f2
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/irqs.h
@@ -0,0 +1,20 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/irqs.h
+ *
+ * IRQ helper macros for spear13xx machine family
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_IRQS_H
+#define __MACH_IRQS_H
+
+#define IRQ_GIC_END                     160
+#define NR_IRQS                         IRQ_GIC_END
+
+#endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/spear.h b/arch/arm/mach-spear13xx/include/mach/spear.h
new file mode 100644
index 000000000000..30c57ef72686
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/spear.h
@@ -0,0 +1,62 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/spear.h
+ *
+ * spear13xx Machine family specific definition
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_SPEAR13XX_H
+#define __MACH_SPEAR13XX_H
+
+#include <asm/memory.h>
+
+#define PERIP_GRP2_BASE                         UL(0xB3000000)
+#define VA_PERIP_GRP2_BASE                      UL(0xFE000000)
+#define MCIF_SDHCI_BASE                         UL(0xB3000000)
+#define SYSRAM0_BASE                            UL(0xB3800000)
+#define VA_SYSRAM0_BASE                         UL(0xFE800000)
+#define SYS_LOCATION                            (VA_SYSRAM0_BASE + 0x600)
+
+#define PERIP_GRP1_BASE                         UL(0xE0000000)
+#define VA_PERIP_GRP1_BASE                      UL(0xFD000000)
+#define UART_BASE                               UL(0xE0000000)
+#define VA_UART_BASE                            UL(0xFD000000)
+#define SSP_BASE                                UL(0xE0100000)
+#define MISC_BASE                               UL(0xE0700000)
+#define VA_MISC_BASE                            IOMEM(UL(0xFD700000))
+
+#define A9SM_AND_MPMC_BASE                      UL(0xEC000000)
+#define VA_A9SM_AND_MPMC_BASE                   UL(0xFC000000)
+
+/* A9SM peripheral offsets */
+#define A9SM_PERIP_BASE                         UL(0xEC800000)
+#define VA_A9SM_PERIP_BASE                      UL(0xFC800000)
+#define VA_SCU_BASE                             (VA_A9SM_PERIP_BASE + 0x00)
+
+#define L2CC_BASE                               UL(0xED000000)
+#define VA_L2CC_BASE                            IOMEM(UL(0xFB000000))
+
+/* others */
+#define DMAC0_BASE                              UL(0xEA800000)
+#define DMAC1_BASE                              UL(0xEB000000)
+#define MCIF_CF_BASE                            UL(0xB2800000)
+
+/* Devices present in SPEAr1310 */
+#ifdef CONFIG_MACH_SPEAR1310
+#define SPEAR1310_RAS_GRP1_BASE                 UL(0xD8000000)
+#define VA_SPEAR1310_RAS_GRP1_BASE              UL(0xFA000000)
+#define SPEAR1310_RAS_BASE                      UL(0xD8400000)
+#define VA_SPEAR1310_RAS_BASE                   IOMEM(UL(0xFA400000))
+#endif /* CONFIG_MACH_SPEAR1310 */
+
+/* Debug uart for linux, will be used for debug and uncompress messages */
+#define SPEAR_DBG_UART_BASE                     UART_BASE
+#define VA_SPEAR_DBG_UART_BASE                  VA_UART_BASE
+
+#endif /* __MACH_SPEAR13XX_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/spear1310_misc_regs.h b/arch/arm/mach-spear13xx/include/mach/spear1310_misc_regs.h
new file mode 100644
index 000000000000..e69de29bb2d1
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/spear1310_misc_regs.h
diff --git a/arch/arm/mach-spear13xx/include/mach/spear1340_misc_regs.h b/arch/arm/mach-spear13xx/include/mach/spear1340_misc_regs.h
new file mode 100644
index 000000000000..e69de29bb2d1
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/spear1340_misc_regs.h
diff --git a/arch/arm/mach-spear13xx/include/mach/timex.h b/arch/arm/mach-spear13xx/include/mach/timex.h
new file mode 100644
index 000000000000..31af3e8d976e
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/timex.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear3xx/include/mach/timex.h
+ *
+ * SPEAr3XX machine family specific timex definitions
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_TIMEX_H
+#define __MACH_TIMEX_H
+
+#include <plat/timex.h>
+
+#endif /* __MACH_TIMEX_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/uncompress.h b/arch/arm/mach-spear13xx/include/mach/uncompress.h
new file mode 100644
index 000000000000..c7840896ae6e
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/uncompress.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/uncompress.h
+ *
+ * Serial port stubs for kernel decompress status messages
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_UNCOMPRESS_H
+#define __MACH_UNCOMPRESS_H
+
+#include <plat/uncompress.h>
+
+#endif /* __MACH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-spear13xx/platsmp.c b/arch/arm/mach-spear13xx/platsmp.c
new file mode 100644
index 000000000000..f5d07f2663d7
--- /dev/null
+++ b/arch/arm/mach-spear13xx/platsmp.c
@@ -0,0 +1,127 @@
+/*
+ * arch/arm/mach-spear13xx/platsmp.c
+ *
+ * based upon linux/arch/arm/mach-realview/platsmp.c
+ *
+ * Copyright (C) 2012 ST Microelectronics Ltd.
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/delay.h>
+#include <linux/jiffies.h>
+#include <linux/io.h>
+#include <linux/smp.h>
+#include <asm/cacheflush.h>
+#include <asm/hardware/gic.h>
+#include <asm/smp_scu.h>
+#include <mach/spear.h>
+
+/*
+ * control for which core is the next to come out of the secondary
+ * boot "holding pen"
+ */
+volatile int __cpuinitdata pen_release = -1;
+static DEFINE_SPINLOCK(boot_lock);
+
+static void __iomem *scu_base = IOMEM(VA_SCU_BASE);
+extern void spear13xx_secondary_startup(void);
+
+void __cpuinit platform_secondary_init(unsigned int cpu)
+{
+        /*
+         * if any interrupts are already enabled for the primary
+         * core (e.g. timer irq), then they will not have been enabled
+         * for us: do so
+         */
+        gic_secondary_init(0);
+
+        /*
+         * let the primary processor know we're out of the
+         * pen, then head off into the C entry point
+         */
+        pen_release = -1;
+        smp_wmb();
+
+        /*
+         * Synchronise with the boot thread.
+         */
+        spin_lock(&boot_lock);
+        spin_unlock(&boot_lock);
+}
+
+int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+        unsigned long timeout;
+
+        /*
+         * set synchronisation state between this boot processor
+         * and the secondary one
+         */
+        spin_lock(&boot_lock);
+
+        /*
+         * The secondary processor is waiting to be released from
+         * the holding pen - release it, then wait for it to flag
+         * that it has been released by resetting pen_release.
+         *
+         * Note that "pen_release" is the hardware CPU ID, whereas
+         * "cpu" is Linux's internal ID.
+         */
+        pen_release = cpu;
+        flush_cache_all();
+        outer_flush_all();
+
+        timeout = jiffies + (1 * HZ);
+        while (time_before(jiffies, timeout)) {
+                smp_rmb();
+                if (pen_release == -1)
+                        break;
+
+                udelay(10);
+        }
+
+        /*
+         * now the secondary core is starting up let it run its
+         * calibrations, then wait for it to finish
+         */
+        spin_unlock(&boot_lock);
+
+        return pen_release != -1 ? -ENOSYS : 0;
+}
+
+/*
+ * Initialise the CPU possible map early - this describes the CPUs
+ * which may be present or become present in the system.
+ */
+void __init smp_init_cpus(void)
+{
+        unsigned int i, ncores = scu_get_core_count(scu_base);
+
+        if (ncores > nr_cpu_ids) {
+                pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
+                        ncores, nr_cpu_ids);
+                ncores = nr_cpu_ids;
+        }
+
+        for (i = 0; i < ncores; i++)
+                set_cpu_possible(i, true);
+
+        set_smp_cross_call(gic_raise_softirq);
+}
+
+void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+{
+
+        scu_enable(scu_base);
+
+        /*
+         * Write the address of secondary startup into the system-wide location
+         * (presently it is in SRAM). The BootMonitor waits until it receives a
+         * soft interrupt, and then the secondary CPU branches to this address.
+         */
+        __raw_writel(virt_to_phys(spear13xx_secondary_startup), SYS_LOCATION);
+}
diff --git a/arch/arm/mach-spear13xx/spear1310.c b/arch/arm/mach-spear13xx/spear1310.c
new file mode 100644
index 000000000000..fefd15b2f380
--- /dev/null
+++ b/arch/arm/mach-spear13xx/spear1310.c
@@ -0,0 +1,88 @@
+/*
+ * arch/arm/mach-spear13xx/spear1310.c
+ *
+ * SPEAr1310 machine source file
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#define pr_fmt(fmt) "SPEAr1310: " fmt
+
+#include <linux/amba/pl022.h>
+#include <linux/of_platform.h>
+#include <asm/hardware/gic.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/generic.h>
+#include <mach/spear.h>
+
+/* Base addresses */
+#define SPEAR1310_SSP1_BASE                     UL(0x5D400000)
+#define SPEAR1310_SATA0_BASE                    UL(0xB1000000)
+#define SPEAR1310_SATA1_BASE                    UL(0xB1800000)
+#define SPEAR1310_SATA2_BASE                    UL(0xB4000000)
+
+/* ssp device registration */
+static struct pl022_ssp_controller ssp1_plat_data = {
+        .bus_id = 0,
+        .enable_dma = 0,
+        .num_chipselect = 3,
+};
+
+/* Add SPEAr1310 auxdata to pass platform data */
+static struct of_dev_auxdata spear1310_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("arasan,cf-spear1340", MCIF_CF_BASE, NULL, &cf_dma_priv),
+        OF_DEV_AUXDATA("snps,dma-spear1340", DMAC0_BASE, NULL, &dmac_plat_data),
+        OF_DEV_AUXDATA("snps,dma-spear1340", DMAC1_BASE, NULL, &dmac_plat_data),
+        OF_DEV_AUXDATA("arm,pl022", SSP_BASE, NULL, &pl022_plat_data),
+
+        OF_DEV_AUXDATA("arm,pl022", SPEAR1310_SSP1_BASE, NULL, &ssp1_plat_data),
+        {}
+};
+
+static void __init spear1310_dt_init(void)
+{
+        of_platform_populate(NULL, of_default_bus_match_table,
+                        spear1310_auxdata_lookup, NULL);
+}
+
+static const char * const spear1310_dt_board_compat[] = {
+        "st,spear1310",
+        "st,spear1310-evb",
+        NULL,
+};
+
+/*
+ * Following will create 16MB static virtual/physical mappings
+ * PHYSICAL             VIRTUAL
+ * 0xD8000000           0xFA000000
+ */
+struct map_desc spear1310_io_desc[] __initdata = {
+        {
+                .virtual        = VA_SPEAR1310_RAS_GRP1_BASE,
+                .pfn            = __phys_to_pfn(SPEAR1310_RAS_GRP1_BASE),
+                .length         = SZ_16M,
+                .type           = MT_DEVICE
+        },
+};
+
+static void __init spear1310_map_io(void)
+{
+        iotable_init(spear1310_io_desc, ARRAY_SIZE(spear1310_io_desc));
+        spear13xx_map_io();
+}
+
+DT_MACHINE_START(SPEAR1310_DT, "ST SPEAr1310 SoC with Flattened Device Tree")
+        .map_io         =       spear1310_map_io,
+        .init_irq       =       spear13xx_dt_init_irq,
+        .handle_irq     =       gic_handle_irq,
+        .timer          =       &spear13xx_timer,
+        .init_machine   =       spear1310_dt_init,
+        .restart        =       spear_restart,
+        .dt_compat      =       spear1310_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-spear13xx/spear1340.c b/arch/arm/mach-spear13xx/spear1340.c
new file mode 100644
index 000000000000..ee38cbc56869
--- /dev/null
+++ b/arch/arm/mach-spear13xx/spear1340.c
@@ -0,0 +1,192 @@
+/*
+ * arch/arm/mach-spear13xx/spear1340.c
+ *
+ * SPEAr1340 machine source file
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#define pr_fmt(fmt) "SPEAr1340: " fmt
+
+#include <linux/ahci_platform.h>
+#include <linux/amba/serial.h>
+#include <linux/delay.h>
+#include <linux/dw_dmac.h>
+#include <linux/of_platform.h>
+#include <asm/hardware/gic.h>
+#include <asm/mach/arch.h>
+#include <mach/dma.h>
+#include <mach/generic.h>
+#include <mach/spear.h>
+
+/* Base addresses */
+#define SPEAR1340_SATA_BASE                     UL(0xB1000000)
+#define SPEAR1340_UART1_BASE                    UL(0xB4100000)
+
+/* Power Management Registers */
+#define SPEAR1340_PCM_CFG                       (VA_MISC_BASE + 0x100)
+#define SPEAR1340_PCM_WKUP_CFG                  (VA_MISC_BASE + 0x104)
+#define SPEAR1340_SWITCH_CTR                    (VA_MISC_BASE + 0x108)
+
+#define SPEAR1340_PERIP1_SW_RST                 (VA_MISC_BASE + 0x318)
+#define SPEAR1340_PERIP2_SW_RST                 (VA_MISC_BASE + 0x31C)
+#define SPEAR1340_PERIP3_SW_RST                 (VA_MISC_BASE + 0x320)
+
+/* PCIE - SATA configuration registers */
+#define SPEAR1340_PCIE_SATA_CFG                 (VA_MISC_BASE + 0x424)
+        /* PCIE CFG MASks */
+        #define SPEAR1340_PCIE_CFG_DEVICE_PRESENT       (1 << 11)
+        #define SPEAR1340_PCIE_CFG_POWERUP_RESET        (1 << 10)
+        #define SPEAR1340_PCIE_CFG_CORE_CLK_EN          (1 << 9)
+        #define SPEAR1340_PCIE_CFG_AUX_CLK_EN           (1 << 8)
+        #define SPEAR1340_SATA_CFG_TX_CLK_EN            (1 << 4)
+        #define SPEAR1340_SATA_CFG_RX_CLK_EN            (1 << 3)
+        #define SPEAR1340_SATA_CFG_POWERUP_RESET        (1 << 2)
+        #define SPEAR1340_SATA_CFG_PM_CLK_EN            (1 << 1)
+        #define SPEAR1340_PCIE_SATA_SEL_PCIE            (0)
+        #define SPEAR1340_PCIE_SATA_SEL_SATA            (1)
+        #define SPEAR1340_SATA_PCIE_CFG_MASK            0xF1F
+        #define SPEAR1340_PCIE_CFG_VAL  (SPEAR1340_PCIE_SATA_SEL_PCIE | \
+                        SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
+                        SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
+                        SPEAR1340_PCIE_CFG_POWERUP_RESET | \
+                        SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
+        #define SPEAR1340_SATA_CFG_VAL  (SPEAR1340_PCIE_SATA_SEL_SATA | \
+                        SPEAR1340_SATA_CFG_PM_CLK_EN | \
+                        SPEAR1340_SATA_CFG_POWERUP_RESET | \
+                        SPEAR1340_SATA_CFG_RX_CLK_EN | \
+                        SPEAR1340_SATA_CFG_TX_CLK_EN)
+
+#define SPEAR1340_PCIE_MIPHY_CFG                (VA_MISC_BASE + 0x428)
+        #define SPEAR1340_MIPHY_OSC_BYPASS_EXT          (1 << 31)
+        #define SPEAR1340_MIPHY_CLK_REF_DIV2            (1 << 27)
+        #define SPEAR1340_MIPHY_CLK_REF_DIV4            (2 << 27)
+        #define SPEAR1340_MIPHY_CLK_REF_DIV8            (3 << 27)
+        #define SPEAR1340_MIPHY_PLL_RATIO_TOP(x)        (x << 0)
+        #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
+                        (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
+                        SPEAR1340_MIPHY_CLK_REF_DIV2 | \
+                        SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
+        #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
+                        (SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
+        #define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
+                        (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
+                        SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
+
+static struct dw_dma_slave uart1_dma_param[] = {
+        {
+                /* Tx */
+                .cfg_hi = DWC_CFGH_DST_PER(SPEAR1340_DMA_REQ_UART1_TX),
+                .cfg_lo = 0,
+                .src_master = DMA_MASTER_MEMORY,
+                .dst_master = SPEAR1340_DMA_MASTER_UART1,
+        }, {
+                /* Rx */
+                .cfg_hi = DWC_CFGH_SRC_PER(SPEAR1340_DMA_REQ_UART1_RX),
+                .cfg_lo = 0,
+                .src_master = SPEAR1340_DMA_MASTER_UART1,
+                .dst_master = DMA_MASTER_MEMORY,
+        }
+};
+
+static struct amba_pl011_data uart1_data = {
+        .dma_filter = dw_dma_filter,
+        .dma_tx_param = &uart1_dma_param[0],
+        .dma_rx_param = &uart1_dma_param[1],
+};
+
+/* SATA device registration */
+static int sata_miphy_init(struct device *dev, void __iomem *addr)
+{
+        writel(SPEAR1340_SATA_CFG_VAL, SPEAR1340_PCIE_SATA_CFG);
+        writel(SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK,
+                        SPEAR1340_PCIE_MIPHY_CFG);
+        /* Switch on sata power domain */
+        writel((readl(SPEAR1340_PCM_CFG) | (0x800)), SPEAR1340_PCM_CFG);
+        msleep(20);
+        /* Disable PCIE SATA Controller reset */
+        writel((readl(SPEAR1340_PERIP1_SW_RST) & (~0x1000)),
+                        SPEAR1340_PERIP1_SW_RST);
+        msleep(20);
+
+        return 0;
+}
+
+void sata_miphy_exit(struct device *dev)
+{
+        writel(0, SPEAR1340_PCIE_SATA_CFG);
+        writel(0, SPEAR1340_PCIE_MIPHY_CFG);
+
+        /* Enable PCIE SATA Controller reset */
+        writel((readl(SPEAR1340_PERIP1_SW_RST) | (0x1000)),
+                        SPEAR1340_PERIP1_SW_RST);
+        msleep(20);
+        /* Switch off sata power domain */
+        writel((readl(SPEAR1340_PCM_CFG) & (~0x800)), SPEAR1340_PCM_CFG);
+        msleep(20);
+}
+
+int sata_suspend(struct device *dev)
+{
+        if (dev->power.power_state.event == PM_EVENT_FREEZE)
+                return 0;
+
+        sata_miphy_exit(dev);
+
+        return 0;
+}
+
+int sata_resume(struct device *dev)
+{
+        if (dev->power.power_state.event == PM_EVENT_THAW)
+                return 0;
+
+        return sata_miphy_init(dev, NULL);
+}
+
+static struct ahci_platform_data sata_pdata = {
+        .init = sata_miphy_init,
+        .exit = sata_miphy_exit,
+        .suspend = sata_suspend,
+        .resume = sata_resume,
+};
+
+/* Add SPEAr1340 auxdata to pass platform data */
+static struct of_dev_auxdata spear1340_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("arasan,cf-spear1340", MCIF_CF_BASE, NULL, &cf_dma_priv),
+        OF_DEV_AUXDATA("snps,dma-spear1340", DMAC0_BASE, NULL, &dmac_plat_data),
+        OF_DEV_AUXDATA("snps,dma-spear1340", DMAC1_BASE, NULL, &dmac_plat_data),
+        OF_DEV_AUXDATA("arm,pl022", SSP_BASE, NULL, &pl022_plat_data),
+
+        OF_DEV_AUXDATA("snps,spear-ahci", SPEAR1340_SATA_BASE, NULL,
+                        &sata_pdata),
+        OF_DEV_AUXDATA("arm,pl011", SPEAR1340_UART1_BASE, NULL, &uart1_data),
+        {}
+};
+
+static void __init spear1340_dt_init(void)
+{
+        of_platform_populate(NULL, of_default_bus_match_table,
+                        spear1340_auxdata_lookup, NULL);
+}
+
+static const char * const spear1340_dt_board_compat[] = {
+        "st,spear1340",
+        "st,spear1340-evb",
+        NULL,
+};
+
+DT_MACHINE_START(SPEAR1340_DT, "ST SPEAr1340 SoC with Flattened Device Tree")
+        .map_io         =       spear13xx_map_io,
+        .init_irq       =       spear13xx_dt_init_irq,
+        .handle_irq     =       gic_handle_irq,
+        .timer          =       &spear13xx_timer,
+        .init_machine   =       spear1340_dt_init,
+        .restart        =       spear_restart,
+        .dt_compat      =       spear1340_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear13xx/spear13xx.c
new file mode 100644
index 000000000000..50b349ae863d
--- /dev/null
+++ b/arch/arm/mach-spear13xx/spear13xx.c
@@ -0,0 +1,197 @@
+/*
+ * arch/arm/mach-spear13xx/spear13xx.c
+ *
+ * SPEAr13XX machines common source file
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#define pr_fmt(fmt) "SPEAr13xx: " fmt
+
+#include <linux/amba/pl022.h>
+#include <linux/clk.h>
+#include <linux/dw_dmac.h>
+#include <linux/err.h>
+#include <linux/of_irq.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/hardware/gic.h>
+#include <asm/mach/map.h>
+#include <asm/smp_twd.h>
+#include <mach/dma.h>
+#include <mach/generic.h>
+#include <mach/spear.h>
+
+/* common dw_dma filter routine to be used by peripherals */
+bool dw_dma_filter(struct dma_chan *chan, void *slave)
+{
+        struct dw_dma_slave *dws = (struct dw_dma_slave *)slave;
+
+        if (chan->device->dev == dws->dma_dev) {
+                chan->private = slave;
+                return true;
+        } else {
+                return false;
+        }
+}
+
+/* ssp device registration */
+static struct dw_dma_slave ssp_dma_param[] = {
+        {
+                /* Tx */
+                .cfg_hi = DWC_CFGH_DST_PER(DMA_REQ_SSP0_TX),
+                .cfg_lo = 0,
+                .src_master = DMA_MASTER_MEMORY,
+                .dst_master = DMA_MASTER_SSP0,
+        }, {
+                /* Rx */
+                .cfg_hi = DWC_CFGH_SRC_PER(DMA_REQ_SSP0_RX),
+                .cfg_lo = 0,
+                .src_master = DMA_MASTER_SSP0,
+                .dst_master = DMA_MASTER_MEMORY,
+        }
+};
+
+struct pl022_ssp_controller pl022_plat_data = {
+        .bus_id = 0,
+        .enable_dma = 1,
+        .dma_filter = dw_dma_filter,
+        .dma_rx_param = &ssp_dma_param[1],
+        .dma_tx_param = &ssp_dma_param[0],
+        .num_chipselect = 3,
+};
+
+/* CF device registration */
+struct dw_dma_slave cf_dma_priv = {
+        .cfg_hi = 0,
+        .cfg_lo = 0,
+        .src_master = 0,
+        .dst_master = 0,
+};
+
+/* dmac device registeration */
+struct dw_dma_platform_data dmac_plat_data = {
+        .nr_channels = 8,
+        .chan_allocation_order = CHAN_ALLOCATION_DESCENDING,
+        .chan_priority = CHAN_PRIORITY_DESCENDING,
+};
+
+void __init spear13xx_l2x0_init(void)
+{
+        /*
+         * 512KB (64KB/way), 8-way associativity, parity supported
+         *
+         * FIXME: 9th bit, of Auxillary Controller register must be set
+         * for some spear13xx devices for stable L2 operation.
+         *
+         * Enable Early BRESP, L2 prefetch for Instruction and Data,
+         * write alloc and 'Full line of zero' options
+         *
+         */
+
+        writel_relaxed(0x06, VA_L2CC_BASE + L2X0_PREFETCH_CTRL);
+
+        /*
+         * Program following latencies in order to make
+         * SPEAr1340 work at 600 MHz
+         */
+        writel_relaxed(0x221, VA_L2CC_BASE + L2X0_TAG_LATENCY_CTRL);
+        writel_relaxed(0x441, VA_L2CC_BASE + L2X0_DATA_LATENCY_CTRL);
+        l2x0_init(VA_L2CC_BASE, 0x70A60001, 0xfe00ffff);
+}
+
+/*
+ * Following will create 16MB static virtual/physical mappings
+ * PHYSICAL             VIRTUAL
+ * 0xB3000000           0xFE000000
+ * 0xE0000000           0xFD000000
+ * 0xEC000000           0xFC000000
+ * 0xED000000           0xFB000000
+ */
+struct map_desc spear13xx_io_desc[] __initdata = {
+        {
+                .virtual        = VA_PERIP_GRP2_BASE,
+                .pfn            = __phys_to_pfn(PERIP_GRP2_BASE),
+                .length         = SZ_16M,
+                .type           = MT_DEVICE
+        }, {
+                .virtual        = VA_PERIP_GRP1_BASE,
+                .pfn            = __phys_to_pfn(PERIP_GRP1_BASE),
+                .length         = SZ_16M,
+                .type           = MT_DEVICE
+        }, {
+                .virtual        = VA_A9SM_AND_MPMC_BASE,
+                .pfn            = __phys_to_pfn(A9SM_AND_MPMC_BASE),
+                .length         = SZ_16M,
+                .type           = MT_DEVICE
+        }, {
+                .virtual        = (unsigned long)VA_L2CC_BASE,
+                .pfn            = __phys_to_pfn(L2CC_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE
+        },
+};
+
+/* This will create static memory mapping for selected devices */
+void __init spear13xx_map_io(void)
+{
+        iotable_init(spear13xx_io_desc, ARRAY_SIZE(spear13xx_io_desc));
+}
+
+static void __init spear13xx_clk_init(void)
+{
+        if (of_machine_is_compatible("st,spear1310"))
+                spear1310_clk_init();
+        else if (of_machine_is_compatible("st,spear1340"))
+                spear1340_clk_init();
+        else
+                pr_err("%s: Unknown machine\n", __func__);
+}
+
+static void __init spear13xx_timer_init(void)
+{
+        char pclk_name[] = "osc_24m_clk";
+        struct clk *gpt_clk, *pclk;
+
+        spear13xx_clk_init();
+
+        /* get the system timer clock */
+        gpt_clk = clk_get_sys("gpt0", NULL);
+        if (IS_ERR(gpt_clk)) {
+                pr_err("%s:couldn't get clk for gpt\n", __func__);
+                BUG();
+        }
+
+        /* get the suitable parent clock for timer*/
+        pclk = clk_get(NULL, pclk_name);
+        if (IS_ERR(pclk)) {
+                pr_err("%s:couldn't get %s as parent for gpt\n", __func__,
+                                pclk_name);
+                BUG();
+        }
+
+        clk_set_parent(gpt_clk, pclk);
+        clk_put(gpt_clk);
+        clk_put(pclk);
+
+        spear_setup_of_timer();
+        twd_local_timer_of_register();
+}
+
+struct sys_timer spear13xx_timer = {
+        .init = spear13xx_timer_init,
+};
+
+static const struct of_device_id gic_of_match[] __initconst = {
+        { .compatible = "arm,cortex-a9-gic", .data = gic_of_init },
+        { /* Sentinel */ }
+};
+
+void __init spear13xx_dt_init_irq(void)
+{
+        of_irq_init(gic_of_match);
+}
diff --git a/arch/arm/mach-spear3xx/Kconfig b/arch/arm/mach-spear3xx/Kconfig
index 2cee6b0de371..8bd37291fa4f 100644
--- a/arch/arm/mach-spear3xx/Kconfig
+++ b/arch/arm/mach-spear3xx/Kconfig
@@ -5,39 +5,22 @@
 if ARCH_SPEAR3XX
 
 menu "SPEAr3xx Implementations"
-config BOARD_SPEAR300_EVB
-        bool "SPEAr300 Evaluation Board"
-        select MACH_SPEAR300
-        help
-          Supports ST SPEAr300 Evaluation Board
-
-config BOARD_SPEAR310_EVB
-        bool "SPEAr310 Evaluation Board"
-        select MACH_SPEAR310
-        help
-          Supports ST SPEAr310 Evaluation Board
-
-config BOARD_SPEAR320_EVB
-        bool "SPEAr320 Evaluation Board"
-        select MACH_SPEAR320
-        help
-          Supports ST SPEAr320 Evaluation Board
-
-endmenu
-
 config MACH_SPEAR300
-        bool "SPEAr300"
+        bool "SPEAr300 Machine support with Device Tree"
+        select PINCTRL_SPEAR300
         help
-          Supports ST SPEAr300 Machine
+          Supports ST SPEAr300 machine configured via the device-tree
 
 config MACH_SPEAR310
-        bool "SPEAr310"
+        bool "SPEAr310 Machine support with Device Tree"
+        select PINCTRL_SPEAR310
         help
-          Supports ST SPEAr310 Machine
+          Supports ST SPEAr310 machine configured via the device-tree
 
 config MACH_SPEAR320
-        bool "SPEAr320"
+        bool "SPEAr320 Machine support with Device Tree"
+        select PINCTRL_SPEAR320
         help
-          Supports ST SPEAr320 Machine
-
+          Supports ST SPEAr320 machine configured via the device-tree
+endmenu
 endif #ARCH_SPEAR3XX
diff --git a/arch/arm/mach-spear3xx/Makefile b/arch/arm/mach-spear3xx/Makefile
index b24862489704..8d12faa178fd 100644
--- a/arch/arm/mach-spear3xx/Makefile
+++ b/arch/arm/mach-spear3xx/Makefile
@@ -3,24 +3,13 @@
 #
 
 # common files
-obj-y   += spear3xx.o clock.o
+obj-$(CONFIG_ARCH_SPEAR3XX)     += spear3xx.o
 
 # spear300 specific files
 obj-$(CONFIG_MACH_SPEAR300) += spear300.o
 
-# spear300 boards files
-obj-$(CONFIG_BOARD_SPEAR300_EVB) += spear300_evb.o
-
-
 # spear310 specific files
 obj-$(CONFIG_MACH_SPEAR310) += spear310.o
 
-# spear310 boards files
-obj-$(CONFIG_BOARD_SPEAR310_EVB) += spear310_evb.o
-
-
 # spear320 specific files
 obj-$(CONFIG_MACH_SPEAR320) += spear320.o
-
-# spear320 boards files
-obj-$(CONFIG_BOARD_SPEAR320_EVB) += spear320_evb.o
diff --git a/arch/arm/mach-spear3xx/Makefile.boot b/arch/arm/mach-spear3xx/Makefile.boot
index 4674a4c221db..d93e2177e6ec 100644
--- a/arch/arm/mach-spear3xx/Makefile.boot
+++ b/arch/arm/mach-spear3xx/Makefile.boot
@@ -1,3 +1,7 @@
 zreladdr-y      += 0x00008000
 params_phys-y   := 0x00000100
 initrd_phys-y   := 0x00800000
+
+dtb-$(CONFIG_MACH_SPEAR300)     += spear300-evb.dtb
+dtb-$(CONFIG_MACH_SPEAR310)     += spear310-evb.dtb
+dtb-$(CONFIG_MACH_SPEAR320)     += spear320-evb.dtb
diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c
deleted file mode 100644
index 6c4841f55223..000000000000
--- a/arch/arm/mach-spear3xx/clock.c
+++ /dev/null
@@ -1,760 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/clock.c
- *
- * SPEAr3xx machines clock framework source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <asm/mach-types.h>
-#include <plat/clock.h>
-#include <mach/misc_regs.h>
-
-/* root clks */
-/* 32 KHz oscillator clock */
-static struct clk osc_32k_clk = {
-        .flags = ALWAYS_ENABLED,
-        .rate = 32000,
-};
-
-/* 24 MHz oscillator clock */
-static struct clk osc_24m_clk = {
-        .flags = ALWAYS_ENABLED,
-        .rate = 24000000,
-};
-
-/* clock derived from 32 KHz osc clk */
-/* rtc clock */
-static struct clk rtc_clk = {
-        .pclk = &osc_32k_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = RTC_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* clock derived from 24 MHz osc clk */
-/* pll masks structure */
-static struct pll_clk_masks pll1_masks = {
-        .mode_mask = PLL_MODE_MASK,
-        .mode_shift = PLL_MODE_SHIFT,
-        .norm_fdbk_m_mask = PLL_NORM_FDBK_M_MASK,
-        .norm_fdbk_m_shift = PLL_NORM_FDBK_M_SHIFT,
-        .dith_fdbk_m_mask = PLL_DITH_FDBK_M_MASK,
-        .dith_fdbk_m_shift = PLL_DITH_FDBK_M_SHIFT,
-        .div_p_mask = PLL_DIV_P_MASK,
-        .div_p_shift = PLL_DIV_P_SHIFT,
-        .div_n_mask = PLL_DIV_N_MASK,
-        .div_n_shift = PLL_DIV_N_SHIFT,
-};
-
-/* pll1 configuration structure */
-static struct pll_clk_config pll1_config = {
-        .mode_reg = PLL1_CTR,
-        .cfg_reg = PLL1_FRQ,
-        .masks = &pll1_masks,
-};
-
-/* pll rate configuration table, in ascending order of rates */
-struct pll_rate_tbl pll_rtbl[] = {
-        {.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* 266 MHz */
-        {.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* 332 MHz */
-};
-
-/* PLL1 clock */
-static struct clk pll1_clk = {
-        .flags = ENABLED_ON_INIT,
-        .pclk = &osc_24m_clk,
-        .en_reg = PLL1_CTR,
-        .en_reg_bit = PLL_ENABLE,
-        .calc_rate = &pll_calc_rate,
-        .recalc = &pll_clk_recalc,
-        .set_rate = &pll_clk_set_rate,
-        .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 1},
-        .private_data = &pll1_config,
-};
-
-/* PLL3 48 MHz clock */
-static struct clk pll3_48m_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &osc_24m_clk,
-        .rate = 48000000,
-};
-
-/* watch dog timer clock */
-static struct clk wdt_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &osc_24m_clk,
-        .recalc = &follow_parent,
-};
-
-/* clock derived from pll1 clk */
-/* cpu clock */
-static struct clk cpu_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &pll1_clk,
-        .recalc = &follow_parent,
-};
-
-/* ahb masks structure */
-static struct bus_clk_masks ahb_masks = {
-        .mask = PLL_HCLK_RATIO_MASK,
-        .shift = PLL_HCLK_RATIO_SHIFT,
-};
-
-/* ahb configuration structure */
-static struct bus_clk_config ahb_config = {
-        .reg = CORE_CLK_CFG,
-        .masks = &ahb_masks,
-};
-
-/* ahb rate configuration table, in ascending order of rates */
-struct bus_rate_tbl bus_rtbl[] = {
-        {.div = 3}, /* == parent divided by 4 */
-        {.div = 2}, /* == parent divided by 3 */
-        {.div = 1}, /* == parent divided by 2 */
-        {.div = 0}, /* == parent divided by 1 */
-};
-
-/* ahb clock */
-static struct clk ahb_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &pll1_clk,
-        .calc_rate = &bus_calc_rate,
-        .recalc = &bus_clk_recalc,
-        .set_rate = &bus_clk_set_rate,
-        .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
-        .private_data = &ahb_config,
-};
-
-/* auxiliary synthesizers masks */
-static struct aux_clk_masks aux_masks = {
-        .eq_sel_mask = AUX_EQ_SEL_MASK,
-        .eq_sel_shift = AUX_EQ_SEL_SHIFT,
-        .eq1_mask = AUX_EQ1_SEL,
-        .eq2_mask = AUX_EQ2_SEL,
-        .xscale_sel_mask = AUX_XSCALE_MASK,
-        .xscale_sel_shift = AUX_XSCALE_SHIFT,
-        .yscale_sel_mask = AUX_YSCALE_MASK,
-        .yscale_sel_shift = AUX_YSCALE_SHIFT,
-};
-
-/* uart synth configurations */
-static struct aux_clk_config uart_synth_config = {
-        .synth_reg = UART_CLK_SYNT,
-        .masks = &aux_masks,
-};
-
-/* aux rate configuration table, in ascending order of rates */
-struct aux_rate_tbl aux_rtbl[] = {
-        /* For PLL1 = 332 MHz */
-        {.xscale = 1, .yscale = 8, .eq = 1}, /* 41.5 MHz */
-        {.xscale = 1, .yscale = 4, .eq = 1}, /* 83 MHz */
-        {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
-};
-
-/* uart synth clock */
-static struct clk uart_synth_clk = {
-        .en_reg = UART_CLK_SYNT,
-        .en_reg_bit = AUX_SYNT_ENB,
-        .pclk = &pll1_clk,
-        .calc_rate = &aux_calc_rate,
-        .recalc = &aux_clk_recalc,
-        .set_rate = &aux_clk_set_rate,
-        .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 1},
-        .private_data = &uart_synth_config,
-};
-
-/* uart parents */
-static struct pclk_info uart_pclk_info[] = {
-        {
-                .pclk = &uart_synth_clk,
-                .pclk_val = AUX_CLK_PLL1_VAL,
-        }, {
-                .pclk = &pll3_48m_clk,
-                .pclk_val = AUX_CLK_PLL3_VAL,
-        },
-};
-
-/* uart parent select structure */
-static struct pclk_sel uart_pclk_sel = {
-        .pclk_info = uart_pclk_info,
-        .pclk_count = ARRAY_SIZE(uart_pclk_info),
-        .pclk_sel_reg = PERIP_CLK_CFG,
-        .pclk_sel_mask = UART_CLK_MASK,
-};
-
-/* uart clock */
-static struct clk uart_clk = {
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = UART_CLK_ENB,
-        .pclk_sel = &uart_pclk_sel,
-        .pclk_sel_shift = UART_CLK_SHIFT,
-        .recalc = &follow_parent,
-};
-
-/* firda configurations */
-static struct aux_clk_config firda_synth_config = {
-        .synth_reg = FIRDA_CLK_SYNT,
-        .masks = &aux_masks,
-};
-
-/* firda synth clock */
-static struct clk firda_synth_clk = {
-        .en_reg = FIRDA_CLK_SYNT,
-        .en_reg_bit = AUX_SYNT_ENB,
-        .pclk = &pll1_clk,
-        .calc_rate = &aux_calc_rate,
-        .recalc = &aux_clk_recalc,
-        .set_rate = &aux_clk_set_rate,
-        .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 1},
-        .private_data = &firda_synth_config,
-};
-
-/* firda parents */
-static struct pclk_info firda_pclk_info[] = {
-        {
-                .pclk = &firda_synth_clk,
-                .pclk_val = AUX_CLK_PLL1_VAL,
-        }, {
-                .pclk = &pll3_48m_clk,
-                .pclk_val = AUX_CLK_PLL3_VAL,
-        },
-};
-
-/* firda parent select structure */
-static struct pclk_sel firda_pclk_sel = {
-        .pclk_info = firda_pclk_info,
-        .pclk_count = ARRAY_SIZE(firda_pclk_info),
-        .pclk_sel_reg = PERIP_CLK_CFG,
-        .pclk_sel_mask = FIRDA_CLK_MASK,
-};
-
-/* firda clock */
-static struct clk firda_clk = {
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = FIRDA_CLK_ENB,
-        .pclk_sel = &firda_pclk_sel,
-        .pclk_sel_shift = FIRDA_CLK_SHIFT,
-        .recalc = &follow_parent,
-};
-
-/* gpt synthesizer masks */
-static struct gpt_clk_masks gpt_masks = {
-        .mscale_sel_mask = GPT_MSCALE_MASK,
-        .mscale_sel_shift = GPT_MSCALE_SHIFT,
-        .nscale_sel_mask = GPT_NSCALE_MASK,
-        .nscale_sel_shift = GPT_NSCALE_SHIFT,
-};
-
-/* gpt rate configuration table, in ascending order of rates */
-struct gpt_rate_tbl gpt_rtbl[] = {
-        /* For pll1 = 332 MHz */
-        {.mscale = 4, .nscale = 0}, /* 41.5 MHz */
-        {.mscale = 2, .nscale = 0}, /* 55.3 MHz */
-        {.mscale = 1, .nscale = 0}, /* 83 MHz */
-};
-
-/* gpt0 synth clk config*/
-static struct gpt_clk_config gpt0_synth_config = {
-        .synth_reg = PRSC1_CLK_CFG,
-        .masks = &gpt_masks,
-};
-
-/* gpt synth clock */
-static struct clk gpt0_synth_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &pll1_clk,
-        .calc_rate = &gpt_calc_rate,
-        .recalc = &gpt_clk_recalc,
-        .set_rate = &gpt_clk_set_rate,
-        .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
-        .private_data = &gpt0_synth_config,
-};
-
-/* gpt parents */
-static struct pclk_info gpt0_pclk_info[] = {
-        {
-                .pclk = &gpt0_synth_clk,
-                .pclk_val = AUX_CLK_PLL1_VAL,
-        }, {
-                .pclk = &pll3_48m_clk,
-                .pclk_val = AUX_CLK_PLL3_VAL,
-        },
-};
-
-/* gpt parent select structure */
-static struct pclk_sel gpt0_pclk_sel = {
-        .pclk_info = gpt0_pclk_info,
-        .pclk_count = ARRAY_SIZE(gpt0_pclk_info),
-        .pclk_sel_reg = PERIP_CLK_CFG,
-        .pclk_sel_mask = GPT_CLK_MASK,
-};
-
-/* gpt0 timer clock */
-static struct clk gpt0_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk_sel = &gpt0_pclk_sel,
-        .pclk_sel_shift = GPT0_CLK_SHIFT,
-        .recalc = &follow_parent,
-};
-
-/* gpt1 synth clk configurations */
-static struct gpt_clk_config gpt1_synth_config = {
-        .synth_reg = PRSC2_CLK_CFG,
-        .masks = &gpt_masks,
-};
-
-/* gpt1 synth clock */
-static struct clk gpt1_synth_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &pll1_clk,
-        .calc_rate = &gpt_calc_rate,
-        .recalc = &gpt_clk_recalc,
-        .set_rate = &gpt_clk_set_rate,
-        .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
-        .private_data = &gpt1_synth_config,
-};
-
-static struct pclk_info gpt1_pclk_info[] = {
-        {
-                .pclk = &gpt1_synth_clk,
-                .pclk_val = AUX_CLK_PLL1_VAL,
-        }, {
-                .pclk = &pll3_48m_clk,
-                .pclk_val = AUX_CLK_PLL3_VAL,
-        },
-};
-
-/* gpt parent select structure */
-static struct pclk_sel gpt1_pclk_sel = {
-        .pclk_info = gpt1_pclk_info,
-        .pclk_count = ARRAY_SIZE(gpt1_pclk_info),
-        .pclk_sel_reg = PERIP_CLK_CFG,
-        .pclk_sel_mask = GPT_CLK_MASK,
-};
-
-/* gpt1 timer clock */
-static struct clk gpt1_clk = {
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = GPT1_CLK_ENB,
-        .pclk_sel = &gpt1_pclk_sel,
-        .pclk_sel_shift = GPT1_CLK_SHIFT,
-        .recalc = &follow_parent,
-};
-
-/* gpt2 synth clk configurations */
-static struct gpt_clk_config gpt2_synth_config = {
-        .synth_reg = PRSC3_CLK_CFG,
-        .masks = &gpt_masks,
-};
-
-/* gpt1 synth clock */
-static struct clk gpt2_synth_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &pll1_clk,
-        .calc_rate = &gpt_calc_rate,
-        .recalc = &gpt_clk_recalc,
-        .set_rate = &gpt_clk_set_rate,
-        .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
-        .private_data = &gpt2_synth_config,
-};
-
-static struct pclk_info gpt2_pclk_info[] = {
-        {
-                .pclk = &gpt2_synth_clk,
-                .pclk_val = AUX_CLK_PLL1_VAL,
-        }, {
-                .pclk = &pll3_48m_clk,
-                .pclk_val = AUX_CLK_PLL3_VAL,
-        },
-};
-
-/* gpt parent select structure */
-static struct pclk_sel gpt2_pclk_sel = {
-        .pclk_info = gpt2_pclk_info,
-        .pclk_count = ARRAY_SIZE(gpt2_pclk_info),
-        .pclk_sel_reg = PERIP_CLK_CFG,
-        .pclk_sel_mask = GPT_CLK_MASK,
-};
-
-/* gpt2 timer clock */
-static struct clk gpt2_clk = {
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = GPT2_CLK_ENB,
-        .pclk_sel = &gpt2_pclk_sel,
-        .pclk_sel_shift = GPT2_CLK_SHIFT,
-        .recalc = &follow_parent,
-};
-
-/* clock derived from pll3 clk */
-/* usbh clock */
-static struct clk usbh_clk = {
-        .pclk = &pll3_48m_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = USBH_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* usbd clock */
-static struct clk usbd_clk = {
-        .pclk = &pll3_48m_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = USBD_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* clock derived from ahb clk */
-/* apb masks structure */
-static struct bus_clk_masks apb_masks = {
-        .mask = HCLK_PCLK_RATIO_MASK,
-        .shift = HCLK_PCLK_RATIO_SHIFT,
-};
-
-/* apb configuration structure */
-static struct bus_clk_config apb_config = {
-        .reg = CORE_CLK_CFG,
-        .masks = &apb_masks,
-};
-
-/* apb clock */
-static struct clk apb_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &ahb_clk,
-        .calc_rate = &bus_calc_rate,
-        .recalc = &bus_clk_recalc,
-        .set_rate = &bus_clk_set_rate,
-        .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
-        .private_data = &apb_config,
-};
-
-/* i2c clock */
-static struct clk i2c_clk = {
-        .pclk = &ahb_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = I2C_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* dma clock */
-static struct clk dma_clk = {
-        .pclk = &ahb_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = DMA_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* jpeg clock */
-static struct clk jpeg_clk = {
-        .pclk = &ahb_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = JPEG_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* gmac clock */
-static struct clk gmac_clk = {
-        .pclk = &ahb_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = GMAC_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* smi clock */
-static struct clk smi_clk = {
-        .pclk = &ahb_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = SMI_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* c3 clock */
-static struct clk c3_clk = {
-        .pclk = &ahb_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = C3_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* clock derived from apb clk */
-/* adc clock */
-static struct clk adc_clk = {
-        .pclk = &apb_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = ADC_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
-/* emi clock */
-static struct clk emi_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &ahb_clk,
-        .recalc = &follow_parent,
-};
-#endif
-
-/* ssp clock */
-static struct clk ssp0_clk = {
-        .pclk = &apb_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = SSP_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* gpio clock */
-static struct clk gpio_clk = {
-        .pclk = &apb_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = GPIO_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-static struct clk dummy_apb_pclk;
-
-#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR310) || \
-        defined(CONFIG_MACH_SPEAR320)
-/* fsmc clock */
-static struct clk fsmc_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &ahb_clk,
-        .recalc = &follow_parent,
-};
-#endif
-
-/* common clocks to spear310 and spear320 */
-#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
-/* uart1 clock */
-static struct clk uart1_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &apb_clk,
-        .recalc = &follow_parent,
-};
-
-/* uart2 clock */
-static struct clk uart2_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &apb_clk,
-        .recalc = &follow_parent,
-};
-#endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */
-
-/* common clocks to spear300 and spear320 */
-#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR320)
-/* clcd clock */
-static struct clk clcd_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &pll3_48m_clk,
-        .recalc = &follow_parent,
-};
-
-/* sdhci clock */
-static struct clk sdhci_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &ahb_clk,
-        .recalc = &follow_parent,
-};
-#endif /* CONFIG_MACH_SPEAR300 || CONFIG_MACH_SPEAR320 */
-
-/* spear300 machine specific clock structures */
-#ifdef CONFIG_MACH_SPEAR300
-/* gpio1 clock */
-static struct clk gpio1_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &apb_clk,
-        .recalc = &follow_parent,
-};
-
-/* keyboard clock */
-static struct clk kbd_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &apb_clk,
-        .recalc = &follow_parent,
-};
-
-#endif
-
-/* spear310 machine specific clock structures */
-#ifdef CONFIG_MACH_SPEAR310
-/* uart3 clock */
-static struct clk uart3_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &apb_clk,
-        .recalc = &follow_parent,
-};
-
-/* uart4 clock */
-static struct clk uart4_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &apb_clk,
-        .recalc = &follow_parent,
-};
-
-/* uart5 clock */
-static struct clk uart5_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &apb_clk,
-        .recalc = &follow_parent,
-};
-#endif
-
-/* spear320 machine specific clock structures */
-#ifdef CONFIG_MACH_SPEAR320
-/* can0 clock */
-static struct clk can0_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &apb_clk,
-        .recalc = &follow_parent,
-};
-
-/* can1 clock */
-static struct clk can1_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &apb_clk,
-        .recalc = &follow_parent,
-};
-
-/* i2c1 clock */
-static struct clk i2c1_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &ahb_clk,
-        .recalc = &follow_parent,
-};
-
-/* ssp1 clock */
-static struct clk ssp1_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &apb_clk,
-        .recalc = &follow_parent,
-};
-
-/* ssp2 clock */
-static struct clk ssp2_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &apb_clk,
-        .recalc = &follow_parent,
-};
-
-/* pwm clock */
-static struct clk pwm_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &apb_clk,
-        .recalc = &follow_parent,
-};
-#endif
-
-/* array of all spear 3xx clock lookups */
-static struct clk_lookup spear_clk_lookups[] = {
-        { .con_id = "apb_pclk",         .clk = &dummy_apb_pclk},
-        /* root clks */
-        { .con_id = "osc_32k_clk",      .clk = &osc_32k_clk},
-        { .con_id = "osc_24m_clk",      .clk = &osc_24m_clk},
-        /* clock derived from 32 KHz osc clk */
-        { .dev_id = "rtc-spear",        .clk = &rtc_clk},
-        /* clock derived from 24 MHz osc clk */
-        { .con_id = "pll1_clk",         .clk = &pll1_clk},
-        { .con_id = "pll3_48m_clk",     .clk = &pll3_48m_clk},
-        { .dev_id = "wdt",              .clk = &wdt_clk},
-        /* clock derived from pll1 clk */
-        { .con_id = "cpu_clk",          .clk = &cpu_clk},
-        { .con_id = "ahb_clk",          .clk = &ahb_clk},
-        { .con_id = "uart_synth_clk",   .clk = &uart_synth_clk},
-        { .con_id = "firda_synth_clk",  .clk = &firda_synth_clk},
-        { .con_id = "gpt0_synth_clk",   .clk = &gpt0_synth_clk},
-        { .con_id = "gpt1_synth_clk",   .clk = &gpt1_synth_clk},
-        { .con_id = "gpt2_synth_clk",   .clk = &gpt2_synth_clk},
-        { .dev_id = "uart",             .clk = &uart_clk},
-        { .dev_id = "firda",            .clk = &firda_clk},
-        { .dev_id = "gpt0",             .clk = &gpt0_clk},
-        { .dev_id = "gpt1",             .clk = &gpt1_clk},
-        { .dev_id = "gpt2",             .clk = &gpt2_clk},
-        /* clock derived from pll3 clk */
-        { .dev_id = "designware_udc",   .clk = &usbd_clk},
-        { .con_id = "usbh_clk",         .clk = &usbh_clk},
-        /* clock derived from ahb clk */
-        { .con_id = "apb_clk",          .clk = &apb_clk},
-        { .dev_id = "i2c_designware.0", .clk = &i2c_clk},
-        { .dev_id = "dma",              .clk = &dma_clk},
-        { .dev_id = "jpeg",             .clk = &jpeg_clk},
-        { .dev_id = "gmac",             .clk = &gmac_clk},
-        { .dev_id = "smi",              .clk = &smi_clk},
-        { .dev_id = "c3",               .clk = &c3_clk},
-        /* clock derived from apb clk */
-        { .dev_id = "adc",              .clk = &adc_clk},
-        { .dev_id = "ssp-pl022.0",      .clk = &ssp0_clk},
-        { .dev_id = "gpio",             .clk = &gpio_clk},
-};
-
-/* array of all spear 300 clock lookups */
-#ifdef CONFIG_MACH_SPEAR300
-static struct clk_lookup spear300_clk_lookups[] = {
-        { .dev_id = "clcd",             .clk = &clcd_clk},
-        { .con_id = "fsmc",             .clk = &fsmc_clk},
-        { .dev_id = "gpio1",            .clk = &gpio1_clk},
-        { .dev_id = "keyboard",         .clk = &kbd_clk},
-        { .dev_id = "sdhci",            .clk = &sdhci_clk},
-};
-#endif
-
-/* array of all spear 310 clock lookups */
-#ifdef CONFIG_MACH_SPEAR310
-static struct clk_lookup spear310_clk_lookups[] = {
-        { .con_id = "fsmc",             .clk = &fsmc_clk},
-        { .con_id = "emi",              .clk = &emi_clk},
-        { .dev_id = "uart1",            .clk = &uart1_clk},
-        { .dev_id = "uart2",            .clk = &uart2_clk},
-        { .dev_id = "uart3",            .clk = &uart3_clk},
-        { .dev_id = "uart4",            .clk = &uart4_clk},
-        { .dev_id = "uart5",            .clk = &uart5_clk},
-};
-#endif
-
-/* array of all spear 320 clock lookups */
-#ifdef CONFIG_MACH_SPEAR320
-static struct clk_lookup spear320_clk_lookups[] = {
-        { .dev_id = "clcd",             .clk = &clcd_clk},
-        { .con_id = "fsmc",             .clk = &fsmc_clk},
-        { .dev_id = "i2c_designware.1", .clk = &i2c1_clk},
-        { .con_id = "emi",              .clk = &emi_clk},
-        { .dev_id = "pwm",              .clk = &pwm_clk},
-        { .dev_id = "sdhci",            .clk = &sdhci_clk},
-        { .dev_id = "c_can_platform.0", .clk = &can0_clk},
-        { .dev_id = "c_can_platform.1", .clk = &can1_clk},
-        { .dev_id = "ssp-pl022.1",      .clk = &ssp1_clk},
-        { .dev_id = "ssp-pl022.2",      .clk = &ssp2_clk},
-        { .dev_id = "uart1",            .clk = &uart1_clk},
-        { .dev_id = "uart2",            .clk = &uart2_clk},
-};
-#endif
-
-void __init spear3xx_clk_init(void)
-{
-        int i, cnt;
-        struct clk_lookup *lookups;
-
-        if (machine_is_spear300()) {
-                cnt = ARRAY_SIZE(spear300_clk_lookups);
-                lookups = spear300_clk_lookups;
-        } else if (machine_is_spear310()) {
-                cnt = ARRAY_SIZE(spear310_clk_lookups);
-                lookups = spear310_clk_lookups;
-        } else {
-                cnt = ARRAY_SIZE(spear320_clk_lookups);
-                lookups = spear320_clk_lookups;
-        }
-
-        for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
-                clk_register(&spear_clk_lookups[i]);
-
-        for (i = 0; i < cnt; i++)
-                clk_register(&lookups[i]);
-
-        clk_init();
-}
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index 14276e5a98d2..4a95b9453c2a 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -14,189 +14,24 @@
 #ifndef __MACH_GENERIC_H
 #define __MACH_GENERIC_H
 
+#include <linux/amba/pl08x.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/amba/bus.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
-#include <plat/padmux.h>
-
-/* spear3xx declarations */
-/*
- * Each GPT has 2 timer channels
- * Following GPT channels will be used as clock source and clockevent
- */
-#define SPEAR_GPT0_BASE         SPEAR3XX_ML1_TMR_BASE
-#define SPEAR_GPT0_CHAN0_IRQ    SPEAR3XX_IRQ_CPU_GPT1_1
-#define SPEAR_GPT0_CHAN1_IRQ    SPEAR3XX_IRQ_CPU_GPT1_2
 
 /* Add spear3xx family device structure declarations here */
-extern struct amba_device spear3xx_gpio_device;
-extern struct amba_device spear3xx_uart_device;
 extern struct sys_timer spear3xx_timer;
+extern struct pl022_ssp_controller pl022_plat_data;
+extern struct pl08x_platform_data pl080_plat_data;
 
 /* Add spear3xx family function declarations here */
+void __init spear_setup_of_timer(void);
 void __init spear3xx_clk_init(void);
-void __init spear_setup_timer(void);
 void __init spear3xx_map_io(void);
-void __init spear3xx_init_irq(void);
-void __init spear3xx_init(void);
+void __init spear3xx_dt_init_irq(void);
 
 void spear_restart(char, const char *);
 
-/* pad mux declarations */
-#define PMX_FIRDA_MASK          (1 << 14)
-#define PMX_I2C_MASK            (1 << 13)
-#define PMX_SSP_CS_MASK         (1 << 12)
-#define PMX_SSP_MASK            (1 << 11)
-#define PMX_MII_MASK            (1 << 10)
-#define PMX_GPIO_PIN0_MASK      (1 << 9)
-#define PMX_GPIO_PIN1_MASK      (1 << 8)
-#define PMX_GPIO_PIN2_MASK      (1 << 7)
-#define PMX_GPIO_PIN3_MASK      (1 << 6)
-#define PMX_GPIO_PIN4_MASK      (1 << 5)
-#define PMX_GPIO_PIN5_MASK      (1 << 4)
-#define PMX_UART0_MODEM_MASK    (1 << 3)
-#define PMX_UART0_MASK          (1 << 2)
-#define PMX_TIMER_3_4_MASK      (1 << 1)
-#define PMX_TIMER_1_2_MASK      (1 << 0)
-
-/* pad mux devices */
-extern struct pmx_dev spear3xx_pmx_firda;
-extern struct pmx_dev spear3xx_pmx_i2c;
-extern struct pmx_dev spear3xx_pmx_ssp_cs;
-extern struct pmx_dev spear3xx_pmx_ssp;
-extern struct pmx_dev spear3xx_pmx_mii;
-extern struct pmx_dev spear3xx_pmx_gpio_pin0;
-extern struct pmx_dev spear3xx_pmx_gpio_pin1;
-extern struct pmx_dev spear3xx_pmx_gpio_pin2;
-extern struct pmx_dev spear3xx_pmx_gpio_pin3;
-extern struct pmx_dev spear3xx_pmx_gpio_pin4;
-extern struct pmx_dev spear3xx_pmx_gpio_pin5;
-extern struct pmx_dev spear3xx_pmx_uart0_modem;
-extern struct pmx_dev spear3xx_pmx_uart0;
-extern struct pmx_dev spear3xx_pmx_timer_3_4;
-extern struct pmx_dev spear3xx_pmx_timer_1_2;
-
-#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
-/* padmux plgpio devices */
-extern struct pmx_dev spear3xx_pmx_plgpio_0_1;
-extern struct pmx_dev spear3xx_pmx_plgpio_2_3;
-extern struct pmx_dev spear3xx_pmx_plgpio_4_5;
-extern struct pmx_dev spear3xx_pmx_plgpio_6_9;
-extern struct pmx_dev spear3xx_pmx_plgpio_10_27;
-extern struct pmx_dev spear3xx_pmx_plgpio_28;
-extern struct pmx_dev spear3xx_pmx_plgpio_29;
-extern struct pmx_dev spear3xx_pmx_plgpio_30;
-extern struct pmx_dev spear3xx_pmx_plgpio_31;
-extern struct pmx_dev spear3xx_pmx_plgpio_32;
-extern struct pmx_dev spear3xx_pmx_plgpio_33;
-extern struct pmx_dev spear3xx_pmx_plgpio_34_36;
-extern struct pmx_dev spear3xx_pmx_plgpio_37_42;
-extern struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48;
-extern struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50;
-#endif
-
-/* spear300 declarations */
-#ifdef CONFIG_MACH_SPEAR300
-/* Add spear300 machine device structure declarations here */
-extern struct amba_device spear300_gpio1_device;
-
-/* pad mux modes */
-extern struct pmx_mode spear300_nand_mode;
-extern struct pmx_mode spear300_nor_mode;
-extern struct pmx_mode spear300_photo_frame_mode;
-extern struct pmx_mode spear300_lend_ip_phone_mode;
-extern struct pmx_mode spear300_hend_ip_phone_mode;
-extern struct pmx_mode spear300_lend_wifi_phone_mode;
-extern struct pmx_mode spear300_hend_wifi_phone_mode;
-extern struct pmx_mode spear300_ata_pabx_wi2s_mode;
-extern struct pmx_mode spear300_ata_pabx_i2s_mode;
-extern struct pmx_mode spear300_caml_lcdw_mode;
-extern struct pmx_mode spear300_camu_lcd_mode;
-extern struct pmx_mode spear300_camu_wlcd_mode;
-extern struct pmx_mode spear300_caml_lcd_mode;
-
-/* pad mux devices */
-extern struct pmx_dev spear300_pmx_fsmc_2_chips;
-extern struct pmx_dev spear300_pmx_fsmc_4_chips;
-extern struct pmx_dev spear300_pmx_keyboard;
-extern struct pmx_dev spear300_pmx_clcd;
-extern struct pmx_dev spear300_pmx_telecom_gpio;
-extern struct pmx_dev spear300_pmx_telecom_tdm;
-extern struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk;
-extern struct pmx_dev spear300_pmx_telecom_camera;
-extern struct pmx_dev spear300_pmx_telecom_dac;
-extern struct pmx_dev spear300_pmx_telecom_i2s;
-extern struct pmx_dev spear300_pmx_telecom_boot_pins;
-extern struct pmx_dev spear300_pmx_telecom_sdhci_4bit;
-extern struct pmx_dev spear300_pmx_telecom_sdhci_8bit;
-extern struct pmx_dev spear300_pmx_gpio1;
-
-/* Add spear300 machine function declarations here */
-void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-                u8 pmx_dev_count);
-
-#endif /* CONFIG_MACH_SPEAR300 */
-
-/* spear310 declarations */
-#ifdef CONFIG_MACH_SPEAR310
-/* Add spear310 machine device structure declarations here */
-
-/* pad mux devices */
-extern struct pmx_dev spear310_pmx_emi_cs_0_1_4_5;
-extern struct pmx_dev spear310_pmx_emi_cs_2_3;
-extern struct pmx_dev spear310_pmx_uart1;
-extern struct pmx_dev spear310_pmx_uart2;
-extern struct pmx_dev spear310_pmx_uart3_4_5;
-extern struct pmx_dev spear310_pmx_fsmc;
-extern struct pmx_dev spear310_pmx_rs485_0_1;
-extern struct pmx_dev spear310_pmx_tdm0;
-
-/* Add spear310 machine function declarations here */
-void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-                u8 pmx_dev_count);
-
-#endif /* CONFIG_MACH_SPEAR310 */
-
-/* spear320 declarations */
-#ifdef CONFIG_MACH_SPEAR320
-/* Add spear320 machine device structure declarations here */
-
-/* pad mux modes */
-extern struct pmx_mode spear320_auto_net_smii_mode;
-extern struct pmx_mode spear320_auto_net_mii_mode;
-extern struct pmx_mode spear320_auto_exp_mode;
-extern struct pmx_mode spear320_small_printers_mode;
-
-/* pad mux devices */
-extern struct pmx_dev spear320_pmx_clcd;
-extern struct pmx_dev spear320_pmx_emi;
-extern struct pmx_dev spear320_pmx_fsmc;
-extern struct pmx_dev spear320_pmx_spp;
-extern struct pmx_dev spear320_pmx_sdhci;
-extern struct pmx_dev spear320_pmx_i2s;
-extern struct pmx_dev spear320_pmx_uart1;
-extern struct pmx_dev spear320_pmx_uart1_modem;
-extern struct pmx_dev spear320_pmx_uart2;
-extern struct pmx_dev spear320_pmx_touchscreen;
-extern struct pmx_dev spear320_pmx_can;
-extern struct pmx_dev spear320_pmx_sdhci_led;
-extern struct pmx_dev spear320_pmx_pwm0;
-extern struct pmx_dev spear320_pmx_pwm1;
-extern struct pmx_dev spear320_pmx_pwm2;
-extern struct pmx_dev spear320_pmx_pwm3;
-extern struct pmx_dev spear320_pmx_ssp1;
-extern struct pmx_dev spear320_pmx_ssp2;
-extern struct pmx_dev spear320_pmx_mii1;
-extern struct pmx_dev spear320_pmx_smii0;
-extern struct pmx_dev spear320_pmx_smii1;
-extern struct pmx_dev spear320_pmx_i2c1;
-
-/* Add spear320 machine function declarations here */
-void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-                u8 pmx_dev_count);
-
-#endif /* CONFIG_MACH_SPEAR320 */
-
 #endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/hardware.h b/arch/arm/mach-spear3xx/include/mach/hardware.h
index 4660c0d8ec0d..40a8c178f10d 100644
--- a/arch/arm/mach-spear3xx/include/mach/hardware.h
+++ b/arch/arm/mach-spear3xx/include/mach/hardware.h
@@ -1,23 +1 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/hardware.h
- *
- * Hardware definitions for SPEAr3xx machine family
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_HARDWARE_H
-#define __MACH_HARDWARE_H
-
-#include <plat/hardware.h>
-#include <mach/spear.h>
-
-/* Vitual to physical translation of statically mapped space */
-#define IO_ADDRESS(x)           (x | 0xF0000000)
-
-#endif /* __MACH_HARDWARE_H */
+/* empty */
diff --git a/arch/arm/mach-spear3xx/include/mach/irqs.h b/arch/arm/mach-spear3xx/include/mach/irqs.h
index 6e265442808e..51bd62a0254c 100644
--- a/arch/arm/mach-spear3xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear3xx/include/mach/irqs.h
@@ -14,141 +14,14 @@
 #ifndef __MACH_IRQS_H
 #define __MACH_IRQS_H
 
-/* SPEAr3xx IRQ definitions */
-#define SPEAR3XX_IRQ_HW_ACCEL_MOD_0             0
+/* FIXME: probe all these from DT */
 #define SPEAR3XX_IRQ_INTRCOMM_RAS_ARM           1
-#define SPEAR3XX_IRQ_CPU_GPT1_1                 2
-#define SPEAR3XX_IRQ_CPU_GPT1_2                 3
-#define SPEAR3XX_IRQ_BASIC_GPT1_1               4
-#define SPEAR3XX_IRQ_BASIC_GPT1_2               5
-#define SPEAR3XX_IRQ_BASIC_GPT2_1               6
-#define SPEAR3XX_IRQ_BASIC_GPT2_2               7
-#define SPEAR3XX_IRQ_BASIC_DMA                  8
-#define SPEAR3XX_IRQ_BASIC_SMI                  9
-#define SPEAR3XX_IRQ_BASIC_RTC                  10
-#define SPEAR3XX_IRQ_BASIC_GPIO                 11
-#define SPEAR3XX_IRQ_BASIC_WDT                  12
-#define SPEAR3XX_IRQ_DDR_CONTROLLER             13
-#define SPEAR3XX_IRQ_SYS_ERROR                  14
-#define SPEAR3XX_IRQ_WAKEUP_RCV                 15
-#define SPEAR3XX_IRQ_JPEG                       16
-#define SPEAR3XX_IRQ_IRDA                       17
-#define SPEAR3XX_IRQ_ADC                        18
-#define SPEAR3XX_IRQ_UART                       19
-#define SPEAR3XX_IRQ_SSP                        20
-#define SPEAR3XX_IRQ_I2C                        21
-#define SPEAR3XX_IRQ_MAC_1                      22
-#define SPEAR3XX_IRQ_MAC_2                      23
-#define SPEAR3XX_IRQ_USB_DEV                    24
-#define SPEAR3XX_IRQ_USB_H_OHCI_0               25
-#define SPEAR3XX_IRQ_USB_H_EHCI_0               26
-#define SPEAR3XX_IRQ_USB_H_EHCI_1               SPEAR3XX_IRQ_USB_H_EHCI_0
-#define SPEAR3XX_IRQ_USB_H_OHCI_1               27
 #define SPEAR3XX_IRQ_GEN_RAS_1                  28
 #define SPEAR3XX_IRQ_GEN_RAS_2                  29
 #define SPEAR3XX_IRQ_GEN_RAS_3                  30
-#define SPEAR3XX_IRQ_HW_ACCEL_MOD_1             31
 #define SPEAR3XX_IRQ_VIC_END                    32
-
 #define SPEAR3XX_VIRQ_START                     SPEAR3XX_IRQ_VIC_END
 
-/* SPEAr300 Virtual irq definitions */
-/* IRQs sharing IRQ_GEN_RAS_1 */
-#define SPEAR300_VIRQ_IT_PERS_S                 (SPEAR3XX_VIRQ_START + 0)
-#define SPEAR300_VIRQ_IT_CHANGE_S               (SPEAR3XX_VIRQ_START + 1)
-#define SPEAR300_VIRQ_I2S                       (SPEAR3XX_VIRQ_START + 2)
-#define SPEAR300_VIRQ_TDM                       (SPEAR3XX_VIRQ_START + 3)
-#define SPEAR300_VIRQ_CAMERA_L                  (SPEAR3XX_VIRQ_START + 4)
-#define SPEAR300_VIRQ_CAMERA_F                  (SPEAR3XX_VIRQ_START + 5)
-#define SPEAR300_VIRQ_CAMERA_V                  (SPEAR3XX_VIRQ_START + 6)
-#define SPEAR300_VIRQ_KEYBOARD                  (SPEAR3XX_VIRQ_START + 7)
-#define SPEAR300_VIRQ_GPIO1                     (SPEAR3XX_VIRQ_START + 8)
-
-/* IRQs sharing IRQ_GEN_RAS_3 */
-#define SPEAR300_IRQ_CLCD                       SPEAR3XX_IRQ_GEN_RAS_3
-
-/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
-#define SPEAR300_IRQ_SDHCI                      SPEAR3XX_IRQ_INTRCOMM_RAS_ARM
-
-/* SPEAr310 Virtual irq definitions */
-/* IRQs sharing IRQ_GEN_RAS_1 */
-#define SPEAR310_VIRQ_SMII0                     (SPEAR3XX_VIRQ_START + 0)
-#define SPEAR310_VIRQ_SMII1                     (SPEAR3XX_VIRQ_START + 1)
-#define SPEAR310_VIRQ_SMII2                     (SPEAR3XX_VIRQ_START + 2)
-#define SPEAR310_VIRQ_SMII3                     (SPEAR3XX_VIRQ_START + 3)
-#define SPEAR310_VIRQ_WAKEUP_SMII0              (SPEAR3XX_VIRQ_START + 4)
-#define SPEAR310_VIRQ_WAKEUP_SMII1              (SPEAR3XX_VIRQ_START + 5)
-#define SPEAR310_VIRQ_WAKEUP_SMII2              (SPEAR3XX_VIRQ_START + 6)
-#define SPEAR310_VIRQ_WAKEUP_SMII3              (SPEAR3XX_VIRQ_START + 7)
-
-/* IRQs sharing IRQ_GEN_RAS_2 */
-#define SPEAR310_VIRQ_UART1                     (SPEAR3XX_VIRQ_START + 8)
-#define SPEAR310_VIRQ_UART2                     (SPEAR3XX_VIRQ_START + 9)
-#define SPEAR310_VIRQ_UART3                     (SPEAR3XX_VIRQ_START + 10)
-#define SPEAR310_VIRQ_UART4                     (SPEAR3XX_VIRQ_START + 11)
-#define SPEAR310_VIRQ_UART5                     (SPEAR3XX_VIRQ_START + 12)
-
-/* IRQs sharing IRQ_GEN_RAS_3 */
-#define SPEAR310_VIRQ_EMI                       (SPEAR3XX_VIRQ_START + 13)
-#define SPEAR310_VIRQ_PLGPIO                    (SPEAR3XX_VIRQ_START + 14)
-
-/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
-#define SPEAR310_VIRQ_TDM_HDLC                  (SPEAR3XX_VIRQ_START + 15)
-#define SPEAR310_VIRQ_RS485_0                   (SPEAR3XX_VIRQ_START + 16)
-#define SPEAR310_VIRQ_RS485_1                   (SPEAR3XX_VIRQ_START + 17)
-
-/* SPEAr320 Virtual irq definitions */
-/* IRQs sharing IRQ_GEN_RAS_1 */
-#define SPEAR320_VIRQ_EMI                       (SPEAR3XX_VIRQ_START + 0)
-#define SPEAR320_VIRQ_CLCD                      (SPEAR3XX_VIRQ_START + 1)
-#define SPEAR320_VIRQ_SPP                       (SPEAR3XX_VIRQ_START + 2)
-
-/* IRQs sharing IRQ_GEN_RAS_2 */
-#define SPEAR320_IRQ_SDHCI                      SPEAR3XX_IRQ_GEN_RAS_2
-
-/* IRQs sharing IRQ_GEN_RAS_3 */
-#define SPEAR320_VIRQ_PLGPIO                    (SPEAR3XX_VIRQ_START + 3)
-#define SPEAR320_VIRQ_I2S_PLAY                  (SPEAR3XX_VIRQ_START + 4)
-#define SPEAR320_VIRQ_I2S_REC                   (SPEAR3XX_VIRQ_START + 5)
-
-/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
-#define SPEAR320_VIRQ_CANU                      (SPEAR3XX_VIRQ_START + 6)
-#define SPEAR320_VIRQ_CANL                      (SPEAR3XX_VIRQ_START + 7)
-#define SPEAR320_VIRQ_UART1                     (SPEAR3XX_VIRQ_START + 8)
-#define SPEAR320_VIRQ_UART2                     (SPEAR3XX_VIRQ_START + 9)
-#define SPEAR320_VIRQ_SSP1                      (SPEAR3XX_VIRQ_START + 10)
-#define SPEAR320_VIRQ_SSP2                      (SPEAR3XX_VIRQ_START + 11)
-#define SPEAR320_VIRQ_SMII0                     (SPEAR3XX_VIRQ_START + 12)
-#define SPEAR320_VIRQ_MII1_SMII1                (SPEAR3XX_VIRQ_START + 13)
-#define SPEAR320_VIRQ_WAKEUP_SMII0              (SPEAR3XX_VIRQ_START + 14)
-#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1         (SPEAR3XX_VIRQ_START + 15)
-#define SPEAR320_VIRQ_I2C1                      (SPEAR3XX_VIRQ_START + 16)
-
-/*
- * GPIO pins virtual irqs
- * Use the lowest number for the GPIO virtual IRQs base on which subarchs
- * we have compiled in
- */
-#if defined(CONFIG_MACH_SPEAR310)
-#define SPEAR3XX_GPIO_INT_BASE                  (SPEAR3XX_VIRQ_START + 18)
-#elif defined(CONFIG_MACH_SPEAR320)
-#define SPEAR3XX_GPIO_INT_BASE                  (SPEAR3XX_VIRQ_START + 17)
-#else
-#define SPEAR3XX_GPIO_INT_BASE                  (SPEAR3XX_VIRQ_START + 9)
-#endif
-
-#define SPEAR300_GPIO1_INT_BASE                 (SPEAR3XX_GPIO_INT_BASE + 8)
-#define SPEAR3XX_PLGPIO_COUNT   102
-
-#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
-#define SPEAR3XX_PLGPIO_INT_BASE                (SPEAR3XX_GPIO_INT_BASE + 8)
-#define SPEAR3XX_GPIO_INT_END                   (SPEAR3XX_PLGPIO_INT_BASE + \
-                                                        SPEAR3XX_PLGPIO_COUNT)
-#else
-#define SPEAR3XX_GPIO_INT_END   (SPEAR300_GPIO1_INT_BASE + 8)
-#endif
-
-#define SPEAR3XX_VIRQ_END       SPEAR3XX_GPIO_INT_END
-#define NR_IRQS                 SPEAR3XX_VIRQ_END
+#define NR_IRQS                 160
 
 #endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/misc_regs.h b/arch/arm/mach-spear3xx/include/mach/misc_regs.h
index 5bd8cd8d4852..18e2ac576f25 100644
--- a/arch/arm/mach-spear3xx/include/mach/misc_regs.h
+++ b/arch/arm/mach-spear3xx/include/mach/misc_regs.h
@@ -14,151 +14,9 @@
 #ifndef __MACH_MISC_REGS_H
 #define __MACH_MISC_REGS_H
 
-#include <mach/hardware.h>
+#include <mach/spear.h>
 
 #define MISC_BASE               IOMEM(VA_SPEAR3XX_ICM3_MISC_REG_BASE)
-
-#define SOC_CFG_CTR             (MISC_BASE + 0x000)
-#define DIAG_CFG_CTR            (MISC_BASE + 0x004)
-#define PLL1_CTR                (MISC_BASE + 0x008)
-#define PLL1_FRQ                (MISC_BASE + 0x00C)
-#define PLL1_MOD                (MISC_BASE + 0x010)
-#define PLL2_CTR                (MISC_BASE + 0x014)
-/* PLL_CTR register masks */
-#define PLL_ENABLE              2
-#define PLL_MODE_SHIFT          4
-#define PLL_MODE_MASK           0x3
-#define PLL_MODE_NORMAL         0
-#define PLL_MODE_FRACTION       1
-#define PLL_MODE_DITH_DSB       2
-#define PLL_MODE_DITH_SSB       3
-
-#define PLL2_FRQ                (MISC_BASE + 0x018)
-/* PLL FRQ register masks */
-#define PLL_DIV_N_SHIFT         0
-#define PLL_DIV_N_MASK          0xFF
-#define PLL_DIV_P_SHIFT         8
-#define PLL_DIV_P_MASK          0x7
-#define PLL_NORM_FDBK_M_SHIFT   24
-#define PLL_NORM_FDBK_M_MASK    0xFF
-#define PLL_DITH_FDBK_M_SHIFT   16
-#define PLL_DITH_FDBK_M_MASK    0xFFFF
-
-#define PLL2_MOD                (MISC_BASE + 0x01C)
-#define PLL_CLK_CFG             (MISC_BASE + 0x020)
-#define CORE_CLK_CFG            (MISC_BASE + 0x024)
-/* CORE CLK CFG register masks */
-#define PLL_HCLK_RATIO_SHIFT    10
-#define PLL_HCLK_RATIO_MASK     0x3
-#define HCLK_PCLK_RATIO_SHIFT   8
-#define HCLK_PCLK_RATIO_MASK    0x3
-
-#define PERIP_CLK_CFG           (MISC_BASE + 0x028)
-/* PERIP_CLK_CFG register masks */
-#define UART_CLK_SHIFT          4
-#define UART_CLK_MASK           0x1
-#define FIRDA_CLK_SHIFT         5
-#define FIRDA_CLK_MASK          0x3
-#define GPT0_CLK_SHIFT          8
-#define GPT1_CLK_SHIFT          11
-#define GPT2_CLK_SHIFT          12
-#define GPT_CLK_MASK            0x1
-#define AUX_CLK_PLL3_VAL        0
-#define AUX_CLK_PLL1_VAL        1
-
-#define PERIP1_CLK_ENB          (MISC_BASE + 0x02C)
-/* PERIP1_CLK_ENB register masks */
-#define UART_CLK_ENB            3
-#define SSP_CLK_ENB             5
-#define I2C_CLK_ENB             7
-#define JPEG_CLK_ENB            8
-#define FIRDA_CLK_ENB           10
-#define GPT1_CLK_ENB            11
-#define GPT2_CLK_ENB            12
-#define ADC_CLK_ENB             15
-#define RTC_CLK_ENB             17
-#define GPIO_CLK_ENB            18
-#define DMA_CLK_ENB             19
-#define SMI_CLK_ENB             21
-#define GMAC_CLK_ENB            23
-#define USBD_CLK_ENB            24
-#define USBH_CLK_ENB            25
-#define C3_CLK_ENB              31
-
-#define SOC_CORE_ID             (MISC_BASE + 0x030)
-#define RAS_CLK_ENB             (MISC_BASE + 0x034)
-#define PERIP1_SOF_RST          (MISC_BASE + 0x038)
-/* PERIP1_SOF_RST register masks */
-#define JPEG_SOF_RST            8
-
-#define SOC_USER_ID             (MISC_BASE + 0x03C)
-#define RAS_SOF_RST             (MISC_BASE + 0x040)
-#define PRSC1_CLK_CFG           (MISC_BASE + 0x044)
-#define PRSC2_CLK_CFG           (MISC_BASE + 0x048)
-#define PRSC3_CLK_CFG           (MISC_BASE + 0x04C)
-/* gpt synthesizer register masks */
-#define GPT_MSCALE_SHIFT        0
-#define GPT_MSCALE_MASK         0xFFF
-#define GPT_NSCALE_SHIFT        12
-#define GPT_NSCALE_MASK         0xF
-
-#define AMEM_CLK_CFG            (MISC_BASE + 0x050)
-#define EXPI_CLK_CFG            (MISC_BASE + 0x054)
-#define CLCD_CLK_SYNT           (MISC_BASE + 0x05C)
-#define FIRDA_CLK_SYNT          (MISC_BASE + 0x060)
-#define UART_CLK_SYNT           (MISC_BASE + 0x064)
-#define GMAC_CLK_SYNT           (MISC_BASE + 0x068)
-#define RAS1_CLK_SYNT           (MISC_BASE + 0x06C)
-#define RAS2_CLK_SYNT           (MISC_BASE + 0x070)
-#define RAS3_CLK_SYNT           (MISC_BASE + 0x074)
-#define RAS4_CLK_SYNT           (MISC_BASE + 0x078)
-/* aux clk synthesiser register masks for irda to ras4 */
-#define AUX_SYNT_ENB            31
-#define AUX_EQ_SEL_SHIFT        30
-#define AUX_EQ_SEL_MASK         1
-#define AUX_EQ1_SEL             0
-#define AUX_EQ2_SEL             1
-#define AUX_XSCALE_SHIFT        16
-#define AUX_XSCALE_MASK         0xFFF
-#define AUX_YSCALE_SHIFT        0
-#define AUX_YSCALE_MASK         0xFFF
-
-#define ICM1_ARB_CFG            (MISC_BASE + 0x07C)
-#define ICM2_ARB_CFG            (MISC_BASE + 0x080)
-#define ICM3_ARB_CFG            (MISC_BASE + 0x084)
-#define ICM4_ARB_CFG            (MISC_BASE + 0x088)
-#define ICM5_ARB_CFG            (MISC_BASE + 0x08C)
-#define ICM6_ARB_CFG            (MISC_BASE + 0x090)
-#define ICM7_ARB_CFG            (MISC_BASE + 0x094)
-#define ICM8_ARB_CFG            (MISC_BASE + 0x098)
-#define ICM9_ARB_CFG            (MISC_BASE + 0x09C)
 #define DMA_CHN_CFG             (MISC_BASE + 0x0A0)
-#define USB2_PHY_CFG            (MISC_BASE + 0x0A4)
-#define GMAC_CFG_CTR            (MISC_BASE + 0x0A8)
-#define EXPI_CFG_CTR            (MISC_BASE + 0x0AC)
-#define PRC1_LOCK_CTR           (MISC_BASE + 0x0C0)
-#define PRC2_LOCK_CTR           (MISC_BASE + 0x0C4)
-#define PRC3_LOCK_CTR           (MISC_BASE + 0x0C8)
-#define PRC4_LOCK_CTR           (MISC_BASE + 0x0CC)
-#define PRC1_IRQ_CTR            (MISC_BASE + 0x0D0)
-#define PRC2_IRQ_CTR            (MISC_BASE + 0x0D4)
-#define PRC3_IRQ_CTR            (MISC_BASE + 0x0D8)
-#define PRC4_IRQ_CTR            (MISC_BASE + 0x0DC)
-#define PWRDOWN_CFG_CTR         (MISC_BASE + 0x0E0)
-#define COMPSSTL_1V8_CFG        (MISC_BASE + 0x0E4)
-#define COMPSSTL_2V5_CFG        (MISC_BASE + 0x0E8)
-#define COMPCOR_3V3_CFG         (MISC_BASE + 0x0EC)
-#define SSTLPAD_CFG_CTR         (MISC_BASE + 0x0F0)
-#define BIST1_CFG_CTR           (MISC_BASE + 0x0F4)
-#define BIST2_CFG_CTR           (MISC_BASE + 0x0F8)
-#define BIST3_CFG_CTR           (MISC_BASE + 0x0FC)
-#define BIST4_CFG_CTR           (MISC_BASE + 0x100)
-#define BIST5_CFG_CTR           (MISC_BASE + 0x104)
-#define BIST1_STS_RES           (MISC_BASE + 0x108)
-#define BIST2_STS_RES           (MISC_BASE + 0x10C)
-#define BIST3_STS_RES           (MISC_BASE + 0x110)
-#define BIST4_STS_RES           (MISC_BASE + 0x114)
-#define BIST5_STS_RES           (MISC_BASE + 0x118)
-#define SYSERR_CFG_CTR          (MISC_BASE + 0x11C)
 
 #endif /* __MACH_MISC_REGS_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear.h b/arch/arm/mach-spear3xx/include/mach/spear.h
index 63fd98356919..51eb953148a9 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear.h
@@ -15,60 +15,26 @@
 #define __MACH_SPEAR3XX_H
 
 #include <asm/memory.h>
-#include <mach/spear300.h>
-#include <mach/spear310.h>
-#include <mach/spear320.h>
-
-#define SPEAR3XX_ML_SDRAM_BASE          UL(0x00000000)
-
-#define SPEAR3XX_ICM9_BASE              UL(0xC0000000)
 
 /* ICM1 - Low speed connection */
 #define SPEAR3XX_ICM1_2_BASE            UL(0xD0000000)
+#define VA_SPEAR3XX_ICM1_2_BASE         UL(0xFD000000)
 #define SPEAR3XX_ICM1_UART_BASE         UL(0xD0000000)
-#define VA_SPEAR3XX_ICM1_UART_BASE      IO_ADDRESS(SPEAR3XX_ICM1_UART_BASE)
-#define SPEAR3XX_ICM1_ADC_BASE          UL(0xD0080000)
+#define VA_SPEAR3XX_ICM1_UART_BASE      (VA_SPEAR3XX_ICM1_2_BASE | SPEAR3XX_ICM1_UART_BASE)
 #define SPEAR3XX_ICM1_SSP_BASE          UL(0xD0100000)
-#define SPEAR3XX_ICM1_I2C_BASE          UL(0xD0180000)
-#define SPEAR3XX_ICM1_JPEG_BASE         UL(0xD0800000)
-#define SPEAR3XX_ICM1_IRDA_BASE         UL(0xD1000000)
-#define SPEAR3XX_ICM1_SRAM_BASE         UL(0xD2800000)
-
-/* ICM2 - Application Subsystem */
-#define SPEAR3XX_ICM2_HWACCEL0_BASE     UL(0xD8800000)
-#define SPEAR3XX_ICM2_HWACCEL1_BASE     UL(0xD9000000)
-
-/* ICM4 - High Speed Connection */
-#define SPEAR3XX_ICM4_BASE              UL(0xE0000000)
-#define SPEAR3XX_ICM4_MII_BASE          UL(0xE0800000)
-#define SPEAR3XX_ICM4_USBD_FIFO_BASE    UL(0xE1000000)
-#define SPEAR3XX_ICM4_USBD_CSR_BASE     UL(0xE1100000)
-#define SPEAR3XX_ICM4_USBD_PLDT_BASE    UL(0xE1200000)
-#define SPEAR3XX_ICM4_USB_EHCI0_1_BASE  UL(0xE1800000)
-#define SPEAR3XX_ICM4_USB_OHCI0_BASE    UL(0xE1900000)
-#define SPEAR3XX_ICM4_USB_OHCI1_BASE    UL(0xE2100000)
-#define SPEAR3XX_ICM4_USB_ARB_BASE      UL(0xE2800000)
 
 /* ML1 - Multi Layer CPU Subsystem */
 #define SPEAR3XX_ICM3_ML1_2_BASE        UL(0xF0000000)
-#define SPEAR3XX_ML1_TMR_BASE           UL(0xF0000000)
-#define SPEAR3XX_ML1_VIC_BASE           UL(0xF1100000)
-#define VA_SPEAR3XX_ML1_VIC_BASE        IO_ADDRESS(SPEAR3XX_ML1_VIC_BASE)
+#define VA_SPEAR6XX_ML_CPU_BASE         UL(0xF0000000)
 
 /* ICM3 - Basic Subsystem */
-#define SPEAR3XX_ICM3_SMEM_BASE         UL(0xF8000000)
 #define SPEAR3XX_ICM3_SMI_CTRL_BASE     UL(0xFC000000)
+#define VA_SPEAR3XX_ICM3_SMI_CTRL_BASE  UL(0xFC000000)
 #define SPEAR3XX_ICM3_DMA_BASE          UL(0xFC400000)
-#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE   UL(0xFC600000)
-#define SPEAR3XX_ICM3_TMR0_BASE         UL(0xFC800000)
-#define SPEAR3XX_ICM3_WDT_BASE          UL(0xFC880000)
-#define SPEAR3XX_ICM3_RTC_BASE          UL(0xFC900000)
-#define SPEAR3XX_ICM3_GPIO_BASE         UL(0xFC980000)
 #define SPEAR3XX_ICM3_SYS_CTRL_BASE     UL(0xFCA00000)
-#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE  IO_ADDRESS(SPEAR3XX_ICM3_SYS_CTRL_BASE)
+#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE  (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_SYS_CTRL_BASE)
 #define SPEAR3XX_ICM3_MISC_REG_BASE     UL(0xFCA80000)
-#define VA_SPEAR3XX_ICM3_MISC_REG_BASE  IO_ADDRESS(SPEAR3XX_ICM3_MISC_REG_BASE)
-#define SPEAR3XX_ICM3_TMR1_BASE         UL(0xFCB00000)
+#define VA_SPEAR3XX_ICM3_MISC_REG_BASE  (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_MISC_REG_BASE)
 
 /* Debug uart for linux, will be used for debug and uncompress messages */
 #define SPEAR_DBG_UART_BASE             SPEAR3XX_ICM1_UART_BASE
@@ -78,4 +44,17 @@
 #define SPEAR_SYS_CTRL_BASE             SPEAR3XX_ICM3_SYS_CTRL_BASE
 #define VA_SPEAR_SYS_CTRL_BASE          VA_SPEAR3XX_ICM3_SYS_CTRL_BASE
 
+/* SPEAr320 Macros */
+#define SPEAR320_SOC_CONFIG_BASE        UL(0xB3000000)
+#define VA_SPEAR320_SOC_CONFIG_BASE     UL(0xFE000000)
+#define SPEAR320_CONTROL_REG            IOMEM(VA_SPEAR320_SOC_CONFIG_BASE)
+#define SPEAR320_EXT_CTRL_REG           IOMEM(VA_SPEAR320_SOC_CONFIG_BASE + 0x0018)
+        #define SPEAR320_UARTX_PCLK_MASK                0x1
+        #define SPEAR320_UART2_PCLK_SHIFT               8
+        #define SPEAR320_UART3_PCLK_SHIFT               9
+        #define SPEAR320_UART4_PCLK_SHIFT               10
+        #define SPEAR320_UART5_PCLK_SHIFT               11
+        #define SPEAR320_UART6_PCLK_SHIFT               12
+        #define SPEAR320_RS485_PCLK_SHIFT               13
+
 #endif /* __MACH_SPEAR3XX_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear300.h b/arch/arm/mach-spear3xx/include/mach/spear300.h
deleted file mode 100644
index 3b6ea0729040..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/spear300.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/spear300.h
- *
- * SPEAr300 Machine specific definition
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifdef  CONFIG_MACH_SPEAR300
-
-#ifndef __MACH_SPEAR300_H
-#define __MACH_SPEAR300_H
-
-/* Base address of various IPs */
-#define SPEAR300_TELECOM_BASE           UL(0x50000000)
-
-/* Interrupt registers offsets and masks */
-#define SPEAR300_INT_ENB_MASK_REG       0x54
-#define SPEAR300_INT_STS_MASK_REG       0x58
-#define SPEAR300_IT_PERS_S_IRQ_MASK     (1 << 0)
-#define SPEAR300_IT_CHANGE_S_IRQ_MASK   (1 << 1)
-#define SPEAR300_I2S_IRQ_MASK           (1 << 2)
-#define SPEAR300_TDM_IRQ_MASK           (1 << 3)
-#define SPEAR300_CAMERA_L_IRQ_MASK      (1 << 4)
-#define SPEAR300_CAMERA_F_IRQ_MASK      (1 << 5)
-#define SPEAR300_CAMERA_V_IRQ_MASK      (1 << 6)
-#define SPEAR300_KEYBOARD_IRQ_MASK      (1 << 7)
-#define SPEAR300_GPIO1_IRQ_MASK         (1 << 8)
-
-#define SPEAR300_SHIRQ_RAS1_MASK        0x1FF
-
-#define SPEAR300_CLCD_BASE              UL(0x60000000)
-#define SPEAR300_SDHCI_BASE             UL(0x70000000)
-#define SPEAR300_NAND_0_BASE            UL(0x80000000)
-#define SPEAR300_NAND_1_BASE            UL(0x84000000)
-#define SPEAR300_NAND_2_BASE            UL(0x88000000)
-#define SPEAR300_NAND_3_BASE            UL(0x8c000000)
-#define SPEAR300_NOR_0_BASE             UL(0x90000000)
-#define SPEAR300_NOR_1_BASE             UL(0x91000000)
-#define SPEAR300_NOR_2_BASE             UL(0x92000000)
-#define SPEAR300_NOR_3_BASE             UL(0x93000000)
-#define SPEAR300_FSMC_BASE              UL(0x94000000)
-#define SPEAR300_SOC_CONFIG_BASE        UL(0x99000000)
-#define SPEAR300_KEYBOARD_BASE          UL(0xA0000000)
-#define SPEAR300_GPIO_BASE              UL(0xA9000000)
-
-#endif /* __MACH_SPEAR300_H */
-
-#endif /* CONFIG_MACH_SPEAR300 */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear310.h b/arch/arm/mach-spear3xx/include/mach/spear310.h
deleted file mode 100644
index 1567d0da725f..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/spear310.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/spear310.h
- *
- * SPEAr310 Machine specific definition
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifdef  CONFIG_MACH_SPEAR310
-
-#ifndef __MACH_SPEAR310_H
-#define __MACH_SPEAR310_H
-
-#define SPEAR310_NAND_BASE              UL(0x40000000)
-#define SPEAR310_FSMC_BASE              UL(0x44000000)
-#define SPEAR310_UART1_BASE             UL(0xB2000000)
-#define SPEAR310_UART2_BASE             UL(0xB2080000)
-#define SPEAR310_UART3_BASE             UL(0xB2100000)
-#define SPEAR310_UART4_BASE             UL(0xB2180000)
-#define SPEAR310_UART5_BASE             UL(0xB2200000)
-#define SPEAR310_HDLC_BASE              UL(0xB2800000)
-#define SPEAR310_RS485_0_BASE           UL(0xB3000000)
-#define SPEAR310_RS485_1_BASE           UL(0xB3800000)
-#define SPEAR310_SOC_CONFIG_BASE        UL(0xB4000000)
-
-/* Interrupt registers offsets and masks */
-#define SPEAR310_INT_STS_MASK_REG       0x04
-#define SPEAR310_SMII0_IRQ_MASK         (1 << 0)
-#define SPEAR310_SMII1_IRQ_MASK         (1 << 1)
-#define SPEAR310_SMII2_IRQ_MASK         (1 << 2)
-#define SPEAR310_SMII3_IRQ_MASK         (1 << 3)
-#define SPEAR310_WAKEUP_SMII0_IRQ_MASK  (1 << 4)
-#define SPEAR310_WAKEUP_SMII1_IRQ_MASK  (1 << 5)
-#define SPEAR310_WAKEUP_SMII2_IRQ_MASK  (1 << 6)
-#define SPEAR310_WAKEUP_SMII3_IRQ_MASK  (1 << 7)
-#define SPEAR310_UART1_IRQ_MASK         (1 << 8)
-#define SPEAR310_UART2_IRQ_MASK         (1 << 9)
-#define SPEAR310_UART3_IRQ_MASK         (1 << 10)
-#define SPEAR310_UART4_IRQ_MASK         (1 << 11)
-#define SPEAR310_UART5_IRQ_MASK         (1 << 12)
-#define SPEAR310_EMI_IRQ_MASK           (1 << 13)
-#define SPEAR310_TDM_HDLC_IRQ_MASK      (1 << 14)
-#define SPEAR310_RS485_0_IRQ_MASK       (1 << 15)
-#define SPEAR310_RS485_1_IRQ_MASK       (1 << 16)
-
-#define SPEAR310_SHIRQ_RAS1_MASK        0x000FF
-#define SPEAR310_SHIRQ_RAS2_MASK        0x01F00
-#define SPEAR310_SHIRQ_RAS3_MASK        0x02000
-#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK        0x1C000
-
-#endif /* __MACH_SPEAR310_H */
-
-#endif /* CONFIG_MACH_SPEAR310 */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h
deleted file mode 100644
index 8cfa83fa1296..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/spear320.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/spear320.h
- *
- * SPEAr320 Machine specific definition
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifdef  CONFIG_MACH_SPEAR320
-
-#ifndef __MACH_SPEAR320_H
-#define __MACH_SPEAR320_H
-
-#define SPEAR320_EMI_CTRL_BASE          UL(0x40000000)
-#define SPEAR320_FSMC_BASE              UL(0x4C000000)
-#define SPEAR320_NAND_BASE              UL(0x50000000)
-#define SPEAR320_I2S_BASE               UL(0x60000000)
-#define SPEAR320_SDHCI_BASE             UL(0x70000000)
-#define SPEAR320_CLCD_BASE              UL(0x90000000)
-#define SPEAR320_PAR_PORT_BASE          UL(0xA0000000)
-#define SPEAR320_CAN0_BASE              UL(0xA1000000)
-#define SPEAR320_CAN1_BASE              UL(0xA2000000)
-#define SPEAR320_UART1_BASE             UL(0xA3000000)
-#define SPEAR320_UART2_BASE             UL(0xA4000000)
-#define SPEAR320_SSP0_BASE              UL(0xA5000000)
-#define SPEAR320_SSP1_BASE              UL(0xA6000000)
-#define SPEAR320_I2C_BASE               UL(0xA7000000)
-#define SPEAR320_PWM_BASE               UL(0xA8000000)
-#define SPEAR320_SMII0_BASE             UL(0xAA000000)
-#define SPEAR320_SMII1_BASE             UL(0xAB000000)
-#define SPEAR320_SOC_CONFIG_BASE        UL(0xB3000000)
-
-/* Interrupt registers offsets and masks */
-#define SPEAR320_INT_STS_MASK_REG               0x04
-#define SPEAR320_INT_CLR_MASK_REG               0x04
-#define SPEAR320_INT_ENB_MASK_REG               0x08
-#define SPEAR320_GPIO_IRQ_MASK                  (1 << 0)
-#define SPEAR320_I2S_PLAY_IRQ_MASK              (1 << 1)
-#define SPEAR320_I2S_REC_IRQ_MASK               (1 << 2)
-#define SPEAR320_EMI_IRQ_MASK                   (1 << 7)
-#define SPEAR320_CLCD_IRQ_MASK                  (1 << 8)
-#define SPEAR320_SPP_IRQ_MASK                   (1 << 9)
-#define SPEAR320_SDHCI_IRQ_MASK                 (1 << 10)
-#define SPEAR320_CAN_U_IRQ_MASK                 (1 << 11)
-#define SPEAR320_CAN_L_IRQ_MASK                 (1 << 12)
-#define SPEAR320_UART1_IRQ_MASK                 (1 << 13)
-#define SPEAR320_UART2_IRQ_MASK                 (1 << 14)
-#define SPEAR320_SSP1_IRQ_MASK                  (1 << 15)
-#define SPEAR320_SSP2_IRQ_MASK                  (1 << 16)
-#define SPEAR320_SMII0_IRQ_MASK                 (1 << 17)
-#define SPEAR320_MII1_SMII1_IRQ_MASK            (1 << 18)
-#define SPEAR320_WAKEUP_SMII0_IRQ_MASK          (1 << 19)
-#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK     (1 << 20)
-#define SPEAR320_I2C1_IRQ_MASK                  (1 << 21)
-
-#define SPEAR320_SHIRQ_RAS1_MASK                0x000380
-#define SPEAR320_SHIRQ_RAS3_MASK                0x000007
-#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK        0x3FF800
-
-#endif /* __MACH_SPEAR320_H */
-
-#endif /* CONFIG_MACH_SPEAR320 */
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index f7db66812abb..f74a05bdb829 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -3,372 +3,62 @@
  *
  * SPEAr300 machine source file
  *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
+ * Copyright (C) 2009-2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
 
-#include <linux/types.h>
-#include <linux/amba/pl061.h>
-#include <linux/ptrace.h>
-#include <asm/irq.h>
+#define pr_fmt(fmt) "SPEAr300: " fmt
+
+#include <linux/amba/pl08x.h>
+#include <linux/of_platform.h>
+#include <asm/hardware/vic.h>
+#include <asm/mach/arch.h>
 #include <plat/shirq.h>
 #include <mach/generic.h>
-#include <mach/hardware.h>
-
-/* pad multiplexing support */
-/* muxing registers */
-#define PAD_MUX_CONFIG_REG      0x00
-#define MODE_CONFIG_REG         0x04
-
-/* modes */
-#define NAND_MODE                       (1 << 0)
-#define NOR_MODE                        (1 << 1)
-#define PHOTO_FRAME_MODE                (1 << 2)
-#define LEND_IP_PHONE_MODE              (1 << 3)
-#define HEND_IP_PHONE_MODE              (1 << 4)
-#define LEND_WIFI_PHONE_MODE            (1 << 5)
-#define HEND_WIFI_PHONE_MODE            (1 << 6)
-#define ATA_PABX_WI2S_MODE              (1 << 7)
-#define ATA_PABX_I2S_MODE               (1 << 8)
-#define CAML_LCDW_MODE                  (1 << 9)
-#define CAMU_LCD_MODE                   (1 << 10)
-#define CAMU_WLCD_MODE                  (1 << 11)
-#define CAML_LCD_MODE                   (1 << 12)
-#define ALL_MODES                       0x1FFF
-
-struct pmx_mode spear300_nand_mode = {
-        .id = NAND_MODE,
-        .name = "nand mode",
-        .mask = 0x00,
-};
-
-struct pmx_mode spear300_nor_mode = {
-        .id = NOR_MODE,
-        .name = "nor mode",
-        .mask = 0x01,
-};
-
-struct pmx_mode spear300_photo_frame_mode = {
-        .id = PHOTO_FRAME_MODE,
-        .name = "photo frame mode",
-        .mask = 0x02,
-};
-
-struct pmx_mode spear300_lend_ip_phone_mode = {
-        .id = LEND_IP_PHONE_MODE,
-        .name = "lend ip phone mode",
-        .mask = 0x03,
-};
-
-struct pmx_mode spear300_hend_ip_phone_mode = {
-        .id = HEND_IP_PHONE_MODE,
-        .name = "hend ip phone mode",
-        .mask = 0x04,
-};
-
-struct pmx_mode spear300_lend_wifi_phone_mode = {
-        .id = LEND_WIFI_PHONE_MODE,
-        .name = "lend wifi phone mode",
-        .mask = 0x05,
-};
-
-struct pmx_mode spear300_hend_wifi_phone_mode = {
-        .id = HEND_WIFI_PHONE_MODE,
-        .name = "hend wifi phone mode",
-        .mask = 0x06,
-};
-
-struct pmx_mode spear300_ata_pabx_wi2s_mode = {
-        .id = ATA_PABX_WI2S_MODE,
-        .name = "ata pabx wi2s mode",
-        .mask = 0x07,
-};
-
-struct pmx_mode spear300_ata_pabx_i2s_mode = {
-        .id = ATA_PABX_I2S_MODE,
-        .name = "ata pabx i2s mode",
-        .mask = 0x08,
-};
-
-struct pmx_mode spear300_caml_lcdw_mode = {
-        .id = CAML_LCDW_MODE,
-        .name = "caml lcdw mode",
-        .mask = 0x0C,
-};
-
-struct pmx_mode spear300_camu_lcd_mode = {
-        .id = CAMU_LCD_MODE,
-        .name = "camu lcd mode",
-        .mask = 0x0D,
-};
-
-struct pmx_mode spear300_camu_wlcd_mode = {
-        .id = CAMU_WLCD_MODE,
-        .name = "camu wlcd mode",
-        .mask = 0x0E,
-};
-
-struct pmx_mode spear300_caml_lcd_mode = {
-        .id = CAML_LCD_MODE,
-        .name = "caml lcd mode",
-        .mask = 0x0F,
-};
-
-/* devices */
-static struct pmx_dev_mode pmx_fsmc_2_chips_modes[] = {
-        {
-                .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
-                        ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
-                .mask = PMX_FIRDA_MASK,
-        },
-};
-
-struct pmx_dev spear300_pmx_fsmc_2_chips = {
-        .name = "fsmc_2_chips",
-        .modes = pmx_fsmc_2_chips_modes,
-        .mode_count = ARRAY_SIZE(pmx_fsmc_2_chips_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_fsmc_4_chips_modes[] = {
-        {
-                .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
-                        ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
-                .mask = PMX_FIRDA_MASK | PMX_UART0_MASK,
-        },
-};
-
-struct pmx_dev spear300_pmx_fsmc_4_chips = {
-        .name = "fsmc_4_chips",
-        .modes = pmx_fsmc_4_chips_modes,
-        .mode_count = ARRAY_SIZE(pmx_fsmc_4_chips_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_keyboard_modes[] = {
-        {
-                .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
-                        LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
-                        CAML_LCDW_MODE | CAMU_LCD_MODE | CAMU_WLCD_MODE |
-                        CAML_LCD_MODE,
-                .mask = 0x0,
-        },
-};
-
-struct pmx_dev spear300_pmx_keyboard = {
-        .name = "keyboard",
-        .modes = pmx_keyboard_modes,
-        .mode_count = ARRAY_SIZE(pmx_keyboard_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_clcd_modes[] = {
-        {
-                .ids = PHOTO_FRAME_MODE,
-                .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK ,
-        }, {
-                .ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE |
-                        CAMU_LCD_MODE | CAML_LCD_MODE,
-                .mask = PMX_TIMER_3_4_MASK,
-        },
-};
-
-struct pmx_dev spear300_pmx_clcd = {
-        .name = "clcd",
-        .modes = pmx_clcd_modes,
-        .mode_count = ARRAY_SIZE(pmx_clcd_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_telecom_gpio_modes[] = {
-        {
-                .ids = PHOTO_FRAME_MODE | CAMU_LCD_MODE | CAML_LCD_MODE,
-                .mask = PMX_MII_MASK,
-        }, {
-                .ids = LEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE,
-                .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
-        }, {
-                .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_WLCD_MODE,
-                .mask = PMX_MII_MASK | PMX_TIMER_3_4_MASK,
-        }, {
-                .ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE,
-                .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK,
-        }, {
-                .ids = ATA_PABX_WI2S_MODE,
-                .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK
-                        | PMX_UART0_MODEM_MASK,
-        },
-};
-
-struct pmx_dev spear300_pmx_telecom_gpio = {
-        .name = "telecom_gpio",
-        .modes = pmx_telecom_gpio_modes,
-        .mode_count = ARRAY_SIZE(pmx_telecom_gpio_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_telecom_tdm_modes[] = {
-        {
-                .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
-                        HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE
-                        | HEND_WIFI_PHONE_MODE | ATA_PABX_WI2S_MODE
-                        | ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
-                        | CAMU_WLCD_MODE | CAML_LCD_MODE,
-                .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
-        },
-};
-
-struct pmx_dev spear300_pmx_telecom_tdm = {
-        .name = "telecom_tdm",
-        .modes = pmx_telecom_tdm_modes,
-        .mode_count = ARRAY_SIZE(pmx_telecom_tdm_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_telecom_spi_cs_i2c_clk_modes[] = {
-        {
-                .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
-                        LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE
-                        | ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE |
-                        CAML_LCDW_MODE | CAML_LCD_MODE,
-                .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
-        },
-};
-
-struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk = {
-        .name = "telecom_spi_cs_i2c_clk",
-        .modes = pmx_telecom_spi_cs_i2c_clk_modes,
-        .mode_count = ARRAY_SIZE(pmx_telecom_spi_cs_i2c_clk_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_telecom_camera_modes[] = {
-        {
-                .ids = CAML_LCDW_MODE | CAML_LCD_MODE,
-                .mask = PMX_MII_MASK,
-        }, {
-                .ids = CAMU_LCD_MODE | CAMU_WLCD_MODE,
-                .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK | PMX_MII_MASK,
-        },
-};
-
-struct pmx_dev spear300_pmx_telecom_camera = {
-        .name = "telecom_camera",
-        .modes = pmx_telecom_camera_modes,
-        .mode_count = ARRAY_SIZE(pmx_telecom_camera_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_telecom_dac_modes[] = {
-        {
-                .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
-                        | CAMU_WLCD_MODE | CAML_LCD_MODE,
-                .mask = PMX_TIMER_1_2_MASK,
-        },
-};
-
-struct pmx_dev spear300_pmx_telecom_dac = {
-        .name = "telecom_dac",
-        .modes = pmx_telecom_dac_modes,
-        .mode_count = ARRAY_SIZE(pmx_telecom_dac_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_telecom_i2s_modes[] = {
-        {
-                .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE
-                        | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
-                        ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
-                        | CAMU_WLCD_MODE | CAML_LCD_MODE,
-                .mask = PMX_UART0_MODEM_MASK,
-        },
-};
-
-struct pmx_dev spear300_pmx_telecom_i2s = {
-        .name = "telecom_i2s",
-        .modes = pmx_telecom_i2s_modes,
-        .mode_count = ARRAY_SIZE(pmx_telecom_i2s_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_telecom_boot_pins_modes[] = {
-        {
-                .ids = NAND_MODE | NOR_MODE,
-                .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
-                        PMX_TIMER_3_4_MASK,
-        },
-};
-
-struct pmx_dev spear300_pmx_telecom_boot_pins = {
-        .name = "telecom_boot_pins",
-        .modes = pmx_telecom_boot_pins_modes,
-        .mode_count = ARRAY_SIZE(pmx_telecom_boot_pins_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_telecom_sdhci_4bit_modes[] = {
-        {
-                .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
-                        HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
-                        HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
-                        CAMU_WLCD_MODE | CAML_LCD_MODE | ATA_PABX_WI2S_MODE |
-                        ATA_PABX_I2S_MODE,
-                .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
-                        PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
-                        PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
-        },
-};
-
-struct pmx_dev spear300_pmx_telecom_sdhci_4bit = {
-        .name = "telecom_sdhci_4bit",
-        .modes = pmx_telecom_sdhci_4bit_modes,
-        .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_4bit_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_telecom_sdhci_8bit_modes[] = {
-        {
-                .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
-                        HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
-                        HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
-                        CAMU_WLCD_MODE | CAML_LCD_MODE,
-                .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
-                        PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
-                        PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK,
-        },
-};
-
-struct pmx_dev spear300_pmx_telecom_sdhci_8bit = {
-        .name = "telecom_sdhci_8bit",
-        .modes = pmx_telecom_sdhci_8bit_modes,
-        .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_8bit_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_gpio1_modes[] = {
-        {
-                .ids = PHOTO_FRAME_MODE,
-                .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
-                        PMX_TIMER_3_4_MASK,
-        },
-};
-
-struct pmx_dev spear300_pmx_gpio1 = {
-        .name = "arm gpio1",
-        .modes = pmx_gpio1_modes,
-        .mode_count = ARRAY_SIZE(pmx_gpio1_modes),
-        .enb_on_reset = 1,
-};
-
-/* pmx driver structure */
-static struct pmx_driver pmx_driver = {
-        .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x0000000f},
-        .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
-};
+#include <mach/spear.h>
+
+/* Base address of various IPs */
+#define SPEAR300_TELECOM_BASE           UL(0x50000000)
+
+/* Interrupt registers offsets and masks */
+#define SPEAR300_INT_ENB_MASK_REG       0x54
+#define SPEAR300_INT_STS_MASK_REG       0x58
+#define SPEAR300_IT_PERS_S_IRQ_MASK     (1 << 0)
+#define SPEAR300_IT_CHANGE_S_IRQ_MASK   (1 << 1)
+#define SPEAR300_I2S_IRQ_MASK           (1 << 2)
+#define SPEAR300_TDM_IRQ_MASK           (1 << 3)
+#define SPEAR300_CAMERA_L_IRQ_MASK      (1 << 4)
+#define SPEAR300_CAMERA_F_IRQ_MASK      (1 << 5)
+#define SPEAR300_CAMERA_V_IRQ_MASK      (1 << 6)
+#define SPEAR300_KEYBOARD_IRQ_MASK      (1 << 7)
+#define SPEAR300_GPIO1_IRQ_MASK         (1 << 8)
+
+#define SPEAR300_SHIRQ_RAS1_MASK        0x1FF
+
+#define SPEAR300_SOC_CONFIG_BASE        UL(0x99000000)
+
+
+/* SPEAr300 Virtual irq definitions */
+/* IRQs sharing IRQ_GEN_RAS_1 */
+#define SPEAR300_VIRQ_IT_PERS_S                 (SPEAR3XX_VIRQ_START + 0)
+#define SPEAR300_VIRQ_IT_CHANGE_S               (SPEAR3XX_VIRQ_START + 1)
+#define SPEAR300_VIRQ_I2S                       (SPEAR3XX_VIRQ_START + 2)
+#define SPEAR300_VIRQ_TDM                       (SPEAR3XX_VIRQ_START + 3)
+#define SPEAR300_VIRQ_CAMERA_L                  (SPEAR3XX_VIRQ_START + 4)
+#define SPEAR300_VIRQ_CAMERA_F                  (SPEAR3XX_VIRQ_START + 5)
+#define SPEAR300_VIRQ_CAMERA_V                  (SPEAR3XX_VIRQ_START + 6)
+#define SPEAR300_VIRQ_KEYBOARD                  (SPEAR3XX_VIRQ_START + 7)
+#define SPEAR300_VIRQ_GPIO1                     (SPEAR3XX_VIRQ_START + 8)
+
+/* IRQs sharing IRQ_GEN_RAS_3 */
+#define SPEAR300_IRQ_CLCD                       SPEAR3XX_IRQ_GEN_RAS_3
+
+/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
+#define SPEAR300_IRQ_SDHCI                      SPEAR3XX_IRQ_INTRCOMM_RAS_ARM
 
 /* spear3xx shared irq */
 static struct shirq_dev_config shirq_ras1_config[] = {
@@ -423,45 +113,238 @@ static struct spear_shirq shirq_ras1 = {
         },
 };
 
-/* Add spear300 specific devices here */
-/* arm gpio1 device registration */
-static struct pl061_platform_data gpio1_plat_data = {
-        .gpio_base      = 8,
-        .irq_base       = SPEAR300_GPIO1_INT_BASE,
+/* DMAC platform data's slave info */
+struct pl08x_channel_data spear300_dma_info[] = {
+        {
+                .bus_id = "uart0_rx",
+                .min_signal = 2,
+                .max_signal = 2,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart0_tx",
+                .min_signal = 3,
+                .max_signal = 3,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ssp0_rx",
+                .min_signal = 8,
+                .max_signal = 8,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ssp0_tx",
+                .min_signal = 9,
+                .max_signal = 9,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "i2c_rx",
+                .min_signal = 10,
+                .max_signal = 10,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "i2c_tx",
+                .min_signal = 11,
+                .max_signal = 11,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "irda",
+                .min_signal = 12,
+                .max_signal = 12,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "adc",
+                .min_signal = 13,
+                .max_signal = 13,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "to_jpeg",
+                .min_signal = 14,
+                .max_signal = 14,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "from_jpeg",
+                .min_signal = 15,
+                .max_signal = 15,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras0_rx",
+                .min_signal = 0,
+                .max_signal = 0,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras0_tx",
+                .min_signal = 1,
+                .max_signal = 1,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras1_rx",
+                .min_signal = 2,
+                .max_signal = 2,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras1_tx",
+                .min_signal = 3,
+                .max_signal = 3,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras2_rx",
+                .min_signal = 4,
+                .max_signal = 4,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras2_tx",
+                .min_signal = 5,
+                .max_signal = 5,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras3_rx",
+                .min_signal = 6,
+                .max_signal = 6,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras3_tx",
+                .min_signal = 7,
+                .max_signal = 7,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras4_rx",
+                .min_signal = 8,
+                .max_signal = 8,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras4_tx",
+                .min_signal = 9,
+                .max_signal = 9,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras5_rx",
+                .min_signal = 10,
+                .max_signal = 10,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras5_tx",
+                .min_signal = 11,
+                .max_signal = 11,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras6_rx",
+                .min_signal = 12,
+                .max_signal = 12,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras6_tx",
+                .min_signal = 13,
+                .max_signal = 13,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras7_rx",
+                .min_signal = 14,
+                .max_signal = 14,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras7_tx",
+                .min_signal = 15,
+                .max_signal = 15,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        },
 };
 
-AMBA_APB_DEVICE(spear300_gpio1, "gpio1", 0, SPEAR300_GPIO_BASE,
-        {SPEAR300_VIRQ_GPIO1}, &gpio1_plat_data);
+/* Add SPEAr300 auxdata to pass platform data */
+static struct of_dev_auxdata spear300_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
+                        &pl022_plat_data),
+        OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
+                        &pl080_plat_data),
+        {}
+};
 
-/* spear300 routines */
-void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-                u8 pmx_dev_count)
+static void __init spear300_dt_init(void)
 {
-        int ret = 0;
+        int ret;
+
+        pl080_plat_data.slave_channels = spear300_dma_info;
+        pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear300_dma_info);
 
-        /* call spear3xx family common init function */
-        spear3xx_init();
+        of_platform_populate(NULL, of_default_bus_match_table,
+                        spear300_auxdata_lookup, NULL);
 
         /* shared irq registration */
         shirq_ras1.regs.base = ioremap(SPEAR300_TELECOM_BASE, SZ_4K);
         if (shirq_ras1.regs.base) {
                 ret = spear_shirq_register(&shirq_ras1);
                 if (ret)
-                        printk(KERN_ERR "Error registering Shared IRQ\n");
+                        pr_err("Error registering Shared IRQ\n");
         }
+}
 
-        /* pmx initialization */
-        pmx_driver.mode = pmx_mode;
-        pmx_driver.devs = pmx_devs;
-        pmx_driver.devs_count = pmx_dev_count;
+static const char * const spear300_dt_board_compat[] = {
+        "st,spear300",
+        "st,spear300-evb",
+        NULL,
+};
 
-        pmx_driver.base = ioremap(SPEAR300_SOC_CONFIG_BASE, SZ_4K);
-        if (pmx_driver.base) {
-                ret = pmx_register(&pmx_driver);
-                if (ret)
-                        printk(KERN_ERR "padmux: registration failed. err no"
-                                        ": %d\n", ret);
-                /* Free Mapping, device selection already done */
-                iounmap(pmx_driver.base);
-        }
+static void __init spear300_map_io(void)
+{
+        spear3xx_map_io();
 }
+
+DT_MACHINE_START(SPEAR300_DT, "ST SPEAr300 SoC with Flattened Device Tree")
+        .map_io         =       spear300_map_io,
+        .init_irq       =       spear3xx_dt_init_irq,
+        .handle_irq     =       vic_handle_irq,
+        .timer          =       &spear3xx_timer,
+        .init_machine   =       spear300_dt_init,
+        .restart        =       spear_restart,
+        .dt_compat      =       spear300_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c
deleted file mode 100644
index 3462ab9d6122..000000000000
--- a/arch/arm/mach-spear3xx/spear300_evb.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/spear300_evb.c
- *
- * SPEAr300 evaluation board source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <asm/hardware/vic.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include <mach/generic.h>
-#include <mach/hardware.h>
-
-/* padmux devices to enable */
-static struct pmx_dev *pmx_devs[] = {
-        /* spear3xx specific devices */
-        &spear3xx_pmx_i2c,
-        &spear3xx_pmx_ssp_cs,
-        &spear3xx_pmx_ssp,
-        &spear3xx_pmx_mii,
-        &spear3xx_pmx_uart0,
-
-        /* spear300 specific devices */
-        &spear300_pmx_fsmc_2_chips,
-        &spear300_pmx_clcd,
-        &spear300_pmx_telecom_sdhci_4bit,
-        &spear300_pmx_gpio1,
-};
-
-static struct amba_device *amba_devs[] __initdata = {
-        /* spear3xx specific devices */
-        &spear3xx_gpio_device,
-        &spear3xx_uart_device,
-
-        /* spear300 specific devices */
-        &spear300_gpio1_device,
-};
-
-static struct platform_device *plat_devs[] __initdata = {
-        /* spear3xx specific devices */
-
-        /* spear300 specific devices */
-};
-
-static void __init spear300_evb_init(void)
-{
-        unsigned int i;
-
-        /* call spear300 machine init function */
-        spear300_init(&spear300_photo_frame_mode, pmx_devs,
-                        ARRAY_SIZE(pmx_devs));
-
-        /* Add Platform Devices */
-        platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
-
-        /* Add Amba Devices */
-        for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
-                amba_device_register(amba_devs[i], &iomem_resource);
-}
-
-MACHINE_START(SPEAR300, "ST-SPEAR300-EVB")
-        .atag_offset    =       0x100,
-        .map_io         =       spear3xx_map_io,
-        .init_irq       =       spear3xx_init_irq,
-        .handle_irq     =       vic_handle_irq,
-        .timer          =       &spear3xx_timer,
-        .init_machine   =       spear300_evb_init,
-        .restart        =       spear_restart,
-MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index febaa6fcfb6a..84dfb0900747 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -3,141 +3,84 @@
  *
  * SPEAr310 machine source file
  *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
+ * Copyright (C) 2009-2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
 
-#include <linux/ptrace.h>
-#include <asm/irq.h>
+#define pr_fmt(fmt) "SPEAr310: " fmt
+
+#include <linux/amba/pl08x.h>
+#include <linux/amba/serial.h>
+#include <linux/of_platform.h>
+#include <asm/hardware/vic.h>
+#include <asm/mach/arch.h>
 #include <plat/shirq.h>
 #include <mach/generic.h>
-#include <mach/hardware.h>
-
-/* pad multiplexing support */
-/* muxing registers */
-#define PAD_MUX_CONFIG_REG      0x08
-
-/* devices */
-static struct pmx_dev_mode pmx_emi_cs_0_1_4_5_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_TIMER_3_4_MASK,
-        },
-};
-
-struct pmx_dev spear310_pmx_emi_cs_0_1_4_5 = {
-        .name = "emi_cs_0_1_4_5",
-        .modes = pmx_emi_cs_0_1_4_5_modes,
-        .mode_count = ARRAY_SIZE(pmx_emi_cs_0_1_4_5_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_emi_cs_2_3_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_TIMER_1_2_MASK,
-        },
-};
-
-struct pmx_dev spear310_pmx_emi_cs_2_3 = {
-        .name = "emi_cs_2_3",
-        .modes = pmx_emi_cs_2_3_modes,
-        .mode_count = ARRAY_SIZE(pmx_emi_cs_2_3_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_uart1_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_FIRDA_MASK,
-        },
-};
-
-struct pmx_dev spear310_pmx_uart1 = {
-        .name = "uart1",
-        .modes = pmx_uart1_modes,
-        .mode_count = ARRAY_SIZE(pmx_uart1_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_uart2_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_TIMER_1_2_MASK,
-        },
-};
-
-struct pmx_dev spear310_pmx_uart2 = {
-        .name = "uart2",
-        .modes = pmx_uart2_modes,
-        .mode_count = ARRAY_SIZE(pmx_uart2_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_uart3_4_5_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_UART0_MODEM_MASK,
-        },
-};
-
-struct pmx_dev spear310_pmx_uart3_4_5 = {
-        .name = "uart3_4_5",
-        .modes = pmx_uart3_4_5_modes,
-        .mode_count = ARRAY_SIZE(pmx_uart3_4_5_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_fsmc_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_SSP_CS_MASK,
-        },
-};
-
-struct pmx_dev spear310_pmx_fsmc = {
-        .name = "fsmc",
-        .modes = pmx_fsmc_modes,
-        .mode_count = ARRAY_SIZE(pmx_fsmc_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_rs485_0_1_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_MII_MASK,
-        },
-};
-
-struct pmx_dev spear310_pmx_rs485_0_1 = {
-        .name = "rs485_0_1",
-        .modes = pmx_rs485_0_1_modes,
-        .mode_count = ARRAY_SIZE(pmx_rs485_0_1_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_tdm0_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_MII_MASK,
-        },
-};
-
-struct pmx_dev spear310_pmx_tdm0 = {
-        .name = "tdm0",
-        .modes = pmx_tdm0_modes,
-        .mode_count = ARRAY_SIZE(pmx_tdm0_modes),
-        .enb_on_reset = 1,
-};
+#include <mach/spear.h>
+
+#define SPEAR310_UART1_BASE             UL(0xB2000000)
+#define SPEAR310_UART2_BASE             UL(0xB2080000)
+#define SPEAR310_UART3_BASE             UL(0xB2100000)
+#define SPEAR310_UART4_BASE             UL(0xB2180000)
+#define SPEAR310_UART5_BASE             UL(0xB2200000)
+#define SPEAR310_SOC_CONFIG_BASE        UL(0xB4000000)
+
+/* Interrupt registers offsets and masks */
+#define SPEAR310_INT_STS_MASK_REG       0x04
+#define SPEAR310_SMII0_IRQ_MASK         (1 << 0)
+#define SPEAR310_SMII1_IRQ_MASK         (1 << 1)
+#define SPEAR310_SMII2_IRQ_MASK         (1 << 2)
+#define SPEAR310_SMII3_IRQ_MASK         (1 << 3)
+#define SPEAR310_WAKEUP_SMII0_IRQ_MASK  (1 << 4)
+#define SPEAR310_WAKEUP_SMII1_IRQ_MASK  (1 << 5)
+#define SPEAR310_WAKEUP_SMII2_IRQ_MASK  (1 << 6)
+#define SPEAR310_WAKEUP_SMII3_IRQ_MASK  (1 << 7)
+#define SPEAR310_UART1_IRQ_MASK         (1 << 8)
+#define SPEAR310_UART2_IRQ_MASK         (1 << 9)
+#define SPEAR310_UART3_IRQ_MASK         (1 << 10)
+#define SPEAR310_UART4_IRQ_MASK         (1 << 11)
+#define SPEAR310_UART5_IRQ_MASK         (1 << 12)
+#define SPEAR310_EMI_IRQ_MASK           (1 << 13)
+#define SPEAR310_TDM_HDLC_IRQ_MASK      (1 << 14)
+#define SPEAR310_RS485_0_IRQ_MASK       (1 << 15)
+#define SPEAR310_RS485_1_IRQ_MASK       (1 << 16)
+
+#define SPEAR310_SHIRQ_RAS1_MASK        0x000FF
+#define SPEAR310_SHIRQ_RAS2_MASK        0x01F00
+#define SPEAR310_SHIRQ_RAS3_MASK        0x02000
+#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK        0x1C000
+
+/* SPEAr310 Virtual irq definitions */
+/* IRQs sharing IRQ_GEN_RAS_1 */
+#define SPEAR310_VIRQ_SMII0                     (SPEAR3XX_VIRQ_START + 0)
+#define SPEAR310_VIRQ_SMII1                     (SPEAR3XX_VIRQ_START + 1)
+#define SPEAR310_VIRQ_SMII2                     (SPEAR3XX_VIRQ_START + 2)
+#define SPEAR310_VIRQ_SMII3                     (SPEAR3XX_VIRQ_START + 3)
+#define SPEAR310_VIRQ_WAKEUP_SMII0              (SPEAR3XX_VIRQ_START + 4)
+#define SPEAR310_VIRQ_WAKEUP_SMII1              (SPEAR3XX_VIRQ_START + 5)
+#define SPEAR310_VIRQ_WAKEUP_SMII2              (SPEAR3XX_VIRQ_START + 6)
+#define SPEAR310_VIRQ_WAKEUP_SMII3              (SPEAR3XX_VIRQ_START + 7)
+
+/* IRQs sharing IRQ_GEN_RAS_2 */
+#define SPEAR310_VIRQ_UART1                     (SPEAR3XX_VIRQ_START + 8)
+#define SPEAR310_VIRQ_UART2                     (SPEAR3XX_VIRQ_START + 9)
+#define SPEAR310_VIRQ_UART3                     (SPEAR3XX_VIRQ_START + 10)
+#define SPEAR310_VIRQ_UART4                     (SPEAR3XX_VIRQ_START + 11)
+#define SPEAR310_VIRQ_UART5                     (SPEAR3XX_VIRQ_START + 12)
+
+/* IRQs sharing IRQ_GEN_RAS_3 */
+#define SPEAR310_VIRQ_EMI                       (SPEAR3XX_VIRQ_START + 13)
+#define SPEAR310_VIRQ_PLGPIO                    (SPEAR3XX_VIRQ_START + 14)
+
+/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
+#define SPEAR310_VIRQ_TDM_HDLC                  (SPEAR3XX_VIRQ_START + 15)
+#define SPEAR310_VIRQ_RS485_0                   (SPEAR3XX_VIRQ_START + 16)
+#define SPEAR310_VIRQ_RS485_1                   (SPEAR3XX_VIRQ_START + 17)
 
-/* pmx driver structure */
-static struct pmx_driver pmx_driver = {
-        .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
-};
 
 /* spear3xx shared irq */
 static struct shirq_dev_config shirq_ras1_config[] = {
@@ -255,17 +198,247 @@ static struct spear_shirq shirq_intrcomm_ras = {
         },
 };
 
-/* Add spear310 specific devices here */
+/* DMAC platform data's slave info */
+struct pl08x_channel_data spear310_dma_info[] = {
+        {
+                .bus_id = "uart0_rx",
+                .min_signal = 2,
+                .max_signal = 2,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart0_tx",
+                .min_signal = 3,
+                .max_signal = 3,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ssp0_rx",
+                .min_signal = 8,
+                .max_signal = 8,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ssp0_tx",
+                .min_signal = 9,
+                .max_signal = 9,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "i2c_rx",
+                .min_signal = 10,
+                .max_signal = 10,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "i2c_tx",
+                .min_signal = 11,
+                .max_signal = 11,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "irda",
+                .min_signal = 12,
+                .max_signal = 12,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "adc",
+                .min_signal = 13,
+                .max_signal = 13,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "to_jpeg",
+                .min_signal = 14,
+                .max_signal = 14,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "from_jpeg",
+                .min_signal = 15,
+                .max_signal = 15,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart1_rx",
+                .min_signal = 0,
+                .max_signal = 0,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart1_tx",
+                .min_signal = 1,
+                .max_signal = 1,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart2_rx",
+                .min_signal = 2,
+                .max_signal = 2,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart2_tx",
+                .min_signal = 3,
+                .max_signal = 3,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart3_rx",
+                .min_signal = 4,
+                .max_signal = 4,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart3_tx",
+                .min_signal = 5,
+                .max_signal = 5,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart4_rx",
+                .min_signal = 6,
+                .max_signal = 6,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart4_tx",
+                .min_signal = 7,
+                .max_signal = 7,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart5_rx",
+                .min_signal = 8,
+                .max_signal = 8,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart5_tx",
+                .min_signal = 9,
+                .max_signal = 9,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras5_rx",
+                .min_signal = 10,
+                .max_signal = 10,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras5_tx",
+                .min_signal = 11,
+                .max_signal = 11,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras6_rx",
+                .min_signal = 12,
+                .max_signal = 12,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras6_tx",
+                .min_signal = 13,
+                .max_signal = 13,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras7_rx",
+                .min_signal = 14,
+                .max_signal = 14,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras7_tx",
+                .min_signal = 15,
+                .max_signal = 15,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        },
+};
 
-/* spear310 routines */
-void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-                u8 pmx_dev_count)
+/* uart devices plat data */
+static struct amba_pl011_data spear310_uart_data[] = {
+        {
+                .dma_filter = pl08x_filter_id,
+                .dma_tx_param = "uart1_tx",
+                .dma_rx_param = "uart1_rx",
+        }, {
+                .dma_filter = pl08x_filter_id,
+                .dma_tx_param = "uart2_tx",
+                .dma_rx_param = "uart2_rx",
+        }, {
+                .dma_filter = pl08x_filter_id,
+                .dma_tx_param = "uart3_tx",
+                .dma_rx_param = "uart3_rx",
+        }, {
+                .dma_filter = pl08x_filter_id,
+                .dma_tx_param = "uart4_tx",
+                .dma_rx_param = "uart4_rx",
+        }, {
+                .dma_filter = pl08x_filter_id,
+                .dma_tx_param = "uart5_tx",
+                .dma_rx_param = "uart5_rx",
+        },
+};
+
+/* Add SPEAr310 auxdata to pass platform data */
+static struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
+                        &pl022_plat_data),
+        OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
+                        &pl080_plat_data),
+        OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART1_BASE, NULL,
+                        &spear310_uart_data[0]),
+        OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART2_BASE, NULL,
+                        &spear310_uart_data[1]),
+        OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART3_BASE, NULL,
+                        &spear310_uart_data[2]),
+        OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART4_BASE, NULL,
+                        &spear310_uart_data[3]),
+        OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART5_BASE, NULL,
+                        &spear310_uart_data[4]),
+        {}
+};
+
+static void __init spear310_dt_init(void)
 {
         void __iomem *base;
-        int ret = 0;
+        int ret;
 
-        /* call spear3xx family common init function */
-        spear3xx_init();
+        pl080_plat_data.slave_channels = spear310_dma_info;
+        pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear310_dma_info);
+
+        of_platform_populate(NULL, of_default_bus_match_table,
+                        spear310_auxdata_lookup, NULL);
 
         /* shared irq registration */
         base = ioremap(SPEAR310_SOC_CONFIG_BASE, SZ_4K);
@@ -274,35 +447,45 @@ void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
                 shirq_ras1.regs.base = base;
                 ret = spear_shirq_register(&shirq_ras1);
                 if (ret)
-                        printk(KERN_ERR "Error registering Shared IRQ 1\n");
+                        pr_err("Error registering Shared IRQ 1\n");
 
                 /* shirq 2 */
                 shirq_ras2.regs.base = base;
                 ret = spear_shirq_register(&shirq_ras2);
                 if (ret)
-                        printk(KERN_ERR "Error registering Shared IRQ 2\n");
+                        pr_err("Error registering Shared IRQ 2\n");
 
                 /* shirq 3 */
                 shirq_ras3.regs.base = base;
                 ret = spear_shirq_register(&shirq_ras3);
                 if (ret)
-                        printk(KERN_ERR "Error registering Shared IRQ 3\n");
+                        pr_err("Error registering Shared IRQ 3\n");
 
                 /* shirq 4 */
                 shirq_intrcomm_ras.regs.base = base;
                 ret = spear_shirq_register(&shirq_intrcomm_ras);
                 if (ret)
-                        printk(KERN_ERR "Error registering Shared IRQ 4\n");
+                        pr_err("Error registering Shared IRQ 4\n");
         }
+}
 
-        /* pmx initialization */
-        pmx_driver.base = base;
-        pmx_driver.mode = pmx_mode;
-        pmx_driver.devs = pmx_devs;
-        pmx_driver.devs_count = pmx_dev_count;
+static const char * const spear310_dt_board_compat[] = {
+        "st,spear310",
+        "st,spear310-evb",
+        NULL,
+};
 
-        ret = pmx_register(&pmx_driver);
-        if (ret)
-                printk(KERN_ERR "padmux: registration failed. err no: %d\n",
-                                ret);
+static void __init spear310_map_io(void)
+{
+        spear3xx_map_io();
 }
+
+DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree")
+        .map_io         =       spear310_map_io,
+        .init_irq       =       spear3xx_dt_init_irq,
+        .handle_irq     =       vic_handle_irq,
+        .timer          =       &spear3xx_timer,
+        .init_machine   =       spear310_dt_init,
+        .restart        =       spear_restart,
+        .dt_compat      =       spear310_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c
deleted file mode 100644
index f92c4993f65a..000000000000
--- a/arch/arm/mach-spear3xx/spear310_evb.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/spear310_evb.c
- *
- * SPEAr310 evaluation board source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <asm/hardware/vic.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include <mach/generic.h>
-#include <mach/hardware.h>
-
-/* padmux devices to enable */
-static struct pmx_dev *pmx_devs[] = {
-        /* spear3xx specific devices */
-        &spear3xx_pmx_i2c,
-        &spear3xx_pmx_ssp,
-        &spear3xx_pmx_gpio_pin0,
-        &spear3xx_pmx_gpio_pin1,
-        &spear3xx_pmx_gpio_pin2,
-        &spear3xx_pmx_gpio_pin3,
-        &spear3xx_pmx_gpio_pin4,
-        &spear3xx_pmx_gpio_pin5,
-        &spear3xx_pmx_uart0,
-
-        /* spear310 specific devices */
-        &spear310_pmx_emi_cs_0_1_4_5,
-        &spear310_pmx_emi_cs_2_3,
-        &spear310_pmx_uart1,
-        &spear310_pmx_uart2,
-        &spear310_pmx_uart3_4_5,
-        &spear310_pmx_fsmc,
-        &spear310_pmx_rs485_0_1,
-        &spear310_pmx_tdm0,
-};
-
-static struct amba_device *amba_devs[] __initdata = {
-        /* spear3xx specific devices */
-        &spear3xx_gpio_device,
-        &spear3xx_uart_device,
-
-        /* spear310 specific devices */
-};
-
-static struct platform_device *plat_devs[] __initdata = {
-        /* spear3xx specific devices */
-
-        /* spear310 specific devices */
-};
-
-static void __init spear310_evb_init(void)
-{
-        unsigned int i;
-
-        /* call spear310 machine init function */
-        spear310_init(NULL, pmx_devs, ARRAY_SIZE(pmx_devs));
-
-        /* Add Platform Devices */
-        platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
-
-        /* Add Amba Devices */
-        for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
-                amba_device_register(amba_devs[i], &iomem_resource);
-}
-
-MACHINE_START(SPEAR310, "ST-SPEAR310-EVB")
-        .atag_offset    =       0x100,
-        .map_io         =       spear3xx_map_io,
-        .init_irq       =       spear3xx_init_irq,
-        .handle_irq     =       vic_handle_irq,
-        .timer          =       &spear3xx_timer,
-        .init_machine   =       spear310_evb_init,
-        .restart        =       spear_restart,
-MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index deaaf199612c..a88fa841d29d 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -3,386 +3,84 @@
  *
  * SPEAr320 machine source file
  *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
+ * Copyright (C) 2009-2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
 
-#include <linux/ptrace.h>
-#include <asm/irq.h>
+#define pr_fmt(fmt) "SPEAr320: " fmt
+
+#include <linux/amba/pl022.h>
+#include <linux/amba/pl08x.h>
+#include <linux/amba/serial.h>
+#include <linux/of_platform.h>
+#include <asm/hardware/vic.h>
+#include <asm/mach/arch.h>
 #include <plat/shirq.h>
 #include <mach/generic.h>
-#include <mach/hardware.h>
-
-/* pad multiplexing support */
-/* muxing registers */
-#define PAD_MUX_CONFIG_REG      0x0C
-#define MODE_CONFIG_REG         0x10
-
-/* modes */
-#define AUTO_NET_SMII_MODE      (1 << 0)
-#define AUTO_NET_MII_MODE       (1 << 1)
-#define AUTO_EXP_MODE           (1 << 2)
-#define SMALL_PRINTERS_MODE     (1 << 3)
-#define ALL_MODES               0xF
-
-struct pmx_mode spear320_auto_net_smii_mode = {
-        .id = AUTO_NET_SMII_MODE,
-        .name = "Automation Networking SMII Mode",
-        .mask = 0x00,
-};
-
-struct pmx_mode spear320_auto_net_mii_mode = {
-        .id = AUTO_NET_MII_MODE,
-        .name = "Automation Networking MII Mode",
-        .mask = 0x01,
-};
-
-struct pmx_mode spear320_auto_exp_mode = {
-        .id = AUTO_EXP_MODE,
-        .name = "Automation Expanded Mode",
-        .mask = 0x02,
-};
-
-struct pmx_mode spear320_small_printers_mode = {
-        .id = SMALL_PRINTERS_MODE,
-        .name = "Small Printers Mode",
-        .mask = 0x03,
-};
-
-/* devices */
-static struct pmx_dev_mode pmx_clcd_modes[] = {
-        {
-                .ids = AUTO_NET_SMII_MODE,
-                .mask = 0x0,
-        },
-};
-
-struct pmx_dev spear320_pmx_clcd = {
-        .name = "clcd",
-        .modes = pmx_clcd_modes,
-        .mode_count = ARRAY_SIZE(pmx_clcd_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_emi_modes[] = {
-        {
-                .ids = AUTO_EXP_MODE,
-                .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_emi = {
-        .name = "emi",
-        .modes = pmx_emi_modes,
-        .mode_count = ARRAY_SIZE(pmx_emi_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_fsmc_modes[] = {
-        {
-                .ids = ALL_MODES,
-                .mask = 0x0,
-        },
-};
-
-struct pmx_dev spear320_pmx_fsmc = {
-        .name = "fsmc",
-        .modes = pmx_fsmc_modes,
-        .mode_count = ARRAY_SIZE(pmx_fsmc_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_spp_modes[] = {
-        {
-                .ids = SMALL_PRINTERS_MODE,
-                .mask = 0x0,
-        },
-};
-
-struct pmx_dev spear320_pmx_spp = {
-        .name = "spp",
-        .modes = pmx_spp_modes,
-        .mode_count = ARRAY_SIZE(pmx_spp_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_sdhci_modes[] = {
-        {
-                .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE |
-                        SMALL_PRINTERS_MODE,
-                .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_sdhci = {
-        .name = "sdhci",
-        .modes = pmx_sdhci_modes,
-        .mode_count = ARRAY_SIZE(pmx_sdhci_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_i2s_modes[] = {
-        {
-                .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
-                .mask = PMX_UART0_MODEM_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_i2s = {
-        .name = "i2s",
-        .modes = pmx_i2s_modes,
-        .mode_count = ARRAY_SIZE(pmx_i2s_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_uart1_modes[] = {
-        {
-                .ids = ALL_MODES,
-                .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_uart1 = {
-        .name = "uart1",
-        .modes = pmx_uart1_modes,
-        .mode_count = ARRAY_SIZE(pmx_uart1_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_uart1_modem_modes[] = {
-        {
-                .ids = AUTO_EXP_MODE,
-                .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK |
-                        PMX_SSP_CS_MASK,
-        }, {
-                .ids = SMALL_PRINTERS_MODE,
-                .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
-                        PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_uart1_modem = {
-        .name = "uart1_modem",
-        .modes = pmx_uart1_modem_modes,
-        .mode_count = ARRAY_SIZE(pmx_uart1_modem_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_uart2_modes[] = {
-        {
-                .ids = ALL_MODES,
-                .mask = PMX_FIRDA_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_uart2 = {
-        .name = "uart2",
-        .modes = pmx_uart2_modes,
-        .mode_count = ARRAY_SIZE(pmx_uart2_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_touchscreen_modes[] = {
-        {
-                .ids = AUTO_NET_SMII_MODE,
-                .mask = PMX_SSP_CS_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_touchscreen = {
-        .name = "touchscreen",
-        .modes = pmx_touchscreen_modes,
-        .mode_count = ARRAY_SIZE(pmx_touchscreen_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_can_modes[] = {
-        {
-                .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE,
-                .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
-                        PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_can = {
-        .name = "can",
-        .modes = pmx_can_modes,
-        .mode_count = ARRAY_SIZE(pmx_can_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_sdhci_led_modes[] = {
-        {
-                .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
-                .mask = PMX_SSP_CS_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_sdhci_led = {
-        .name = "sdhci_led",
-        .modes = pmx_sdhci_led_modes,
-        .mode_count = ARRAY_SIZE(pmx_sdhci_led_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_pwm0_modes[] = {
-        {
-                .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
-                .mask = PMX_UART0_MODEM_MASK,
-        }, {
-                .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
-                .mask = PMX_MII_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_pwm0 = {
-        .name = "pwm0",
-        .modes = pmx_pwm0_modes,
-        .mode_count = ARRAY_SIZE(pmx_pwm0_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_pwm1_modes[] = {
-        {
-                .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
-                .mask = PMX_UART0_MODEM_MASK,
-        }, {
-                .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
-                .mask = PMX_MII_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_pwm1 = {
-        .name = "pwm1",
-        .modes = pmx_pwm1_modes,
-        .mode_count = ARRAY_SIZE(pmx_pwm1_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_pwm2_modes[] = {
-        {
-                .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
-                .mask = PMX_SSP_CS_MASK,
-        }, {
-                .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
-                .mask = PMX_MII_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_pwm2 = {
-        .name = "pwm2",
-        .modes = pmx_pwm2_modes,
-        .mode_count = ARRAY_SIZE(pmx_pwm2_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_pwm3_modes[] = {
-        {
-                .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
-                .mask = PMX_MII_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_pwm3 = {
-        .name = "pwm3",
-        .modes = pmx_pwm3_modes,
-        .mode_count = ARRAY_SIZE(pmx_pwm3_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_ssp1_modes[] = {
-        {
-                .ids = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
-                .mask = PMX_MII_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_ssp1 = {
-        .name = "ssp1",
-        .modes = pmx_ssp1_modes,
-        .mode_count = ARRAY_SIZE(pmx_ssp1_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_ssp2_modes[] = {
-        {
-                .ids = AUTO_NET_SMII_MODE,
-                .mask = PMX_MII_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_ssp2 = {
-        .name = "ssp2",
-        .modes = pmx_ssp2_modes,
-        .mode_count = ARRAY_SIZE(pmx_ssp2_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_mii1_modes[] = {
-        {
-                .ids = AUTO_NET_MII_MODE,
-                .mask = 0x0,
-        },
-};
-
-struct pmx_dev spear320_pmx_mii1 = {
-        .name = "mii1",
-        .modes = pmx_mii1_modes,
-        .mode_count = ARRAY_SIZE(pmx_mii1_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_smii0_modes[] = {
-        {
-                .ids = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
-                .mask = PMX_MII_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_smii0 = {
-        .name = "smii0",
-        .modes = pmx_smii0_modes,
-        .mode_count = ARRAY_SIZE(pmx_smii0_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_smii1_modes[] = {
-        {
-                .ids = AUTO_NET_SMII_MODE | SMALL_PRINTERS_MODE,
-                .mask = PMX_MII_MASK,
-        },
-};
-
-struct pmx_dev spear320_pmx_smii1 = {
-        .name = "smii1",
-        .modes = pmx_smii1_modes,
-        .mode_count = ARRAY_SIZE(pmx_smii1_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_i2c1_modes[] = {
-        {
-                .ids = AUTO_EXP_MODE,
-                .mask = 0x0,
-        },
-};
-
-struct pmx_dev spear320_pmx_i2c1 = {
-        .name = "i2c1",
-        .modes = pmx_i2c1_modes,
-        .mode_count = ARRAY_SIZE(pmx_i2c1_modes),
-        .enb_on_reset = 1,
-};
-
-/* pmx driver structure */
-static struct pmx_driver pmx_driver = {
-        .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x00000007},
-        .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
-};
+#include <mach/spear.h>
+
+#define SPEAR320_UART1_BASE             UL(0xA3000000)
+#define SPEAR320_UART2_BASE             UL(0xA4000000)
+#define SPEAR320_SSP0_BASE              UL(0xA5000000)
+#define SPEAR320_SSP1_BASE              UL(0xA6000000)
+
+/* Interrupt registers offsets and masks */
+#define SPEAR320_INT_STS_MASK_REG               0x04
+#define SPEAR320_INT_CLR_MASK_REG               0x04
+#define SPEAR320_INT_ENB_MASK_REG               0x08
+#define SPEAR320_GPIO_IRQ_MASK                  (1 << 0)
+#define SPEAR320_I2S_PLAY_IRQ_MASK              (1 << 1)
+#define SPEAR320_I2S_REC_IRQ_MASK               (1 << 2)
+#define SPEAR320_EMI_IRQ_MASK                   (1 << 7)
+#define SPEAR320_CLCD_IRQ_MASK                  (1 << 8)
+#define SPEAR320_SPP_IRQ_MASK                   (1 << 9)
+#define SPEAR320_SDHCI_IRQ_MASK                 (1 << 10)
+#define SPEAR320_CAN_U_IRQ_MASK                 (1 << 11)
+#define SPEAR320_CAN_L_IRQ_MASK                 (1 << 12)
+#define SPEAR320_UART1_IRQ_MASK                 (1 << 13)
+#define SPEAR320_UART2_IRQ_MASK                 (1 << 14)
+#define SPEAR320_SSP1_IRQ_MASK                  (1 << 15)
+#define SPEAR320_SSP2_IRQ_MASK                  (1 << 16)
+#define SPEAR320_SMII0_IRQ_MASK                 (1 << 17)
+#define SPEAR320_MII1_SMII1_IRQ_MASK            (1 << 18)
+#define SPEAR320_WAKEUP_SMII0_IRQ_MASK          (1 << 19)
+#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK     (1 << 20)
+#define SPEAR320_I2C1_IRQ_MASK                  (1 << 21)
+
+#define SPEAR320_SHIRQ_RAS1_MASK                0x000380
+#define SPEAR320_SHIRQ_RAS3_MASK                0x000007
+#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK        0x3FF800
+
+/* SPEAr320 Virtual irq definitions */
+/* IRQs sharing IRQ_GEN_RAS_1 */
+#define SPEAR320_VIRQ_EMI                       (SPEAR3XX_VIRQ_START + 0)
+#define SPEAR320_VIRQ_CLCD                      (SPEAR3XX_VIRQ_START + 1)
+#define SPEAR320_VIRQ_SPP                       (SPEAR3XX_VIRQ_START + 2)
+
+/* IRQs sharing IRQ_GEN_RAS_2 */
+#define SPEAR320_IRQ_SDHCI                      SPEAR3XX_IRQ_GEN_RAS_2
+
+/* IRQs sharing IRQ_GEN_RAS_3 */
+#define SPEAR320_VIRQ_PLGPIO                    (SPEAR3XX_VIRQ_START + 3)
+#define SPEAR320_VIRQ_I2S_PLAY                  (SPEAR3XX_VIRQ_START + 4)
+#define SPEAR320_VIRQ_I2S_REC                   (SPEAR3XX_VIRQ_START + 5)
+
+/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
+#define SPEAR320_VIRQ_CANU                      (SPEAR3XX_VIRQ_START + 6)
+#define SPEAR320_VIRQ_CANL                      (SPEAR3XX_VIRQ_START + 7)
+#define SPEAR320_VIRQ_UART1                     (SPEAR3XX_VIRQ_START + 8)
+#define SPEAR320_VIRQ_UART2                     (SPEAR3XX_VIRQ_START + 9)
+#define SPEAR320_VIRQ_SSP1                      (SPEAR3XX_VIRQ_START + 10)
+#define SPEAR320_VIRQ_SSP2                      (SPEAR3XX_VIRQ_START + 11)
+#define SPEAR320_VIRQ_SMII0                     (SPEAR3XX_VIRQ_START + 12)
+#define SPEAR320_VIRQ_MII1_SMII1                (SPEAR3XX_VIRQ_START + 13)
+#define SPEAR320_VIRQ_WAKEUP_SMII0              (SPEAR3XX_VIRQ_START + 14)
+#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1         (SPEAR3XX_VIRQ_START + 15)
+#define SPEAR320_VIRQ_I2C1                      (SPEAR3XX_VIRQ_START + 16)
 
 /* spear3xx shared irq */
 static struct shirq_dev_config shirq_ras1_config[] = {
@@ -508,17 +206,250 @@ static struct spear_shirq shirq_intrcomm_ras = {
         },
 };
 
-/* Add spear320 specific devices here */
+/* DMAC platform data's slave info */
+struct pl08x_channel_data spear320_dma_info[] = {
+        {
+                .bus_id = "uart0_rx",
+                .min_signal = 2,
+                .max_signal = 2,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart0_tx",
+                .min_signal = 3,
+                .max_signal = 3,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ssp0_rx",
+                .min_signal = 8,
+                .max_signal = 8,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ssp0_tx",
+                .min_signal = 9,
+                .max_signal = 9,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "i2c0_rx",
+                .min_signal = 10,
+                .max_signal = 10,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "i2c0_tx",
+                .min_signal = 11,
+                .max_signal = 11,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "irda",
+                .min_signal = 12,
+                .max_signal = 12,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "adc",
+                .min_signal = 13,
+                .max_signal = 13,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "to_jpeg",
+                .min_signal = 14,
+                .max_signal = 14,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "from_jpeg",
+                .min_signal = 15,
+                .max_signal = 15,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ssp1_rx",
+                .min_signal = 0,
+                .max_signal = 0,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ssp1_tx",
+                .min_signal = 1,
+                .max_signal = 1,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ssp2_rx",
+                .min_signal = 2,
+                .max_signal = 2,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ssp2_tx",
+                .min_signal = 3,
+                .max_signal = 3,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "uart1_rx",
+                .min_signal = 4,
+                .max_signal = 4,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "uart1_tx",
+                .min_signal = 5,
+                .max_signal = 5,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "uart2_rx",
+                .min_signal = 6,
+                .max_signal = 6,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "uart2_tx",
+                .min_signal = 7,
+                .max_signal = 7,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "i2c1_rx",
+                .min_signal = 8,
+                .max_signal = 8,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "i2c1_tx",
+                .min_signal = 9,
+                .max_signal = 9,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "i2c2_rx",
+                .min_signal = 10,
+                .max_signal = 10,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "i2c2_tx",
+                .min_signal = 11,
+                .max_signal = 11,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "i2s_rx",
+                .min_signal = 12,
+                .max_signal = 12,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "i2s_tx",
+                .min_signal = 13,
+                .max_signal = 13,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "rs485_rx",
+                .min_signal = 14,
+                .max_signal = 14,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "rs485_tx",
+                .min_signal = 15,
+                .max_signal = 15,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        },
+};
+
+static struct pl022_ssp_controller spear320_ssp_data[] = {
+        {
+                .bus_id = 1,
+                .enable_dma = 1,
+                .dma_filter = pl08x_filter_id,
+                .dma_tx_param = "ssp1_tx",
+                .dma_rx_param = "ssp1_rx",
+                .num_chipselect = 2,
+        }, {
+                .bus_id = 2,
+                .enable_dma = 1,
+                .dma_filter = pl08x_filter_id,
+                .dma_tx_param = "ssp2_tx",
+                .dma_rx_param = "ssp2_rx",
+                .num_chipselect = 2,
+        }
+};
+
+static struct amba_pl011_data spear320_uart_data[] = {
+        {
+                .dma_filter = pl08x_filter_id,
+                .dma_tx_param = "uart1_tx",
+                .dma_rx_param = "uart1_rx",
+        }, {
+                .dma_filter = pl08x_filter_id,
+                .dma_tx_param = "uart2_tx",
+                .dma_rx_param = "uart2_rx",
+        },
+};
 
-/* spear320 routines */
-void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-                u8 pmx_dev_count)
+/* Add SPEAr310 auxdata to pass platform data */
+static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
+                        &pl022_plat_data),
+        OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
+                        &pl080_plat_data),
+        OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP0_BASE, NULL,
+                        &spear320_ssp_data[0]),
+        OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP1_BASE, NULL,
+                        &spear320_ssp_data[1]),
+        OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART1_BASE, NULL,
+                        &spear320_uart_data[0]),
+        OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART2_BASE, NULL,
+                        &spear320_uart_data[1]),
+        {}
+};
+
+static void __init spear320_dt_init(void)
 {
         void __iomem *base;
-        int ret = 0;
+        int ret;
 
-        /* call spear3xx family common init function */
-        spear3xx_init();
+        pl080_plat_data.slave_channels = spear320_dma_info;
+        pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info);
+
+        of_platform_populate(NULL, of_default_bus_match_table,
+                        spear320_auxdata_lookup, NULL);
 
         /* shared irq registration */
         base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K);
@@ -527,29 +458,49 @@ void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
                 shirq_ras1.regs.base = base;
                 ret = spear_shirq_register(&shirq_ras1);
                 if (ret)
-                        printk(KERN_ERR "Error registering Shared IRQ 1\n");
+                        pr_err("Error registering Shared IRQ 1\n");
 
                 /* shirq 3 */
                 shirq_ras3.regs.base = base;
                 ret = spear_shirq_register(&shirq_ras3);
                 if (ret)
-                        printk(KERN_ERR "Error registering Shared IRQ 3\n");
+                        pr_err("Error registering Shared IRQ 3\n");
 
                 /* shirq 4 */
                 shirq_intrcomm_ras.regs.base = base;
                 ret = spear_shirq_register(&shirq_intrcomm_ras);
                 if (ret)
-                        printk(KERN_ERR "Error registering Shared IRQ 4\n");
+                        pr_err("Error registering Shared IRQ 4\n");
         }
+}
+
+static const char * const spear320_dt_board_compat[] = {
+        "st,spear320",
+        "st,spear320-evb",
+        NULL,
+};
 
-        /* pmx initialization */
-        pmx_driver.base = base;
-        pmx_driver.mode = pmx_mode;
-        pmx_driver.devs = pmx_devs;
-        pmx_driver.devs_count = pmx_dev_count;
+struct map_desc spear320_io_desc[] __initdata = {
+        {
+                .virtual        = VA_SPEAR320_SOC_CONFIG_BASE,
+                .pfn            = __phys_to_pfn(SPEAR320_SOC_CONFIG_BASE),
+                .length         = SZ_16M,
+                .type           = MT_DEVICE
+        },
+};
 
-        ret = pmx_register(&pmx_driver);
-        if (ret)
-                printk(KERN_ERR "padmux: registration failed. err no: %d\n",
-                                ret);
+static void __init spear320_map_io(void)
+{
+        iotable_init(spear320_io_desc, ARRAY_SIZE(spear320_io_desc));
+        spear3xx_map_io();
 }
+
+DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree")
+        .map_io         =       spear320_map_io,
+        .init_irq       =       spear3xx_dt_init_irq,
+        .handle_irq     =       vic_handle_irq,
+        .timer          =       &spear3xx_timer,
+        .init_machine   =       spear320_dt_init,
+        .restart        =       spear_restart,
+        .dt_compat      =       spear320_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
deleted file mode 100644
index 105334ab7021..000000000000
--- a/arch/arm/mach-spear3xx/spear320_evb.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/spear320_evb.c
- *
- * SPEAr320 evaluation board source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <asm/hardware/vic.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include <mach/generic.h>
-#include <mach/hardware.h>
-
-/* padmux devices to enable */
-static struct pmx_dev *pmx_devs[] = {
-        /* spear3xx specific devices */
-        &spear3xx_pmx_i2c,
-        &spear3xx_pmx_ssp,
-        &spear3xx_pmx_mii,
-        &spear3xx_pmx_uart0,
-
-        /* spear320 specific devices */
-        &spear320_pmx_fsmc,
-        &spear320_pmx_sdhci,
-        &spear320_pmx_i2s,
-        &spear320_pmx_uart1,
-        &spear320_pmx_uart2,
-        &spear320_pmx_can,
-        &spear320_pmx_pwm0,
-        &spear320_pmx_pwm1,
-        &spear320_pmx_pwm2,
-        &spear320_pmx_mii1,
-};
-
-static struct amba_device *amba_devs[] __initdata = {
-        /* spear3xx specific devices */
-        &spear3xx_gpio_device,
-        &spear3xx_uart_device,
-
-        /* spear320 specific devices */
-};
-
-static struct platform_device *plat_devs[] __initdata = {
-        /* spear3xx specific devices */
-
-        /* spear320 specific devices */
-};
-
-static void __init spear320_evb_init(void)
-{
-        unsigned int i;
-
-        /* call spear320 machine init function */
-        spear320_init(&spear320_auto_net_mii_mode, pmx_devs,
-                        ARRAY_SIZE(pmx_devs));
-
-        /* Add Platform Devices */
-        platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
-
-        /* Add Amba Devices */
-        for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
-                amba_device_register(amba_devs[i], &iomem_resource);
-}
-
-MACHINE_START(SPEAR320, "ST-SPEAR320-EVB")
-        .atag_offset    =       0x100,
-        .map_io         =       spear3xx_map_io,
-        .init_irq       =       spear3xx_init_irq,
-        .handle_irq     =       vic_handle_irq,
-        .timer          =       &spear3xx_timer,
-        .init_machine   =       spear320_evb_init,
-        .restart        =       spear_restart,
-MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index b1733c37f209..f22419ed74a8 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -3,71 +3,78 @@
  *
  * SPEAr3XX machines common source file
  *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
+ * Copyright (C) 2009-2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
 
-#include <linux/types.h>
-#include <linux/amba/pl061.h>
-#include <linux/ptrace.h>
+#define pr_fmt(fmt) "SPEAr3xx: " fmt
+
+#include <linux/amba/pl022.h>
+#include <linux/amba/pl08x.h>
+#include <linux/of_irq.h>
 #include <linux/io.h>
+#include <asm/hardware/pl080.h>
 #include <asm/hardware/vic.h>
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
+#include <plat/pl080.h>
 #include <mach/generic.h>
-#include <mach/hardware.h>
-
-/* Add spear3xx machines common devices here */
-/* gpio device registration */
-static struct pl061_platform_data gpio_plat_data = {
-        .gpio_base      = 0,
-        .irq_base       = SPEAR3XX_GPIO_INT_BASE,
+#include <mach/spear.h>
+
+/* ssp device registration */
+struct pl022_ssp_controller pl022_plat_data = {
+        .bus_id = 0,
+        .enable_dma = 1,
+        .dma_filter = pl08x_filter_id,
+        .dma_tx_param = "ssp0_tx",
+        .dma_rx_param = "ssp0_rx",
+        /*
+         * This is number of spi devices that can be connected to spi. There are
+         * two type of chipselects on which slave devices can work. One is chip
+         * select provided by spi masters other is controlled through external
+         * gpio's. We can't use chipselect provided from spi master (because as
+         * soon as FIFO becomes empty, CS is disabled and transfer ends). So
+         * this number now depends on number of gpios available for spi. each
+         * slave on each master requires a separate gpio pin.
+         */
+        .num_chipselect = 2,
+};
+
+/* dmac device registration */
+struct pl08x_platform_data pl080_plat_data = {
+        .memcpy_channel = {
+                .bus_id = "memcpy",
+                .cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
+                        PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
+                        PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
+                        PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
+                        PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
+                        PL080_CONTROL_PROT_SYS),
+        },
+        .lli_buses = PL08X_AHB1,
+        .mem_buses = PL08X_AHB1,
+        .get_signal = pl080_get_signal,
+        .put_signal = pl080_put_signal,
 };
 
-AMBA_APB_DEVICE(spear3xx_gpio, "gpio", 0, SPEAR3XX_ICM3_GPIO_BASE,
-        {SPEAR3XX_IRQ_BASIC_GPIO}, &gpio_plat_data);
-
-/* uart device registration */
-AMBA_APB_DEVICE(spear3xx_uart, "uart", 0, SPEAR3XX_ICM1_UART_BASE,
-        {SPEAR3XX_IRQ_UART}, NULL);
-
-/* Do spear3xx familiy common initialization part here */
-void __init spear3xx_init(void)
-{
-        /* nothing to do for now */
-}
-
-/* This will initialize vic */
-void __init spear3xx_init_irq(void)
-{
-        vic_init((void __iomem *)VA_SPEAR3XX_ML1_VIC_BASE, 0, ~0, 0);
-}
-
-/* Following will create static virtual/physical mappings */
+/*
+ * Following will create 16MB static virtual/physical mappings
+ * PHYSICAL             VIRTUAL
+ * 0xD0000000           0xFD000000
+ * 0xFC000000           0xFC000000
+ */
 struct map_desc spear3xx_io_desc[] __initdata = {
         {
-                .virtual        = VA_SPEAR3XX_ICM1_UART_BASE,
-                .pfn            = __phys_to_pfn(SPEAR3XX_ICM1_UART_BASE),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE
-        }, {
-                .virtual        = VA_SPEAR3XX_ML1_VIC_BASE,
-                .pfn            = __phys_to_pfn(SPEAR3XX_ML1_VIC_BASE),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE
-        }, {
-                .virtual        = VA_SPEAR3XX_ICM3_SYS_CTRL_BASE,
-                .pfn            = __phys_to_pfn(SPEAR3XX_ICM3_SYS_CTRL_BASE),
-                .length         = SZ_4K,
+                .virtual        = VA_SPEAR3XX_ICM1_2_BASE,
+                .pfn            = __phys_to_pfn(SPEAR3XX_ICM1_2_BASE),
+                .length         = SZ_16M,
                 .type           = MT_DEVICE
         }, {
-                .virtual        = VA_SPEAR3XX_ICM3_MISC_REG_BASE,
-                .pfn            = __phys_to_pfn(SPEAR3XX_ICM3_MISC_REG_BASE),
-                .length         = SZ_4K,
+                .virtual        = VA_SPEAR3XX_ICM3_SMI_CTRL_BASE,
+                .pfn            = __phys_to_pfn(SPEAR3XX_ICM3_SMI_CTRL_BASE),
+                .length         = SZ_16M,
                 .type           = MT_DEVICE
         },
 };
@@ -76,441 +83,15 @@ struct map_desc spear3xx_io_desc[] __initdata = {
 void __init spear3xx_map_io(void)
 {
         iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc));
-
-        /* This will initialize clock framework */
-        spear3xx_clk_init();
 }
 
-/* pad multiplexing support */
-/* devices */
-static struct pmx_dev_mode pmx_firda_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_FIRDA_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_firda = {
-        .name = "firda",
-        .modes = pmx_firda_modes,
-        .mode_count = ARRAY_SIZE(pmx_firda_modes),
-        .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_i2c_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_I2C_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_i2c = {
-        .name = "i2c",
-        .modes = pmx_i2c_modes,
-        .mode_count = ARRAY_SIZE(pmx_i2c_modes),
-        .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_ssp_cs_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_SSP_CS_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_ssp_cs = {
-        .name = "ssp_chip_selects",
-        .modes = pmx_ssp_cs_modes,
-        .mode_count = ARRAY_SIZE(pmx_ssp_cs_modes),
-        .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_ssp_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_SSP_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_ssp = {
-        .name = "ssp",
-        .modes = pmx_ssp_modes,
-        .mode_count = ARRAY_SIZE(pmx_ssp_modes),
-        .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_mii_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_MII_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_mii = {
-        .name = "mii",
-        .modes = pmx_mii_modes,
-        .mode_count = ARRAY_SIZE(pmx_mii_modes),
-        .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_gpio_pin0_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_GPIO_PIN0_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_gpio_pin0 = {
-        .name = "gpio_pin0",
-        .modes = pmx_gpio_pin0_modes,
-        .mode_count = ARRAY_SIZE(pmx_gpio_pin0_modes),
-        .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_gpio_pin1_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_GPIO_PIN1_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_gpio_pin1 = {
-        .name = "gpio_pin1",
-        .modes = pmx_gpio_pin1_modes,
-        .mode_count = ARRAY_SIZE(pmx_gpio_pin1_modes),
-        .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_gpio_pin2_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_GPIO_PIN2_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_gpio_pin2 = {
-        .name = "gpio_pin2",
-        .modes = pmx_gpio_pin2_modes,
-        .mode_count = ARRAY_SIZE(pmx_gpio_pin2_modes),
-        .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_gpio_pin3_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_GPIO_PIN3_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_gpio_pin3 = {
-        .name = "gpio_pin3",
-        .modes = pmx_gpio_pin3_modes,
-        .mode_count = ARRAY_SIZE(pmx_gpio_pin3_modes),
-        .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_gpio_pin4_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_GPIO_PIN4_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_gpio_pin4 = {
-        .name = "gpio_pin4",
-        .modes = pmx_gpio_pin4_modes,
-        .mode_count = ARRAY_SIZE(pmx_gpio_pin4_modes),
-        .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_gpio_pin5_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_GPIO_PIN5_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_gpio_pin5 = {
-        .name = "gpio_pin5",
-        .modes = pmx_gpio_pin5_modes,
-        .mode_count = ARRAY_SIZE(pmx_gpio_pin5_modes),
-        .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_uart0_modem_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_UART0_MODEM_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_uart0_modem = {
-        .name = "uart0_modem",
-        .modes = pmx_uart0_modem_modes,
-        .mode_count = ARRAY_SIZE(pmx_uart0_modem_modes),
-        .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_uart0_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_UART0_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_uart0 = {
-        .name = "uart0",
-        .modes = pmx_uart0_modes,
-        .mode_count = ARRAY_SIZE(pmx_uart0_modes),
-        .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_timer_3_4_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_TIMER_3_4_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_timer_3_4 = {
-        .name = "timer_3_4",
-        .modes = pmx_timer_3_4_modes,
-        .mode_count = ARRAY_SIZE(pmx_timer_3_4_modes),
-        .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_timer_1_2_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_TIMER_1_2_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_timer_1_2 = {
-        .name = "timer_1_2",
-        .modes = pmx_timer_1_2_modes,
-        .mode_count = ARRAY_SIZE(pmx_timer_1_2_modes),
-        .enb_on_reset = 0,
-};
-
-#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
-/* plgpios devices */
-static struct pmx_dev_mode pmx_plgpio_0_1_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_FIRDA_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_0_1 = {
-        .name = "plgpio 0 and 1",
-        .modes = pmx_plgpio_0_1_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_0_1_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_2_3_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_UART0_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_2_3 = {
-        .name = "plgpio 2 and 3",
-        .modes = pmx_plgpio_2_3_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_2_3_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_4_5_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_I2C_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_4_5 = {
-        .name = "plgpio 4 and 5",
-        .modes = pmx_plgpio_4_5_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_4_5_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_6_9_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_SSP_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_6_9 = {
-        .name = "plgpio 6 to 9",
-        .modes = pmx_plgpio_6_9_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_6_9_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_10_27_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_MII_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_10_27 = {
-        .name = "plgpio 10 to 27",
-        .modes = pmx_plgpio_10_27_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_10_27_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_28_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_GPIO_PIN0_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_28 = {
-        .name = "plgpio 28",
-        .modes = pmx_plgpio_28_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_28_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_29_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_GPIO_PIN1_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_29 = {
-        .name = "plgpio 29",
-        .modes = pmx_plgpio_29_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_29_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_30_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_GPIO_PIN2_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_30 = {
-        .name = "plgpio 30",
-        .modes = pmx_plgpio_30_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_30_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_31_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_GPIO_PIN3_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_31 = {
-        .name = "plgpio 31",
-        .modes = pmx_plgpio_31_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_31_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_32_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_GPIO_PIN4_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_32 = {
-        .name = "plgpio 32",
-        .modes = pmx_plgpio_32_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_32_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_33_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_GPIO_PIN5_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_33 = {
-        .name = "plgpio 33",
-        .modes = pmx_plgpio_33_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_33_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_34_36_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_SSP_CS_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_34_36 = {
-        .name = "plgpio 34 to 36",
-        .modes = pmx_plgpio_34_36_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_34_36_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_37_42_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_UART0_MODEM_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_37_42 = {
-        .name = "plgpio 37 to 42",
-        .modes = pmx_plgpio_37_42_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_37_42_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_TIMER_1_2_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48 = {
-        .name = "plgpio 43, 44, 47 and 48",
-        .modes = pmx_plgpio_43_44_47_48_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_43_44_47_48_modes),
-        .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_TIMER_3_4_MASK,
-        },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50 = {
-        .name = "plgpio 45, 46, 49 and 50",
-        .modes = pmx_plgpio_45_46_49_50_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_45_46_49_50_modes),
-        .enb_on_reset = 1,
-};
-#endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */
-
 static void __init spear3xx_timer_init(void)
 {
         char pclk_name[] = "pll3_48m_clk";
         struct clk *gpt_clk, *pclk;
 
+        spear3xx_clk_init();
+
         /* get the system timer clock */
         gpt_clk = clk_get_sys("gpt0", NULL);
         if (IS_ERR(gpt_clk)) {
@@ -530,9 +111,19 @@ static void __init spear3xx_timer_init(void)
         clk_put(gpt_clk);
         clk_put(pclk);
 
-        spear_setup_timer();
+        spear_setup_of_timer();
 }
 
 struct sys_timer spear3xx_timer = {
         .init = spear3xx_timer_init,
 };
+
+static const struct of_device_id vic_of_match[] __initconst = {
+        { .compatible = "arm,pl190-vic", .data = vic_of_init, },
+        { /* Sentinel */ }
+};
+
+void __init spear3xx_dt_init_irq(void)
+{
+        of_irq_init(vic_of_match);
+}
diff --git a/arch/arm/mach-spear6xx/Makefile b/arch/arm/mach-spear6xx/Makefile
index 76e5750552fc..898831d93f37 100644
--- a/arch/arm/mach-spear6xx/Makefile
+++ b/arch/arm/mach-spear6xx/Makefile
@@ -3,4 +3,4 @@
 #
 
 # common files
-obj-y   += clock.o spear6xx.o
+obj-y   += spear6xx.o
diff --git a/arch/arm/mach-spear6xx/Makefile.boot b/arch/arm/mach-spear6xx/Makefile.boot
index 4674a4c221db..af493da37ab6 100644
--- a/arch/arm/mach-spear6xx/Makefile.boot
+++ b/arch/arm/mach-spear6xx/Makefile.boot
@@ -1,3 +1,5 @@
 zreladdr-y      += 0x00008000
 params_phys-y   := 0x00000100
 initrd_phys-y   := 0x00800000
+
+dtb-$(CONFIG_BOARD_SPEAR600_DT) += spear600-evb.dtb
diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c
deleted file mode 100644
index a86499a8a15f..000000000000
--- a/arch/arm/mach-spear6xx/clock.c
+++ /dev/null
@@ -1,683 +0,0 @@
-/*
- * arch/arm/mach-spear6xx/clock.c
- *
- * SPEAr6xx machines clock framework source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <plat/clock.h>
-#include <mach/misc_regs.h>
-
-/* root clks */
-/* 32 KHz oscillator clock */
-static struct clk osc_32k_clk = {
-        .flags = ALWAYS_ENABLED,
-        .rate = 32000,
-};
-
-/* 30 MHz oscillator clock */
-static struct clk osc_30m_clk = {
-        .flags = ALWAYS_ENABLED,
-        .rate = 30000000,
-};
-
-/* clock derived from 32 KHz osc clk */
-/* rtc clock */
-static struct clk rtc_clk = {
-        .pclk = &osc_32k_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = RTC_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* clock derived from 30 MHz osc clk */
-/* pll masks structure */
-static struct pll_clk_masks pll1_masks = {
-        .mode_mask = PLL_MODE_MASK,
-        .mode_shift = PLL_MODE_SHIFT,
-        .norm_fdbk_m_mask = PLL_NORM_FDBK_M_MASK,
-        .norm_fdbk_m_shift = PLL_NORM_FDBK_M_SHIFT,
-        .dith_fdbk_m_mask = PLL_DITH_FDBK_M_MASK,
-        .dith_fdbk_m_shift = PLL_DITH_FDBK_M_SHIFT,
-        .div_p_mask = PLL_DIV_P_MASK,
-        .div_p_shift = PLL_DIV_P_SHIFT,
-        .div_n_mask = PLL_DIV_N_MASK,
-        .div_n_shift = PLL_DIV_N_SHIFT,
-};
-
-/* pll1 configuration structure */
-static struct pll_clk_config pll1_config = {
-        .mode_reg = PLL1_CTR,
-        .cfg_reg = PLL1_FRQ,
-        .masks = &pll1_masks,
-};
-
-/* pll rate configuration table, in ascending order of rates */
-struct pll_rate_tbl pll_rtbl[] = {
-        {.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* 266 MHz */
-        {.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* 332 MHz */
-};
-
-/* PLL1 clock */
-static struct clk pll1_clk = {
-        .flags = ENABLED_ON_INIT,
-        .pclk = &osc_30m_clk,
-        .en_reg = PLL1_CTR,
-        .en_reg_bit = PLL_ENABLE,
-        .calc_rate = &pll_calc_rate,
-        .recalc = &pll_clk_recalc,
-        .set_rate = &pll_clk_set_rate,
-        .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 1},
-        .private_data = &pll1_config,
-};
-
-/* PLL3 48 MHz clock */
-static struct clk pll3_48m_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &osc_30m_clk,
-        .rate = 48000000,
-};
-
-/* watch dog timer clock */
-static struct clk wdt_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &osc_30m_clk,
-        .recalc = &follow_parent,
-};
-
-/* clock derived from pll1 clk */
-/* cpu clock */
-static struct clk cpu_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &pll1_clk,
-        .recalc = &follow_parent,
-};
-
-/* ahb masks structure */
-static struct bus_clk_masks ahb_masks = {
-        .mask = PLL_HCLK_RATIO_MASK,
-        .shift = PLL_HCLK_RATIO_SHIFT,
-};
-
-/* ahb configuration structure */
-static struct bus_clk_config ahb_config = {
-        .reg = CORE_CLK_CFG,
-        .masks = &ahb_masks,
-};
-
-/* ahb rate configuration table, in ascending order of rates */
-struct bus_rate_tbl bus_rtbl[] = {
-        {.div = 3}, /* == parent divided by 4 */
-        {.div = 2}, /* == parent divided by 3 */
-        {.div = 1}, /* == parent divided by 2 */
-        {.div = 0}, /* == parent divided by 1 */
-};
-
-/* ahb clock */
-static struct clk ahb_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &pll1_clk,
-        .calc_rate = &bus_calc_rate,
-        .recalc = &bus_clk_recalc,
-        .set_rate = &bus_clk_set_rate,
-        .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
-        .private_data = &ahb_config,
-};
-
-/* auxiliary synthesizers masks */
-static struct aux_clk_masks aux_masks = {
-        .eq_sel_mask = AUX_EQ_SEL_MASK,
-        .eq_sel_shift = AUX_EQ_SEL_SHIFT,
-        .eq1_mask = AUX_EQ1_SEL,
-        .eq2_mask = AUX_EQ2_SEL,
-        .xscale_sel_mask = AUX_XSCALE_MASK,
-        .xscale_sel_shift = AUX_XSCALE_SHIFT,
-        .yscale_sel_mask = AUX_YSCALE_MASK,
-        .yscale_sel_shift = AUX_YSCALE_SHIFT,
-};
-
-/* uart configurations */
-static struct aux_clk_config uart_synth_config = {
-        .synth_reg = UART_CLK_SYNT,
-        .masks = &aux_masks,
-};
-
-/* aux rate configuration table, in ascending order of rates */
-struct aux_rate_tbl aux_rtbl[] = {
-        /* For PLL1 = 332 MHz */
-        {.xscale = 1, .yscale = 8, .eq = 1}, /* 41.5 MHz */
-        {.xscale = 1, .yscale = 4, .eq = 1}, /* 83 MHz */
-        {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
-};
-
-/* uart synth clock */
-static struct clk uart_synth_clk = {
-        .en_reg = UART_CLK_SYNT,
-        .en_reg_bit = AUX_SYNT_ENB,
-        .pclk = &pll1_clk,
-        .calc_rate = &aux_calc_rate,
-        .recalc = &aux_clk_recalc,
-        .set_rate = &aux_clk_set_rate,
-        .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2},
-        .private_data = &uart_synth_config,
-};
-
-/* uart parents */
-static struct pclk_info uart_pclk_info[] = {
-        {
-                .pclk = &uart_synth_clk,
-                .pclk_val = AUX_CLK_PLL1_VAL,
-        }, {
-                .pclk = &pll3_48m_clk,
-                .pclk_val = AUX_CLK_PLL3_VAL,
-        },
-};
-
-/* uart parent select structure */
-static struct pclk_sel uart_pclk_sel = {
-        .pclk_info = uart_pclk_info,
-        .pclk_count = ARRAY_SIZE(uart_pclk_info),
-        .pclk_sel_reg = PERIP_CLK_CFG,
-        .pclk_sel_mask = UART_CLK_MASK,
-};
-
-/* uart0 clock */
-static struct clk uart0_clk = {
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = UART0_CLK_ENB,
-        .pclk_sel = &uart_pclk_sel,
-        .pclk_sel_shift = UART_CLK_SHIFT,
-        .recalc = &follow_parent,
-};
-
-/* uart1 clock */
-static struct clk uart1_clk = {
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = UART1_CLK_ENB,
-        .pclk_sel = &uart_pclk_sel,
-        .pclk_sel_shift = UART_CLK_SHIFT,
-        .recalc = &follow_parent,
-};
-
-/* firda configurations */
-static struct aux_clk_config firda_synth_config = {
-        .synth_reg = FIRDA_CLK_SYNT,
-        .masks = &aux_masks,
-};
-
-/* firda synth clock */
-static struct clk firda_synth_clk = {
-        .en_reg = FIRDA_CLK_SYNT,
-        .en_reg_bit = AUX_SYNT_ENB,
-        .pclk = &pll1_clk,
-        .calc_rate = &aux_calc_rate,
-        .recalc = &aux_clk_recalc,
-        .set_rate = &aux_clk_set_rate,
-        .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2},
-        .private_data = &firda_synth_config,
-};
-
-/* firda parents */
-static struct pclk_info firda_pclk_info[] = {
-        {
-                .pclk = &firda_synth_clk,
-                .pclk_val = AUX_CLK_PLL1_VAL,
-        }, {
-                .pclk = &pll3_48m_clk,
-                .pclk_val = AUX_CLK_PLL3_VAL,
-        },
-};
-
-/* firda parent select structure */
-static struct pclk_sel firda_pclk_sel = {
-        .pclk_info = firda_pclk_info,
-        .pclk_count = ARRAY_SIZE(firda_pclk_info),
-        .pclk_sel_reg = PERIP_CLK_CFG,
-        .pclk_sel_mask = FIRDA_CLK_MASK,
-};
-
-/* firda clock */
-static struct clk firda_clk = {
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = FIRDA_CLK_ENB,
-        .pclk_sel = &firda_pclk_sel,
-        .pclk_sel_shift = FIRDA_CLK_SHIFT,
-        .recalc = &follow_parent,
-};
-
-/* clcd configurations */
-static struct aux_clk_config clcd_synth_config = {
-        .synth_reg = CLCD_CLK_SYNT,
-        .masks = &aux_masks,
-};
-
-/* firda synth clock */
-static struct clk clcd_synth_clk = {
-        .en_reg = CLCD_CLK_SYNT,
-        .en_reg_bit = AUX_SYNT_ENB,
-        .pclk = &pll1_clk,
-        .calc_rate = &aux_calc_rate,
-        .recalc = &aux_clk_recalc,
-        .set_rate = &aux_clk_set_rate,
-        .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2},
-        .private_data = &clcd_synth_config,
-};
-
-/* clcd parents */
-static struct pclk_info clcd_pclk_info[] = {
-        {
-                .pclk = &clcd_synth_clk,
-                .pclk_val = AUX_CLK_PLL1_VAL,
-        }, {
-                .pclk = &pll3_48m_clk,
-                .pclk_val = AUX_CLK_PLL3_VAL,
-        },
-};
-
-/* clcd parent select structure */
-static struct pclk_sel clcd_pclk_sel = {
-        .pclk_info = clcd_pclk_info,
-        .pclk_count = ARRAY_SIZE(clcd_pclk_info),
-        .pclk_sel_reg = PERIP_CLK_CFG,
-        .pclk_sel_mask = CLCD_CLK_MASK,
-};
-
-/* clcd clock */
-static struct clk clcd_clk = {
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = CLCD_CLK_ENB,
-        .pclk_sel = &clcd_pclk_sel,
-        .pclk_sel_shift = CLCD_CLK_SHIFT,
-        .recalc = &follow_parent,
-};
-
-/* gpt synthesizer masks */
-static struct gpt_clk_masks gpt_masks = {
-        .mscale_sel_mask = GPT_MSCALE_MASK,
-        .mscale_sel_shift = GPT_MSCALE_SHIFT,
-        .nscale_sel_mask = GPT_NSCALE_MASK,
-        .nscale_sel_shift = GPT_NSCALE_SHIFT,
-};
-
-/* gpt rate configuration table, in ascending order of rates */
-struct gpt_rate_tbl gpt_rtbl[] = {
-        /* For pll1 = 332 MHz */
-        {.mscale = 4, .nscale = 0}, /* 41.5 MHz */
-        {.mscale = 2, .nscale = 0}, /* 55.3 MHz */
-        {.mscale = 1, .nscale = 0}, /* 83 MHz */
-};
-
-/* gpt0 synth clk config*/
-static struct gpt_clk_config gpt0_synth_config = {
-        .synth_reg = PRSC1_CLK_CFG,
-        .masks = &gpt_masks,
-};
-
-/* gpt synth clock */
-static struct clk gpt0_synth_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &pll1_clk,
-        .calc_rate = &gpt_calc_rate,
-        .recalc = &gpt_clk_recalc,
-        .set_rate = &gpt_clk_set_rate,
-        .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
-        .private_data = &gpt0_synth_config,
-};
-
-/* gpt parents */
-static struct pclk_info gpt0_pclk_info[] = {
-        {
-                .pclk = &gpt0_synth_clk,
-                .pclk_val = AUX_CLK_PLL1_VAL,
-        }, {
-                .pclk = &pll3_48m_clk,
-                .pclk_val = AUX_CLK_PLL3_VAL,
-        },
-};
-
-/* gpt parent select structure */
-static struct pclk_sel gpt0_pclk_sel = {
-        .pclk_info = gpt0_pclk_info,
-        .pclk_count = ARRAY_SIZE(gpt0_pclk_info),
-        .pclk_sel_reg = PERIP_CLK_CFG,
-        .pclk_sel_mask = GPT_CLK_MASK,
-};
-
-/* gpt0 ARM1 subsystem timer clock */
-static struct clk gpt0_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk_sel = &gpt0_pclk_sel,
-        .pclk_sel_shift = GPT0_CLK_SHIFT,
-        .recalc = &follow_parent,
-};
-
-
-/* Note: gpt0 and gpt1 share same parent clocks */
-/* gpt parent select structure */
-static struct pclk_sel gpt1_pclk_sel = {
-        .pclk_info = gpt0_pclk_info,
-        .pclk_count = ARRAY_SIZE(gpt0_pclk_info),
-        .pclk_sel_reg = PERIP_CLK_CFG,
-        .pclk_sel_mask = GPT_CLK_MASK,
-};
-
-/* gpt1 timer clock */
-static struct clk gpt1_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk_sel = &gpt1_pclk_sel,
-        .pclk_sel_shift = GPT1_CLK_SHIFT,
-        .recalc = &follow_parent,
-};
-
-/* gpt2 synth clk config*/
-static struct gpt_clk_config gpt2_synth_config = {
-        .synth_reg = PRSC2_CLK_CFG,
-        .masks = &gpt_masks,
-};
-
-/* gpt synth clock */
-static struct clk gpt2_synth_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &pll1_clk,
-        .calc_rate = &gpt_calc_rate,
-        .recalc = &gpt_clk_recalc,
-        .set_rate = &gpt_clk_set_rate,
-        .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
-        .private_data = &gpt2_synth_config,
-};
-
-/* gpt parents */
-static struct pclk_info gpt2_pclk_info[] = {
-        {
-                .pclk = &gpt2_synth_clk,
-                .pclk_val = AUX_CLK_PLL1_VAL,
-        }, {
-                .pclk = &pll3_48m_clk,
-                .pclk_val = AUX_CLK_PLL3_VAL,
-        },
-};
-
-/* gpt parent select structure */
-static struct pclk_sel gpt2_pclk_sel = {
-        .pclk_info = gpt2_pclk_info,
-        .pclk_count = ARRAY_SIZE(gpt2_pclk_info),
-        .pclk_sel_reg = PERIP_CLK_CFG,
-        .pclk_sel_mask = GPT_CLK_MASK,
-};
-
-/* gpt2 timer clock */
-static struct clk gpt2_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk_sel = &gpt2_pclk_sel,
-        .pclk_sel_shift = GPT2_CLK_SHIFT,
-        .recalc = &follow_parent,
-};
-
-/* gpt3 synth clk config*/
-static struct gpt_clk_config gpt3_synth_config = {
-        .synth_reg = PRSC3_CLK_CFG,
-        .masks = &gpt_masks,
-};
-
-/* gpt synth clock */
-static struct clk gpt3_synth_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &pll1_clk,
-        .calc_rate = &gpt_calc_rate,
-        .recalc = &gpt_clk_recalc,
-        .set_rate = &gpt_clk_set_rate,
-        .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
-        .private_data = &gpt3_synth_config,
-};
-
-/* gpt parents */
-static struct pclk_info gpt3_pclk_info[] = {
-        {
-                .pclk = &gpt3_synth_clk,
-                .pclk_val = AUX_CLK_PLL1_VAL,
-        }, {
-                .pclk = &pll3_48m_clk,
-                .pclk_val = AUX_CLK_PLL3_VAL,
-        },
-};
-
-/* gpt parent select structure */
-static struct pclk_sel gpt3_pclk_sel = {
-        .pclk_info = gpt3_pclk_info,
-        .pclk_count = ARRAY_SIZE(gpt3_pclk_info),
-        .pclk_sel_reg = PERIP_CLK_CFG,
-        .pclk_sel_mask = GPT_CLK_MASK,
-};
-
-/* gpt3 timer clock */
-static struct clk gpt3_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk_sel = &gpt3_pclk_sel,
-        .pclk_sel_shift = GPT3_CLK_SHIFT,
-        .recalc = &follow_parent,
-};
-
-/* clock derived from pll3 clk */
-/* usbh0 clock */
-static struct clk usbh0_clk = {
-        .pclk = &pll3_48m_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = USBH0_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* usbh1 clock */
-static struct clk usbh1_clk = {
-        .pclk = &pll3_48m_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = USBH1_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* usbd clock */
-static struct clk usbd_clk = {
-        .pclk = &pll3_48m_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = USBD_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* clock derived from ahb clk */
-/* apb masks structure */
-static struct bus_clk_masks apb_masks = {
-        .mask = HCLK_PCLK_RATIO_MASK,
-        .shift = HCLK_PCLK_RATIO_SHIFT,
-};
-
-/* apb configuration structure */
-static struct bus_clk_config apb_config = {
-        .reg = CORE_CLK_CFG,
-        .masks = &apb_masks,
-};
-
-/* apb clock */
-static struct clk apb_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &ahb_clk,
-        .calc_rate = &bus_calc_rate,
-        .recalc = &bus_clk_recalc,
-        .set_rate = &bus_clk_set_rate,
-        .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
-        .private_data = &apb_config,
-};
-
-/* i2c clock */
-static struct clk i2c_clk = {
-        .pclk = &ahb_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = I2C_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* dma clock */
-static struct clk dma_clk = {
-        .pclk = &ahb_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = DMA_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* jpeg clock */
-static struct clk jpeg_clk = {
-        .pclk = &ahb_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = JPEG_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* gmac clock */
-static struct clk gmac_clk = {
-        .pclk = &ahb_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = GMAC_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* smi clock */
-static struct clk smi_clk = {
-        .pclk = &ahb_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = SMI_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* fsmc clock */
-static struct clk fsmc_clk = {
-        .pclk = &ahb_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = FSMC_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* clock derived from apb clk */
-/* adc clock */
-static struct clk adc_clk = {
-        .pclk = &apb_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = ADC_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* ssp0 clock */
-static struct clk ssp0_clk = {
-        .pclk = &apb_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = SSP0_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* ssp1 clock */
-static struct clk ssp1_clk = {
-        .pclk = &apb_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = SSP1_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* ssp2 clock */
-static struct clk ssp2_clk = {
-        .pclk = &apb_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = SSP2_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* gpio0 ARM subsystem clock */
-static struct clk gpio0_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &apb_clk,
-        .recalc = &follow_parent,
-};
-
-/* gpio1 clock */
-static struct clk gpio1_clk = {
-        .pclk = &apb_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = GPIO1_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* gpio2 clock */
-static struct clk gpio2_clk = {
-        .pclk = &apb_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = GPIO2_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-static struct clk dummy_apb_pclk;
-
-/* array of all spear 6xx clock lookups */
-static struct clk_lookup spear_clk_lookups[] = {
-        { .con_id = "apb_pclk",         .clk = &dummy_apb_pclk},
-        /* root clks */
-        { .con_id = "osc_32k_clk",      .clk = &osc_32k_clk},
-        { .con_id = "osc_30m_clk",      .clk = &osc_30m_clk},
-        /* clock derived from 32 KHz os          clk */
-        { .dev_id = "rtc-spear",        .clk = &rtc_clk},
-        /* clock derived from 30 MHz os          clk */
-        { .con_id = "pll1_clk",         .clk = &pll1_clk},
-        { .con_id = "pll3_48m_clk",     .clk = &pll3_48m_clk},
-        { .dev_id = "wdt",              .clk = &wdt_clk},
-        /* clock derived from pll1 clk */
-        { .con_id = "cpu_clk",          .clk = &cpu_clk},
-        { .con_id = "ahb_clk",          .clk = &ahb_clk},
-        { .con_id = "uart_synth_clk",   .clk = &uart_synth_clk},
-        { .con_id = "firda_synth_clk",  .clk = &firda_synth_clk},
-        { .con_id = "clcd_synth_clk",   .clk = &clcd_synth_clk},
-        { .con_id = "gpt0_synth_clk",   .clk = &gpt0_synth_clk},
-        { .con_id = "gpt2_synth_clk",   .clk = &gpt2_synth_clk},
-        { .con_id = "gpt3_synth_clk",   .clk = &gpt3_synth_clk},
-        { .dev_id = "d0000000.serial",  .clk = &uart0_clk},
-        { .dev_id = "d0080000.serial",  .clk = &uart1_clk},
-        { .dev_id = "firda",            .clk = &firda_clk},
-        { .dev_id = "clcd",             .clk = &clcd_clk},
-        { .dev_id = "gpt0",             .clk = &gpt0_clk},
-        { .dev_id = "gpt1",             .clk = &gpt1_clk},
-        { .dev_id = "gpt2",             .clk = &gpt2_clk},
-        { .dev_id = "gpt3",             .clk = &gpt3_clk},
-        /* clock derived from pll3 clk */
-        { .dev_id = "designware_udc",   .clk = &usbd_clk},
-        { .con_id = "usbh.0_clk",       .clk = &usbh0_clk},
-        { .con_id = "usbh.1_clk",       .clk = &usbh1_clk},
-        /* clock derived from ahb clk */
-        { .con_id = "apb_clk",          .clk = &apb_clk},
-        { .dev_id = "d0200000.i2c",     .clk = &i2c_clk},
-        { .dev_id = "dma",              .clk = &dma_clk},
-        { .dev_id = "jpeg",             .clk = &jpeg_clk},
-        { .dev_id = "gmac",             .clk = &gmac_clk},
-        { .dev_id = "smi",              .clk = &smi_clk},
-        { .dev_id = "fsmc-nand",        .clk = &fsmc_clk},
-        /* clock derived from apb clk */
-        { .dev_id = "adc",              .clk = &adc_clk},
-        { .dev_id = "ssp-pl022.0",      .clk = &ssp0_clk},
-        { .dev_id = "ssp-pl022.1",      .clk = &ssp1_clk},
-        { .dev_id = "ssp-pl022.2",      .clk = &ssp2_clk},
-        { .dev_id = "f0100000.gpio",    .clk = &gpio0_clk},
-        { .dev_id = "fc980000.gpio",    .clk = &gpio1_clk},
-        { .dev_id = "d8100000.gpio",    .clk = &gpio2_clk},
-};
-
-void __init spear6xx_clk_init(void)
-{
-        int i;
-
-        for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
-                clk_register(&spear_clk_lookups[i]);
-
-        clk_init();
-}
diff --git a/arch/arm/mach-spear6xx/include/mach/generic.h b/arch/arm/mach-spear6xx/include/mach/generic.h
index 116b99301cf5..65514b159370 100644
--- a/arch/arm/mach-spear6xx/include/mach/generic.h
+++ b/arch/arm/mach-spear6xx/include/mach/generic.h
@@ -15,34 +15,9 @@
 #define __MACH_GENERIC_H
 
 #include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/amba/bus.h>
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
-
-/*
- * Each GPT has 2 timer channels
- * Following GPT channels will be used as clock source and clockevent
- */
-#define SPEAR_GPT0_BASE         SPEAR6XX_CPU_TMR_BASE
-#define SPEAR_GPT0_CHAN0_IRQ    IRQ_CPU_GPT1_1
-#define SPEAR_GPT0_CHAN1_IRQ    IRQ_CPU_GPT1_2
-
-/* Add spear6xx family device structure declarations here */
-extern struct amba_device gpio_device[];
-extern struct amba_device uart_device[];
-extern struct sys_timer spear6xx_timer;
-
-/* Add spear6xx family function declarations here */
-void __init spear_setup_timer(void);
-void __init spear6xx_map_io(void);
-void __init spear6xx_init_irq(void);
-void __init spear6xx_init(void);
-void __init spear600_init(void);
-void __init spear6xx_clk_init(void);
 
+void __init spear_setup_of_timer(void);
 void spear_restart(char, const char *);
-
-/* Add spear600 machine device structure declarations here */
+void __init spear6xx_clk_init(void);
 
 #endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/hardware.h b/arch/arm/mach-spear6xx/include/mach/hardware.h
index 0b3f96ae2848..40a8c178f10d 100644
--- a/arch/arm/mach-spear6xx/include/mach/hardware.h
+++ b/arch/arm/mach-spear6xx/include/mach/hardware.h
@@ -1,23 +1 @@
-/*
- * arch/arm/mach-spear6xx/include/mach/hardware.h
- *
- * Hardware definitions for SPEAr6xx machine family
- *
- * Copyright (C) 2009 ST Microelectronics
- * Rajeev Kumar<rajeev-dlh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_HARDWARE_H
-#define __MACH_HARDWARE_H
-
-#include <plat/hardware.h>
-#include <mach/spear.h>
-
-/* Vitual to physical translation of statically mapped space */
-#define IO_ADDRESS(x)           (x | 0xF0000000)
-
-#endif /* __MACH_HARDWARE_H */
+/* empty */
diff --git a/arch/arm/mach-spear6xx/include/mach/irqs.h b/arch/arm/mach-spear6xx/include/mach/irqs.h
index 8f214b03d75d..37a5c411a866 100644
--- a/arch/arm/mach-spear6xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear6xx/include/mach/irqs.h
@@ -16,82 +16,10 @@
 
 /* IRQ definitions */
 /* VIC 1 */
-#define IRQ_INTRCOMM_SW_IRQ                     0
-#define IRQ_INTRCOMM_CPU_1                      1
-#define IRQ_INTRCOMM_CPU_2                      2
-#define IRQ_INTRCOMM_RAS2A11_1                  3
-#define IRQ_INTRCOMM_RAS2A11_2                  4
-#define IRQ_INTRCOMM_RAS2A12_1                  5
-#define IRQ_INTRCOMM_RAS2A12_2                  6
-#define IRQ_GEN_RAS_0                           7
-#define IRQ_GEN_RAS_1                           8
-#define IRQ_GEN_RAS_2                           9
-#define IRQ_GEN_RAS_3                           10
-#define IRQ_GEN_RAS_4                           11
-#define IRQ_GEN_RAS_5                           12
-#define IRQ_GEN_RAS_6                           13
-#define IRQ_GEN_RAS_7                           14
-#define IRQ_GEN_RAS_8                           15
-#define IRQ_CPU_GPT1_1                          16
-#define IRQ_CPU_GPT1_2                          17
-#define IRQ_LOCAL_GPIO                          18
-#define IRQ_PLL_UNLOCK                          19
-#define IRQ_JPEG                                20
-#define IRQ_FSMC                                21
-#define IRQ_IRDA                                22
-#define IRQ_RESERVED                            23
-#define IRQ_UART_0                              24
-#define IRQ_UART_1                              25
-#define IRQ_SSP_1                               26
-#define IRQ_SSP_2                               27
-#define IRQ_I2C                                 28
-#define IRQ_GEN_RAS_9                           29
-#define IRQ_GEN_RAS_10                          30
-#define IRQ_GEN_RAS_11                          31
-
-/* VIC 2 */
-#define IRQ_APPL_GPT1_1                         32
-#define IRQ_APPL_GPT1_2                         33
-#define IRQ_APPL_GPT2_1                         34
-#define IRQ_APPL_GPT2_2                         35
-#define IRQ_APPL_GPIO                           36
-#define IRQ_APPL_SSP                            37
-#define IRQ_APPL_ADC                            38
-#define IRQ_APPL_RESERVED                       39
-#define IRQ_AHB_EXP_MASTER                      40
-#define IRQ_DDR_CONTROLLER                      41
-#define IRQ_BASIC_DMA                           42
-#define IRQ_BASIC_RESERVED1                     43
-#define IRQ_BASIC_SMI                           44
-#define IRQ_BASIC_CLCD                          45
-#define IRQ_EXP_AHB_1                           46
-#define IRQ_EXP_AHB_2                           47
-#define IRQ_BASIC_GPT1_1                        48
-#define IRQ_BASIC_GPT1_2                        49
-#define IRQ_BASIC_RTC                           50
-#define IRQ_BASIC_GPIO                          51
-#define IRQ_BASIC_WDT                           52
-#define IRQ_BASIC_RESERVED                      53
-#define IRQ_AHB_EXP_SLAVE                       54
-#define IRQ_GMAC_1                              55
-#define IRQ_GMAC_2                              56
-#define IRQ_USB_DEV                             57
-#define IRQ_USB_H_OHCI_0                        58
-#define IRQ_USB_H_EHCI_0                        59
-#define IRQ_USB_H_OHCI_1                        60
-#define IRQ_USB_H_EHCI_1                        61
-#define IRQ_EXP_AHB_3                           62
-#define IRQ_EXP_AHB_4                           63
-
 #define IRQ_VIC_END                             64
 
 /* GPIO pins virtual irqs */
-#define SPEAR_GPIO_INT_BASE     IRQ_VIC_END
-#define SPEAR_GPIO0_INT_BASE    SPEAR_GPIO_INT_BASE
-#define SPEAR_GPIO1_INT_BASE    (SPEAR_GPIO0_INT_BASE + 8)
-#define SPEAR_GPIO2_INT_BASE    (SPEAR_GPIO1_INT_BASE + 8)
-#define SPEAR_GPIO_INT_END      (SPEAR_GPIO2_INT_BASE + 8)
-#define VIRTUAL_IRQS            (SPEAR_GPIO_INT_END - IRQ_VIC_END)
-#define NR_IRQS                 (IRQ_VIC_END + VIRTUAL_IRQS)
+#define VIRTUAL_IRQS                            24
+#define NR_IRQS                                 (IRQ_VIC_END + VIRTUAL_IRQS)
 
 #endif  /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/misc_regs.h b/arch/arm/mach-spear6xx/include/mach/misc_regs.h
index 68c20a007b0d..179e45774b3a 100644
--- a/arch/arm/mach-spear6xx/include/mach/misc_regs.h
+++ b/arch/arm/mach-spear6xx/include/mach/misc_regs.h
@@ -14,161 +14,9 @@
 #ifndef __MACH_MISC_REGS_H
 #define __MACH_MISC_REGS_H
 
-#include <mach/hardware.h>
+#include <mach/spear.h>
 
 #define MISC_BASE               IOMEM(VA_SPEAR6XX_ICM3_MISC_REG_BASE)
-
-#define SOC_CFG_CTR             (MISC_BASE + 0x000)
-#define DIAG_CFG_CTR            (MISC_BASE + 0x004)
-#define PLL1_CTR                (MISC_BASE + 0x008)
-#define PLL1_FRQ                (MISC_BASE + 0x00C)
-#define PLL1_MOD                (MISC_BASE + 0x010)
-#define PLL2_CTR                (MISC_BASE + 0x014)
-/* PLL_CTR register masks */
-#define PLL_ENABLE              2
-#define PLL_MODE_SHIFT          4
-#define PLL_MODE_MASK           0x3
-#define PLL_MODE_NORMAL         0
-#define PLL_MODE_FRACTION       1
-#define PLL_MODE_DITH_DSB       2
-#define PLL_MODE_DITH_SSB       3
-
-#define PLL2_FRQ                (MISC_BASE + 0x018)
-/* PLL FRQ register masks */
-#define PLL_DIV_N_SHIFT         0
-#define PLL_DIV_N_MASK          0xFF
-#define PLL_DIV_P_SHIFT         8
-#define PLL_DIV_P_MASK          0x7
-#define PLL_NORM_FDBK_M_SHIFT   24
-#define PLL_NORM_FDBK_M_MASK    0xFF
-#define PLL_DITH_FDBK_M_SHIFT   16
-#define PLL_DITH_FDBK_M_MASK    0xFFFF
-
-#define PLL2_MOD                (MISC_BASE + 0x01C)
-#define PLL_CLK_CFG             (MISC_BASE + 0x020)
-#define CORE_CLK_CFG            (MISC_BASE + 0x024)
-/* CORE CLK CFG register masks */
-#define PLL_HCLK_RATIO_SHIFT    10
-#define PLL_HCLK_RATIO_MASK     0x3
-#define HCLK_PCLK_RATIO_SHIFT   8
-#define HCLK_PCLK_RATIO_MASK    0x3
-
-#define PERIP_CLK_CFG           (MISC_BASE + 0x028)
-/* PERIP_CLK_CFG register masks */
-#define CLCD_CLK_SHIFT          2
-#define CLCD_CLK_MASK           0x3
-#define UART_CLK_SHIFT          4
-#define UART_CLK_MASK           0x1
-#define FIRDA_CLK_SHIFT         5
-#define FIRDA_CLK_MASK          0x3
-#define GPT0_CLK_SHIFT          8
-#define GPT1_CLK_SHIFT          10
-#define GPT2_CLK_SHIFT          11
-#define GPT3_CLK_SHIFT          12
-#define GPT_CLK_MASK            0x1
-#define AUX_CLK_PLL3_VAL        0
-#define AUX_CLK_PLL1_VAL        1
-
-#define PERIP1_CLK_ENB          (MISC_BASE + 0x02C)
-/* PERIP1_CLK_ENB register masks */
-#define UART0_CLK_ENB           3
-#define UART1_CLK_ENB           4
-#define SSP0_CLK_ENB            5
-#define SSP1_CLK_ENB            6
-#define I2C_CLK_ENB             7
-#define JPEG_CLK_ENB            8
-#define FSMC_CLK_ENB            9
-#define FIRDA_CLK_ENB           10
-#define GPT2_CLK_ENB            11
-#define GPT3_CLK_ENB            12
-#define GPIO2_CLK_ENB           13
-#define SSP2_CLK_ENB            14
-#define ADC_CLK_ENB             15
-#define GPT1_CLK_ENB            11
-#define RTC_CLK_ENB             17
-#define GPIO1_CLK_ENB           18
-#define DMA_CLK_ENB             19
-#define SMI_CLK_ENB             21
-#define CLCD_CLK_ENB            22
-#define GMAC_CLK_ENB            23
-#define USBD_CLK_ENB            24
-#define USBH0_CLK_ENB           25
-#define USBH1_CLK_ENB           26
-
-#define SOC_CORE_ID             (MISC_BASE + 0x030)
-#define RAS_CLK_ENB             (MISC_BASE + 0x034)
-#define PERIP1_SOF_RST          (MISC_BASE + 0x038)
-/* PERIP1_SOF_RST register masks */
-#define JPEG_SOF_RST            8
-
-#define SOC_USER_ID             (MISC_BASE + 0x03C)
-#define RAS_SOF_RST             (MISC_BASE + 0x040)
-#define PRSC1_CLK_CFG           (MISC_BASE + 0x044)
-#define PRSC2_CLK_CFG           (MISC_BASE + 0x048)
-#define PRSC3_CLK_CFG           (MISC_BASE + 0x04C)
-/* gpt synthesizer register masks */
-#define GPT_MSCALE_SHIFT        0
-#define GPT_MSCALE_MASK         0xFFF
-#define GPT_NSCALE_SHIFT        12
-#define GPT_NSCALE_MASK         0xF
-
-#define AMEM_CLK_CFG            (MISC_BASE + 0x050)
-#define EXPI_CLK_CFG            (MISC_BASE + 0x054)
-#define CLCD_CLK_SYNT           (MISC_BASE + 0x05C)
-#define FIRDA_CLK_SYNT          (MISC_BASE + 0x060)
-#define UART_CLK_SYNT           (MISC_BASE + 0x064)
-#define GMAC_CLK_SYNT           (MISC_BASE + 0x068)
-#define RAS1_CLK_SYNT           (MISC_BASE + 0x06C)
-#define RAS2_CLK_SYNT           (MISC_BASE + 0x070)
-#define RAS3_CLK_SYNT           (MISC_BASE + 0x074)
-#define RAS4_CLK_SYNT           (MISC_BASE + 0x078)
-/* aux clk synthesiser register masks for irda to ras4 */
-#define AUX_SYNT_ENB            31
-#define AUX_EQ_SEL_SHIFT        30
-#define AUX_EQ_SEL_MASK         1
-#define AUX_EQ1_SEL             0
-#define AUX_EQ2_SEL             1
-#define AUX_XSCALE_SHIFT        16
-#define AUX_XSCALE_MASK         0xFFF
-#define AUX_YSCALE_SHIFT        0
-#define AUX_YSCALE_MASK         0xFFF
-
-#define ICM1_ARB_CFG            (MISC_BASE + 0x07C)
-#define ICM2_ARB_CFG            (MISC_BASE + 0x080)
-#define ICM3_ARB_CFG            (MISC_BASE + 0x084)
-#define ICM4_ARB_CFG            (MISC_BASE + 0x088)
-#define ICM5_ARB_CFG            (MISC_BASE + 0x08C)
-#define ICM6_ARB_CFG            (MISC_BASE + 0x090)
-#define ICM7_ARB_CFG            (MISC_BASE + 0x094)
-#define ICM8_ARB_CFG            (MISC_BASE + 0x098)
-#define ICM9_ARB_CFG            (MISC_BASE + 0x09C)
 #define DMA_CHN_CFG             (MISC_BASE + 0x0A0)
-#define USB2_PHY_CFG            (MISC_BASE + 0x0A4)
-#define GMAC_CFG_CTR            (MISC_BASE + 0x0A8)
-#define EXPI_CFG_CTR            (MISC_BASE + 0x0AC)
-#define PRC1_LOCK_CTR           (MISC_BASE + 0x0C0)
-#define PRC2_LOCK_CTR           (MISC_BASE + 0x0C4)
-#define PRC3_LOCK_CTR           (MISC_BASE + 0x0C8)
-#define PRC4_LOCK_CTR           (MISC_BASE + 0x0CC)
-#define PRC1_IRQ_CTR            (MISC_BASE + 0x0D0)
-#define PRC2_IRQ_CTR            (MISC_BASE + 0x0D4)
-#define PRC3_IRQ_CTR            (MISC_BASE + 0x0D8)
-#define PRC4_IRQ_CTR            (MISC_BASE + 0x0DC)
-#define PWRDOWN_CFG_CTR         (MISC_BASE + 0x0E0)
-#define COMPSSTL_1V8_CFG        (MISC_BASE + 0x0E4)
-#define COMPSSTL_2V5_CFG        (MISC_BASE + 0x0E8)
-#define COMPCOR_3V3_CFG         (MISC_BASE + 0x0EC)
-#define SSTLPAD_CFG_CTR         (MISC_BASE + 0x0F0)
-#define BIST1_CFG_CTR           (MISC_BASE + 0x0F4)
-#define BIST2_CFG_CTR           (MISC_BASE + 0x0F8)
-#define BIST3_CFG_CTR           (MISC_BASE + 0x0FC)
-#define BIST4_CFG_CTR           (MISC_BASE + 0x100)
-#define BIST5_CFG_CTR           (MISC_BASE + 0x104)
-#define BIST1_STS_RES           (MISC_BASE + 0x108)
-#define BIST2_STS_RES           (MISC_BASE + 0x10C)
-#define BIST3_STS_RES           (MISC_BASE + 0x110)
-#define BIST4_STS_RES           (MISC_BASE + 0x114)
-#define BIST5_STS_RES           (MISC_BASE + 0x118)
-#define SYSERR_CFG_CTR          (MISC_BASE + 0x11C)
 
 #endif /* __MACH_MISC_REGS_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/spear.h b/arch/arm/mach-spear6xx/include/mach/spear.h
index 7fd621532def..cb8ed2f4dc85 100644
--- a/arch/arm/mach-spear6xx/include/mach/spear.h
+++ b/arch/arm/mach-spear6xx/include/mach/spear.h
@@ -15,69 +15,25 @@
 #define __MACH_SPEAR6XX_H
 
 #include <asm/memory.h>
-#include <mach/spear600.h>
 
-#define SPEAR6XX_ML_SDRAM_BASE          UL(0x00000000)
 /* ICM1 - Low speed connection */
 #define SPEAR6XX_ICM1_BASE              UL(0xD0000000)
-
+#define VA_SPEAR6XX_ICM1_BASE           UL(0xFD000000)
 #define SPEAR6XX_ICM1_UART0_BASE        UL(0xD0000000)
-#define VA_SPEAR6XX_ICM1_UART0_BASE     IO_ADDRESS(SPEAR6XX_ICM1_UART0_BASE)
-
-#define SPEAR6XX_ICM1_UART1_BASE        UL(0xD0080000)
-#define SPEAR6XX_ICM1_SSP0_BASE         UL(0xD0100000)
-#define SPEAR6XX_ICM1_SSP1_BASE         UL(0xD0180000)
-#define SPEAR6XX_ICM1_I2C_BASE          UL(0xD0200000)
-#define SPEAR6XX_ICM1_JPEG_BASE         UL(0xD0800000)
-#define SPEAR6XX_ICM1_IRDA_BASE         UL(0xD1000000)
-#define SPEAR6XX_ICM1_FSMC_BASE         UL(0xD1800000)
-#define SPEAR6XX_ICM1_NAND_BASE         UL(0xD2000000)
-#define SPEAR6XX_ICM1_SRAM_BASE         UL(0xD2800000)
-
-/* ICM2 - Application Subsystem */
-#define SPEAR6XX_ICM2_BASE              UL(0xD8000000)
-#define SPEAR6XX_ICM2_TMR0_BASE         UL(0xD8000000)
-#define SPEAR6XX_ICM2_TMR1_BASE         UL(0xD8080000)
-#define SPEAR6XX_ICM2_GPIO_BASE         UL(0xD8100000)
-#define SPEAR6XX_ICM2_SSP2_BASE         UL(0xD8180000)
-#define SPEAR6XX_ICM2_ADC_BASE          UL(0xD8200000)
+#define VA_SPEAR6XX_ICM1_UART0_BASE     (VA_SPEAR6XX_ICM1_2_BASE | SPEAR6XX_ICM1_UART0_BASE)
 
 /* ML-1, 2 - Multi Layer CPU Subsystem */
 #define SPEAR6XX_ML_CPU_BASE            UL(0xF0000000)
-#define SPEAR6XX_CPU_TMR_BASE           UL(0xF0000000)
-#define SPEAR6XX_CPU_GPIO_BASE          UL(0xF0100000)
-#define SPEAR6XX_CPU_VIC_SEC_BASE       UL(0xF1000000)
-#define VA_SPEAR6XX_CPU_VIC_SEC_BASE    IO_ADDRESS(SPEAR6XX_CPU_VIC_SEC_BASE)
-#define SPEAR6XX_CPU_VIC_PRI_BASE       UL(0xF1100000)
-#define VA_SPEAR6XX_CPU_VIC_PRI_BASE    IO_ADDRESS(SPEAR6XX_CPU_VIC_PRI_BASE)
+#define VA_SPEAR6XX_ML_CPU_BASE         UL(0xF0000000)
 
 /* ICM3 - Basic Subsystem */
-#define SPEAR6XX_ICM3_BASE              UL(0xF8000000)
-#define SPEAR6XX_ICM3_SMEM_BASE         UL(0xF8000000)
 #define SPEAR6XX_ICM3_SMI_CTRL_BASE     UL(0xFC000000)
-#define SPEAR6XX_ICM3_CLCD_BASE         UL(0xFC200000)
+#define VA_SPEAR6XX_ICM3_SMI_CTRL_BASE  UL(0xFC000000)
 #define SPEAR6XX_ICM3_DMA_BASE          UL(0xFC400000)
-#define SPEAR6XX_ICM3_SDRAM_CTRL_BASE   UL(0xFC600000)
-#define SPEAR6XX_ICM3_TMR_BASE          UL(0xFC800000)
-#define SPEAR6XX_ICM3_WDT_BASE          UL(0xFC880000)
-#define SPEAR6XX_ICM3_RTC_BASE          UL(0xFC900000)
-#define SPEAR6XX_ICM3_GPIO_BASE         UL(0xFC980000)
 #define SPEAR6XX_ICM3_SYS_CTRL_BASE     UL(0xFCA00000)
-#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE  IO_ADDRESS(SPEAR6XX_ICM3_SYS_CTRL_BASE)
+#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE  (VA_SPEAR6XX_ICM3_SMI_CTRL_BASE | SPEAR6XX_ICM3_SYS_CTRL_BASE)
 #define SPEAR6XX_ICM3_MISC_REG_BASE     UL(0xFCA80000)
-#define VA_SPEAR6XX_ICM3_MISC_REG_BASE  IO_ADDRESS(SPEAR6XX_ICM3_MISC_REG_BASE)
-
-/* ICM4 - High Speed Connection */
-#define SPEAR6XX_ICM4_BASE              UL(0xE0000000)
-#define SPEAR6XX_ICM4_GMAC_BASE         UL(0xE0800000)
-#define SPEAR6XX_ICM4_USBD_FIFO_BASE    UL(0xE1000000)
-#define SPEAR6XX_ICM4_USBD_CSR_BASE     UL(0xE1100000)
-#define SPEAR6XX_ICM4_USBD_PLDT_BASE    UL(0xE1200000)
-#define SPEAR6XX_ICM4_USB_EHCI0_BASE    UL(0xE1800000)
-#define SPEAR6XX_ICM4_USB_OHCI0_BASE    UL(0xE1900000)
-#define SPEAR6XX_ICM4_USB_EHCI1_BASE    UL(0xE2000000)
-#define SPEAR6XX_ICM4_USB_OHCI1_BASE    UL(0xE2100000)
-#define SPEAR6XX_ICM4_USB_ARB_BASE      UL(0xE2800000)
+#define VA_SPEAR6XX_ICM3_MISC_REG_BASE  (VA_SPEAR6XX_ICM3_SMI_CTRL_BASE | SPEAR6XX_ICM3_MISC_REG_BASE)
 
 /* Debug uart for linux, will be used for debug and uncompress messages */
 #define SPEAR_DBG_UART_BASE             SPEAR6XX_ICM1_UART0_BASE
diff --git a/arch/arm/mach-spear6xx/include/mach/spear600.h b/arch/arm/mach-spear6xx/include/mach/spear600.h
deleted file mode 100644
index c068cc50b0fb..000000000000
--- a/arch/arm/mach-spear6xx/include/mach/spear600.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * arch/arm/mach-spear66xx/include/mach/spear600.h
- *
- * SPEAr600 Machine specific definition
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifdef  CONFIG_MACH_SPEAR600
-
-#ifndef __MACH_SPEAR600_H
-#define __MACH_SPEAR600_H
-
-#endif /* __MACH_SPEAR600_H */
-
-#endif /* CONFIG_MACH_SPEAR600 */
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index 2ed8b14c82c8..2e2e3596583e 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -13,41 +13,404 @@
  * warranty of any kind, whether express or implied.
  */
 
+#include <linux/amba/pl08x.h>
+#include <linux/clk.h>
+#include <linux/err.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <asm/hardware/pl080.h>
 #include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+#include <plat/pl080.h>
 #include <mach/generic.h>
-#include <mach/hardware.h>
+#include <mach/spear.h>
 
-/* Following will create static virtual/physical mappings */
-static struct map_desc spear6xx_io_desc[] __initdata = {
+/* dmac device registration */
+static struct pl08x_channel_data spear600_dma_info[] = {
         {
-                .virtual        = VA_SPEAR6XX_ICM1_UART0_BASE,
-                .pfn            = __phys_to_pfn(SPEAR6XX_ICM1_UART0_BASE),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE
+                .bus_id = "ssp1_rx",
+                .min_signal = 0,
+                .max_signal = 0,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
         }, {
-                .virtual        = VA_SPEAR6XX_CPU_VIC_PRI_BASE,
-                .pfn            = __phys_to_pfn(SPEAR6XX_CPU_VIC_PRI_BASE),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE
+                .bus_id = "ssp1_tx",
+                .min_signal = 1,
+                .max_signal = 1,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
         }, {
-                .virtual        = VA_SPEAR6XX_CPU_VIC_SEC_BASE,
-                .pfn            = __phys_to_pfn(SPEAR6XX_CPU_VIC_SEC_BASE),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE
+                .bus_id = "uart0_rx",
+                .min_signal = 2,
+                .max_signal = 2,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart0_tx",
+                .min_signal = 3,
+                .max_signal = 3,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart1_rx",
+                .min_signal = 4,
+                .max_signal = 4,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart1_tx",
+                .min_signal = 5,
+                .max_signal = 5,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ssp2_rx",
+                .min_signal = 6,
+                .max_signal = 6,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ssp2_tx",
+                .min_signal = 7,
+                .max_signal = 7,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ssp0_rx",
+                .min_signal = 8,
+                .max_signal = 8,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ssp0_tx",
+                .min_signal = 9,
+                .max_signal = 9,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "i2c_rx",
+                .min_signal = 10,
+                .max_signal = 10,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "i2c_tx",
+                .min_signal = 11,
+                .max_signal = 11,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "irda",
+                .min_signal = 12,
+                .max_signal = 12,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "adc",
+                .min_signal = 13,
+                .max_signal = 13,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "to_jpeg",
+                .min_signal = 14,
+                .max_signal = 14,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "from_jpeg",
+                .min_signal = 15,
+                .max_signal = 15,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras0_rx",
+                .min_signal = 0,
+                .max_signal = 0,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras0_tx",
+                .min_signal = 1,
+                .max_signal = 1,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras1_rx",
+                .min_signal = 2,
+                .max_signal = 2,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras1_tx",
+                .min_signal = 3,
+                .max_signal = 3,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras2_rx",
+                .min_signal = 4,
+                .max_signal = 4,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras2_tx",
+                .min_signal = 5,
+                .max_signal = 5,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras3_rx",
+                .min_signal = 6,
+                .max_signal = 6,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras3_tx",
+                .min_signal = 7,
+                .max_signal = 7,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras4_rx",
+                .min_signal = 8,
+                .max_signal = 8,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras4_tx",
+                .min_signal = 9,
+                .max_signal = 9,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras5_rx",
+                .min_signal = 10,
+                .max_signal = 10,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras5_tx",
+                .min_signal = 11,
+                .max_signal = 11,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras6_rx",
+                .min_signal = 12,
+                .max_signal = 12,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras6_tx",
+                .min_signal = 13,
+                .max_signal = 13,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras7_rx",
+                .min_signal = 14,
+                .max_signal = 14,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras7_tx",
+                .min_signal = 15,
+                .max_signal = 15,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
         }, {
-                .virtual        = VA_SPEAR6XX_ICM3_SYS_CTRL_BASE,
-                .pfn            = __phys_to_pfn(SPEAR6XX_ICM3_SYS_CTRL_BASE),
-                .length         = SZ_4K,
+                .bus_id = "ext0_rx",
+                .min_signal = 0,
+                .max_signal = 0,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext0_tx",
+                .min_signal = 1,
+                .max_signal = 1,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext1_rx",
+                .min_signal = 2,
+                .max_signal = 2,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext1_tx",
+                .min_signal = 3,
+                .max_signal = 3,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext2_rx",
+                .min_signal = 4,
+                .max_signal = 4,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext2_tx",
+                .min_signal = 5,
+                .max_signal = 5,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext3_rx",
+                .min_signal = 6,
+                .max_signal = 6,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext3_tx",
+                .min_signal = 7,
+                .max_signal = 7,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext4_rx",
+                .min_signal = 8,
+                .max_signal = 8,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext4_tx",
+                .min_signal = 9,
+                .max_signal = 9,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext5_rx",
+                .min_signal = 10,
+                .max_signal = 10,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext5_tx",
+                .min_signal = 11,
+                .max_signal = 11,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext6_rx",
+                .min_signal = 12,
+                .max_signal = 12,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext6_tx",
+                .min_signal = 13,
+                .max_signal = 13,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext7_rx",
+                .min_signal = 14,
+                .max_signal = 14,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext7_tx",
+                .min_signal = 15,
+                .max_signal = 15,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        },
+};
+
+struct pl08x_platform_data pl080_plat_data = {
+        .memcpy_channel = {
+                .bus_id = "memcpy",
+                .cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
+                        PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
+                        PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
+                        PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
+                        PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
+                        PL080_CONTROL_PROT_SYS),
+        },
+        .lli_buses = PL08X_AHB1,
+        .mem_buses = PL08X_AHB1,
+        .get_signal = pl080_get_signal,
+        .put_signal = pl080_put_signal,
+        .slave_channels = spear600_dma_info,
+        .num_slave_channels = ARRAY_SIZE(spear600_dma_info),
+};
+
+/*
+ * Following will create 16MB static virtual/physical mappings
+ * PHYSICAL             VIRTUAL
+ * 0xF0000000           0xF0000000
+ * 0xF1000000           0xF1000000
+ * 0xD0000000           0xFD000000
+ * 0xFC000000           0xFC000000
+ */
+struct map_desc spear6xx_io_desc[] __initdata = {
+        {
+                .virtual        = VA_SPEAR6XX_ML_CPU_BASE,
+                .pfn            = __phys_to_pfn(SPEAR6XX_ML_CPU_BASE),
+                .length         = 2 * SZ_16M,
+                .type           = MT_DEVICE
+        },      {
+                .virtual        = VA_SPEAR6XX_ICM1_BASE,
+                .pfn            = __phys_to_pfn(SPEAR6XX_ICM1_BASE),
+                .length         = SZ_16M,
                 .type           = MT_DEVICE
         }, {
-                .virtual        = VA_SPEAR6XX_ICM3_MISC_REG_BASE,
-                .pfn            = __phys_to_pfn(SPEAR6XX_ICM3_MISC_REG_BASE),
-                .length         = SZ_4K,
+                .virtual        = VA_SPEAR6XX_ICM3_SMI_CTRL_BASE,
+                .pfn            = __phys_to_pfn(SPEAR6XX_ICM3_SMI_CTRL_BASE),
+                .length         = SZ_16M,
                 .type           = MT_DEVICE
         },
 };
@@ -56,9 +419,6 @@ static struct map_desc spear6xx_io_desc[] __initdata = {
 void __init spear6xx_map_io(void)
 {
         iotable_init(spear6xx_io_desc, ARRAY_SIZE(spear6xx_io_desc));
-
-        /* This will initialize clock framework */
-        spear6xx_clk_init();
 }
 
 static void __init spear6xx_timer_init(void)
@@ -66,6 +426,8 @@ static void __init spear6xx_timer_init(void)
         char pclk_name[] = "pll3_48m_clk";
         struct clk *gpt_clk, *pclk;
 
+        spear6xx_clk_init();
+
         /* get the system timer clock */
         gpt_clk = clk_get_sys("gpt0", NULL);
         if (IS_ERR(gpt_clk)) {
@@ -85,16 +447,24 @@ static void __init spear6xx_timer_init(void)
         clk_put(gpt_clk);
         clk_put(pclk);
 
-        spear_setup_timer();
+        spear_setup_of_timer();
 }
 
 struct sys_timer spear6xx_timer = {
         .init = spear6xx_timer_init,
 };
 
+/* Add auxdata to pass platform data */
+struct of_dev_auxdata spear6xx_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("arm,pl080", SPEAR6XX_ICM3_DMA_BASE, NULL,
+                        &pl080_plat_data),
+        {}
+};
+
 static void __init spear600_dt_init(void)
 {
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+        of_platform_populate(NULL, of_default_bus_match_table,
+                        spear6xx_auxdata_lookup, NULL);
 }
 
 static const char *spear600_dt_board_compat[] = {
diff --git a/arch/arm/plat-spear/Kconfig b/arch/arm/plat-spear/Kconfig
index 1bb3dbce8810..4404f82d5979 100644
--- a/arch/arm/plat-spear/Kconfig
+++ b/arch/arm/plat-spear/Kconfig
@@ -8,10 +8,23 @@ choice
         prompt "ST SPEAr Family"
         default ARCH_SPEAR3XX
 
+config ARCH_SPEAR13XX
+        bool "ST SPEAr13xx with Device Tree"
+        select ARM_GIC
+        select CPU_V7
+        select USE_OF
+        select HAVE_SMP
+        select MIGHT_HAVE_CACHE_L2X0
+        select PINCTRL
+        help
+          Supports for ARM's SPEAR13XX family
+
 config ARCH_SPEAR3XX
-        bool "SPEAr3XX"
+        bool "ST SPEAr3xx with Device Tree"
         select ARM_VIC
         select CPU_ARM926T
+        select USE_OF
+        select PINCTRL
         help
           Supports for ARM's SPEAR3XX family
 
@@ -25,6 +38,7 @@ config ARCH_SPEAR6XX
 endchoice
 
 # Adding SPEAr machine specific configuration files
+source "arch/arm/mach-spear13xx/Kconfig"
 source "arch/arm/mach-spear3xx/Kconfig"
 source "arch/arm/mach-spear6xx/Kconfig"
 
diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile
index e0f2e5b9530c..2607bd05c525 100644
--- a/arch/arm/plat-spear/Makefile
+++ b/arch/arm/plat-spear/Makefile
@@ -3,6 +3,7 @@
 #
 
 # Common support
-obj-y   := clock.o restart.o time.o
+obj-y   := restart.o time.o
 
-obj-$(CONFIG_ARCH_SPEAR3XX)     += shirq.o padmux.o
+obj-$(CONFIG_ARCH_SPEAR3XX)     += pl080.o shirq.o
+obj-$(CONFIG_ARCH_SPEAR6XX)     += pl080.o
diff --git a/arch/arm/plat-spear/clock.c b/arch/arm/plat-spear/clock.c
deleted file mode 100644
index 67dd00381ea6..000000000000
--- a/arch/arm/plat-spear/clock.c
+++ /dev/null
@@ -1,1005 +0,0 @@
-/*
- * arch/arm/plat-spear/clock.c
- *
- * Clock framework for SPEAr platform
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/bug.h>
-#include <linux/clk.h>
-#include <linux/debugfs.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/list.h>
-#include <linux/module.h>
-#include <linux/spinlock.h>
-#include <plat/clock.h>
-
-static DEFINE_SPINLOCK(clocks_lock);
-static LIST_HEAD(root_clks);
-#ifdef CONFIG_DEBUG_FS
-static LIST_HEAD(clocks);
-#endif
-
-static void propagate_rate(struct clk *, int on_init);
-#ifdef CONFIG_DEBUG_FS
-static int clk_debugfs_reparent(struct clk *);
-#endif
-
-static int generic_clk_enable(struct clk *clk)
-{
-        unsigned int val;
-
-        if (!clk->en_reg)
-                return -EFAULT;
-
-        val = readl(clk->en_reg);
-        if (unlikely(clk->flags & RESET_TO_ENABLE))
-                val &= ~(1 << clk->en_reg_bit);
-        else
-                val |= 1 << clk->en_reg_bit;
-
-        writel(val, clk->en_reg);
-
-        return 0;
-}
-
-static void generic_clk_disable(struct clk *clk)
-{
-        unsigned int val;
-
-        if (!clk->en_reg)
-                return;
-
-        val = readl(clk->en_reg);
-        if (unlikely(clk->flags & RESET_TO_ENABLE))
-                val |= 1 << clk->en_reg_bit;
-        else
-                val &= ~(1 << clk->en_reg_bit);
-
-        writel(val, clk->en_reg);
-}
-
-/* generic clk ops */
-static struct clkops generic_clkops = {
-        .enable = generic_clk_enable,
-        .disable = generic_clk_disable,
-};
-
-/* returns current programmed clocks clock info structure */
-static struct pclk_info *pclk_info_get(struct clk *clk)
-{
-        unsigned int val, i;
-        struct pclk_info *info = NULL;
-
-        val = (readl(clk->pclk_sel->pclk_sel_reg) >> clk->pclk_sel_shift)
-                & clk->pclk_sel->pclk_sel_mask;
-
-        for (i = 0; i < clk->pclk_sel->pclk_count; i++) {
-                if (clk->pclk_sel->pclk_info[i].pclk_val == val)
-                        info = &clk->pclk_sel->pclk_info[i];
-        }
-
-        return info;
-}
-
-/*
- * Set Update pclk, and pclk_info of clk and add clock sibling node to current
- * parents children list
- */
-static void clk_reparent(struct clk *clk, struct pclk_info *pclk_info)
-{
-        unsigned long flags;
-
-        spin_lock_irqsave(&clocks_lock, flags);
-        list_del(&clk->sibling);
-        list_add(&clk->sibling, &pclk_info->pclk->children);
-
-        clk->pclk = pclk_info->pclk;
-        spin_unlock_irqrestore(&clocks_lock, flags);
-
-#ifdef CONFIG_DEBUG_FS
-        clk_debugfs_reparent(clk);
-#endif
-}
-
-static void do_clk_disable(struct clk *clk)
-{
-        if (!clk)
-                return;
-
-        if (!clk->usage_count) {
-                WARN_ON(1);
-                return;
-        }
-
-        clk->usage_count--;
-
-        if (clk->usage_count == 0) {
-                /*
-                 * Surely, there are no active childrens or direct users
-                 * of this clock
-                 */
-                if (clk->pclk)
-                        do_clk_disable(clk->pclk);
-
-                if (clk->ops && clk->ops->disable)
-                        clk->ops->disable(clk);
-        }
-}
-
-static int do_clk_enable(struct clk *clk)
-{
-        int ret = 0;
-
-        if (!clk)
-                return -EFAULT;
-
-        if (clk->usage_count == 0) {
-                if (clk->pclk) {
-                        ret = do_clk_enable(clk->pclk);
-                        if (ret)
-                                goto err;
-                }
-                if (clk->ops && clk->ops->enable) {
-                        ret = clk->ops->enable(clk);
-                        if (ret) {
-                                if (clk->pclk)
-                                        do_clk_disable(clk->pclk);
-                                goto err;
-                        }
-                }
-                /*
-                 * Since the clock is going to be used for the first
-                 * time please reclac
-                 */
-                if (clk->recalc) {
-                        ret = clk->recalc(clk);
-                        if (ret)
-                                goto err;
-                }
-        }
-        clk->usage_count++;
-err:
-        return ret;
-}
-
-/*
- * clk_enable - inform the system when the clock source should be running.
- * @clk: clock source
- *
- * If the clock can not be enabled/disabled, this should return success.
- *
- * Returns success (0) or negative errno.
- */
-int clk_enable(struct clk *clk)
-{
-        unsigned long flags;
-        int ret = 0;
-
-        spin_lock_irqsave(&clocks_lock, flags);
-        ret = do_clk_enable(clk);
-        spin_unlock_irqrestore(&clocks_lock, flags);
-        return ret;
-}
-EXPORT_SYMBOL(clk_enable);
-
-/*
- * clk_disable - inform the system when the clock source is no longer required.
- * @clk: clock source
- *
- * Inform the system that a clock source is no longer required by
- * a driver and may be shut down.
- *
- * Implementation detail: if the clock source is shared between
- * multiple drivers, clk_enable() calls must be balanced by the
- * same number of clk_disable() calls for the clock source to be
- * disabled.
- */
-void clk_disable(struct clk *clk)
-{
-        unsigned long flags;
-
-        spin_lock_irqsave(&clocks_lock, flags);
-        do_clk_disable(clk);
-        spin_unlock_irqrestore(&clocks_lock, flags);
-}
-EXPORT_SYMBOL(clk_disable);
-
-/**
- * clk_get_rate - obtain the current clock rate (in Hz) for a clock source.
- *               This is only valid once the clock source has been enabled.
- * @clk: clock source
- */
-unsigned long clk_get_rate(struct clk *clk)
-{
-        unsigned long flags, rate;
-
-        spin_lock_irqsave(&clocks_lock, flags);
-        rate = clk->rate;
-        spin_unlock_irqrestore(&clocks_lock, flags);
-
-        return rate;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-/**
- * clk_set_parent - set the parent clock source for this clock
- * @clk: clock source
- * @parent: parent clock source
- *
- * Returns success (0) or negative errno.
- */
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
-        int i, found = 0, val = 0;
-        unsigned long flags;
-
-        if (!clk || !parent)
-                return -EFAULT;
-        if (clk->pclk == parent)
-                return 0;
-        if (!clk->pclk_sel)
-                return -EPERM;
-
-        /* check if requested parent is in clk parent list */
-        for (i = 0; i < clk->pclk_sel->pclk_count; i++) {
-                if (clk->pclk_sel->pclk_info[i].pclk == parent) {
-                        found = 1;
-                        break;
-                }
-        }
-
-        if (!found)
-                return -EINVAL;
-
-        spin_lock_irqsave(&clocks_lock, flags);
-        /* reflect parent change in hardware */
-        val = readl(clk->pclk_sel->pclk_sel_reg);
-        val &= ~(clk->pclk_sel->pclk_sel_mask << clk->pclk_sel_shift);
-        val |= clk->pclk_sel->pclk_info[i].pclk_val << clk->pclk_sel_shift;
-        writel(val, clk->pclk_sel->pclk_sel_reg);
-        spin_unlock_irqrestore(&clocks_lock, flags);
-
-        /* reflect parent change in software */
-        clk_reparent(clk, &clk->pclk_sel->pclk_info[i]);
-
-        propagate_rate(clk, 0);
-        return 0;
-}
-EXPORT_SYMBOL(clk_set_parent);
-
-/**
- * clk_set_rate - set the clock rate for a clock source
- * @clk: clock source
- * @rate: desired clock rate in Hz
- *
- * Returns success (0) or negative errno.
- */
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned long flags;
-        int ret = -EINVAL;
-
-        if (!clk || !rate)
-                return -EFAULT;
-
-        if (clk->set_rate) {
-                spin_lock_irqsave(&clocks_lock, flags);
-                ret = clk->set_rate(clk, rate);
-                if (!ret)
-                        /* if successful -> propagate */
-                        propagate_rate(clk, 0);
-                spin_unlock_irqrestore(&clocks_lock, flags);
-        } else if (clk->pclk) {
-                u32 mult = clk->div_factor ? clk->div_factor : 1;
-                ret = clk_set_rate(clk->pclk, mult * rate);
-        }
-
-        return ret;
-}
-EXPORT_SYMBOL(clk_set_rate);
-
-/* registers clock in platform clock framework */
-void clk_register(struct clk_lookup *cl)
-{
-        struct clk *clk;
-        unsigned long flags;
-
-        if (!cl || !cl->clk)
-                return;
-        clk = cl->clk;
-
-        spin_lock_irqsave(&clocks_lock, flags);
-
-        INIT_LIST_HEAD(&clk->children);
-        if (clk->flags & ALWAYS_ENABLED)
-                clk->ops = NULL;
-        else if (!clk->ops)
-                clk->ops = &generic_clkops;
-
-        /* root clock don't have any parents */
-        if (!clk->pclk && !clk->pclk_sel) {
-                list_add(&clk->sibling, &root_clks);
-        } else if (clk->pclk && !clk->pclk_sel) {
-                /* add clocks with only one parent to parent's children list */
-                list_add(&clk->sibling, &clk->pclk->children);
-        } else {
-                /* clocks with more than one parent */
-                struct pclk_info *pclk_info;
-
-                pclk_info = pclk_info_get(clk);
-                if (!pclk_info) {
-                        pr_err("CLKDEV: invalid pclk info of clk with"
-                                        " %s dev_id and %s con_id\n",
-                                        cl->dev_id, cl->con_id);
-                } else {
-                        clk->pclk = pclk_info->pclk;
-                        list_add(&clk->sibling, &pclk_info->pclk->children);
-                }
-        }
-
-        spin_unlock_irqrestore(&clocks_lock, flags);
-
-        /* debugfs specific */
-#ifdef CONFIG_DEBUG_FS
-        list_add(&clk->node, &clocks);
-        clk->cl = cl;
-#endif
-
-        /* add clock to arm clockdev framework */
-        clkdev_add(cl);
-}
-
-/**
- * propagate_rate - recalculate and propagate all clocks to children
- * @pclk: parent clock required to be propogated
- * @on_init: flag for enabling clocks which are ENABLED_ON_INIT.
- *
- * Recalculates all children clocks
- */
-void propagate_rate(struct clk *pclk, int on_init)
-{
-        struct clk *clk, *_temp;
-        int ret = 0;
-
-        list_for_each_entry_safe(clk, _temp, &pclk->children, sibling) {
-                if (clk->recalc) {
-                        ret = clk->recalc(clk);
-                        /*
-                         * recalc will return error if clk out is not programmed
-                         * In this case configure default rate.
-                         */
-                        if (ret && clk->set_rate)
-                                clk->set_rate(clk, 0);
-                }
-                propagate_rate(clk, on_init);
-
-                if (!on_init)
-                        continue;
-
-                /* Enable clks enabled on init, in software view */
-                if (clk->flags & ENABLED_ON_INIT)
-                        do_clk_enable(clk);
-        }
-}
-
-/**
- * round_rate_index - return closest programmable rate index in rate_config tbl
- * @clk: ptr to clock structure
- * @drate: desired rate
- * @rate: final rate will be returned in this variable only.
- *
- * Finds index in rate_config for highest clk rate which is less than
- * requested rate. If there is no clk rate lesser than requested rate then
- * -EINVAL is returned. This routine assumes that rate_config is written
- * in incrementing order of clk rates.
- * If drate passed is zero then default rate is programmed.
- */
-static int
-round_rate_index(struct clk *clk, unsigned long drate, unsigned long *rate)
-{
-        unsigned long tmp = 0, prev_rate = 0;
-        int index;
-
-        if (!clk->calc_rate)
-                return -EFAULT;
-
-        if (!drate)
-                return -EINVAL;
-
-        /*
-         * This loops ends on two conditions:
-         * - as soon as clk is found with rate greater than requested rate.
-         * - if all clks in rate_config are smaller than requested rate.
-         */
-        for (index = 0; index < clk->rate_config.count; index++) {
-                prev_rate = tmp;
-                tmp = clk->calc_rate(clk, index);
-                if (drate < tmp) {
-                        index--;
-                        break;
-                }
-        }
-        /* return if can't find suitable clock */
-        if (index < 0) {
-                index = -EINVAL;
-                *rate = 0;
-        } else if (index == clk->rate_config.count) {
-                /* program with highest clk rate possible */
-                index = clk->rate_config.count - 1;
-                *rate = tmp;
-        } else
-                *rate = prev_rate;
-
-        return index;
-}
-
-/**
- * clk_round_rate - adjust a rate to the exact rate a clock can provide
- * @clk: clock source
- * @rate: desired clock rate in Hz
- *
- * Returns rounded clock rate in Hz, or negative errno.
- */
-long clk_round_rate(struct clk *clk, unsigned long drate)
-{
-        long rate = 0;
-        int index;
-
-        /*
-         * propagate call to parent who supports calc_rate. Similar approach is
-         * used in clk_set_rate.
-         */
-        if (!clk->calc_rate) {
-                u32 mult;
-                if (!clk->pclk)
-                        return clk->rate;
-
-                mult = clk->div_factor ? clk->div_factor : 1;
-                return clk_round_rate(clk->pclk, mult * drate) / mult;
-        }
-
-        index = round_rate_index(clk, drate, &rate);
-        if (index >= 0)
-                return rate;
-        else
-                return index;
-}
-EXPORT_SYMBOL(clk_round_rate);
-
-/*All below functions are called with lock held */
-
-/*
- * Calculates pll clk rate for specific value of mode, m, n and p
- *
- * In normal mode
- * rate = (2 * M[15:8] * Fin)/(N * 2^P)
- *
- * In Dithered mode
- * rate = (2 * M[15:0] * Fin)/(256 * N * 2^P)
- */
-unsigned long pll_calc_rate(struct clk *clk, int index)
-{
-        unsigned long rate = clk->pclk->rate;
-        struct pll_rate_tbl *tbls = clk->rate_config.tbls;
-        unsigned int mode;
-
-        mode = tbls[index].mode ? 256 : 1;
-        return (((2 * rate / 10000) * tbls[index].m) /
-                        (mode * tbls[index].n * (1 << tbls[index].p))) * 10000;
-}
-
-/*
- * calculates current programmed rate of pll1
- *
- * In normal mode
- * rate = (2 * M[15:8] * Fin)/(N * 2^P)
- *
- * In Dithered mode
- * rate = (2 * M[15:0] * Fin)/(256 * N * 2^P)
- */
-int pll_clk_recalc(struct clk *clk)
-{
-        struct pll_clk_config *config = clk->private_data;
-        unsigned int num = 2, den = 0, val, mode = 0;
-
-        mode = (readl(config->mode_reg) >> config->masks->mode_shift) &
-                config->masks->mode_mask;
-
-        val = readl(config->cfg_reg);
-        /* calculate denominator */
-        den = (val >> config->masks->div_p_shift) & config->masks->div_p_mask;
-        den = 1 << den;
-        den *= (val >> config->masks->div_n_shift) & config->masks->div_n_mask;
-
-        /* calculate numerator & denominator */
-        if (!mode) {
-                /* Normal mode */
-                num *= (val >> config->masks->norm_fdbk_m_shift) &
-                        config->masks->norm_fdbk_m_mask;
-        } else {
-                /* Dithered mode */
-                num *= (val >> config->masks->dith_fdbk_m_shift) &
-                        config->masks->dith_fdbk_m_mask;
-                den *= 256;
-        }
-
-        if (!den)
-                return -EINVAL;
-
-        clk->rate = (((clk->pclk->rate/10000) * num) / den) * 10000;
-        return 0;
-}
-
-/*
- * Configures new clock rate of pll
- */
-int pll_clk_set_rate(struct clk *clk, unsigned long desired_rate)
-{
-        struct pll_rate_tbl *tbls = clk->rate_config.tbls;
-        struct pll_clk_config *config = clk->private_data;
-        unsigned long val, rate;
-        int i;
-
-        i = round_rate_index(clk, desired_rate, &rate);
-        if (i < 0)
-                return i;
-
-        val = readl(config->mode_reg) &
-                ~(config->masks->mode_mask << config->masks->mode_shift);
-        val |= (tbls[i].mode & config->masks->mode_mask) <<
-                config->masks->mode_shift;
-        writel(val, config->mode_reg);
-
-        val = readl(config->cfg_reg) &
-                ~(config->masks->div_p_mask << config->masks->div_p_shift);
-        val |= (tbls[i].p & config->masks->div_p_mask) <<
-                config->masks->div_p_shift;
-        val &= ~(config->masks->div_n_mask << config->masks->div_n_shift);
-        val |= (tbls[i].n & config->masks->div_n_mask) <<
-                config->masks->div_n_shift;
-        val &= ~(config->masks->dith_fdbk_m_mask <<
-                        config->masks->dith_fdbk_m_shift);
-        if (tbls[i].mode)
-                val |= (tbls[i].m & config->masks->dith_fdbk_m_mask) <<
-                        config->masks->dith_fdbk_m_shift;
-        else
-                val |= (tbls[i].m & config->masks->norm_fdbk_m_mask) <<
-                        config->masks->norm_fdbk_m_shift;
-
-        writel(val, config->cfg_reg);
-
-        clk->rate = rate;
-
-        return 0;
-}
-
-/*
- * Calculates ahb, apb clk rate for specific value of div
- */
-unsigned long bus_calc_rate(struct clk *clk, int index)
-{
-        unsigned long rate = clk->pclk->rate;
-        struct bus_rate_tbl *tbls = clk->rate_config.tbls;
-
-        return rate / (tbls[index].div + 1);
-}
-
-/* calculates current programmed rate of ahb or apb bus */
-int bus_clk_recalc(struct clk *clk)
-{
-        struct bus_clk_config *config = clk->private_data;
-        unsigned int div;
-
-        div = ((readl(config->reg) >> config->masks->shift) &
-                        config->masks->mask) + 1;
-
-        if (!div)
-                return -EINVAL;
-
-        clk->rate = (unsigned long)clk->pclk->rate / div;
-        return 0;
-}
-
-/* Configures new clock rate of AHB OR APB bus */
-int bus_clk_set_rate(struct clk *clk, unsigned long desired_rate)
-{
-        struct bus_rate_tbl *tbls = clk->rate_config.tbls;
-        struct bus_clk_config *config = clk->private_data;
-        unsigned long val, rate;
-        int i;
-
-        i = round_rate_index(clk, desired_rate, &rate);
-        if (i < 0)
-                return i;
-
-        val = readl(config->reg) &
-                ~(config->masks->mask << config->masks->shift);
-        val |= (tbls[i].div & config->masks->mask) << config->masks->shift;
-        writel(val, config->reg);
-
-        clk->rate = rate;
-
-        return 0;
-}
-
-/*
- * gives rate for different values of eq, x and y
- *
- * Fout from synthesizer can be given from two equations:
- * Fout1 = (Fin * X/Y)/2                EQ1
- * Fout2 = Fin * X/Y                    EQ2
- */
-unsigned long aux_calc_rate(struct clk *clk, int index)
-{
-        unsigned long rate = clk->pclk->rate;
-        struct aux_rate_tbl *tbls = clk->rate_config.tbls;
-        u8 eq = tbls[index].eq ? 1 : 2;
-
-        return (((rate/10000) * tbls[index].xscale) /
-                        (tbls[index].yscale * eq)) * 10000;
-}
-
-/*
- * calculates current programmed rate of auxiliary synthesizers
- * used by: UART, FIRDA
- *
- * Fout from synthesizer can be given from two equations:
- * Fout1 = (Fin * X/Y)/2
- * Fout2 = Fin * X/Y
- *
- * Selection of eqn 1 or 2 is programmed in register
- */
-int aux_clk_recalc(struct clk *clk)
-{
-        struct aux_clk_config *config = clk->private_data;
-        unsigned int num = 1, den = 1, val, eqn;
-
-        val = readl(config->synth_reg);
-
-        eqn = (val >> config->masks->eq_sel_shift) &
-                config->masks->eq_sel_mask;
-        if (eqn == config->masks->eq1_mask)
-                den *= 2;
-
-        /* calculate numerator */
-        num = (val >> config->masks->xscale_sel_shift) &
-                config->masks->xscale_sel_mask;
-
-        /* calculate denominator */
-        den *= (val >> config->masks->yscale_sel_shift) &
-                config->masks->yscale_sel_mask;
-
-        if (!den)
-                return -EINVAL;
-
-        clk->rate = (((clk->pclk->rate/10000) * num) / den) * 10000;
-        return 0;
-}
-
-/* Configures new clock rate of auxiliary synthesizers used by: UART, FIRDA*/
-int aux_clk_set_rate(struct clk *clk, unsigned long desired_rate)
-{
-        struct aux_rate_tbl *tbls = clk->rate_config.tbls;
-        struct aux_clk_config *config = clk->private_data;
-        unsigned long val, rate;
-        int i;
-
-        i = round_rate_index(clk, desired_rate, &rate);
-        if (i < 0)
-                return i;
-
-        val = readl(config->synth_reg) &
-                ~(config->masks->eq_sel_mask << config->masks->eq_sel_shift);
-        val |= (tbls[i].eq & config->masks->eq_sel_mask) <<
-                config->masks->eq_sel_shift;
-        val &= ~(config->masks->xscale_sel_mask <<
-                        config->masks->xscale_sel_shift);
-        val |= (tbls[i].xscale & config->masks->xscale_sel_mask) <<
-                config->masks->xscale_sel_shift;
-        val &= ~(config->masks->yscale_sel_mask <<
-                        config->masks->yscale_sel_shift);
-        val |= (tbls[i].yscale & config->masks->yscale_sel_mask) <<
-                config->masks->yscale_sel_shift;
-        writel(val, config->synth_reg);
-
-        clk->rate = rate;
-
-        return 0;
-}
-
-/*
- * Calculates gpt clk rate for different values of mscale and nscale
- *
- * Fout= Fin/((2 ^ (N+1)) * (M+1))
- */
-unsigned long gpt_calc_rate(struct clk *clk, int index)
-{
-        unsigned long rate = clk->pclk->rate;
-        struct gpt_rate_tbl *tbls = clk->rate_config.tbls;
-
-        return rate / ((1 << (tbls[index].nscale + 1)) *
-                        (tbls[index].mscale + 1));
-}
-
-/*
- * calculates current programmed rate of gpt synthesizers
- * Fout from synthesizer can be given from below equations:
- * Fout= Fin/((2 ^ (N+1)) * (M+1))
- */
-int gpt_clk_recalc(struct clk *clk)
-{
-        struct gpt_clk_config *config = clk->private_data;
-        unsigned int div = 1, val;
-
-        val = readl(config->synth_reg);
-        div += (val >> config->masks->mscale_sel_shift) &
-                config->masks->mscale_sel_mask;
-        div *= 1 << (((val >> config->masks->nscale_sel_shift) &
-                                config->masks->nscale_sel_mask) + 1);
-
-        if (!div)
-                return -EINVAL;
-
-        clk->rate = (unsigned long)clk->pclk->rate / div;
-        return 0;
-}
-
-/* Configures new clock rate of gptiliary synthesizers used by: UART, FIRDA*/
-int gpt_clk_set_rate(struct clk *clk, unsigned long desired_rate)
-{
-        struct gpt_rate_tbl *tbls = clk->rate_config.tbls;
-        struct gpt_clk_config *config = clk->private_data;
-        unsigned long val, rate;
-        int i;
-
-        i = round_rate_index(clk, desired_rate, &rate);
-        if (i < 0)
-                return i;
-
-        val = readl(config->synth_reg) & ~(config->masks->mscale_sel_mask <<
-                        config->masks->mscale_sel_shift);
-        val |= (tbls[i].mscale & config->masks->mscale_sel_mask) <<
-                config->masks->mscale_sel_shift;
-        val &= ~(config->masks->nscale_sel_mask <<
-                        config->masks->nscale_sel_shift);
-        val |= (tbls[i].nscale & config->masks->nscale_sel_mask) <<
-                config->masks->nscale_sel_shift;
-        writel(val, config->synth_reg);
-
-        clk->rate = rate;
-
-        return 0;
-}
-
-/*
- * Calculates clcd clk rate for different values of div
- *
- * Fout from synthesizer can be given from below equation:
- * Fout= Fin/2*div (division factor)
- * div is 17 bits:-
- *      0-13 (fractional part)
- *      14-16 (integer part)
- * To calculate Fout we left shift val by 14 bits and divide Fin by
- * complete div (including fractional part) and then right shift the
- * result by 14 places.
- */
-unsigned long clcd_calc_rate(struct clk *clk, int index)
-{
-        unsigned long rate = clk->pclk->rate;
-        struct clcd_rate_tbl *tbls = clk->rate_config.tbls;
-
-        rate /= 1000;
-        rate <<= 12;
-        rate /= (2 * tbls[index].div);
-        rate >>= 12;
-        rate *= 1000;
-
-        return rate;
-}
-
-/*
- * calculates current programmed rate of clcd synthesizer
- * Fout from synthesizer can be given from below equation:
- * Fout= Fin/2*div (division factor)
- * div is 17 bits:-
- *      0-13 (fractional part)
- *      14-16 (integer part)
- * To calculate Fout we left shift val by 14 bits and divide Fin by
- * complete div (including fractional part) and then right shift the
- * result by 14 places.
- */
-int clcd_clk_recalc(struct clk *clk)
-{
-        struct clcd_clk_config *config = clk->private_data;
-        unsigned int div = 1;
-        unsigned long prate;
-        unsigned int val;
-
-        val = readl(config->synth_reg);
-        div = (val >> config->masks->div_factor_shift) &
-                config->masks->div_factor_mask;
-
-        if (!div)
-                return -EINVAL;
-
-        prate = clk->pclk->rate / 1000; /* first level division, make it KHz */
-
-        clk->rate = (((unsigned long)prate << 12) / (2 * div)) >> 12;
-        clk->rate *= 1000;
-        return 0;
-}
-
-/* Configures new clock rate of auxiliary synthesizers used by: UART, FIRDA*/
-int clcd_clk_set_rate(struct clk *clk, unsigned long desired_rate)
-{
-        struct clcd_rate_tbl *tbls = clk->rate_config.tbls;
-        struct clcd_clk_config *config = clk->private_data;
-        unsigned long val, rate;
-        int i;
-
-        i = round_rate_index(clk, desired_rate, &rate);
-        if (i < 0)
-                return i;
-
-        val = readl(config->synth_reg) & ~(config->masks->div_factor_mask <<
-                        config->masks->div_factor_shift);
-        val |= (tbls[i].div & config->masks->div_factor_mask) <<
-                config->masks->div_factor_shift;
-        writel(val, config->synth_reg);
-
-        clk->rate = rate;
-
-        return 0;
-}
-
-/*
- * Used for clocks that always have value as the parent clock divided by a
- * fixed divisor
- */
-int follow_parent(struct clk *clk)
-{
-        unsigned int div_factor = (clk->div_factor < 1) ? 1 : clk->div_factor;
-
-        clk->rate = clk->pclk->rate/div_factor;
-        return 0;
-}
-
-/**
- * recalc_root_clocks - recalculate and propagate all root clocks
- *
- * Recalculates all root clocks (clocks with no parent), which if the
- * clock's .recalc is set correctly, should also propagate their rates.
- */
-void recalc_root_clocks(void)
-{
-        struct clk *pclk;
-        unsigned long flags;
-        int ret = 0;
-
-        spin_lock_irqsave(&clocks_lock, flags);
-        list_for_each_entry(pclk, &root_clks, sibling) {
-                if (pclk->recalc) {
-                        ret = pclk->recalc(pclk);
-                        /*
-                         * recalc will return error if clk out is not programmed
-                         * In this case configure default clock.
-                         */
-                        if (ret && pclk->set_rate)
-                                pclk->set_rate(pclk, 0);
-                }
-                propagate_rate(pclk, 1);
-                /* Enable clks enabled on init, in software view */
-                if (pclk->flags & ENABLED_ON_INIT)
-                        do_clk_enable(pclk);
-        }
-        spin_unlock_irqrestore(&clocks_lock, flags);
-}
-
-void __init clk_init(void)
-{
-        recalc_root_clocks();
-}
-
-#ifdef CONFIG_DEBUG_FS
-/*
- *      debugfs support to trace clock tree hierarchy and attributes
- */
-static struct dentry *clk_debugfs_root;
-static int clk_debugfs_register_one(struct clk *c)
-{
-        int err;
-        struct dentry *d;
-        struct clk *pa = c->pclk;
-        char s[255];
-        char *p = s;
-
-        if (c) {
-                if (c->cl->con_id)
-                        p += sprintf(p, "%s", c->cl->con_id);
-                if (c->cl->dev_id)
-                        p += sprintf(p, "%s", c->cl->dev_id);
-        }
-        d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root);
-        if (!d)
-                return -ENOMEM;
-        c->dent = d;
-
-        d = debugfs_create_u32("usage_count", S_IRUGO, c->dent,
-                        (u32 *)&c->usage_count);
-        if (!d) {
-                err = -ENOMEM;
-                goto err_out;
-        }
-        d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
-        if (!d) {
-                err = -ENOMEM;
-                goto err_out;
-        }
-        d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags);
-        if (!d) {
-                err = -ENOMEM;
-                goto err_out;
-        }
-        return 0;
-
-err_out:
-        debugfs_remove_recursive(c->dent);
-        return err;
-}
-
-static int clk_debugfs_register(struct clk *c)
-{
-        int err;
-        struct clk *pa = c->pclk;
-
-        if (pa && !pa->dent) {
-                err = clk_debugfs_register(pa);
-                if (err)
-                        return err;
-        }
-
-        if (!c->dent) {
-                err = clk_debugfs_register_one(c);
-                if (err)
-                        return err;
-        }
-        return 0;
-}
-
-static int __init clk_debugfs_init(void)
-{
-        struct clk *c;
-        struct dentry *d;
-        int err;
-
-        d = debugfs_create_dir("clock", NULL);
-        if (!d)
-                return -ENOMEM;
-        clk_debugfs_root = d;
-
-        list_for_each_entry(c, &clocks, node) {
-                err = clk_debugfs_register(c);
-                if (err)
-                        goto err_out;
-        }
-        return 0;
-err_out:
-        debugfs_remove_recursive(clk_debugfs_root);
-        return err;
-}
-late_initcall(clk_debugfs_init);
-
-static int clk_debugfs_reparent(struct clk *c)
-{
-        debugfs_remove(c->dent);
-        return clk_debugfs_register_one(c);
-}
-#endif /* CONFIG_DEBUG_FS */
diff --git a/arch/arm/plat-spear/include/plat/clock.h b/arch/arm/plat-spear/include/plat/clock.h
deleted file mode 100644
index 0062bafef12d..000000000000
--- a/arch/arm/plat-spear/include/plat/clock.h
+++ /dev/null
@@ -1,249 +0,0 @@
-/*
- * arch/arm/plat-spear/include/plat/clock.h
- *
- * Clock framework definitions for SPEAr platform
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __PLAT_CLOCK_H
-#define __PLAT_CLOCK_H
-
-#include <linux/list.h>
-#include <linux/clkdev.h>
-#include <linux/types.h>
-
-/* clk structure flags */
-#define ALWAYS_ENABLED          (1 << 0) /* clock always enabled */
-#define RESET_TO_ENABLE         (1 << 1) /* reset register bit to enable clk */
-#define ENABLED_ON_INIT         (1 << 2) /* clocks enabled at init */
-
-/**
- * struct clkops - clock operations
- * @enable: pointer to clock enable function
- * @disable: pointer to clock disable function
- */
-struct clkops {
-        int (*enable) (struct clk *);
-        void (*disable) (struct clk *);
-};
-
-/**
- * struct pclk_info - parents info
- * @pclk: pointer to parent clk
- * @pclk_val: value to be written for selecting this parent
- */
-struct pclk_info {
-        struct clk *pclk;
-        u8 pclk_val;
-};
-
-/**
- * struct pclk_sel - parents selection configuration
- * @pclk_info: pointer to array of parent clock info
- * @pclk_count: number of parents
- * @pclk_sel_reg: register for selecting a parent
- * @pclk_sel_mask: mask for selecting parent (can be used to clear bits also)
- */
-struct pclk_sel {
-        struct pclk_info *pclk_info;
-        u8 pclk_count;
-        void __iomem *pclk_sel_reg;
-        unsigned int pclk_sel_mask;
-};
-
-/**
- * struct rate_config - clk rate configurations
- * @tbls: array of device specific clk rate tables, in ascending order of rates
- * @count: size of tbls array
- * @default_index: default setting when originally disabled
- */
-struct rate_config {
-        void *tbls;
-        u8 count;
-        u8 default_index;
-};
-
-/**
- * struct clk - clock structure
- * @usage_count: num of users who enabled this clock
- * @flags: flags for clock properties
- * @rate: programmed clock rate in Hz
- * @en_reg: clk enable/disable reg
- * @en_reg_bit: clk enable/disable bit
- * @ops: clk enable/disable ops - generic_clkops selected if NULL
- * @recalc: pointer to clock rate recalculate function
- * @set_rate: pointer to clock set rate function
- * @calc_rate: pointer to clock get rate function for index
- * @rate_config: rate configuration information, used by set_rate
- * @div_factor: division factor to parent clock.
- * @pclk: current parent clk
- * @pclk_sel: pointer to parent selection structure
- * @pclk_sel_shift: register shift for selecting parent of this clock
- * @children: list for childrens or this clock
- * @sibling: node for list of clocks having same parents
- * @private_data: clock specific private data
- * @node: list to maintain clocks linearly
- * @cl: clocklook up associated with this clock
- * @dent: object for debugfs
- */
-struct clk {
-        unsigned int usage_count;
-        unsigned int flags;
-        unsigned long rate;
-        void __iomem *en_reg;
-        u8 en_reg_bit;
-        const struct clkops *ops;
-        int (*recalc) (struct clk *);
-        int (*set_rate) (struct clk *, unsigned long rate);
-        unsigned long (*calc_rate)(struct clk *, int index);
-        struct rate_config rate_config;
-        unsigned int div_factor;
-
-        struct clk *pclk;
-        struct pclk_sel *pclk_sel;
-        unsigned int pclk_sel_shift;
-
-        struct list_head children;
-        struct list_head sibling;
-        void *private_data;
-#ifdef CONFIG_DEBUG_FS
-        struct list_head node;
-        struct clk_lookup *cl;
-        struct dentry *dent;
-#endif
-};
-
-/* pll configuration structure */
-struct pll_clk_masks {
-        u32 mode_mask;
-        u32 mode_shift;
-
-        u32 norm_fdbk_m_mask;
-        u32 norm_fdbk_m_shift;
-        u32 dith_fdbk_m_mask;
-        u32 dith_fdbk_m_shift;
-        u32 div_p_mask;
-        u32 div_p_shift;
-        u32 div_n_mask;
-        u32 div_n_shift;
-};
-
-struct pll_clk_config {
-        void __iomem *mode_reg;
-        void __iomem *cfg_reg;
-        struct pll_clk_masks *masks;
-};
-
-/* pll clk rate config structure */
-struct pll_rate_tbl {
-        u8 mode;
-        u16 m;
-        u8 n;
-        u8 p;
-};
-
-/* ahb and apb bus configuration structure */
-struct bus_clk_masks {
-        u32 mask;
-        u32 shift;
-};
-
-struct bus_clk_config {
-        void __iomem *reg;
-        struct bus_clk_masks *masks;
-};
-
-/* ahb and apb clk bus rate config structure */
-struct bus_rate_tbl {
-        u8 div;
-};
-
-/* Aux clk configuration structure: applicable to UART and FIRDA */
-struct aux_clk_masks {
-        u32 eq_sel_mask;
-        u32 eq_sel_shift;
-        u32 eq1_mask;
-        u32 eq2_mask;
-        u32 xscale_sel_mask;
-        u32 xscale_sel_shift;
-        u32 yscale_sel_mask;
-        u32 yscale_sel_shift;
-};
-
-struct aux_clk_config {
-        void __iomem *synth_reg;
-        struct aux_clk_masks *masks;
-};
-
-/* aux clk rate config structure */
-struct aux_rate_tbl {
-        u16 xscale;
-        u16 yscale;
-        u8 eq;
-};
-
-/* GPT clk configuration structure */
-struct gpt_clk_masks {
-        u32 mscale_sel_mask;
-        u32 mscale_sel_shift;
-        u32 nscale_sel_mask;
-        u32 nscale_sel_shift;
-};
-
-struct gpt_clk_config {
-        void __iomem *synth_reg;
-        struct gpt_clk_masks *masks;
-};
-
-/* gpt clk rate config structure */
-struct gpt_rate_tbl {
-        u16 mscale;
-        u16 nscale;
-};
-
-/* clcd clk configuration structure */
-struct clcd_synth_masks {
-        u32 div_factor_mask;
-        u32 div_factor_shift;
-};
-
-struct clcd_clk_config {
-        void __iomem *synth_reg;
-        struct clcd_synth_masks *masks;
-};
-
-/* clcd clk rate config structure */
-struct clcd_rate_tbl {
-        u16 div;
-};
-
-/* platform specific clock functions */
-void __init clk_init(void);
-void clk_register(struct clk_lookup *cl);
-void recalc_root_clocks(void);
-
-/* clock recalc & set rate functions */
-int follow_parent(struct clk *clk);
-unsigned long pll_calc_rate(struct clk *clk, int index);
-int pll_clk_recalc(struct clk *clk);
-int pll_clk_set_rate(struct clk *clk, unsigned long desired_rate);
-unsigned long bus_calc_rate(struct clk *clk, int index);
-int bus_clk_recalc(struct clk *clk);
-int bus_clk_set_rate(struct clk *clk, unsigned long desired_rate);
-unsigned long gpt_calc_rate(struct clk *clk, int index);
-int gpt_clk_recalc(struct clk *clk);
-int gpt_clk_set_rate(struct clk *clk, unsigned long desired_rate);
-unsigned long aux_calc_rate(struct clk *clk, int index);
-int aux_clk_recalc(struct clk *clk);
-int aux_clk_set_rate(struct clk *clk, unsigned long desired_rate);
-unsigned long clcd_calc_rate(struct clk *clk, int index);
-int clcd_clk_recalc(struct clk *clk);
-int clcd_clk_set_rate(struct clk *clk, unsigned long desired_rate);
-
-#endif /* __PLAT_CLOCK_H */
diff --git a/arch/arm/plat-spear/include/plat/debug-macro.S b/arch/arm/plat-spear/include/plat/debug-macro.S
index 02b160a1ec9b..ab3de721c5db 100644
--- a/arch/arm/plat-spear/include/plat/debug-macro.S
+++ b/arch/arm/plat-spear/include/plat/debug-macro.S
@@ -12,7 +12,7 @@
  */
 
 #include <linux/amba/serial.h>
-#include <mach/hardware.h>
+#include <mach/spear.h>
 
                 .macro  addruart, rp, rv, tmp
                 mov     \rp, #SPEAR_DBG_UART_BASE               @ Physical base
diff --git a/arch/arm/plat-spear/include/plat/hardware.h b/arch/arm/plat-spear/include/plat/hardware.h
deleted file mode 100644
index 70187d763e26..000000000000
--- a/arch/arm/plat-spear/include/plat/hardware.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * arch/arm/plat-spear/include/plat/hardware.h
- *
- * Hardware definitions for SPEAr
- *
- * Copyright (C) 2010 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __PLAT_HARDWARE_H
-#define __PLAT_HARDWARE_H
-
-#endif /* __PLAT_HARDWARE_H */
diff --git a/arch/arm/plat-spear/include/plat/padmux.h b/arch/arm/plat-spear/include/plat/padmux.h
deleted file mode 100644
index 877f3adcf610..000000000000
--- a/arch/arm/plat-spear/include/plat/padmux.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * arch/arm/plat-spear/include/plat/padmux.h
- *
- * SPEAr platform specific gpio pads muxing file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __PLAT_PADMUX_H
-#define __PLAT_PADMUX_H
-
-#include <linux/types.h>
-
-/*
- * struct pmx_reg: configuration structure for mode reg and mux reg
- *
- * offset: offset of mode reg
- * mask: mask of mode reg
- */
-struct pmx_reg {
-        u32 offset;
-        u32 mask;
-};
-
-/*
- * struct pmx_dev_mode: configuration structure every group of modes of a device
- *
- * ids: all modes for this configuration
- * mask: mask for supported mode
- */
-struct pmx_dev_mode {
-        u32 ids;
-        u32 mask;
-};
-
-/*
- * struct pmx_mode: mode definition structure
- *
- * name: mode name
- * mask: mode mask
- */
-struct pmx_mode {
-        char *name;
-        u32 id;
-        u32 mask;
-};
-
-/*
- * struct pmx_dev: device definition structure
- *
- * name: device name
- * modes: device configuration array for different modes supported
- * mode_count: size of modes array
- * is_active: is peripheral active/enabled
- * enb_on_reset: if 1, mask bits to be cleared in reg otherwise to be set in reg
- */
-struct pmx_dev {
-        char *name;
-        struct pmx_dev_mode *modes;
-        u8 mode_count;
-        bool is_active;
-        bool enb_on_reset;
-};
-
-/*
- * struct pmx_driver: driver definition structure
- *
- * mode: mode to be set
- * devs: array of pointer to pmx devices
- * devs_count: ARRAY_SIZE of devs
- * base: base address of soc config registers
- * mode_reg: structure of mode config register
- * mux_reg: structure of device mux config register
- */
-struct pmx_driver {
-        struct pmx_mode *mode;
-        struct pmx_dev **devs;
-        u8 devs_count;
-        u32 *base;
-        struct pmx_reg mode_reg;
-        struct pmx_reg mux_reg;
-};
-
-/* pmx functions */
-int pmx_register(struct pmx_driver *driver);
-
-#endif /* __PLAT_PADMUX_H */
diff --git a/arch/arm/plat-spear/include/plat/pl080.h b/arch/arm/plat-spear/include/plat/pl080.h
new file mode 100644
index 000000000000..e14a3e4932f9
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/pl080.h
@@ -0,0 +1,21 @@
+/*
+ * arch/arm/plat-spear/include/plat/pl080.h
+ *
+ * DMAC pl080 definitions for SPEAr platform
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PLAT_PL080_H
+#define __PLAT_PL080_H
+
+struct pl08x_dma_chan;
+int pl080_get_signal(struct pl08x_dma_chan *ch);
+void pl080_put_signal(struct pl08x_dma_chan *ch);
+
+#endif /* __PLAT_PL080_H */
diff --git a/arch/arm/plat-spear/include/plat/uncompress.h b/arch/arm/plat-spear/include/plat/uncompress.h
index 1bf84527aee4..6dd455bafdfd 100644
--- a/arch/arm/plat-spear/include/plat/uncompress.h
+++ b/arch/arm/plat-spear/include/plat/uncompress.h
@@ -13,7 +13,7 @@
 
 #include <linux/io.h>
 #include <linux/amba/serial.h>
-#include <mach/hardware.h>
+#include <mach/spear.h>
 
 #ifndef __PLAT_UNCOMPRESS_H
 #define __PLAT_UNCOMPRESS_H
diff --git a/arch/arm/plat-spear/padmux.c b/arch/arm/plat-spear/padmux.c
deleted file mode 100644
index 555eec6dc1cb..000000000000
--- a/arch/arm/plat-spear/padmux.c
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
- * arch/arm/plat-spear/include/plat/padmux.c
- *
- * SPEAr platform specific gpio pads muxing source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-#include <plat/padmux.h>
-
-/*
- * struct pmx: pmx definition structure
- *
- * base: base address of configuration registers
- * mode_reg: mode configurations
- * mux_reg: muxing configurations
- * active_mode: pointer to current active mode
- */
-struct pmx {
-        u32 base;
-        struct pmx_reg mode_reg;
-        struct pmx_reg mux_reg;
-        struct pmx_mode *active_mode;
-};
-
-static struct pmx *pmx;
-
-/**
- * pmx_mode_set - Enables an multiplexing mode
- * @mode - pointer to pmx mode
- *
- * It will set mode of operation in hardware.
- * Returns -ve on Err otherwise 0
- */
-static int pmx_mode_set(struct pmx_mode *mode)
-{
-        u32 val;
-
-        if (!mode->name)
-                return -EFAULT;
-
-        pmx->active_mode = mode;
-
-        val = readl(pmx->base + pmx->mode_reg.offset);
-        val &= ~pmx->mode_reg.mask;
-        val |= mode->mask & pmx->mode_reg.mask;
-        writel(val, pmx->base + pmx->mode_reg.offset);
-
-        return 0;
-}
-
-/**
- * pmx_devs_enable - Enables list of devices
- * @devs - pointer to pmx device array
- * @count - number of devices to enable
- *
- * It will enable pads for all required peripherals once and only once.
- * If peripheral is not supported by current mode then request is rejected.
- * Conflicts between peripherals are not handled and peripherals will be
- * enabled in the order they are present in pmx_dev array.
- * In case of conflicts last peripheral enabled will be present.
- * Returns -ve on Err otherwise 0
- */
-static int pmx_devs_enable(struct pmx_dev **devs, u8 count)
-{
-        u32 val, i, mask;
-
-        if (!count)
-                return -EINVAL;
-
-        val = readl(pmx->base + pmx->mux_reg.offset);
-        for (i = 0; i < count; i++) {
-                u8 j = 0;
-
-                if (!devs[i]->name || !devs[i]->modes) {
-                        printk(KERN_ERR "padmux: dev name or modes is null\n");
-                        continue;
-                }
-                /* check if peripheral exists in active mode */
-                if (pmx->active_mode) {
-                        bool found = false;
-                        for (j = 0; j < devs[i]->mode_count; j++) {
-                                if (devs[i]->modes[j].ids &
-                                                pmx->active_mode->id) {
-                                        found = true;
-                                        break;
-                                }
-                        }
-                        if (found == false) {
-                                printk(KERN_ERR "%s device not available in %s"\
-                                                "mode\n", devs[i]->name,
-                                                pmx->active_mode->name);
-                                continue;
-                        }
-                }
-
-                /* enable peripheral */
-                mask = devs[i]->modes[j].mask & pmx->mux_reg.mask;
-                if (devs[i]->enb_on_reset)
-                        val &= ~mask;
-                else
-                        val |= mask;
-
-                devs[i]->is_active = true;
-        }
-        writel(val, pmx->base + pmx->mux_reg.offset);
-        kfree(pmx);
-
-        /* this will ensure that multiplexing can't be changed now */
-        pmx = (struct pmx *)-1;
-
-        return 0;
-}
-
-/**
- * pmx_register - registers a platform requesting pad mux feature
- * @driver - pointer to driver structure containing driver specific parameters
- *
- * Also this must be called only once. This will allocate memory for pmx
- * structure, will call pmx_mode_set, will call pmx_devs_enable.
- * Returns -ve on Err otherwise 0
- */
-int pmx_register(struct pmx_driver *driver)
-{
-        int ret = 0;
-
-        if (pmx)
-                return -EPERM;
-        if (!driver->base || !driver->devs)
-                return -EFAULT;
-
-        pmx = kzalloc(sizeof(*pmx), GFP_KERNEL);
-        if (!pmx)
-                return -ENOMEM;
-
-        pmx->base = (u32)driver->base;
-        pmx->mode_reg.offset = driver->mode_reg.offset;
-        pmx->mode_reg.mask = driver->mode_reg.mask;
-        pmx->mux_reg.offset = driver->mux_reg.offset;
-        pmx->mux_reg.mask = driver->mux_reg.mask;
-
-        /* choose mode to enable */
-        if (driver->mode) {
-                ret = pmx_mode_set(driver->mode);
-                if (ret)
-                        goto pmx_fail;
-        }
-        ret = pmx_devs_enable(driver->devs, driver->devs_count);
-        if (ret)
-                goto pmx_fail;
-
-        return 0;
-
-pmx_fail:
-        return ret;
-}
diff --git a/arch/arm/plat-spear/pl080.c b/arch/arm/plat-spear/pl080.c
new file mode 100644
index 000000000000..a56a067717c1
--- /dev/null
+++ b/arch/arm/plat-spear/pl080.c
@@ -0,0 +1,80 @@
+/*
+ * arch/arm/plat-spear/pl080.c
+ *
+ * DMAC pl080 definitions for SPEAr platform
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/amba/pl08x.h>
+#include <linux/amba/bus.h>
+#include <linux/bug.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/spinlock_types.h>
+#include <mach/spear.h>
+#include <mach/misc_regs.h>
+
+static spinlock_t lock = __SPIN_LOCK_UNLOCKED(x);
+
+struct {
+        unsigned char busy;
+        unsigned char val;
+} signals[16] = {{0, 0}, };
+
+int pl080_get_signal(struct pl08x_dma_chan *ch)
+{
+        const struct pl08x_channel_data *cd = ch->cd;
+        unsigned int signal = cd->min_signal, val;
+        unsigned long flags;
+
+        spin_lock_irqsave(&lock, flags);
+
+        /* Return if signal is already acquired by somebody else */
+        if (signals[signal].busy &&
+                        (signals[signal].val != cd->muxval)) {
+                spin_unlock_irqrestore(&lock, flags);
+                return -EBUSY;
+        }
+
+        /* If acquiring for the first time, configure it */
+        if (!signals[signal].busy) {
+                val = readl(DMA_CHN_CFG);
+
+                /*
+                 * Each request line has two bits in DMA_CHN_CFG register. To
+                 * goto the bits of current request line, do left shift of
+                 * value by 2 * signal number.
+                 */
+                val &= ~(0x3 << (signal * 2));
+                val |= cd->muxval << (signal * 2);
+                writel(val, DMA_CHN_CFG);
+        }
+
+        signals[signal].busy++;
+        signals[signal].val = cd->muxval;
+        spin_unlock_irqrestore(&lock, flags);
+
+        return signal;
+}
+
+void pl080_put_signal(struct pl08x_dma_chan *ch)
+{
+        const struct pl08x_channel_data *cd = ch->cd;
+        unsigned long flags;
+
+        spin_lock_irqsave(&lock, flags);
+
+        /* if signal is not used */
+        if (!signals[cd->min_signal].busy)
+                BUG();
+
+        signals[cd->min_signal].busy--;
+
+        spin_unlock_irqrestore(&lock, flags);
+}
diff --git a/arch/arm/plat-spear/restart.c b/arch/arm/plat-spear/restart.c
index 16f203e78d89..ea0a61302b7e 100644
--- a/arch/arm/plat-spear/restart.c
+++ b/arch/arm/plat-spear/restart.c
@@ -13,9 +13,10 @@
 #include <linux/io.h>
 #include <asm/system_misc.h>
 #include <asm/hardware/sp810.h>
-#include <mach/hardware.h>
+#include <mach/spear.h>
 #include <mach/generic.h>
 
+#define SPEAR13XX_SYS_SW_RES                    (VA_MISC_BASE + 0x204)
 void spear_restart(char mode, const char *cmd)
 {
         if (mode == 's') {
@@ -23,6 +24,10 @@ void spear_restart(char mode, const char *cmd)
                 soft_restart(0);
         } else {
                 /* hardware reset, Use on-chip reset capability */
+#ifdef CONFIG_ARCH_SPEAR13XX
+                writel_relaxed(0x01, SPEAR13XX_SYS_SW_RES);
+#else
                 sysctl_soft_reset((void __iomem *)VA_SPEAR_SYS_CTRL_BASE);
+#endif
         }
 }
diff --git a/arch/arm/plat-spear/time.c b/arch/arm/plat-spear/time.c
index abb5bdecd509..03321af5de9f 100644
--- a/arch/arm/plat-spear/time.c
+++ b/arch/arm/plat-spear/time.c
@@ -15,14 +15,15 @@
 #include <linux/err.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
+#include <linux/ioport.h>
 #include <linux/io.h>
 #include <linux/kernel.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
 #include <linux/time.h>
 #include <linux/irq.h>
 #include <asm/mach/time.h>
 #include <mach/generic.h>
-#include <mach/hardware.h>
-#include <mach/irqs.h>
 
 /*
  * We would use TIMER0 and TIMER1 as clockevent and clocksource.
@@ -175,7 +176,7 @@ static struct irqaction spear_timer_irq = {
         .handler = spear_timer_interrupt
 };
 
-static void __init spear_clockevent_init(void)
+static void __init spear_clockevent_init(int irq)
 {
         u32 tick_rate;
 
@@ -195,22 +196,35 @@ static void __init spear_clockevent_init(void)
 
         clockevents_register_device(&clkevt);
 
-        setup_irq(SPEAR_GPT0_CHAN0_IRQ, &spear_timer_irq);
+        setup_irq(irq, &spear_timer_irq);
 }
 
-void __init spear_setup_timer(void)
+const static struct of_device_id timer_of_match[] __initconst = {
+        { .compatible = "st,spear-timer", },
+        { },
+};
+
+void __init spear_setup_of_timer(void)
 {
-        int ret;
+        struct device_node *np;
+        int irq, ret;
+
+        np = of_find_matching_node(NULL, timer_of_match);
+        if (!np) {
+                pr_err("%s: No timer passed via DT\n", __func__);
+                return;
+        }
 
-        if (!request_mem_region(SPEAR_GPT0_BASE, SZ_1K, "gpt0")) {
-                pr_err("%s:cannot get IO addr\n", __func__);
+        irq = irq_of_parse_and_map(np, 0);
+        if (!irq) {
+                pr_err("%s: No irq passed for timer via DT\n", __func__);
                 return;
         }
 
-        gpt_base = (void __iomem *)ioremap(SPEAR_GPT0_BASE, SZ_1K);
+        gpt_base = of_iomap(np, 0);
         if (!gpt_base) {
-                pr_err("%s:ioremap failed for gpt\n", __func__);
-                goto err_mem;
+                pr_err("%s: of iomap failed\n", __func__);
+                return;
         }
 
         gpt_clk = clk_get_sys("gpt0", NULL);
@@ -219,21 +233,19 @@ void __init spear_setup_timer(void)
                 goto err_iomap;
         }
 
-        ret = clk_enable(gpt_clk);
+        ret = clk_prepare_enable(gpt_clk);
         if (ret < 0) {
-                pr_err("%s:couldn't enable gpt clock\n", __func__);
-                goto err_clk;
+                pr_err("%s:couldn't prepare-enable gpt clock\n", __func__);
+                goto err_prepare_enable_clk;
         }
 
-        spear_clockevent_init();
+        spear_clockevent_init(irq);
         spear_clocksource_init();
 
         return;
 
-err_clk:
+err_prepare_enable_clk:
         clk_put(gpt_clk);
 err_iomap:
         iounmap(gpt_base);
-err_mem:
-        release_mem_region(SPEAR_GPT0_BASE, SZ_1K);
 }
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 165e1febae53..4864407e3fc4 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -12,6 +12,7 @@ config HAVE_MACH_CLKDEV
 config COMMON_CLK
         bool
         select HAVE_CLK_PREPARE
+        select CLKDEV_LOOKUP
         ---help---
           The common clock framework is a single definition of struct
           clk, useful across many platforms, as well as an
@@ -22,17 +23,6 @@ config COMMON_CLK
 menu "Common Clock Framework"
         depends on COMMON_CLK
 
-config COMMON_CLK_DISABLE_UNUSED
-        bool "Disabled unused clocks at boot"
-        depends on COMMON_CLK
-        ---help---
-          Traverses the entire clock tree and disables any clocks that are
-          enabled in hardware but have not been enabled by any device drivers.
-          This saves power and keeps the software model of the clock in line
-          with reality.
-
-          If in doubt, say "N".
-
 config COMMON_CLK_DEBUG
         bool "DebugFS representation of clock tree"
         depends on COMMON_CLK
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 1f736bc11c4b..0f5e03d1ef5c 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -1,4 +1,7 @@
 
 obj-$(CONFIG_CLKDEV_LOOKUP)     += clkdev.o
 obj-$(CONFIG_COMMON_CLK)        += clk.o clk-fixed-rate.o clk-gate.o \
-                                   clk-mux.o clk-divider.o
+                                   clk-mux.o clk-divider.o clk-fixed-factor.o
+
+# SoCs specific
+obj-$(CONFIG_PLAT_SPEAR)        += spear/
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index d5ac6a75ea57..8ea11b444528 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -45,7 +45,6 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
 
         return parent_rate / div;
 }
-EXPORT_SYMBOL_GPL(clk_divider_recalc_rate);
 
 /*
  * The reverse of DIV_ROUND_UP: The maximum number which
@@ -68,8 +67,8 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
         if (divider->flags & CLK_DIVIDER_ONE_BASED)
                 maxdiv--;
 
-        if (!best_parent_rate) {
-                parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
+        if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
+                parent_rate = *best_parent_rate;
                 bestdiv = DIV_ROUND_UP(parent_rate, rate);
                 bestdiv = bestdiv == 0 ? 1 : bestdiv;
                 bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
@@ -109,24 +108,18 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
         int div;
         div = clk_divider_bestdiv(hw, rate, prate);
 
-        if (prate)
-                return *prate / div;
-        else {
-                unsigned long r;
-                r = __clk_get_rate(__clk_get_parent(hw->clk));
-                return r / div;
-        }
+        return *prate / div;
 }
-EXPORT_SYMBOL_GPL(clk_divider_round_rate);
 
-static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate)
+static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long parent_rate)
 {
         struct clk_divider *divider = to_clk_divider(hw);
         unsigned int div;
         unsigned long flags = 0;
         u32 val;
 
-        div = __clk_get_rate(__clk_get_parent(hw->clk)) / rate;
+        div = parent_rate / rate;
 
         if (!(divider->flags & CLK_DIVIDER_ONE_BASED))
                 div--;
@@ -147,15 +140,26 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate)
 
         return 0;
 }
-EXPORT_SYMBOL_GPL(clk_divider_set_rate);
 
-struct clk_ops clk_divider_ops = {
+const struct clk_ops clk_divider_ops = {
         .recalc_rate = clk_divider_recalc_rate,
         .round_rate = clk_divider_round_rate,
         .set_rate = clk_divider_set_rate,
 };
 EXPORT_SYMBOL_GPL(clk_divider_ops);
 
+/**
+ * clk_register_divider - register a divider clock with the clock framework
+ * @dev: device registering this clock
+ * @name: name of this clock
+ * @parent_name: name of clock's parent
+ * @flags: framework-specific flags
+ * @reg: register address to adjust divider
+ * @shift: number of bits to shift the bitfield
+ * @width: width of the bitfield
+ * @clk_divider_flags: divider-specific flags for this clock
+ * @lock: shared register lock for this clock
+ */
 struct clk *clk_register_divider(struct device *dev, const char *name,
                 const char *parent_name, unsigned long flags,
                 void __iomem *reg, u8 shift, u8 width,
@@ -163,38 +167,34 @@ struct clk *clk_register_divider(struct device *dev, const char *name,
 {
         struct clk_divider *div;
         struct clk *clk;
+        struct clk_init_data init;
 
+        /* allocate the divider */
         div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL);
-
         if (!div) {
                 pr_err("%s: could not allocate divider clk\n", __func__);
-                return NULL;
+                return ERR_PTR(-ENOMEM);
         }
 
+        init.name = name;
+        init.ops = &clk_divider_ops;
+        init.flags = flags;
+        init.parent_names = (parent_name ? &parent_name: NULL);
+        init.num_parents = (parent_name ? 1 : 0);
+
         /* struct clk_divider assignments */
         div->reg = reg;
         div->shift = shift;
         div->width = width;
         div->flags = clk_divider_flags;
         div->lock = lock;
+        div->hw.init = &init;
 
-        if (parent_name) {
-                div->parent[0] = kstrdup(parent_name, GFP_KERNEL);
-                if (!div->parent[0])
-                        goto out;
-        }
-
-        clk = clk_register(dev, name,
-                        &clk_divider_ops, &div->hw,
-                        div->parent,
-                        (parent_name ? 1 : 0),
-                        flags);
-        if (clk)
-                return clk;
+        /* register the clock */
+        clk = clk_register(dev, &div->hw);
 
-out:
-        kfree(div->parent[0]);
-        kfree(div);
+        if (IS_ERR(clk))
+                kfree(div);
 
-        return NULL;
+        return clk;
 }
diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c
new file mode 100644
index 000000000000..c8c003e217ad
--- /dev/null
+++ b/drivers/clk/clk-fixed-factor.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Standard functionality for the common clock API.
+ */
+#include <linux/module.h>
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+
+/*
+ * DOC: basic fixed multiplier and divider clock that cannot gate
+ *
+ * Traits of this clock:
+ * prepare - clk_prepare only ensures that parents are prepared
+ * enable - clk_enable only ensures that parents are enabled
+ * rate - rate is fixed.  clk->rate = parent->rate / div * mult
+ * parent - fixed parent.  No clk_set_parent support
+ */
+
+#define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)
+
+static unsigned long clk_factor_recalc_rate(struct clk_hw *hw,
+                unsigned long parent_rate)
+{
+        struct clk_fixed_factor *fix = to_clk_fixed_factor(hw);
+
+        return parent_rate * fix->mult / fix->div;
+}
+
+static long clk_factor_round_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long *prate)
+{
+        struct clk_fixed_factor *fix = to_clk_fixed_factor(hw);
+
+        if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) {
+                unsigned long best_parent;
+
+                best_parent = (rate / fix->mult) * fix->div;
+                *prate = __clk_round_rate(__clk_get_parent(hw->clk),
+                                best_parent);
+        }
+
+        return (*prate / fix->div) * fix->mult;
+}
+
+static int clk_factor_set_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long parent_rate)
+{
+        return 0;
+}
+
+struct clk_ops clk_fixed_factor_ops = {
+        .round_rate = clk_factor_round_rate,
+        .set_rate = clk_factor_set_rate,
+        .recalc_rate = clk_factor_recalc_rate,
+};
+EXPORT_SYMBOL_GPL(clk_fixed_factor_ops);
+
+struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
+                const char *parent_name, unsigned long flags,
+                unsigned int mult, unsigned int div)
+{
+        struct clk_fixed_factor *fix;
+        struct clk_init_data init;
+        struct clk *clk;
+
+        fix = kmalloc(sizeof(*fix), GFP_KERNEL);
+        if (!fix) {
+                pr_err("%s: could not allocate fixed factor clk\n", __func__);
+                return ERR_PTR(-ENOMEM);
+        }
+
+        /* struct clk_fixed_factor assignments */
+        fix->mult = mult;
+        fix->div = div;
+        fix->hw.init = &init;
+
+        init.name = name;
+        init.ops = &clk_fixed_factor_ops;
+        init.flags = flags;
+        init.parent_names = &parent_name;
+        init.num_parents = 1;
+
+        clk = clk_register(dev, &fix->hw);
+
+        if (IS_ERR(clk))
+                kfree(fix);
+
+        return clk;
+}
diff --git a/drivers/clk/clk-fixed-rate.c b/drivers/clk/clk-fixed-rate.c
index 90c79fb5d1bd..cbd246229786 100644
--- a/drivers/clk/clk-fixed-rate.c
+++ b/drivers/clk/clk-fixed-rate.c
@@ -32,51 +32,50 @@ static unsigned long clk_fixed_rate_recalc_rate(struct clk_hw *hw,
 {
         return to_clk_fixed_rate(hw)->fixed_rate;
 }
-EXPORT_SYMBOL_GPL(clk_fixed_rate_recalc_rate);
 
-struct clk_ops clk_fixed_rate_ops = {
+const struct clk_ops clk_fixed_rate_ops = {
         .recalc_rate = clk_fixed_rate_recalc_rate,
 };
 EXPORT_SYMBOL_GPL(clk_fixed_rate_ops);
 
+/**
+ * clk_register_fixed_rate - register fixed-rate clock with the clock framework
+ * @dev: device that is registering this clock
+ * @name: name of this clock
+ * @parent_name: name of clock's parent
+ * @flags: framework-specific flags
+ * @fixed_rate: non-adjustable clock rate
+ */
 struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
                 const char *parent_name, unsigned long flags,
                 unsigned long fixed_rate)
 {
         struct clk_fixed_rate *fixed;
-        char **parent_names = NULL;
-        u8 len;
+        struct clk *clk;
+        struct clk_init_data init;
 
+        /* allocate fixed-rate clock */
         fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL);
-
         if (!fixed) {
                 pr_err("%s: could not allocate fixed clk\n", __func__);
                 return ERR_PTR(-ENOMEM);
         }
 
+        init.name = name;
+        init.ops = &clk_fixed_rate_ops;
+        init.flags = flags;
+        init.parent_names = (parent_name ? &parent_name: NULL);
+        init.num_parents = (parent_name ? 1 : 0);
+
         /* struct clk_fixed_rate assignments */
         fixed->fixed_rate = fixed_rate;
+        fixed->hw.init = &init;
 
-        if (parent_name) {
-                parent_names = kmalloc(sizeof(char *), GFP_KERNEL);
-
-                if (! parent_names)
-                        goto out;
+        /* register the clock */
+        clk = clk_register(dev, &fixed->hw);
 
-                len = sizeof(char) * strlen(parent_name);
-
-                parent_names[0] = kmalloc(len, GFP_KERNEL);
-
-                if (!parent_names[0])
-                        goto out;
-
-                strncpy(parent_names[0], parent_name, len);
-        }
+        if (IS_ERR(clk))
+                kfree(fixed);
 
-out:
-        return clk_register(dev, name,
-                        &clk_fixed_rate_ops, &fixed->hw,
-                        parent_names,
-                        (parent_name ? 1 : 0),
-                        flags);
+        return clk;
 }
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index b5902e2ef2fd..578465e04be6 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -28,32 +28,38 @@
 
 #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
 
-static void clk_gate_set_bit(struct clk_gate *gate)
+/*
+ * It works on following logic:
+ *
+ * For enabling clock, enable = 1
+ *      set2dis = 1     -> clear bit    -> set = 0
+ *      set2dis = 0     -> set bit      -> set = 1
+ *
+ * For disabling clock, enable = 0
+ *      set2dis = 1     -> set bit      -> set = 1
+ *      set2dis = 0     -> clear bit    -> set = 0
+ *
+ * So, result is always: enable xor set2dis.
+ */
+static void clk_gate_endisable(struct clk_hw *hw, int enable)
 {
-        u32 reg;
+        struct clk_gate *gate = to_clk_gate(hw);
+        int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
         unsigned long flags = 0;
+        u32 reg;
+
+        set ^= enable;
 
         if (gate->lock)
                 spin_lock_irqsave(gate->lock, flags);
 
         reg = readl(gate->reg);
-        reg |= BIT(gate->bit_idx);
-        writel(reg, gate->reg);
-
-        if (gate->lock)
-                spin_unlock_irqrestore(gate->lock, flags);
-}
-
-static void clk_gate_clear_bit(struct clk_gate *gate)
-{
-        u32 reg;
-        unsigned long flags = 0;
 
-        if (gate->lock)
-                spin_lock_irqsave(gate->lock, flags);
+        if (set)
+                reg |= BIT(gate->bit_idx);
+        else
+                reg &= ~BIT(gate->bit_idx);
 
-        reg = readl(gate->reg);
-        reg &= ~BIT(gate->bit_idx);
         writel(reg, gate->reg);
 
         if (gate->lock)
@@ -62,27 +68,15 @@ static void clk_gate_clear_bit(struct clk_gate *gate)
 
 static int clk_gate_enable(struct clk_hw *hw)
 {
-        struct clk_gate *gate = to_clk_gate(hw);
-
-        if (gate->flags & CLK_GATE_SET_TO_DISABLE)
-                clk_gate_clear_bit(gate);
-        else
-                clk_gate_set_bit(gate);
+        clk_gate_endisable(hw, 1);
 
         return 0;
 }
-EXPORT_SYMBOL_GPL(clk_gate_enable);
 
 static void clk_gate_disable(struct clk_hw *hw)
 {
-        struct clk_gate *gate = to_clk_gate(hw);
-
-        if (gate->flags & CLK_GATE_SET_TO_DISABLE)
-                clk_gate_set_bit(gate);
-        else
-                clk_gate_clear_bit(gate);
+        clk_gate_endisable(hw, 0);
 }
-EXPORT_SYMBOL_GPL(clk_gate_disable);
 
 static int clk_gate_is_enabled(struct clk_hw *hw)
 {
@@ -99,15 +93,25 @@ static int clk_gate_is_enabled(struct clk_hw *hw)
 
         return reg ? 1 : 0;
 }
-EXPORT_SYMBOL_GPL(clk_gate_is_enabled);
 
-struct clk_ops clk_gate_ops = {
+const struct clk_ops clk_gate_ops = {
         .enable = clk_gate_enable,
         .disable = clk_gate_disable,
         .is_enabled = clk_gate_is_enabled,
 };
 EXPORT_SYMBOL_GPL(clk_gate_ops);
 
+/**
+ * clk_register_gate - register a gate clock with the clock framework
+ * @dev: device that is registering this clock
+ * @name: name of this clock
+ * @parent_name: name of this clock's parent
+ * @flags: framework-specific flags for this clock
+ * @reg: register address to control gating of this clock
+ * @bit_idx: which bit in the register controls gating of this clock
+ * @clk_gate_flags: gate-specific flags for this clock
+ * @lock: shared register lock for this clock
+ */
 struct clk *clk_register_gate(struct device *dev, const char *name,
                 const char *parent_name, unsigned long flags,
                 void __iomem *reg, u8 bit_idx,
@@ -115,36 +119,32 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
 {
         struct clk_gate *gate;
         struct clk *clk;
+        struct clk_init_data init;
 
+        /* allocate the gate */
         gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
-
         if (!gate) {
                 pr_err("%s: could not allocate gated clk\n", __func__);
-                return NULL;
+                return ERR_PTR(-ENOMEM);
         }
 
+        init.name = name;
+        init.ops = &clk_gate_ops;
+        init.flags = flags;
+        init.parent_names = (parent_name ? &parent_name: NULL);
+        init.num_parents = (parent_name ? 1 : 0);
+
         /* struct clk_gate assignments */
         gate->reg = reg;
         gate->bit_idx = bit_idx;
         gate->flags = clk_gate_flags;
         gate->lock = lock;
+        gate->hw.init = &init;
 
-        if (parent_name) {
-                gate->parent[0] = kstrdup(parent_name, GFP_KERNEL);
-                if (!gate->parent[0])
-                        goto out;
-        }
+        clk = clk_register(dev, &gate->hw);
+
+        if (IS_ERR(clk))
+                kfree(gate);
 
-        clk = clk_register(dev, name,
-                        &clk_gate_ops, &gate->hw,
-                        gate->parent,
-                        (parent_name ? 1 : 0),
-                        flags);
-        if (clk)
-                return clk;
-out:
-        kfree(gate->parent[0]);
-        kfree(gate);
-
-        return NULL;
+        return clk;
 }
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index c71ad1f41a97..fd36a8ea73d9 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -55,7 +55,6 @@ static u8 clk_mux_get_parent(struct clk_hw *hw)
 
         return val;
 }
-EXPORT_SYMBOL_GPL(clk_mux_get_parent);
 
 static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
 {
@@ -82,35 +81,47 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
 
         return 0;
 }
-EXPORT_SYMBOL_GPL(clk_mux_set_parent);
 
-struct clk_ops clk_mux_ops = {
+const struct clk_ops clk_mux_ops = {
         .get_parent = clk_mux_get_parent,
         .set_parent = clk_mux_set_parent,
 };
 EXPORT_SYMBOL_GPL(clk_mux_ops);
 
 struct clk *clk_register_mux(struct device *dev, const char *name,
-                char **parent_names, u8 num_parents, unsigned long flags,
+                const char **parent_names, u8 num_parents, unsigned long flags,
                 void __iomem *reg, u8 shift, u8 width,
                 u8 clk_mux_flags, spinlock_t *lock)
 {
         struct clk_mux *mux;
+        struct clk *clk;
+        struct clk_init_data init;
 
-        mux = kmalloc(sizeof(struct clk_mux), GFP_KERNEL);
-
+        /* allocate the mux */
+        mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
         if (!mux) {
                 pr_err("%s: could not allocate mux clk\n", __func__);
                 return ERR_PTR(-ENOMEM);
         }
 
+        init.name = name;
+        init.ops = &clk_mux_ops;
+        init.flags = flags;
+        init.parent_names = parent_names;
+        init.num_parents = num_parents;
+
         /* struct clk_mux assignments */
         mux->reg = reg;
         mux->shift = shift;
         mux->width = width;
         mux->flags = clk_mux_flags;
         mux->lock = lock;
+        mux->hw.init = &init;
+
+        clk = clk_register(dev, &mux->hw);
+
+        if (IS_ERR(clk))
+                kfree(mux);
 
-        return clk_register(dev, name, &clk_mux_ops, &mux->hw,
-                        parent_names, num_parents, flags);
+        return clk;
 }
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 9cf6f59e3e19..e5d5dc13bcfd 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -194,9 +194,8 @@ static int __init clk_debug_init(void)
 late_initcall(clk_debug_init);
 #else
 static inline int clk_debug_register(struct clk *clk) { return 0; }
-#endif /* CONFIG_COMMON_CLK_DEBUG */
+#endif
 
-#ifdef CONFIG_COMMON_CLK_DISABLE_UNUSED
 /* caller must hold prepare_lock */
 static void clk_disable_unused_subtree(struct clk *clk)
 {
@@ -246,9 +245,6 @@ static int clk_disable_unused(void)
         return 0;
 }
 late_initcall(clk_disable_unused);
-#else
-static inline int clk_disable_unused(struct clk *clk) { return 0; }
-#endif /* CONFIG_COMMON_CLK_DISABLE_UNUSED */
 
 /***    helper functions   ***/
 
@@ -287,7 +283,7 @@ unsigned long __clk_get_rate(struct clk *clk)
         unsigned long ret;
 
         if (!clk) {
-                ret = -EINVAL;
+                ret = 0;
                 goto out;
         }
 
@@ -297,7 +293,7 @@ unsigned long __clk_get_rate(struct clk *clk)
                 goto out;
 
         if (!clk->parent)
-                ret = -ENODEV;
+                ret = 0;
 
 out:
         return ret;
@@ -562,7 +558,7 @@ EXPORT_SYMBOL_GPL(clk_enable);
  * @clk: the clk whose rate is being returned
  *
  * Simply returns the cached rate of the clk.  Does not query the hardware.  If
- * clk is NULL then returns -EINVAL.
+ * clk is NULL then returns 0.
  */
 unsigned long clk_get_rate(struct clk *clk)
 {
@@ -584,18 +580,22 @@ EXPORT_SYMBOL_GPL(clk_get_rate);
  */
 unsigned long __clk_round_rate(struct clk *clk, unsigned long rate)
 {
-        unsigned long unused;
+        unsigned long parent_rate = 0;
 
         if (!clk)
                 return -EINVAL;
 
-        if (!clk->ops->round_rate)
-                return clk->rate;
+        if (!clk->ops->round_rate) {
+                if (clk->flags & CLK_SET_RATE_PARENT)
+                        return __clk_round_rate(clk->parent, rate);
+                else
+                        return clk->rate;
+        }
 
-        if (clk->flags & CLK_SET_RATE_PARENT)
-                return clk->ops->round_rate(clk->hw, rate, &unused);
-        else
-                return clk->ops->round_rate(clk->hw, rate, NULL);
+        if (clk->parent)
+                parent_rate = clk->parent->rate;
+
+        return clk->ops->round_rate(clk->hw, rate, &parent_rate);
 }
 
 /**
@@ -765,25 +765,41 @@ static void clk_calc_subtree(struct clk *clk, unsigned long new_rate)
 static struct clk *clk_calc_new_rates(struct clk *clk, unsigned long rate)
 {
         struct clk *top = clk;
-        unsigned long best_parent_rate = clk->parent->rate;
+        unsigned long best_parent_rate = 0;
         unsigned long new_rate;
 
-        if (!clk->ops->round_rate && !(clk->flags & CLK_SET_RATE_PARENT)) {
-                clk->new_rate = clk->rate;
+        /* sanity */
+        if (IS_ERR_OR_NULL(clk))
                 return NULL;
+
+        /* save parent rate, if it exists */
+        if (clk->parent)
+                best_parent_rate = clk->parent->rate;
+
+        /* never propagate up to the parent */
+        if (!(clk->flags & CLK_SET_RATE_PARENT)) {
+                if (!clk->ops->round_rate) {
+                        clk->new_rate = clk->rate;
+                        return NULL;
+                }
+                new_rate = clk->ops->round_rate(clk->hw, rate, &best_parent_rate);
+                goto out;
         }
 
-        if (!clk->ops->round_rate && (clk->flags & CLK_SET_RATE_PARENT)) {
+        /* need clk->parent from here on out */
+        if (!clk->parent) {
+                pr_debug("%s: %s has NULL parent\n", __func__, clk->name);
+                return NULL;
+        }
+
+        if (!clk->ops->round_rate) {
                 top = clk_calc_new_rates(clk->parent, rate);
-                new_rate = clk->new_rate = clk->parent->new_rate;
+                new_rate = clk->parent->new_rate;
 
                 goto out;
         }
 
-        if (clk->flags & CLK_SET_RATE_PARENT)
-                new_rate = clk->ops->round_rate(clk->hw, rate, &best_parent_rate);
-        else
-                new_rate = clk->ops->round_rate(clk->hw, rate, NULL);
+        new_rate = clk->ops->round_rate(clk->hw, rate, &best_parent_rate);
 
         if (best_parent_rate != clk->parent->rate) {
                 top = clk_calc_new_rates(clk->parent, best_parent_rate);
@@ -839,7 +855,7 @@ static void clk_change_rate(struct clk *clk)
         old_rate = clk->rate;
 
         if (clk->ops->set_rate)
-                clk->ops->set_rate(clk->hw, clk->new_rate);
+                clk->ops->set_rate(clk->hw, clk->new_rate, clk->parent->rate);
 
         if (clk->ops->recalc_rate)
                 clk->rate = clk->ops->recalc_rate(clk->hw,
@@ -859,38 +875,19 @@ static void clk_change_rate(struct clk *clk)
  * @clk: the clk whose rate is being changed
  * @rate: the new rate for clk
  *
- * In the simplest case clk_set_rate will only change the rate of clk.
+ * In the simplest case clk_set_rate will only adjust the rate of clk.
  *
- * If clk has the CLK_SET_RATE_GATE flag set and it is enabled this call
- * will fail; only when the clk is disabled will it be able to change
- * its rate.
+ * Setting the CLK_SET_RATE_PARENT flag allows the rate change operation to
+ * propagate up to clk's parent; whether or not this happens depends on the
+ * outcome of clk's .round_rate implementation.  If *parent_rate is unchanged
+ * after calling .round_rate then upstream parent propagation is ignored.  If
+ * *parent_rate comes back with a new rate for clk's parent then we propagate
+ * up to clk's parent and set it's rate.  Upward propagation will continue
+ * until either a clk does not support the CLK_SET_RATE_PARENT flag or
+ * .round_rate stops requesting changes to clk's parent_rate.
  *
- * Setting the CLK_SET_RATE_PARENT flag allows clk_set_rate to
- * recursively propagate up to clk's parent; whether or not this happens
- * depends on the outcome of clk's .round_rate implementation.  If
- * *parent_rate is 0 after calling .round_rate then upstream parent
- * propagation is ignored.  If *parent_rate comes back with a new rate
- * for clk's parent then we propagate up to clk's parent and set it's
- * rate.  Upward propagation will continue until either a clk does not
- * support the CLK_SET_RATE_PARENT flag or .round_rate stops requesting
- * changes to clk's parent_rate.  If there is a failure during upstream
- * propagation then clk_set_rate will unwind and restore each clk's rate
- * that had been successfully changed.  Afterwards a rate change abort
- * notification will be propagated downstream, starting from the clk
- * that failed.
- *
- * At the end of all of the rate setting, clk_set_rate internally calls
- * __clk_recalc_rates and propagates the rate changes downstream,
- * starting from the highest clk whose rate was changed.  This has the
- * added benefit of propagating post-rate change notifiers.
- *
- * Note that while post-rate change and rate change abort notifications
- * are guaranteed to be sent to a clk only once per call to
- * clk_set_rate, pre-change notifications will be sent for every clk
- * whose rate is changed.  Stacking pre-change notifications is noisy
- * for the drivers subscribed to them, but this allows drivers to react
- * to intermediate clk rate changes up until the point where the final
- * rate is achieved at the end of upstream propagation.
+ * Rate changes are accomplished via tree traversal that also recalculates the
+ * rates for the clocks and fires off POST_RATE_CHANGE notifiers.
  *
  * Returns 0 on success, -EERROR otherwise.
  */
@@ -906,6 +903,11 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
         if (rate == clk->rate)
                 goto out;
 
+        if ((clk->flags & CLK_SET_RATE_GATE) && __clk_is_enabled(clk)) {
+                ret = -EBUSY;
+                goto out;
+        }
+
         /* calculate new rates and get the topmost changed clock */
         top = clk_calc_new_rates(clk, rate);
         if (!top) {
@@ -1175,40 +1177,41 @@ EXPORT_SYMBOL_GPL(clk_set_parent);
  *
  * Initializes the lists in struct clk, queries the hardware for the
  * parent and rate and sets them both.
- *
- * Any struct clk passed into __clk_init must have the following members
- * populated:
- *      .name
- *      .ops
- *      .hw
- *      .parent_names
- *      .num_parents
- *      .flags
- *
- * Essentially, everything that would normally be passed into clk_register is
- * assumed to be initialized already in __clk_init.  The other members may be
- * populated, but are optional.
- *
- * __clk_init is only exposed via clk-private.h and is intended for use with
- * very large numbers of clocks that need to be statically initialized.  It is
- * a layering violation to include clk-private.h from any code which implements
- * a clock's .ops; as such any statically initialized clock data MUST be in a
- * separate C file from the logic that implements it's operations.
  */
-void __clk_init(struct device *dev, struct clk *clk)
+int __clk_init(struct device *dev, struct clk *clk)
 {
-        int i;
+        int i, ret = 0;
         struct clk *orphan;
         struct hlist_node *tmp, *tmp2;
 
         if (!clk)
-                return;
+                return -EINVAL;
 
         mutex_lock(&prepare_lock);
 
         /* check to see if a clock with this name is already registered */
-        if (__clk_lookup(clk->name))
+        if (__clk_lookup(clk->name)) {
+                pr_debug("%s: clk %s already initialized\n",
+                                __func__, clk->name);
+                ret = -EEXIST;
+                goto out;
+        }
+
+        /* check that clk_ops are sane.  See Documentation/clk.txt */
+        if (clk->ops->set_rate &&
+                        !(clk->ops->round_rate && clk->ops->recalc_rate)) {
+                pr_warning("%s: %s must implement .round_rate & .recalc_rate\n",
+                                __func__, clk->name);
+                ret = -EINVAL;
                 goto out;
+        }
+
+        if (clk->ops->set_parent && !clk->ops->get_parent) {
+                pr_warning("%s: %s must implement .get_parent & .set_parent\n",
+                                __func__, clk->name);
+                ret = -EINVAL;
+                goto out;
+        }
 
         /* throw a WARN if any entries in parent_names are NULL */
         for (i = 0; i < clk->num_parents; i++)
@@ -1302,45 +1305,118 @@ void __clk_init(struct device *dev, struct clk *clk)
 out:
         mutex_unlock(&prepare_lock);
 
-        return;
+        return ret;
 }
 
 /**
+ * __clk_register - register a clock and return a cookie.
+ *
+ * Same as clk_register, except that the .clk field inside hw shall point to a
+ * preallocated (generally statically allocated) struct clk. None of the fields
+ * of the struct clk need to be initialized.
+ *
+ * The data pointed to by .init and .clk field shall NOT be marked as init
+ * data.
+ *
+ * __clk_register is only exposed via clk-private.h and is intended for use with
+ * very large numbers of clocks that need to be statically initialized.  It is
+ * a layering violation to include clk-private.h from any code which implements
+ * a clock's .ops; as such any statically initialized clock data MUST be in a
+ * separate C file from the logic that implements it's operations.  Returns 0
+ * on success, otherwise an error code.
+ */
+struct clk *__clk_register(struct device *dev, struct clk_hw *hw)
+{
+        int ret;
+        struct clk *clk;
+
+        clk = hw->clk;
+        clk->name = hw->init->name;
+        clk->ops = hw->init->ops;
+        clk->hw = hw;
+        clk->flags = hw->init->flags;
+        clk->parent_names = hw->init->parent_names;
+        clk->num_parents = hw->init->num_parents;
+
+        ret = __clk_init(dev, clk);
+        if (ret)
+                return ERR_PTR(ret);
+
+        return clk;
+}
+EXPORT_SYMBOL_GPL(__clk_register);
+
+/**
  * clk_register - allocate a new clock, register it and return an opaque cookie
  * @dev: device that is registering this clock
- * @name: clock name
- * @ops: operations this clock supports
  * @hw: link to hardware-specific clock data
- * @parent_names: array of string names for all possible parents
- * @num_parents: number of possible parents
- * @flags: framework-level hints and quirks
  *
  * clk_register is the primary interface for populating the clock tree with new
  * clock nodes.  It returns a pointer to the newly allocated struct clk which
  * cannot be dereferenced by driver code but may be used in conjuction with the
- * rest of the clock API.
+ * rest of the clock API.  In the event of an error clk_register will return an
+ * error code; drivers must test for an error code after calling clk_register.
  */
-struct clk *clk_register(struct device *dev, const char *name,
-                const struct clk_ops *ops, struct clk_hw *hw,
-                char **parent_names, u8 num_parents, unsigned long flags)
+struct clk *clk_register(struct device *dev, struct clk_hw *hw)
 {
+        int i, ret;
         struct clk *clk;
 
         clk = kzalloc(sizeof(*clk), GFP_KERNEL);
-        if (!clk)
-                return NULL;
+        if (!clk) {
+                pr_err("%s: could not allocate clk\n", __func__);
+                ret = -ENOMEM;
+                goto fail_out;
+        }
 
-        clk->name = name;
-        clk->ops = ops;
+        clk->name = kstrdup(hw->init->name, GFP_KERNEL);
+        if (!clk->name) {
+                pr_err("%s: could not allocate clk->name\n", __func__);
+                ret = -ENOMEM;
+                goto fail_name;
+        }
+        clk->ops = hw->init->ops;
         clk->hw = hw;
-        clk->flags = flags;
-        clk->parent_names = parent_names;
-        clk->num_parents = num_parents;
+        clk->flags = hw->init->flags;
+        clk->num_parents = hw->init->num_parents;
         hw->clk = clk;
 
-        __clk_init(dev, clk);
+        /* allocate local copy in case parent_names is __initdata */
+        clk->parent_names = kzalloc((sizeof(char*) * clk->num_parents),
+                        GFP_KERNEL);
 
-        return clk;
+        if (!clk->parent_names) {
+                pr_err("%s: could not allocate clk->parent_names\n", __func__);
+                ret = -ENOMEM;
+                goto fail_parent_names;
+        }
+
+
+        /* copy each string name in case parent_names is __initdata */
+        for (i = 0; i < clk->num_parents; i++) {
+                clk->parent_names[i] = kstrdup(hw->init->parent_names[i],
+                                                GFP_KERNEL);
+                if (!clk->parent_names[i]) {
+                        pr_err("%s: could not copy parent_names\n", __func__);
+                        ret = -ENOMEM;
+                        goto fail_parent_names_copy;
+                }
+        }
+
+        ret = __clk_init(dev, clk);
+        if (!ret)
+                return clk;
+
+fail_parent_names_copy:
+        while (--i >= 0)
+                kfree(clk->parent_names[i]);
+        kfree(clk->parent_names);
+fail_parent_names:
+        kfree(clk->name);
+fail_name:
+        kfree(clk);
+fail_out:
+        return ERR_PTR(ret);
 }
 EXPORT_SYMBOL_GPL(clk_register);
 
diff --git a/drivers/clk/clkdev.c b/drivers/clk/clkdev.c
index 6db161f64ae0..c535cf8c5770 100644
--- a/drivers/clk/clkdev.c
+++ b/drivers/clk/clkdev.c
@@ -35,7 +35,12 @@ static DEFINE_MUTEX(clocks_mutex);
 static struct clk_lookup *clk_find(const char *dev_id, const char *con_id)
 {
         struct clk_lookup *p, *cl = NULL;
-        int match, best = 0;
+        int match, best_found = 0, best_possible = 0;
+
+        if (dev_id)
+                best_possible += 2;
+        if (con_id)
+                best_possible += 1;
 
         list_for_each_entry(p, &clocks, node) {
                 match = 0;
@@ -50,10 +55,10 @@ static struct clk_lookup *clk_find(const char *dev_id, const char *con_id)
                         match += 1;
                 }
 
-                if (match > best) {
+                if (match > best_found) {
                         cl = p;
-                        if (match != 3)
-                                best = match;
+                        if (match != best_possible)
+                                best_found = match;
                         else
                                 break;
                 }
@@ -89,6 +94,51 @@ void clk_put(struct clk *clk)
 }
 EXPORT_SYMBOL(clk_put);
 
+static void devm_clk_release(struct device *dev, void *res)
+{
+        clk_put(*(struct clk **)res);
+}
+
+struct clk *devm_clk_get(struct device *dev, const char *id)
+{
+        struct clk **ptr, *clk;
+
+        ptr = devres_alloc(devm_clk_release, sizeof(*ptr), GFP_KERNEL);
+        if (!ptr)
+                return ERR_PTR(-ENOMEM);
+
+        clk = clk_get(dev, id);
+        if (!IS_ERR(clk)) {
+                *ptr = clk;
+                devres_add(dev, ptr);
+        } else {
+                devres_free(ptr);
+        }
+
+        return clk;
+}
+EXPORT_SYMBOL(devm_clk_get);
+
+static int devm_clk_match(struct device *dev, void *res, void *data)
+{
+        struct clk **c = res;
+        if (!c || !*c) {
+                WARN_ON(!c || !*c);
+                return 0;
+        }
+        return *c == data;
+}
+
+void devm_clk_put(struct device *dev, struct clk *clk)
+{
+        int ret;
+
+        ret = devres_destroy(dev, devm_clk_release, devm_clk_match, clk);
+
+        WARN_ON(ret);
+}
+EXPORT_SYMBOL(devm_clk_put);
+
 void clkdev_add(struct clk_lookup *cl)
 {
         mutex_lock(&clocks_mutex);
@@ -116,8 +166,9 @@ struct clk_lookup_alloc {
         char    con_id[MAX_CON_ID];
 };
 
-struct clk_lookup * __init_refok
-clkdev_alloc(struct clk *clk, const char *con_id, const char *dev_fmt, ...)
+static struct clk_lookup * __init_refok
+vclkdev_alloc(struct clk *clk, const char *con_id, const char *dev_fmt,
+        va_list ap)
 {
         struct clk_lookup_alloc *cla;
 
@@ -132,16 +183,25 @@ clkdev_alloc(struct clk *clk, const char *con_id, const char *dev_fmt, ...)
         }
 
         if (dev_fmt) {
-                va_list ap;
-
-                va_start(ap, dev_fmt);
                 vscnprintf(cla->dev_id, sizeof(cla->dev_id), dev_fmt, ap);
                 cla->cl.dev_id = cla->dev_id;
-                va_end(ap);
         }
 
         return &cla->cl;
 }
+
+struct clk_lookup * __init_refok
+clkdev_alloc(struct clk *clk, const char *con_id, const char *dev_fmt, ...)
+{
+        struct clk_lookup *cl;
+        va_list ap;
+
+        va_start(ap, dev_fmt);
+        cl = vclkdev_alloc(clk, con_id, dev_fmt, ap);
+        va_end(ap);
+
+        return cl;
+}
 EXPORT_SYMBOL(clkdev_alloc);
 
 int clk_add_alias(const char *alias, const char *alias_dev_name, char *id,
@@ -173,3 +233,65 @@ void clkdev_drop(struct clk_lookup *cl)
         kfree(cl);
 }
 EXPORT_SYMBOL(clkdev_drop);
+
+/**
+ * clk_register_clkdev - register one clock lookup for a struct clk
+ * @clk: struct clk to associate with all clk_lookups
+ * @con_id: connection ID string on device
+ * @dev_id: format string describing device name
+ *
+ * con_id or dev_id may be NULL as a wildcard, just as in the rest of
+ * clkdev.
+ *
+ * To make things easier for mass registration, we detect error clks
+ * from a previous clk_register() call, and return the error code for
+ * those.  This is to permit this function to be called immediately
+ * after clk_register().
+ */
+int clk_register_clkdev(struct clk *clk, const char *con_id,
+        const char *dev_fmt, ...)
+{
+        struct clk_lookup *cl;
+        va_list ap;
+
+        if (IS_ERR(clk))
+                return PTR_ERR(clk);
+
+        va_start(ap, dev_fmt);
+        cl = vclkdev_alloc(clk, con_id, dev_fmt, ap);
+        va_end(ap);
+
+        if (!cl)
+                return -ENOMEM;
+
+        clkdev_add(cl);
+
+        return 0;
+}
+
+/**
+ * clk_register_clkdevs - register a set of clk_lookup for a struct clk
+ * @clk: struct clk to associate with all clk_lookups
+ * @cl: array of clk_lookup structures with con_id and dev_id pre-initialized
+ * @num: number of clk_lookup structures to register
+ *
+ * To make things easier for mass registration, we detect error clks
+ * from a previous clk_register() call, and return the error code for
+ * those.  This is to permit this function to be called immediately
+ * after clk_register().
+ */
+int clk_register_clkdevs(struct clk *clk, struct clk_lookup *cl, size_t num)
+{
+        unsigned i;
+
+        if (IS_ERR(clk))
+                return PTR_ERR(clk);
+
+        for (i = 0; i < num; i++, cl++) {
+                cl->clk = clk;
+                clkdev_add(cl);
+        }
+
+        return 0;
+}
+EXPORT_SYMBOL(clk_register_clkdevs);
diff --git a/drivers/clk/spear/Makefile b/drivers/clk/spear/Makefile
new file mode 100644
index 000000000000..cdb425d3b8ee
--- /dev/null
+++ b/drivers/clk/spear/Makefile
@@ -0,0 +1,10 @@
+#
+# SPEAr Clock specific Makefile
+#
+
+obj-y   += clk.o clk-aux-synth.o clk-frac-synth.o clk-gpt-synth.o clk-vco-pll.o
+
+obj-$(CONFIG_ARCH_SPEAR3XX)     += spear3xx_clock.o
+obj-$(CONFIG_ARCH_SPEAR6XX)     += spear6xx_clock.o
+obj-$(CONFIG_MACH_SPEAR1310)    += spear1310_clock.o
+obj-$(CONFIG_MACH_SPEAR1340)    += spear1340_clock.o
diff --git a/drivers/clk/spear/clk-aux-synth.c b/drivers/clk/spear/clk-aux-synth.c
new file mode 100644
index 000000000000..af34074e702b
--- /dev/null
+++ b/drivers/clk/spear/clk-aux-synth.c
@@ -0,0 +1,198 @@
+/*
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Auxiliary Synthesizer clock implementation
+ */
+
+#define pr_fmt(fmt) "clk-aux-synth: " fmt
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include "clk.h"
+
+/*
+ * DOC: Auxiliary Synthesizer clock
+ *
+ * Aux synth gives rate for different values of eq, x and y
+ *
+ * Fout from synthesizer can be given from two equations:
+ * Fout1 = (Fin * X/Y)/2                EQ1
+ * Fout2 = Fin * X/Y                    EQ2
+ */
+
+#define to_clk_aux(_hw) container_of(_hw, struct clk_aux, hw)
+
+static struct aux_clk_masks default_aux_masks = {
+        .eq_sel_mask = AUX_EQ_SEL_MASK,
+        .eq_sel_shift = AUX_EQ_SEL_SHIFT,
+        .eq1_mask = AUX_EQ1_SEL,
+        .eq2_mask = AUX_EQ2_SEL,
+        .xscale_sel_mask = AUX_XSCALE_MASK,
+        .xscale_sel_shift = AUX_XSCALE_SHIFT,
+        .yscale_sel_mask = AUX_YSCALE_MASK,
+        .yscale_sel_shift = AUX_YSCALE_SHIFT,
+        .enable_bit = AUX_SYNT_ENB,
+};
+
+static unsigned long aux_calc_rate(struct clk_hw *hw, unsigned long prate,
+                int index)
+{
+        struct clk_aux *aux = to_clk_aux(hw);
+        struct aux_rate_tbl *rtbl = aux->rtbl;
+        u8 eq = rtbl[index].eq ? 1 : 2;
+
+        return (((prate / 10000) * rtbl[index].xscale) /
+                        (rtbl[index].yscale * eq)) * 10000;
+}
+
+static long clk_aux_round_rate(struct clk_hw *hw, unsigned long drate,
+                unsigned long *prate)
+{
+        struct clk_aux *aux = to_clk_aux(hw);
+        int unused;
+
+        return clk_round_rate_index(hw, drate, *prate, aux_calc_rate,
+                        aux->rtbl_cnt, &unused);
+}
+
+static unsigned long clk_aux_recalc_rate(struct clk_hw *hw,
+                unsigned long parent_rate)
+{
+        struct clk_aux *aux = to_clk_aux(hw);
+        unsigned int num = 1, den = 1, val, eqn;
+        unsigned long flags = 0;
+
+        if (aux->lock)
+                spin_lock_irqsave(aux->lock, flags);
+
+        val = readl_relaxed(aux->reg);
+
+        if (aux->lock)
+                spin_unlock_irqrestore(aux->lock, flags);
+
+        eqn = (val >> aux->masks->eq_sel_shift) & aux->masks->eq_sel_mask;
+        if (eqn == aux->masks->eq1_mask)
+                den = 2;
+
+        /* calculate numerator */
+        num = (val >> aux->masks->xscale_sel_shift) &
+                aux->masks->xscale_sel_mask;
+
+        /* calculate denominator */
+        den *= (val >> aux->masks->yscale_sel_shift) &
+                aux->masks->yscale_sel_mask;
+
+        if (!den)
+                return 0;
+
+        return (((parent_rate / 10000) * num) / den) * 10000;
+}
+
+/* Configures new clock rate of aux */
+static int clk_aux_set_rate(struct clk_hw *hw, unsigned long drate,
+                                unsigned long prate)
+{
+        struct clk_aux *aux = to_clk_aux(hw);
+        struct aux_rate_tbl *rtbl = aux->rtbl;
+        unsigned long val, flags = 0;
+        int i;
+
+        clk_round_rate_index(hw, drate, prate, aux_calc_rate, aux->rtbl_cnt,
+                        &i);
+
+        if (aux->lock)
+                spin_lock_irqsave(aux->lock, flags);
+
+        val = readl_relaxed(aux->reg) &
+                ~(aux->masks->eq_sel_mask << aux->masks->eq_sel_shift);
+        val |= (rtbl[i].eq & aux->masks->eq_sel_mask) <<
+                aux->masks->eq_sel_shift;
+        val &= ~(aux->masks->xscale_sel_mask << aux->masks->xscale_sel_shift);
+        val |= (rtbl[i].xscale & aux->masks->xscale_sel_mask) <<
+                aux->masks->xscale_sel_shift;
+        val &= ~(aux->masks->yscale_sel_mask << aux->masks->yscale_sel_shift);
+        val |= (rtbl[i].yscale & aux->masks->yscale_sel_mask) <<
+                aux->masks->yscale_sel_shift;
+        writel_relaxed(val, aux->reg);
+
+        if (aux->lock)
+                spin_unlock_irqrestore(aux->lock, flags);
+
+        return 0;
+}
+
+static struct clk_ops clk_aux_ops = {
+        .recalc_rate = clk_aux_recalc_rate,
+        .round_rate = clk_aux_round_rate,
+        .set_rate = clk_aux_set_rate,
+};
+
+struct clk *clk_register_aux(const char *aux_name, const char *gate_name,
+                const char *parent_name, unsigned long flags, void __iomem *reg,
+                struct aux_clk_masks *masks, struct aux_rate_tbl *rtbl,
+                u8 rtbl_cnt, spinlock_t *lock, struct clk **gate_clk)
+{
+        struct clk_aux *aux;
+        struct clk_init_data init;
+        struct clk *clk;
+
+        if (!aux_name || !parent_name || !reg || !rtbl || !rtbl_cnt) {
+                pr_err("Invalid arguments passed");
+                return ERR_PTR(-EINVAL);
+        }
+
+        aux = kzalloc(sizeof(*aux), GFP_KERNEL);
+        if (!aux) {
+                pr_err("could not allocate aux clk\n");
+                return ERR_PTR(-ENOMEM);
+        }
+
+        /* struct clk_aux assignments */
+        if (!masks)
+                aux->masks = &default_aux_masks;
+        else
+                aux->masks = masks;
+
+        aux->reg = reg;
+        aux->rtbl = rtbl;
+        aux->rtbl_cnt = rtbl_cnt;
+        aux->lock = lock;
+        aux->hw.init = &init;
+
+        init.name = aux_name;
+        init.ops = &clk_aux_ops;
+        init.flags = flags;
+        init.parent_names = &parent_name;
+        init.num_parents = 1;
+
+        clk = clk_register(NULL, &aux->hw);
+        if (IS_ERR_OR_NULL(clk))
+                goto free_aux;
+
+        if (gate_name) {
+                struct clk *tgate_clk;
+
+                tgate_clk = clk_register_gate(NULL, gate_name, aux_name, 0, reg,
+                                aux->masks->enable_bit, 0, lock);
+                if (IS_ERR_OR_NULL(tgate_clk))
+                        goto free_aux;
+
+                if (gate_clk)
+                        *gate_clk = tgate_clk;
+        }
+
+        return clk;
+
+free_aux:
+        kfree(aux);
+        pr_err("clk register failed\n");
+
+        return NULL;
+}
diff --git a/drivers/clk/spear/clk-frac-synth.c b/drivers/clk/spear/clk-frac-synth.c
new file mode 100644
index 000000000000..4dbdb3fe18e0
--- /dev/null
+++ b/drivers/clk/spear/clk-frac-synth.c
@@ -0,0 +1,165 @@
+/*
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Fractional Synthesizer clock implementation
+ */
+
+#define pr_fmt(fmt) "clk-frac-synth: " fmt
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include "clk.h"
+
+#define DIV_FACTOR_MASK         0x1FFFF
+
+/*
+ * DOC: Fractional Synthesizer clock
+ *
+ * Fout from synthesizer can be given from below equation:
+ *
+ * Fout= Fin/2*div (division factor)
+ * div is 17 bits:-
+ *      0-13 (fractional part)
+ *      14-16 (integer part)
+ *      div is (16-14 bits).(13-0 bits) (in binary)
+ *
+ *      Fout = Fin/(2 * div)
+ *      Fout = ((Fin / 10000)/(2 * div)) * 10000
+ *      Fout = (2^14 * (Fin / 10000)/(2^14 * (2 * div))) * 10000
+ *      Fout = (((Fin / 10000) << 14)/(2 * (div << 14))) * 10000
+ *
+ * div << 14 simply 17 bit value written at register.
+ * Max error due to scaling down by 10000 is 10 KHz
+ */
+
+#define to_clk_frac(_hw) container_of(_hw, struct clk_frac, hw)
+
+static unsigned long frac_calc_rate(struct clk_hw *hw, unsigned long prate,
+                int index)
+{
+        struct clk_frac *frac = to_clk_frac(hw);
+        struct frac_rate_tbl *rtbl = frac->rtbl;
+
+        prate /= 10000;
+        prate <<= 14;
+        prate /= (2 * rtbl[index].div);
+        prate *= 10000;
+
+        return prate;
+}
+
+static long clk_frac_round_rate(struct clk_hw *hw, unsigned long drate,
+                unsigned long *prate)
+{
+        struct clk_frac *frac = to_clk_frac(hw);
+        int unused;
+
+        return clk_round_rate_index(hw, drate, *prate, frac_calc_rate,
+                        frac->rtbl_cnt, &unused);
+}
+
+static unsigned long clk_frac_recalc_rate(struct clk_hw *hw,
+                unsigned long parent_rate)
+{
+        struct clk_frac *frac = to_clk_frac(hw);
+        unsigned long flags = 0;
+        unsigned int div = 1, val;
+
+        if (frac->lock)
+                spin_lock_irqsave(frac->lock, flags);
+
+        val = readl_relaxed(frac->reg);
+
+        if (frac->lock)
+                spin_unlock_irqrestore(frac->lock, flags);
+
+        div = val & DIV_FACTOR_MASK;
+
+        if (!div)
+                return 0;
+
+        parent_rate = parent_rate / 10000;
+
+        parent_rate = (parent_rate << 14) / (2 * div);
+        return parent_rate * 10000;
+}
+
+/* Configures new clock rate of frac */
+static int clk_frac_set_rate(struct clk_hw *hw, unsigned long drate,
+                                unsigned long prate)
+{
+        struct clk_frac *frac = to_clk_frac(hw);
+        struct frac_rate_tbl *rtbl = frac->rtbl;
+        unsigned long flags = 0, val;
+        int i;
+
+        clk_round_rate_index(hw, drate, prate, frac_calc_rate, frac->rtbl_cnt,
+                        &i);
+
+        if (frac->lock)
+                spin_lock_irqsave(frac->lock, flags);
+
+        val = readl_relaxed(frac->reg) & ~DIV_FACTOR_MASK;
+        val |= rtbl[i].div & DIV_FACTOR_MASK;
+        writel_relaxed(val, frac->reg);
+
+        if (frac->lock)
+                spin_unlock_irqrestore(frac->lock, flags);
+
+        return 0;
+}
+
+struct clk_ops clk_frac_ops = {
+        .recalc_rate = clk_frac_recalc_rate,
+        .round_rate = clk_frac_round_rate,
+        .set_rate = clk_frac_set_rate,
+};
+
+struct clk *clk_register_frac(const char *name, const char *parent_name,
+                unsigned long flags, void __iomem *reg,
+                struct frac_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock)
+{
+        struct clk_init_data init;
+        struct clk_frac *frac;
+        struct clk *clk;
+
+        if (!name || !parent_name || !reg || !rtbl || !rtbl_cnt) {
+                pr_err("Invalid arguments passed");
+                return ERR_PTR(-EINVAL);
+        }
+
+        frac = kzalloc(sizeof(*frac), GFP_KERNEL);
+        if (!frac) {
+                pr_err("could not allocate frac clk\n");
+                return ERR_PTR(-ENOMEM);
+        }
+
+        /* struct clk_frac assignments */
+        frac->reg = reg;
+        frac->rtbl = rtbl;
+        frac->rtbl_cnt = rtbl_cnt;
+        frac->lock = lock;
+        frac->hw.init = &init;
+
+        init.name = name;
+        init.ops = &clk_frac_ops;
+        init.flags = flags;
+        init.parent_names = &parent_name;
+        init.num_parents = 1;
+
+        clk = clk_register(NULL, &frac->hw);
+        if (!IS_ERR_OR_NULL(clk))
+                return clk;
+
+        pr_err("clk register failed\n");
+        kfree(frac);
+
+        return NULL;
+}
diff --git a/drivers/clk/spear/clk-gpt-synth.c b/drivers/clk/spear/clk-gpt-synth.c
new file mode 100644
index 000000000000..b471c9762a97
--- /dev/null
+++ b/drivers/clk/spear/clk-gpt-synth.c
@@ -0,0 +1,154 @@
+/*
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * General Purpose Timer Synthesizer clock implementation
+ */
+
+#define pr_fmt(fmt) "clk-gpt-synth: " fmt
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include "clk.h"
+
+#define GPT_MSCALE_MASK         0xFFF
+#define GPT_NSCALE_SHIFT        12
+#define GPT_NSCALE_MASK         0xF
+
+/*
+ * DOC: General Purpose Timer Synthesizer clock
+ *
+ * Calculates gpt synth clk rate for different values of mscale and nscale
+ *
+ * Fout= Fin/((2 ^ (N+1)) * (M+1))
+ */
+
+#define to_clk_gpt(_hw) container_of(_hw, struct clk_gpt, hw)
+
+static unsigned long gpt_calc_rate(struct clk_hw *hw, unsigned long prate,
+                int index)
+{
+        struct clk_gpt *gpt = to_clk_gpt(hw);
+        struct gpt_rate_tbl *rtbl = gpt->rtbl;
+
+        prate /= ((1 << (rtbl[index].nscale + 1)) * (rtbl[index].mscale + 1));
+
+        return prate;
+}
+
+static long clk_gpt_round_rate(struct clk_hw *hw, unsigned long drate,
+                unsigned long *prate)
+{
+        struct clk_gpt *gpt = to_clk_gpt(hw);
+        int unused;
+
+        return clk_round_rate_index(hw, drate, *prate, gpt_calc_rate,
+                        gpt->rtbl_cnt, &unused);
+}
+
+static unsigned long clk_gpt_recalc_rate(struct clk_hw *hw,
+                unsigned long parent_rate)
+{
+        struct clk_gpt *gpt = to_clk_gpt(hw);
+        unsigned long flags = 0;
+        unsigned int div = 1, val;
+
+        if (gpt->lock)
+                spin_lock_irqsave(gpt->lock, flags);
+
+        val = readl_relaxed(gpt->reg);
+
+        if (gpt->lock)
+                spin_unlock_irqrestore(gpt->lock, flags);
+
+        div += val & GPT_MSCALE_MASK;
+        div *= 1 << (((val >> GPT_NSCALE_SHIFT) & GPT_NSCALE_MASK) + 1);
+
+        if (!div)
+                return 0;
+
+        return parent_rate / div;
+}
+
+/* Configures new clock rate of gpt */
+static int clk_gpt_set_rate(struct clk_hw *hw, unsigned long drate,
+                                unsigned long prate)
+{
+        struct clk_gpt *gpt = to_clk_gpt(hw);
+        struct gpt_rate_tbl *rtbl = gpt->rtbl;
+        unsigned long flags = 0, val;
+        int i;
+
+        clk_round_rate_index(hw, drate, prate, gpt_calc_rate, gpt->rtbl_cnt,
+                        &i);
+
+        if (gpt->lock)
+                spin_lock_irqsave(gpt->lock, flags);
+
+        val = readl(gpt->reg) & ~GPT_MSCALE_MASK;
+        val &= ~(GPT_NSCALE_MASK << GPT_NSCALE_SHIFT);
+
+        val |= rtbl[i].mscale & GPT_MSCALE_MASK;
+        val |= (rtbl[i].nscale & GPT_NSCALE_MASK) << GPT_NSCALE_SHIFT;
+
+        writel_relaxed(val, gpt->reg);
+
+        if (gpt->lock)
+                spin_unlock_irqrestore(gpt->lock, flags);
+
+        return 0;
+}
+
+static struct clk_ops clk_gpt_ops = {
+        .recalc_rate = clk_gpt_recalc_rate,
+        .round_rate = clk_gpt_round_rate,
+        .set_rate = clk_gpt_set_rate,
+};
+
+struct clk *clk_register_gpt(const char *name, const char *parent_name, unsigned
+                long flags, void __iomem *reg, struct gpt_rate_tbl *rtbl, u8
+                rtbl_cnt, spinlock_t *lock)
+{
+        struct clk_init_data init;
+        struct clk_gpt *gpt;
+        struct clk *clk;
+
+        if (!name || !parent_name || !reg || !rtbl || !rtbl_cnt) {
+                pr_err("Invalid arguments passed");
+                return ERR_PTR(-EINVAL);
+        }
+
+        gpt = kzalloc(sizeof(*gpt), GFP_KERNEL);
+        if (!gpt) {
+                pr_err("could not allocate gpt clk\n");
+                return ERR_PTR(-ENOMEM);
+        }
+
+        /* struct clk_gpt assignments */
+        gpt->reg = reg;
+        gpt->rtbl = rtbl;
+        gpt->rtbl_cnt = rtbl_cnt;
+        gpt->lock = lock;
+        gpt->hw.init = &init;
+
+        init.name = name;
+        init.ops = &clk_gpt_ops;
+        init.flags = flags;
+        init.parent_names = &parent_name;
+        init.num_parents = 1;
+
+        clk = clk_register(NULL, &gpt->hw);
+        if (!IS_ERR_OR_NULL(clk))
+                return clk;
+
+        pr_err("clk register failed\n");
+        kfree(gpt);
+
+        return NULL;
+}
diff --git a/drivers/clk/spear/clk-vco-pll.c b/drivers/clk/spear/clk-vco-pll.c
new file mode 100644
index 000000000000..dcd4bdf4b0d9
--- /dev/null
+++ b/drivers/clk/spear/clk-vco-pll.c
@@ -0,0 +1,363 @@
+/*
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * VCO-PLL clock implementation
+ */
+
+#define pr_fmt(fmt) "clk-vco-pll: " fmt
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include "clk.h"
+
+/*
+ * DOC: VCO-PLL clock
+ *
+ * VCO and PLL rate are derived from following equations:
+ *
+ * In normal mode
+ * vco = (2 * M[15:8] * Fin)/N
+ *
+ * In Dithered mode
+ * vco = (2 * M[15:0] * Fin)/(256 * N)
+ *
+ * pll_rate = pll/2^p
+ *
+ * vco and pll are very closely bound to each other, "vco needs to program:
+ * mode, m & n" and "pll needs to program p", both share common enable/disable
+ * logic.
+ *
+ * clk_register_vco_pll() registers instances of both vco & pll.
+ * CLK_SET_RATE_PARENT flag is forced for pll, as it will always pass its
+ * set_rate to vco. A single rate table exists for both the clocks, which
+ * configures m, n and p.
+ */
+
+/* PLL_CTR register masks */
+#define PLL_MODE_NORMAL         0
+#define PLL_MODE_FRACTION       1
+#define PLL_MODE_DITH_DSM       2
+#define PLL_MODE_DITH_SSM       3
+#define PLL_MODE_MASK           3
+#define PLL_MODE_SHIFT          3
+#define PLL_ENABLE              2
+
+#define PLL_LOCK_SHIFT          0
+#define PLL_LOCK_MASK           1
+
+/* PLL FRQ register masks */
+#define PLL_NORM_FDBK_M_MASK    0xFF
+#define PLL_NORM_FDBK_M_SHIFT   24
+#define PLL_DITH_FDBK_M_MASK    0xFFFF
+#define PLL_DITH_FDBK_M_SHIFT   16
+#define PLL_DIV_P_MASK          0x7
+#define PLL_DIV_P_SHIFT         8
+#define PLL_DIV_N_MASK          0xFF
+#define PLL_DIV_N_SHIFT         0
+
+#define to_clk_vco(_hw) container_of(_hw, struct clk_vco, hw)
+#define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
+
+/* Calculates pll clk rate for specific value of mode, m, n and p */
+static unsigned long pll_calc_rate(struct pll_rate_tbl *rtbl,
+                unsigned long prate, int index, unsigned long *pll_rate)
+{
+        unsigned long rate = prate;
+        unsigned int mode;
+
+        mode = rtbl[index].mode ? 256 : 1;
+        rate = (((2 * rate / 10000) * rtbl[index].m) / (mode * rtbl[index].n));
+
+        if (pll_rate)
+                *pll_rate = (rate / (1 << rtbl[index].p)) * 10000;
+
+        return rate * 10000;
+}
+
+static long clk_pll_round_rate_index(struct clk_hw *hw, unsigned long drate,
+                                unsigned long *prate, int *index)
+{
+        struct clk_pll *pll = to_clk_pll(hw);
+        unsigned long prev_rate, vco_prev_rate, rate = 0;
+        unsigned long vco_parent_rate =
+                __clk_get_rate(__clk_get_parent(__clk_get_parent(hw->clk)));
+
+        if (!prate) {
+                pr_err("%s: prate is must for pll clk\n", __func__);
+                return -EINVAL;
+        }
+
+        for (*index = 0; *index < pll->vco->rtbl_cnt; (*index)++) {
+                prev_rate = rate;
+                vco_prev_rate = *prate;
+                *prate = pll_calc_rate(pll->vco->rtbl, vco_parent_rate, *index,
+                                &rate);
+                if (drate < rate) {
+                        /* previous clock was best */
+                        if (*index) {
+                                rate = prev_rate;
+                                *prate = vco_prev_rate;
+                                (*index)--;
+                        }
+                        break;
+                }
+        }
+
+        return rate;
+}
+
+static long clk_pll_round_rate(struct clk_hw *hw, unsigned long drate,
+                                unsigned long *prate)
+{
+        int unused;
+
+        return clk_pll_round_rate_index(hw, drate, prate, &unused);
+}
+
+static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, unsigned long
+                parent_rate)
+{
+        struct clk_pll *pll = to_clk_pll(hw);
+        unsigned long flags = 0;
+        unsigned int p;
+
+        if (pll->vco->lock)
+                spin_lock_irqsave(pll->vco->lock, flags);
+
+        p = readl_relaxed(pll->vco->cfg_reg);
+
+        if (pll->vco->lock)
+                spin_unlock_irqrestore(pll->vco->lock, flags);
+
+        p = (p >> PLL_DIV_P_SHIFT) & PLL_DIV_P_MASK;
+
+        return parent_rate / (1 << p);
+}
+
+static int clk_pll_set_rate(struct clk_hw *hw, unsigned long drate,
+                                unsigned long prate)
+{
+        struct clk_pll *pll = to_clk_pll(hw);
+        struct pll_rate_tbl *rtbl = pll->vco->rtbl;
+        unsigned long flags = 0, val;
+        int i;
+
+        clk_pll_round_rate_index(hw, drate, NULL, &i);
+
+        if (pll->vco->lock)
+                spin_lock_irqsave(pll->vco->lock, flags);
+
+        val = readl_relaxed(pll->vco->cfg_reg);
+        val &= ~(PLL_DIV_P_MASK << PLL_DIV_P_SHIFT);
+        val |= (rtbl[i].p & PLL_DIV_P_MASK) << PLL_DIV_P_SHIFT;
+        writel_relaxed(val, pll->vco->cfg_reg);
+
+        if (pll->vco->lock)
+                spin_unlock_irqrestore(pll->vco->lock, flags);
+
+        return 0;
+}
+
+static struct clk_ops clk_pll_ops = {
+        .recalc_rate = clk_pll_recalc_rate,
+        .round_rate = clk_pll_round_rate,
+        .set_rate = clk_pll_set_rate,
+};
+
+static inline unsigned long vco_calc_rate(struct clk_hw *hw,
+                unsigned long prate, int index)
+{
+        struct clk_vco *vco = to_clk_vco(hw);
+
+        return pll_calc_rate(vco->rtbl, prate, index, NULL);
+}
+
+static long clk_vco_round_rate(struct clk_hw *hw, unsigned long drate,
+                unsigned long *prate)
+{
+        struct clk_vco *vco = to_clk_vco(hw);
+        int unused;
+
+        return clk_round_rate_index(hw, drate, *prate, vco_calc_rate,
+                        vco->rtbl_cnt, &unused);
+}
+
+static unsigned long clk_vco_recalc_rate(struct clk_hw *hw,
+                unsigned long parent_rate)
+{
+        struct clk_vco *vco = to_clk_vco(hw);
+        unsigned long flags = 0;
+        unsigned int num = 2, den = 0, val, mode = 0;
+
+        if (vco->lock)
+                spin_lock_irqsave(vco->lock, flags);
+
+        mode = (readl_relaxed(vco->mode_reg) >> PLL_MODE_SHIFT) & PLL_MODE_MASK;
+
+        val = readl_relaxed(vco->cfg_reg);
+
+        if (vco->lock)
+                spin_unlock_irqrestore(vco->lock, flags);
+
+        den = (val >> PLL_DIV_N_SHIFT) & PLL_DIV_N_MASK;
+
+        /* calculate numerator & denominator */
+        if (!mode) {
+                /* Normal mode */
+                num *= (val >> PLL_NORM_FDBK_M_SHIFT) & PLL_NORM_FDBK_M_MASK;
+        } else {
+                /* Dithered mode */
+                num *= (val >> PLL_DITH_FDBK_M_SHIFT) & PLL_DITH_FDBK_M_MASK;
+                den *= 256;
+        }
+
+        if (!den) {
+                WARN(1, "%s: denominator can't be zero\n", __func__);
+                return 0;
+        }
+
+        return (((parent_rate / 10000) * num) / den) * 10000;
+}
+
+/* Configures new clock rate of vco */
+static int clk_vco_set_rate(struct clk_hw *hw, unsigned long drate,
+                                unsigned long prate)
+{
+        struct clk_vco *vco = to_clk_vco(hw);
+        struct pll_rate_tbl *rtbl = vco->rtbl;
+        unsigned long flags = 0, val;
+        int i;
+
+        clk_round_rate_index(hw, drate, prate, vco_calc_rate, vco->rtbl_cnt,
+                        &i);
+
+        if (vco->lock)
+                spin_lock_irqsave(vco->lock, flags);
+
+        val = readl_relaxed(vco->mode_reg);
+        val &= ~(PLL_MODE_MASK << PLL_MODE_SHIFT);
+        val |= (rtbl[i].mode & PLL_MODE_MASK) << PLL_MODE_SHIFT;
+        writel_relaxed(val, vco->mode_reg);
+
+        val = readl_relaxed(vco->cfg_reg);
+        val &= ~(PLL_DIV_N_MASK << PLL_DIV_N_SHIFT);
+        val |= (rtbl[i].n & PLL_DIV_N_MASK) << PLL_DIV_N_SHIFT;
+
+        val &= ~(PLL_DITH_FDBK_M_MASK << PLL_DITH_FDBK_M_SHIFT);
+        if (rtbl[i].mode)
+                val |= (rtbl[i].m & PLL_DITH_FDBK_M_MASK) <<
+                        PLL_DITH_FDBK_M_SHIFT;
+        else
+                val |= (rtbl[i].m & PLL_NORM_FDBK_M_MASK) <<
+                        PLL_NORM_FDBK_M_SHIFT;
+
+        writel_relaxed(val, vco->cfg_reg);
+
+        if (vco->lock)
+                spin_unlock_irqrestore(vco->lock, flags);
+
+        return 0;
+}
+
+static struct clk_ops clk_vco_ops = {
+        .recalc_rate = clk_vco_recalc_rate,
+        .round_rate = clk_vco_round_rate,
+        .set_rate = clk_vco_set_rate,
+};
+
+struct clk *clk_register_vco_pll(const char *vco_name, const char *pll_name,
+                const char *vco_gate_name, const char *parent_name,
+                unsigned long flags, void __iomem *mode_reg, void __iomem
+                *cfg_reg, struct pll_rate_tbl *rtbl, u8 rtbl_cnt,
+                spinlock_t *lock, struct clk **pll_clk,
+                struct clk **vco_gate_clk)
+{
+        struct clk_vco *vco;
+        struct clk_pll *pll;
+        struct clk *vco_clk, *tpll_clk, *tvco_gate_clk;
+        struct clk_init_data vco_init, pll_init;
+        const char **vco_parent_name;
+
+        if (!vco_name || !pll_name || !parent_name || !mode_reg || !cfg_reg ||
+                        !rtbl || !rtbl_cnt) {
+                pr_err("Invalid arguments passed");
+                return ERR_PTR(-EINVAL);
+        }
+
+        vco = kzalloc(sizeof(*vco), GFP_KERNEL);
+        if (!vco) {
+                pr_err("could not allocate vco clk\n");
+                return ERR_PTR(-ENOMEM);
+        }
+
+        pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+        if (!pll) {
+                pr_err("could not allocate pll clk\n");
+                goto free_vco;
+        }
+
+        /* struct clk_vco assignments */
+        vco->mode_reg = mode_reg;
+        vco->cfg_reg = cfg_reg;
+        vco->rtbl = rtbl;
+        vco->rtbl_cnt = rtbl_cnt;
+        vco->lock = lock;
+        vco->hw.init = &vco_init;
+
+        pll->vco = vco;
+        pll->hw.init = &pll_init;
+
+        if (vco_gate_name) {
+                tvco_gate_clk = clk_register_gate(NULL, vco_gate_name,
+                                parent_name, 0, mode_reg, PLL_ENABLE, 0, lock);
+                if (IS_ERR_OR_NULL(tvco_gate_clk))
+                        goto free_pll;
+
+                if (vco_gate_clk)
+                        *vco_gate_clk = tvco_gate_clk;
+                vco_parent_name = &vco_gate_name;
+        } else {
+                vco_parent_name = &parent_name;
+        }
+
+        vco_init.name = vco_name;
+        vco_init.ops = &clk_vco_ops;
+        vco_init.flags = flags;
+        vco_init.parent_names = vco_parent_name;
+        vco_init.num_parents = 1;
+
+        pll_init.name = pll_name;
+        pll_init.ops = &clk_pll_ops;
+        pll_init.flags = CLK_SET_RATE_PARENT;
+        pll_init.parent_names = &vco_name;
+        pll_init.num_parents = 1;
+
+        vco_clk = clk_register(NULL, &vco->hw);
+        if (IS_ERR_OR_NULL(vco_clk))
+                goto free_pll;
+
+        tpll_clk = clk_register(NULL, &pll->hw);
+        if (IS_ERR_OR_NULL(tpll_clk))
+                goto free_pll;
+
+        if (pll_clk)
+                *pll_clk = tpll_clk;
+
+        return vco_clk;
+
+free_pll:
+        kfree(pll);
+free_vco:
+        kfree(vco);
+
+        pr_err("Failed to register vco pll clock\n");
+
+        return ERR_PTR(-ENOMEM);
+}
diff --git a/drivers/clk/spear/clk.c b/drivers/clk/spear/clk.c
new file mode 100644
index 000000000000..376d4e5ff326
--- /dev/null
+++ b/drivers/clk/spear/clk.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * SPEAr clk - Common routines
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/types.h>
+#include "clk.h"
+
+long clk_round_rate_index(struct clk_hw *hw, unsigned long drate,
+                unsigned long parent_rate, clk_calc_rate calc_rate, u8 rtbl_cnt,
+                int *index)
+{
+        unsigned long prev_rate, rate = 0;
+
+        for (*index = 0; *index < rtbl_cnt; (*index)++) {
+                prev_rate = rate;
+                rate = calc_rate(hw, parent_rate, *index);
+                if (drate < rate) {
+                        /* previous clock was best */
+                        if (*index) {
+                                rate = prev_rate;
+                                (*index)--;
+                        }
+                        break;
+                }
+        }
+
+        return rate;
+}
diff --git a/drivers/clk/spear/clk.h b/drivers/clk/spear/clk.h
new file mode 100644
index 000000000000..3321c46a071c
--- /dev/null
+++ b/drivers/clk/spear/clk.h
@@ -0,0 +1,134 @@
+/*
+ * Clock framework definitions for SPEAr platform
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __SPEAR_CLK_H
+#define __SPEAR_CLK_H
+
+#include <linux/clk-provider.h>
+#include <linux/spinlock_types.h>
+#include <linux/types.h>
+
+/* Auxiliary Synth clk */
+/* Default masks */
+#define AUX_EQ_SEL_SHIFT        30
+#define AUX_EQ_SEL_MASK         1
+#define AUX_EQ1_SEL             0
+#define AUX_EQ2_SEL             1
+#define AUX_XSCALE_SHIFT        16
+#define AUX_XSCALE_MASK         0xFFF
+#define AUX_YSCALE_SHIFT        0
+#define AUX_YSCALE_MASK         0xFFF
+#define AUX_SYNT_ENB            31
+
+struct aux_clk_masks {
+        u32 eq_sel_mask;
+        u32 eq_sel_shift;
+        u32 eq1_mask;
+        u32 eq2_mask;
+        u32 xscale_sel_mask;
+        u32 xscale_sel_shift;
+        u32 yscale_sel_mask;
+        u32 yscale_sel_shift;
+        u32 enable_bit;
+};
+
+struct aux_rate_tbl {
+        u16 xscale;
+        u16 yscale;
+        u8 eq;
+};
+
+struct clk_aux {
+        struct                  clk_hw hw;
+        void __iomem            *reg;
+        struct aux_clk_masks    *masks;
+        struct aux_rate_tbl     *rtbl;
+        u8                      rtbl_cnt;
+        spinlock_t              *lock;
+};
+
+/* Fractional Synth clk */
+struct frac_rate_tbl {
+        u32 div;
+};
+
+struct clk_frac {
+        struct                  clk_hw hw;
+        void __iomem            *reg;
+        struct frac_rate_tbl    *rtbl;
+        u8                      rtbl_cnt;
+        spinlock_t              *lock;
+};
+
+/* GPT clk */
+struct gpt_rate_tbl {
+        u16 mscale;
+        u16 nscale;
+};
+
+struct clk_gpt {
+        struct                  clk_hw hw;
+        void __iomem            *reg;
+        struct gpt_rate_tbl     *rtbl;
+        u8                      rtbl_cnt;
+        spinlock_t              *lock;
+};
+
+/* VCO-PLL clk */
+struct pll_rate_tbl {
+        u8 mode;
+        u16 m;
+        u8 n;
+        u8 p;
+};
+
+struct clk_vco {
+        struct                  clk_hw hw;
+        void __iomem            *mode_reg;
+        void __iomem            *cfg_reg;
+        struct pll_rate_tbl     *rtbl;
+        u8                      rtbl_cnt;
+        spinlock_t              *lock;
+};
+
+struct clk_pll {
+        struct                  clk_hw hw;
+        struct clk_vco          *vco;
+        const char              *parent[1];
+        spinlock_t              *lock;
+};
+
+typedef unsigned long (*clk_calc_rate)(struct clk_hw *hw, unsigned long prate,
+                int index);
+
+/* clk register routines */
+struct clk *clk_register_aux(const char *aux_name, const char *gate_name,
+                const char *parent_name, unsigned long flags, void __iomem *reg,
+                struct aux_clk_masks *masks, struct aux_rate_tbl *rtbl,
+                u8 rtbl_cnt, spinlock_t *lock, struct clk **gate_clk);
+struct clk *clk_register_frac(const char *name, const char *parent_name,
+                unsigned long flags, void __iomem *reg,
+                struct frac_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock);
+struct clk *clk_register_gpt(const char *name, const char *parent_name, unsigned
+                long flags, void __iomem *reg, struct gpt_rate_tbl *rtbl, u8
+                rtbl_cnt, spinlock_t *lock);
+struct clk *clk_register_vco_pll(const char *vco_name, const char *pll_name,
+                const char *vco_gate_name, const char *parent_name,
+                unsigned long flags, void __iomem *mode_reg, void __iomem
+                *cfg_reg, struct pll_rate_tbl *rtbl, u8 rtbl_cnt,
+                spinlock_t *lock, struct clk **pll_clk,
+                struct clk **vco_gate_clk);
+
+long clk_round_rate_index(struct clk_hw *hw, unsigned long drate,
+                unsigned long parent_rate, clk_calc_rate calc_rate, u8 rtbl_cnt,
+                int *index);
+
+#endif /* __SPEAR_CLK_H */
diff --git a/drivers/clk/spear/spear1310_clock.c b/drivers/clk/spear/spear1310_clock.c
new file mode 100644
index 000000000000..42b68df9aeef
--- /dev/null
+++ b/drivers/clk/spear/spear1310_clock.c
@@ -0,0 +1,1106 @@
+/*
+ * arch/arm/mach-spear13xx/spear1310_clock.c
+ *
+ * SPEAr1310 machine clock framework source file
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/of_platform.h>
+#include <linux/spinlock_types.h>
+#include <mach/spear.h>
+#include "clk.h"
+
+/* PLL related registers and bit values */
+#define SPEAR1310_PLL_CFG                       (VA_MISC_BASE + 0x210)
+        /* PLL_CFG bit values */
+        #define SPEAR1310_CLCD_SYNT_CLK_MASK            1
+        #define SPEAR1310_CLCD_SYNT_CLK_SHIFT           31
+        #define SPEAR1310_RAS_SYNT2_3_CLK_MASK          2
+        #define SPEAR1310_RAS_SYNT2_3_CLK_SHIFT         29
+        #define SPEAR1310_RAS_SYNT_CLK_MASK             2
+        #define SPEAR1310_RAS_SYNT0_1_CLK_SHIFT         27
+        #define SPEAR1310_PLL_CLK_MASK                  2
+        #define SPEAR1310_PLL3_CLK_SHIFT                24
+        #define SPEAR1310_PLL2_CLK_SHIFT                22
+        #define SPEAR1310_PLL1_CLK_SHIFT                20
+
+#define SPEAR1310_PLL1_CTR                      (VA_MISC_BASE + 0x214)
+#define SPEAR1310_PLL1_FRQ                      (VA_MISC_BASE + 0x218)
+#define SPEAR1310_PLL2_CTR                      (VA_MISC_BASE + 0x220)
+#define SPEAR1310_PLL2_FRQ                      (VA_MISC_BASE + 0x224)
+#define SPEAR1310_PLL3_CTR                      (VA_MISC_BASE + 0x22C)
+#define SPEAR1310_PLL3_FRQ                      (VA_MISC_BASE + 0x230)
+#define SPEAR1310_PLL4_CTR                      (VA_MISC_BASE + 0x238)
+#define SPEAR1310_PLL4_FRQ                      (VA_MISC_BASE + 0x23C)
+#define SPEAR1310_PERIP_CLK_CFG                 (VA_MISC_BASE + 0x244)
+        /* PERIP_CLK_CFG bit values */
+        #define SPEAR1310_GPT_OSC24_VAL                 0
+        #define SPEAR1310_GPT_APB_VAL                   1
+        #define SPEAR1310_GPT_CLK_MASK                  1
+        #define SPEAR1310_GPT3_CLK_SHIFT                11
+        #define SPEAR1310_GPT2_CLK_SHIFT                10
+        #define SPEAR1310_GPT1_CLK_SHIFT                9
+        #define SPEAR1310_GPT0_CLK_SHIFT                8
+        #define SPEAR1310_UART_CLK_PLL5_VAL             0
+        #define SPEAR1310_UART_CLK_OSC24_VAL            1
+        #define SPEAR1310_UART_CLK_SYNT_VAL             2
+        #define SPEAR1310_UART_CLK_MASK                 2
+        #define SPEAR1310_UART_CLK_SHIFT                4
+
+        #define SPEAR1310_AUX_CLK_PLL5_VAL              0
+        #define SPEAR1310_AUX_CLK_SYNT_VAL              1
+        #define SPEAR1310_CLCD_CLK_MASK                 2
+        #define SPEAR1310_CLCD_CLK_SHIFT                2
+        #define SPEAR1310_C3_CLK_MASK                   1
+        #define SPEAR1310_C3_CLK_SHIFT                  1
+
+#define SPEAR1310_GMAC_CLK_CFG                  (VA_MISC_BASE + 0x248)
+        #define SPEAR1310_GMAC_PHY_IF_SEL_MASK          3
+        #define SPEAR1310_GMAC_PHY_IF_SEL_SHIFT         4
+        #define SPEAR1310_GMAC_PHY_CLK_MASK             1
+        #define SPEAR1310_GMAC_PHY_CLK_SHIFT            3
+        #define SPEAR1310_GMAC_PHY_INPUT_CLK_MASK       2
+        #define SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT      1
+
+#define SPEAR1310_I2S_CLK_CFG                   (VA_MISC_BASE + 0x24C)
+        /* I2S_CLK_CFG register mask */
+        #define SPEAR1310_I2S_SCLK_X_MASK               0x1F
+        #define SPEAR1310_I2S_SCLK_X_SHIFT              27
+        #define SPEAR1310_I2S_SCLK_Y_MASK               0x1F
+        #define SPEAR1310_I2S_SCLK_Y_SHIFT              22
+        #define SPEAR1310_I2S_SCLK_EQ_SEL_SHIFT         21
+        #define SPEAR1310_I2S_SCLK_SYNTH_ENB            20
+        #define SPEAR1310_I2S_PRS1_CLK_X_MASK           0xFF
+        #define SPEAR1310_I2S_PRS1_CLK_X_SHIFT          12
+        #define SPEAR1310_I2S_PRS1_CLK_Y_MASK           0xFF
+        #define SPEAR1310_I2S_PRS1_CLK_Y_SHIFT          4
+        #define SPEAR1310_I2S_PRS1_EQ_SEL_SHIFT         3
+        #define SPEAR1310_I2S_REF_SEL_MASK              1
+        #define SPEAR1310_I2S_REF_SHIFT                 2
+        #define SPEAR1310_I2S_SRC_CLK_MASK              2
+        #define SPEAR1310_I2S_SRC_CLK_SHIFT             0
+
+#define SPEAR1310_C3_CLK_SYNT                   (VA_MISC_BASE + 0x250)
+#define SPEAR1310_UART_CLK_SYNT                 (VA_MISC_BASE + 0x254)
+#define SPEAR1310_GMAC_CLK_SYNT                 (VA_MISC_BASE + 0x258)
+#define SPEAR1310_SDHCI_CLK_SYNT                (VA_MISC_BASE + 0x25C)
+#define SPEAR1310_CFXD_CLK_SYNT                 (VA_MISC_BASE + 0x260)
+#define SPEAR1310_ADC_CLK_SYNT                  (VA_MISC_BASE + 0x264)
+#define SPEAR1310_AMBA_CLK_SYNT                 (VA_MISC_BASE + 0x268)
+#define SPEAR1310_CLCD_CLK_SYNT                 (VA_MISC_BASE + 0x270)
+#define SPEAR1310_RAS_CLK_SYNT0                 (VA_MISC_BASE + 0x280)
+#define SPEAR1310_RAS_CLK_SYNT1                 (VA_MISC_BASE + 0x288)
+#define SPEAR1310_RAS_CLK_SYNT2                 (VA_MISC_BASE + 0x290)
+#define SPEAR1310_RAS_CLK_SYNT3                 (VA_MISC_BASE + 0x298)
+        /* Check Fractional synthesizer reg masks */
+
+#define SPEAR1310_PERIP1_CLK_ENB                (VA_MISC_BASE + 0x300)
+        /* PERIP1_CLK_ENB register masks */
+        #define SPEAR1310_RTC_CLK_ENB                   31
+        #define SPEAR1310_ADC_CLK_ENB                   30
+        #define SPEAR1310_C3_CLK_ENB                    29
+        #define SPEAR1310_JPEG_CLK_ENB                  28
+        #define SPEAR1310_CLCD_CLK_ENB                  27
+        #define SPEAR1310_DMA_CLK_ENB                   25
+        #define SPEAR1310_GPIO1_CLK_ENB                 24
+        #define SPEAR1310_GPIO0_CLK_ENB                 23
+        #define SPEAR1310_GPT1_CLK_ENB                  22
+        #define SPEAR1310_GPT0_CLK_ENB                  21
+        #define SPEAR1310_I2S0_CLK_ENB                  20
+        #define SPEAR1310_I2S1_CLK_ENB                  19
+        #define SPEAR1310_I2C0_CLK_ENB                  18
+        #define SPEAR1310_SSP_CLK_ENB                   17
+        #define SPEAR1310_UART_CLK_ENB                  15
+        #define SPEAR1310_PCIE_SATA_2_CLK_ENB           14
+        #define SPEAR1310_PCIE_SATA_1_CLK_ENB           13
+        #define SPEAR1310_PCIE_SATA_0_CLK_ENB           12
+        #define SPEAR1310_UOC_CLK_ENB                   11
+        #define SPEAR1310_UHC1_CLK_ENB                  10
+        #define SPEAR1310_UHC0_CLK_ENB                  9
+        #define SPEAR1310_GMAC_CLK_ENB                  8
+        #define SPEAR1310_CFXD_CLK_ENB                  7
+        #define SPEAR1310_SDHCI_CLK_ENB                 6
+        #define SPEAR1310_SMI_CLK_ENB                   5
+        #define SPEAR1310_FSMC_CLK_ENB                  4
+        #define SPEAR1310_SYSRAM0_CLK_ENB               3
+        #define SPEAR1310_SYSRAM1_CLK_ENB               2
+        #define SPEAR1310_SYSROM_CLK_ENB                1
+        #define SPEAR1310_BUS_CLK_ENB                   0
+
+#define SPEAR1310_PERIP2_CLK_ENB                (VA_MISC_BASE + 0x304)
+        /* PERIP2_CLK_ENB register masks */
+        #define SPEAR1310_THSENS_CLK_ENB                8
+        #define SPEAR1310_I2S_REF_PAD_CLK_ENB           7
+        #define SPEAR1310_ACP_CLK_ENB                   6
+        #define SPEAR1310_GPT3_CLK_ENB                  5
+        #define SPEAR1310_GPT2_CLK_ENB                  4
+        #define SPEAR1310_KBD_CLK_ENB                   3
+        #define SPEAR1310_CPU_DBG_CLK_ENB               2
+        #define SPEAR1310_DDR_CORE_CLK_ENB              1
+        #define SPEAR1310_DDR_CTRL_CLK_ENB              0
+
+#define SPEAR1310_RAS_CLK_ENB                   (VA_MISC_BASE + 0x310)
+        /* RAS_CLK_ENB register masks */
+        #define SPEAR1310_SYNT3_CLK_ENB                 17
+        #define SPEAR1310_SYNT2_CLK_ENB                 16
+        #define SPEAR1310_SYNT1_CLK_ENB                 15
+        #define SPEAR1310_SYNT0_CLK_ENB                 14
+        #define SPEAR1310_PCLK3_CLK_ENB                 13
+        #define SPEAR1310_PCLK2_CLK_ENB                 12
+        #define SPEAR1310_PCLK1_CLK_ENB                 11
+        #define SPEAR1310_PCLK0_CLK_ENB                 10
+        #define SPEAR1310_PLL3_CLK_ENB                  9
+        #define SPEAR1310_PLL2_CLK_ENB                  8
+        #define SPEAR1310_C125M_PAD_CLK_ENB             7
+        #define SPEAR1310_C30M_CLK_ENB                  6
+        #define SPEAR1310_C48M_CLK_ENB                  5
+        #define SPEAR1310_OSC_25M_CLK_ENB               4
+        #define SPEAR1310_OSC_32K_CLK_ENB               3
+        #define SPEAR1310_OSC_24M_CLK_ENB               2
+        #define SPEAR1310_PCLK_CLK_ENB                  1
+        #define SPEAR1310_ACLK_CLK_ENB                  0
+
+/* RAS Area Control Register */
+#define SPEAR1310_RAS_CTRL_REG0                 (VA_SPEAR1310_RAS_BASE + 0x000)
+        #define SPEAR1310_SSP1_CLK_MASK                 3
+        #define SPEAR1310_SSP1_CLK_SHIFT                26
+        #define SPEAR1310_TDM_CLK_MASK                  1
+        #define SPEAR1310_TDM2_CLK_SHIFT                24
+        #define SPEAR1310_TDM1_CLK_SHIFT                23
+        #define SPEAR1310_I2C_CLK_MASK                  1
+        #define SPEAR1310_I2C7_CLK_SHIFT                22
+        #define SPEAR1310_I2C6_CLK_SHIFT                21
+        #define SPEAR1310_I2C5_CLK_SHIFT                20
+        #define SPEAR1310_I2C4_CLK_SHIFT                19
+        #define SPEAR1310_I2C3_CLK_SHIFT                18
+        #define SPEAR1310_I2C2_CLK_SHIFT                17
+        #define SPEAR1310_I2C1_CLK_SHIFT                16
+        #define SPEAR1310_GPT64_CLK_MASK                1
+        #define SPEAR1310_GPT64_CLK_SHIFT               15
+        #define SPEAR1310_RAS_UART_CLK_MASK             1
+        #define SPEAR1310_UART5_CLK_SHIFT               14
+        #define SPEAR1310_UART4_CLK_SHIFT               13
+        #define SPEAR1310_UART3_CLK_SHIFT               12
+        #define SPEAR1310_UART2_CLK_SHIFT               11
+        #define SPEAR1310_UART1_CLK_SHIFT               10
+        #define SPEAR1310_PCI_CLK_MASK                  1
+        #define SPEAR1310_PCI_CLK_SHIFT                 0
+
+#define SPEAR1310_RAS_CTRL_REG1                 (VA_SPEAR1310_RAS_BASE + 0x004)
+        #define SPEAR1310_PHY_CLK_MASK                  0x3
+        #define SPEAR1310_RMII_PHY_CLK_SHIFT            0
+        #define SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT      2
+
+#define SPEAR1310_RAS_SW_CLK_CTRL               (VA_SPEAR1310_RAS_BASE + 0x0148)
+        #define SPEAR1310_CAN1_CLK_ENB                  25
+        #define SPEAR1310_CAN0_CLK_ENB                  24
+        #define SPEAR1310_GPT64_CLK_ENB                 23
+        #define SPEAR1310_SSP1_CLK_ENB                  22
+        #define SPEAR1310_I2C7_CLK_ENB                  21
+        #define SPEAR1310_I2C6_CLK_ENB                  20
+        #define SPEAR1310_I2C5_CLK_ENB                  19
+        #define SPEAR1310_I2C4_CLK_ENB                  18
+        #define SPEAR1310_I2C3_CLK_ENB                  17
+        #define SPEAR1310_I2C2_CLK_ENB                  16
+        #define SPEAR1310_I2C1_CLK_ENB                  15
+        #define SPEAR1310_UART5_CLK_ENB                 14
+        #define SPEAR1310_UART4_CLK_ENB                 13
+        #define SPEAR1310_UART3_CLK_ENB                 12
+        #define SPEAR1310_UART2_CLK_ENB                 11
+        #define SPEAR1310_UART1_CLK_ENB                 10
+        #define SPEAR1310_RS485_1_CLK_ENB               9
+        #define SPEAR1310_RS485_0_CLK_ENB               8
+        #define SPEAR1310_TDM2_CLK_ENB                  7
+        #define SPEAR1310_TDM1_CLK_ENB                  6
+        #define SPEAR1310_PCI_CLK_ENB                   5
+        #define SPEAR1310_GMII_CLK_ENB                  4
+        #define SPEAR1310_MII2_CLK_ENB                  3
+        #define SPEAR1310_MII1_CLK_ENB                  2
+        #define SPEAR1310_MII0_CLK_ENB                  1
+        #define SPEAR1310_ESRAM_CLK_ENB                 0
+
+static DEFINE_SPINLOCK(_lock);
+
+/* pll rate configuration table, in ascending order of rates */
+static struct pll_rate_tbl pll_rtbl[] = {
+        /* PCLK 24MHz */
+        {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
+        {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
+        {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
+        {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
+        {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
+        {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
+        {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
+};
+
+/* vco-pll4 rate configuration table, in ascending order of rates */
+static struct pll_rate_tbl pll4_rtbl[] = {
+        {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
+        {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
+        {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x2}, /* vco 1600, pll 400 MHz */
+        {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
+};
+
+/* aux rate configuration table, in ascending order of rates */
+static struct aux_rate_tbl aux_rtbl[] = {
+        /* For VCO1div2 = 500 MHz */
+        {.xscale = 10, .yscale = 204, .eq = 0}, /* 12.29 MHz */
+        {.xscale = 4, .yscale = 21, .eq = 0}, /* 48 MHz */
+        {.xscale = 2, .yscale = 6, .eq = 0}, /* 83 MHz */
+        {.xscale = 2, .yscale = 4, .eq = 0}, /* 125 MHz */
+        {.xscale = 1, .yscale = 3, .eq = 1}, /* 166 MHz */
+        {.xscale = 1, .yscale = 2, .eq = 1}, /* 250 MHz */
+};
+
+/* gmac rate configuration table, in ascending order of rates */
+static struct aux_rate_tbl gmac_rtbl[] = {
+        /* For gmac phy input clk */
+        {.xscale = 2, .yscale = 6, .eq = 0}, /* divided by 6 */
+        {.xscale = 2, .yscale = 4, .eq = 0}, /* divided by 4 */
+        {.xscale = 1, .yscale = 3, .eq = 1}, /* divided by 3 */
+        {.xscale = 1, .yscale = 2, .eq = 1}, /* divided by 2 */
+};
+
+/* clcd rate configuration table, in ascending order of rates */
+static struct frac_rate_tbl clcd_rtbl[] = {
+        {.div = 0x14000}, /* 25 Mhz , for vc01div4 = 250 MHz*/
+        {.div = 0x1284B}, /* 27 Mhz , for vc01div4 = 250 MHz*/
+        {.div = 0x0D8D3}, /* 58 Mhz , for vco1div4 = 393 MHz */
+        {.div = 0x0B72C}, /* 58 Mhz , for vco1div4 = 332 MHz */
+        {.div = 0x089EE}, /* 58 Mhz , for vc01div4 = 250 MHz*/
+        {.div = 0x06f1C}, /* 72 Mhz , for vc01div4 = 250 MHz*/
+        {.div = 0x06E58}, /* 58 Mhz , for vco1div4 = 200 MHz */
+        {.div = 0x06c1B}, /* 74 Mhz , for vc01div4 = 250 MHz*/
+        {.div = 0x04A12}, /* 108 Mhz , for vc01div4 = 250 MHz*/
+        {.div = 0x0378E}, /* 144 Mhz , for vc01div4 = 250 MHz*/
+};
+
+/* i2s prescaler1 masks */
+static struct aux_clk_masks i2s_prs1_masks = {
+        .eq_sel_mask = AUX_EQ_SEL_MASK,
+        .eq_sel_shift = SPEAR1310_I2S_PRS1_EQ_SEL_SHIFT,
+        .eq1_mask = AUX_EQ1_SEL,
+        .eq2_mask = AUX_EQ2_SEL,
+        .xscale_sel_mask = SPEAR1310_I2S_PRS1_CLK_X_MASK,
+        .xscale_sel_shift = SPEAR1310_I2S_PRS1_CLK_X_SHIFT,
+        .yscale_sel_mask = SPEAR1310_I2S_PRS1_CLK_Y_MASK,
+        .yscale_sel_shift = SPEAR1310_I2S_PRS1_CLK_Y_SHIFT,
+};
+
+/* i2s sclk (bit clock) syynthesizers masks */
+static struct aux_clk_masks i2s_sclk_masks = {
+        .eq_sel_mask = AUX_EQ_SEL_MASK,
+        .eq_sel_shift = SPEAR1310_I2S_SCLK_EQ_SEL_SHIFT,
+        .eq1_mask = AUX_EQ1_SEL,
+        .eq2_mask = AUX_EQ2_SEL,
+        .xscale_sel_mask = SPEAR1310_I2S_SCLK_X_MASK,
+        .xscale_sel_shift = SPEAR1310_I2S_SCLK_X_SHIFT,
+        .yscale_sel_mask = SPEAR1310_I2S_SCLK_Y_MASK,
+        .yscale_sel_shift = SPEAR1310_I2S_SCLK_Y_SHIFT,
+        .enable_bit = SPEAR1310_I2S_SCLK_SYNTH_ENB,
+};
+
+/* i2s prs1 aux rate configuration table, in ascending order of rates */
+static struct aux_rate_tbl i2s_prs1_rtbl[] = {
+        /* For parent clk = 49.152 MHz */
+        {.xscale = 1, .yscale = 2, .eq = 0}, /* 12.288 MHz */
+};
+
+/* i2s sclk aux rate configuration table, in ascending order of rates */
+static struct aux_rate_tbl i2s_sclk_rtbl[] = {
+        /* For i2s_ref_clk = 12.288MHz */
+        {.xscale = 1, .yscale = 4, .eq = 0}, /* 1.53 MHz */
+        {.xscale = 1, .yscale = 2, .eq = 0}, /* 3.07 Mhz */
+};
+
+/* adc rate configuration table, in ascending order of rates */
+/* possible adc range is 2.5 MHz to 20 MHz. */
+static struct aux_rate_tbl adc_rtbl[] = {
+        /* For ahb = 166.67 MHz */
+        {.xscale = 1, .yscale = 31, .eq = 0}, /* 2.68 MHz */
+        {.xscale = 2, .yscale = 21, .eq = 0}, /* 7.94 MHz */
+        {.xscale = 4, .yscale = 21, .eq = 0}, /* 15.87 MHz */
+        {.xscale = 10, .yscale = 42, .eq = 0}, /* 19.84 MHz */
+};
+
+/* General synth rate configuration table, in ascending order of rates */
+static struct frac_rate_tbl gen_rtbl[] = {
+        /* For vco1div4 = 250 MHz */
+        {.div = 0x14000}, /* 25 MHz */
+        {.div = 0x0A000}, /* 50 MHz */
+        {.div = 0x05000}, /* 100 MHz */
+        {.div = 0x02000}, /* 250 MHz */
+};
+
+/* clock parents */
+static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", };
+static const char *gpt_parents[] = { "osc_24m_clk", "apb_clk", };
+static const char *uart0_parents[] = { "pll5_clk", "uart_synth_gate_clk", };
+static const char *c3_parents[] = { "pll5_clk", "c3_synth_gate_clk", };
+static const char *gmac_phy_input_parents[] = { "gmii_125m_pad_clk", "pll2_clk",
+        "osc_25m_clk", };
+static const char *gmac_phy_parents[] = { "gmac_phy_input_mux_clk",
+        "gmac_phy_synth_gate_clk", };
+static const char *clcd_synth_parents[] = { "vco1div4_clk", "pll2_clk", };
+static const char *clcd_pixel_parents[] = { "pll5_clk", "clcd_synth_clk", };
+static const char *i2s_src_parents[] = { "vco1div2_clk", "none", "pll3_clk",
+        "i2s_src_pad_clk", };
+static const char *i2s_ref_parents[] = { "i2s_src_mux_clk", "i2s_prs1_clk", };
+static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk",
+        "pll3_clk", };
+static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco3div2_clk",
+        "pll2_clk", };
+static const char *rmii_phy_parents[] = { "ras_tx50_clk", "none",
+        "ras_pll2_clk", "ras_synth0_clk", };
+static const char *smii_rgmii_phy_parents[] = { "none", "ras_tx125_clk",
+        "ras_pll2_clk", "ras_synth0_clk", };
+static const char *uart_parents[] = { "ras_apb_clk", "gen_synth3_clk", };
+static const char *i2c_parents[] = { "ras_apb_clk", "gen_synth1_clk", };
+static const char *ssp1_parents[] = { "ras_apb_clk", "gen_synth1_clk",
+        "ras_plclk0_clk", };
+static const char *pci_parents[] = { "ras_pll3_clk", "gen_synth2_clk", };
+static const char *tdm_parents[] = { "ras_pll3_clk", "gen_synth1_clk", };
+
+void __init spear1310_clk_init(void)
+{
+        struct clk *clk, *clk1;
+
+        clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
+        clk_register_clkdev(clk, "apb_pclk", NULL);
+
+        clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
+                        32000);
+        clk_register_clkdev(clk, "osc_32k_clk", NULL);
+
+        clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT,
+                        24000000);
+        clk_register_clkdev(clk, "osc_24m_clk", NULL);
+
+        clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, CLK_IS_ROOT,
+                        25000000);
+        clk_register_clkdev(clk, "osc_25m_clk", NULL);
+
+        clk = clk_register_fixed_rate(NULL, "gmii_125m_pad_clk", NULL,
+                        CLK_IS_ROOT, 125000000);
+        clk_register_clkdev(clk, "gmii_125m_pad_clk", NULL);
+
+        clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL,
+                        CLK_IS_ROOT, 12288000);
+        clk_register_clkdev(clk, "i2s_src_pad_clk", NULL);
+
+        /* clock derived from 32 KHz osc clk */
+        clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0,
+                        SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_RTC_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "fc900000.rtc");
+
+        /* clock derived from 24 or 25 MHz osc clk */
+        /* vco-pll */
+        clk = clk_register_mux(NULL, "vco1_mux_clk", vco_parents,
+                        ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG,
+                        SPEAR1310_PLL1_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "vco1_mux_clk", NULL);
+        clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mux_clk",
+                        0, SPEAR1310_PLL1_CTR, SPEAR1310_PLL1_FRQ, pll_rtbl,
+                        ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
+        clk_register_clkdev(clk, "vco1_clk", NULL);
+        clk_register_clkdev(clk1, "pll1_clk", NULL);
+
+        clk = clk_register_mux(NULL, "vco2_mux_clk", vco_parents,
+                        ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG,
+                        SPEAR1310_PLL2_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "vco2_mux_clk", NULL);
+        clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mux_clk",
+                        0, SPEAR1310_PLL2_CTR, SPEAR1310_PLL2_FRQ, pll_rtbl,
+                        ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
+        clk_register_clkdev(clk, "vco2_clk", NULL);
+        clk_register_clkdev(clk1, "pll2_clk", NULL);
+
+        clk = clk_register_mux(NULL, "vco3_mux_clk", vco_parents,
+                        ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG,
+                        SPEAR1310_PLL3_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "vco3_mux_clk", NULL);
+        clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mux_clk",
+                        0, SPEAR1310_PLL3_CTR, SPEAR1310_PLL3_FRQ, pll_rtbl,
+                        ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
+        clk_register_clkdev(clk, "vco3_clk", NULL);
+        clk_register_clkdev(clk1, "pll3_clk", NULL);
+
+        clk = clk_register_vco_pll("vco4_clk", "pll4_clk", NULL, "osc_24m_clk",
+                        0, SPEAR1310_PLL4_CTR, SPEAR1310_PLL4_FRQ, pll4_rtbl,
+                        ARRAY_SIZE(pll4_rtbl), &_lock, &clk1, NULL);
+        clk_register_clkdev(clk, "vco4_clk", NULL);
+        clk_register_clkdev(clk1, "pll4_clk", NULL);
+
+        clk = clk_register_fixed_rate(NULL, "pll5_clk", "osc_24m_clk", 0,
+                        48000000);
+        clk_register_clkdev(clk, "pll5_clk", NULL);
+
+        clk = clk_register_fixed_rate(NULL, "pll6_clk", "osc_25m_clk", 0,
+                        25000000);
+        clk_register_clkdev(clk, "pll6_clk", NULL);
+
+        /* vco div n clocks */
+        clk = clk_register_fixed_factor(NULL, "vco1div2_clk", "vco1_clk", 0, 1,
+                        2);
+        clk_register_clkdev(clk, "vco1div2_clk", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "vco1div4_clk", "vco1_clk", 0, 1,
+                        4);
+        clk_register_clkdev(clk, "vco1div4_clk", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "vco2div2_clk", "vco2_clk", 0, 1,
+                        2);
+        clk_register_clkdev(clk, "vco2div2_clk", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "vco3div2_clk", "vco3_clk", 0, 1,
+                        2);
+        clk_register_clkdev(clk, "vco3div2_clk", NULL);
+
+        /* peripherals */
+        clk_register_fixed_factor(NULL, "thermal_clk", "osc_24m_clk", 0, 1,
+                        128);
+        clk = clk_register_gate(NULL, "thermal_gate_clk", "thermal_clk", 0,
+                        SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_THSENS_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "spear_thermal");
+
+        /* clock derived from pll4 clk */
+        clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1,
+                        1);
+        clk_register_clkdev(clk, "ddr_clk", NULL);
+
+        /* clock derived from pll1 clk */
+        clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", 0, 1, 2);
+        clk_register_clkdev(clk, "cpu_clk", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1,
+                        2);
+        clk_register_clkdev(clk, NULL, "ec800620.wdt");
+
+        clk = clk_register_fixed_factor(NULL, "ahb_clk", "pll1_clk", 0, 1,
+                        6);
+        clk_register_clkdev(clk, "ahb_clk", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "apb_clk", "pll1_clk", 0, 1,
+                        12);
+        clk_register_clkdev(clk, "apb_clk", NULL);
+
+        /* gpt clocks */
+        clk = clk_register_mux(NULL, "gpt0_mux_clk", gpt_parents,
+                        ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
+                        SPEAR1310_GPT0_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "gpt0_mux_clk", NULL);
+        clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mux_clk", 0,
+                        SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT0_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "gpt0");
+
+        clk = clk_register_mux(NULL, "gpt1_mux_clk", gpt_parents,
+                        ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
+                        SPEAR1310_GPT1_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "gpt1_mux_clk", NULL);
+        clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mux_clk", 0,
+                        SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT1_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "gpt1");
+
+        clk = clk_register_mux(NULL, "gpt2_mux_clk", gpt_parents,
+                        ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
+                        SPEAR1310_GPT2_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "gpt2_mux_clk", NULL);
+        clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mux_clk", 0,
+                        SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT2_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "gpt2");
+
+        clk = clk_register_mux(NULL, "gpt3_mux_clk", gpt_parents,
+                        ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
+                        SPEAR1310_GPT3_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "gpt3_mux_clk", NULL);
+        clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mux_clk", 0,
+                        SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT3_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "gpt3");
+
+        /* others */
+        clk = clk_register_aux("uart_synth_clk", "uart_synth_gate_clk",
+                        "vco1div2_clk", 0, SPEAR1310_UART_CLK_SYNT, NULL,
+                        aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
+        clk_register_clkdev(clk, "uart_synth_clk", NULL);
+        clk_register_clkdev(clk1, "uart_synth_gate_clk", NULL);
+
+        clk = clk_register_mux(NULL, "uart0_mux_clk", uart0_parents,
+                        ARRAY_SIZE(uart0_parents), 0, SPEAR1310_PERIP_CLK_CFG,
+                        SPEAR1310_UART_CLK_SHIFT, SPEAR1310_UART_CLK_MASK, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "uart0_mux_clk", NULL);
+
+        clk = clk_register_gate(NULL, "uart0_clk", "uart0_mux_clk", 0,
+                        SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UART_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "e0000000.serial");
+
+        clk = clk_register_aux("sdhci_synth_clk", "sdhci_synth_gate_clk",
+                        "vco1div2_clk", 0, SPEAR1310_SDHCI_CLK_SYNT, NULL,
+                        aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
+        clk_register_clkdev(clk, "sdhci_synth_clk", NULL);
+        clk_register_clkdev(clk1, "sdhci_synth_gate_clk", NULL);
+
+        clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_synth_gate_clk", 0,
+                        SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SDHCI_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "b3000000.sdhci");
+
+        clk = clk_register_aux("cfxd_synth_clk", "cfxd_synth_gate_clk",
+                        "vco1div2_clk", 0, SPEAR1310_CFXD_CLK_SYNT, NULL,
+                        aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
+        clk_register_clkdev(clk, "cfxd_synth_clk", NULL);
+        clk_register_clkdev(clk1, "cfxd_synth_gate_clk", NULL);
+
+        clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_synth_gate_clk", 0,
+                        SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_CFXD_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "b2800000.cf");
+        clk_register_clkdev(clk, NULL, "arasan_xd");
+
+        clk = clk_register_aux("c3_synth_clk", "c3_synth_gate_clk",
+                        "vco1div2_clk", 0, SPEAR1310_C3_CLK_SYNT, NULL,
+                        aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
+        clk_register_clkdev(clk, "c3_synth_clk", NULL);
+        clk_register_clkdev(clk1, "c3_synth_gate_clk", NULL);
+
+        clk = clk_register_mux(NULL, "c3_mux_clk", c3_parents,
+                        ARRAY_SIZE(c3_parents), 0, SPEAR1310_PERIP_CLK_CFG,
+                        SPEAR1310_C3_CLK_SHIFT, SPEAR1310_C3_CLK_MASK, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "c3_mux_clk", NULL);
+
+        clk = clk_register_gate(NULL, "c3_clk", "c3_mux_clk", 0,
+                        SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_C3_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "c3");
+
+        /* gmac */
+        clk = clk_register_mux(NULL, "gmac_phy_input_mux_clk",
+                        gmac_phy_input_parents,
+                        ARRAY_SIZE(gmac_phy_input_parents), 0,
+                        SPEAR1310_GMAC_CLK_CFG,
+                        SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT,
+                        SPEAR1310_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock);
+        clk_register_clkdev(clk, "gmac_phy_input_mux_clk", NULL);
+
+        clk = clk_register_aux("gmac_phy_synth_clk", "gmac_phy_synth_gate_clk",
+                        "gmac_phy_input_mux_clk", 0, SPEAR1310_GMAC_CLK_SYNT,
+                        NULL, gmac_rtbl, ARRAY_SIZE(gmac_rtbl), &_lock, &clk1);
+        clk_register_clkdev(clk, "gmac_phy_synth_clk", NULL);
+        clk_register_clkdev(clk1, "gmac_phy_synth_gate_clk", NULL);
+
+        clk = clk_register_mux(NULL, "gmac_phy_mux_clk", gmac_phy_parents,
+                        ARRAY_SIZE(gmac_phy_parents), 0,
+                        SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GMAC_PHY_CLK_SHIFT,
+                        SPEAR1310_GMAC_PHY_CLK_MASK, 0, &_lock);
+        clk_register_clkdev(clk, NULL, "stmmacphy.0");
+
+        /* clcd */
+        clk = clk_register_mux(NULL, "clcd_synth_mux_clk", clcd_synth_parents,
+                        ARRAY_SIZE(clcd_synth_parents), 0,
+                        SPEAR1310_CLCD_CLK_SYNT, SPEAR1310_CLCD_SYNT_CLK_SHIFT,
+                        SPEAR1310_CLCD_SYNT_CLK_MASK, 0, &_lock);
+        clk_register_clkdev(clk, "clcd_synth_mux_clk", NULL);
+
+        clk = clk_register_frac("clcd_synth_clk", "clcd_synth_mux_clk", 0,
+                        SPEAR1310_CLCD_CLK_SYNT, clcd_rtbl,
+                        ARRAY_SIZE(clcd_rtbl), &_lock);
+        clk_register_clkdev(clk, "clcd_synth_clk", NULL);
+
+        clk = clk_register_mux(NULL, "clcd_pixel_mux_clk", clcd_pixel_parents,
+                        ARRAY_SIZE(clcd_pixel_parents), 0,
+                        SPEAR1310_PERIP_CLK_CFG, SPEAR1310_CLCD_CLK_SHIFT,
+                        SPEAR1310_CLCD_CLK_MASK, 0, &_lock);
+        clk_register_clkdev(clk, "clcd_pixel_clk", NULL);
+
+        clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mux_clk", 0,
+                        SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_CLCD_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "clcd_clk", NULL);
+
+        /* i2s */
+        clk = clk_register_mux(NULL, "i2s_src_mux_clk", i2s_src_parents,
+                        ARRAY_SIZE(i2s_src_parents), 0, SPEAR1310_I2S_CLK_CFG,
+                        SPEAR1310_I2S_SRC_CLK_SHIFT, SPEAR1310_I2S_SRC_CLK_MASK,
+                        0, &_lock);
+        clk_register_clkdev(clk, "i2s_src_clk", NULL);
+
+        clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mux_clk", 0,
+                        SPEAR1310_I2S_CLK_CFG, &i2s_prs1_masks, i2s_prs1_rtbl,
+                        ARRAY_SIZE(i2s_prs1_rtbl), &_lock, NULL);
+        clk_register_clkdev(clk, "i2s_prs1_clk", NULL);
+
+        clk = clk_register_mux(NULL, "i2s_ref_mux_clk", i2s_ref_parents,
+                        ARRAY_SIZE(i2s_ref_parents), 0, SPEAR1310_I2S_CLK_CFG,
+                        SPEAR1310_I2S_REF_SHIFT, SPEAR1310_I2S_REF_SEL_MASK, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "i2s_ref_clk", NULL);
+
+        clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mux_clk", 0,
+                        SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_I2S_REF_PAD_CLK_ENB,
+                        0, &_lock);
+        clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL);
+
+        clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gate_clk",
+                        "i2s_ref_pad_clk", 0, SPEAR1310_I2S_CLK_CFG,
+                        &i2s_sclk_masks, i2s_sclk_rtbl,
+                        ARRAY_SIZE(i2s_sclk_rtbl), &_lock, &clk1);
+        clk_register_clkdev(clk, "i2s_sclk_clk", NULL);
+        clk_register_clkdev(clk1, "i2s_sclk_gate_clk", NULL);
+
+        /* clock derived from ahb clk */
+        clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0,
+                        SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2C0_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "e0280000.i2c");
+
+        clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0,
+                        SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_DMA_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "ea800000.dma");
+        clk_register_clkdev(clk, NULL, "eb000000.dma");
+
+        clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0,
+                        SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_JPEG_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "b2000000.jpeg");
+
+        clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0,
+                        SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GMAC_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "e2000000.eth");
+
+        clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0,
+                        SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_FSMC_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "b0000000.flash");
+
+        clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0,
+                        SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SMI_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "ea000000.flash");
+
+        clk = clk_register_gate(NULL, "usbh0_clk", "ahb_clk", 0,
+                        SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC0_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "usbh.0_clk", NULL);
+
+        clk = clk_register_gate(NULL, "usbh1_clk", "ahb_clk", 0,
+                        SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC1_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "usbh.1_clk", NULL);
+
+        clk = clk_register_gate(NULL, "uoc_clk", "ahb_clk", 0,
+                        SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UOC_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "uoc");
+
+        clk = clk_register_gate(NULL, "pcie_sata_0_clk", "ahb_clk", 0,
+                        SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_0_CLK_ENB,
+                        0, &_lock);
+        clk_register_clkdev(clk, NULL, "dw_pcie.0");
+        clk_register_clkdev(clk, NULL, "ahci.0");
+
+        clk = clk_register_gate(NULL, "pcie_sata_1_clk", "ahb_clk", 0,
+                        SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_1_CLK_ENB,
+                        0, &_lock);
+        clk_register_clkdev(clk, NULL, "dw_pcie.1");
+        clk_register_clkdev(clk, NULL, "ahci.1");
+
+        clk = clk_register_gate(NULL, "pcie_sata_2_clk", "ahb_clk", 0,
+                        SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_2_CLK_ENB,
+                        0, &_lock);
+        clk_register_clkdev(clk, NULL, "dw_pcie.2");
+        clk_register_clkdev(clk, NULL, "ahci.2");
+
+        clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
+                        SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SYSRAM0_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "sysram0_clk", NULL);
+
+        clk = clk_register_gate(NULL, "sysram1_clk", "ahb_clk", 0,
+                        SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SYSRAM1_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "sysram1_clk", NULL);
+
+        clk = clk_register_aux("adc_synth_clk", "adc_synth_gate_clk", "ahb_clk",
+                        0, SPEAR1310_ADC_CLK_SYNT, NULL, adc_rtbl,
+                        ARRAY_SIZE(adc_rtbl), &_lock, &clk1);
+        clk_register_clkdev(clk, "adc_synth_clk", NULL);
+        clk_register_clkdev(clk1, "adc_synth_gate_clk", NULL);
+
+        clk = clk_register_gate(NULL, "adc_clk", "adc_synth_gate_clk", 0,
+                        SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_ADC_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "adc_clk");
+
+        /* clock derived from apb clk */
+        clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0,
+                        SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SSP_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "e0100000.spi");
+
+        clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0,
+                        SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPIO0_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "e0600000.gpio");
+
+        clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0,
+                        SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPIO1_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "e0680000.gpio");
+
+        clk = clk_register_gate(NULL, "i2s0_clk", "apb_clk", 0,
+                        SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2S0_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "e0180000.i2s");
+
+        clk = clk_register_gate(NULL, "i2s1_clk", "apb_clk", 0,
+                        SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2S1_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "e0200000.i2s");
+
+        clk = clk_register_gate(NULL, "kbd_clk", "apb_clk", 0,
+                        SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_KBD_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "e0300000.kbd");
+
+        /* RAS clks */
+        clk = clk_register_mux(NULL, "gen_synth0_1_mux_clk",
+                        gen_synth0_1_parents, ARRAY_SIZE(gen_synth0_1_parents),
+                        0, SPEAR1310_PLL_CFG, SPEAR1310_RAS_SYNT0_1_CLK_SHIFT,
+                        SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock);
+        clk_register_clkdev(clk, "gen_synth0_1_clk", NULL);
+
+        clk = clk_register_mux(NULL, "gen_synth2_3_mux_clk",
+                        gen_synth2_3_parents, ARRAY_SIZE(gen_synth2_3_parents),
+                        0, SPEAR1310_PLL_CFG, SPEAR1310_RAS_SYNT2_3_CLK_SHIFT,
+                        SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock);
+        clk_register_clkdev(clk, "gen_synth2_3_clk", NULL);
+
+        clk = clk_register_frac("gen_synth0_clk", "gen_synth0_1_clk", 0,
+                        SPEAR1310_RAS_CLK_SYNT0, gen_rtbl, ARRAY_SIZE(gen_rtbl),
+                        &_lock);
+        clk_register_clkdev(clk, "gen_synth0_clk", NULL);
+
+        clk = clk_register_frac("gen_synth1_clk", "gen_synth0_1_clk", 0,
+                        SPEAR1310_RAS_CLK_SYNT1, gen_rtbl, ARRAY_SIZE(gen_rtbl),
+                        &_lock);
+        clk_register_clkdev(clk, "gen_synth1_clk", NULL);
+
+        clk = clk_register_frac("gen_synth2_clk", "gen_synth2_3_clk", 0,
+                        SPEAR1310_RAS_CLK_SYNT2, gen_rtbl, ARRAY_SIZE(gen_rtbl),
+                        &_lock);
+        clk_register_clkdev(clk, "gen_synth2_clk", NULL);
+
+        clk = clk_register_frac("gen_synth3_clk", "gen_synth2_3_clk", 0,
+                        SPEAR1310_RAS_CLK_SYNT3, gen_rtbl, ARRAY_SIZE(gen_rtbl),
+                        &_lock);
+        clk_register_clkdev(clk, "gen_synth3_clk", NULL);
+
+        clk = clk_register_gate(NULL, "ras_osc_24m_clk", "osc_24m_clk", 0,
+                        SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_24M_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "ras_osc_24m_clk", NULL);
+
+        clk = clk_register_gate(NULL, "ras_osc_25m_clk", "osc_25m_clk", 0,
+                        SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_25M_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "ras_osc_25m_clk", NULL);
+
+        clk = clk_register_gate(NULL, "ras_osc_32k_clk", "osc_32k_clk", 0,
+                        SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_32K_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "ras_osc_32k_clk", NULL);
+
+        clk = clk_register_gate(NULL, "ras_pll2_clk", "pll2_clk", 0,
+                        SPEAR1310_RAS_CLK_ENB, SPEAR1310_PLL2_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "ras_pll2_clk", NULL);
+
+        clk = clk_register_gate(NULL, "ras_pll3_clk", "pll3_clk", 0,
+                        SPEAR1310_RAS_CLK_ENB, SPEAR1310_PLL3_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "ras_pll3_clk", NULL);
+
+        clk = clk_register_gate(NULL, "ras_tx125_clk", "gmii_125m_pad_clk", 0,
+                        SPEAR1310_RAS_CLK_ENB, SPEAR1310_C125M_PAD_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "ras_tx125_clk", NULL);
+
+        clk = clk_register_fixed_rate(NULL, "ras_30m_fixed_clk", "pll5_clk", 0,
+                        30000000);
+        clk = clk_register_gate(NULL, "ras_30m_clk", "ras_30m_fixed_clk", 0,
+                        SPEAR1310_RAS_CLK_ENB, SPEAR1310_C30M_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "ras_30m_clk", NULL);
+
+        clk = clk_register_fixed_rate(NULL, "ras_48m_fixed_clk", "pll5_clk", 0,
+                        48000000);
+        clk = clk_register_gate(NULL, "ras_48m_clk", "ras_48m_fixed_clk", 0,
+                        SPEAR1310_RAS_CLK_ENB, SPEAR1310_C48M_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "ras_48m_clk", NULL);
+
+        clk = clk_register_gate(NULL, "ras_ahb_clk", "ahb_clk", 0,
+                        SPEAR1310_RAS_CLK_ENB, SPEAR1310_ACLK_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "ras_ahb_clk", NULL);
+
+        clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0,
+                        SPEAR1310_RAS_CLK_ENB, SPEAR1310_PCLK_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "ras_apb_clk", NULL);
+
+        clk = clk_register_fixed_rate(NULL, "ras_plclk0_clk", NULL, CLK_IS_ROOT,
+                        50000000);
+
+        clk = clk_register_fixed_rate(NULL, "ras_tx50_clk", NULL, CLK_IS_ROOT,
+                        50000000);
+
+        clk = clk_register_gate(NULL, "can0_clk", "apb_clk", 0,
+                        SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_CAN0_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "c_can_platform.0");
+
+        clk = clk_register_gate(NULL, "can1_clk", "apb_clk", 0,
+                        SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_CAN1_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "c_can_platform.1");
+
+        clk = clk_register_gate(NULL, "ras_smii0_clk", "ras_ahb_clk", 0,
+                        SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII0_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "5c400000.eth");
+
+        clk = clk_register_gate(NULL, "ras_smii1_clk", "ras_ahb_clk", 0,
+                        SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII1_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "5c500000.eth");
+
+        clk = clk_register_gate(NULL, "ras_smii2_clk", "ras_ahb_clk", 0,
+                        SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII2_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "5c600000.eth");
+
+        clk = clk_register_gate(NULL, "ras_rgmii_clk", "ras_ahb_clk", 0,
+                        SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_GMII_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "5c700000.eth");
+
+        clk = clk_register_mux(NULL, "smii_rgmii_phy_mux_clk",
+                        smii_rgmii_phy_parents,
+                        ARRAY_SIZE(smii_rgmii_phy_parents), 0,
+                        SPEAR1310_RAS_CTRL_REG1,
+                        SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT,
+                        SPEAR1310_PHY_CLK_MASK, 0, &_lock);
+        clk_register_clkdev(clk, NULL, "stmmacphy.1");
+        clk_register_clkdev(clk, NULL, "stmmacphy.2");
+        clk_register_clkdev(clk, NULL, "stmmacphy.4");
+
+        clk = clk_register_mux(NULL, "rmii_phy_mux_clk", rmii_phy_parents,
+                        ARRAY_SIZE(rmii_phy_parents), 0,
+                        SPEAR1310_RAS_CTRL_REG1, SPEAR1310_RMII_PHY_CLK_SHIFT,
+                        SPEAR1310_PHY_CLK_MASK, 0, &_lock);
+        clk_register_clkdev(clk, NULL, "stmmacphy.3");
+
+        clk = clk_register_mux(NULL, "uart1_mux_clk", uart_parents,
+                        ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
+                        SPEAR1310_UART1_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
+                        0, &_lock);
+        clk_register_clkdev(clk, "uart1_mux_clk", NULL);
+
+        clk = clk_register_gate(NULL, "uart1_clk", "uart1_mux_clk", 0,
+                        SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART1_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "5c800000.serial");
+
+        clk = clk_register_mux(NULL, "uart2_mux_clk", uart_parents,
+                        ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
+                        SPEAR1310_UART2_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
+                        0, &_lock);
+        clk_register_clkdev(clk, "uart2_mux_clk", NULL);
+
+        clk = clk_register_gate(NULL, "uart2_clk", "uart2_mux_clk", 0,
+                        SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART2_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "5c900000.serial");
+
+        clk = clk_register_mux(NULL, "uart3_mux_clk", uart_parents,
+                        ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
+                        SPEAR1310_UART3_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
+                        0, &_lock);
+        clk_register_clkdev(clk, "uart3_mux_clk", NULL);
+
+        clk = clk_register_gate(NULL, "uart3_clk", "uart3_mux_clk", 0,
+                        SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART3_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "5ca00000.serial");
+
+        clk = clk_register_mux(NULL, "uart4_mux_clk", uart_parents,
+                        ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
+                        SPEAR1310_UART4_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
+                        0, &_lock);
+        clk_register_clkdev(clk, "uart4_mux_clk", NULL);
+
+        clk = clk_register_gate(NULL, "uart4_clk", "uart4_mux_clk", 0,
+                        SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART4_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "5cb00000.serial");
+
+        clk = clk_register_mux(NULL, "uart5_mux_clk", uart_parents,
+                        ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
+                        SPEAR1310_UART5_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
+                        0, &_lock);
+        clk_register_clkdev(clk, "uart5_mux_clk", NULL);
+
+        clk = clk_register_gate(NULL, "uart5_clk", "uart5_mux_clk", 0,
+                        SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART5_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "5cc00000.serial");
+
+        clk = clk_register_mux(NULL, "i2c1_mux_clk", i2c_parents,
+                        ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
+                        SPEAR1310_I2C1_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "i2c1_mux_clk", NULL);
+
+        clk = clk_register_gate(NULL, "i2c1_clk", "i2c1_mux_clk", 0,
+                        SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C1_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "5cd00000.i2c");
+
+        clk = clk_register_mux(NULL, "i2c2_mux_clk", i2c_parents,
+                        ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
+                        SPEAR1310_I2C2_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "i2c2_mux_clk", NULL);
+
+        clk = clk_register_gate(NULL, "i2c2_clk", "i2c2_mux_clk", 0,
+                        SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C2_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "5ce00000.i2c");
+
+        clk = clk_register_mux(NULL, "i2c3_mux_clk", i2c_parents,
+                        ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
+                        SPEAR1310_I2C3_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "i2c3_mux_clk", NULL);
+
+        clk = clk_register_gate(NULL, "i2c3_clk", "i2c3_mux_clk", 0,
+                        SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C3_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "5cf00000.i2c");
+
+        clk = clk_register_mux(NULL, "i2c4_mux_clk", i2c_parents,
+                        ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
+                        SPEAR1310_I2C4_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "i2c4_mux_clk", NULL);
+
+        clk = clk_register_gate(NULL, "i2c4_clk", "i2c4_mux_clk", 0,
+                        SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C4_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "5d000000.i2c");
+
+        clk = clk_register_mux(NULL, "i2c5_mux_clk", i2c_parents,
+                        ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
+                        SPEAR1310_I2C5_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "i2c5_mux_clk", NULL);
+
+        clk = clk_register_gate(NULL, "i2c5_clk", "i2c5_mux_clk", 0,
+                        SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C5_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "5d100000.i2c");
+
+        clk = clk_register_mux(NULL, "i2c6_mux_clk", i2c_parents,
+                        ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
+                        SPEAR1310_I2C6_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "i2c6_mux_clk", NULL);
+
+        clk = clk_register_gate(NULL, "i2c6_clk", "i2c6_mux_clk", 0,
+                        SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C6_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "5d200000.i2c");
+
+        clk = clk_register_mux(NULL, "i2c7_mux_clk", i2c_parents,
+                        ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
+                        SPEAR1310_I2C7_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "i2c7_mux_clk", NULL);
+
+        clk = clk_register_gate(NULL, "i2c7_clk", "i2c7_mux_clk", 0,
+                        SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C7_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "5d300000.i2c");
+
+        clk = clk_register_mux(NULL, "ssp1_mux_clk", ssp1_parents,
+                        ARRAY_SIZE(ssp1_parents), 0, SPEAR1310_RAS_CTRL_REG0,
+                        SPEAR1310_SSP1_CLK_SHIFT, SPEAR1310_SSP1_CLK_MASK, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "ssp1_mux_clk", NULL);
+
+        clk = clk_register_gate(NULL, "ssp1_clk", "ssp1_mux_clk", 0,
+                        SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_SSP1_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "5d400000.spi");
+
+        clk = clk_register_mux(NULL, "pci_mux_clk", pci_parents,
+                        ARRAY_SIZE(pci_parents), 0, SPEAR1310_RAS_CTRL_REG0,
+                        SPEAR1310_PCI_CLK_SHIFT, SPEAR1310_PCI_CLK_MASK, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "pci_mux_clk", NULL);
+
+        clk = clk_register_gate(NULL, "pci_clk", "pci_mux_clk", 0,
+                        SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_PCI_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "pci");
+
+        clk = clk_register_mux(NULL, "tdm1_mux_clk", tdm_parents,
+                        ARRAY_SIZE(tdm_parents), 0, SPEAR1310_RAS_CTRL_REG0,
+                        SPEAR1310_TDM1_CLK_SHIFT, SPEAR1310_TDM_CLK_MASK, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "tdm1_mux_clk", NULL);
+
+        clk = clk_register_gate(NULL, "tdm1_clk", "tdm1_mux_clk", 0,
+                        SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_TDM1_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "tdm_hdlc.0");
+
+        clk = clk_register_mux(NULL, "tdm2_mux_clk", tdm_parents,
+                        ARRAY_SIZE(tdm_parents), 0, SPEAR1310_RAS_CTRL_REG0,
+                        SPEAR1310_TDM2_CLK_SHIFT, SPEAR1310_TDM_CLK_MASK, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "tdm2_mux_clk", NULL);
+
+        clk = clk_register_gate(NULL, "tdm2_clk", "tdm2_mux_clk", 0,
+                        SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_TDM2_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "tdm_hdlc.1");
+}
diff --git a/drivers/clk/spear/spear1340_clock.c b/drivers/clk/spear/spear1340_clock.c
new file mode 100644
index 000000000000..f130919d5bf8
--- /dev/null
+++ b/drivers/clk/spear/spear1340_clock.c
@@ -0,0 +1,964 @@
+/*
+ * arch/arm/mach-spear13xx/spear1340_clock.c
+ *
+ * SPEAr1340 machine clock framework source file
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/of_platform.h>
+#include <linux/spinlock_types.h>
+#include <mach/spear.h>
+#include "clk.h"
+
+/* Clock Configuration Registers */
+#define SPEAR1340_SYS_CLK_CTRL                  (VA_MISC_BASE + 0x200)
+        #define SPEAR1340_HCLK_SRC_SEL_SHIFT    27
+        #define SPEAR1340_HCLK_SRC_SEL_MASK     1
+        #define SPEAR1340_SCLK_SRC_SEL_SHIFT    23
+        #define SPEAR1340_SCLK_SRC_SEL_MASK     3
+
+/* PLL related registers and bit values */
+#define SPEAR1340_PLL_CFG                       (VA_MISC_BASE + 0x210)
+        /* PLL_CFG bit values */
+        #define SPEAR1340_CLCD_SYNT_CLK_MASK            1
+        #define SPEAR1340_CLCD_SYNT_CLK_SHIFT           31
+        #define SPEAR1340_GEN_SYNT2_3_CLK_SHIFT         29
+        #define SPEAR1340_GEN_SYNT_CLK_MASK             2
+        #define SPEAR1340_GEN_SYNT0_1_CLK_SHIFT         27
+        #define SPEAR1340_PLL_CLK_MASK                  2
+        #define SPEAR1340_PLL3_CLK_SHIFT                24
+        #define SPEAR1340_PLL2_CLK_SHIFT                22
+        #define SPEAR1340_PLL1_CLK_SHIFT                20
+
+#define SPEAR1340_PLL1_CTR                      (VA_MISC_BASE + 0x214)
+#define SPEAR1340_PLL1_FRQ                      (VA_MISC_BASE + 0x218)
+#define SPEAR1340_PLL2_CTR                      (VA_MISC_BASE + 0x220)
+#define SPEAR1340_PLL2_FRQ                      (VA_MISC_BASE + 0x224)
+#define SPEAR1340_PLL3_CTR                      (VA_MISC_BASE + 0x22C)
+#define SPEAR1340_PLL3_FRQ                      (VA_MISC_BASE + 0x230)
+#define SPEAR1340_PLL4_CTR                      (VA_MISC_BASE + 0x238)
+#define SPEAR1340_PLL4_FRQ                      (VA_MISC_BASE + 0x23C)
+#define SPEAR1340_PERIP_CLK_CFG                 (VA_MISC_BASE + 0x244)
+        /* PERIP_CLK_CFG bit values */
+        #define SPEAR1340_SPDIF_CLK_MASK                1
+        #define SPEAR1340_SPDIF_OUT_CLK_SHIFT           15
+        #define SPEAR1340_SPDIF_IN_CLK_SHIFT            14
+        #define SPEAR1340_GPT3_CLK_SHIFT                13
+        #define SPEAR1340_GPT2_CLK_SHIFT                12
+        #define SPEAR1340_GPT_CLK_MASK                  1
+        #define SPEAR1340_GPT1_CLK_SHIFT                9
+        #define SPEAR1340_GPT0_CLK_SHIFT                8
+        #define SPEAR1340_UART_CLK_MASK                 2
+        #define SPEAR1340_UART1_CLK_SHIFT               6
+        #define SPEAR1340_UART0_CLK_SHIFT               4
+        #define SPEAR1340_CLCD_CLK_MASK                 2
+        #define SPEAR1340_CLCD_CLK_SHIFT                2
+        #define SPEAR1340_C3_CLK_MASK                   1
+        #define SPEAR1340_C3_CLK_SHIFT                  1
+
+#define SPEAR1340_GMAC_CLK_CFG                  (VA_MISC_BASE + 0x248)
+        #define SPEAR1340_GMAC_PHY_CLK_MASK             1
+        #define SPEAR1340_GMAC_PHY_CLK_SHIFT            2
+        #define SPEAR1340_GMAC_PHY_INPUT_CLK_MASK       2
+        #define SPEAR1340_GMAC_PHY_INPUT_CLK_SHIFT      0
+
+#define SPEAR1340_I2S_CLK_CFG                   (VA_MISC_BASE + 0x24C)
+        /* I2S_CLK_CFG register mask */
+        #define SPEAR1340_I2S_SCLK_X_MASK               0x1F
+        #define SPEAR1340_I2S_SCLK_X_SHIFT              27
+        #define SPEAR1340_I2S_SCLK_Y_MASK               0x1F
+        #define SPEAR1340_I2S_SCLK_Y_SHIFT              22
+        #define SPEAR1340_I2S_SCLK_EQ_SEL_SHIFT         21
+        #define SPEAR1340_I2S_SCLK_SYNTH_ENB            20
+        #define SPEAR1340_I2S_PRS1_CLK_X_MASK           0xFF
+        #define SPEAR1340_I2S_PRS1_CLK_X_SHIFT          12
+        #define SPEAR1340_I2S_PRS1_CLK_Y_MASK           0xFF
+        #define SPEAR1340_I2S_PRS1_CLK_Y_SHIFT          4
+        #define SPEAR1340_I2S_PRS1_EQ_SEL_SHIFT         3
+        #define SPEAR1340_I2S_REF_SEL_MASK              1
+        #define SPEAR1340_I2S_REF_SHIFT                 2
+        #define SPEAR1340_I2S_SRC_CLK_MASK              2
+        #define SPEAR1340_I2S_SRC_CLK_SHIFT             0
+
+#define SPEAR1340_C3_CLK_SYNT                   (VA_MISC_BASE + 0x250)
+#define SPEAR1340_UART0_CLK_SYNT                (VA_MISC_BASE + 0x254)
+#define SPEAR1340_UART1_CLK_SYNT                (VA_MISC_BASE + 0x258)
+#define SPEAR1340_GMAC_CLK_SYNT                 (VA_MISC_BASE + 0x25C)
+#define SPEAR1340_SDHCI_CLK_SYNT                (VA_MISC_BASE + 0x260)
+#define SPEAR1340_CFXD_CLK_SYNT                 (VA_MISC_BASE + 0x264)
+#define SPEAR1340_ADC_CLK_SYNT                  (VA_MISC_BASE + 0x270)
+#define SPEAR1340_AMBA_CLK_SYNT                 (VA_MISC_BASE + 0x274)
+#define SPEAR1340_CLCD_CLK_SYNT                 (VA_MISC_BASE + 0x27C)
+#define SPEAR1340_SYS_CLK_SYNT                  (VA_MISC_BASE + 0x284)
+#define SPEAR1340_GEN_CLK_SYNT0                 (VA_MISC_BASE + 0x28C)
+#define SPEAR1340_GEN_CLK_SYNT1                 (VA_MISC_BASE + 0x294)
+#define SPEAR1340_GEN_CLK_SYNT2                 (VA_MISC_BASE + 0x29C)
+#define SPEAR1340_GEN_CLK_SYNT3                 (VA_MISC_BASE + 0x304)
+#define SPEAR1340_PERIP1_CLK_ENB                (VA_MISC_BASE + 0x30C)
+        #define SPEAR1340_RTC_CLK_ENB                   31
+        #define SPEAR1340_ADC_CLK_ENB                   30
+        #define SPEAR1340_C3_CLK_ENB                    29
+        #define SPEAR1340_CLCD_CLK_ENB                  27
+        #define SPEAR1340_DMA_CLK_ENB                   25
+        #define SPEAR1340_GPIO1_CLK_ENB                 24
+        #define SPEAR1340_GPIO0_CLK_ENB                 23
+        #define SPEAR1340_GPT1_CLK_ENB                  22
+        #define SPEAR1340_GPT0_CLK_ENB                  21
+        #define SPEAR1340_I2S_PLAY_CLK_ENB              20
+        #define SPEAR1340_I2S_REC_CLK_ENB               19
+        #define SPEAR1340_I2C0_CLK_ENB                  18
+        #define SPEAR1340_SSP_CLK_ENB                   17
+        #define SPEAR1340_UART0_CLK_ENB                 15
+        #define SPEAR1340_PCIE_SATA_CLK_ENB             12
+        #define SPEAR1340_UOC_CLK_ENB                   11
+        #define SPEAR1340_UHC1_CLK_ENB                  10
+        #define SPEAR1340_UHC0_CLK_ENB                  9
+        #define SPEAR1340_GMAC_CLK_ENB                  8
+        #define SPEAR1340_CFXD_CLK_ENB                  7
+        #define SPEAR1340_SDHCI_CLK_ENB                 6
+        #define SPEAR1340_SMI_CLK_ENB                   5
+        #define SPEAR1340_FSMC_CLK_ENB                  4
+        #define SPEAR1340_SYSRAM0_CLK_ENB               3
+        #define SPEAR1340_SYSRAM1_CLK_ENB               2
+        #define SPEAR1340_SYSROM_CLK_ENB                1
+        #define SPEAR1340_BUS_CLK_ENB                   0
+
+#define SPEAR1340_PERIP2_CLK_ENB                (VA_MISC_BASE + 0x310)
+        #define SPEAR1340_THSENS_CLK_ENB                8
+        #define SPEAR1340_I2S_REF_PAD_CLK_ENB           7
+        #define SPEAR1340_ACP_CLK_ENB                   6
+        #define SPEAR1340_GPT3_CLK_ENB                  5
+        #define SPEAR1340_GPT2_CLK_ENB                  4
+        #define SPEAR1340_KBD_CLK_ENB                   3
+        #define SPEAR1340_CPU_DBG_CLK_ENB               2
+        #define SPEAR1340_DDR_CORE_CLK_ENB              1
+        #define SPEAR1340_DDR_CTRL_CLK_ENB              0
+
+#define SPEAR1340_PERIP3_CLK_ENB                (VA_MISC_BASE + 0x314)
+        #define SPEAR1340_PLGPIO_CLK_ENB                18
+        #define SPEAR1340_VIDEO_DEC_CLK_ENB             16
+        #define SPEAR1340_VIDEO_ENC_CLK_ENB             15
+        #define SPEAR1340_SPDIF_OUT_CLK_ENB             13
+        #define SPEAR1340_SPDIF_IN_CLK_ENB              12
+        #define SPEAR1340_VIDEO_IN_CLK_ENB              11
+        #define SPEAR1340_CAM0_CLK_ENB                  10
+        #define SPEAR1340_CAM1_CLK_ENB                  9
+        #define SPEAR1340_CAM2_CLK_ENB                  8
+        #define SPEAR1340_CAM3_CLK_ENB                  7
+        #define SPEAR1340_MALI_CLK_ENB                  6
+        #define SPEAR1340_CEC0_CLK_ENB                  5
+        #define SPEAR1340_CEC1_CLK_ENB                  4
+        #define SPEAR1340_PWM_CLK_ENB                   3
+        #define SPEAR1340_I2C1_CLK_ENB                  2
+        #define SPEAR1340_UART1_CLK_ENB                 1
+
+static DEFINE_SPINLOCK(_lock);
+
+/* pll rate configuration table, in ascending order of rates */
+static struct pll_rate_tbl pll_rtbl[] = {
+        /* PCLK 24MHz */
+        {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
+        {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
+        {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
+        {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
+        {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
+        {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
+        {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
+        {.mode = 0, .m = 0x96, .n = 0x06, .p = 0x0}, /* vco 1200, pll 1200 MHz */
+};
+
+/* vco-pll4 rate configuration table, in ascending order of rates */
+static struct pll_rate_tbl pll4_rtbl[] = {
+        {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
+        {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
+        {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x2}, /* vco 1600, pll 400 MHz */
+        {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
+};
+
+/*
+ * All below entries generate 166 MHz for
+ * different values of vco1div2
+ */
+static struct frac_rate_tbl amba_synth_rtbl[] = {
+        {.div = 0x06062}, /* for vco1div2 = 500 MHz */
+        {.div = 0x04D1B}, /* for vco1div2 = 400 MHz */
+        {.div = 0x04000}, /* for vco1div2 = 332 MHz */
+        {.div = 0x03031}, /* for vco1div2 = 250 MHz */
+        {.div = 0x0268D}, /* for vco1div2 = 200 MHz */
+};
+
+/*
+ * Synthesizer Clock derived from vcodiv2. This clock is one of the
+ * possible clocks to feed cpu directly.
+ * We can program this synthesizer to make cpu run on different clock
+ * frequencies.
+ * Following table provides configuration values to let cpu run on 200,
+ * 250, 332, 400 or 500 MHz considering different possibilites of input
+ * (vco1div2) clock.
+ *
+ * --------------------------------------------------------------------
+ * vco1div2(Mhz)        fout(Mhz)       cpuclk = fout/2         div
+ * --------------------------------------------------------------------
+ * 400                  200             100                     0x04000
+ * 400                  250             125                     0x03333
+ * 400                  332             166                     0x0268D
+ * 400                  400             200                     0x02000
+ * --------------------------------------------------------------------
+ * 500                  200             100                     0x05000
+ * 500                  250             125                     0x04000
+ * 500                  332             166                     0x03031
+ * 500                  400             200                     0x02800
+ * 500                  500             250                     0x02000
+ * --------------------------------------------------------------------
+ * 664                  200             100                     0x06a38
+ * 664                  250             125                     0x054FD
+ * 664                  332             166                     0x04000
+ * 664                  400             200                     0x0351E
+ * 664                  500             250                     0x02A7E
+ * --------------------------------------------------------------------
+ * 800                  200             100                     0x08000
+ * 800                  250             125                     0x06666
+ * 800                  332             166                     0x04D18
+ * 800                  400             200                     0x04000
+ * 800                  500             250                     0x03333
+ * --------------------------------------------------------------------
+ * sys rate configuration table is in descending order of divisor.
+ */
+static struct frac_rate_tbl sys_synth_rtbl[] = {
+        {.div = 0x08000},
+        {.div = 0x06a38},
+        {.div = 0x06666},
+        {.div = 0x054FD},
+        {.div = 0x05000},
+        {.div = 0x04D18},
+        {.div = 0x04000},
+        {.div = 0x0351E},
+        {.div = 0x03333},
+        {.div = 0x03031},
+        {.div = 0x02A7E},
+        {.div = 0x02800},
+        {.div = 0x0268D},
+        {.div = 0x02000},
+};
+
+/* aux rate configuration table, in ascending order of rates */
+static struct aux_rate_tbl aux_rtbl[] = {
+        /* For VCO1div2 = 500 MHz */
+        {.xscale = 10, .yscale = 204, .eq = 0}, /* 12.29 MHz */
+        {.xscale = 4, .yscale = 21, .eq = 0}, /* 48 MHz */
+        {.xscale = 2, .yscale = 6, .eq = 0}, /* 83 MHz */
+        {.xscale = 2, .yscale = 4, .eq = 0}, /* 125 MHz */
+        {.xscale = 1, .yscale = 3, .eq = 1}, /* 166 MHz */
+        {.xscale = 1, .yscale = 2, .eq = 1}, /* 250 MHz */
+};
+
+/* gmac rate configuration table, in ascending order of rates */
+static struct aux_rate_tbl gmac_rtbl[] = {
+        /* For gmac phy input clk */
+        {.xscale = 2, .yscale = 6, .eq = 0}, /* divided by 6 */
+        {.xscale = 2, .yscale = 4, .eq = 0}, /* divided by 4 */
+        {.xscale = 1, .yscale = 3, .eq = 1}, /* divided by 3 */
+        {.xscale = 1, .yscale = 2, .eq = 1}, /* divided by 2 */
+};
+
+/* clcd rate configuration table, in ascending order of rates */
+static struct frac_rate_tbl clcd_rtbl[] = {
+        {.div = 0x14000}, /* 25 Mhz , for vc01div4 = 250 MHz*/
+        {.div = 0x1284B}, /* 27 Mhz , for vc01div4 = 250 MHz*/
+        {.div = 0x0D8D3}, /* 58 Mhz , for vco1div4 = 393 MHz */
+        {.div = 0x0B72C}, /* 58 Mhz , for vco1div4 = 332 MHz */
+        {.div = 0x089EE}, /* 58 Mhz , for vc01div4 = 250 MHz*/
+        {.div = 0x07BA0}, /* 65 Mhz , for vc01div4 = 250 MHz*/
+        {.div = 0x06f1C}, /* 72 Mhz , for vc01div4 = 250 MHz*/
+        {.div = 0x06E58}, /* 58 Mhz , for vco1div4 = 200 MHz */
+        {.div = 0x06c1B}, /* 74 Mhz , for vc01div4 = 250 MHz*/
+        {.div = 0x04A12}, /* 108 Mhz , for vc01div4 = 250 MHz*/
+        {.div = 0x0378E}, /* 144 Mhz , for vc01div4 = 250 MHz*/
+        {.div = 0x0360D}, /* 148 Mhz , for vc01div4 = 250 MHz*/
+        {.div = 0x035E0}, /* 148.5 MHz, for vc01div4 = 250 MHz*/
+};
+
+/* i2s prescaler1 masks */
+static struct aux_clk_masks i2s_prs1_masks = {
+        .eq_sel_mask = AUX_EQ_SEL_MASK,
+        .eq_sel_shift = SPEAR1340_I2S_PRS1_EQ_SEL_SHIFT,
+        .eq1_mask = AUX_EQ1_SEL,
+        .eq2_mask = AUX_EQ2_SEL,
+        .xscale_sel_mask = SPEAR1340_I2S_PRS1_CLK_X_MASK,
+        .xscale_sel_shift = SPEAR1340_I2S_PRS1_CLK_X_SHIFT,
+        .yscale_sel_mask = SPEAR1340_I2S_PRS1_CLK_Y_MASK,
+        .yscale_sel_shift = SPEAR1340_I2S_PRS1_CLK_Y_SHIFT,
+};
+
+/* i2s sclk (bit clock) syynthesizers masks */
+static struct aux_clk_masks i2s_sclk_masks = {
+        .eq_sel_mask = AUX_EQ_SEL_MASK,
+        .eq_sel_shift = SPEAR1340_I2S_SCLK_EQ_SEL_SHIFT,
+        .eq1_mask = AUX_EQ1_SEL,
+        .eq2_mask = AUX_EQ2_SEL,
+        .xscale_sel_mask = SPEAR1340_I2S_SCLK_X_MASK,
+        .xscale_sel_shift = SPEAR1340_I2S_SCLK_X_SHIFT,
+        .yscale_sel_mask = SPEAR1340_I2S_SCLK_Y_MASK,
+        .yscale_sel_shift = SPEAR1340_I2S_SCLK_Y_SHIFT,
+        .enable_bit = SPEAR1340_I2S_SCLK_SYNTH_ENB,
+};
+
+/* i2s prs1 aux rate configuration table, in ascending order of rates */
+static struct aux_rate_tbl i2s_prs1_rtbl[] = {
+        /* For parent clk = 49.152 MHz */
+        {.xscale = 1, .yscale = 12, .eq = 0}, /* 2.048 MHz, smp freq = 8Khz */
+        {.xscale = 11, .yscale = 96, .eq = 0}, /* 2.816 MHz, smp freq = 11Khz */
+        {.xscale = 1, .yscale = 6, .eq = 0}, /* 4.096 MHz, smp freq = 16Khz */
+        {.xscale = 11, .yscale = 48, .eq = 0}, /* 5.632 MHz, smp freq = 22Khz */
+
+        /*
+         * with parent clk = 49.152, freq gen is 8.192 MHz, smp freq = 32Khz
+         * with parent clk = 12.288, freq gen is 2.048 MHz, smp freq = 8Khz
+         */
+        {.xscale = 1, .yscale = 3, .eq = 0},
+
+        /* For parent clk = 49.152 MHz */
+        {.xscale = 17, .yscale = 37, .eq = 0}, /* 11.289 MHz, smp freq = 44Khz*/
+        {.xscale = 1, .yscale = 2, .eq = 0}, /* 12.288 MHz, smp freq = 48Khz*/
+};
+
+/* i2s sclk aux rate configuration table, in ascending order of rates */
+static struct aux_rate_tbl i2s_sclk_rtbl[] = {
+        /* For sclk = ref_clk * x/2/y */
+        {.xscale = 1, .yscale = 4, .eq = 0},
+        {.xscale = 1, .yscale = 2, .eq = 0},
+};
+
+/* adc rate configuration table, in ascending order of rates */
+/* possible adc range is 2.5 MHz to 20 MHz. */
+static struct aux_rate_tbl adc_rtbl[] = {
+        /* For ahb = 166.67 MHz */
+        {.xscale = 1, .yscale = 31, .eq = 0}, /* 2.68 MHz */
+        {.xscale = 2, .yscale = 21, .eq = 0}, /* 7.94 MHz */
+        {.xscale = 4, .yscale = 21, .eq = 0}, /* 15.87 MHz */
+        {.xscale = 10, .yscale = 42, .eq = 0}, /* 19.84 MHz */
+};
+
+/* General synth rate configuration table, in ascending order of rates */
+static struct frac_rate_tbl gen_rtbl[] = {
+        /* For vco1div4 = 250 MHz */
+        {.div = 0x1624E}, /* 22.5792 MHz */
+        {.div = 0x14585}, /* 24.576 MHz */
+        {.div = 0x14000}, /* 25 MHz */
+        {.div = 0x0B127}, /* 45.1584 MHz */
+        {.div = 0x0A000}, /* 50 MHz */
+        {.div = 0x061A8}, /* 81.92 MHz */
+        {.div = 0x05000}, /* 100 MHz */
+        {.div = 0x02800}, /* 200 MHz */
+        {.div = 0x02620}, /* 210 MHz */
+        {.div = 0x02460}, /* 220 MHz */
+        {.div = 0x022C0}, /* 230 MHz */
+        {.div = 0x02160}, /* 240 MHz */
+        {.div = 0x02000}, /* 250 MHz */
+};
+
+/* clock parents */
+static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", };
+static const char *sys_parents[] = { "none", "pll1_clk", "none", "none",
+        "sys_synth_clk", "none", "pll2_clk", "pll3_clk", };
+static const char *ahb_parents[] = { "cpu_div3_clk", "amba_synth_clk", };
+static const char *gpt_parents[] = { "osc_24m_clk", "apb_clk", };
+static const char *uart0_parents[] = { "pll5_clk", "osc_24m_clk",
+        "uart0_synth_gate_clk", };
+static const char *uart1_parents[] = { "pll5_clk", "osc_24m_clk",
+        "uart1_synth_gate_clk", };
+static const char *c3_parents[] = { "pll5_clk", "c3_synth_gate_clk", };
+static const char *gmac_phy_input_parents[] = { "gmii_125m_pad_clk", "pll2_clk",
+        "osc_25m_clk", };
+static const char *gmac_phy_parents[] = { "gmac_phy_input_mux_clk",
+        "gmac_phy_synth_gate_clk", };
+static const char *clcd_synth_parents[] = { "vco1div4_clk", "pll2_clk", };
+static const char *clcd_pixel_parents[] = { "pll5_clk", "clcd_synth_clk", };
+static const char *i2s_src_parents[] = { "vco1div2_clk", "pll2_clk", "pll3_clk",
+        "i2s_src_pad_clk", };
+static const char *i2s_ref_parents[] = { "i2s_src_mux_clk", "i2s_prs1_clk", };
+static const char *spdif_out_parents[] = { "i2s_src_pad_clk", "gen_synth2_clk",
+};
+static const char *spdif_in_parents[] = { "pll2_clk", "gen_synth3_clk", };
+
+static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk",
+        "pll3_clk", };
+static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco3div2_clk",
+        "pll2_clk", };
+
+void __init spear1340_clk_init(void)
+{
+        struct clk *clk, *clk1;
+
+        clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
+        clk_register_clkdev(clk, "apb_pclk", NULL);
+
+        clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
+                        32000);
+        clk_register_clkdev(clk, "osc_32k_clk", NULL);
+
+        clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT,
+                        24000000);
+        clk_register_clkdev(clk, "osc_24m_clk", NULL);
+
+        clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, CLK_IS_ROOT,
+                        25000000);
+        clk_register_clkdev(clk, "osc_25m_clk", NULL);
+
+        clk = clk_register_fixed_rate(NULL, "gmii_125m_pad_clk", NULL,
+                        CLK_IS_ROOT, 125000000);
+        clk_register_clkdev(clk, "gmii_125m_pad_clk", NULL);
+
+        clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL,
+                        CLK_IS_ROOT, 12288000);
+        clk_register_clkdev(clk, "i2s_src_pad_clk", NULL);
+
+        /* clock derived from 32 KHz osc clk */
+        clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0,
+                        SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_RTC_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "fc900000.rtc");
+
+        /* clock derived from 24 or 25 MHz osc clk */
+        /* vco-pll */
+        clk = clk_register_mux(NULL, "vco1_mux_clk", vco_parents,
+                        ARRAY_SIZE(vco_parents), 0, SPEAR1340_PLL_CFG,
+                        SPEAR1340_PLL1_CLK_SHIFT, SPEAR1340_PLL_CLK_MASK, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "vco1_mux_clk", NULL);
+        clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mux_clk",
+                        0, SPEAR1340_PLL1_CTR, SPEAR1340_PLL1_FRQ, pll_rtbl,
+                        ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
+        clk_register_clkdev(clk, "vco1_clk", NULL);
+        clk_register_clkdev(clk1, "pll1_clk", NULL);
+
+        clk = clk_register_mux(NULL, "vco2_mux_clk", vco_parents,
+                        ARRAY_SIZE(vco_parents), 0, SPEAR1340_PLL_CFG,
+                        SPEAR1340_PLL2_CLK_SHIFT, SPEAR1340_PLL_CLK_MASK, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "vco2_mux_clk", NULL);
+        clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mux_clk",
+                        0, SPEAR1340_PLL2_CTR, SPEAR1340_PLL2_FRQ, pll_rtbl,
+                        ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
+        clk_register_clkdev(clk, "vco2_clk", NULL);
+        clk_register_clkdev(clk1, "pll2_clk", NULL);
+
+        clk = clk_register_mux(NULL, "vco3_mux_clk", vco_parents,
+                        ARRAY_SIZE(vco_parents), 0, SPEAR1340_PLL_CFG,
+                        SPEAR1340_PLL3_CLK_SHIFT, SPEAR1340_PLL_CLK_MASK, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "vco3_mux_clk", NULL);
+        clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mux_clk",
+                        0, SPEAR1340_PLL3_CTR, SPEAR1340_PLL3_FRQ, pll_rtbl,
+                        ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
+        clk_register_clkdev(clk, "vco3_clk", NULL);
+        clk_register_clkdev(clk1, "pll3_clk", NULL);
+
+        clk = clk_register_vco_pll("vco4_clk", "pll4_clk", NULL, "osc_24m_clk",
+                        0, SPEAR1340_PLL4_CTR, SPEAR1340_PLL4_FRQ, pll4_rtbl,
+                        ARRAY_SIZE(pll4_rtbl), &_lock, &clk1, NULL);
+        clk_register_clkdev(clk, "vco4_clk", NULL);
+        clk_register_clkdev(clk1, "pll4_clk", NULL);
+
+        clk = clk_register_fixed_rate(NULL, "pll5_clk", "osc_24m_clk", 0,
+                        48000000);
+        clk_register_clkdev(clk, "pll5_clk", NULL);
+
+        clk = clk_register_fixed_rate(NULL, "pll6_clk", "osc_25m_clk", 0,
+                        25000000);
+        clk_register_clkdev(clk, "pll6_clk", NULL);
+
+        /* vco div n clocks */
+        clk = clk_register_fixed_factor(NULL, "vco1div2_clk", "vco1_clk", 0, 1,
+                        2);
+        clk_register_clkdev(clk, "vco1div2_clk", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "vco1div4_clk", "vco1_clk", 0, 1,
+                        4);
+        clk_register_clkdev(clk, "vco1div4_clk", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "vco2div2_clk", "vco2_clk", 0, 1,
+                        2);
+        clk_register_clkdev(clk, "vco2div2_clk", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "vco3div2_clk", "vco3_clk", 0, 1,
+                        2);
+        clk_register_clkdev(clk, "vco3div2_clk", NULL);
+
+        /* peripherals */
+        clk_register_fixed_factor(NULL, "thermal_clk", "osc_24m_clk", 0, 1,
+                        128);
+        clk = clk_register_gate(NULL, "thermal_gate_clk", "thermal_clk", 0,
+                        SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_THSENS_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "spear_thermal");
+
+        /* clock derived from pll4 clk */
+        clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1,
+                        1);
+        clk_register_clkdev(clk, "ddr_clk", NULL);
+
+        /* clock derived from pll1 clk */
+        clk = clk_register_frac("sys_synth_clk", "vco1div2_clk", 0,
+                        SPEAR1340_SYS_CLK_SYNT, sys_synth_rtbl,
+                        ARRAY_SIZE(sys_synth_rtbl), &_lock);
+        clk_register_clkdev(clk, "sys_synth_clk", NULL);
+
+        clk = clk_register_frac("amba_synth_clk", "vco1div2_clk", 0,
+                        SPEAR1340_AMBA_CLK_SYNT, amba_synth_rtbl,
+                        ARRAY_SIZE(amba_synth_rtbl), &_lock);
+        clk_register_clkdev(clk, "amba_synth_clk", NULL);
+
+        clk = clk_register_mux(NULL, "sys_mux_clk", sys_parents,
+                        ARRAY_SIZE(sys_parents), 0, SPEAR1340_SYS_CLK_CTRL,
+                        SPEAR1340_SCLK_SRC_SEL_SHIFT,
+                        SPEAR1340_SCLK_SRC_SEL_MASK, 0, &_lock);
+        clk_register_clkdev(clk, "sys_clk", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "cpu_clk", "sys_mux_clk", 0, 1,
+                        2);
+        clk_register_clkdev(clk, "cpu_clk", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "cpu_div3_clk", "cpu_clk", 0, 1,
+                        3);
+        clk_register_clkdev(clk, "cpu_div3_clk", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1,
+                        2);
+        clk_register_clkdev(clk, NULL, "ec800620.wdt");
+
+        clk = clk_register_mux(NULL, "ahb_clk", ahb_parents,
+                        ARRAY_SIZE(ahb_parents), 0, SPEAR1340_SYS_CLK_CTRL,
+                        SPEAR1340_HCLK_SRC_SEL_SHIFT,
+                        SPEAR1340_HCLK_SRC_SEL_MASK, 0, &_lock);
+        clk_register_clkdev(clk, "ahb_clk", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1,
+                        2);
+        clk_register_clkdev(clk, "apb_clk", NULL);
+
+        /* gpt clocks */
+        clk = clk_register_mux(NULL, "gpt0_mux_clk", gpt_parents,
+                        ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG,
+                        SPEAR1340_GPT0_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "gpt0_mux_clk", NULL);
+        clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mux_clk", 0,
+                        SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPT0_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "gpt0");
+
+        clk = clk_register_mux(NULL, "gpt1_mux_clk", gpt_parents,
+                        ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG,
+                        SPEAR1340_GPT1_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "gpt1_mux_clk", NULL);
+        clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mux_clk", 0,
+                        SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPT1_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "gpt1");
+
+        clk = clk_register_mux(NULL, "gpt2_mux_clk", gpt_parents,
+                        ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG,
+                        SPEAR1340_GPT2_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "gpt2_mux_clk", NULL);
+        clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mux_clk", 0,
+                        SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_GPT2_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "gpt2");
+
+        clk = clk_register_mux(NULL, "gpt3_mux_clk", gpt_parents,
+                        ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG,
+                        SPEAR1340_GPT3_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "gpt3_mux_clk", NULL);
+        clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mux_clk", 0,
+                        SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_GPT3_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "gpt3");
+
+        /* others */
+        clk = clk_register_aux("uart0_synth_clk", "uart0_synth_gate_clk",
+                        "vco1div2_clk", 0, SPEAR1340_UART0_CLK_SYNT, NULL,
+                        aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
+        clk_register_clkdev(clk, "uart0_synth_clk", NULL);
+        clk_register_clkdev(clk1, "uart0_synth_gate_clk", NULL);
+
+        clk = clk_register_mux(NULL, "uart0_mux_clk", uart0_parents,
+                        ARRAY_SIZE(uart0_parents), 0, SPEAR1340_PERIP_CLK_CFG,
+                        SPEAR1340_UART0_CLK_SHIFT, SPEAR1340_UART_CLK_MASK, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "uart0_mux_clk", NULL);
+
+        clk = clk_register_gate(NULL, "uart0_clk", "uart0_mux_clk", 0,
+                        SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UART0_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "e0000000.serial");
+
+        clk = clk_register_aux("uart1_synth_clk", "uart1_synth_gate_clk",
+                        "vco1div2_clk", 0, SPEAR1340_UART1_CLK_SYNT, NULL,
+                        aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
+        clk_register_clkdev(clk, "uart1_synth_clk", NULL);
+        clk_register_clkdev(clk1, "uart1_synth_gate_clk", NULL);
+
+        clk = clk_register_mux(NULL, "uart1_mux_clk", uart1_parents,
+                        ARRAY_SIZE(uart1_parents), 0, SPEAR1340_PERIP_CLK_CFG,
+                        SPEAR1340_UART1_CLK_SHIFT, SPEAR1340_UART_CLK_MASK, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "uart1_mux_clk", NULL);
+
+        clk = clk_register_gate(NULL, "uart1_clk", "uart1_mux_clk", 0,
+                        SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UART1_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "b4100000.serial");
+
+        clk = clk_register_aux("sdhci_synth_clk", "sdhci_synth_gate_clk",
+                        "vco1div2_clk", 0, SPEAR1340_SDHCI_CLK_SYNT, NULL,
+                        aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
+        clk_register_clkdev(clk, "sdhci_synth_clk", NULL);
+        clk_register_clkdev(clk1, "sdhci_synth_gate_clk", NULL);
+
+        clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_synth_gate_clk", 0,
+                        SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SDHCI_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "b3000000.sdhci");
+
+        clk = clk_register_aux("cfxd_synth_clk", "cfxd_synth_gate_clk",
+                        "vco1div2_clk", 0, SPEAR1340_CFXD_CLK_SYNT, NULL,
+                        aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
+        clk_register_clkdev(clk, "cfxd_synth_clk", NULL);
+        clk_register_clkdev(clk1, "cfxd_synth_gate_clk", NULL);
+
+        clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_synth_gate_clk", 0,
+                        SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_CFXD_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "b2800000.cf");
+        clk_register_clkdev(clk, NULL, "arasan_xd");
+
+        clk = clk_register_aux("c3_synth_clk", "c3_synth_gate_clk",
+                        "vco1div2_clk", 0, SPEAR1340_C3_CLK_SYNT, NULL,
+                        aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
+        clk_register_clkdev(clk, "c3_synth_clk", NULL);
+        clk_register_clkdev(clk1, "c3_synth_gate_clk", NULL);
+
+        clk = clk_register_mux(NULL, "c3_mux_clk", c3_parents,
+                        ARRAY_SIZE(c3_parents), 0, SPEAR1340_PERIP_CLK_CFG,
+                        SPEAR1340_C3_CLK_SHIFT, SPEAR1340_C3_CLK_MASK, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "c3_mux_clk", NULL);
+
+        clk = clk_register_gate(NULL, "c3_clk", "c3_mux_clk", 0,
+                        SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_C3_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "c3");
+
+        /* gmac */
+        clk = clk_register_mux(NULL, "gmac_phy_input_mux_clk",
+                        gmac_phy_input_parents,
+                        ARRAY_SIZE(gmac_phy_input_parents), 0,
+                        SPEAR1340_GMAC_CLK_CFG,
+                        SPEAR1340_GMAC_PHY_INPUT_CLK_SHIFT,
+                        SPEAR1340_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock);
+        clk_register_clkdev(clk, "gmac_phy_input_mux_clk", NULL);
+
+        clk = clk_register_aux("gmac_phy_synth_clk", "gmac_phy_synth_gate_clk",
+                        "gmac_phy_input_mux_clk", 0, SPEAR1340_GMAC_CLK_SYNT,
+                        NULL, gmac_rtbl, ARRAY_SIZE(gmac_rtbl), &_lock, &clk1);
+        clk_register_clkdev(clk, "gmac_phy_synth_clk", NULL);
+        clk_register_clkdev(clk1, "gmac_phy_synth_gate_clk", NULL);
+
+        clk = clk_register_mux(NULL, "gmac_phy_mux_clk", gmac_phy_parents,
+                        ARRAY_SIZE(gmac_phy_parents), 0,
+                        SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GMAC_PHY_CLK_SHIFT,
+                        SPEAR1340_GMAC_PHY_CLK_MASK, 0, &_lock);
+        clk_register_clkdev(clk, NULL, "stmmacphy.0");
+
+        /* clcd */
+        clk = clk_register_mux(NULL, "clcd_synth_mux_clk", clcd_synth_parents,
+                        ARRAY_SIZE(clcd_synth_parents), 0,
+                        SPEAR1340_CLCD_CLK_SYNT, SPEAR1340_CLCD_SYNT_CLK_SHIFT,
+                        SPEAR1340_CLCD_SYNT_CLK_MASK, 0, &_lock);
+        clk_register_clkdev(clk, "clcd_synth_mux_clk", NULL);
+
+        clk = clk_register_frac("clcd_synth_clk", "clcd_synth_mux_clk", 0,
+                        SPEAR1340_CLCD_CLK_SYNT, clcd_rtbl,
+                        ARRAY_SIZE(clcd_rtbl), &_lock);
+        clk_register_clkdev(clk, "clcd_synth_clk", NULL);
+
+        clk = clk_register_mux(NULL, "clcd_pixel_mux_clk", clcd_pixel_parents,
+                        ARRAY_SIZE(clcd_pixel_parents), 0,
+                        SPEAR1340_PERIP_CLK_CFG, SPEAR1340_CLCD_CLK_SHIFT,
+                        SPEAR1340_CLCD_CLK_MASK, 0, &_lock);
+        clk_register_clkdev(clk, "clcd_pixel_clk", NULL);
+
+        clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mux_clk", 0,
+                        SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_CLCD_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "clcd_clk", NULL);
+
+        /* i2s */
+        clk = clk_register_mux(NULL, "i2s_src_mux_clk", i2s_src_parents,
+                        ARRAY_SIZE(i2s_src_parents), 0, SPEAR1340_I2S_CLK_CFG,
+                        SPEAR1340_I2S_SRC_CLK_SHIFT, SPEAR1340_I2S_SRC_CLK_MASK,
+                        0, &_lock);
+        clk_register_clkdev(clk, "i2s_src_clk", NULL);
+
+        clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mux_clk", 0,
+                        SPEAR1340_I2S_CLK_CFG, &i2s_prs1_masks, i2s_prs1_rtbl,
+                        ARRAY_SIZE(i2s_prs1_rtbl), &_lock, NULL);
+        clk_register_clkdev(clk, "i2s_prs1_clk", NULL);
+
+        clk = clk_register_mux(NULL, "i2s_ref_mux_clk", i2s_ref_parents,
+                        ARRAY_SIZE(i2s_ref_parents), 0, SPEAR1340_I2S_CLK_CFG,
+                        SPEAR1340_I2S_REF_SHIFT, SPEAR1340_I2S_REF_SEL_MASK, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "i2s_ref_clk", NULL);
+
+        clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mux_clk", 0,
+                        SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_I2S_REF_PAD_CLK_ENB,
+                        0, &_lock);
+        clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL);
+
+        clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gate_clk",
+                        "i2s_ref_mux_clk", 0, SPEAR1340_I2S_CLK_CFG,
+                        &i2s_sclk_masks, i2s_sclk_rtbl,
+                        ARRAY_SIZE(i2s_sclk_rtbl), &_lock, &clk1);
+        clk_register_clkdev(clk, "i2s_sclk_clk", NULL);
+        clk_register_clkdev(clk1, "i2s_sclk_gate_clk", NULL);
+
+        /* clock derived from ahb clk */
+        clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0,
+                        SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2C0_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "e0280000.i2c");
+
+        clk = clk_register_gate(NULL, "i2c1_clk", "ahb_clk", 0,
+                        SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2C1_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "b4000000.i2c");
+
+        clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0,
+                        SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_DMA_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "ea800000.dma");
+        clk_register_clkdev(clk, NULL, "eb000000.dma");
+
+        clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0,
+                        SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GMAC_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "e2000000.eth");
+
+        clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0,
+                        SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_FSMC_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "b0000000.flash");
+
+        clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0,
+                        SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SMI_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "ea000000.flash");
+
+        clk = clk_register_gate(NULL, "usbh0_clk", "ahb_clk", 0,
+                        SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UHC0_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "usbh.0_clk", NULL);
+
+        clk = clk_register_gate(NULL, "usbh1_clk", "ahb_clk", 0,
+                        SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UHC1_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "usbh.1_clk", NULL);
+
+        clk = clk_register_gate(NULL, "uoc_clk", "ahb_clk", 0,
+                        SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UOC_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "uoc");
+
+        clk = clk_register_gate(NULL, "pcie_sata_clk", "ahb_clk", 0,
+                        SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_PCIE_SATA_CLK_ENB,
+                        0, &_lock);
+        clk_register_clkdev(clk, NULL, "dw_pcie");
+        clk_register_clkdev(clk, NULL, "ahci");
+
+        clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
+                        SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SYSRAM0_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "sysram0_clk", NULL);
+
+        clk = clk_register_gate(NULL, "sysram1_clk", "ahb_clk", 0,
+                        SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SYSRAM1_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "sysram1_clk", NULL);
+
+        clk = clk_register_aux("adc_synth_clk", "adc_synth_gate_clk", "ahb_clk",
+                        0, SPEAR1340_ADC_CLK_SYNT, NULL, adc_rtbl,
+                        ARRAY_SIZE(adc_rtbl), &_lock, &clk1);
+        clk_register_clkdev(clk, "adc_synth_clk", NULL);
+        clk_register_clkdev(clk1, "adc_synth_gate_clk", NULL);
+
+        clk = clk_register_gate(NULL, "adc_clk", "adc_synth_gate_clk", 0,
+                        SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_ADC_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "adc_clk");
+
+        /* clock derived from apb clk */
+        clk = clk_register_gate(NULL, "ssp_clk", "apb_clk", 0,
+                        SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SSP_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "e0100000.spi");
+
+        clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0,
+                        SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPIO0_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "e0600000.gpio");
+
+        clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0,
+                        SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPIO1_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "e0680000.gpio");
+
+        clk = clk_register_gate(NULL, "i2s_play_clk", "apb_clk", 0,
+                        SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2S_PLAY_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "b2400000.i2s");
+
+        clk = clk_register_gate(NULL, "i2s_rec_clk", "apb_clk", 0,
+                        SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2S_REC_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "b2000000.i2s");
+
+        clk = clk_register_gate(NULL, "kbd_clk", "apb_clk", 0,
+                        SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_KBD_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "e0300000.kbd");
+
+        /* RAS clks */
+        clk = clk_register_mux(NULL, "gen_synth0_1_mux_clk",
+                        gen_synth0_1_parents, ARRAY_SIZE(gen_synth0_1_parents),
+                        0, SPEAR1340_PLL_CFG, SPEAR1340_GEN_SYNT0_1_CLK_SHIFT,
+                        SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock);
+        clk_register_clkdev(clk, "gen_synth0_1_clk", NULL);
+
+        clk = clk_register_mux(NULL, "gen_synth2_3_mux_clk",
+                        gen_synth2_3_parents, ARRAY_SIZE(gen_synth2_3_parents),
+                        0, SPEAR1340_PLL_CFG, SPEAR1340_GEN_SYNT2_3_CLK_SHIFT,
+                        SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock);
+        clk_register_clkdev(clk, "gen_synth2_3_clk", NULL);
+
+        clk = clk_register_frac("gen_synth0_clk", "gen_synth0_1_clk", 0,
+                        SPEAR1340_GEN_CLK_SYNT0, gen_rtbl, ARRAY_SIZE(gen_rtbl),
+                        &_lock);
+        clk_register_clkdev(clk, "gen_synth0_clk", NULL);
+
+        clk = clk_register_frac("gen_synth1_clk", "gen_synth0_1_clk", 0,
+                        SPEAR1340_GEN_CLK_SYNT1, gen_rtbl, ARRAY_SIZE(gen_rtbl),
+                        &_lock);
+        clk_register_clkdev(clk, "gen_synth1_clk", NULL);
+
+        clk = clk_register_frac("gen_synth2_clk", "gen_synth2_3_clk", 0,
+                        SPEAR1340_GEN_CLK_SYNT2, gen_rtbl, ARRAY_SIZE(gen_rtbl),
+                        &_lock);
+        clk_register_clkdev(clk, "gen_synth2_clk", NULL);
+
+        clk = clk_register_frac("gen_synth3_clk", "gen_synth2_3_clk", 0,
+                        SPEAR1340_GEN_CLK_SYNT3, gen_rtbl, ARRAY_SIZE(gen_rtbl),
+                        &_lock);
+        clk_register_clkdev(clk, "gen_synth3_clk", NULL);
+
+        clk = clk_register_gate(NULL, "mali_clk", "gen_synth3_clk", 0,
+                        SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_MALI_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "mali");
+
+        clk = clk_register_gate(NULL, "cec0_clk", "ahb_clk", 0,
+                        SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CEC0_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "spear_cec.0");
+
+        clk = clk_register_gate(NULL, "cec1_clk", "ahb_clk", 0,
+                        SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CEC1_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "spear_cec.1");
+
+        clk = clk_register_mux(NULL, "spdif_out_mux_clk", spdif_out_parents,
+                        ARRAY_SIZE(spdif_out_parents), 0,
+                        SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_OUT_CLK_SHIFT,
+                        SPEAR1340_SPDIF_CLK_MASK, 0, &_lock);
+        clk_register_clkdev(clk, "spdif_out_mux_clk", NULL);
+
+        clk = clk_register_gate(NULL, "spdif_out_clk", "spdif_out_mux_clk", 0,
+                        SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_SPDIF_OUT_CLK_ENB,
+                        0, &_lock);
+        clk_register_clkdev(clk, NULL, "spdif-out");
+
+        clk = clk_register_mux(NULL, "spdif_in_mux_clk", spdif_in_parents,
+                        ARRAY_SIZE(spdif_in_parents), 0,
+                        SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_IN_CLK_SHIFT,
+                        SPEAR1340_SPDIF_CLK_MASK, 0, &_lock);
+        clk_register_clkdev(clk, "spdif_in_mux_clk", NULL);
+
+        clk = clk_register_gate(NULL, "spdif_in_clk", "spdif_in_mux_clk", 0,
+                        SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_SPDIF_IN_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "spdif-in");
+
+        clk = clk_register_gate(NULL, "acp_clk", "acp_mux_clk", 0,
+                        SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_ACP_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "acp_clk");
+
+        clk = clk_register_gate(NULL, "plgpio_clk", "plgpio_mux_clk", 0,
+                        SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PLGPIO_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "plgpio");
+
+        clk = clk_register_gate(NULL, "video_dec_clk", "video_dec_mux_clk", 0,
+                        SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_DEC_CLK_ENB,
+                        0, &_lock);
+        clk_register_clkdev(clk, NULL, "video_dec");
+
+        clk = clk_register_gate(NULL, "video_enc_clk", "video_enc_mux_clk", 0,
+                        SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_ENC_CLK_ENB,
+                        0, &_lock);
+        clk_register_clkdev(clk, NULL, "video_enc");
+
+        clk = clk_register_gate(NULL, "video_in_clk", "video_in_mux_clk", 0,
+                        SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_IN_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "spear_vip");
+
+        clk = clk_register_gate(NULL, "cam0_clk", "cam0_mux_clk", 0,
+                        SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM0_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "spear_camif.0");
+
+        clk = clk_register_gate(NULL, "cam1_clk", "cam1_mux_clk", 0,
+                        SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM1_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "spear_camif.1");
+
+        clk = clk_register_gate(NULL, "cam2_clk", "cam2_mux_clk", 0,
+                        SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM2_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "spear_camif.2");
+
+        clk = clk_register_gate(NULL, "cam3_clk", "cam3_mux_clk", 0,
+                        SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM3_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "spear_camif.3");
+
+        clk = clk_register_gate(NULL, "pwm_clk", "pwm_mux_clk", 0,
+                        SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PWM_CLK_ENB, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "pwm");
+}
diff --git a/drivers/clk/spear/spear3xx_clock.c b/drivers/clk/spear/spear3xx_clock.c
new file mode 100644
index 000000000000..440bb3e4c971
--- /dev/null
+++ b/drivers/clk/spear/spear3xx_clock.c
@@ -0,0 +1,612 @@
+/*
+ * SPEAr3xx machines clock framework source file
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/of_platform.h>
+#include <linux/spinlock_types.h>
+#include <mach/misc_regs.h>
+#include "clk.h"
+
+static DEFINE_SPINLOCK(_lock);
+
+#define PLL1_CTR                        (MISC_BASE + 0x008)
+#define PLL1_FRQ                        (MISC_BASE + 0x00C)
+#define PLL2_CTR                        (MISC_BASE + 0x014)
+#define PLL2_FRQ                        (MISC_BASE + 0x018)
+#define PLL_CLK_CFG                     (MISC_BASE + 0x020)
+        /* PLL_CLK_CFG register masks */
+        #define MCTR_CLK_SHIFT          28
+        #define MCTR_CLK_MASK           3
+
+#define CORE_CLK_CFG                    (MISC_BASE + 0x024)
+        /* CORE CLK CFG register masks */
+        #define GEN_SYNTH2_3_CLK_SHIFT  18
+        #define GEN_SYNTH2_3_CLK_MASK   1
+
+        #define HCLK_RATIO_SHIFT        10
+        #define HCLK_RATIO_MASK         2
+        #define PCLK_RATIO_SHIFT        8
+        #define PCLK_RATIO_MASK         2
+
+#define PERIP_CLK_CFG                   (MISC_BASE + 0x028)
+        /* PERIP_CLK_CFG register masks */
+        #define UART_CLK_SHIFT          4
+        #define UART_CLK_MASK           1
+        #define FIRDA_CLK_SHIFT         5
+        #define FIRDA_CLK_MASK          2
+        #define GPT0_CLK_SHIFT          8
+        #define GPT1_CLK_SHIFT          11
+        #define GPT2_CLK_SHIFT          12
+        #define GPT_CLK_MASK            1
+
+#define PERIP1_CLK_ENB                  (MISC_BASE + 0x02C)
+        /* PERIP1_CLK_ENB register masks */
+        #define UART_CLK_ENB            3
+        #define SSP_CLK_ENB             5
+        #define I2C_CLK_ENB             7
+        #define JPEG_CLK_ENB            8
+        #define FIRDA_CLK_ENB           10
+        #define GPT1_CLK_ENB            11
+        #define GPT2_CLK_ENB            12
+        #define ADC_CLK_ENB             15
+        #define RTC_CLK_ENB             17
+        #define GPIO_CLK_ENB            18
+        #define DMA_CLK_ENB             19
+        #define SMI_CLK_ENB             21
+        #define GMAC_CLK_ENB            23
+        #define USBD_CLK_ENB            24
+        #define USBH_CLK_ENB            25
+        #define C3_CLK_ENB              31
+
+#define RAS_CLK_ENB                     (MISC_BASE + 0x034)
+        #define RAS_AHB_CLK_ENB         0
+        #define RAS_PLL1_CLK_ENB        1
+        #define RAS_APB_CLK_ENB         2
+        #define RAS_32K_CLK_ENB         3
+        #define RAS_24M_CLK_ENB         4
+        #define RAS_48M_CLK_ENB         5
+        #define RAS_PLL2_CLK_ENB        7
+        #define RAS_SYNT0_CLK_ENB       8
+        #define RAS_SYNT1_CLK_ENB       9
+        #define RAS_SYNT2_CLK_ENB       10
+        #define RAS_SYNT3_CLK_ENB       11
+
+#define PRSC0_CLK_CFG                   (MISC_BASE + 0x044)
+#define PRSC1_CLK_CFG                   (MISC_BASE + 0x048)
+#define PRSC2_CLK_CFG                   (MISC_BASE + 0x04C)
+#define AMEM_CLK_CFG                    (MISC_BASE + 0x050)
+        #define AMEM_CLK_ENB            0
+
+#define CLCD_CLK_SYNT                   (MISC_BASE + 0x05C)
+#define FIRDA_CLK_SYNT                  (MISC_BASE + 0x060)
+#define UART_CLK_SYNT                   (MISC_BASE + 0x064)
+#define GMAC_CLK_SYNT                   (MISC_BASE + 0x068)
+#define GEN0_CLK_SYNT                   (MISC_BASE + 0x06C)
+#define GEN1_CLK_SYNT                   (MISC_BASE + 0x070)
+#define GEN2_CLK_SYNT                   (MISC_BASE + 0x074)
+#define GEN3_CLK_SYNT                   (MISC_BASE + 0x078)
+
+/* pll rate configuration table, in ascending order of rates */
+static struct pll_rate_tbl pll_rtbl[] = {
+        {.mode = 0, .m = 0x53, .n = 0x0C, .p = 0x1}, /* vco 332 & pll 166 MHz */
+        {.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* vco 532 & pll 266 MHz */
+        {.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* vco 664 & pll 332 MHz */
+};
+
+/* aux rate configuration table, in ascending order of rates */
+static struct aux_rate_tbl aux_rtbl[] = {
+        /* For PLL1 = 332 MHz */
+        {.xscale = 2, .yscale = 27, .eq = 0}, /* 12.296 MHz */
+        {.xscale = 2, .yscale = 8, .eq = 0}, /* 41.5 MHz */
+        {.xscale = 2, .yscale = 4, .eq = 0}, /* 83 MHz */
+        {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
+};
+
+/* gpt rate configuration table, in ascending order of rates */
+static struct gpt_rate_tbl gpt_rtbl[] = {
+        /* For pll1 = 332 MHz */
+        {.mscale = 4, .nscale = 0}, /* 41.5 MHz */
+        {.mscale = 2, .nscale = 0}, /* 55.3 MHz */
+        {.mscale = 1, .nscale = 0}, /* 83 MHz */
+};
+
+/* clock parents */
+static const char *uart0_parents[] = { "pll3_48m_clk", "uart_synth_gate_clk", };
+static const char *firda_parents[] = { "pll3_48m_clk", "firda_synth_gate_clk",
+};
+static const char *gpt0_parents[] = { "pll3_48m_clk", "gpt0_synth_clk", };
+static const char *gpt1_parents[] = { "pll3_48m_clk", "gpt1_synth_clk", };
+static const char *gpt2_parents[] = { "pll3_48m_clk", "gpt2_synth_clk", };
+static const char *gen2_3_parents[] = { "pll1_clk", "pll2_clk", };
+static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none",
+        "pll2_clk", };
+
+#ifdef CONFIG_MACH_SPEAR300
+static void __init spear300_clk_init(void)
+{
+        struct clk *clk;
+
+        clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_48m_clk", 0,
+                        1, 1);
+        clk_register_clkdev(clk, NULL, "60000000.clcd");
+
+        clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1,
+                        1);
+        clk_register_clkdev(clk, NULL, "94000000.flash");
+
+        clk = clk_register_fixed_factor(NULL, "sdhci_clk", "ras_ahb_clk", 0, 1,
+                        1);
+        clk_register_clkdev(clk, NULL, "70000000.sdhci");
+
+        clk = clk_register_fixed_factor(NULL, "gpio1_clk", "ras_apb_clk", 0, 1,
+                        1);
+        clk_register_clkdev(clk, NULL, "a9000000.gpio");
+
+        clk = clk_register_fixed_factor(NULL, "kbd_clk", "ras_apb_clk", 0, 1,
+                        1);
+        clk_register_clkdev(clk, NULL, "a0000000.kbd");
+}
+#endif
+
+/* array of all spear 310 clock lookups */
+#ifdef CONFIG_MACH_SPEAR310
+static void __init spear310_clk_init(void)
+{
+        struct clk *clk;
+
+        clk = clk_register_fixed_factor(NULL, "emi_clk", "ras_ahb_clk", 0, 1,
+                        1);
+        clk_register_clkdev(clk, "emi", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1,
+                        1);
+        clk_register_clkdev(clk, NULL, "44000000.flash");
+
+        clk = clk_register_fixed_factor(NULL, "tdm_clk", "ras_ahb_clk", 0, 1,
+                        1);
+        clk_register_clkdev(clk, NULL, "tdm");
+
+        clk = clk_register_fixed_factor(NULL, "uart1_clk", "ras_apb_clk", 0, 1,
+                        1);
+        clk_register_clkdev(clk, NULL, "b2000000.serial");
+
+        clk = clk_register_fixed_factor(NULL, "uart2_clk", "ras_apb_clk", 0, 1,
+                        1);
+        clk_register_clkdev(clk, NULL, "b2080000.serial");
+
+        clk = clk_register_fixed_factor(NULL, "uart3_clk", "ras_apb_clk", 0, 1,
+                        1);
+        clk_register_clkdev(clk, NULL, "b2100000.serial");
+
+        clk = clk_register_fixed_factor(NULL, "uart4_clk", "ras_apb_clk", 0, 1,
+                        1);
+        clk_register_clkdev(clk, NULL, "b2180000.serial");
+
+        clk = clk_register_fixed_factor(NULL, "uart5_clk", "ras_apb_clk", 0, 1,
+                        1);
+        clk_register_clkdev(clk, NULL, "b2200000.serial");
+}
+#endif
+
+/* array of all spear 320 clock lookups */
+#ifdef CONFIG_MACH_SPEAR320
+        #define SMII_PCLK_SHIFT                         18
+        #define SMII_PCLK_MASK                          2
+        #define SMII_PCLK_VAL_PAD                       0x0
+        #define SMII_PCLK_VAL_PLL2                      0x1
+        #define SMII_PCLK_VAL_SYNTH0                    0x2
+        #define SDHCI_PCLK_SHIFT                        15
+        #define SDHCI_PCLK_MASK                         1
+        #define SDHCI_PCLK_VAL_48M                      0x0
+        #define SDHCI_PCLK_VAL_SYNTH3                   0x1
+        #define I2S_REF_PCLK_SHIFT                      8
+        #define I2S_REF_PCLK_MASK                       1
+        #define I2S_REF_PCLK_SYNTH_VAL                  0x1
+        #define I2S_REF_PCLK_PLL2_VAL                   0x0
+        #define UART1_PCLK_SHIFT                        6
+        #define UART1_PCLK_MASK                         1
+        #define SPEAR320_UARTX_PCLK_VAL_SYNTH1          0x0
+        #define SPEAR320_UARTX_PCLK_VAL_APB             0x1
+
+static const char *i2s_ref_parents[] = { "ras_pll2_clk",
+        "ras_gen2_synth_gate_clk", };
+static const char *sdhci_parents[] = { "ras_pll3_48m_clk",
+        "ras_gen3_synth_gate_clk",
+};
+static const char *smii0_parents[] = { "smii_125m_pad", "ras_pll2_clk",
+        "ras_gen0_synth_gate_clk", };
+static const char *uartx_parents[] = { "ras_gen1_synth_gate_clk", "ras_apb_clk",
+};
+
+static void __init spear320_clk_init(void)
+{
+        struct clk *clk;
+
+        clk = clk_register_fixed_rate(NULL, "smii_125m_pad_clk", NULL,
+                        CLK_IS_ROOT, 125000000);
+        clk_register_clkdev(clk, "smii_125m_pad", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_48m_clk", 0,
+                        1, 1);
+        clk_register_clkdev(clk, NULL, "90000000.clcd");
+
+        clk = clk_register_fixed_factor(NULL, "emi_clk", "ras_ahb_clk", 0, 1,
+                        1);
+        clk_register_clkdev(clk, "emi", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1,
+                        1);
+        clk_register_clkdev(clk, NULL, "4c000000.flash");
+
+        clk = clk_register_fixed_factor(NULL, "i2c1_clk", "ras_ahb_clk", 0, 1,
+                        1);
+        clk_register_clkdev(clk, NULL, "a7000000.i2c");
+
+        clk = clk_register_fixed_factor(NULL, "pwm_clk", "ras_ahb_clk", 0, 1,
+                        1);
+        clk_register_clkdev(clk, "pwm", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "ssp1_clk", "ras_ahb_clk", 0, 1,
+                        1);
+        clk_register_clkdev(clk, NULL, "a5000000.spi");
+
+        clk = clk_register_fixed_factor(NULL, "ssp2_clk", "ras_ahb_clk", 0, 1,
+                        1);
+        clk_register_clkdev(clk, NULL, "a6000000.spi");
+
+        clk = clk_register_fixed_factor(NULL, "can0_clk", "ras_apb_clk", 0, 1,
+                        1);
+        clk_register_clkdev(clk, NULL, "c_can_platform.0");
+
+        clk = clk_register_fixed_factor(NULL, "can1_clk", "ras_apb_clk", 0, 1,
+                        1);
+        clk_register_clkdev(clk, NULL, "c_can_platform.1");
+
+        clk = clk_register_fixed_factor(NULL, "i2s_clk", "ras_apb_clk", 0, 1,
+                        1);
+        clk_register_clkdev(clk, NULL, "i2s");
+
+        clk = clk_register_mux(NULL, "i2s_ref_clk", i2s_ref_parents,
+                        ARRAY_SIZE(i2s_ref_parents), 0, SPEAR320_CONTROL_REG,
+                        I2S_REF_PCLK_SHIFT, I2S_REF_PCLK_MASK, 0, &_lock);
+        clk_register_clkdev(clk, "i2s_ref_clk", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "i2s_sclk", "i2s_ref_clk", 0, 1,
+                        4);
+        clk_register_clkdev(clk, "i2s_sclk", NULL);
+
+        clk = clk_register_mux(NULL, "rs485_clk", uartx_parents,
+                        ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG,
+                        SPEAR320_RS485_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "a9300000.serial");
+
+        clk = clk_register_mux(NULL, "sdhci_clk", sdhci_parents,
+                        ARRAY_SIZE(sdhci_parents), 0, SPEAR320_CONTROL_REG,
+                        SDHCI_PCLK_SHIFT, SDHCI_PCLK_MASK, 0, &_lock);
+        clk_register_clkdev(clk, NULL, "70000000.sdhci");
+
+        clk = clk_register_mux(NULL, "smii_pclk", smii0_parents,
+                        ARRAY_SIZE(smii0_parents), 0, SPEAR320_CONTROL_REG,
+                        SMII_PCLK_SHIFT, SMII_PCLK_MASK, 0, &_lock);
+        clk_register_clkdev(clk, NULL, "smii_pclk");
+
+        clk = clk_register_fixed_factor(NULL, "smii_clk", "smii_pclk", 0, 1, 1);
+        clk_register_clkdev(clk, NULL, "smii");
+
+        clk = clk_register_mux(NULL, "uart1_clk", uartx_parents,
+                        ARRAY_SIZE(uartx_parents), 0, SPEAR320_CONTROL_REG,
+                        UART1_PCLK_SHIFT, UART1_PCLK_MASK, 0, &_lock);
+        clk_register_clkdev(clk, NULL, "a3000000.serial");
+
+        clk = clk_register_mux(NULL, "uart2_clk", uartx_parents,
+                        ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG,
+                        SPEAR320_UART2_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "a4000000.serial");
+
+        clk = clk_register_mux(NULL, "uart3_clk", uartx_parents,
+                        ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG,
+                        SPEAR320_UART3_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "a9100000.serial");
+
+        clk = clk_register_mux(NULL, "uart4_clk", uartx_parents,
+                        ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG,
+                        SPEAR320_UART4_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "a9200000.serial");
+
+        clk = clk_register_mux(NULL, "uart5_clk", uartx_parents,
+                        ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG,
+                        SPEAR320_UART5_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "60000000.serial");
+
+        clk = clk_register_mux(NULL, "uart6_clk", uartx_parents,
+                        ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG,
+                        SPEAR320_UART6_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0,
+                        &_lock);
+        clk_register_clkdev(clk, NULL, "60100000.serial");
+}
+#endif
+
+void __init spear3xx_clk_init(void)
+{
+        struct clk *clk, *clk1;
+
+        clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
+        clk_register_clkdev(clk, "apb_pclk", NULL);
+
+        clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
+                        32000);
+        clk_register_clkdev(clk, "osc_32k_clk", NULL);
+
+        clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT,
+                        24000000);
+        clk_register_clkdev(clk, "osc_24m_clk", NULL);
+
+        /* clock derived from 32 KHz osc clk */
+        clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0,
+                        PERIP1_CLK_ENB, RTC_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, NULL, "fc900000.rtc");
+
+        /* clock derived from 24 MHz osc clk */
+        clk = clk_register_fixed_rate(NULL, "pll3_48m_clk", "osc_24m_clk", 0,
+                        48000000);
+        clk_register_clkdev(clk, "pll3_48m_clk", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_24m_clk", 0, 1,
+                        1);
+        clk_register_clkdev(clk, NULL, "fc880000.wdt");
+
+        clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL,
+                        "osc_24m_clk", 0, PLL1_CTR, PLL1_FRQ, pll_rtbl,
+                        ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
+        clk_register_clkdev(clk, "vco1_clk", NULL);
+        clk_register_clkdev(clk1, "pll1_clk", NULL);
+
+        clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL,
+                        "osc_24m_clk", 0, PLL2_CTR, PLL2_FRQ, pll_rtbl,
+                        ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
+        clk_register_clkdev(clk, "vco2_clk", NULL);
+        clk_register_clkdev(clk1, "pll2_clk", NULL);
+
+        /* clock derived from pll1 clk */
+        clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", 0, 1, 1);
+        clk_register_clkdev(clk, "cpu_clk", NULL);
+
+        clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk",
+                        CLK_SET_RATE_PARENT, CORE_CLK_CFG, HCLK_RATIO_SHIFT,
+                        HCLK_RATIO_MASK, 0, &_lock);
+        clk_register_clkdev(clk, "ahb_clk", NULL);
+
+        clk = clk_register_aux("uart_synth_clk", "uart_synth_gate_clk",
+                        "pll1_clk", 0, UART_CLK_SYNT, NULL, aux_rtbl,
+                        ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
+        clk_register_clkdev(clk, "uart_synth_clk", NULL);
+        clk_register_clkdev(clk1, "uart_synth_gate_clk", NULL);
+
+        clk = clk_register_mux(NULL, "uart0_mux_clk", uart0_parents,
+                        ARRAY_SIZE(uart0_parents), 0, PERIP_CLK_CFG,
+                        UART_CLK_SHIFT, UART_CLK_MASK, 0, &_lock);
+        clk_register_clkdev(clk, "uart0_mux_clk", NULL);
+
+        clk = clk_register_gate(NULL, "uart0", "uart0_mux_clk", 0,
+                        PERIP1_CLK_ENB, UART_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, NULL, "d0000000.serial");
+
+        clk = clk_register_aux("firda_synth_clk", "firda_synth_gate_clk",
+                        "pll1_clk", 0, FIRDA_CLK_SYNT, NULL, aux_rtbl,
+                        ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
+        clk_register_clkdev(clk, "firda_synth_clk", NULL);
+        clk_register_clkdev(clk1, "firda_synth_gate_clk", NULL);
+
+        clk = clk_register_mux(NULL, "firda_mux_clk", firda_parents,
+                        ARRAY_SIZE(firda_parents), 0, PERIP_CLK_CFG,
+                        FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0, &_lock);
+        clk_register_clkdev(clk, "firda_mux_clk", NULL);
+
+        clk = clk_register_gate(NULL, "firda_clk", "firda_mux_clk", 0,
+                        PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, NULL, "firda");
+
+        /* gpt clocks */
+        clk_register_gpt("gpt0_synth_clk", "pll1_clk", 0, PRSC0_CLK_CFG,
+                        gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
+        clk = clk_register_mux(NULL, "gpt0_clk", gpt0_parents,
+                        ARRAY_SIZE(gpt0_parents), 0, PERIP_CLK_CFG,
+                        GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
+        clk_register_clkdev(clk, NULL, "gpt0");
+
+        clk_register_gpt("gpt1_synth_clk", "pll1_clk", 0, PRSC1_CLK_CFG,
+                        gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
+        clk = clk_register_mux(NULL, "gpt1_mux_clk", gpt1_parents,
+                        ARRAY_SIZE(gpt1_parents), 0, PERIP_CLK_CFG,
+                        GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
+        clk_register_clkdev(clk, "gpt1_mux_clk", NULL);
+        clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mux_clk", 0,
+                        PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, NULL, "gpt1");
+
+        clk_register_gpt("gpt2_synth_clk", "pll1_clk", 0, PRSC2_CLK_CFG,
+                        gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
+        clk = clk_register_mux(NULL, "gpt2_mux_clk", gpt2_parents,
+                        ARRAY_SIZE(gpt2_parents), 0, PERIP_CLK_CFG,
+                        GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
+        clk_register_clkdev(clk, "gpt2_mux_clk", NULL);
+        clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mux_clk", 0,
+                        PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, NULL, "gpt2");
+
+        /* general synths clocks */
+        clk = clk_register_aux("gen0_synth_clk", "gen0_synth_gate_clk",
+                        "pll1_clk", 0, GEN0_CLK_SYNT, NULL, aux_rtbl,
+                        ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
+        clk_register_clkdev(clk, "gen0_synth_clk", NULL);
+        clk_register_clkdev(clk1, "gen0_synth_gate_clk", NULL);
+
+        clk = clk_register_aux("gen1_synth_clk", "gen1_synth_gate_clk",
+                        "pll1_clk", 0, GEN1_CLK_SYNT, NULL, aux_rtbl,
+                        ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
+        clk_register_clkdev(clk, "gen1_synth_clk", NULL);
+        clk_register_clkdev(clk1, "gen1_synth_gate_clk", NULL);
+
+        clk = clk_register_mux(NULL, "gen2_3_parent_clk", gen2_3_parents,
+                        ARRAY_SIZE(gen2_3_parents), 0, CORE_CLK_CFG,
+                        GEN_SYNTH2_3_CLK_SHIFT, GEN_SYNTH2_3_CLK_MASK, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "gen2_3_parent_clk", NULL);
+
+        clk = clk_register_aux("gen2_synth_clk", "gen2_synth_gate_clk",
+                        "gen2_3_parent_clk", 0, GEN2_CLK_SYNT, NULL, aux_rtbl,
+                        ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
+        clk_register_clkdev(clk, "gen2_synth_clk", NULL);
+        clk_register_clkdev(clk1, "gen2_synth_gate_clk", NULL);
+
+        clk = clk_register_aux("gen3_synth_clk", "gen3_synth_gate_clk",
+                        "gen2_3_parent_clk", 0, GEN3_CLK_SYNT, NULL, aux_rtbl,
+                        ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
+        clk_register_clkdev(clk, "gen3_synth_clk", NULL);
+        clk_register_clkdev(clk1, "gen3_synth_gate_clk", NULL);
+
+        /* clock derived from pll3 clk */
+        clk = clk_register_gate(NULL, "usbh_clk", "pll3_48m_clk", 0,
+                        PERIP1_CLK_ENB, USBH_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, "usbh_clk", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "usbh.0_clk", "usbh_clk", 0, 1,
+                        1);
+        clk_register_clkdev(clk, "usbh.0_clk", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "usbh.1_clk", "usbh_clk", 0, 1,
+                        1);
+        clk_register_clkdev(clk, "usbh.1_clk", NULL);
+
+        clk = clk_register_gate(NULL, "usbd_clk", "pll3_48m_clk", 0,
+                        PERIP1_CLK_ENB, USBD_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, NULL, "designware_udc");
+
+        /* clock derived from ahb clk */
+        clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2,
+                        1);
+        clk_register_clkdev(clk, "ahbmult2_clk", NULL);
+
+        clk = clk_register_mux(NULL, "ddr_clk", ddr_parents,
+                        ARRAY_SIZE(ddr_parents), 0, PLL_CLK_CFG, MCTR_CLK_SHIFT,
+                        MCTR_CLK_MASK, 0, &_lock);
+        clk_register_clkdev(clk, "ddr_clk", NULL);
+
+        clk = clk_register_divider(NULL, "apb_clk", "ahb_clk",
+                        CLK_SET_RATE_PARENT, CORE_CLK_CFG, PCLK_RATIO_SHIFT,
+                        PCLK_RATIO_MASK, 0, &_lock);
+        clk_register_clkdev(clk, "apb_clk", NULL);
+
+        clk = clk_register_gate(NULL, "amem_clk", "ahb_clk", 0, AMEM_CLK_CFG,
+                        AMEM_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, "amem_clk", NULL);
+
+        clk = clk_register_gate(NULL, "c3_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
+                        C3_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, NULL, "c3_clk");
+
+        clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
+                        DMA_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, NULL, "fc400000.dma");
+
+        clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
+                        GMAC_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, NULL, "e0800000.eth");
+
+        clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
+                        I2C_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, NULL, "d0180000.i2c");
+
+        clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
+                        JPEG_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, NULL, "jpeg");
+
+        clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
+                        SMI_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, NULL, "fc000000.flash");
+
+        /* clock derived from apb clk */
+        clk = clk_register_gate(NULL, "adc_clk", "apb_clk", 0, PERIP1_CLK_ENB,
+                        ADC_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, NULL, "adc");
+
+        clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0, PERIP1_CLK_ENB,
+                        GPIO_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, NULL, "fc980000.gpio");
+
+        clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, PERIP1_CLK_ENB,
+                        SSP_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, NULL, "d0100000.spi");
+
+        /* RAS clk enable */
+        clk = clk_register_gate(NULL, "ras_ahb_clk", "ahb_clk", 0, RAS_CLK_ENB,
+                        RAS_AHB_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, "ras_ahb_clk", NULL);
+
+        clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0, RAS_CLK_ENB,
+                        RAS_APB_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, "ras_apb_clk", NULL);
+
+        clk = clk_register_gate(NULL, "ras_32k_clk", "osc_32k_clk", 0,
+                        RAS_CLK_ENB, RAS_32K_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, "ras_32k_clk", NULL);
+
+        clk = clk_register_gate(NULL, "ras_24m_clk", "osc_24m_clk", 0,
+                        RAS_CLK_ENB, RAS_24M_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, "ras_24m_clk", NULL);
+
+        clk = clk_register_gate(NULL, "ras_pll1_clk", "pll1_clk", 0,
+                        RAS_CLK_ENB, RAS_PLL1_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, "ras_pll1_clk", NULL);
+
+        clk = clk_register_gate(NULL, "ras_pll2_clk", "pll2_clk", 0,
+                        RAS_CLK_ENB, RAS_PLL2_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, "ras_pll2_clk", NULL);
+
+        clk = clk_register_gate(NULL, "ras_pll3_48m_clk", "pll3_48m_clk", 0,
+                        RAS_CLK_ENB, RAS_48M_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, "ras_pll3_48m_clk", NULL);
+
+        clk = clk_register_gate(NULL, "ras_gen0_synth_gate_clk",
+                        "gen0_synth_gate_clk", 0, RAS_CLK_ENB,
+                        RAS_SYNT0_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, "ras_gen0_synth_gate_clk", NULL);
+
+        clk = clk_register_gate(NULL, "ras_gen1_synth_gate_clk",
+                        "gen1_synth_gate_clk", 0, RAS_CLK_ENB,
+                        RAS_SYNT1_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, "ras_gen1_synth_gate_clk", NULL);
+
+        clk = clk_register_gate(NULL, "ras_gen2_synth_gate_clk",
+                        "gen2_synth_gate_clk", 0, RAS_CLK_ENB,
+                        RAS_SYNT2_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, "ras_gen2_synth_gate_clk", NULL);
+
+        clk = clk_register_gate(NULL, "ras_gen3_synth_gate_clk",
+                        "gen3_synth_gate_clk", 0, RAS_CLK_ENB,
+                        RAS_SYNT3_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, "ras_gen3_synth_gate_clk", NULL);
+
+        if (of_machine_is_compatible("st,spear300"))
+                spear300_clk_init();
+        else if (of_machine_is_compatible("st,spear310"))
+                spear310_clk_init();
+        else if (of_machine_is_compatible("st,spear320"))
+                spear320_clk_init();
+}
diff --git a/drivers/clk/spear/spear6xx_clock.c b/drivers/clk/spear/spear6xx_clock.c
new file mode 100644
index 000000000000..f9a20b382304
--- /dev/null
+++ b/drivers/clk/spear/spear6xx_clock.c
@@ -0,0 +1,342 @@
+/*
+ * SPEAr6xx machines clock framework source file
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/io.h>
+#include <linux/spinlock_types.h>
+#include <mach/misc_regs.h>
+#include "clk.h"
+
+static DEFINE_SPINLOCK(_lock);
+
+#define PLL1_CTR                        (MISC_BASE + 0x008)
+#define PLL1_FRQ                        (MISC_BASE + 0x00C)
+#define PLL2_CTR                        (MISC_BASE + 0x014)
+#define PLL2_FRQ                        (MISC_BASE + 0x018)
+#define PLL_CLK_CFG                     (MISC_BASE + 0x020)
+        /* PLL_CLK_CFG register masks */
+        #define MCTR_CLK_SHIFT          28
+        #define MCTR_CLK_MASK           3
+
+#define CORE_CLK_CFG                    (MISC_BASE + 0x024)
+        /* CORE CLK CFG register masks */
+        #define HCLK_RATIO_SHIFT        10
+        #define HCLK_RATIO_MASK         2
+        #define PCLK_RATIO_SHIFT        8
+        #define PCLK_RATIO_MASK         2
+
+#define PERIP_CLK_CFG                   (MISC_BASE + 0x028)
+        /* PERIP_CLK_CFG register masks */
+        #define CLCD_CLK_SHIFT          2
+        #define CLCD_CLK_MASK           2
+        #define UART_CLK_SHIFT          4
+        #define UART_CLK_MASK           1
+        #define FIRDA_CLK_SHIFT         5
+        #define FIRDA_CLK_MASK          2
+        #define GPT0_CLK_SHIFT          8
+        #define GPT1_CLK_SHIFT          10
+        #define GPT2_CLK_SHIFT          11
+        #define GPT3_CLK_SHIFT          12
+        #define GPT_CLK_MASK            1
+
+#define PERIP1_CLK_ENB                  (MISC_BASE + 0x02C)
+        /* PERIP1_CLK_ENB register masks */
+        #define UART0_CLK_ENB           3
+        #define UART1_CLK_ENB           4
+        #define SSP0_CLK_ENB            5
+        #define SSP1_CLK_ENB            6
+        #define I2C_CLK_ENB             7
+        #define JPEG_CLK_ENB            8
+        #define FSMC_CLK_ENB            9
+        #define FIRDA_CLK_ENB           10
+        #define GPT2_CLK_ENB            11
+        #define GPT3_CLK_ENB            12
+        #define GPIO2_CLK_ENB           13
+        #define SSP2_CLK_ENB            14
+        #define ADC_CLK_ENB             15
+        #define GPT1_CLK_ENB            11
+        #define RTC_CLK_ENB             17
+        #define GPIO1_CLK_ENB           18
+        #define DMA_CLK_ENB             19
+        #define SMI_CLK_ENB             21
+        #define CLCD_CLK_ENB            22
+        #define GMAC_CLK_ENB            23
+        #define USBD_CLK_ENB            24
+        #define USBH0_CLK_ENB           25
+        #define USBH1_CLK_ENB           26
+
+#define PRSC0_CLK_CFG                   (MISC_BASE + 0x044)
+#define PRSC1_CLK_CFG                   (MISC_BASE + 0x048)
+#define PRSC2_CLK_CFG                   (MISC_BASE + 0x04C)
+
+#define CLCD_CLK_SYNT                   (MISC_BASE + 0x05C)
+#define FIRDA_CLK_SYNT                  (MISC_BASE + 0x060)
+#define UART_CLK_SYNT                   (MISC_BASE + 0x064)
+
+/* vco rate configuration table, in ascending order of rates */
+static struct pll_rate_tbl pll_rtbl[] = {
+        {.mode = 0, .m = 0x53, .n = 0x0F, .p = 0x1}, /* vco 332 & pll 166 MHz */
+        {.mode = 0, .m = 0x85, .n = 0x0F, .p = 0x1}, /* vco 532 & pll 266 MHz */
+        {.mode = 0, .m = 0xA6, .n = 0x0F, .p = 0x1}, /* vco 664 & pll 332 MHz */
+};
+
+/* aux rate configuration table, in ascending order of rates */
+static struct aux_rate_tbl aux_rtbl[] = {
+        /* For PLL1 = 332 MHz */
+        {.xscale = 2, .yscale = 8, .eq = 0}, /* 41.5 MHz */
+        {.xscale = 2, .yscale = 4, .eq = 0}, /* 83 MHz */
+        {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
+};
+
+static const char *clcd_parents[] = { "pll3_48m_clk", "clcd_synth_gate_clk", };
+static const char *firda_parents[] = { "pll3_48m_clk", "firda_synth_gate_clk",
+};
+static const char *uart_parents[] = { "pll3_48m_clk", "uart_synth_gate_clk", };
+static const char *gpt0_1_parents[] = { "pll3_48m_clk", "gpt0_1_synth_clk", };
+static const char *gpt2_parents[] = { "pll3_48m_clk", "gpt2_synth_clk", };
+static const char *gpt3_parents[] = { "pll3_48m_clk", "gpt3_synth_clk", };
+static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none",
+        "pll2_clk", };
+
+/* gpt rate configuration table, in ascending order of rates */
+static struct gpt_rate_tbl gpt_rtbl[] = {
+        /* For pll1 = 332 MHz */
+        {.mscale = 4, .nscale = 0}, /* 41.5 MHz */
+        {.mscale = 2, .nscale = 0}, /* 55.3 MHz */
+        {.mscale = 1, .nscale = 0}, /* 83 MHz */
+};
+
+void __init spear6xx_clk_init(void)
+{
+        struct clk *clk, *clk1;
+
+        clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
+        clk_register_clkdev(clk, "apb_pclk", NULL);
+
+        clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
+                        32000);
+        clk_register_clkdev(clk, "osc_32k_clk", NULL);
+
+        clk = clk_register_fixed_rate(NULL, "osc_30m_clk", NULL, CLK_IS_ROOT,
+                        30000000);
+        clk_register_clkdev(clk, "osc_30m_clk", NULL);
+
+        /* clock derived from 32 KHz osc clk */
+        clk = clk_register_gate(NULL, "rtc_spear", "osc_32k_clk", 0,
+                        PERIP1_CLK_ENB, RTC_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, NULL, "rtc-spear");
+
+        /* clock derived from 30 MHz osc clk */
+        clk = clk_register_fixed_rate(NULL, "pll3_48m_clk", "osc_24m_clk", 0,
+                        48000000);
+        clk_register_clkdev(clk, "pll3_48m_clk", NULL);
+
+        clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "osc_30m_clk",
+                        0, PLL1_CTR, PLL1_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl),
+                        &_lock, &clk1, NULL);
+        clk_register_clkdev(clk, "vco1_clk", NULL);
+        clk_register_clkdev(clk1, "pll1_clk", NULL);
+
+        clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL,
+                        "osc_30m_clk", 0, PLL2_CTR, PLL2_FRQ, pll_rtbl,
+                        ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
+        clk_register_clkdev(clk, "vco2_clk", NULL);
+        clk_register_clkdev(clk1, "pll2_clk", NULL);
+
+        clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_30m_clk", 0, 1,
+                        1);
+        clk_register_clkdev(clk, NULL, "wdt");
+
+        /* clock derived from pll1 clk */
+        clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", 0, 1, 1);
+        clk_register_clkdev(clk, "cpu_clk", NULL);
+
+        clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk",
+                        CLK_SET_RATE_PARENT, CORE_CLK_CFG, HCLK_RATIO_SHIFT,
+                        HCLK_RATIO_MASK, 0, &_lock);
+        clk_register_clkdev(clk, "ahb_clk", NULL);
+
+        clk = clk_register_aux("uart_synth_clk", "uart_synth_gate_clk",
+                        "pll1_clk", 0, UART_CLK_SYNT, NULL, aux_rtbl,
+                        ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
+        clk_register_clkdev(clk, "uart_synth_clk", NULL);
+        clk_register_clkdev(clk1, "uart_synth_gate_clk", NULL);
+
+        clk = clk_register_mux(NULL, "uart_mux_clk", uart_parents,
+                        ARRAY_SIZE(uart_parents), 0, PERIP_CLK_CFG,
+                        UART_CLK_SHIFT, UART_CLK_MASK, 0, &_lock);
+        clk_register_clkdev(clk, "uart_mux_clk", NULL);
+
+        clk = clk_register_gate(NULL, "uart0", "uart_mux_clk", 0,
+                        PERIP1_CLK_ENB, UART0_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, NULL, "d0000000.serial");
+
+        clk = clk_register_gate(NULL, "uart1", "uart_mux_clk", 0,
+                        PERIP1_CLK_ENB, UART1_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, NULL, "d0080000.serial");
+
+        clk = clk_register_aux("firda_synth_clk", "firda_synth_gate_clk",
+                        "pll1_clk", 0, FIRDA_CLK_SYNT, NULL, aux_rtbl,
+                        ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
+        clk_register_clkdev(clk, "firda_synth_clk", NULL);
+        clk_register_clkdev(clk1, "firda_synth_gate_clk", NULL);
+
+        clk = clk_register_mux(NULL, "firda_mux_clk", firda_parents,
+                        ARRAY_SIZE(firda_parents), 0, PERIP_CLK_CFG,
+                        FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0, &_lock);
+        clk_register_clkdev(clk, "firda_mux_clk", NULL);
+
+        clk = clk_register_gate(NULL, "firda_clk", "firda_mux_clk", 0,
+                        PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, NULL, "firda");
+
+        clk = clk_register_aux("clcd_synth_clk", "clcd_synth_gate_clk",
+                        "pll1_clk", 0, CLCD_CLK_SYNT, NULL, aux_rtbl,
+                        ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
+        clk_register_clkdev(clk, "clcd_synth_clk", NULL);
+        clk_register_clkdev(clk1, "clcd_synth_gate_clk", NULL);
+
+        clk = clk_register_mux(NULL, "clcd_mux_clk", clcd_parents,
+                        ARRAY_SIZE(clcd_parents), 0, PERIP_CLK_CFG,
+                        CLCD_CLK_SHIFT, CLCD_CLK_MASK, 0, &_lock);
+        clk_register_clkdev(clk, "clcd_mux_clk", NULL);
+
+        clk = clk_register_gate(NULL, "clcd_clk", "clcd_mux_clk", 0,
+                        PERIP1_CLK_ENB, CLCD_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, NULL, "clcd");
+
+        /* gpt clocks */
+        clk = clk_register_gpt("gpt0_1_synth_clk", "pll1_clk", 0, PRSC0_CLK_CFG,
+                        gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
+        clk_register_clkdev(clk, "gpt0_1_synth_clk", NULL);
+
+        clk = clk_register_mux(NULL, "gpt0_mux_clk", gpt0_1_parents,
+                        ARRAY_SIZE(gpt0_1_parents), 0, PERIP_CLK_CFG,
+                        GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
+        clk_register_clkdev(clk, NULL, "gpt0");
+
+        clk = clk_register_mux(NULL, "gpt1_mux_clk", gpt0_1_parents,
+                        ARRAY_SIZE(gpt0_1_parents), 0, PERIP_CLK_CFG,
+                        GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
+        clk_register_clkdev(clk, "gpt1_mux_clk", NULL);
+
+        clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mux_clk", 0,
+                        PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, NULL, "gpt1");
+
+        clk = clk_register_gpt("gpt2_synth_clk", "pll1_clk", 0, PRSC1_CLK_CFG,
+                        gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
+        clk_register_clkdev(clk, "gpt2_synth_clk", NULL);
+
+        clk = clk_register_mux(NULL, "gpt2_mux_clk", gpt2_parents,
+                        ARRAY_SIZE(gpt2_parents), 0, PERIP_CLK_CFG,
+                        GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
+        clk_register_clkdev(clk, "gpt2_mux_clk", NULL);
+
+        clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mux_clk", 0,
+                        PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, NULL, "gpt2");
+
+        clk = clk_register_gpt("gpt3_synth_clk", "pll1_clk", 0, PRSC2_CLK_CFG,
+                        gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
+        clk_register_clkdev(clk, "gpt3_synth_clk", NULL);
+
+        clk = clk_register_mux(NULL, "gpt3_mux_clk", gpt3_parents,
+                        ARRAY_SIZE(gpt3_parents), 0, PERIP_CLK_CFG,
+                        GPT3_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
+        clk_register_clkdev(clk, "gpt3_mux_clk", NULL);
+
+        clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mux_clk", 0,
+                        PERIP1_CLK_ENB, GPT3_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, NULL, "gpt3");
+
+        /* clock derived from pll3 clk */
+        clk = clk_register_gate(NULL, "usbh0_clk", "pll3_48m_clk", 0,
+                        PERIP1_CLK_ENB, USBH0_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, NULL, "usbh.0_clk");
+
+        clk = clk_register_gate(NULL, "usbh1_clk", "pll3_48m_clk", 0,
+                        PERIP1_CLK_ENB, USBH1_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, NULL, "usbh.1_clk");
+
+        clk = clk_register_gate(NULL, "usbd_clk", "pll3_48m_clk", 0,
+                        PERIP1_CLK_ENB, USBD_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, NULL, "designware_udc");
+
+        /* clock derived from ahb clk */
+        clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2,
+                        1);
+        clk_register_clkdev(clk, "ahbmult2_clk", NULL);
+
+        clk = clk_register_mux(NULL, "ddr_clk", ddr_parents,
+                        ARRAY_SIZE(ddr_parents),
+                        0, PLL_CLK_CFG, MCTR_CLK_SHIFT, MCTR_CLK_MASK, 0,
+                        &_lock);
+        clk_register_clkdev(clk, "ddr_clk", NULL);
+
+        clk = clk_register_divider(NULL, "apb_clk", "ahb_clk",
+                        CLK_SET_RATE_PARENT, CORE_CLK_CFG, PCLK_RATIO_SHIFT,
+                        PCLK_RATIO_MASK, 0, &_lock);
+        clk_register_clkdev(clk, "apb_clk", NULL);
+
+        clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
+                        DMA_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, NULL, "fc400000.dma");
+
+        clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
+                        FSMC_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, NULL, "d1800000.flash");
+
+        clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
+                        GMAC_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, NULL, "gmac");
+
+        clk = clk_register_gate(NULL, "i2c_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
+                        I2C_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, NULL, "d0200000.i2c");
+
+        clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
+                        JPEG_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, NULL, "jpeg");
+
+        clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
+                        SMI_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, NULL, "fc000000.flash");
+
+        /* clock derived from apb clk */
+        clk = clk_register_gate(NULL, "adc_clk", "apb_clk", 0, PERIP1_CLK_ENB,
+                        ADC_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, NULL, "adc");
+
+        clk = clk_register_fixed_factor(NULL, "gpio0_clk", "apb_clk", 0, 1, 1);
+        clk_register_clkdev(clk, NULL, "f0100000.gpio");
+
+        clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0, PERIP1_CLK_ENB,
+                        GPIO1_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, NULL, "fc980000.gpio");
+
+        clk = clk_register_gate(NULL, "gpio2_clk", "apb_clk", 0, PERIP1_CLK_ENB,
+                        GPIO2_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, NULL, "d8100000.gpio");
+
+        clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, PERIP1_CLK_ENB,
+                        SSP0_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, NULL, "ssp-pl022.0");
+
+        clk = clk_register_gate(NULL, "ssp1_clk", "apb_clk", 0, PERIP1_CLK_ENB,
+                        SSP1_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, NULL, "ssp-pl022.1");
+
+        clk = clk_register_gate(NULL, "ssp2_clk", "apb_clk", 0, PERIP1_CLK_ENB,
+                        SSP2_CLK_ENB, 0, &_lock);
+        clk_register_clkdev(clk, NULL, "ssp-pl022.2");
+}
diff --git a/drivers/of/address.c b/drivers/of/address.c
index 66d96f14c274..7e262a6124c5 100644
--- a/drivers/of/address.c
+++ b/drivers/of/address.c
@@ -1,4 +1,5 @@
 
+#include <linux/device.h>
 #include <linux/io.h>
 #include <linux/ioport.h>
 #include <linux/module.h>
diff --git a/drivers/of/base.c b/drivers/of/base.c
index 580644986945..d9bfd49b1935 100644
--- a/drivers/of/base.c
+++ b/drivers/of/base.c
@@ -1260,3 +1260,44 @@ int of_alias_get_id(struct device_node *np, const char *stem)
         return id;
 }
 EXPORT_SYMBOL_GPL(of_alias_get_id);
+
+const __be32 *of_prop_next_u32(struct property *prop, const __be32 *cur,
+                               u32 *pu)
+{
+        const void *curv = cur;
+
+        if (!prop)
+                return NULL;
+
+        if (!cur) {
+                curv = prop->value;
+                goto out_val;
+        }
+
+        curv += sizeof(*cur);
+        if (curv >= prop->value + prop->length)
+                return NULL;
+
+out_val:
+        *pu = be32_to_cpup(curv);
+        return curv;
+}
+EXPORT_SYMBOL_GPL(of_prop_next_u32);
+
+const char *of_prop_next_string(struct property *prop, const char *cur)
+{
+        const void *curv = cur;
+
+        if (!prop)
+                return NULL;
+
+        if (!cur)
+                return prop->value;
+
+        curv += strlen(cur) + 1;
+        if (curv >= prop->value + prop->length)
+                return NULL;
+
+        return curv;
+}
+EXPORT_SYMBOL_GPL(of_prop_next_string);
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index abfb96408779..a54a93112cba 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -4,7 +4,6 @@
 
 config PINCTRL
         bool
-        depends on EXPERIMENTAL
 
 if PINCTRL
 
@@ -27,6 +26,19 @@ config DEBUG_PINCTRL
         help
           Say Y here to add some extra checks and diagnostics to PINCTRL calls.
 
+config PINCTRL_IMX
+        bool
+        select PINMUX
+        select PINCONF
+
+config PINCTRL_IMX6Q
+        bool "IMX6Q pinctrl driver"
+        depends on OF
+        depends on SOC_IMX6Q
+        select PINCTRL_IMX
+        help
+          Say Y here to enable the imx6q pinctrl driver
+
 config PINCTRL_PXA3xx
         bool
         select PINMUX
@@ -37,6 +49,21 @@ config PINCTRL_MMP2
         select PINCTRL_PXA3xx
         select PINCONF
 
+config PINCTRL_MXS
+        bool
+
+config PINCTRL_IMX23
+        bool
+        select PINMUX
+        select PINCONF
+        select PINCTRL_MXS
+
+config PINCTRL_IMX28
+        bool
+        select PINMUX
+        select PINCONF
+        select PINCTRL_MXS
+
 config PINCTRL_PXA168
         bool "PXA168 pin controller driver"
         depends on ARCH_MMP
@@ -84,6 +111,8 @@ config PINCTRL_COH901
           COH 901 335 and COH 901 571/3. They contain 3, 5 or 7
           ports of 8 GPIO pins each.
 
+source "drivers/pinctrl/spear/Kconfig"
+
 endmenu
 
 endif
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 6d4150b4eced..c9b0be56ff49 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -5,9 +5,17 @@ ccflags-$(CONFIG_DEBUG_PINCTRL)	+= -DDEBUG
 obj-$(CONFIG_PINCTRL)           += core.o
 obj-$(CONFIG_PINMUX)            += pinmux.o
 obj-$(CONFIG_PINCONF)           += pinconf.o
+ifeq ($(CONFIG_OF),y)
+obj-$(CONFIG_PINCTRL)           += devicetree.o
+endif
 obj-$(CONFIG_GENERIC_PINCONF)   += pinconf-generic.o
+obj-$(CONFIG_PINCTRL_IMX)       += pinctrl-imx.o
+obj-$(CONFIG_PINCTRL_IMX6Q)     += pinctrl-imx6q.o
 obj-$(CONFIG_PINCTRL_PXA3xx)    += pinctrl-pxa3xx.o
 obj-$(CONFIG_PINCTRL_MMP2)      += pinctrl-mmp2.o
+obj-$(CONFIG_PINCTRL_MXS)       += pinctrl-mxs.o
+obj-$(CONFIG_PINCTRL_IMX23)     += pinctrl-imx23.o
+obj-$(CONFIG_PINCTRL_IMX28)     += pinctrl-imx28.o
 obj-$(CONFIG_PINCTRL_PXA168)    += pinctrl-pxa168.o
 obj-$(CONFIG_PINCTRL_PXA910)    += pinctrl-pxa910.o
 obj-$(CONFIG_PINCTRL_SIRF)      += pinctrl-sirf.o
@@ -16,3 +24,5 @@ obj-$(CONFIG_PINCTRL_TEGRA20)	+= pinctrl-tegra20.o
 obj-$(CONFIG_PINCTRL_TEGRA30)   += pinctrl-tegra30.o
 obj-$(CONFIG_PINCTRL_U300)      += pinctrl-u300.o
 obj-$(CONFIG_PINCTRL_COH901)    += pinctrl-coh901.o
+
+obj-$(CONFIG_PLAT_SPEAR)        += spear/
diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c
index df6296c5f47b..c3b331b74fa0 100644
--- a/drivers/pinctrl/core.c
+++ b/drivers/pinctrl/core.c
@@ -23,9 +23,11 @@
 #include <linux/sysfs.h>
 #include <linux/debugfs.h>
 #include <linux/seq_file.h>
+#include <linux/pinctrl/consumer.h>
 #include <linux/pinctrl/pinctrl.h>
 #include <linux/pinctrl/machine.h>
 #include "core.h"
+#include "devicetree.h"
 #include "pinmux.h"
 #include "pinconf.h"
 
@@ -41,11 +43,13 @@ struct pinctrl_maps {
         unsigned num_maps;
 };
 
+static bool pinctrl_dummy_state;
+
 /* Mutex taken by all entry points */
 DEFINE_MUTEX(pinctrl_mutex);
 
 /* Global list of pin control devices (struct pinctrl_dev) */
-static LIST_HEAD(pinctrldev_list);
+LIST_HEAD(pinctrldev_list);
 
 /* List of pin controller handles (struct pinctrl) */
 static LIST_HEAD(pinctrl_list);
@@ -59,6 +63,19 @@ static LIST_HEAD(pinctrl_maps);
                         _i_ < _maps_node_->num_maps; \
                         i++, _map_ = &_maps_node_->maps[_i_])
 
+/**
+ * pinctrl_provide_dummies() - indicate if pinctrl provides dummy state support
+ *
+ * Usually this function is called by platforms without pinctrl driver support
+ * but run with some shared drivers using pinctrl APIs.
+ * After calling this function, the pinctrl core will return successfully
+ * with creating a dummy state for the driver to keep going smoothly.
+ */
+void pinctrl_provide_dummies(void)
+{
+        pinctrl_dummy_state = true;
+}
+
 const char *pinctrl_dev_get_name(struct pinctrl_dev *pctldev)
 {
         /* We're not allowed to register devices without name */
@@ -124,6 +141,25 @@ int pin_get_from_name(struct pinctrl_dev *pctldev, const char *name)
 }
 
 /**
+ * pin_get_name_from_id() - look up a pin name from a pin id
+ * @pctldev: the pin control device to lookup the pin on
+ * @name: the name of the pin to look up
+ */
+const char *pin_get_name(struct pinctrl_dev *pctldev, const unsigned pin)
+{
+        const struct pin_desc *desc;
+
+        desc = pin_desc_get(pctldev, pin);
+        if (desc == NULL) {
+                dev_err(pctldev->dev, "failed to get pin(%d) name\n",
+                        pin);
+                return NULL;
+        }
+
+        return desc->name;
+}
+
+/**
  * pin_is_valid() - check if pin exists on controller
  * @pctldev: the pin control device to check the pin on
  * @pin: pin to check, use the local pin controller index number
@@ -255,7 +291,8 @@ pinctrl_match_gpio_range(struct pinctrl_dev *pctldev, unsigned gpio)
  *
  * Find the pin controller handling a certain GPIO pin from the pinspace of
  * the GPIO subsystem, return the device and the matching GPIO range. Returns
- * negative if the GPIO range could not be found in any device.
+ * -EPROBE_DEFER if the GPIO range could not be found in any device since it
+ * may still have not been registered.
  */
 static int pinctrl_get_device_gpio_range(unsigned gpio,
                                          struct pinctrl_dev **outdev,
@@ -275,7 +312,7 @@ static int pinctrl_get_device_gpio_range(unsigned gpio,
                 }
         }
 
-        return -EINVAL;
+        return -EPROBE_DEFER;
 }
 
 /**
@@ -318,9 +355,10 @@ int pinctrl_get_group_selector(struct pinctrl_dev *pctldev,
                                const char *pin_group)
 {
         const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
+        unsigned ngroups = pctlops->get_groups_count(pctldev);
         unsigned group_selector = 0;
 
-        while (pctlops->list_groups(pctldev, group_selector) >= 0) {
+        while (group_selector < ngroups) {
                 const char *gname = pctlops->get_group_name(pctldev,
                                                             group_selector);
                 if (!strcmp(gname, pin_group)) {
@@ -360,7 +398,7 @@ int pinctrl_request_gpio(unsigned gpio)
         ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range);
         if (ret) {
                 mutex_unlock(&pinctrl_mutex);
-                return -EINVAL;
+                return ret;
         }
 
         /* Convert to the pin controllers number space */
@@ -516,11 +554,14 @@ static int add_setting(struct pinctrl *p, struct pinctrl_map const *map)
 
         setting->pctldev = get_pinctrl_dev_from_devname(map->ctrl_dev_name);
         if (setting->pctldev == NULL) {
-                dev_err(p->dev, "unknown pinctrl device %s in map entry",
+                dev_info(p->dev, "unknown pinctrl device %s in map entry, deferring probe",
                         map->ctrl_dev_name);
                 kfree(setting);
-                /* Eventually, this should trigger deferred probe */
-                return -ENODEV;
+                /*
+                 * OK let us guess that the driver is not there yet, and
+                 * let's defer obtaining this pinctrl handle to later...
+                 */
+                return -EPROBE_DEFER;
         }
 
         switch (map->type) {
@@ -579,6 +620,13 @@ static struct pinctrl *create_pinctrl(struct device *dev)
         }
         p->dev = dev;
         INIT_LIST_HEAD(&p->states);
+        INIT_LIST_HEAD(&p->dt_maps);
+
+        ret = pinctrl_dt_to_map(p);
+        if (ret < 0) {
+                kfree(p);
+                return ERR_PTR(ret);
+        }
 
         devname = dev_name(dev);
 
@@ -662,6 +710,8 @@ static void pinctrl_put_locked(struct pinctrl *p, bool inlist)
                 kfree(state);
         }
 
+        pinctrl_dt_free_maps(p);
+
         if (inlist)
                 list_del(&p->node);
         kfree(p);
@@ -685,8 +735,18 @@ static struct pinctrl_state *pinctrl_lookup_state_locked(struct pinctrl *p,
         struct pinctrl_state *state;
 
         state = find_state(p, name);
-        if (!state)
-                return ERR_PTR(-ENODEV);
+        if (!state) {
+                if (pinctrl_dummy_state) {
+                        /* create dummy state */
+                        dev_dbg(p->dev, "using pinctrl dummy state (%s)\n",
+                                name);
+                        state = create_state(p, name);
+                        if (IS_ERR(state))
+                                return state;
+                } else {
+                        return ERR_PTR(-ENODEV);
+                }
+        }
 
         return state;
 }
@@ -787,15 +847,63 @@ int pinctrl_select_state(struct pinctrl *p, struct pinctrl_state *state)
 }
 EXPORT_SYMBOL_GPL(pinctrl_select_state);
 
+static void devm_pinctrl_release(struct device *dev, void *res)
+{
+        pinctrl_put(*(struct pinctrl **)res);
+}
+
 /**
- * pinctrl_register_mappings() - register a set of pin controller mappings
- * @maps: the pincontrol mappings table to register. This should probably be
- *      marked with __initdata so it can be discarded after boot. This
- *      function will perform a shallow copy for the mapping entries.
- * @num_maps: the number of maps in the mapping table
+ * struct devm_pinctrl_get() - Resource managed pinctrl_get()
+ * @dev: the device to obtain the handle for
+ *
+ * If there is a need to explicitly destroy the returned struct pinctrl,
+ * devm_pinctrl_put() should be used, rather than plain pinctrl_put().
  */
-int pinctrl_register_mappings(struct pinctrl_map const *maps,
-                              unsigned num_maps)
+struct pinctrl *devm_pinctrl_get(struct device *dev)
+{
+        struct pinctrl **ptr, *p;
+
+        ptr = devres_alloc(devm_pinctrl_release, sizeof(*ptr), GFP_KERNEL);
+        if (!ptr)
+                return ERR_PTR(-ENOMEM);
+
+        p = pinctrl_get(dev);
+        if (!IS_ERR(p)) {
+                *ptr = p;
+                devres_add(dev, ptr);
+        } else {
+                devres_free(ptr);
+        }
+
+        return p;
+}
+EXPORT_SYMBOL_GPL(devm_pinctrl_get);
+
+static int devm_pinctrl_match(struct device *dev, void *res, void *data)
+{
+        struct pinctrl **p = res;
+
+        return *p == data;
+}
+
+/**
+ * devm_pinctrl_put() - Resource managed pinctrl_put()
+ * @p: the pinctrl handle to release
+ *
+ * Deallocate a struct pinctrl obtained via devm_pinctrl_get(). Normally
+ * this function will not need to be called and the resource management
+ * code will ensure that the resource is freed.
+ */
+void devm_pinctrl_put(struct pinctrl *p)
+{
+        WARN_ON(devres_destroy(p->dev, devm_pinctrl_release,
+                               devm_pinctrl_match, p));
+        pinctrl_put(p);
+}
+EXPORT_SYMBOL_GPL(devm_pinctrl_put);
+
+int pinctrl_register_map(struct pinctrl_map const *maps, unsigned num_maps,
+                         bool dup, bool locked)
 {
         int i, ret;
         struct pinctrl_maps *maps_node;
@@ -829,13 +937,13 @@ int pinctrl_register_mappings(struct pinctrl_map const *maps,
                 case PIN_MAP_TYPE_MUX_GROUP:
                         ret = pinmux_validate_map(&maps[i], i);
                         if (ret < 0)
-                                return 0;
+                                return ret;
                         break;
                 case PIN_MAP_TYPE_CONFIGS_PIN:
                 case PIN_MAP_TYPE_CONFIGS_GROUP:
                         ret = pinconf_validate_map(&maps[i], i);
                         if (ret < 0)
-                                return 0;
+                                return ret;
                         break;
                 default:
                         pr_err("failed to register map %s (%d): invalid type given\n",
@@ -851,20 +959,52 @@ int pinctrl_register_mappings(struct pinctrl_map const *maps,
         }
 
         maps_node->num_maps = num_maps;
-        maps_node->maps = kmemdup(maps, sizeof(*maps) * num_maps, GFP_KERNEL);
-        if (!maps_node->maps) {
-                pr_err("failed to duplicate mapping table\n");
-                kfree(maps_node);
-                return -ENOMEM;
+        if (dup) {
+                maps_node->maps = kmemdup(maps, sizeof(*maps) * num_maps,
+                                          GFP_KERNEL);
+                if (!maps_node->maps) {
+                        pr_err("failed to duplicate mapping table\n");
+                        kfree(maps_node);
+                        return -ENOMEM;
+                }
+        } else {
+                maps_node->maps = maps;
         }
 
-        mutex_lock(&pinctrl_mutex);
+        if (!locked)
+                mutex_lock(&pinctrl_mutex);
         list_add_tail(&maps_node->node, &pinctrl_maps);
-        mutex_unlock(&pinctrl_mutex);
+        if (!locked)
+                mutex_unlock(&pinctrl_mutex);
 
         return 0;
 }
 
+/**
+ * pinctrl_register_mappings() - register a set of pin controller mappings
+ * @maps: the pincontrol mappings table to register. This should probably be
+ *      marked with __initdata so it can be discarded after boot. This
+ *      function will perform a shallow copy for the mapping entries.
+ * @num_maps: the number of maps in the mapping table
+ */
+int pinctrl_register_mappings(struct pinctrl_map const *maps,
+                              unsigned num_maps)
+{
+        return pinctrl_register_map(maps, num_maps, true, false);
+}
+
+void pinctrl_unregister_map(struct pinctrl_map const *map)
+{
+        struct pinctrl_maps *maps_node;
+
+        list_for_each_entry(maps_node, &pinctrl_maps, node) {
+                if (maps_node->maps == map) {
+                        list_del(&maps_node->node);
+                        return;
+                }
+        }
+}
+
 #ifdef CONFIG_DEBUG_FS
 
 static int pinctrl_pins_show(struct seq_file *s, void *what)
@@ -906,15 +1046,17 @@ static int pinctrl_groups_show(struct seq_file *s, void *what)
 {
         struct pinctrl_dev *pctldev = s->private;
         const struct pinctrl_ops *ops = pctldev->desc->pctlops;
-        unsigned selector = 0;
+        unsigned ngroups, selector = 0;
 
+        ngroups = ops->get_groups_count(pctldev);
         mutex_lock(&pinctrl_mutex);
 
         seq_puts(s, "registered pin groups:\n");
-        while (ops->list_groups(pctldev, selector) >= 0) {
+        while (selector < ngroups) {
                 const unsigned *pins;
                 unsigned num_pins;
                 const char *gname = ops->get_group_name(pctldev, selector);
+                const char *pname;
                 int ret;
                 int i;
 
@@ -924,10 +1066,14 @@ static int pinctrl_groups_show(struct seq_file *s, void *what)
                         seq_printf(s, "%s [ERROR GETTING PINS]\n",
                                    gname);
                 else {
-                        seq_printf(s, "group: %s, pins = [ ", gname);
-                        for (i = 0; i < num_pins; i++)
-                                seq_printf(s, "%d ", pins[i]);
-                        seq_puts(s, "]\n");
+                        seq_printf(s, "group: %s\n", gname);
+                        for (i = 0; i < num_pins; i++) {
+                                pname = pin_get_name(pctldev, pins[i]);
+                                if (WARN_ON(!pname))
+                                        return -EINVAL;
+                                seq_printf(s, "pin %d (%s)\n", pins[i], pname);
+                        }
+                        seq_puts(s, "\n");
                 }
                 selector++;
         }
@@ -1226,11 +1372,14 @@ static int pinctrl_check_ops(struct pinctrl_dev *pctldev)
         const struct pinctrl_ops *ops = pctldev->desc->pctlops;
 
         if (!ops ||
-            !ops->list_groups ||
+            !ops->get_groups_count ||
             !ops->get_group_name ||
             !ops->get_group_pins)
                 return -EINVAL;
 
+        if (ops->dt_node_to_map && !ops->dt_free_map)
+                return -EINVAL;
+
         return 0;
 }
 
@@ -1268,37 +1417,29 @@ struct pinctrl_dev *pinctrl_register(struct pinctrl_desc *pctldesc,
         /* check core ops for sanity */
         ret = pinctrl_check_ops(pctldev);
         if (ret) {
-                pr_err("%s pinctrl ops lacks necessary functions\n",
-                        pctldesc->name);
+                dev_err(dev, "pinctrl ops lacks necessary functions\n");
                 goto out_err;
         }
 
         /* If we're implementing pinmuxing, check the ops for sanity */
         if (pctldesc->pmxops) {
                 ret = pinmux_check_ops(pctldev);
-                if (ret) {
-                        pr_err("%s pinmux ops lacks necessary functions\n",
-                               pctldesc->name);
+                if (ret)
                         goto out_err;
-                }
         }
 
         /* If we're implementing pinconfig, check the ops for sanity */
         if (pctldesc->confops) {
                 ret = pinconf_check_ops(pctldev);
-                if (ret) {
-                        pr_err("%s pin config ops lacks necessary functions\n",
-                               pctldesc->name);
+                if (ret)
                         goto out_err;
-                }
         }
 
         /* Register all the pins */
-        pr_debug("try to register %d pins on %s...\n",
-                 pctldesc->npins, pctldesc->name);
+        dev_dbg(dev, "try to register %d pins ...\n",  pctldesc->npins);
         ret = pinctrl_register_pins(pctldev, pctldesc->pins, pctldesc->npins);
         if (ret) {
-                pr_err("error during pin registration\n");
+                dev_err(dev, "error during pin registration\n");
                 pinctrl_free_pindescs(pctldev, pctldesc->pins,
                                       pctldesc->npins);
                 goto out_err;
@@ -1313,8 +1454,15 @@ struct pinctrl_dev *pinctrl_register(struct pinctrl_desc *pctldesc,
                 struct pinctrl_state *s =
                         pinctrl_lookup_state_locked(pctldev->p,
                                                     PINCTRL_STATE_DEFAULT);
-                if (!IS_ERR(s))
-                        pinctrl_select_state_locked(pctldev->p, s);
+                if (IS_ERR(s)) {
+                        dev_dbg(dev, "failed to lookup the default state\n");
+                } else {
+                        ret = pinctrl_select_state_locked(pctldev->p, s);
+                        if (ret) {
+                                dev_err(dev,
+                                        "failed to select default state\n");
+                        }
+                }
         }
 
         mutex_unlock(&pinctrl_mutex);
diff --git a/drivers/pinctrl/core.h b/drivers/pinctrl/core.h
index 17ecf651b123..1f40ff68a8c4 100644
--- a/drivers/pinctrl/core.h
+++ b/drivers/pinctrl/core.h
@@ -52,12 +52,15 @@ struct pinctrl_dev {
  * @dev: the device using this pin control handle
  * @states: a list of states for this device
  * @state: the current state
+ * @dt_maps: the mapping table chunks dynamically parsed from device tree for
+ *      this device, if any
  */
 struct pinctrl {
         struct list_head node;
         struct device *dev;
         struct list_head states;
         struct pinctrl_state *state;
+        struct list_head dt_maps;
 };
 
 /**
@@ -100,7 +103,8 @@ struct pinctrl_setting_configs {
  * struct pinctrl_setting - an individual mux or config setting
  * @node: list node for struct pinctrl_settings's @settings field
  * @type: the type of setting
- * @pctldev: pin control device handling to be programmed
+ * @pctldev: pin control device handling to be programmed. Not used for
+ *   PIN_MAP_TYPE_DUMMY_STATE.
  * @data: Data specific to the setting type
  */
 struct pinctrl_setting {
@@ -144,6 +148,7 @@ struct pin_desc {
 
 struct pinctrl_dev *get_pinctrl_dev_from_devname(const char *dev_name);
 int pin_get_from_name(struct pinctrl_dev *pctldev, const char *name);
+const char *pin_get_name(struct pinctrl_dev *pctldev, const unsigned pin);
 int pinctrl_get_group_selector(struct pinctrl_dev *pctldev,
                                const char *pin_group);
 
@@ -153,4 +158,9 @@ static inline struct pin_desc *pin_desc_get(struct pinctrl_dev *pctldev,
         return radix_tree_lookup(&pctldev->pin_desc_tree, pin);
 }
 
+int pinctrl_register_map(struct pinctrl_map const *maps, unsigned num_maps,
+                         bool dup, bool locked);
+void pinctrl_unregister_map(struct pinctrl_map const *map);
+
 extern struct mutex pinctrl_mutex;
+extern struct list_head pinctrldev_list;
diff --git a/drivers/pinctrl/devicetree.c b/drivers/pinctrl/devicetree.c
new file mode 100644
index 000000000000..fcb1de45473c
--- /dev/null
+++ b/drivers/pinctrl/devicetree.c
@@ -0,0 +1,249 @@
+/*
+ * Device tree integration for the pin control subsystem
+ *
+ * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/device.h>
+#include <linux/of.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/slab.h>
+
+#include "core.h"
+#include "devicetree.h"
+
+/**
+ * struct pinctrl_dt_map - mapping table chunk parsed from device tree
+ * @node: list node for struct pinctrl's @dt_maps field
+ * @pctldev: the pin controller that allocated this struct, and will free it
+ * @maps: the mapping table entries
+ */
+struct pinctrl_dt_map {
+        struct list_head node;
+        struct pinctrl_dev *pctldev;
+        struct pinctrl_map *map;
+        unsigned num_maps;
+};
+
+static void dt_free_map(struct pinctrl_dev *pctldev,
+                     struct pinctrl_map *map, unsigned num_maps)
+{
+        if (pctldev) {
+                struct pinctrl_ops *ops = pctldev->desc->pctlops;
+                ops->dt_free_map(pctldev, map, num_maps);
+        } else {
+                /* There is no pctldev for PIN_MAP_TYPE_DUMMY_STATE */
+                kfree(map);
+        }
+}
+
+void pinctrl_dt_free_maps(struct pinctrl *p)
+{
+        struct pinctrl_dt_map *dt_map, *n1;
+
+        list_for_each_entry_safe(dt_map, n1, &p->dt_maps, node) {
+                pinctrl_unregister_map(dt_map->map);
+                list_del(&dt_map->node);
+                dt_free_map(dt_map->pctldev, dt_map->map,
+                            dt_map->num_maps);
+                kfree(dt_map);
+        }
+
+        of_node_put(p->dev->of_node);
+}
+
+static int dt_remember_or_free_map(struct pinctrl *p, const char *statename,
+                                   struct pinctrl_dev *pctldev,
+                                   struct pinctrl_map *map, unsigned num_maps)
+{
+        int i;
+        struct pinctrl_dt_map *dt_map;
+
+        /* Initialize common mapping table entry fields */
+        for (i = 0; i < num_maps; i++) {
+                map[i].dev_name = dev_name(p->dev);
+                map[i].name = statename;
+                if (pctldev)
+                        map[i].ctrl_dev_name = dev_name(pctldev->dev);
+        }
+
+        /* Remember the converted mapping table entries */
+        dt_map = kzalloc(sizeof(*dt_map), GFP_KERNEL);
+        if (!dt_map) {
+                dev_err(p->dev, "failed to alloc struct pinctrl_dt_map\n");
+                dt_free_map(pctldev, map, num_maps);
+                return -ENOMEM;
+        }
+
+        dt_map->pctldev = pctldev;
+        dt_map->map = map;
+        dt_map->num_maps = num_maps;
+        list_add_tail(&dt_map->node, &p->dt_maps);
+
+        return pinctrl_register_map(map, num_maps, false, true);
+}
+
+static struct pinctrl_dev *find_pinctrl_by_of_node(struct device_node *np)
+{
+        struct pinctrl_dev *pctldev;
+
+        list_for_each_entry(pctldev, &pinctrldev_list, node)
+                if (pctldev->dev->of_node == np)
+                        return pctldev;
+
+        return NULL;
+}
+
+static int dt_to_map_one_config(struct pinctrl *p, const char *statename,
+                                struct device_node *np_config)
+{
+        struct device_node *np_pctldev;
+        struct pinctrl_dev *pctldev;
+        struct pinctrl_ops *ops;
+        int ret;
+        struct pinctrl_map *map;
+        unsigned num_maps;
+
+        /* Find the pin controller containing np_config */
+        np_pctldev = of_node_get(np_config);
+        for (;;) {
+                np_pctldev = of_get_next_parent(np_pctldev);
+                if (!np_pctldev || of_node_is_root(np_pctldev)) {
+                        dev_info(p->dev, "could not find pctldev for node %s, deferring probe\n",
+                                np_config->full_name);
+                        of_node_put(np_pctldev);
+                        /* OK let's just assume this will appear later then */
+                        return -EPROBE_DEFER;
+                }
+                pctldev = find_pinctrl_by_of_node(np_pctldev);
+                if (pctldev)
+                        break;
+        }
+        of_node_put(np_pctldev);
+
+        /*
+         * Call pinctrl driver to parse device tree node, and
+         * generate mapping table entries
+         */
+        ops = pctldev->desc->pctlops;
+        if (!ops->dt_node_to_map) {
+                dev_err(p->dev, "pctldev %s doesn't support DT\n",
+                        dev_name(pctldev->dev));
+                return -ENODEV;
+        }
+        ret = ops->dt_node_to_map(pctldev, np_config, &map, &num_maps);
+        if (ret < 0)
+                return ret;
+
+        /* Stash the mapping table chunk away for later use */
+        return dt_remember_or_free_map(p, statename, pctldev, map, num_maps);
+}
+
+static int dt_remember_dummy_state(struct pinctrl *p, const char *statename)
+{
+        struct pinctrl_map *map;
+
+        map = kzalloc(sizeof(*map), GFP_KERNEL);
+        if (!map) {
+                dev_err(p->dev, "failed to alloc struct pinctrl_map\n");
+                return -ENOMEM;
+        }
+
+        /* There is no pctldev for PIN_MAP_TYPE_DUMMY_STATE */
+        map->type = PIN_MAP_TYPE_DUMMY_STATE;
+
+        return dt_remember_or_free_map(p, statename, NULL, map, 1);
+}
+
+int pinctrl_dt_to_map(struct pinctrl *p)
+{
+        struct device_node *np = p->dev->of_node;
+        int state, ret;
+        char *propname;
+        struct property *prop;
+        const char *statename;
+        const __be32 *list;
+        int size, config;
+        phandle phandle;
+        struct device_node *np_config;
+
+        /* CONFIG_OF enabled, p->dev not instantiated from DT */
+        if (!np) {
+                dev_dbg(p->dev, "no of_node; not parsing pinctrl DT\n");
+                return 0;
+        }
+
+        /* We may store pointers to property names within the node */
+        of_node_get(np);
+
+        /* For each defined state ID */
+        for (state = 0; ; state++) {
+                /* Retrieve the pinctrl-* property */
+                propname = kasprintf(GFP_KERNEL, "pinctrl-%d", state);
+                prop = of_find_property(np, propname, &size);
+                kfree(propname);
+                if (!prop)
+                        break;
+                list = prop->value;
+                size /= sizeof(*list);
+
+                /* Determine whether pinctrl-names property names the state */
+                ret = of_property_read_string_index(np, "pinctrl-names",
+                                                    state, &statename);
+                /*
+                 * If not, statename is just the integer state ID. But rather
+                 * than dynamically allocate it and have to free it later,
+                 * just point part way into the property name for the string.
+                 */
+                if (ret < 0) {
+                        /* strlen("pinctrl-") == 8 */
+                        statename = prop->name + 8;
+                }
+
+                /* For every referenced pin configuration node in it */
+                for (config = 0; config < size; config++) {
+                        phandle = be32_to_cpup(list++);
+
+                        /* Look up the pin configuration node */
+                        np_config = of_find_node_by_phandle(phandle);
+                        if (!np_config) {
+                                dev_err(p->dev,
+                                        "prop %s index %i invalid phandle\n",
+                                        prop->name, config);
+                                ret = -EINVAL;
+                                goto err;
+                        }
+
+                        /* Parse the node */
+                        ret = dt_to_map_one_config(p, statename, np_config);
+                        of_node_put(np_config);
+                        if (ret < 0)
+                                goto err;
+                }
+
+                /* No entries in DT? Generate a dummy state table entry */
+                if (!size) {
+                        ret = dt_remember_dummy_state(p, statename);
+                        if (ret < 0)
+                                goto err;
+                }
+        }
+
+        return 0;
+
+err:
+        pinctrl_dt_free_maps(p);
+        return ret;
+}
diff --git a/drivers/pinctrl/devicetree.h b/drivers/pinctrl/devicetree.h
new file mode 100644
index 000000000000..760bc4960f58
--- /dev/null
+++ b/drivers/pinctrl/devicetree.h
@@ -0,0 +1,35 @@
+/*
+ * Internal interface to pinctrl device tree integration
+ *
+ * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifdef CONFIG_OF
+
+void pinctrl_dt_free_maps(struct pinctrl *p);
+int pinctrl_dt_to_map(struct pinctrl *p);
+
+#else
+
+static inline int pinctrl_dt_to_map(struct pinctrl *p)
+{
+        return 0;
+}
+
+static inline void pinctrl_dt_free_maps(struct pinctrl *p)
+{
+}
+
+#endif
diff --git a/drivers/pinctrl/pinconf.c b/drivers/pinctrl/pinconf.c
index 7321e8601294..7ce139ef7e64 100644
--- a/drivers/pinctrl/pinconf.c
+++ b/drivers/pinctrl/pinconf.c
@@ -28,11 +28,17 @@ int pinconf_check_ops(struct pinctrl_dev *pctldev)
         const struct pinconf_ops *ops = pctldev->desc->confops;
 
         /* We must be able to read out pin status */
-        if (!ops->pin_config_get && !ops->pin_config_group_get)
+        if (!ops->pin_config_get && !ops->pin_config_group_get) {
+                dev_err(pctldev->dev,
+                        "pinconf must be able to read out pin status\n");
                 return -EINVAL;
+        }
         /* We have to be able to config the pins in SOME way */
-        if (!ops->pin_config_set && !ops->pin_config_group_set)
+        if (!ops->pin_config_set && !ops->pin_config_group_set) {
+                dev_err(pctldev->dev,
+                        "pinconf has to be able to set a pins config\n");
                 return -EINVAL;
+        }
         return 0;
 }
 
@@ -379,8 +385,16 @@ int pinconf_apply_setting(struct pinctrl_setting const *setting)
 
 void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map)
 {
+        struct pinctrl_dev *pctldev;
+        const struct pinconf_ops *confops;
         int i;
 
+        pctldev = get_pinctrl_dev_from_devname(map->ctrl_dev_name);
+        if (pctldev)
+                confops = pctldev->desc->confops;
+        else
+                confops = NULL;
+
         switch (map->type) {
         case PIN_MAP_TYPE_CONFIGS_PIN:
                 seq_printf(s, "pin ");
@@ -394,8 +408,15 @@ void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map)
 
         seq_printf(s, "%s\n", map->data.configs.group_or_pin);
 
-        for (i = 0; i < map->data.configs.num_configs; i++)
-                seq_printf(s, "config %08lx\n", map->data.configs.configs[i]);
+        for (i = 0; i < map->data.configs.num_configs; i++) {
+                seq_printf(s, "config ");
+                if (confops && confops->pin_config_config_dbg_show)
+                        confops->pin_config_config_dbg_show(pctldev, s,
+                                                map->data.configs.configs[i]);
+                else
+                        seq_printf(s, "%08lx", map->data.configs.configs[i]);
+                seq_printf(s, "\n");
+        }
 }
 
 void pinconf_show_setting(struct seq_file *s,
@@ -403,6 +424,7 @@ void pinconf_show_setting(struct seq_file *s,
 {
         struct pinctrl_dev *pctldev = setting->pctldev;
         const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
+        const struct pinconf_ops *confops = pctldev->desc->confops;
         struct pin_desc *desc;
         int i;
 
@@ -428,8 +450,15 @@ void pinconf_show_setting(struct seq_file *s,
          * FIXME: We should really get the pin controler to dump the config
          * values, so they can be decoded to something meaningful.
          */
-        for (i = 0; i < setting->data.configs.num_configs; i++)
-                seq_printf(s, " %08lx", setting->data.configs.configs[i]);
+        for (i = 0; i < setting->data.configs.num_configs; i++) {
+                seq_printf(s, " ");
+                if (confops && confops->pin_config_config_dbg_show)
+                        confops->pin_config_config_dbg_show(pctldev, s,
+                                setting->data.configs.configs[i]);
+                else
+                        seq_printf(s, "%08lx",
+                                   setting->data.configs.configs[i]);
+        }
 
         seq_printf(s, "\n");
 }
@@ -448,10 +477,14 @@ static void pinconf_dump_pin(struct pinctrl_dev *pctldev,
 static int pinconf_pins_show(struct seq_file *s, void *what)
 {
         struct pinctrl_dev *pctldev = s->private;
+        const struct pinconf_ops *ops = pctldev->desc->confops;
         unsigned i, pin;
 
+        if (!ops || !ops->pin_config_get)
+                return 0;
+
         seq_puts(s, "Pin config settings per pin\n");
-        seq_puts(s, "Format: pin (name): pinmux setting array\n");
+        seq_puts(s, "Format: pin (name): configs\n");
 
         mutex_lock(&pinctrl_mutex);
 
@@ -495,17 +528,18 @@ static int pinconf_groups_show(struct seq_file *s, void *what)
         struct pinctrl_dev *pctldev = s->private;
         const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
         const struct pinconf_ops *ops = pctldev->desc->confops;
+        unsigned ngroups = pctlops->get_groups_count(pctldev);
         unsigned selector = 0;
 
         if (!ops || !ops->pin_config_group_get)
                 return 0;
 
         seq_puts(s, "Pin config settings per pin group\n");
-        seq_puts(s, "Format: group (name): pinmux setting array\n");
+        seq_puts(s, "Format: group (name): configs\n");
 
         mutex_lock(&pinctrl_mutex);
 
-        while (pctlops->list_groups(pctldev, selector) >= 0) {
+        while (selector < ngroups) {
                 const char *gname = pctlops->get_group_name(pctldev, selector);
 
                 seq_printf(s, "%u (%s):", selector, gname);
diff --git a/drivers/pinctrl/pinconf.h b/drivers/pinctrl/pinconf.h
index 54510de5e8c6..e3ed8cb072a5 100644
--- a/drivers/pinctrl/pinconf.h
+++ b/drivers/pinctrl/pinconf.h
@@ -19,11 +19,6 @@ int pinconf_map_to_setting(struct pinctrl_map const *map,
                           struct pinctrl_setting *setting);
 void pinconf_free_setting(struct pinctrl_setting const *setting);
 int pinconf_apply_setting(struct pinctrl_setting const *setting);
-void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map);
-void pinconf_show_setting(struct seq_file *s,
-                          struct pinctrl_setting const *setting);
-void pinconf_init_device_debugfs(struct dentry *devroot,
-                                 struct pinctrl_dev *pctldev);
 
 /*
  * You will only be interested in these if you're using PINCONF
@@ -61,6 +56,18 @@ static inline int pinconf_apply_setting(struct pinctrl_setting const *setting)
         return 0;
 }
 
+#endif
+
+#if defined(CONFIG_PINCONF) && defined(CONFIG_DEBUG_FS)
+
+void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map);
+void pinconf_show_setting(struct seq_file *s,
+                          struct pinctrl_setting const *setting);
+void pinconf_init_device_debugfs(struct dentry *devroot,
+                                 struct pinctrl_dev *pctldev);
+
+#else
+
 static inline void pinconf_show_map(struct seq_file *s,
                                     struct pinctrl_map const *map)
 {
diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c
index 0797eba3e33a..55697a5d7482 100644
--- a/drivers/pinctrl/pinctrl-coh901.c
+++ b/drivers/pinctrl/pinctrl-coh901.c
@@ -174,7 +174,7 @@ struct u300_gpio_confdata {
 
 
 /* Initial configuration */
-static const struct __initdata u300_gpio_confdata
+static const struct __initconst u300_gpio_confdata
 bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
         /* Port 0, pins 0-7 */
         {
@@ -255,7 +255,7 @@ bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
         }
 };
 
-static const struct __initdata u300_gpio_confdata
+static const struct __initconst u300_gpio_confdata
 bs365_gpio_config[BS365_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
         /* Port 0, pins 0-7 */
         {
diff --git a/drivers/pinctrl/pinctrl-imx.c b/drivers/pinctrl/pinctrl-imx.c
new file mode 100644
index 000000000000..8faf613ff1b2
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx.c
@@ -0,0 +1,627 @@
+/*
+ * Core driver for the imx pin controller
+ *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012 Linaro Ltd.
+ *
+ * Author: Dong Aisheng <dong.aisheng@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/slab.h>
+
+#include "core.h"
+#include "pinctrl-imx.h"
+
+#define IMX_PMX_DUMP(info, p, m, c, n)          \
+{                                               \
+        int i, j;                               \
+        printk("Format: Pin Mux Config\n");     \
+        for (i = 0; i < n; i++) {               \
+                j = p[i];                       \
+                printk("%s %d 0x%lx\n",         \
+                        info->pins[j].name,     \
+                        m[i], c[i]);            \
+        }                                       \
+}
+
+/* The bits in CONFIG cell defined in binding doc*/
+#define IMX_NO_PAD_CTL  0x80000000      /* no pin config need */
+#define IMX_PAD_SION 0x40000000         /* set SION */
+
+/**
+ * @dev: a pointer back to containing device
+ * @base: the offset to the controller in virtual memory
+ */
+struct imx_pinctrl {
+        struct device *dev;
+        struct pinctrl_dev *pctl;
+        void __iomem *base;
+        const struct imx_pinctrl_soc_info *info;
+};
+
+static const struct imx_pin_reg *imx_find_pin_reg(
+                                const struct imx_pinctrl_soc_info *info,
+                                unsigned pin, bool is_mux, unsigned mux)
+{
+        const struct imx_pin_reg *pin_reg = NULL;
+        int i;
+
+        for (i = 0; i < info->npin_regs; i++) {
+                pin_reg = &info->pin_regs[i];
+                if (pin_reg->pid != pin)
+                        continue;
+                if (!is_mux)
+                        break;
+                else if (pin_reg->mux_mode == (mux & IMX_MUX_MASK))
+                        break;
+        }
+
+        if (!pin_reg) {
+                dev_err(info->dev, "Pin(%s): unable to find pin reg map\n",
+                        info->pins[pin].name);
+                return NULL;
+        }
+
+        return pin_reg;
+}
+
+static const inline struct imx_pin_group *imx_pinctrl_find_group_by_name(
+                                const struct imx_pinctrl_soc_info *info,
+                                const char *name)
+{
+        const struct imx_pin_group *grp = NULL;
+        int i;
+
+        for (i = 0; i < info->ngroups; i++) {
+                if (!strcmp(info->groups[i].name, name)) {
+                        grp = &info->groups[i];
+                        break;
+                }
+        }
+
+        return grp;
+}
+
+static int imx_get_groups_count(struct pinctrl_dev *pctldev)
+{
+        struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+        const struct imx_pinctrl_soc_info *info = ipctl->info;
+
+        return info->ngroups;
+}
+
+static const char *imx_get_group_name(struct pinctrl_dev *pctldev,
+                                       unsigned selector)
+{
+        struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+        const struct imx_pinctrl_soc_info *info = ipctl->info;
+
+        return info->groups[selector].name;
+}
+
+static int imx_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
+                               const unsigned **pins,
+                               unsigned *npins)
+{
+        struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+        const struct imx_pinctrl_soc_info *info = ipctl->info;
+
+        if (selector >= info->ngroups)
+                return -EINVAL;
+
+        *pins = info->groups[selector].pins;
+        *npins = info->groups[selector].npins;
+
+        return 0;
+}
+
+static void imx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
+                   unsigned offset)
+{
+        seq_printf(s, "%s", dev_name(pctldev->dev));
+}
+
+static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
+                        struct device_node *np,
+                        struct pinctrl_map **map, unsigned *num_maps)
+{
+        struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+        const struct imx_pinctrl_soc_info *info = ipctl->info;
+        const struct imx_pin_group *grp;
+        struct pinctrl_map *new_map;
+        struct device_node *parent;
+        int map_num = 1;
+        int i;
+
+        /*
+         * first find the group of this node and check if we need create
+         * config maps for pins
+         */
+        grp = imx_pinctrl_find_group_by_name(info, np->name);
+        if (!grp) {
+                dev_err(info->dev, "unable to find group for node %s\n",
+                        np->name);
+                return -EINVAL;
+        }
+
+        for (i = 0; i < grp->npins; i++) {
+                if (!(grp->configs[i] & IMX_NO_PAD_CTL))
+                        map_num++;
+        }
+
+        new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL);
+        if (!new_map)
+                return -ENOMEM;
+
+        *map = new_map;
+        *num_maps = map_num;
+
+        /* create mux map */
+        parent = of_get_parent(np);
+        if (!parent)
+                return -EINVAL;
+        new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
+        new_map[0].data.mux.function = parent->name;
+        new_map[0].data.mux.group = np->name;
+        of_node_put(parent);
+
+        /* create config map */
+        new_map++;
+        for (i = 0; i < grp->npins; i++) {
+                if (!(grp->configs[i] & IMX_NO_PAD_CTL)) {
+                        new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
+                        new_map[i].data.configs.group_or_pin =
+                                        pin_get_name(pctldev, grp->pins[i]);
+                        new_map[i].data.configs.configs = &grp->configs[i];
+                        new_map[i].data.configs.num_configs = 1;
+                }
+        }
+
+        dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
+                new_map->data.mux.function, new_map->data.mux.group, map_num);
+
+        return 0;
+}
+
+static void imx_dt_free_map(struct pinctrl_dev *pctldev,
+                                struct pinctrl_map *map, unsigned num_maps)
+{
+        int i;
+
+        for (i = 0; i < num_maps; i++)
+                kfree(map);
+}
+
+static struct pinctrl_ops imx_pctrl_ops = {
+        .get_groups_count = imx_get_groups_count,
+        .get_group_name = imx_get_group_name,
+        .get_group_pins = imx_get_group_pins,
+        .pin_dbg_show = imx_pin_dbg_show,
+        .dt_node_to_map = imx_dt_node_to_map,
+        .dt_free_map = imx_dt_free_map,
+
+};
+
+static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
+                           unsigned group)
+{
+        struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+        const struct imx_pinctrl_soc_info *info = ipctl->info;
+        const struct imx_pin_reg *pin_reg;
+        const unsigned *pins, *mux;
+        unsigned int npins, pin_id;
+        int i;
+
+        /*
+         * Configure the mux mode for each pin in the group for a specific
+         * function.
+         */
+        pins = info->groups[group].pins;
+        npins = info->groups[group].npins;
+        mux = info->groups[group].mux_mode;
+
+        WARN_ON(!pins || !npins || !mux);
+
+        dev_dbg(ipctl->dev, "enable function %s group %s\n",
+                info->functions[selector].name, info->groups[group].name);
+
+        for (i = 0; i < npins; i++) {
+                pin_id = pins[i];
+
+                pin_reg = imx_find_pin_reg(info, pin_id, 1, mux[i]);
+                if (!pin_reg)
+                        return -EINVAL;
+
+                if (!pin_reg->mux_reg) {
+                        dev_err(ipctl->dev, "Pin(%s) does not support mux function\n",
+                                info->pins[pin_id].name);
+                        return -EINVAL;
+                }
+
+                writel(mux[i], ipctl->base + pin_reg->mux_reg);
+                dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
+                        pin_reg->mux_reg, mux[i]);
+
+                /* some pins also need select input setting, set it if found */
+                if (pin_reg->input_reg) {
+                        writel(pin_reg->input_val, ipctl->base + pin_reg->input_reg);
+                        dev_dbg(ipctl->dev,
+                                "==>select_input: offset 0x%x val 0x%x\n",
+                                pin_reg->input_reg, pin_reg->input_val);
+                }
+        }
+
+        return 0;
+}
+
+static void imx_pmx_disable(struct pinctrl_dev *pctldev, unsigned func_selector,
+                            unsigned group_selector)
+{
+        /* nothing to do here */
+}
+
+static int imx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
+{
+        struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+        const struct imx_pinctrl_soc_info *info = ipctl->info;
+
+        return info->nfunctions;
+}
+
+static const char *imx_pmx_get_func_name(struct pinctrl_dev *pctldev,
+                                          unsigned selector)
+{
+        struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+        const struct imx_pinctrl_soc_info *info = ipctl->info;
+
+        return info->functions[selector].name;
+}
+
+static int imx_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
+                               const char * const **groups,
+                               unsigned * const num_groups)
+{
+        struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+        const struct imx_pinctrl_soc_info *info = ipctl->info;
+
+        *groups = info->functions[selector].groups;
+        *num_groups = info->functions[selector].num_groups;
+
+        return 0;
+}
+
+static struct pinmux_ops imx_pmx_ops = {
+        .get_functions_count = imx_pmx_get_funcs_count,
+        .get_function_name = imx_pmx_get_func_name,
+        .get_function_groups = imx_pmx_get_groups,
+        .enable = imx_pmx_enable,
+        .disable = imx_pmx_disable,
+};
+
+static int imx_pinconf_get(struct pinctrl_dev *pctldev,
+                             unsigned pin_id, unsigned long *config)
+{
+        struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+        const struct imx_pinctrl_soc_info *info = ipctl->info;
+        const struct imx_pin_reg *pin_reg;
+
+        pin_reg = imx_find_pin_reg(info, pin_id, 0, 0);
+        if (!pin_reg)
+                return -EINVAL;
+
+        if (!pin_reg->conf_reg) {
+                dev_err(info->dev, "Pin(%s) does not support config function\n",
+                        info->pins[pin_id].name);
+                return -EINVAL;
+        }
+
+        *config = readl(ipctl->base + pin_reg->conf_reg);
+
+        return 0;
+}
+
+static int imx_pinconf_set(struct pinctrl_dev *pctldev,
+                             unsigned pin_id, unsigned long config)
+{
+        struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+        const struct imx_pinctrl_soc_info *info = ipctl->info;
+        const struct imx_pin_reg *pin_reg;
+
+        pin_reg = imx_find_pin_reg(info, pin_id, 0, 0);
+        if (!pin_reg)
+                return -EINVAL;
+
+        if (!pin_reg->conf_reg) {
+                dev_err(info->dev, "Pin(%s) does not support config function\n",
+                        info->pins[pin_id].name);
+                return -EINVAL;
+        }
+
+        dev_dbg(ipctl->dev, "pinconf set pin %s\n",
+                info->pins[pin_id].name);
+
+        writel(config, ipctl->base + pin_reg->conf_reg);
+        dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n",
+                pin_reg->conf_reg, config);
+
+        return 0;
+}
+
+static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
+                                   struct seq_file *s, unsigned pin_id)
+{
+        struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+        const struct imx_pinctrl_soc_info *info = ipctl->info;
+        const struct imx_pin_reg *pin_reg;
+        unsigned long config;
+
+        pin_reg = imx_find_pin_reg(info, pin_id, 0, 0);
+        if (!pin_reg || !pin_reg->conf_reg) {
+                seq_printf(s, "N/A");
+                return;
+        }
+
+        config = readl(ipctl->base + pin_reg->conf_reg);
+        seq_printf(s, "0x%lx", config);
+}
+
+static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
+                                         struct seq_file *s, unsigned group)
+{
+        struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+        const struct imx_pinctrl_soc_info *info = ipctl->info;
+        struct imx_pin_group *grp;
+        unsigned long config;
+        const char *name;
+        int i, ret;
+
+        if (group > info->ngroups)
+                return;
+
+        seq_printf(s, "\n");
+        grp = &info->groups[group];
+        for (i = 0; i < grp->npins; i++) {
+                name = pin_get_name(pctldev, grp->pins[i]);
+                ret = imx_pinconf_get(pctldev, grp->pins[i], &config);
+                if (ret)
+                        return;
+                seq_printf(s, "%s: 0x%lx", name, config);
+        }
+}
+
+struct pinconf_ops imx_pinconf_ops = {
+        .pin_config_get = imx_pinconf_get,
+        .pin_config_set = imx_pinconf_set,
+        .pin_config_dbg_show = imx_pinconf_dbg_show,
+        .pin_config_group_dbg_show = imx_pinconf_group_dbg_show,
+};
+
+static struct pinctrl_desc imx_pinctrl_desc = {
+        .pctlops = &imx_pctrl_ops,
+        .pmxops = &imx_pmx_ops,
+        .confops = &imx_pinconf_ops,
+        .owner = THIS_MODULE,
+};
+
+/* decode pin id and mux from pin function id got from device tree*/
+static int imx_pinctrl_get_pin_id_and_mux(const struct imx_pinctrl_soc_info *info,
+                                unsigned int pin_func_id, unsigned int *pin_id,
+                                unsigned int *mux)
+{
+        if (pin_func_id > info->npin_regs)
+                return -EINVAL;
+
+        *pin_id = info->pin_regs[pin_func_id].pid;
+        *mux = info->pin_regs[pin_func_id].mux_mode;
+
+        return 0;
+}
+
+static int __devinit imx_pinctrl_parse_groups(struct device_node *np,
+                                struct imx_pin_group *grp,
+                                struct imx_pinctrl_soc_info *info,
+                                u32 index)
+{
+        unsigned int pin_func_id;
+        int ret, size;
+        const const __be32 *list;
+        int i, j;
+        u32 config;
+
+        dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
+
+        /* Initialise group */
+        grp->name = np->name;
+
+        /*
+         * the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>,
+         * do sanity check and calculate pins number
+         */
+        list = of_get_property(np, "fsl,pins", &size);
+        /* we do not check return since it's safe node passed down */
+        size /= sizeof(*list);
+        if (!size || size % 2) {
+                dev_err(info->dev, "wrong pins number or pins and configs should be pairs\n");
+                return -EINVAL;
+        }
+
+        grp->npins = size / 2;
+        grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
+                                GFP_KERNEL);
+        grp->mux_mode = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
+                                GFP_KERNEL);
+        grp->configs = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned long),
+                                GFP_KERNEL);
+        for (i = 0, j = 0; i < size; i += 2, j++) {
+                pin_func_id = be32_to_cpu(*list++);
+                ret = imx_pinctrl_get_pin_id_and_mux(info, pin_func_id,
+                                        &grp->pins[j], &grp->mux_mode[j]);
+                if (ret) {
+                        dev_err(info->dev, "get invalid pin function id\n");
+                        return -EINVAL;
+                }
+                /* SION bit is in mux register */
+                config = be32_to_cpu(*list++);
+                if (config & IMX_PAD_SION)
+                        grp->mux_mode[j] |= IOMUXC_CONFIG_SION;
+                grp->configs[j] = config & ~IMX_PAD_SION;
+        }
+
+#ifdef DEBUG
+        IMX_PMX_DUMP(info, grp->pins, grp->mux_mode, grp->configs, grp->npins);
+#endif
+        return 0;
+}
+
+static int __devinit imx_pinctrl_parse_functions(struct device_node *np,
+                        struct imx_pinctrl_soc_info *info, u32 index)
+{
+        struct device_node *child;
+        struct imx_pmx_func *func;
+        struct imx_pin_group *grp;
+        int ret;
+        static u32 grp_index;
+        u32 i = 0;
+
+        dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
+
+        func = &info->functions[index];
+
+        /* Initialise function */
+        func->name = np->name;
+        func->num_groups = of_get_child_count(np);
+        if (func->num_groups <= 0) {
+                dev_err(info->dev, "no groups defined\n");
+                return -EINVAL;
+        }
+        func->groups = devm_kzalloc(info->dev,
+                        func->num_groups * sizeof(char *), GFP_KERNEL);
+
+        for_each_child_of_node(np, child) {
+                func->groups[i] = child->name;
+                grp = &info->groups[grp_index++];
+                ret = imx_pinctrl_parse_groups(child, grp, info, i++);
+                if (ret)
+                        return ret;
+        }
+
+        return 0;
+}
+
+static int __devinit imx_pinctrl_probe_dt(struct platform_device *pdev,
+                                struct imx_pinctrl_soc_info *info)
+{
+        struct device_node *np = pdev->dev.of_node;
+        struct device_node *child;
+        int ret;
+        u32 nfuncs = 0;
+        u32 i = 0;
+
+        if (!np)
+                return -ENODEV;
+
+        nfuncs = of_get_child_count(np);
+        if (nfuncs <= 0) {
+                dev_err(&pdev->dev, "no functions defined\n");
+                return -EINVAL;
+        }
+
+        info->nfunctions = nfuncs;
+        info->functions = devm_kzalloc(&pdev->dev, nfuncs * sizeof(struct imx_pmx_func),
+                                        GFP_KERNEL);
+        if (!info->functions)
+                return -ENOMEM;
+
+        info->ngroups = 0;
+        for_each_child_of_node(np, child)
+                info->ngroups += of_get_child_count(child);
+        info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct imx_pin_group),
+                                        GFP_KERNEL);
+        if (!info->groups)
+                return -ENOMEM;
+
+        for_each_child_of_node(np, child) {
+                ret = imx_pinctrl_parse_functions(child, info, i++);
+                if (ret) {
+                        dev_err(&pdev->dev, "failed to parse function\n");
+                        return ret;
+                }
+        }
+
+        return 0;
+}
+
+int __devinit imx_pinctrl_probe(struct platform_device *pdev,
+                                struct imx_pinctrl_soc_info *info)
+{
+        struct imx_pinctrl *ipctl;
+        struct resource *res;
+        int ret;
+
+        if (!info || !info->pins || !info->npins
+                  || !info->pin_regs || !info->npin_regs) {
+                dev_err(&pdev->dev, "wrong pinctrl info\n");
+                return -EINVAL;
+        }
+        info->dev = &pdev->dev;
+
+        /* Create state holders etc for this driver */
+        ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
+        if (!ipctl)
+                return -ENOMEM;
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!res)
+                return -ENOENT;
+
+        ipctl->base = devm_request_and_ioremap(&pdev->dev, res);
+        if (!ipctl->base)
+                return -EBUSY;
+
+        imx_pinctrl_desc.name = dev_name(&pdev->dev);
+        imx_pinctrl_desc.pins = info->pins;
+        imx_pinctrl_desc.npins = info->npins;
+
+        ret = imx_pinctrl_probe_dt(pdev, info);
+        if (ret) {
+                dev_err(&pdev->dev, "fail to probe dt properties\n");
+                return ret;
+        }
+
+        ipctl->info = info;
+        ipctl->dev = info->dev;
+        platform_set_drvdata(pdev, ipctl);
+        ipctl->pctl = pinctrl_register(&imx_pinctrl_desc, &pdev->dev, ipctl);
+        if (!ipctl->pctl) {
+                dev_err(&pdev->dev, "could not register IMX pinctrl driver\n");
+                return -EINVAL;
+        }
+
+        dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");
+
+        return 0;
+}
+
+int __devexit imx_pinctrl_remove(struct platform_device *pdev)
+{
+        struct imx_pinctrl *ipctl = platform_get_drvdata(pdev);
+
+        pinctrl_unregister(ipctl->pctl);
+
+        return 0;
+}
diff --git a/drivers/pinctrl/pinctrl-imx.h b/drivers/pinctrl/pinctrl-imx.h
new file mode 100644
index 000000000000..9b65e7828f1d
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx.h
@@ -0,0 +1,106 @@
+/*
+ * IMX pinmux core definitions
+ *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012 Linaro Ltd.
+ *
+ * Author: Dong Aisheng <dong.aisheng@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DRIVERS_PINCTRL_IMX_H
+#define __DRIVERS_PINCTRL_IMX_H
+
+struct platform_device;
+
+/**
+ * struct imx_pin_group - describes an IMX pin group
+ * @name: the name of this specific pin group
+ * @pins: an array of discrete physical pins used in this group, taken
+ *      from the driver-local pin enumeration space
+ * @npins: the number of pins in this group array, i.e. the number of
+ *      elements in .pins so we can iterate over that array
+ * @mux_mode: the mux mode for each pin in this group. The size of this
+ *      array is the same as pins.
+ * @configs: the config for each pin in this group. The size of this
+ *      array is the same as pins.
+ */
+struct imx_pin_group {
+        const char *name;
+        unsigned int *pins;
+        unsigned npins;
+        unsigned int *mux_mode;
+        unsigned long *configs;
+};
+
+/**
+ * struct imx_pmx_func - describes IMX pinmux functions
+ * @name: the name of this specific function
+ * @groups: corresponding pin groups
+ * @num_groups: the number of groups
+ */
+struct imx_pmx_func {
+        const char *name;
+        const char **groups;
+        unsigned num_groups;
+};
+
+/**
+ * struct imx_pin_reg - describe a pin reg map
+ * The last 3 members are used for select input setting
+ * @pid: pin id
+ * @mux_reg: mux register offset
+ * @conf_reg: config register offset
+ * @mux_mode: mux mode
+ * @input_reg: select input register offset for this mux if any
+ *  0 if no select input setting needed.
+ * @input_val: the value set to select input register
+ */
+struct imx_pin_reg {
+        u16 pid;
+        u16 mux_reg;
+        u16 conf_reg;
+        u8 mux_mode;
+        u16 input_reg;
+        u8 input_val;
+};
+
+struct imx_pinctrl_soc_info {
+        struct device *dev;
+        const struct pinctrl_pin_desc *pins;
+        unsigned int npins;
+        const struct imx_pin_reg *pin_regs;
+        unsigned int npin_regs;
+        struct imx_pin_group *groups;
+        unsigned int ngroups;
+        struct imx_pmx_func *functions;
+        unsigned int nfunctions;
+};
+
+#define NO_MUX          0x0
+#define NO_PAD          0x0
+
+#define IMX_PIN_REG(id, conf, mux, mode, input, val)    \
+        {                                               \
+                .pid = id,                              \
+                .conf_reg = conf,                       \
+                .mux_reg = mux,                         \
+                .mux_mode  = mode,                      \
+                .input_reg = input,                     \
+                .input_val = val,                       \
+        }
+
+#define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
+
+#define PAD_CTL_MASK(len)       ((1 << len) - 1)
+#define IMX_MUX_MASK    0x7
+#define IOMUXC_CONFIG_SION      (0x1 << 4)
+
+int imx_pinctrl_probe(struct platform_device *pdev,
+                        struct imx_pinctrl_soc_info *info);
+int imx_pinctrl_remove(struct platform_device *pdev);
+#endif /* __DRIVERS_PINCTRL_IMX_H */
diff --git a/drivers/pinctrl/pinctrl-imx23.c b/drivers/pinctrl/pinctrl-imx23.c
new file mode 100644
index 000000000000..75d3eff94296
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx23.c
@@ -0,0 +1,305 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include "pinctrl-mxs.h"
+
+enum imx23_pin_enum {
+        GPMI_D00        = PINID(0, 0),
+        GPMI_D01        = PINID(0, 1),
+        GPMI_D02        = PINID(0, 2),
+        GPMI_D03        = PINID(0, 3),
+        GPMI_D04        = PINID(0, 4),
+        GPMI_D05        = PINID(0, 5),
+        GPMI_D06        = PINID(0, 6),
+        GPMI_D07        = PINID(0, 7),
+        GPMI_D08        = PINID(0, 8),
+        GPMI_D09        = PINID(0, 9),
+        GPMI_D10        = PINID(0, 10),
+        GPMI_D11        = PINID(0, 11),
+        GPMI_D12        = PINID(0, 12),
+        GPMI_D13        = PINID(0, 13),
+        GPMI_D14        = PINID(0, 14),
+        GPMI_D15        = PINID(0, 15),
+        GPMI_CLE        = PINID(0, 16),
+        GPMI_ALE        = PINID(0, 17),
+        GPMI_CE2N       = PINID(0, 18),
+        GPMI_RDY0       = PINID(0, 19),
+        GPMI_RDY1       = PINID(0, 20),
+        GPMI_RDY2       = PINID(0, 21),
+        GPMI_RDY3       = PINID(0, 22),
+        GPMI_WPN        = PINID(0, 23),
+        GPMI_WRN        = PINID(0, 24),
+        GPMI_RDN        = PINID(0, 25),
+        AUART1_CTS      = PINID(0, 26),
+        AUART1_RTS      = PINID(0, 27),
+        AUART1_RX       = PINID(0, 28),
+        AUART1_TX       = PINID(0, 29),
+        I2C_SCL         = PINID(0, 30),
+        I2C_SDA         = PINID(0, 31),
+        LCD_D00         = PINID(1, 0),
+        LCD_D01         = PINID(1, 1),
+        LCD_D02         = PINID(1, 2),
+        LCD_D03         = PINID(1, 3),
+        LCD_D04         = PINID(1, 4),
+        LCD_D05         = PINID(1, 5),
+        LCD_D06         = PINID(1, 6),
+        LCD_D07         = PINID(1, 7),
+        LCD_D08         = PINID(1, 8),
+        LCD_D09         = PINID(1, 9),
+        LCD_D10         = PINID(1, 10),
+        LCD_D11         = PINID(1, 11),
+        LCD_D12         = PINID(1, 12),
+        LCD_D13         = PINID(1, 13),
+        LCD_D14         = PINID(1, 14),
+        LCD_D15         = PINID(1, 15),
+        LCD_D16         = PINID(1, 16),
+        LCD_D17         = PINID(1, 17),
+        LCD_RESET       = PINID(1, 18),
+        LCD_RS          = PINID(1, 19),
+        LCD_WR          = PINID(1, 20),
+        LCD_CS          = PINID(1, 21),
+        LCD_DOTCK       = PINID(1, 22),
+        LCD_ENABLE      = PINID(1, 23),
+        LCD_HSYNC       = PINID(1, 24),
+        LCD_VSYNC       = PINID(1, 25),
+        PWM0            = PINID(1, 26),
+        PWM1            = PINID(1, 27),
+        PWM2            = PINID(1, 28),
+        PWM3            = PINID(1, 29),
+        PWM4            = PINID(1, 30),
+        SSP1_CMD        = PINID(2, 0),
+        SSP1_DETECT     = PINID(2, 1),
+        SSP1_DATA0      = PINID(2, 2),
+        SSP1_DATA1      = PINID(2, 3),
+        SSP1_DATA2      = PINID(2, 4),
+        SSP1_DATA3      = PINID(2, 5),
+        SSP1_SCK        = PINID(2, 6),
+        ROTARYA         = PINID(2, 7),
+        ROTARYB         = PINID(2, 8),
+        EMI_A00         = PINID(2, 9),
+        EMI_A01         = PINID(2, 10),
+        EMI_A02         = PINID(2, 11),
+        EMI_A03         = PINID(2, 12),
+        EMI_A04         = PINID(2, 13),
+        EMI_A05         = PINID(2, 14),
+        EMI_A06         = PINID(2, 15),
+        EMI_A07         = PINID(2, 16),
+        EMI_A08         = PINID(2, 17),
+        EMI_A09         = PINID(2, 18),
+        EMI_A10         = PINID(2, 19),
+        EMI_A11         = PINID(2, 20),
+        EMI_A12         = PINID(2, 21),
+        EMI_BA0         = PINID(2, 22),
+        EMI_BA1         = PINID(2, 23),
+        EMI_CASN        = PINID(2, 24),
+        EMI_CE0N        = PINID(2, 25),
+        EMI_CE1N        = PINID(2, 26),
+        GPMI_CE1N       = PINID(2, 27),
+        GPMI_CE0N       = PINID(2, 28),
+        EMI_CKE         = PINID(2, 29),
+        EMI_RASN        = PINID(2, 30),
+        EMI_WEN         = PINID(2, 31),
+        EMI_D00         = PINID(3, 0),
+        EMI_D01         = PINID(3, 1),
+        EMI_D02         = PINID(3, 2),
+        EMI_D03         = PINID(3, 3),
+        EMI_D04         = PINID(3, 4),
+        EMI_D05         = PINID(3, 5),
+        EMI_D06         = PINID(3, 6),
+        EMI_D07         = PINID(3, 7),
+        EMI_D08         = PINID(3, 8),
+        EMI_D09         = PINID(3, 9),
+        EMI_D10         = PINID(3, 10),
+        EMI_D11         = PINID(3, 11),
+        EMI_D12         = PINID(3, 12),
+        EMI_D13         = PINID(3, 13),
+        EMI_D14         = PINID(3, 14),
+        EMI_D15         = PINID(3, 15),
+        EMI_DQM0        = PINID(3, 16),
+        EMI_DQM1        = PINID(3, 17),
+        EMI_DQS0        = PINID(3, 18),
+        EMI_DQS1        = PINID(3, 19),
+        EMI_CLK         = PINID(3, 20),
+        EMI_CLKN        = PINID(3, 21),
+};
+
+static const struct pinctrl_pin_desc imx23_pins[] = {
+        MXS_PINCTRL_PIN(GPMI_D00),
+        MXS_PINCTRL_PIN(GPMI_D01),
+        MXS_PINCTRL_PIN(GPMI_D02),
+        MXS_PINCTRL_PIN(GPMI_D03),
+        MXS_PINCTRL_PIN(GPMI_D04),
+        MXS_PINCTRL_PIN(GPMI_D05),
+        MXS_PINCTRL_PIN(GPMI_D06),
+        MXS_PINCTRL_PIN(GPMI_D07),
+        MXS_PINCTRL_PIN(GPMI_D08),
+        MXS_PINCTRL_PIN(GPMI_D09),
+        MXS_PINCTRL_PIN(GPMI_D10),
+        MXS_PINCTRL_PIN(GPMI_D11),
+        MXS_PINCTRL_PIN(GPMI_D12),
+        MXS_PINCTRL_PIN(GPMI_D13),
+        MXS_PINCTRL_PIN(GPMI_D14),
+        MXS_PINCTRL_PIN(GPMI_D15),
+        MXS_PINCTRL_PIN(GPMI_CLE),
+        MXS_PINCTRL_PIN(GPMI_ALE),
+        MXS_PINCTRL_PIN(GPMI_CE2N),
+        MXS_PINCTRL_PIN(GPMI_RDY0),
+        MXS_PINCTRL_PIN(GPMI_RDY1),
+        MXS_PINCTRL_PIN(GPMI_RDY2),
+        MXS_PINCTRL_PIN(GPMI_RDY3),
+        MXS_PINCTRL_PIN(GPMI_WPN),
+        MXS_PINCTRL_PIN(GPMI_WRN),
+        MXS_PINCTRL_PIN(GPMI_RDN),
+        MXS_PINCTRL_PIN(AUART1_CTS),
+        MXS_PINCTRL_PIN(AUART1_RTS),
+        MXS_PINCTRL_PIN(AUART1_RX),
+        MXS_PINCTRL_PIN(AUART1_TX),
+        MXS_PINCTRL_PIN(I2C_SCL),
+        MXS_PINCTRL_PIN(I2C_SDA),
+        MXS_PINCTRL_PIN(LCD_D00),
+        MXS_PINCTRL_PIN(LCD_D01),
+        MXS_PINCTRL_PIN(LCD_D02),
+        MXS_PINCTRL_PIN(LCD_D03),
+        MXS_PINCTRL_PIN(LCD_D04),
+        MXS_PINCTRL_PIN(LCD_D05),
+        MXS_PINCTRL_PIN(LCD_D06),
+        MXS_PINCTRL_PIN(LCD_D07),
+        MXS_PINCTRL_PIN(LCD_D08),
+        MXS_PINCTRL_PIN(LCD_D09),
+        MXS_PINCTRL_PIN(LCD_D10),
+        MXS_PINCTRL_PIN(LCD_D11),
+        MXS_PINCTRL_PIN(LCD_D12),
+        MXS_PINCTRL_PIN(LCD_D13),
+        MXS_PINCTRL_PIN(LCD_D14),
+        MXS_PINCTRL_PIN(LCD_D15),
+        MXS_PINCTRL_PIN(LCD_D16),
+        MXS_PINCTRL_PIN(LCD_D17),
+        MXS_PINCTRL_PIN(LCD_RESET),
+        MXS_PINCTRL_PIN(LCD_RS),
+        MXS_PINCTRL_PIN(LCD_WR),
+        MXS_PINCTRL_PIN(LCD_CS),
+        MXS_PINCTRL_PIN(LCD_DOTCK),
+        MXS_PINCTRL_PIN(LCD_ENABLE),
+        MXS_PINCTRL_PIN(LCD_HSYNC),
+        MXS_PINCTRL_PIN(LCD_VSYNC),
+        MXS_PINCTRL_PIN(PWM0),
+        MXS_PINCTRL_PIN(PWM1),
+        MXS_PINCTRL_PIN(PWM2),
+        MXS_PINCTRL_PIN(PWM3),
+        MXS_PINCTRL_PIN(PWM4),
+        MXS_PINCTRL_PIN(SSP1_CMD),
+        MXS_PINCTRL_PIN(SSP1_DETECT),
+        MXS_PINCTRL_PIN(SSP1_DATA0),
+        MXS_PINCTRL_PIN(SSP1_DATA1),
+        MXS_PINCTRL_PIN(SSP1_DATA2),
+        MXS_PINCTRL_PIN(SSP1_DATA3),
+        MXS_PINCTRL_PIN(SSP1_SCK),
+        MXS_PINCTRL_PIN(ROTARYA),
+        MXS_PINCTRL_PIN(ROTARYB),
+        MXS_PINCTRL_PIN(EMI_A00),
+        MXS_PINCTRL_PIN(EMI_A01),
+        MXS_PINCTRL_PIN(EMI_A02),
+        MXS_PINCTRL_PIN(EMI_A03),
+        MXS_PINCTRL_PIN(EMI_A04),
+        MXS_PINCTRL_PIN(EMI_A05),
+        MXS_PINCTRL_PIN(EMI_A06),
+        MXS_PINCTRL_PIN(EMI_A07),
+        MXS_PINCTRL_PIN(EMI_A08),
+        MXS_PINCTRL_PIN(EMI_A09),
+        MXS_PINCTRL_PIN(EMI_A10),
+        MXS_PINCTRL_PIN(EMI_A11),
+        MXS_PINCTRL_PIN(EMI_A12),
+        MXS_PINCTRL_PIN(EMI_BA0),
+        MXS_PINCTRL_PIN(EMI_BA1),
+        MXS_PINCTRL_PIN(EMI_CASN),
+        MXS_PINCTRL_PIN(EMI_CE0N),
+        MXS_PINCTRL_PIN(EMI_CE1N),
+        MXS_PINCTRL_PIN(GPMI_CE1N),
+        MXS_PINCTRL_PIN(GPMI_CE0N),
+        MXS_PINCTRL_PIN(EMI_CKE),
+        MXS_PINCTRL_PIN(EMI_RASN),
+        MXS_PINCTRL_PIN(EMI_WEN),
+        MXS_PINCTRL_PIN(EMI_D00),
+        MXS_PINCTRL_PIN(EMI_D01),
+        MXS_PINCTRL_PIN(EMI_D02),
+        MXS_PINCTRL_PIN(EMI_D03),
+        MXS_PINCTRL_PIN(EMI_D04),
+        MXS_PINCTRL_PIN(EMI_D05),
+        MXS_PINCTRL_PIN(EMI_D06),
+        MXS_PINCTRL_PIN(EMI_D07),
+        MXS_PINCTRL_PIN(EMI_D08),
+        MXS_PINCTRL_PIN(EMI_D09),
+        MXS_PINCTRL_PIN(EMI_D10),
+        MXS_PINCTRL_PIN(EMI_D11),
+        MXS_PINCTRL_PIN(EMI_D12),
+        MXS_PINCTRL_PIN(EMI_D13),
+        MXS_PINCTRL_PIN(EMI_D14),
+        MXS_PINCTRL_PIN(EMI_D15),
+        MXS_PINCTRL_PIN(EMI_DQM0),
+        MXS_PINCTRL_PIN(EMI_DQM1),
+        MXS_PINCTRL_PIN(EMI_DQS0),
+        MXS_PINCTRL_PIN(EMI_DQS1),
+        MXS_PINCTRL_PIN(EMI_CLK),
+        MXS_PINCTRL_PIN(EMI_CLKN),
+};
+
+static struct mxs_regs imx23_regs = {
+        .muxsel = 0x100,
+        .drive = 0x200,
+        .pull = 0x400,
+};
+
+static struct mxs_pinctrl_soc_data imx23_pinctrl_data = {
+        .regs = &imx23_regs,
+        .pins = imx23_pins,
+        .npins = ARRAY_SIZE(imx23_pins),
+};
+
+static int __devinit imx23_pinctrl_probe(struct platform_device *pdev)
+{
+        return mxs_pinctrl_probe(pdev, &imx23_pinctrl_data);
+}
+
+static struct of_device_id imx23_pinctrl_of_match[] __devinitdata = {
+        { .compatible = "fsl,imx23-pinctrl", },
+        { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, imx23_pinctrl_of_match);
+
+static struct platform_driver imx23_pinctrl_driver = {
+        .driver = {
+                .name = "imx23-pinctrl",
+                .owner = THIS_MODULE,
+                .of_match_table = imx23_pinctrl_of_match,
+        },
+        .probe = imx23_pinctrl_probe,
+        .remove = __devexit_p(mxs_pinctrl_remove),
+};
+
+static int __init imx23_pinctrl_init(void)
+{
+        return platform_driver_register(&imx23_pinctrl_driver);
+}
+arch_initcall(imx23_pinctrl_init);
+
+static void __exit imx23_pinctrl_exit(void)
+{
+        platform_driver_unregister(&imx23_pinctrl_driver);
+}
+module_exit(imx23_pinctrl_exit);
+
+MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
+MODULE_DESCRIPTION("Freescale i.MX23 pinctrl driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-imx28.c b/drivers/pinctrl/pinctrl-imx28.c
new file mode 100644
index 000000000000..b973026811a2
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx28.c
@@ -0,0 +1,421 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include "pinctrl-mxs.h"
+
+enum imx28_pin_enum {
+        GPMI_D00        = PINID(0, 0),
+        GPMI_D01        = PINID(0, 1),
+        GPMI_D02        = PINID(0, 2),
+        GPMI_D03        = PINID(0, 3),
+        GPMI_D04        = PINID(0, 4),
+        GPMI_D05        = PINID(0, 5),
+        GPMI_D06        = PINID(0, 6),
+        GPMI_D07        = PINID(0, 7),
+        GPMI_CE0N       = PINID(0, 16),
+        GPMI_CE1N       = PINID(0, 17),
+        GPMI_CE2N       = PINID(0, 18),
+        GPMI_CE3N       = PINID(0, 19),
+        GPMI_RDY0       = PINID(0, 20),
+        GPMI_RDY1       = PINID(0, 21),
+        GPMI_RDY2       = PINID(0, 22),
+        GPMI_RDY3       = PINID(0, 23),
+        GPMI_RDN        = PINID(0, 24),
+        GPMI_WRN        = PINID(0, 25),
+        GPMI_ALE        = PINID(0, 26),
+        GPMI_CLE        = PINID(0, 27),
+        GPMI_RESETN     = PINID(0, 28),
+        LCD_D00         = PINID(1, 0),
+        LCD_D01         = PINID(1, 1),
+        LCD_D02         = PINID(1, 2),
+        LCD_D03         = PINID(1, 3),
+        LCD_D04         = PINID(1, 4),
+        LCD_D05         = PINID(1, 5),
+        LCD_D06         = PINID(1, 6),
+        LCD_D07         = PINID(1, 7),
+        LCD_D08         = PINID(1, 8),
+        LCD_D09         = PINID(1, 9),
+        LCD_D10         = PINID(1, 10),
+        LCD_D11         = PINID(1, 11),
+        LCD_D12         = PINID(1, 12),
+        LCD_D13         = PINID(1, 13),
+        LCD_D14         = PINID(1, 14),
+        LCD_D15         = PINID(1, 15),
+        LCD_D16         = PINID(1, 16),
+        LCD_D17         = PINID(1, 17),
+        LCD_D18         = PINID(1, 18),
+        LCD_D19         = PINID(1, 19),
+        LCD_D20         = PINID(1, 20),
+        LCD_D21         = PINID(1, 21),
+        LCD_D22         = PINID(1, 22),
+        LCD_D23         = PINID(1, 23),
+        LCD_RD_E        = PINID(1, 24),
+        LCD_WR_RWN      = PINID(1, 25),
+        LCD_RS          = PINID(1, 26),
+        LCD_CS          = PINID(1, 27),
+        LCD_VSYNC       = PINID(1, 28),
+        LCD_HSYNC       = PINID(1, 29),
+        LCD_DOTCLK      = PINID(1, 30),
+        LCD_ENABLE      = PINID(1, 31),
+        SSP0_DATA0      = PINID(2, 0),
+        SSP0_DATA1      = PINID(2, 1),
+        SSP0_DATA2      = PINID(2, 2),
+        SSP0_DATA3      = PINID(2, 3),
+        SSP0_DATA4      = PINID(2, 4),
+        SSP0_DATA5      = PINID(2, 5),
+        SSP0_DATA6      = PINID(2, 6),
+        SSP0_DATA7      = PINID(2, 7),
+        SSP0_CMD        = PINID(2, 8),
+        SSP0_DETECT     = PINID(2, 9),
+        SSP0_SCK        = PINID(2, 10),
+        SSP1_SCK        = PINID(2, 12),
+        SSP1_CMD        = PINID(2, 13),
+        SSP1_DATA0      = PINID(2, 14),
+        SSP1_DATA3      = PINID(2, 15),
+        SSP2_SCK        = PINID(2, 16),
+        SSP2_MOSI       = PINID(2, 17),
+        SSP2_MISO       = PINID(2, 18),
+        SSP2_SS0        = PINID(2, 19),
+        SSP2_SS1        = PINID(2, 20),
+        SSP2_SS2        = PINID(2, 21),
+        SSP3_SCK        = PINID(2, 24),
+        SSP3_MOSI       = PINID(2, 25),
+        SSP3_MISO       = PINID(2, 26),
+        SSP3_SS0        = PINID(2, 27),
+        AUART0_RX       = PINID(3, 0),
+        AUART0_TX       = PINID(3, 1),
+        AUART0_CTS      = PINID(3, 2),
+        AUART0_RTS      = PINID(3, 3),
+        AUART1_RX       = PINID(3, 4),
+        AUART1_TX       = PINID(3, 5),
+        AUART1_CTS      = PINID(3, 6),
+        AUART1_RTS      = PINID(3, 7),
+        AUART2_RX       = PINID(3, 8),
+        AUART2_TX       = PINID(3, 9),
+        AUART2_CTS      = PINID(3, 10),
+        AUART2_RTS      = PINID(3, 11),
+        AUART3_RX       = PINID(3, 12),
+        AUART3_TX       = PINID(3, 13),
+        AUART3_CTS      = PINID(3, 14),
+        AUART3_RTS      = PINID(3, 15),
+        PWM0            = PINID(3, 16),
+        PWM1            = PINID(3, 17),
+        PWM2            = PINID(3, 18),
+        SAIF0_MCLK      = PINID(3, 20),
+        SAIF0_LRCLK     = PINID(3, 21),
+        SAIF0_BITCLK    = PINID(3, 22),
+        SAIF0_SDATA0    = PINID(3, 23),
+        I2C0_SCL        = PINID(3, 24),
+        I2C0_SDA        = PINID(3, 25),
+        SAIF1_SDATA0    = PINID(3, 26),
+        SPDIF           = PINID(3, 27),
+        PWM3            = PINID(3, 28),
+        PWM4            = PINID(3, 29),
+        LCD_RESET       = PINID(3, 30),
+        ENET0_MDC       = PINID(4, 0),
+        ENET0_MDIO      = PINID(4, 1),
+        ENET0_RX_EN     = PINID(4, 2),
+        ENET0_RXD0      = PINID(4, 3),
+        ENET0_RXD1      = PINID(4, 4),
+        ENET0_TX_CLK    = PINID(4, 5),
+        ENET0_TX_EN     = PINID(4, 6),
+        ENET0_TXD0      = PINID(4, 7),
+        ENET0_TXD1      = PINID(4, 8),
+        ENET0_RXD2      = PINID(4, 9),
+        ENET0_RXD3      = PINID(4, 10),
+        ENET0_TXD2      = PINID(4, 11),
+        ENET0_TXD3      = PINID(4, 12),
+        ENET0_RX_CLK    = PINID(4, 13),
+        ENET0_COL       = PINID(4, 14),
+        ENET0_CRS       = PINID(4, 15),
+        ENET_CLK        = PINID(4, 16),
+        JTAG_RTCK       = PINID(4, 20),
+        EMI_D00         = PINID(5, 0),
+        EMI_D01         = PINID(5, 1),
+        EMI_D02         = PINID(5, 2),
+        EMI_D03         = PINID(5, 3),
+        EMI_D04         = PINID(5, 4),
+        EMI_D05         = PINID(5, 5),
+        EMI_D06         = PINID(5, 6),
+        EMI_D07         = PINID(5, 7),
+        EMI_D08         = PINID(5, 8),
+        EMI_D09         = PINID(5, 9),
+        EMI_D10         = PINID(5, 10),
+        EMI_D11         = PINID(5, 11),
+        EMI_D12         = PINID(5, 12),
+        EMI_D13         = PINID(5, 13),
+        EMI_D14         = PINID(5, 14),
+        EMI_D15         = PINID(5, 15),
+        EMI_ODT0        = PINID(5, 16),
+        EMI_DQM0        = PINID(5, 17),
+        EMI_ODT1        = PINID(5, 18),
+        EMI_DQM1        = PINID(5, 19),
+        EMI_DDR_OPEN_FB = PINID(5, 20),
+        EMI_CLK         = PINID(5, 21),
+        EMI_DQS0        = PINID(5, 22),
+        EMI_DQS1        = PINID(5, 23),
+        EMI_DDR_OPEN    = PINID(5, 26),
+        EMI_A00         = PINID(6, 0),
+        EMI_A01         = PINID(6, 1),
+        EMI_A02         = PINID(6, 2),
+        EMI_A03         = PINID(6, 3),
+        EMI_A04         = PINID(6, 4),
+        EMI_A05         = PINID(6, 5),
+        EMI_A06         = PINID(6, 6),
+        EMI_A07         = PINID(6, 7),
+        EMI_A08         = PINID(6, 8),
+        EMI_A09         = PINID(6, 9),
+        EMI_A10         = PINID(6, 10),
+        EMI_A11         = PINID(6, 11),
+        EMI_A12         = PINID(6, 12),
+        EMI_A13         = PINID(6, 13),
+        EMI_A14         = PINID(6, 14),
+        EMI_BA0         = PINID(6, 16),
+        EMI_BA1         = PINID(6, 17),
+        EMI_BA2         = PINID(6, 18),
+        EMI_CASN        = PINID(6, 19),
+        EMI_RASN        = PINID(6, 20),
+        EMI_WEN         = PINID(6, 21),
+        EMI_CE0N        = PINID(6, 22),
+        EMI_CE1N        = PINID(6, 23),
+        EMI_CKE         = PINID(6, 24),
+};
+
+static const struct pinctrl_pin_desc imx28_pins[] = {
+        MXS_PINCTRL_PIN(GPMI_D00),
+        MXS_PINCTRL_PIN(GPMI_D01),
+        MXS_PINCTRL_PIN(GPMI_D02),
+        MXS_PINCTRL_PIN(GPMI_D03),
+        MXS_PINCTRL_PIN(GPMI_D04),
+        MXS_PINCTRL_PIN(GPMI_D05),
+        MXS_PINCTRL_PIN(GPMI_D06),
+        MXS_PINCTRL_PIN(GPMI_D07),
+        MXS_PINCTRL_PIN(GPMI_CE0N),
+        MXS_PINCTRL_PIN(GPMI_CE1N),
+        MXS_PINCTRL_PIN(GPMI_CE2N),
+        MXS_PINCTRL_PIN(GPMI_CE3N),
+        MXS_PINCTRL_PIN(GPMI_RDY0),
+        MXS_PINCTRL_PIN(GPMI_RDY1),
+        MXS_PINCTRL_PIN(GPMI_RDY2),
+        MXS_PINCTRL_PIN(GPMI_RDY3),
+        MXS_PINCTRL_PIN(GPMI_RDN),
+        MXS_PINCTRL_PIN(GPMI_WRN),
+        MXS_PINCTRL_PIN(GPMI_ALE),
+        MXS_PINCTRL_PIN(GPMI_CLE),
+        MXS_PINCTRL_PIN(GPMI_RESETN),
+        MXS_PINCTRL_PIN(LCD_D00),
+        MXS_PINCTRL_PIN(LCD_D01),
+        MXS_PINCTRL_PIN(LCD_D02),
+        MXS_PINCTRL_PIN(LCD_D03),
+        MXS_PINCTRL_PIN(LCD_D04),
+        MXS_PINCTRL_PIN(LCD_D05),
+        MXS_PINCTRL_PIN(LCD_D06),
+        MXS_PINCTRL_PIN(LCD_D07),
+        MXS_PINCTRL_PIN(LCD_D08),
+        MXS_PINCTRL_PIN(LCD_D09),
+        MXS_PINCTRL_PIN(LCD_D10),
+        MXS_PINCTRL_PIN(LCD_D11),
+        MXS_PINCTRL_PIN(LCD_D12),
+        MXS_PINCTRL_PIN(LCD_D13),
+        MXS_PINCTRL_PIN(LCD_D14),
+        MXS_PINCTRL_PIN(LCD_D15),
+        MXS_PINCTRL_PIN(LCD_D16),
+        MXS_PINCTRL_PIN(LCD_D17),
+        MXS_PINCTRL_PIN(LCD_D18),
+        MXS_PINCTRL_PIN(LCD_D19),
+        MXS_PINCTRL_PIN(LCD_D20),
+        MXS_PINCTRL_PIN(LCD_D21),
+        MXS_PINCTRL_PIN(LCD_D22),
+        MXS_PINCTRL_PIN(LCD_D23),
+        MXS_PINCTRL_PIN(LCD_RD_E),
+        MXS_PINCTRL_PIN(LCD_WR_RWN),
+        MXS_PINCTRL_PIN(LCD_RS),
+        MXS_PINCTRL_PIN(LCD_CS),
+        MXS_PINCTRL_PIN(LCD_VSYNC),
+        MXS_PINCTRL_PIN(LCD_HSYNC),
+        MXS_PINCTRL_PIN(LCD_DOTCLK),
+        MXS_PINCTRL_PIN(LCD_ENABLE),
+        MXS_PINCTRL_PIN(SSP0_DATA0),
+        MXS_PINCTRL_PIN(SSP0_DATA1),
+        MXS_PINCTRL_PIN(SSP0_DATA2),
+        MXS_PINCTRL_PIN(SSP0_DATA3),
+        MXS_PINCTRL_PIN(SSP0_DATA4),
+        MXS_PINCTRL_PIN(SSP0_DATA5),
+        MXS_PINCTRL_PIN(SSP0_DATA6),
+        MXS_PINCTRL_PIN(SSP0_DATA7),
+        MXS_PINCTRL_PIN(SSP0_CMD),
+        MXS_PINCTRL_PIN(SSP0_DETECT),
+        MXS_PINCTRL_PIN(SSP0_SCK),
+        MXS_PINCTRL_PIN(SSP1_SCK),
+        MXS_PINCTRL_PIN(SSP1_CMD),
+        MXS_PINCTRL_PIN(SSP1_DATA0),
+        MXS_PINCTRL_PIN(SSP1_DATA3),
+        MXS_PINCTRL_PIN(SSP2_SCK),
+        MXS_PINCTRL_PIN(SSP2_MOSI),
+        MXS_PINCTRL_PIN(SSP2_MISO),
+        MXS_PINCTRL_PIN(SSP2_SS0),
+        MXS_PINCTRL_PIN(SSP2_SS1),
+        MXS_PINCTRL_PIN(SSP2_SS2),
+        MXS_PINCTRL_PIN(SSP3_SCK),
+        MXS_PINCTRL_PIN(SSP3_MOSI),
+        MXS_PINCTRL_PIN(SSP3_MISO),
+        MXS_PINCTRL_PIN(SSP3_SS0),
+        MXS_PINCTRL_PIN(AUART0_RX),
+        MXS_PINCTRL_PIN(AUART0_TX),
+        MXS_PINCTRL_PIN(AUART0_CTS),
+        MXS_PINCTRL_PIN(AUART0_RTS),
+        MXS_PINCTRL_PIN(AUART1_RX),
+        MXS_PINCTRL_PIN(AUART1_TX),
+        MXS_PINCTRL_PIN(AUART1_CTS),
+        MXS_PINCTRL_PIN(AUART1_RTS),
+        MXS_PINCTRL_PIN(AUART2_RX),
+        MXS_PINCTRL_PIN(AUART2_TX),
+        MXS_PINCTRL_PIN(AUART2_CTS),
+        MXS_PINCTRL_PIN(AUART2_RTS),
+        MXS_PINCTRL_PIN(AUART3_RX),
+        MXS_PINCTRL_PIN(AUART3_TX),
+        MXS_PINCTRL_PIN(AUART3_CTS),
+        MXS_PINCTRL_PIN(AUART3_RTS),
+        MXS_PINCTRL_PIN(PWM0),
+        MXS_PINCTRL_PIN(PWM1),
+        MXS_PINCTRL_PIN(PWM2),
+        MXS_PINCTRL_PIN(SAIF0_MCLK),
+        MXS_PINCTRL_PIN(SAIF0_LRCLK),
+        MXS_PINCTRL_PIN(SAIF0_BITCLK),
+        MXS_PINCTRL_PIN(SAIF0_SDATA0),
+        MXS_PINCTRL_PIN(I2C0_SCL),
+        MXS_PINCTRL_PIN(I2C0_SDA),
+        MXS_PINCTRL_PIN(SAIF1_SDATA0),
+        MXS_PINCTRL_PIN(SPDIF),
+        MXS_PINCTRL_PIN(PWM3),
+        MXS_PINCTRL_PIN(PWM4),
+        MXS_PINCTRL_PIN(LCD_RESET),
+        MXS_PINCTRL_PIN(ENET0_MDC),
+        MXS_PINCTRL_PIN(ENET0_MDIO),
+        MXS_PINCTRL_PIN(ENET0_RX_EN),
+        MXS_PINCTRL_PIN(ENET0_RXD0),
+        MXS_PINCTRL_PIN(ENET0_RXD1),
+        MXS_PINCTRL_PIN(ENET0_TX_CLK),
+        MXS_PINCTRL_PIN(ENET0_TX_EN),
+        MXS_PINCTRL_PIN(ENET0_TXD0),
+        MXS_PINCTRL_PIN(ENET0_TXD1),
+        MXS_PINCTRL_PIN(ENET0_RXD2),
+        MXS_PINCTRL_PIN(ENET0_RXD3),
+        MXS_PINCTRL_PIN(ENET0_TXD2),
+        MXS_PINCTRL_PIN(ENET0_TXD3),
+        MXS_PINCTRL_PIN(ENET0_RX_CLK),
+        MXS_PINCTRL_PIN(ENET0_COL),
+        MXS_PINCTRL_PIN(ENET0_CRS),
+        MXS_PINCTRL_PIN(ENET_CLK),
+        MXS_PINCTRL_PIN(JTAG_RTCK),
+        MXS_PINCTRL_PIN(EMI_D00),
+        MXS_PINCTRL_PIN(EMI_D01),
+        MXS_PINCTRL_PIN(EMI_D02),
+        MXS_PINCTRL_PIN(EMI_D03),
+        MXS_PINCTRL_PIN(EMI_D04),
+        MXS_PINCTRL_PIN(EMI_D05),
+        MXS_PINCTRL_PIN(EMI_D06),
+        MXS_PINCTRL_PIN(EMI_D07),
+        MXS_PINCTRL_PIN(EMI_D08),
+        MXS_PINCTRL_PIN(EMI_D09),
+        MXS_PINCTRL_PIN(EMI_D10),
+        MXS_PINCTRL_PIN(EMI_D11),
+        MXS_PINCTRL_PIN(EMI_D12),
+        MXS_PINCTRL_PIN(EMI_D13),
+        MXS_PINCTRL_PIN(EMI_D14),
+        MXS_PINCTRL_PIN(EMI_D15),
+        MXS_PINCTRL_PIN(EMI_ODT0),
+        MXS_PINCTRL_PIN(EMI_DQM0),
+        MXS_PINCTRL_PIN(EMI_ODT1),
+        MXS_PINCTRL_PIN(EMI_DQM1),
+        MXS_PINCTRL_PIN(EMI_DDR_OPEN_FB),
+        MXS_PINCTRL_PIN(EMI_CLK),
+        MXS_PINCTRL_PIN(EMI_DQS0),
+        MXS_PINCTRL_PIN(EMI_DQS1),
+        MXS_PINCTRL_PIN(EMI_DDR_OPEN),
+        MXS_PINCTRL_PIN(EMI_A00),
+        MXS_PINCTRL_PIN(EMI_A01),
+        MXS_PINCTRL_PIN(EMI_A02),
+        MXS_PINCTRL_PIN(EMI_A03),
+        MXS_PINCTRL_PIN(EMI_A04),
+        MXS_PINCTRL_PIN(EMI_A05),
+        MXS_PINCTRL_PIN(EMI_A06),
+        MXS_PINCTRL_PIN(EMI_A07),
+        MXS_PINCTRL_PIN(EMI_A08),
+        MXS_PINCTRL_PIN(EMI_A09),
+        MXS_PINCTRL_PIN(EMI_A10),
+        MXS_PINCTRL_PIN(EMI_A11),
+        MXS_PINCTRL_PIN(EMI_A12),
+        MXS_PINCTRL_PIN(EMI_A13),
+        MXS_PINCTRL_PIN(EMI_A14),
+        MXS_PINCTRL_PIN(EMI_BA0),
+        MXS_PINCTRL_PIN(EMI_BA1),
+        MXS_PINCTRL_PIN(EMI_BA2),
+        MXS_PINCTRL_PIN(EMI_CASN),
+        MXS_PINCTRL_PIN(EMI_RASN),
+        MXS_PINCTRL_PIN(EMI_WEN),
+        MXS_PINCTRL_PIN(EMI_CE0N),
+        MXS_PINCTRL_PIN(EMI_CE1N),
+        MXS_PINCTRL_PIN(EMI_CKE),
+};
+
+static struct mxs_regs imx28_regs = {
+        .muxsel = 0x100,
+        .drive = 0x300,
+        .pull = 0x600,
+};
+
+static struct mxs_pinctrl_soc_data imx28_pinctrl_data = {
+        .regs = &imx28_regs,
+        .pins = imx28_pins,
+        .npins = ARRAY_SIZE(imx28_pins),
+};
+
+static int __devinit imx28_pinctrl_probe(struct platform_device *pdev)
+{
+        return mxs_pinctrl_probe(pdev, &imx28_pinctrl_data);
+}
+
+static struct of_device_id imx28_pinctrl_of_match[] __devinitdata = {
+        { .compatible = "fsl,imx28-pinctrl", },
+        { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, imx28_pinctrl_of_match);
+
+static struct platform_driver imx28_pinctrl_driver = {
+        .driver = {
+                .name = "imx28-pinctrl",
+                .owner = THIS_MODULE,
+                .of_match_table = imx28_pinctrl_of_match,
+        },
+        .probe = imx28_pinctrl_probe,
+        .remove = __devexit_p(mxs_pinctrl_remove),
+};
+
+static int __init imx28_pinctrl_init(void)
+{
+        return platform_driver_register(&imx28_pinctrl_driver);
+}
+arch_initcall(imx28_pinctrl_init);
+
+static void __exit imx28_pinctrl_exit(void)
+{
+        platform_driver_unregister(&imx28_pinctrl_driver);
+}
+module_exit(imx28_pinctrl_exit);
+
+MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
+MODULE_DESCRIPTION("Freescale i.MX28 pinctrl driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-imx6q.c b/drivers/pinctrl/pinctrl-imx6q.c
new file mode 100644
index 000000000000..7737d4d71a3c
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx6q.c
@@ -0,0 +1,2331 @@
+/*
+ * imx6q pinctrl driver based on imx pinmux core
+ *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012 Linaro, Inc.
+ *
+ * Author: Dong Aisheng <dong.aisheng@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-imx.h"
+
+enum imx6q_pads {
+        MX6Q_PAD_SD2_DAT1 = 0,
+        MX6Q_PAD_SD2_DAT2 = 1,
+        MX6Q_PAD_SD2_DAT0 = 2,
+        MX6Q_PAD_RGMII_TXC = 3,
+        MX6Q_PAD_RGMII_TD0 = 4,
+        MX6Q_PAD_RGMII_TD1 = 5,
+        MX6Q_PAD_RGMII_TD2 = 6,
+        MX6Q_PAD_RGMII_TD3 = 7,
+        MX6Q_PAD_RGMII_RX_CTL = 8,
+        MX6Q_PAD_RGMII_RD0 = 9,
+        MX6Q_PAD_RGMII_TX_CTL = 10,
+        MX6Q_PAD_RGMII_RD1 = 11,
+        MX6Q_PAD_RGMII_RD2 = 12,
+        MX6Q_PAD_RGMII_RD3 = 13,
+        MX6Q_PAD_RGMII_RXC = 14,
+        MX6Q_PAD_EIM_A25 = 15,
+        MX6Q_PAD_EIM_EB2 = 16,
+        MX6Q_PAD_EIM_D16 = 17,
+        MX6Q_PAD_EIM_D17 = 18,
+        MX6Q_PAD_EIM_D18 = 19,
+        MX6Q_PAD_EIM_D19 = 20,
+        MX6Q_PAD_EIM_D20 = 21,
+        MX6Q_PAD_EIM_D21 = 22,
+        MX6Q_PAD_EIM_D22 = 23,
+        MX6Q_PAD_EIM_D23 = 24,
+        MX6Q_PAD_EIM_EB3 = 25,
+        MX6Q_PAD_EIM_D24 = 26,
+        MX6Q_PAD_EIM_D25 = 27,
+        MX6Q_PAD_EIM_D26 = 28,
+        MX6Q_PAD_EIM_D27 = 29,
+        MX6Q_PAD_EIM_D28 = 30,
+        MX6Q_PAD_EIM_D29 = 31,
+        MX6Q_PAD_EIM_D30 = 32,
+        MX6Q_PAD_EIM_D31 = 33,
+        MX6Q_PAD_EIM_A24 = 34,
+        MX6Q_PAD_EIM_A23 = 35,
+        MX6Q_PAD_EIM_A22 = 36,
+        MX6Q_PAD_EIM_A21 = 37,
+        MX6Q_PAD_EIM_A20 = 38,
+        MX6Q_PAD_EIM_A19 = 39,
+        MX6Q_PAD_EIM_A18 = 40,
+        MX6Q_PAD_EIM_A17 = 41,
+        MX6Q_PAD_EIM_A16 = 42,
+        MX6Q_PAD_EIM_CS0 = 43,
+        MX6Q_PAD_EIM_CS1 = 44,
+        MX6Q_PAD_EIM_OE = 45,
+        MX6Q_PAD_EIM_RW = 46,
+        MX6Q_PAD_EIM_LBA = 47,
+        MX6Q_PAD_EIM_EB0 = 48,
+        MX6Q_PAD_EIM_EB1 = 49,
+        MX6Q_PAD_EIM_DA0 = 50,
+        MX6Q_PAD_EIM_DA1 = 51,
+        MX6Q_PAD_EIM_DA2 = 52,
+        MX6Q_PAD_EIM_DA3 = 53,
+        MX6Q_PAD_EIM_DA4 = 54,
+        MX6Q_PAD_EIM_DA5 = 55,
+        MX6Q_PAD_EIM_DA6 = 56,
+        MX6Q_PAD_EIM_DA7 = 57,
+        MX6Q_PAD_EIM_DA8 = 58,
+        MX6Q_PAD_EIM_DA9 = 59,
+        MX6Q_PAD_EIM_DA10 = 60,
+        MX6Q_PAD_EIM_DA11 = 61,
+        MX6Q_PAD_EIM_DA12 = 62,
+        MX6Q_PAD_EIM_DA13 = 63,
+        MX6Q_PAD_EIM_DA14 = 64,
+        MX6Q_PAD_EIM_DA15 = 65,
+        MX6Q_PAD_EIM_WAIT = 66,
+        MX6Q_PAD_EIM_BCLK = 67,
+        MX6Q_PAD_DI0_DISP_CLK = 68,
+        MX6Q_PAD_DI0_PIN15 = 69,
+        MX6Q_PAD_DI0_PIN2 = 70,
+        MX6Q_PAD_DI0_PIN3 = 71,
+        MX6Q_PAD_DI0_PIN4 = 72,
+        MX6Q_PAD_DISP0_DAT0 = 73,
+        MX6Q_PAD_DISP0_DAT1 = 74,
+        MX6Q_PAD_DISP0_DAT2 = 75,
+        MX6Q_PAD_DISP0_DAT3 = 76,
+        MX6Q_PAD_DISP0_DAT4 = 77,
+        MX6Q_PAD_DISP0_DAT5 = 78,
+        MX6Q_PAD_DISP0_DAT6 = 79,
+        MX6Q_PAD_DISP0_DAT7 = 80,
+        MX6Q_PAD_DISP0_DAT8 = 81,
+        MX6Q_PAD_DISP0_DAT9 = 82,
+        MX6Q_PAD_DISP0_DAT10 = 83,
+        MX6Q_PAD_DISP0_DAT11 = 84,
+        MX6Q_PAD_DISP0_DAT12 = 85,
+        MX6Q_PAD_DISP0_DAT13 = 86,
+        MX6Q_PAD_DISP0_DAT14 = 87,
+        MX6Q_PAD_DISP0_DAT15 = 88,
+        MX6Q_PAD_DISP0_DAT16 = 89,
+        MX6Q_PAD_DISP0_DAT17 = 90,
+        MX6Q_PAD_DISP0_DAT18 = 91,
+        MX6Q_PAD_DISP0_DAT19 = 92,
+        MX6Q_PAD_DISP0_DAT20 = 93,
+        MX6Q_PAD_DISP0_DAT21 = 94,
+        MX6Q_PAD_DISP0_DAT22 = 95,
+        MX6Q_PAD_DISP0_DAT23 = 96,
+        MX6Q_PAD_ENET_MDIO = 97,
+        MX6Q_PAD_ENET_REF_CLK = 98,
+        MX6Q_PAD_ENET_RX_ER = 99,
+        MX6Q_PAD_ENET_CRS_DV = 100,
+        MX6Q_PAD_ENET_RXD1 = 101,
+        MX6Q_PAD_ENET_RXD0 = 102,
+        MX6Q_PAD_ENET_TX_EN = 103,
+        MX6Q_PAD_ENET_TXD1 = 104,
+        MX6Q_PAD_ENET_TXD0 = 105,
+        MX6Q_PAD_ENET_MDC = 106,
+        MX6Q_PAD_DRAM_D40 = 107,
+        MX6Q_PAD_DRAM_D41 = 108,
+        MX6Q_PAD_DRAM_D42 = 109,
+        MX6Q_PAD_DRAM_D43 = 110,
+        MX6Q_PAD_DRAM_D44 = 111,
+        MX6Q_PAD_DRAM_D45 = 112,
+        MX6Q_PAD_DRAM_D46 = 113,
+        MX6Q_PAD_DRAM_D47 = 114,
+        MX6Q_PAD_DRAM_SDQS5 = 115,
+        MX6Q_PAD_DRAM_DQM5 = 116,
+        MX6Q_PAD_DRAM_D32 = 117,
+        MX6Q_PAD_DRAM_D33 = 118,
+        MX6Q_PAD_DRAM_D34 = 119,
+        MX6Q_PAD_DRAM_D35 = 120,
+        MX6Q_PAD_DRAM_D36 = 121,
+        MX6Q_PAD_DRAM_D37 = 122,
+        MX6Q_PAD_DRAM_D38 = 123,
+        MX6Q_PAD_DRAM_D39 = 124,
+        MX6Q_PAD_DRAM_DQM4 = 125,
+        MX6Q_PAD_DRAM_SDQS4 = 126,
+        MX6Q_PAD_DRAM_D24 = 127,
+        MX6Q_PAD_DRAM_D25 = 128,
+        MX6Q_PAD_DRAM_D26 = 129,
+        MX6Q_PAD_DRAM_D27 = 130,
+        MX6Q_PAD_DRAM_D28 = 131,
+        MX6Q_PAD_DRAM_D29 = 132,
+        MX6Q_PAD_DRAM_SDQS3 = 133,
+        MX6Q_PAD_DRAM_D30 = 134,
+        MX6Q_PAD_DRAM_D31 = 135,
+        MX6Q_PAD_DRAM_DQM3 = 136,
+        MX6Q_PAD_DRAM_D16 = 137,
+        MX6Q_PAD_DRAM_D17 = 138,
+        MX6Q_PAD_DRAM_D18 = 139,
+        MX6Q_PAD_DRAM_D19 = 140,
+        MX6Q_PAD_DRAM_D20 = 141,
+        MX6Q_PAD_DRAM_D21 = 142,
+        MX6Q_PAD_DRAM_D22 = 143,
+        MX6Q_PAD_DRAM_SDQS2 = 144,
+        MX6Q_PAD_DRAM_D23 = 145,
+        MX6Q_PAD_DRAM_DQM2 = 146,
+        MX6Q_PAD_DRAM_A0 = 147,
+        MX6Q_PAD_DRAM_A1 = 148,
+        MX6Q_PAD_DRAM_A2 = 149,
+        MX6Q_PAD_DRAM_A3 = 150,
+        MX6Q_PAD_DRAM_A4 = 151,
+        MX6Q_PAD_DRAM_A5 = 152,
+        MX6Q_PAD_DRAM_A6 = 153,
+        MX6Q_PAD_DRAM_A7 = 154,
+        MX6Q_PAD_DRAM_A8 = 155,
+        MX6Q_PAD_DRAM_A9 = 156,
+        MX6Q_PAD_DRAM_A10 = 157,
+        MX6Q_PAD_DRAM_A11 = 158,
+        MX6Q_PAD_DRAM_A12 = 159,
+        MX6Q_PAD_DRAM_A13 = 160,
+        MX6Q_PAD_DRAM_A14 = 161,
+        MX6Q_PAD_DRAM_A15 = 162,
+        MX6Q_PAD_DRAM_CAS = 163,
+        MX6Q_PAD_DRAM_CS0 = 164,
+        MX6Q_PAD_DRAM_CS1 = 165,
+        MX6Q_PAD_DRAM_RAS = 166,
+        MX6Q_PAD_DRAM_RESET = 167,
+        MX6Q_PAD_DRAM_SDBA0 = 168,
+        MX6Q_PAD_DRAM_SDBA1 = 169,
+        MX6Q_PAD_DRAM_SDCLK_0 = 170,
+        MX6Q_PAD_DRAM_SDBA2 = 171,
+        MX6Q_PAD_DRAM_SDCKE0 = 172,
+        MX6Q_PAD_DRAM_SDCLK_1 = 173,
+        MX6Q_PAD_DRAM_SDCKE1 = 174,
+        MX6Q_PAD_DRAM_SDODT0 = 175,
+        MX6Q_PAD_DRAM_SDODT1 = 176,
+        MX6Q_PAD_DRAM_SDWE = 177,
+        MX6Q_PAD_DRAM_D0 = 178,
+        MX6Q_PAD_DRAM_D1 = 179,
+        MX6Q_PAD_DRAM_D2 = 180,
+        MX6Q_PAD_DRAM_D3 = 181,
+        MX6Q_PAD_DRAM_D4 = 182,
+        MX6Q_PAD_DRAM_D5 = 183,
+        MX6Q_PAD_DRAM_SDQS0 = 184,
+        MX6Q_PAD_DRAM_D6 = 185,
+        MX6Q_PAD_DRAM_D7 = 186,
+        MX6Q_PAD_DRAM_DQM0 = 187,
+        MX6Q_PAD_DRAM_D8 = 188,
+        MX6Q_PAD_DRAM_D9 = 189,
+        MX6Q_PAD_DRAM_D10 = 190,
+        MX6Q_PAD_DRAM_D11 = 191,
+        MX6Q_PAD_DRAM_D12 = 192,
+        MX6Q_PAD_DRAM_D13 = 193,
+        MX6Q_PAD_DRAM_D14 = 194,
+        MX6Q_PAD_DRAM_SDQS1 = 195,
+        MX6Q_PAD_DRAM_D15 = 196,
+        MX6Q_PAD_DRAM_DQM1 = 197,
+        MX6Q_PAD_DRAM_D48 = 198,
+        MX6Q_PAD_DRAM_D49 = 199,
+        MX6Q_PAD_DRAM_D50 = 200,
+        MX6Q_PAD_DRAM_D51 = 201,
+        MX6Q_PAD_DRAM_D52 = 202,
+        MX6Q_PAD_DRAM_D53 = 203,
+        MX6Q_PAD_DRAM_D54 = 204,
+        MX6Q_PAD_DRAM_D55 = 205,
+        MX6Q_PAD_DRAM_SDQS6 = 206,
+        MX6Q_PAD_DRAM_DQM6 = 207,
+        MX6Q_PAD_DRAM_D56 = 208,
+        MX6Q_PAD_DRAM_SDQS7 = 209,
+        MX6Q_PAD_DRAM_D57 = 210,
+        MX6Q_PAD_DRAM_D58 = 211,
+        MX6Q_PAD_DRAM_D59 = 212,
+        MX6Q_PAD_DRAM_D60 = 213,
+        MX6Q_PAD_DRAM_DQM7 = 214,
+        MX6Q_PAD_DRAM_D61 = 215,
+        MX6Q_PAD_DRAM_D62 = 216,
+        MX6Q_PAD_DRAM_D63 = 217,
+        MX6Q_PAD_KEY_COL0 = 218,
+        MX6Q_PAD_KEY_ROW0 = 219,
+        MX6Q_PAD_KEY_COL1 = 220,
+        MX6Q_PAD_KEY_ROW1 = 221,
+        MX6Q_PAD_KEY_COL2 = 222,
+        MX6Q_PAD_KEY_ROW2 = 223,
+        MX6Q_PAD_KEY_COL3 = 224,
+        MX6Q_PAD_KEY_ROW3 = 225,
+        MX6Q_PAD_KEY_COL4 = 226,
+        MX6Q_PAD_KEY_ROW4 = 227,
+        MX6Q_PAD_GPIO_0 = 228,
+        MX6Q_PAD_GPIO_1 = 229,
+        MX6Q_PAD_GPIO_9 = 230,
+        MX6Q_PAD_GPIO_3 = 231,
+        MX6Q_PAD_GPIO_6 = 232,
+        MX6Q_PAD_GPIO_2 = 233,
+        MX6Q_PAD_GPIO_4 = 234,
+        MX6Q_PAD_GPIO_5 = 235,
+        MX6Q_PAD_GPIO_7 = 236,
+        MX6Q_PAD_GPIO_8 = 237,
+        MX6Q_PAD_GPIO_16 = 238,
+        MX6Q_PAD_GPIO_17 = 239,
+        MX6Q_PAD_GPIO_18 = 240,
+        MX6Q_PAD_GPIO_19 = 241,
+        MX6Q_PAD_CSI0_PIXCLK = 242,
+        MX6Q_PAD_CSI0_MCLK = 243,
+        MX6Q_PAD_CSI0_DATA_EN = 244,
+        MX6Q_PAD_CSI0_VSYNC = 245,
+        MX6Q_PAD_CSI0_DAT4 = 246,
+        MX6Q_PAD_CSI0_DAT5 = 247,
+        MX6Q_PAD_CSI0_DAT6 = 248,
+        MX6Q_PAD_CSI0_DAT7 = 249,
+        MX6Q_PAD_CSI0_DAT8 = 250,
+        MX6Q_PAD_CSI0_DAT9 = 251,
+        MX6Q_PAD_CSI0_DAT10 = 252,
+        MX6Q_PAD_CSI0_DAT11 = 253,
+        MX6Q_PAD_CSI0_DAT12 = 254,
+        MX6Q_PAD_CSI0_DAT13 = 255,
+        MX6Q_PAD_CSI0_DAT14 = 256,
+        MX6Q_PAD_CSI0_DAT15 = 257,
+        MX6Q_PAD_CSI0_DAT16 = 258,
+        MX6Q_PAD_CSI0_DAT17 = 259,
+        MX6Q_PAD_CSI0_DAT18 = 260,
+        MX6Q_PAD_CSI0_DAT19 = 261,
+        MX6Q_PAD_JTAG_TMS = 262,
+        MX6Q_PAD_JTAG_MOD = 263,
+        MX6Q_PAD_JTAG_TRSTB = 264,
+        MX6Q_PAD_JTAG_TDI = 265,
+        MX6Q_PAD_JTAG_TCK = 266,
+        MX6Q_PAD_JTAG_TDO = 267,
+        MX6Q_PAD_LVDS1_TX3_P = 268,
+        MX6Q_PAD_LVDS1_TX2_P = 269,
+        MX6Q_PAD_LVDS1_CLK_P = 270,
+        MX6Q_PAD_LVDS1_TX1_P = 271,
+        MX6Q_PAD_LVDS1_TX0_P = 272,
+        MX6Q_PAD_LVDS0_TX3_P = 273,
+        MX6Q_PAD_LVDS0_CLK_P = 274,
+        MX6Q_PAD_LVDS0_TX2_P = 275,
+        MX6Q_PAD_LVDS0_TX1_P = 276,
+        MX6Q_PAD_LVDS0_TX0_P = 277,
+        MX6Q_PAD_TAMPER = 278,
+        MX6Q_PAD_PMIC_ON_REQ = 279,
+        MX6Q_PAD_PMIC_STBY_REQ = 280,
+        MX6Q_PAD_POR_B = 281,
+        MX6Q_PAD_BOOT_MODE1 = 282,
+        MX6Q_PAD_RESET_IN_B = 283,
+        MX6Q_PAD_BOOT_MODE0 = 284,
+        MX6Q_PAD_TEST_MODE = 285,
+        MX6Q_PAD_SD3_DAT7 = 286,
+        MX6Q_PAD_SD3_DAT6 = 287,
+        MX6Q_PAD_SD3_DAT5 = 288,
+        MX6Q_PAD_SD3_DAT4 = 289,
+        MX6Q_PAD_SD3_CMD = 290,
+        MX6Q_PAD_SD3_CLK = 291,
+        MX6Q_PAD_SD3_DAT0 = 292,
+        MX6Q_PAD_SD3_DAT1 = 293,
+        MX6Q_PAD_SD3_DAT2 = 294,
+        MX6Q_PAD_SD3_DAT3 = 295,
+        MX6Q_PAD_SD3_RST = 296,
+        MX6Q_PAD_NANDF_CLE = 297,
+        MX6Q_PAD_NANDF_ALE = 298,
+        MX6Q_PAD_NANDF_WP_B = 299,
+        MX6Q_PAD_NANDF_RB0 = 300,
+        MX6Q_PAD_NANDF_CS0 = 301,
+        MX6Q_PAD_NANDF_CS1 = 302,
+        MX6Q_PAD_NANDF_CS2 = 303,
+        MX6Q_PAD_NANDF_CS3 = 304,
+        MX6Q_PAD_SD4_CMD = 305,
+        MX6Q_PAD_SD4_CLK = 306,
+        MX6Q_PAD_NANDF_D0 = 307,
+        MX6Q_PAD_NANDF_D1 = 308,
+        MX6Q_PAD_NANDF_D2 = 309,
+        MX6Q_PAD_NANDF_D3 = 310,
+        MX6Q_PAD_NANDF_D4 = 311,
+        MX6Q_PAD_NANDF_D5 = 312,
+        MX6Q_PAD_NANDF_D6 = 313,
+        MX6Q_PAD_NANDF_D7 = 314,
+        MX6Q_PAD_SD4_DAT0 = 315,
+        MX6Q_PAD_SD4_DAT1 = 316,
+        MX6Q_PAD_SD4_DAT2 = 317,
+        MX6Q_PAD_SD4_DAT3 = 318,
+        MX6Q_PAD_SD4_DAT4 = 319,
+        MX6Q_PAD_SD4_DAT5 = 320,
+        MX6Q_PAD_SD4_DAT6 = 321,
+        MX6Q_PAD_SD4_DAT7 = 322,
+        MX6Q_PAD_SD1_DAT1 = 323,
+        MX6Q_PAD_SD1_DAT0 = 324,
+        MX6Q_PAD_SD1_DAT3 = 325,
+        MX6Q_PAD_SD1_CMD = 326,
+        MX6Q_PAD_SD1_DAT2 = 327,
+        MX6Q_PAD_SD1_CLK = 328,
+        MX6Q_PAD_SD2_CLK = 329,
+        MX6Q_PAD_SD2_CMD = 330,
+        MX6Q_PAD_SD2_DAT3 = 331,
+};
+
+/* imx6q register maps */
+static struct imx_pin_reg imx6q_pin_regs[] = {
+        IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 0, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */
+        IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 1, 0x0834, 0), /* MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 */
+        IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 2, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 */
+        IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 3, 0x07C8, 0), /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
+        IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 4, 0x08F0, 0), /* MX6Q_PAD_SD2_DAT1__KPP_COL_7 */
+        IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__GPIO_1_14 */
+        IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__CCM_WAIT */
+        IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__ANATOP_TESTO_0 */
+        IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 0, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */
+        IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 1, 0x0838, 0), /* MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 */
+        IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 2, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 */
+        IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 3, 0x07B8, 0), /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
+        IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 4, 0x08F8, 0), /* MX6Q_PAD_SD2_DAT2__KPP_ROW_6 */
+        IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__GPIO_1_13 */
+        IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__CCM_STOP */
+        IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__ANATOP_TESTO_1 */
+        IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 0, 0x0000, 0), /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */
+        IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 1, 0x082C, 0), /* MX6Q_PAD_SD2_DAT0__ECSPI5_MISO */
+        IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 3, 0x07B4, 0), /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
+        IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 4, 0x08FC, 0), /* MX6Q_PAD_SD2_DAT0__KPP_ROW_7 */
+        IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT0__GPIO_1_15 */
+        IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT */
+        IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT0__TESTO_2 */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 2, 0x0918, 0), /* MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__GPIO_6_19 */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_IN_0 */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 7, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__ANATOP_24M_OUT */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_TD0, 0x0370, 0x005C, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TD0__MIPI_HSI_CRL_TX_RDY */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_TD0, 0x0370, 0x005C, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_TD0, 0x0370, 0x005C, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TD0__GPIO_6_20 */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_TD0, 0x0370, 0x005C, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_IN_1 */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__MIPI_HSI_CRL_RX_FLG */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__GPIO_6_21 */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_IN_2 */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 7, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__MIPI_HSI_CRL_RX_DTA */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__GPIO_6_22 */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_IN_3 */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 7, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_TD3, 0x037C, 0x0068, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TD3__MIPI_HSI_CRL_RX_WAK */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_TD3, 0x037C, 0x0068, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_TD3, 0x037C, 0x0068, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TD3__GPIO_6_23 */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_TD3, 0x037C, 0x0068, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_IN_4 */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_RX_CTL, 0x0380, 0x006C, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_RX_CTL, 0x0380, 0x006C, 1, 0x0858, 0), /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_RX_CTL, 0x0380, 0x006C, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_RX_CTL, 0x0380, 0x006C, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RX_CTL__MIPI_DPHY_IN_5 */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_RD0, 0x0384, 0x0070, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RD0__MIPI_HSI_CRL_RX_RDY */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_RD0, 0x0384, 0x0070, 1, 0x0848, 0), /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_RD0, 0x0384, 0x0070, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RD0__GPIO_6_25 */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_RD0, 0x0384, 0x0070, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_IN_6 */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TX_CTL__CORE_DPHY_IN_7 */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 7, 0x083C, 0), /* MX6Q_PAD_RGMII_TX_CTL__ANATOP_REF_OUT */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FL */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 1, 0x084C, 0), /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RD1__GPIO_6_27 */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RD1__CORE_DPHY_TEST_IN_8 */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 7, 0x0000, 0), /* MX6Q_PAD_RGMII_RD1__SJC_FAIL */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_RD2, 0x0390, 0x007C, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RD2__MIPI_HSI_CRL_TX_DTA */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_RD2, 0x0390, 0x007C, 1, 0x0850, 0), /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_RD2, 0x0390, 0x007C, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RD2__GPIO_6_28 */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_RD2, 0x0390, 0x007C, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_IN_9 */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_RD3, 0x0394, 0x0080, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RD3__MIPI_HSI_CRL_TX_WAK */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_RD3, 0x0394, 0x0080, 1, 0x0854, 0), /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_RD3, 0x0394, 0x0080, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RD3__GPIO_6_29 */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_RD3, 0x0394, 0x0080, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_IN10 */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_RXC, 0x0398, 0x0084, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_RXC, 0x0398, 0x0084, 1, 0x0844, 0), /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_RXC, 0x0398, 0x0084, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RXC__GPIO_6_30 */
+        IMX_PIN_REG(MX6Q_PAD_RGMII_RXC, 0x0398, 0x0084, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_IN11 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A25__ECSPI4_SS1 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 2, 0x0000, 0), /* MX6Q_PAD_EIM_A25__ECSPI2_RDY */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A25__GPIO_5_2 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 6, 0x088C, 0), /* MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A25__PL301_PER1_HBURST_0 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 1, 0x0800, 0), /* MX6Q_PAD_EIM_EB2__ECSPI1_SS0 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 2, 0x07EC, 0), /* MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK */
+        IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 3, 0x08D4, 0), /* MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 4, 0x0890, 0), /* MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL */
+        IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_EB2__GPIO_2_30 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 6, 0x08A0, 0), /* MX6Q_PAD_EIM_EB2__I2C2_SCL */
+        IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 1, 0x07F4, 0), /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 3, 0x08D0, 0), /* MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 4, 0x0894, 0), /* MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D16__GPIO_3_16 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 6, 0x08A4, 0), /* MX6Q_PAD_EIM_D16__I2C2_SDA */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 1, 0x07F8, 0), /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 3, 0x08E0, 0), /* MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D17__GPIO_3_17 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 6, 0x08A8, 0), /* MX6Q_PAD_EIM_D17__I2C3_SCL */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D17__PL301_PER1_HBURST_1 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 1, 0x07FC, 0), /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 3, 0x08CC, 0), /* MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D18__GPIO_3_18 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 6, 0x08AC, 0), /* MX6Q_PAD_EIM_D18__I2C3_SDA */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D18__PL301_PER1_HBURST_2 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 1, 0x0804, 0), /* MX6Q_PAD_EIM_D19__ECSPI1_SS1 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 3, 0x08C8, 0), /* MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 4, 0x091C, 0), /* MX6Q_PAD_EIM_D19__UART1_CTS */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D19__EPIT1_EPITO */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D19__PL301_PER1_HRESP */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 1, 0x0824, 0), /* MX6Q_PAD_EIM_D20__ECSPI4_SS0 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 3, 0x08C4, 0), /* MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 4, 0x091C, 1), /* MX6Q_PAD_EIM_D20__UART1_RTS */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D20__GPIO_3_20 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D20__EPIT2_EPITO */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D21__ECSPI4_SCLK */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 3, 0x08B4, 0), /* MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 4, 0x0944, 0), /* MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D21__GPIO_3_21 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 6, 0x0898, 0), /* MX6Q_PAD_EIM_D21__I2C1_SCL */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 7, 0x0914, 0), /* MX6Q_PAD_EIM_D21__SPDIF_IN1 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D22__ECSPI4_MISO */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 3, 0x08B0, 0), /* MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D22__SPDIF_OUT1 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D22__PL301_PER1_HWRITE */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 2, 0x092C, 0), /* MX6Q_PAD_EIM_D23__UART3_CTS */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 3, 0x0000, 0), /* MX6Q_PAD_EIM_D23__UART1_DCD */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 4, 0x08D8, 0), /* MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D23__GPIO_3_23 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__ECSPI4_RDY */
+        IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 2, 0x092C, 1), /* MX6Q_PAD_EIM_EB3__UART3_RTS */
+        IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 3, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__UART1_RI */
+        IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 4, 0x08DC, 0), /* MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC */
+        IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__GPIO_2_31 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D24__ECSPI4_SS2 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D24__UART3_TXD */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 3, 0x0808, 0), /* MX6Q_PAD_EIM_D24__ECSPI1_SS2 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D24__ECSPI2_SS2 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D24__GPIO_3_24 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 6, 0x07D8, 0), /* MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D24__UART1_DTR */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D25__ECSPI4_SS3 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 2, 0x0930, 1), /* MX6Q_PAD_EIM_D25__UART3_RXD */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 3, 0x080C, 0), /* MX6Q_PAD_EIM_D25__ECSPI1_SS3 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D25__ECSPI2_SS3 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D25__GPIO_3_25 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 6, 0x07D4, 0), /* MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D25__UART1_DSR */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 3, 0x08C0, 0), /* MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D26__UART2_TXD */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D26__GPIO_3_26 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D26__IPU1_SISG_2 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 3, 0x08BC, 0), /* MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 4, 0x0928, 1), /* MX6Q_PAD_EIM_D27__UART2_RXD */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D27__GPIO_3_27 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D27__IPU1_SISG_3 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 1, 0x089C, 0), /* MX6Q_PAD_EIM_D28__I2C1_SDA */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D28__ECSPI4_MOSI */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 3, 0x08B8, 0), /* MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 4, 0x0924, 0), /* MX6Q_PAD_EIM_D28__UART2_CTS */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D28__GPIO_3_28 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 2, 0x0824, 1), /* MX6Q_PAD_EIM_D29__ECSPI4_SS0 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 4, 0x0924, 1), /* MX6Q_PAD_EIM_D29__UART2_RTS */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D29__GPIO_3_29 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 6, 0x08E4, 0), /* MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 3, 0x0000, 0), /* MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 4, 0x092C, 2), /* MX6Q_PAD_EIM_D30__UART3_CTS */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D30__GPIO_3_30 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 6, 0x0948, 0), /* MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D30__PL301_PER1_HPROT_0 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 3, 0x0000, 0), /* MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 4, 0x092C, 3), /* MX6Q_PAD_EIM_D31__UART3_RTS */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D31__GPIO_3_31 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR */
+        IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D31__PL301_PER1_HPROT_1 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 2, 0x08D4, 1), /* MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A24__IPU2_SISG_2 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A24__IPU1_SISG_2 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A24__GPIO_5_4 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A24__PL301_PER1_HPROT_2 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 2, 0x08D0, 1), /* MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A23__IPU2_SISG_3 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A23__IPU1_SISG_3 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A23__GPIO_6_6 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A23__PL301_PER1_HPROT_3 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 2, 0x08CC, 1), /* MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A22__GPIO_2_16 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 2, 0x08C8, 1), /* MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A21__RESERVED_RESERVED */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_OUT_18 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A21__GPIO_2_17 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 2, 0x08C4, 1), /* MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A20__RESERVED_RESERVED */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_OUT_19 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A20__GPIO_2_18 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 2, 0x08C0, 1), /* MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A19__RESERVED_RESERVED */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_OUT_20 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A19__GPIO_2_19 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 2, 0x08BC, 1), /* MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A18__RESERVED_RESERVED */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_OUT_21 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A18__GPIO_2_20 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 2, 0x08B8, 1), /* MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A17__RESERVED_RESERVED */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_OUT_22 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A17__GPIO_2_21 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 2, 0x08E0, 1), /* MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_OUT_23 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A16__GPIO_2_22 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 2, 0x0810, 0), /* MX6Q_PAD_EIM_CS0__ECSPI2_SCLK */
+        IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_OUT_24 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__GPIO_2_23 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 6, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 2, 0x0818, 0), /* MX6Q_PAD_EIM_CS1__ECSPI2_MOSI */
+        IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 4, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_OUT_25 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__GPIO_2_24 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 0, 0x0000, 0), /* MX6Q_PAD_EIM_OE__WEIM_WEIM_OE */
+        IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 1, 0x0000, 0), /* MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 2, 0x0814, 0), /* MX6Q_PAD_EIM_OE__ECSPI2_MISO */
+        IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 4, 0x0000, 0), /* MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_OUT_26 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 5, 0x0000, 0), /* MX6Q_PAD_EIM_OE__GPIO_2_25 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 6, 0x0000, 0), /* MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 0, 0x0000, 0), /* MX6Q_PAD_EIM_RW__WEIM_WEIM_RW */
+        IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 1, 0x0000, 0), /* MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 2, 0x081C, 0), /* MX6Q_PAD_EIM_RW__ECSPI2_SS0 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 4, 0x0000, 0), /* MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_OUT_27 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 5, 0x0000, 0), /* MX6Q_PAD_EIM_RW__GPIO_2_26 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 6, 0x0000, 0), /* MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 7, 0x0000, 0), /* MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 0, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA */
+        IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 1, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 2, 0x0820, 0), /* MX6Q_PAD_EIM_LBA__ECSPI2_SS1 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 5, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__GPIO_2_27 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 6, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 7, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 2, 0x08B4, 1), /* MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_OUT_0 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 4, 0x07F0, 0), /* MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY */
+        IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__GPIO_2_28 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 0, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 1, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 2, 0x08B0, 1), /* MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 3, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY__OUT_1 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 5, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__GPIO_2_29 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 6, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 7, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY__OUT_2 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__GPIO_3_0 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_OUT_3 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__USBPHY1_TX_LS_MODE */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__GPIO_3_1 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_OUT_4 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__USBPHY1_TX_HS_MODE */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__GPIO_3_2 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_OUT_5 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__USBPHY1_TX_HIZ */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__GPIO_3_3 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_OUT_6 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TX_EN */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__GPIO_3_4 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_OUT_7 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TX_DP */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__GPIO_3_5 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_OUT_8 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TX_DN */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__GPIO_3_6 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_OUT_9 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__GPIO_3_7 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_OUT_10 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__GPIO_3_8 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_OUT_11 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__GPIO_3_9 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 2, 0x08D8, 1), /* MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_OUT12 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__GPIO_3_10 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 2, 0x08DC, 1), /* MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_OUT13 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__SDMA_DBG_EVT_CHN_6 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__GPIO_3_11 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 2, 0x08E4, 1), /* MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_OUT14 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_3 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__GPIO_3_12 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 2, 0x07EC, 1), /* MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_OUT15 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_4 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__GPIO_3_13 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_OUT16 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_5 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__GPIO_3_14 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_OUT17 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__GPIO_3_15 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 0, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT */
+        IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 1, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B */
+        IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 5, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__GPIO_5_0 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 6, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 7, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_BCLK, 0x046C, 0x0158, 0, 0x0000, 0), /* MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK */
+        IMX_PIN_REG(MX6Q_PAD_EIM_BCLK, 0x046C, 0x0158, 1, 0x0000, 0), /* MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_BCLK, 0x046C, 0x0158, 5, 0x0000, 0), /* MX6Q_PAD_EIM_BCLK__GPIO_6_31 */
+        IMX_PIN_REG(MX6Q_PAD_EIM_BCLK, 0x046C, 0x0158, 6, 0x0000, 0), /* MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 */
+        IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 0, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DSP_CLK */
+        IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 1, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DSP_CLK */
+        IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 3, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__MIPI_CR_DPY_OT28 */
+        IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 4, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__SDMA_DBG_CR_STA0 */
+        IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 5, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 */
+        IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 6, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__MMDC_DEBUG_0 */
+        IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 0, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 */
+        IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 1, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 */
+        IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 2, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC */
+        IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 3, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__MIPI_CR_DPHY_OUT_29 */
+        IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 4, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__SDMA_DBG_CORE_STA_1 */
+        IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 5, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__GPIO_4_17 */
+        IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 6, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 */
+        IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 0, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 */
+        IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 1, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 */
+        IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 2, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD */
+        IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 3, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__MIPI_CR_DPHY_OUT_30 */
+        IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 4, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__SDMA_DBG_CORE_STA_2 */
+        IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 5, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__GPIO_4_18 */
+        IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 6, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__MMDC_DEBUG_2 */
+        IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 7, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__PL301_PER1_HADDR_9 */
+        IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 0, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 */
+        IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 1, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 */
+        IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 2, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS */
+        IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 3, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_OUT31 */
+        IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 4, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__SDMA_DBG_CORE_STA_3 */
+        IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 5, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__GPIO_4_19 */
+        IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 6, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 */
+        IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 7, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__PL301_PER1_HADDR_10 */
+        IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 0, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 */
+        IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 1, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 */
+        IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 2, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD */
+        IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 3, 0x094C, 0), /* MX6Q_PAD_DI0_PIN4__USDHC1_WP */
+        IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 4, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD */
+        IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 5, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__GPIO_4_20 */
+        IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 6, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 */
+        IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 7, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__PL301_PER1_HADDR_11 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DBG_0 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__SDMA_DBG_CORE_RUN */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__GPIO_4_21 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DBG_1 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__SDMA_DBG_EVT_CHNSL */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__GPIO_4_22 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__MMDC_DEBUG_6 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__PL301_PER1_HADR_12 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DBG_2 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__GPIO_4_23 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__MMDC_DEBUG_7 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__PL301_PER1_HADR_13 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DBG_3 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__SDMA_DBG_BUS_ERROR */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__GPIO_4_24 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DBG_8 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__PL301_PER1_HADR_14 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DBG_4 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__GPIO_4_25 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__PL301_PER1_HADR_15 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__SDMA_DBG_MCH_DMBUS */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__GPIO_4_26 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__MMDC_DEBUG_10 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__PL301_PER1_HADR_16 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__SDMA_DBG_RTBUF_WRT */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__GPIO_4_27 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__MMDC_DEBUG_11 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__PL301_PER1_HADR_17 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DBG_5 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__SDMA_DBG_EVT_CHN_0 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__GPIO_4_28 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__MMDC_DEBUG_12 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__PL301_PER1_HADR_18 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__PWM1_PWMO */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__SDMA_DBG_EVT_CHN_1 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__GPIO_4_29 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__MMDC_DEBUG_13 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__PL301_PER1_HADR_19 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__PWM2_PWMO */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__SDMA_DBG_EVT_CHN_2 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__GPIO_4_30 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__MMDC_DEBUG_14 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__PL301_PER1_HADR_20 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__USDHC1_DBG_6 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__SDMA_DBG_EVT_CHN3 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__GPIO_4_31 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__MMDC_DEBUG_15 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__PL301_PER1_HADR21 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DBG7 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__SDMA_DBG_EVT_CHN4 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__GPIO_5_5 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__MMDC_DEBUG_16 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__PL301_PER1_HADR22 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__SDMA_DBG_EVT_CHN5 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__GPIO_5_6 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__MMDC_DEBUG_17 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__PL301_PER1_HADR23 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 3, 0x07D8, 1), /* MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__SDMA_DBG_EVT_CHN0 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__GPIO_5_7 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__MMDC_DEBUG_18 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__PL301_PER1_HADR24 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 3, 0x07D4, 1), /* MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__SDMA_DBG_EVT_CHN1 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__GPIO_5_8 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__MMDC_DEBUG_19 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 2, 0x0804, 1), /* MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 3, 0x0820, 1), /* MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__SDMA_DBG_EVT_CHN2 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__GPIO_5_9 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__MMDC_DEBUG_20 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__PL301_PER1_HADR25 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 2, 0x0818, 1), /* MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 3, 0x07DC, 0), /* MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 4, 0x090C, 0), /* MX6Q_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__GPIO_5_10 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__MMDC_DEBUG_21 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__PL301_PER1_HADR26 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 2, 0x0814, 1), /* MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 3, 0x07D0, 0), /* MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 4, 0x0910, 0), /* MX6Q_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__GPIO_5_11 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__MMDC_DEBUG_22 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__PL301_PER1_HADR27 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 2, 0x081C, 1), /* MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 3, 0x07E0, 0), /* MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 4, 0x07C0, 0), /* MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__GPIO_5_12 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__MMDC_DEBUG_23 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 2, 0x0810, 1), /* MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 3, 0x07CC, 0), /* MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 4, 0x07BC, 0), /* MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__GPIO_5_13 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__MMDC_DEBUG_24 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 2, 0x07F4, 1), /* MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 3, 0x07C4, 0), /* MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__SDMA_DBG_EVT_CHN7 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__GPIO_5_14 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__MMDC_DEBUG_25 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__PL301_PER1_HADR28 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 2, 0x07FC, 1), /* MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 3, 0x07B8, 1), /* MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__SDMA_DBG_BUS_DEV0 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__GPIO_5_15 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__MMDC_DEBUG_26 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__PL301_PER1_HADR29 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 2, 0x07F8, 1), /* MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 3, 0x07C8, 1), /* MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__SDMA_DBG_BUS_DEV1 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__GPIO_5_16 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__MMDC_DEBUG_27 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__PL301_PER1_HADR30 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 2, 0x0800, 1), /* MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 3, 0x07B4, 1), /* MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__SDMA_DBG_BUS_DEV2 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__GPIO_5_17 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__MMDC_DEBUG_28 */
+        IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__PL301_PER1_HADR31 */
+        IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 0, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED */
+        IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 1, 0x0840, 0), /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */
+        IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 2, 0x086C, 0), /* MX6Q_PAD_ENET_MDIO__ESAI1_SCKR */
+        IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 3, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEV3 */
+        IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 4, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__ENET_1588_EVT1_OUT */
+        IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 5, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__GPIO_1_22 */
+        IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 6, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK */
+        IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 0, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__RESERVED_RSRVED */
+        IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 1, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
+        IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 2, 0x085C, 0), /* MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR */
+        IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 3, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__SDMA_DBGBUS_DEV4 */
+        IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 5, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 */
+        IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 6, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK */
+        IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 7, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__USBPHY1_RX_SQH */
+        IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 1, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__ENET_RX_ER */
+        IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 2, 0x0864, 0), /* MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR */
+        IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 3, 0x0914, 1), /* MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 */
+        IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 4, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__ENET_1588_EVT2_OUT */
+        IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 5, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__GPIO_1_24 */
+        IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 6, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__PHY_TDI */
+        IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 7, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__USBPHY1_RX_HS_RXD */
+        IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 0, 0x0000, 0), /* MX6Q_PAD_ENET_CRS_DV__RESERVED_RSRVED */
+        IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 1, 0x0858, 1), /* MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN */
+        IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 2, 0x0870, 0), /* MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT */
+        IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 3, 0x0918, 1), /* MX6Q_PAD_ENET_CRS_DV__SPDIF_EXTCLK */
+        IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 5, 0x0000, 0), /* MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 */
+        IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 6, 0x0000, 0), /* MX6Q_PAD_ENET_CRS_DV__PHY_TDO */
+        IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 7, 0x0000, 0), /* MX6Q_PAD_ENET_CRS_DV__USBPHY1_RX_FS_RXD */
+        IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 0, 0x0908, 0), /* MX6Q_PAD_ENET_RXD1__MLB_MLBSIG */
+        IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 1, 0x084C, 1), /* MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 */
+        IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 2, 0x0860, 0), /* MX6Q_PAD_ENET_RXD1__ESAI1_FST */
+        IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 4, 0x0000, 0), /* MX6Q_PAD_ENET_RXD1__ENET_1588_EVT3_OUT */
+        IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 5, 0x0000, 0), /* MX6Q_PAD_ENET_RXD1__GPIO_1_26 */
+        IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 6, 0x0000, 0), /* MX6Q_PAD_ENET_RXD1__PHY_TCK */
+        IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 7, 0x0000, 0), /* MX6Q_PAD_ENET_RXD1__USBPHY1_RX_DISCON */
+        IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 0, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT */
+        IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 1, 0x0848, 1), /* MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 */
+        IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 2, 0x0868, 0), /* MX6Q_PAD_ENET_RXD0__ESAI1_HCKT */
+        IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 3, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 */
+        IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 5, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__GPIO_1_27 */
+        IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 6, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__PHY_TMS */
+        IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 7, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__USBPHY1_PLL_CK20DIV */
+        IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 0, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__RESERVED_RSRVED */
+        IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 1, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__ENET_TX_EN */
+        IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 2, 0x0880, 0), /* MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 */
+        IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 5, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__GPIO_1_28 */
+        IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 6, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI */
+        IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 7, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__USBPHY2_RX_SQH */
+        IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 0, 0x0900, 0), /* MX6Q_PAD_ENET_TXD1__MLB_MLBCLK */
+        IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 1, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 */
+        IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 2, 0x087C, 0), /* MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 */
+        IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 4, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN */
+        IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 5, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__GPIO_1_29 */
+        IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 6, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO */
+        IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 7, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__USBPHY2_RX_HS_RXD */
+        IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 0, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__RESERVED_RSRVED */
+        IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 1, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 */
+        IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 2, 0x0884, 0), /* MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 */
+        IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 5, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__GPIO_1_30 */
+        IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 6, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK */
+        IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 7, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__USBPHY2_RX_FS_RXD */
+        IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 0, 0x0904, 0), /* MX6Q_PAD_ENET_MDC__MLB_MLBDAT */
+        IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 1, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__ENET_MDC */
+        IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 2, 0x0888, 0), /* MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 */
+        IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 4, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN */
+        IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 5, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__GPIO_1_31 */
+        IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 6, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__SATA_PHY_TMS */
+        IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 7, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__USBPHY2_RX_DISCON */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D40, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D41, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D42, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D43, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D44, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D45, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D46, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D47, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS5, 0x050C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_DQM5, 0x0510, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D32, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D33, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D34, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D35, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D36, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D37, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D38, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D39, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_DQM4, 0x0514, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS4, 0x0518, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D24, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D25, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D26, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D27, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D28, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D29, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS3, 0x051C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D30, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D31, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_DQM3, 0x0520, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D16, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D17, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D18, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D19, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D20, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D21, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D22, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS2, 0x0524, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D23, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_DQM2, 0x0528, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_A0, 0x052C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_A1, 0x0530, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_A2, 0x0534, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_A3, 0x0538, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_A4, 0x053C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_A5, 0x0540, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_A6, 0x0544, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_A7, 0x0548, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_A8, 0x054C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_A9, 0x0550, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_A10, 0x0554, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_A11, 0x0558, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_A12, 0x055C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_A13, 0x0560, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_A14, 0x0564, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_A15, 0x0568, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_CAS, 0x056C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_CS0, 0x0570, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_CS1, 0x0574, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_RAS, 0x0578, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_RESET, 0x057C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_SDBA0, 0x0580, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_SDBA1, 0x0584, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_SDCLK_0, 0x0588, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_SDBA2, 0x058C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_SDCKE0, 0x0590, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_SDCLK_1, 0x0594, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_SDCKE1, 0x0598, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_SDODT0, 0x059C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_SDODT1, 0x05A0, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_SDWE, 0x05A4, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D0, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D1, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D2, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D3, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D4, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D5, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS0, 0x05A8, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D6, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D7, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_DQM0, 0x05AC, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D8, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D9, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D10, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D11, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D12, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D13, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D14, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS1, 0x05B0, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D15, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_DQM1, 0x05B4, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D48, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D49, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D50, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D51, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D52, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D53, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D54, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D55, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS6, 0x05B8, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_DQM6, 0x05BC, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D56, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS7, 0x05C0, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D57, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D58, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D59, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D60, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_DQM7, 0x05C4, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D61, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D62, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 */
+        IMX_PIN_REG(MX6Q_PAD_DRAM_D63, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 */
+        IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 0, 0x07F4, 2), /* MX6Q_PAD_KEY_COL0__ECSPI1_SCLK */
+        IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 1, 0x0854, 1), /* MX6Q_PAD_KEY_COL0__ENET_RDATA_3 */
+        IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 2, 0x07DC, 1), /* MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC */
+        IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__KPP_COL_0 */
+        IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 4, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__UART4_TXD */
+        IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__GPIO_4_6 */
+        IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 6, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT */
+        IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST */
+        IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 0, 0x07FC, 2), /* MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI */
+        IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 1, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 */
+        IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 2, 0x07D0, 1), /* MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */
+        IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__KPP_ROW_0 */
+        IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 4, 0x0938, 1), /* MX6Q_PAD_KEY_ROW0__UART4_RXD */
+        IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__GPIO_4_7 */
+        IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 6, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT */
+        IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__PL301_PER1_HADR_0 */
+        IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 0, 0x07F8, 2), /* MX6Q_PAD_KEY_COL1__ECSPI1_MISO */
+        IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 1, 0x0840, 1), /* MX6Q_PAD_KEY_COL1__ENET_MDIO */
+        IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 2, 0x07E0, 1), /* MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */
+        IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__KPP_COL_1 */
+        IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 4, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__UART5_TXD */
+        IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__GPIO_4_8 */
+        IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 6, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__USDHC1_VSELECT */
+        IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__PL301MX_PER1_HADR_1 */
+        IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 0, 0x0800, 2), /* MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 */
+        IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 1, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__ENET_COL */
+        IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 2, 0x07CC, 1), /* MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */
+        IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__KPP_ROW_1 */
+        IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 4, 0x0940, 1), /* MX6Q_PAD_KEY_ROW1__UART5_RXD */
+        IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__GPIO_4_9 */
+        IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 6, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT */
+        IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__PL301_PER1_HADDR_2 */
+        IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 0, 0x0804, 2), /* MX6Q_PAD_KEY_COL2__ECSPI1_SS1 */
+        IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 1, 0x0850, 1), /* MX6Q_PAD_KEY_COL2__ENET_RDATA_2 */
+        IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 2, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__CAN1_TXCAN */
+        IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__KPP_COL_2 */
+        IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 4, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__ENET_MDC */
+        IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__GPIO_4_10 */
+        IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 6, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__USBOH3_H1_PWRCTL_WKP */
+        IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__PL301_PER1_HADDR_3 */
+        IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 0, 0x0808, 1), /* MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 */
+        IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 1, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 */
+        IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 2, 0x07E4, 0), /* MX6Q_PAD_KEY_ROW2__CAN1_RXCAN */
+        IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__KPP_ROW_2 */
+        IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 4, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT */
+        IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__GPIO_4_11 */
+        IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 6, 0x088C, 1), /* MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE */
+        IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__PL301_PER1_HADR_4 */
+        IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 0, 0x080C, 1), /* MX6Q_PAD_KEY_COL3__ECSPI1_SS3 */
+        IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 1, 0x0000, 0), /* MX6Q_PAD_KEY_COL3__ENET_CRS */
+        IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 2, 0x0890, 1), /* MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL */
+        IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL3__KPP_COL_3 */
+        IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 4, 0x08A0, 1), /* MX6Q_PAD_KEY_COL3__I2C2_SCL */
+        IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL3__GPIO_4_12 */
+        IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 6, 0x0914, 2), /* MX6Q_PAD_KEY_COL3__SPDIF_IN1 */
+        IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL3__PL301_PER1_HADR_5 */
+        IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 0, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT */
+        IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 1, 0x07B0, 0), /* MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK */
+        IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 2, 0x0894, 1), /* MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA */
+        IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__KPP_ROW_3 */
+        IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 4, 0x08A4, 1), /* MX6Q_PAD_KEY_ROW3__I2C2_SDA */
+        IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__GPIO_4_13 */
+        IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 6, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT */
+        IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__PL301_PER1_HADR_6 */
+        IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 0, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__CAN2_TXCAN */
+        IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 1, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__IPU1_SISG_4 */
+        IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 2, 0x0944, 1), /* MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC */
+        IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__KPP_COL_4 */
+        IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 4, 0x093C, 0), /* MX6Q_PAD_KEY_COL4__UART5_RTS */
+        IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__GPIO_4_14 */
+        IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 6, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__MMDC_DEBUG_49 */
+        IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__PL301_PER1_HADDR_7 */
+        IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 0, 0x07E8, 0), /* MX6Q_PAD_KEY_ROW4__CAN2_RXCAN */
+        IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 1, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 */
+        IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 2, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR */
+        IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__KPP_ROW_4 */
+        IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 4, 0x093C, 1), /* MX6Q_PAD_KEY_ROW4__UART5_CTS */
+        IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__GPIO_4_15 */
+        IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 6, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__MMDC_DEBUG_50 */
+        IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__PL301_PER1_HADR_8 */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 0, 0x0000, 0), /* MX6Q_PAD_GPIO_0__CCM_CLKO */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 2, 0x08E8, 0), /* MX6Q_PAD_GPIO_0__KPP_COL_5 */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 3, 0x07B0, 1), /* MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_0__EPIT1_EPITO */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_0__GPIO_1_0 */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_0__SNVS_HP_WRAP_SNVS_VIO5 */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 0, 0x086C, 1), /* MX6Q_PAD_GPIO_1__ESAI1_SCKR */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_1__WDOG2_WDOG_B */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 2, 0x08F4, 0), /* MX6Q_PAD_GPIO_1__KPP_ROW_5 */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_1__PWM2_PWMO */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_1__GPIO_1_1 */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_1__USDHC1_CD */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_1__SRC_TESTER_ACK */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 0, 0x085C, 1), /* MX6Q_PAD_GPIO_9__ESAI1_FSR */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_9__WDOG1_WDOG_B */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 2, 0x08EC, 0), /* MX6Q_PAD_GPIO_9__KPP_COL_6 */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_9__CCM_REF_EN_B */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_9__PWM1_PWMO */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_9__GPIO_1_9 */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 6, 0x094C, 1), /* MX6Q_PAD_GPIO_9__USDHC1_WP */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_9__SRC_EARLY_RST */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 0, 0x0864, 1), /* MX6Q_PAD_GPIO_3__ESAI1_HCKR */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_3__OBSERVE_MUX_INT_OUT0 */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 2, 0x08A8, 1), /* MX6Q_PAD_GPIO_3__I2C3_SCL */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_3__ANATOP_24M_OUT */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_3__CCM_CLKO2 */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_3__GPIO_1_3 */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 6, 0x0948, 1), /* MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 7, 0x0900, 1), /* MX6Q_PAD_GPIO_3__MLB_MLBCLK */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 0, 0x0870, 1), /* MX6Q_PAD_GPIO_6__ESAI1_SCKT */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_6__OBSERVE_MUX_INT_OUT1 */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 2, 0x08AC, 1), /* MX6Q_PAD_GPIO_6__I2C3_SDA */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_6__GPIO_1_6 */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_6__USDHC2_LCTL */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 7, 0x0908, 1), /* MX6Q_PAD_GPIO_6__MLB_MLBSIG */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 0, 0x0860, 1), /* MX6Q_PAD_GPIO_2__ESAI1_FST */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_2__OBSERVE_MUX_INT_OUT2 */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 2, 0x08F8, 1), /* MX6Q_PAD_GPIO_2__KPP_ROW_6 */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_2__GPIO_1_2 */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_2__USDHC2_WP */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 7, 0x0904, 1), /* MX6Q_PAD_GPIO_2__MLB_MLBDAT */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 0, 0x0868, 1), /* MX6Q_PAD_GPIO_4__ESAI1_HCKT */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_4__OBSERVE_MUX_INT_OUT3 */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 2, 0x08F0, 1), /* MX6Q_PAD_GPIO_4__KPP_COL_7 */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_4__GPIO_1_4 */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_4__USDHC2_CD */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_4__OCOTP_CRL_WRAR_FUSE_LA */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 0, 0x087C, 1), /* MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_5__OBSERVE_MUX_INT_OUT4 */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 2, 0x08FC, 1), /* MX6Q_PAD_GPIO_5__KPP_ROW_7 */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_5__CCM_CLKO */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_5__GPIO_1_5 */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 6, 0x08A8, 2), /* MX6Q_PAD_GPIO_5__I2C3_SCL */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_5__CHEETAH_EVENTI */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 0, 0x0884, 1), /* MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_7__ECSPI5_RDY */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 2, 0x0000, 0), /* MX6Q_PAD_GPIO_7__EPIT1_EPITO */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_7__CAN1_TXCAN */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_7__UART2_TXD */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_7__GPIO_1_7 */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_7__SPDIF_PLOCK */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HST_MODE */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 0, 0x0888, 1), /* MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 2, 0x0000, 0), /* MX6Q_PAD_GPIO_8__EPIT2_EPITO */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 3, 0x07E4, 1), /* MX6Q_PAD_GPIO_8__CAN1_RXCAN */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 4, 0x0928, 3), /* MX6Q_PAD_GPIO_8__UART2_RXD */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_8__GPIO_1_8 */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_8__SPDIF_SRCLK */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_8__USBOH3_OTG_PWRCTL_WAK */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 0, 0x0880, 1), /* MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 2, 0x083C, 1), /* MX6Q_PAD_GPIO_16__ENET_ETHERNET_REF_OUT */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_16__USDHC1_LCTL */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 4, 0x0914, 3), /* MX6Q_PAD_GPIO_16__SPDIF_IN1 */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_16__GPIO_7_11 */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 6, 0x08AC, 2), /* MX6Q_PAD_GPIO_16__I2C3_SDA */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_16__SJC_DE_B */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 0, 0x0874, 0), /* MX6Q_PAD_GPIO_17__ESAI1_TX0 */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 2, 0x07F0, 1), /* MX6Q_PAD_GPIO_17__CCM_PMIC_RDY */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 3, 0x090C, 1), /* MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_17__SPDIF_OUT1 */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_17__GPIO_7_12 */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_17__SJC_JTAG_ACT */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 0, 0x0878, 0), /* MX6Q_PAD_GPIO_18__ESAI1_TX1 */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 1, 0x0844, 1), /* MX6Q_PAD_GPIO_18__ENET_RX_CLK */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 2, 0x0000, 0), /* MX6Q_PAD_GPIO_18__USDHC3_VSELECT */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 3, 0x0910, 1), /* MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 4, 0x07B0, 2), /* MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_18__GPIO_7_13 */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_18__SNVS_HP_WRA_SNVS_VIO5 */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 0, 0x08E8, 1), /* MX6Q_PAD_GPIO_19__KPP_COL_5 */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 2, 0x0000, 0), /* MX6Q_PAD_GPIO_19__SPDIF_OUT1 */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_19__CCM_CLKO */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_19__ECSPI1_RDY */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_19__GPIO_4_5 */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_19__ENET_TX_ER */
+        IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_19__SRC_INT_BOOT */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_MUX_12 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK___MMDC_DEBUG_29 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_MUX_13 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 3, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__CCM_CLKO */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__GPIO_5_19 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DA_EN */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_MUX_14 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__MMDC_DEBUG_31 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_MUX_15 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__MMDC_DEBUG_32 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 2, 0x07F4, 3), /* MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 3, 0x08E8, 2), /* MX6Q_PAD_CSI0_DAT4__KPP_COL_5 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__GPIO_5_22 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__MMDC_DEBUG_43 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 2, 0x07FC, 3), /* MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 3, 0x08F4, 1), /* MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__GPIO_5_23 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 2, 0x07F8, 3), /* MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 3, 0x08EC, 1), /* MX6Q_PAD_CSI0_DAT6__KPP_COL_6 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__GPIO_5_24 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 2, 0x0800, 3), /* MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 3, 0x08F8, 2), /* MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__GPIO_5_25 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 2, 0x0810, 2), /* MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 3, 0x08F0, 2), /* MX6Q_PAD_CSI0_DAT8__KPP_COL_7 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 4, 0x089C, 1), /* MX6Q_PAD_CSI0_DAT8__I2C1_SDA */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__GPIO_5_26 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 2, 0x0818, 2), /* MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 3, 0x08FC, 2), /* MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 4, 0x0898, 1), /* MX6Q_PAD_CSI0_DAT9__I2C1_SCL */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__GPIO_5_27 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 2, 0x0814, 2), /* MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 3, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__GPIO_5_28 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 2, 0x081C, 2), /* MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 3, 0x0920, 1), /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__GPIO_5_29 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_MUX_16 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 3, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__UART4_TXD */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__GPIO_5_30 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_MUX_17 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 3, 0x0938, 3), /* MX6Q_PAD_CSI0_DAT13__UART4_RXD */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__GPIO_5_31 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_MUX_18 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 3, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__UART5_TXD */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__GPIO_6_0 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_MUX_19 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 3, 0x0940, 3), /* MX6Q_PAD_CSI0_DAT15__UART5_RXD */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__GPIO_6_1 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_MUX_20 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 3, 0x0934, 0), /* MX6Q_PAD_CSI0_DAT16__UART4_RTS */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__GPIO_6_2 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_MUX_21 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 3, 0x0934, 1), /* MX6Q_PAD_CSI0_DAT17__UART4_CTS */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__GPIO_6_3 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_MUX_22 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 3, 0x093C, 2), /* MX6Q_PAD_CSI0_DAT18__UART5_RTS */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__GPIO_6_4 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_MUX_23 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 3, 0x093C, 3), /* MX6Q_PAD_CSI0_DAT19__UART5_CTS */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__GPIO_6_5 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 */
+        IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__ANATOP_TESTO_9 */
+        IMX_PIN_REG(MX6Q_PAD_JTAG_TMS, 0x0678, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TMS__SJC_TMS */
+        IMX_PIN_REG(MX6Q_PAD_JTAG_MOD, 0x067C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_MOD__SJC_MOD */
+        IMX_PIN_REG(MX6Q_PAD_JTAG_TRSTB, 0x0680, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB */
+        IMX_PIN_REG(MX6Q_PAD_JTAG_TDI, 0x0684, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TDI__SJC_TDI */
+        IMX_PIN_REG(MX6Q_PAD_JTAG_TCK, 0x0688, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TCK__SJC_TCK */
+        IMX_PIN_REG(MX6Q_PAD_JTAG_TDO, 0x068C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TDO__SJC_TDO */
+        IMX_PIN_REG(MX6Q_PAD_LVDS1_TX3_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 */
+        IMX_PIN_REG(MX6Q_PAD_LVDS1_TX2_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 */
+        IMX_PIN_REG(MX6Q_PAD_LVDS1_CLK_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK */
+        IMX_PIN_REG(MX6Q_PAD_LVDS1_TX1_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 */
+        IMX_PIN_REG(MX6Q_PAD_LVDS1_TX0_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 */
+        IMX_PIN_REG(MX6Q_PAD_LVDS0_TX3_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 */
+        IMX_PIN_REG(MX6Q_PAD_LVDS0_CLK_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK */
+        IMX_PIN_REG(MX6Q_PAD_LVDS0_TX2_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 */
+        IMX_PIN_REG(MX6Q_PAD_LVDS0_TX1_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 */
+        IMX_PIN_REG(MX6Q_PAD_LVDS0_TX0_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 */
+        IMX_PIN_REG(MX6Q_PAD_TAMPER, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_TAMPER__SNVS_LP_WRAP_SNVS_TD1 */
+        IMX_PIN_REG(MX6Q_PAD_PMIC_ON_REQ, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_PMIC_ON_REQ__SNVS_LPWRAP_WKALM */
+        IMX_PIN_REG(MX6Q_PAD_PMIC_STBY_REQ, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_STBYRQ */
+        IMX_PIN_REG(MX6Q_PAD_POR_B, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_POR_B__SRC_POR_B */
+        IMX_PIN_REG(MX6Q_PAD_BOOT_MODE1, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 */
+        IMX_PIN_REG(MX6Q_PAD_RESET_IN_B, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_RESET_IN_B__SRC_RESET_B */
+        IMX_PIN_REG(MX6Q_PAD_BOOT_MODE0, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 */
+        IMX_PIN_REG(MX6Q_PAD_TEST_MODE, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_TEST_MODE__TCU_TEST_MODE */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 1, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__UART1_TXD */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__PCIE_CTRL_MUX_24 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__GPIO_6_17 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_IN_12 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__USBPHY2_CLK20DIV */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 1, 0x0920, 3), /* MX6Q_PAD_SD3_DAT6__UART1_RXD */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__PCIE_CTRL_MUX_25 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__GPIO_6_18 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_IN_13 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__ANATOP_TESTO_10 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 1, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__UART2_TXD */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__PCIE_CTRL_MUX_26 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__GPIO_7_0 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_IN_14 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__ANATOP_TESTO_11 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 1, 0x0928, 5), /* MX6Q_PAD_SD3_DAT4__UART2_RXD */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__PCIE_CTRL_MUX_27 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__GPIO_7_1 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_IN_15 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__ANATOP_TESTO_12 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 0, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
+        IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 1, 0x0924, 2), /* MX6Q_PAD_SD3_CMD__UART2_CTS */
+        IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 2, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__CAN1_TXCAN */
+        IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 3, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 4, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 5, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__GPIO_7_2 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 6, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_IN_16 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 7, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__ANATOP_TESTO_13 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 0, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
+        IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 1, 0x0924, 3), /* MX6Q_PAD_SD3_CLK__UART2_RTS */
+        IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 2, 0x07E4, 2), /* MX6Q_PAD_SD3_CLK__CAN1_RXCAN */
+        IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 3, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 4, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 5, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__GPIO_7_3 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 6, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_IN_17 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 7, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__ANATOP_TESTO_14 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 1, 0x091C, 2), /* MX6Q_PAD_SD3_DAT0__UART1_CTS */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__CAN2_TXCAN */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__GPIO_7_4 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_IN_18 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__ANATOP_TESTO_15 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 1, 0x091C, 3), /* MX6Q_PAD_SD3_DAT1__UART1_RTS */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 2, 0x07E8, 1), /* MX6Q_PAD_SD3_DAT1__CAN2_RXCAN */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__GPIO_7_5 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_IN_19 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__ANATOP_TESTI_0 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__PCIE_CTRL_MUX_28 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__GPIO_7_6 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_IN_20 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__ANATOP_TESTI_1 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 1, 0x092C, 4), /* MX6Q_PAD_SD3_DAT3__UART3_CTS */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__PCIE_CTRL_MUX_29 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__GPIO_7_7 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_IN_21 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__ANATOP_TESTI_2 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 0, 0x0000, 0), /* MX6Q_PAD_SD3_RST__USDHC3_RST */
+        IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 1, 0x092C, 5), /* MX6Q_PAD_SD3_RST__UART3_RTS */
+        IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 2, 0x0000, 0), /* MX6Q_PAD_SD3_RST__PCIE_CTRL_MUX_30 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 3, 0x0000, 0), /* MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 4, 0x0000, 0), /* MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 5, 0x0000, 0), /* MX6Q_PAD_SD3_RST__GPIO_7_8 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 6, 0x0000, 0), /* MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_IN_22 */
+        IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 7, 0x0000, 0), /* MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__PCIE_CTRL_MUX_31 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OT11 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OT11 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__GPIO_6_7 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_IN23 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__USDHC4_RST */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__PCIE_CTRL_MUX_0 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OT12 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OT12 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__GPIO_6_8 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__MIPI_CR_DPHY_IN_24 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__PCIE_CTRL__MUX_1 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFDOT13 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFDOT13 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__GPIO_6_9 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__MIPI_CR_DPHY_OUT32 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__PL301_PER1_HSIZE_0 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__PCIE_CTRL_MUX_2 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OT14 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OT14 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__GPIO_6_10 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__MIPI_CR_DPHY_OUT_33 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__PL301_PER1_HSIZE_1 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OT15 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OT15 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__PL301_PER1_HSIZE_2 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__PCIE_CTRL_MUX_3 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__PL301_PER1_HRDYOUT */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 2, 0x0874, 1), /* MX6Q_PAD_NANDF_CS2__ESAI1_TX0 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__CCM_CLKO2 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__GPIO_6_15 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 2, 0x0878, 1), /* MX6Q_PAD_NANDF_CS3__ESAI1_TX1 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__PCIE_CTRL_MUX_4 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__GPIO_6_16 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__TPSMP_CLK */
+        IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 0, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
+        IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 1, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
+        IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 2, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__UART3_TXD */
+        IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 4, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__PCIE_CTRL_MUX_5 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 5, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__GPIO_7_9 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 7, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR */
+        IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 0, 0x0000, 0), /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
+        IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 1, 0x0000, 0), /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
+        IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 2, 0x0930, 3), /* MX6Q_PAD_SD4_CLK__UART3_RXD */
+        IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 4, 0x0000, 0), /* MX6Q_PAD_SD4_CLK__PCIE_CTRL_MUX_6 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 5, 0x0000, 0), /* MX6Q_PAD_SD4_CLK__GPIO_7_10 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__USDHC1_DAT4 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__GPU3D_GPU_DBG_OUT_0 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT16 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT16 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__USDHC1_DAT5 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT1 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT17 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT17 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__USDHC1_DAT6 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__GPU3D_GPU_DBG_OUT_2 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT18 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT18 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__USDHC1_DAT7 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__GPU3D_GPU_DBG_OUT_3 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT19 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT19 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__GPIO_2_3 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__GPU3D_GPU_DBG_OUT_4 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT20 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT20 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__GPIO_2_4 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__GPU3D_GPU_DBG_OUT_5 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT21 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT21 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__GPIO_2_5 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__GPU3D_GPU_DBG_OUT_6 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT22 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT22 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__GPIO_2_6 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__GPU3D_GPU_DBG_OUT_7 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT23 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT23 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__GPIO_2_7 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 */
+        IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__RAWNAND_D8 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 2, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT24 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT24 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__GPIO_2_8 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__RAWNAND_D9 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 2, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__PWM3_PWMO */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT25 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT25 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__GPIO_2_9 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__RAWNAND_D10 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 2, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__PWM4_PWMO */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT26 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT26 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__GPIO_2_10 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__RAWNAND_D11 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT27 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT27 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__GPIO_2_11 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__RAWNAND_D12 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 2, 0x0928, 6), /* MX6Q_PAD_SD4_DAT4__UART2_RXD */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT28 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT28 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__GPIO_2_12 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__RAWNAND_D13 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 2, 0x0924, 4), /* MX6Q_PAD_SD4_DAT5__UART2_RTS */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT29 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT29 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__GPIO_2_13 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__RAWNAND_D14 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 2, 0x0924, 5), /* MX6Q_PAD_SD4_DAT6__UART2_CTS */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT30 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT30 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__GPIO_2_14 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__RAWNAND_D15 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 2, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__UART2_TXD */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT31 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT31 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__GPIO_2_15 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 */
+        IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 */
+        IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 0, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 */
+        IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 1, 0x0834, 1), /* MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 */
+        IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 2, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__PWM3_PWMO */
+        IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 3, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 */
+        IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 4, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__PCIE_CTRL_MUX_7 */
+        IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 5, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__GPIO_1_17 */
+        IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 6, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 */
+        IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 7, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__ANATOP_TESTO_8 */
+        IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 0, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 */
+        IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 1, 0x082C, 1), /* MX6Q_PAD_SD1_DAT0__ECSPI5_MISO */
+        IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 2, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__CAAM_WRAP_RNG_OSCOBS */
+        IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 3, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 */
+        IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 4, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__PCIE_CTRL_MUX_8 */
+        IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 5, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__GPIO_1_16 */
+        IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 6, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 */
+        IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 7, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__ANATOP_TESTO_7 */
+        IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 0, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 */
+        IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 1, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 */
+        IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 2, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 */
+        IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 3, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__PWM1_PWMO */
+        IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 4, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B */
+        IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 5, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__GPIO_1_21 */
+        IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 6, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB */
+        IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 7, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__ANATOP_TESTO_6 */
+        IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 0, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__USDHC1_CMD */
+        IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 1, 0x0830, 0), /* MX6Q_PAD_SD1_CMD__ECSPI5_MOSI */
+        IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 2, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__PWM4_PWMO */
+        IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 3, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 */
+        IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 5, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__GPIO_1_18 */
+        IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 7, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__ANATOP_TESTO_5 */
+        IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 0, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 */
+        IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 1, 0x0838, 1), /* MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 */
+        IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 2, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 */
+        IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 3, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__PWM2_PWMO */
+        IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 4, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B */
+        IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 5, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__GPIO_1_19 */
+        IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 6, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB */
+        IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 7, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__ANATOP_TESTO_4 */
+        IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 0, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__USDHC1_CLK */
+        IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 1, 0x0828, 0), /* MX6Q_PAD_SD1_CLK__ECSPI5_SCLK */
+        IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 2, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT */
+        IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 3, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__GPT_CLKIN */
+        IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 5, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__GPIO_1_20 */
+        IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 6, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__PHY_DTB_0 */
+        IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 7, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 */
+        IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 0, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */
+        IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 1, 0x0828, 1), /* MX6Q_PAD_SD2_CLK__ECSPI5_SCLK */
+        IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 2, 0x08E8, 3), /* MX6Q_PAD_SD2_CLK__KPP_COL_5 */
+        IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 3, 0x07C0, 1), /* MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS */
+        IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 4, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__PCIE_CTRL_MUX_9 */
+        IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 5, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__GPIO_1_10 */
+        IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 6, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__PHY_DTB_1 */
+        IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 7, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 */
+        IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 0, 0x0000, 0), /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */
+        IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 1, 0x0830, 1), /* MX6Q_PAD_SD2_CMD__ECSPI5_MOSI */
+        IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 2, 0x08F4, 2), /* MX6Q_PAD_SD2_CMD__KPP_ROW_5 */
+        IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 3, 0x07BC, 1), /* MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC */
+        IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 4, 0x0000, 0), /* MX6Q_PAD_SD2_CMD__PCIE_CTRL_MUX_10 */
+        IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 5, 0x0000, 0), /* MX6Q_PAD_SD2_CMD__GPIO_1_11 */
+        IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 0, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */
+        IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 1, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 */
+        IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 2, 0x08EC, 2), /* MX6Q_PAD_SD2_DAT3__KPP_COL_6 */
+        IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 3, 0x07C4, 1), /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
+        IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 4, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__PCIE_CTRL_MUX_11 */
+        IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__GPIO_1_12 */
+        IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__SJC_DONE */
+        IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__ANATOP_TESTO_3 */
+};
+
+/* Pad names for the pinmux subsystem */
+static const struct pinctrl_pin_desc imx6q_pinctrl_pads[] = {
+        IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT1),
+        IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT2),
+        IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT0),
+        IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TXC),
+        IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD0),
+        IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD1),
+        IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD2),
+        IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD3),
+        IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RX_CTL),
+        IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD0),
+        IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TX_CTL),
+        IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD1),
+        IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD2),
+        IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD3),
+        IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RXC),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A25),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB2),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D16),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D17),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D18),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D19),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D20),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D21),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D22),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D23),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB3),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D24),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D25),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D26),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D27),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D28),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D29),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D30),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D31),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A24),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A23),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A22),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A21),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A20),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A19),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A18),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A17),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A16),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_CS0),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_CS1),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_OE),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_RW),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_LBA),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB0),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB1),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA0),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA1),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA2),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA3),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA4),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA5),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA6),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA7),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA8),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA9),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA10),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA11),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA12),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA13),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA14),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA15),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_WAIT),
+        IMX_PINCTRL_PIN(MX6Q_PAD_EIM_BCLK),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DI0_DISP_CLK),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN15),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN2),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN3),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN4),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT0),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT1),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT2),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT3),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT4),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT5),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT6),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT7),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT8),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT9),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT10),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT11),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT12),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT13),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT14),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT15),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT16),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT17),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT18),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT19),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT20),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT21),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT22),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT23),
+        IMX_PINCTRL_PIN(MX6Q_PAD_ENET_MDIO),
+        IMX_PINCTRL_PIN(MX6Q_PAD_ENET_REF_CLK),
+        IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RX_ER),
+        IMX_PINCTRL_PIN(MX6Q_PAD_ENET_CRS_DV),
+        IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RXD1),
+        IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RXD0),
+        IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TX_EN),
+        IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TXD1),
+        IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TXD0),
+        IMX_PINCTRL_PIN(MX6Q_PAD_ENET_MDC),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D40),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D41),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D42),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D43),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D44),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D45),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D46),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D47),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS5),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM5),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D32),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D33),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D34),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D35),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D36),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D37),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D38),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D39),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM4),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS4),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D24),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D25),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D26),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D27),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D28),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D29),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS3),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D30),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D31),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM3),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D16),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D17),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D18),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D19),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D20),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D21),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D22),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS2),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D23),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM2),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A0),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A1),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A2),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A3),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A4),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A5),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A6),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A7),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A8),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A9),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A10),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A11),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A12),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A13),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A14),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A15),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_CAS),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_CS0),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_CS1),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_RAS),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_RESET),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDBA0),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDBA1),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDCLK_0),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDBA2),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDCKE0),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDCLK_1),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDCKE1),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDODT0),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDODT1),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDWE),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D0),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D1),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D2),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D3),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D4),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D5),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS0),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D6),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D7),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM0),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D8),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D9),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D10),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D11),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D12),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D13),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D14),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS1),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D15),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM1),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D48),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D49),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D50),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D51),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D52),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D53),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D54),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D55),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS6),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM6),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D56),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS7),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D57),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D58),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D59),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D60),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM7),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D61),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D62),
+        IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D63),
+        IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL0),
+        IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW0),
+        IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL1),
+        IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW1),
+        IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL2),
+        IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW2),
+        IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL3),
+        IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW3),
+        IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL4),
+        IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW4),
+        IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_0),
+        IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_1),
+        IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_9),
+        IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_3),
+        IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_6),
+        IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_2),
+        IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_4),
+        IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_5),
+        IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_7),
+        IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_8),
+        IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_16),
+        IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_17),
+        IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_18),
+        IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_19),
+        IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_PIXCLK),
+        IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_MCLK),
+        IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DATA_EN),
+        IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_VSYNC),
+        IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT4),
+        IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT5),
+        IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT6),
+        IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT7),
+        IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT8),
+        IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT9),
+        IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT10),
+        IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT11),
+        IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT12),
+        IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT13),
+        IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT14),
+        IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT15),
+        IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT16),
+        IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT17),
+        IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT18),
+        IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT19),
+        IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TMS),
+        IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_MOD),
+        IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TRSTB),
+        IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TDI),
+        IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TCK),
+        IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TDO),
+        IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_TX3_P),
+        IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_TX2_P),
+        IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_CLK_P),
+        IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_TX1_P),
+        IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_TX0_P),
+        IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_TX3_P),
+        IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_CLK_P),
+        IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_TX2_P),
+        IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_TX1_P),
+        IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_TX0_P),
+        IMX_PINCTRL_PIN(MX6Q_PAD_TAMPER),
+        IMX_PINCTRL_PIN(MX6Q_PAD_PMIC_ON_REQ),
+        IMX_PINCTRL_PIN(MX6Q_PAD_PMIC_STBY_REQ),
+        IMX_PINCTRL_PIN(MX6Q_PAD_POR_B),
+        IMX_PINCTRL_PIN(MX6Q_PAD_BOOT_MODE1),
+        IMX_PINCTRL_PIN(MX6Q_PAD_RESET_IN_B),
+        IMX_PINCTRL_PIN(MX6Q_PAD_BOOT_MODE0),
+        IMX_PINCTRL_PIN(MX6Q_PAD_TEST_MODE),
+        IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT7),
+        IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT6),
+        IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT5),
+        IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT4),
+        IMX_PINCTRL_PIN(MX6Q_PAD_SD3_CMD),
+        IMX_PINCTRL_PIN(MX6Q_PAD_SD3_CLK),
+        IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT0),
+        IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT1),
+        IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT2),
+        IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT3),
+        IMX_PINCTRL_PIN(MX6Q_PAD_SD3_RST),
+        IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CLE),
+        IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_ALE),
+        IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_WP_B),
+        IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_RB0),
+        IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS0),
+        IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS1),
+        IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS2),
+        IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS3),
+        IMX_PINCTRL_PIN(MX6Q_PAD_SD4_CMD),
+        IMX_PINCTRL_PIN(MX6Q_PAD_SD4_CLK),
+        IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D0),
+        IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D1),
+        IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D2),
+        IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D3),
+        IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D4),
+        IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D5),
+        IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D6),
+        IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D7),
+        IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT0),
+        IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT1),
+        IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT2),
+        IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT3),
+        IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT4),
+        IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT5),
+        IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT6),
+        IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT7),
+        IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT1),
+        IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT0),
+        IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT3),
+        IMX_PINCTRL_PIN(MX6Q_PAD_SD1_CMD),
+        IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT2),
+        IMX_PINCTRL_PIN(MX6Q_PAD_SD1_CLK),
+        IMX_PINCTRL_PIN(MX6Q_PAD_SD2_CLK),
+        IMX_PINCTRL_PIN(MX6Q_PAD_SD2_CMD),
+        IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT3),
+};
+
+static struct imx_pinctrl_soc_info imx6q_pinctrl_info = {
+        .pins = imx6q_pinctrl_pads,
+        .npins = ARRAY_SIZE(imx6q_pinctrl_pads),
+        .pin_regs = imx6q_pin_regs,
+        .npin_regs = ARRAY_SIZE(imx6q_pin_regs),
+};
+
+static struct of_device_id imx6q_pinctrl_of_match[] __devinitdata = {
+        { .compatible = "fsl,imx6q-iomuxc", },
+        { /* sentinel */ }
+};
+
+static int __devinit imx6q_pinctrl_probe(struct platform_device *pdev)
+{
+        return imx_pinctrl_probe(pdev, &imx6q_pinctrl_info);
+}
+
+static struct platform_driver imx6q_pinctrl_driver = {
+        .driver = {
+                .name = "imx6q-pinctrl",
+                .owner = THIS_MODULE,
+                .of_match_table = of_match_ptr(imx6q_pinctrl_of_match),
+        },
+        .probe = imx6q_pinctrl_probe,
+        .remove = __devexit_p(imx_pinctrl_remove),
+};
+
+static int __init imx6q_pinctrl_init(void)
+{
+        return platform_driver_register(&imx6q_pinctrl_driver);
+}
+arch_initcall(imx6q_pinctrl_init);
+
+static void __exit imx6q_pinctrl_exit(void)
+{
+        platform_driver_unregister(&imx6q_pinctrl_driver);
+}
+module_exit(imx6q_pinctrl_exit);
+MODULE_AUTHOR("Dong Aisheng <dong.aisheng@linaro.org>");
+MODULE_DESCRIPTION("Freescale IMX6Q pinctrl driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-mxs.c b/drivers/pinctrl/pinctrl-mxs.c
new file mode 100644
index 000000000000..93cd959971c5
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-mxs.c
@@ -0,0 +1,508 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include "core.h"
+#include "pinctrl-mxs.h"
+
+#define SUFFIX_LEN      4
+
+struct mxs_pinctrl_data {
+        struct device *dev;
+        struct pinctrl_dev *pctl;
+        void __iomem *base;
+        struct mxs_pinctrl_soc_data *soc;
+};
+
+static int mxs_get_groups_count(struct pinctrl_dev *pctldev)
+{
+        struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
+
+        return d->soc->ngroups;
+}
+
+static const char *mxs_get_group_name(struct pinctrl_dev *pctldev,
+                                      unsigned group)
+{
+        struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
+
+        return d->soc->groups[group].name;
+}
+
+static int mxs_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
+                              const unsigned **pins, unsigned *num_pins)
+{
+        struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
+
+        *pins = d->soc->groups[group].pins;
+        *num_pins = d->soc->groups[group].npins;
+
+        return 0;
+}
+
+static void mxs_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
+                             unsigned offset)
+{
+        seq_printf(s, " %s", dev_name(pctldev->dev));
+}
+
+static int mxs_dt_node_to_map(struct pinctrl_dev *pctldev,
+                              struct device_node *np,
+                              struct pinctrl_map **map, unsigned *num_maps)
+{
+        struct pinctrl_map *new_map;
+        char *group;
+        unsigned new_num;
+        unsigned long config = 0;
+        unsigned long *pconfig;
+        int length = strlen(np->name) + SUFFIX_LEN;
+        u32 val;
+        int ret;
+
+        ret = of_property_read_u32(np, "fsl,drive-strength", &val);
+        if (!ret)
+                config = val | MA_PRESENT;
+        ret = of_property_read_u32(np, "fsl,voltage", &val);
+        if (!ret)
+                config |= val << VOL_SHIFT | VOL_PRESENT;
+        ret = of_property_read_u32(np, "fsl,pull-up", &val);
+        if (!ret)
+                config |= val << PULL_SHIFT | PULL_PRESENT;
+
+        new_num = config ? 2 : 1;
+        new_map = kzalloc(sizeof(*new_map) * new_num, GFP_KERNEL);
+        if (!new_map)
+                return -ENOMEM;
+
+        new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
+        new_map[0].data.mux.function = np->name;
+
+        /* Compose group name */
+        group = kzalloc(length, GFP_KERNEL);
+        if (!group)
+                return -ENOMEM;
+        of_property_read_u32(np, "reg", &val);
+        snprintf(group, length, "%s.%d", np->name, val);
+        new_map[0].data.mux.group = group;
+
+        if (config) {
+                pconfig = kmemdup(&config, sizeof(config), GFP_KERNEL);
+                if (!pconfig) {
+                        ret = -ENOMEM;
+                        goto free;
+                }
+
+                new_map[1].type = PIN_MAP_TYPE_CONFIGS_GROUP;
+                new_map[1].data.configs.group_or_pin = group;
+                new_map[1].data.configs.configs = pconfig;
+                new_map[1].data.configs.num_configs = 1;
+        }
+
+        *map = new_map;
+        *num_maps = new_num;
+
+        return 0;
+
+free:
+        kfree(new_map);
+        return ret;
+}
+
+static void mxs_dt_free_map(struct pinctrl_dev *pctldev,
+                            struct pinctrl_map *map, unsigned num_maps)
+{
+        int i;
+
+        for (i = 0; i < num_maps; i++) {
+                if (map[i].type == PIN_MAP_TYPE_MUX_GROUP)
+                        kfree(map[i].data.mux.group);
+                if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
+                        kfree(map[i].data.configs.configs);
+        }
+
+        kfree(map);
+}
+
+static struct pinctrl_ops mxs_pinctrl_ops = {
+        .get_groups_count = mxs_get_groups_count,
+        .get_group_name = mxs_get_group_name,
+        .get_group_pins = mxs_get_group_pins,
+        .pin_dbg_show = mxs_pin_dbg_show,
+        .dt_node_to_map = mxs_dt_node_to_map,
+        .dt_free_map = mxs_dt_free_map,
+};
+
+static int mxs_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
+{
+        struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
+
+        return d->soc->nfunctions;
+}
+
+static const char *mxs_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
+                                             unsigned function)
+{
+        struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
+
+        return d->soc->functions[function].name;
+}
+
+static int mxs_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
+                                       unsigned group,
+                                       const char * const **groups,
+                                       unsigned * const num_groups)
+{
+        struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
+
+        *groups = d->soc->functions[group].groups;
+        *num_groups = d->soc->functions[group].ngroups;
+
+        return 0;
+}
+
+static int mxs_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned selector,
+                              unsigned group)
+{
+        struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
+        struct mxs_group *g = &d->soc->groups[group];
+        void __iomem *reg;
+        u8 bank, shift;
+        u16 pin;
+        int i;
+
+        for (i = 0; i < g->npins; i++) {
+                bank = PINID_TO_BANK(g->pins[i]);
+                pin = PINID_TO_PIN(g->pins[i]);
+                reg = d->base + d->soc->regs->muxsel;
+                reg += bank * 0x20 + pin / 16 * 0x10;
+                shift = pin % 16 * 2;
+
+                writel(0x3 << shift, reg + CLR);
+                writel(g->muxsel[i] << shift, reg + SET);
+        }
+
+        return 0;
+}
+
+static void mxs_pinctrl_disable(struct pinctrl_dev *pctldev,
+                                unsigned function, unsigned group)
+{
+        /* Nothing to do here */
+}
+
+static struct pinmux_ops mxs_pinmux_ops = {
+        .get_functions_count = mxs_pinctrl_get_funcs_count,
+        .get_function_name = mxs_pinctrl_get_func_name,
+        .get_function_groups = mxs_pinctrl_get_func_groups,
+        .enable = mxs_pinctrl_enable,
+        .disable = mxs_pinctrl_disable,
+};
+
+static int mxs_pinconf_get(struct pinctrl_dev *pctldev,
+                           unsigned pin, unsigned long *config)
+{
+        return -ENOTSUPP;
+}
+
+static int mxs_pinconf_set(struct pinctrl_dev *pctldev,
+                           unsigned pin, unsigned long config)
+{
+        return -ENOTSUPP;
+}
+
+static int mxs_pinconf_group_get(struct pinctrl_dev *pctldev,
+                                 unsigned group, unsigned long *config)
+{
+        struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
+
+        *config = d->soc->groups[group].config;
+
+        return 0;
+}
+
+static int mxs_pinconf_group_set(struct pinctrl_dev *pctldev,
+                                 unsigned group, unsigned long config)
+{
+        struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
+        struct mxs_group *g = &d->soc->groups[group];
+        void __iomem *reg;
+        u8 ma, vol, pull, bank, shift;
+        u16 pin;
+        int i;
+
+        ma = CONFIG_TO_MA(config);
+        vol = CONFIG_TO_VOL(config);
+        pull = CONFIG_TO_PULL(config);
+
+        for (i = 0; i < g->npins; i++) {
+                bank = PINID_TO_BANK(g->pins[i]);
+                pin = PINID_TO_PIN(g->pins[i]);
+
+                /* drive */
+                reg = d->base + d->soc->regs->drive;
+                reg += bank * 0x40 + pin / 8 * 0x10;
+
+                /* mA */
+                if (config & MA_PRESENT) {
+                        shift = pin % 8 * 4;
+                        writel(0x3 << shift, reg + CLR);
+                        writel(ma << shift, reg + SET);
+                }
+
+                /* vol */
+                if (config & VOL_PRESENT) {
+                        shift = pin % 8 * 4 + 2;
+                        if (vol)
+                                writel(1 << shift, reg + SET);
+                        else
+                                writel(1 << shift, reg + CLR);
+                }
+
+                /* pull */
+                if (config & PULL_PRESENT) {
+                        reg = d->base + d->soc->regs->pull;
+                        reg += bank * 0x10;
+                        shift = pin;
+                        if (pull)
+                                writel(1 << shift, reg + SET);
+                        else
+                                writel(1 << shift, reg + CLR);
+                }
+        }
+
+        /* cache the config value for mxs_pinconf_group_get() */
+        g->config = config;
+
+        return 0;
+}
+
+static void mxs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
+                                 struct seq_file *s, unsigned pin)
+{
+        /* Not support */
+}
+
+static void mxs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
+                                       struct seq_file *s, unsigned group)
+{
+        unsigned long config;
+
+        if (!mxs_pinconf_group_get(pctldev, group, &config))
+                seq_printf(s, "0x%lx", config);
+}
+
+struct pinconf_ops mxs_pinconf_ops = {
+        .pin_config_get = mxs_pinconf_get,
+        .pin_config_set = mxs_pinconf_set,
+        .pin_config_group_get = mxs_pinconf_group_get,
+        .pin_config_group_set = mxs_pinconf_group_set,
+        .pin_config_dbg_show = mxs_pinconf_dbg_show,
+        .pin_config_group_dbg_show = mxs_pinconf_group_dbg_show,
+};
+
+static struct pinctrl_desc mxs_pinctrl_desc = {
+        .pctlops = &mxs_pinctrl_ops,
+        .pmxops = &mxs_pinmux_ops,
+        .confops = &mxs_pinconf_ops,
+        .owner = THIS_MODULE,
+};
+
+static int __devinit mxs_pinctrl_parse_group(struct platform_device *pdev,
+                                             struct device_node *np, int idx,
+                                             const char **out_name)
+{
+        struct mxs_pinctrl_data *d = platform_get_drvdata(pdev);
+        struct mxs_group *g = &d->soc->groups[idx];
+        struct property *prop;
+        const char *propname = "fsl,pinmux-ids";
+        char *group;
+        int length = strlen(np->name) + SUFFIX_LEN;
+        int i;
+        u32 val;
+
+        group = devm_kzalloc(&pdev->dev, length, GFP_KERNEL);
+        if (!group)
+                return -ENOMEM;
+        of_property_read_u32(np, "reg", &val);
+        snprintf(group, length, "%s.%d", np->name, val);
+        g->name = group;
+
+        prop = of_find_property(np, propname, &length);
+        if (!prop)
+                return -EINVAL;
+        g->npins = length / sizeof(u32);
+
+        g->pins = devm_kzalloc(&pdev->dev, g->npins * sizeof(*g->pins),
+                               GFP_KERNEL);
+        if (!g->pins)
+                return -ENOMEM;
+
+        g->muxsel = devm_kzalloc(&pdev->dev, g->npins * sizeof(*g->muxsel),
+                                 GFP_KERNEL);
+        if (!g->muxsel)
+                return -ENOMEM;
+
+        of_property_read_u32_array(np, propname, g->pins, g->npins);
+        for (i = 0; i < g->npins; i++) {
+                g->muxsel[i] = MUXID_TO_MUXSEL(g->pins[i]);
+                g->pins[i] = MUXID_TO_PINID(g->pins[i]);
+        }
+
+        *out_name = g->name;
+
+        return 0;
+}
+
+static int __devinit mxs_pinctrl_probe_dt(struct platform_device *pdev,
+                                          struct mxs_pinctrl_data *d)
+{
+        struct mxs_pinctrl_soc_data *soc = d->soc;
+        struct device_node *np = pdev->dev.of_node;
+        struct device_node *child;
+        struct mxs_function *f;
+        const char *fn, *fnull = "";
+        int i = 0, idxf = 0, idxg = 0;
+        int ret;
+        u32 val;
+
+        child = of_get_next_child(np, NULL);
+        if (!child) {
+                dev_err(&pdev->dev, "no group is defined\n");
+                return -ENOENT;
+        }
+
+        /* Count total functions and groups */
+        fn = fnull;
+        for_each_child_of_node(np, child) {
+                /* Skip pure pinconf node */
+                if (of_property_read_u32(child, "reg", &val))
+                        continue;
+                if (strcmp(fn, child->name)) {
+                        fn = child->name;
+                        soc->nfunctions++;
+                }
+                soc->ngroups++;
+        }
+
+        soc->functions = devm_kzalloc(&pdev->dev, soc->nfunctions *
+                                      sizeof(*soc->functions), GFP_KERNEL);
+        if (!soc->functions)
+                return -ENOMEM;
+
+        soc->groups = devm_kzalloc(&pdev->dev, soc->ngroups *
+                                   sizeof(*soc->groups), GFP_KERNEL);
+        if (!soc->groups)
+                return -ENOMEM;
+
+        /* Count groups for each function */
+        fn = fnull;
+        f = &soc->functions[idxf];
+        for_each_child_of_node(np, child) {
+                if (of_property_read_u32(child, "reg", &val))
+                        continue;
+                if (strcmp(fn, child->name)) {
+                        f = &soc->functions[idxf++];
+                        f->name = fn = child->name;
+                }
+                f->ngroups++;
+        };
+
+        /* Get groups for each function */
+        idxf = 0;
+        fn = fnull;
+        for_each_child_of_node(np, child) {
+                if (of_property_read_u32(child, "reg", &val))
+                        continue;
+                if (strcmp(fn, child->name)) {
+                        f = &soc->functions[idxf++];
+                        f->groups = devm_kzalloc(&pdev->dev, f->ngroups *
+                                                 sizeof(*f->groups),
+                                                 GFP_KERNEL);
+                        if (!f->groups)
+                                return -ENOMEM;
+                        fn = child->name;
+                        i = 0;
+                }
+                ret = mxs_pinctrl_parse_group(pdev, child, idxg++,
+                                              &f->groups[i++]);
+                if (ret)
+                        return ret;
+        }
+
+        return 0;
+}
+
+int __devinit mxs_pinctrl_probe(struct platform_device *pdev,
+                                struct mxs_pinctrl_soc_data *soc)
+{
+        struct device_node *np = pdev->dev.of_node;
+        struct mxs_pinctrl_data *d;
+        int ret;
+
+        d = devm_kzalloc(&pdev->dev, sizeof(*d), GFP_KERNEL);
+        if (!d)
+                return -ENOMEM;
+
+        d->dev = &pdev->dev;
+        d->soc = soc;
+
+        d->base = of_iomap(np, 0);
+        if (!d->base)
+                return -EADDRNOTAVAIL;
+
+        mxs_pinctrl_desc.pins = d->soc->pins;
+        mxs_pinctrl_desc.npins = d->soc->npins;
+        mxs_pinctrl_desc.name = dev_name(&pdev->dev);
+
+        platform_set_drvdata(pdev, d);
+
+        ret = mxs_pinctrl_probe_dt(pdev, d);
+        if (ret) {
+                dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
+                goto err;
+        }
+
+        d->pctl = pinctrl_register(&mxs_pinctrl_desc, &pdev->dev, d);
+        if (!d->pctl) {
+                dev_err(&pdev->dev, "Couldn't register MXS pinctrl driver\n");
+                ret = -EINVAL;
+                goto err;
+        }
+
+        return 0;
+
+err:
+        iounmap(d->base);
+        return ret;
+}
+EXPORT_SYMBOL_GPL(mxs_pinctrl_probe);
+
+int __devexit mxs_pinctrl_remove(struct platform_device *pdev)
+{
+        struct mxs_pinctrl_data *d = platform_get_drvdata(pdev);
+
+        pinctrl_unregister(d->pctl);
+        iounmap(d->base);
+
+        return 0;
+}
+EXPORT_SYMBOL_GPL(mxs_pinctrl_remove);
diff --git a/drivers/pinctrl/pinctrl-mxs.h b/drivers/pinctrl/pinctrl-mxs.h
new file mode 100644
index 000000000000..fdd88d0bae22
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-mxs.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __PINCTRL_MXS_H
+#define __PINCTRL_MXS_H
+
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#define SET     0x4
+#define CLR     0x8
+#define TOG     0xc
+
+#define MXS_PINCTRL_PIN(pin)    PINCTRL_PIN(pin, #pin)
+#define PINID(bank, pin)        ((bank) * 32 + (pin))
+
+/*
+ * pinmux-id bit field definitions
+ *
+ * bank:        15..12  (4)
+ * pin:         11..4   (8)
+ * muxsel:      3..0    (4)
+ */
+#define MUXID_TO_PINID(m)       PINID((m) >> 12 & 0xf, (m) >> 4 & 0xff)
+#define MUXID_TO_MUXSEL(m)      ((m) & 0xf)
+
+#define PINID_TO_BANK(p)        ((p) >> 5)
+#define PINID_TO_PIN(p)         ((p) % 32)
+
+/*
+ * pin config bit field definitions
+ *
+ * pull-up:     6..5    (2)
+ * voltage:     4..3    (2)
+ * mA:          2..0    (3)
+ *
+ * MSB of each field is presence bit for the config.
+ */
+#define PULL_PRESENT            (1 << 6)
+#define PULL_SHIFT              5
+#define VOL_PRESENT             (1 << 4)
+#define VOL_SHIFT               3
+#define MA_PRESENT              (1 << 2)
+#define MA_SHIFT                0
+#define CONFIG_TO_PULL(c)       ((c) >> PULL_SHIFT & 0x1)
+#define CONFIG_TO_VOL(c)        ((c) >> VOL_SHIFT & 0x1)
+#define CONFIG_TO_MA(c)         ((c) >> MA_SHIFT & 0x3)
+
+struct mxs_function {
+        const char *name;
+        const char **groups;
+        unsigned ngroups;
+};
+
+struct mxs_group {
+        const char *name;
+        unsigned int *pins;
+        unsigned npins;
+        u8 *muxsel;
+        u8 config;
+};
+
+struct mxs_regs {
+        u16 muxsel;
+        u16 drive;
+        u16 pull;
+};
+
+struct mxs_pinctrl_soc_data {
+        const struct mxs_regs *regs;
+        const struct pinctrl_pin_desc *pins;
+        unsigned npins;
+        struct mxs_function *functions;
+        unsigned nfunctions;
+        struct mxs_group *groups;
+        unsigned ngroups;
+};
+
+int mxs_pinctrl_probe(struct platform_device *pdev,
+                      struct mxs_pinctrl_soc_data *soc);
+int mxs_pinctrl_remove(struct platform_device *pdev);
+
+#endif /* __PINCTRL_MXS_H */
diff --git a/drivers/pinctrl/pinctrl-pxa3xx.c b/drivers/pinctrl/pinctrl-pxa3xx.c
index 079dce0e93e9..7644e42ac211 100644
--- a/drivers/pinctrl/pinctrl-pxa3xx.c
+++ b/drivers/pinctrl/pinctrl-pxa3xx.c
@@ -25,20 +25,18 @@ static struct pinctrl_gpio_range pxa3xx_pinctrl_gpio_range = {
         .pin_base       = 0,
 };
 
-static int pxa3xx_list_groups(struct pinctrl_dev *pctrldev, unsigned selector)
+static int pxa3xx_get_groups_count(struct pinctrl_dev *pctrldev)
 {
         struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
-        if (selector >= info->num_grps)
-                return -EINVAL;
-        return 0;
+
+        return info->num_grps;
 }
 
 static const char *pxa3xx_get_group_name(struct pinctrl_dev *pctrldev,
                                          unsigned selector)
 {
         struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
-        if (selector >= info->num_grps)
-                return NULL;
+
         return info->grps[selector].name;
 }
 
@@ -48,25 +46,23 @@ static int pxa3xx_get_group_pins(struct pinctrl_dev *pctrldev,
                                  unsigned *num_pins)
 {
         struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
-        if (selector >= info->num_grps)
-                return -EINVAL;
+
         *pins = info->grps[selector].pins;
         *num_pins = info->grps[selector].npins;
         return 0;
 }
 
 static struct pinctrl_ops pxa3xx_pctrl_ops = {
-        .list_groups    = pxa3xx_list_groups,
+        .get_groups_count = pxa3xx_get_groups_count,
         .get_group_name = pxa3xx_get_group_name,
         .get_group_pins = pxa3xx_get_group_pins,
 };
 
-static int pxa3xx_pmx_list_func(struct pinctrl_dev *pctrldev, unsigned func)
+static int pxa3xx_pmx_get_funcs_count(struct pinctrl_dev *pctrldev)
 {
         struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
-        if (func >= info->num_funcs)
-                return -EINVAL;
-        return 0;
+
+        return info->num_funcs;
 }
 
 static const char *pxa3xx_pmx_get_func_name(struct pinctrl_dev *pctrldev,
@@ -170,7 +166,7 @@ static int pxa3xx_pmx_request_gpio(struct pinctrl_dev *pctrldev,
 }
 
 static struct pinmux_ops pxa3xx_pmx_ops = {
-        .list_functions         = pxa3xx_pmx_list_func,
+        .get_functions_count    = pxa3xx_pmx_get_funcs_count,
         .get_function_name      = pxa3xx_pmx_get_func_name,
         .get_function_groups    = pxa3xx_pmx_get_groups,
         .enable                 = pxa3xx_pmx_enable,
diff --git a/drivers/pinctrl/pinctrl-sirf.c b/drivers/pinctrl/pinctrl-sirf.c
index 6b3534cc051a..ba15b1a29e52 100644
--- a/drivers/pinctrl/pinctrl-sirf.c
+++ b/drivers/pinctrl/pinctrl-sirf.c
@@ -853,18 +853,14 @@ static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
         SIRFSOC_PIN_GROUP("gpsgrp", gps_pins),
 };
 
-static int sirfsoc_list_groups(struct pinctrl_dev *pctldev, unsigned selector)
+static int sirfsoc_get_groups_count(struct pinctrl_dev *pctldev)
 {
-        if (selector >= ARRAY_SIZE(sirfsoc_pin_groups))
-                return -EINVAL;
-        return 0;
+        return ARRAY_SIZE(sirfsoc_pin_groups);
 }
 
 static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev,
                                        unsigned selector)
 {
-        if (selector >= ARRAY_SIZE(sirfsoc_pin_groups))
-                return NULL;
         return sirfsoc_pin_groups[selector].name;
 }
 
@@ -872,8 +868,6 @@ static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector
                                const unsigned **pins,
                                unsigned *num_pins)
 {
-        if (selector >= ARRAY_SIZE(sirfsoc_pin_groups))
-                return -EINVAL;
         *pins = sirfsoc_pin_groups[selector].pins;
         *num_pins = sirfsoc_pin_groups[selector].num_pins;
         return 0;
@@ -886,7 +880,7 @@ static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s
 }
 
 static struct pinctrl_ops sirfsoc_pctrl_ops = {
-        .list_groups = sirfsoc_list_groups,
+        .get_groups_count = sirfsoc_get_groups_count,
         .get_group_name = sirfsoc_get_group_name,
         .get_group_pins = sirfsoc_get_group_pins,
         .pin_dbg_show = sirfsoc_pin_dbg_show,
@@ -1033,11 +1027,9 @@ static void sirfsoc_pinmux_disable(struct pinctrl_dev *pmxdev, unsigned selector
         sirfsoc_pinmux_endisable(spmx, selector, false);
 }
 
-static int sirfsoc_pinmux_list_funcs(struct pinctrl_dev *pmxdev, unsigned selector)
+static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev)
 {
-        if (selector >= ARRAY_SIZE(sirfsoc_pmx_functions))
-                return -EINVAL;
-        return 0;
+        return ARRAY_SIZE(sirfsoc_pmx_functions);
 }
 
 static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev,
@@ -1074,9 +1066,9 @@ static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev,
 }
 
 static struct pinmux_ops sirfsoc_pinmux_ops = {
-        .list_functions = sirfsoc_pinmux_list_funcs,
         .enable = sirfsoc_pinmux_enable,
         .disable = sirfsoc_pinmux_disable,
+        .get_functions_count = sirfsoc_pinmux_get_funcs_count,
         .get_function_name = sirfsoc_pinmux_get_func_name,
         .get_function_groups = sirfsoc_pinmux_get_groups,
         .gpio_request_enable = sirfsoc_pinmux_request_gpio,
diff --git a/drivers/pinctrl/pinctrl-tegra.c b/drivers/pinctrl/pinctrl-tegra.c
index 9b329688120c..2c98fba01ca5 100644
--- a/drivers/pinctrl/pinctrl-tegra.c
+++ b/drivers/pinctrl/pinctrl-tegra.c
@@ -23,9 +23,11 @@
 #include <linux/io.h>
 #include <linux/module.h>
 #include <linux/of_device.h>
+#include <linux/pinctrl/machine.h>
 #include <linux/pinctrl/pinctrl.h>
 #include <linux/pinctrl/pinmux.h>
 #include <linux/pinctrl/pinconf.h>
+#include <linux/slab.h>
 
 #include <mach/pinconf-tegra.h>
 
@@ -53,15 +55,11 @@ static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg)
         writel(val, pmx->regs[bank] + reg);
 }
 
-static int tegra_pinctrl_list_groups(struct pinctrl_dev *pctldev,
-                                     unsigned group)
+static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
 {
         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 
-        if (group >= pmx->soc->ngroups)
-                return -EINVAL;
-
-        return 0;
+        return pmx->soc->ngroups;
 }
 
 static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
@@ -69,9 +67,6 @@ static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
 {
         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 
-        if (group >= pmx->soc->ngroups)
-                return NULL;
-
         return pmx->soc->groups[group].name;
 }
 
@@ -82,9 +77,6 @@ static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
 {
         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 
-        if (group >= pmx->soc->ngroups)
-                return -EINVAL;
-
         *pins = pmx->soc->groups[group].pins;
         *num_pins = pmx->soc->groups[group].npins;
 
@@ -98,22 +90,221 @@ static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
         seq_printf(s, " " DRIVER_NAME);
 }
 
+static int reserve_map(struct pinctrl_map **map, unsigned *reserved_maps,
+                       unsigned *num_maps, unsigned reserve)
+{
+        unsigned old_num = *reserved_maps;
+        unsigned new_num = *num_maps + reserve;
+        struct pinctrl_map *new_map;
+
+        if (old_num >= new_num)
+                return 0;
+
+        new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
+        if (!new_map)
+                return -ENOMEM;
+
+        memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
+
+        *map = new_map;
+        *reserved_maps = new_num;
+
+        return 0;
+}
+
+static int add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
+                       unsigned *num_maps, const char *group,
+                       const char *function)
+{
+        if (*num_maps == *reserved_maps)
+                return -ENOSPC;
+
+        (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
+        (*map)[*num_maps].data.mux.group = group;
+        (*map)[*num_maps].data.mux.function = function;
+        (*num_maps)++;
+
+        return 0;
+}
+
+static int add_map_configs(struct pinctrl_map **map, unsigned *reserved_maps,
+                           unsigned *num_maps, const char *group,
+                           unsigned long *configs, unsigned num_configs)
+{
+        unsigned long *dup_configs;
+
+        if (*num_maps == *reserved_maps)
+                return -ENOSPC;
+
+        dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
+                              GFP_KERNEL);
+        if (!dup_configs)
+                return -ENOMEM;
+
+        (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
+        (*map)[*num_maps].data.configs.group_or_pin = group;
+        (*map)[*num_maps].data.configs.configs = dup_configs;
+        (*map)[*num_maps].data.configs.num_configs = num_configs;
+        (*num_maps)++;
+
+        return 0;
+}
+
+static int add_config(unsigned long **configs, unsigned *num_configs,
+                      unsigned long config)
+{
+        unsigned old_num = *num_configs;
+        unsigned new_num = old_num + 1;
+        unsigned long *new_configs;
+
+        new_configs = krealloc(*configs, sizeof(*new_configs) * new_num,
+                               GFP_KERNEL);
+        if (!new_configs)
+                return -ENOMEM;
+
+        new_configs[old_num] = config;
+
+        *configs = new_configs;
+        *num_configs = new_num;
+
+        return 0;
+}
+
+void tegra_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
+                               struct pinctrl_map *map, unsigned num_maps)
+{
+        int i;
+
+        for (i = 0; i < num_maps; i++)
+                if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
+                        kfree(map[i].data.configs.configs);
+
+        kfree(map);
+}
+
+static const struct cfg_param {
+        const char *property;
+        enum tegra_pinconf_param param;
+} cfg_params[] = {
+        {"nvidia,pull",                 TEGRA_PINCONF_PARAM_PULL},
+        {"nvidia,tristate",             TEGRA_PINCONF_PARAM_TRISTATE},
+        {"nvidia,enable-input",         TEGRA_PINCONF_PARAM_ENABLE_INPUT},
+        {"nvidia,open-drain",           TEGRA_PINCONF_PARAM_OPEN_DRAIN},
+        {"nvidia,lock",                 TEGRA_PINCONF_PARAM_LOCK},
+        {"nvidia,io-reset",             TEGRA_PINCONF_PARAM_IORESET},
+        {"nvidia,high-speed-mode",      TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
+        {"nvidia,schmitt",              TEGRA_PINCONF_PARAM_SCHMITT},
+        {"nvidia,low-power-mode",       TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
+        {"nvidia,pull-down-strength",   TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH},
+        {"nvidia,pull-up-strength",     TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH},
+        {"nvidia,slew-rate-falling",    TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
+        {"nvidia,slew-rate-rising",     TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
+};
+
+int tegra_pinctrl_dt_subnode_to_map(struct device_node *np,
+                                    struct pinctrl_map **map,
+                                    unsigned *reserved_maps,
+                                    unsigned *num_maps)
+{
+        int ret, i;
+        const char *function;
+        u32 val;
+        unsigned long config;
+        unsigned long *configs = NULL;
+        unsigned num_configs = 0;
+        unsigned reserve;
+        struct property *prop;
+        const char *group;
+
+        ret = of_property_read_string(np, "nvidia,function", &function);
+        if (ret < 0)
+                function = NULL;
+
+        for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
+                ret = of_property_read_u32(np, cfg_params[i].property, &val);
+                if (!ret) {
+                        config = TEGRA_PINCONF_PACK(cfg_params[i].param, val);
+                        ret = add_config(&configs, &num_configs, config);
+                        if (ret < 0)
+                                goto exit;
+                }
+        }
+
+        reserve = 0;
+        if (function != NULL)
+                reserve++;
+        if (num_configs)
+                reserve++;
+        ret = of_property_count_strings(np, "nvidia,pins");
+        if (ret < 0)
+                goto exit;
+        reserve *= ret;
+
+        ret = reserve_map(map, reserved_maps, num_maps, reserve);
+        if (ret < 0)
+                goto exit;
+
+        of_property_for_each_string(np, "nvidia,pins", prop, group) {
+                if (function) {
+                        ret = add_map_mux(map, reserved_maps, num_maps,
+                                          group, function);
+                        if (ret < 0)
+                                goto exit;
+                }
+
+                if (num_configs) {
+                        ret = add_map_configs(map, reserved_maps, num_maps,
+                                              group, configs, num_configs);
+                        if (ret < 0)
+                                goto exit;
+                }
+        }
+
+        ret = 0;
+
+exit:
+        kfree(configs);
+        return ret;
+}
+
+int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
+                                 struct device_node *np_config,
+                                 struct pinctrl_map **map, unsigned *num_maps)
+{
+        unsigned reserved_maps;
+        struct device_node *np;
+        int ret;
+
+        reserved_maps = 0;
+        *map = NULL;
+        *num_maps = 0;
+
+        for_each_child_of_node(np_config, np) {
+                ret = tegra_pinctrl_dt_subnode_to_map(np, map, &reserved_maps,
+                                                      num_maps);
+                if (ret < 0) {
+                        tegra_pinctrl_dt_free_map(pctldev, *map, *num_maps);
+                        return ret;
+                }
+        }
+
+        return 0;
+}
+
 static struct pinctrl_ops tegra_pinctrl_ops = {
-        .list_groups = tegra_pinctrl_list_groups,
+        .get_groups_count = tegra_pinctrl_get_groups_count,
         .get_group_name = tegra_pinctrl_get_group_name,
         .get_group_pins = tegra_pinctrl_get_group_pins,
         .pin_dbg_show = tegra_pinctrl_pin_dbg_show,
+        .dt_node_to_map = tegra_pinctrl_dt_node_to_map,
+        .dt_free_map = tegra_pinctrl_dt_free_map,
 };
 
-static int tegra_pinctrl_list_funcs(struct pinctrl_dev *pctldev,
-                                    unsigned function)
+static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
 {
         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 
-        if (function >= pmx->soc->nfunctions)
-                return -EINVAL;
-
-        return 0;
+        return pmx->soc->nfunctions;
 }
 
 static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
@@ -121,9 +312,6 @@ static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
 {
         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 
-        if (function >= pmx->soc->nfunctions)
-                return NULL;
-
         return pmx->soc->functions[function].name;
 }
 
@@ -134,9 +322,6 @@ static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
 {
         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 
-        if (function >= pmx->soc->nfunctions)
-                return -EINVAL;
-
         *groups = pmx->soc->functions[function].groups;
         *num_groups = pmx->soc->functions[function].ngroups;
 
@@ -151,8 +336,6 @@ static int tegra_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
         int i;
         u32 val;
 
-        if (group >= pmx->soc->ngroups)
-                return -EINVAL;
         g = &pmx->soc->groups[group];
 
         if (g->mux_reg < 0)
@@ -180,8 +363,6 @@ static void tegra_pinctrl_disable(struct pinctrl_dev *pctldev,
         const struct tegra_pingroup *g;
         u32 val;
 
-        if (group >= pmx->soc->ngroups)
-                return;
         g = &pmx->soc->groups[group];
 
         if (g->mux_reg < 0)
@@ -194,7 +375,7 @@ static void tegra_pinctrl_disable(struct pinctrl_dev *pctldev,
 }
 
 static struct pinmux_ops tegra_pinmux_ops = {
-        .list_functions = tegra_pinctrl_list_funcs,
+        .get_functions_count = tegra_pinctrl_get_funcs_count,
         .get_function_name = tegra_pinctrl_get_func_name,
         .get_function_groups = tegra_pinctrl_get_func_groups,
         .enable = tegra_pinctrl_enable,
@@ -324,8 +505,6 @@ static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev,
         s16 reg;
         u32 val, mask;
 
-        if (group >= pmx->soc->ngroups)
-                return -EINVAL;
         g = &pmx->soc->groups[group];
 
         ret = tegra_pinconf_reg(pmx, g, param, &bank, &reg, &bit, &width);
@@ -353,8 +532,6 @@ static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
         s16 reg;
         u32 val, mask;
 
-        if (group >= pmx->soc->ngroups)
-                return -EINVAL;
         g = &pmx->soc->groups[group];
 
         ret = tegra_pinconf_reg(pmx, g, param, &bank, &reg, &bit, &width);
diff --git a/drivers/pinctrl/pinctrl-u300.c b/drivers/pinctrl/pinctrl-u300.c
index 26eb8ccd72d5..05d029911be6 100644
--- a/drivers/pinctrl/pinctrl-u300.c
+++ b/drivers/pinctrl/pinctrl-u300.c
@@ -836,18 +836,14 @@ static const struct u300_pin_group u300_pin_groups[] = {
         },
 };
 
-static int u300_list_groups(struct pinctrl_dev *pctldev, unsigned selector)
+static int u300_get_groups_count(struct pinctrl_dev *pctldev)
 {
-        if (selector >= ARRAY_SIZE(u300_pin_groups))
-                return -EINVAL;
-        return 0;
+        return ARRAY_SIZE(u300_pin_groups);
 }
 
 static const char *u300_get_group_name(struct pinctrl_dev *pctldev,
                                        unsigned selector)
 {
-        if (selector >= ARRAY_SIZE(u300_pin_groups))
-                return NULL;
         return u300_pin_groups[selector].name;
 }
 
@@ -855,8 +851,6 @@ static int u300_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
                                const unsigned **pins,
                                unsigned *num_pins)
 {
-        if (selector >= ARRAY_SIZE(u300_pin_groups))
-                return -EINVAL;
         *pins = u300_pin_groups[selector].pins;
         *num_pins = u300_pin_groups[selector].num_pins;
         return 0;
@@ -869,7 +863,7 @@ static void u300_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
 }
 
 static struct pinctrl_ops u300_pctrl_ops = {
-        .list_groups = u300_list_groups,
+        .get_groups_count = u300_get_groups_count,
         .get_group_name = u300_get_group_name,
         .get_group_pins = u300_get_group_pins,
         .pin_dbg_show = u300_pin_dbg_show,
@@ -991,11 +985,9 @@ static void u300_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector,
         u300_pmx_endisable(upmx, selector, false);
 }
 
-static int u300_pmx_list_funcs(struct pinctrl_dev *pctldev, unsigned selector)
+static int u300_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
 {
-        if (selector >= ARRAY_SIZE(u300_pmx_functions))
-                return -EINVAL;
-        return 0;
+        return ARRAY_SIZE(u300_pmx_functions);
 }
 
 static const char *u300_pmx_get_func_name(struct pinctrl_dev *pctldev,
@@ -1014,7 +1006,7 @@ static int u300_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
 }
 
 static struct pinmux_ops u300_pmx_ops = {
-        .list_functions = u300_pmx_list_funcs,
+        .get_functions_count = u300_pmx_get_funcs_count,
         .get_function_name = u300_pmx_get_func_name,
         .get_function_groups = u300_pmx_get_groups,
         .enable = u300_pmx_enable,
diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c
index 4e62783a573a..220fa492c9f0 100644
--- a/drivers/pinctrl/pinmux.c
+++ b/drivers/pinctrl/pinmux.c
@@ -33,22 +33,26 @@
 int pinmux_check_ops(struct pinctrl_dev *pctldev)
 {
         const struct pinmux_ops *ops = pctldev->desc->pmxops;
+        unsigned nfuncs;
         unsigned selector = 0;
 
         /* Check that we implement required operations */
-        if (!ops->list_functions ||
+        if (!ops ||
+            !ops->get_functions_count ||
             !ops->get_function_name ||
             !ops->get_function_groups ||
             !ops->enable ||
-            !ops->disable)
+            !ops->disable) {
+                dev_err(pctldev->dev, "pinmux ops lacks necessary functions\n");
                 return -EINVAL;
-
+        }
         /* Check that all functions registered have names */
-        while (ops->list_functions(pctldev, selector) >= 0) {
+        nfuncs = ops->get_functions_count(pctldev);
+        while (selector < nfuncs) {
                 const char *fname = ops->get_function_name(pctldev,
                                                            selector);
                 if (!fname) {
-                        pr_err("pinmux ops has no name for function%u\n",
+                        dev_err(pctldev->dev, "pinmux ops has no name for function%u\n",
                                 selector);
                         return -EINVAL;
                 }
@@ -85,20 +89,23 @@ static int pin_request(struct pinctrl_dev *pctldev,
         const struct pinmux_ops *ops = pctldev->desc->pmxops;
         int status = -EINVAL;
 
-        dev_dbg(pctldev->dev, "request pin %d for %s\n", pin, owner);
-
         desc = pin_desc_get(pctldev, pin);
         if (desc == NULL) {
                 dev_err(pctldev->dev,
-                        "pin is not registered so it cannot be requested\n");
+                        "pin %d is not registered so it cannot be requested\n",
+                        pin);
                 goto out;
         }
 
+        dev_dbg(pctldev->dev, "request pin %d (%s) for %s\n",
+                pin, desc->name, owner);
+
         if (gpio_range) {
                 /* There's no need to support multiple GPIO requests */
                 if (desc->gpio_owner) {
                         dev_err(pctldev->dev,
-                                "pin already requested\n");
+                                "pin %s already requested by %s; cannot claim for %s\n",
+                                desc->name, desc->gpio_owner, owner);
                         goto out;
                 }
 
@@ -106,7 +113,8 @@ static int pin_request(struct pinctrl_dev *pctldev,
         } else {
                 if (desc->mux_usecount && strcmp(desc->mux_owner, owner)) {
                         dev_err(pctldev->dev,
-                                "pin already requested\n");
+                                "pin %s already requested by %s; cannot claim for %s\n",
+                                desc->name, desc->mux_owner, owner);
                         goto out;
                 }
 
@@ -139,8 +147,7 @@ static int pin_request(struct pinctrl_dev *pctldev,
                 status = 0;
 
         if (status) {
-                dev_err(pctldev->dev, "->request on device %s failed for pin %d\n",
-                       pctldev->desc->name, pin);
+                dev_err(pctldev->dev, "request() failed for pin %d\n", pin);
                 module_put(pctldev->owner);
         }
 
@@ -157,7 +164,7 @@ out_free_pin:
 out:
         if (status)
                 dev_err(pctldev->dev, "pin-%d (%s) status %d\n",
-                       pin, owner, status);
+                        pin, owner, status);
 
         return status;
 }
@@ -287,10 +294,11 @@ static int pinmux_func_name_to_selector(struct pinctrl_dev *pctldev,
                                         const char *function)
 {
         const struct pinmux_ops *ops = pctldev->desc->pmxops;
+        unsigned nfuncs = ops->get_functions_count(pctldev);
         unsigned selector = 0;
 
         /* See if this pctldev has this function */
-        while (ops->list_functions(pctldev, selector) >= 0) {
+        while (selector < nfuncs) {
                 const char *fname = ops->get_function_name(pctldev,
                                                            selector);
 
@@ -319,18 +327,32 @@ int pinmux_map_to_setting(struct pinctrl_map const *map,
         const unsigned *pins;
         unsigned num_pins;
 
-        setting->data.mux.func =
-                pinmux_func_name_to_selector(pctldev, map->data.mux.function);
-        if (setting->data.mux.func < 0)
-                return setting->data.mux.func;
+        if (!pmxops) {
+                dev_err(pctldev->dev, "does not support mux function\n");
+                return -EINVAL;
+        }
+
+        ret = pinmux_func_name_to_selector(pctldev, map->data.mux.function);
+        if (ret < 0) {
+                dev_err(pctldev->dev, "invalid function %s in map table\n",
+                        map->data.mux.function);
+                return ret;
+        }
+        setting->data.mux.func = ret;
 
         ret = pmxops->get_function_groups(pctldev, setting->data.mux.func,
                                           &groups, &num_groups);
-        if (ret < 0)
+        if (ret < 0) {
+                dev_err(pctldev->dev, "can't query groups for function %s\n",
+                        map->data.mux.function);
                 return ret;
-        if (!num_groups)
+        }
+        if (!num_groups) {
+                dev_err(pctldev->dev,
+                        "function %s can't be selected on any group\n",
+                        map->data.mux.function);
                 return -EINVAL;
-
+        }
         if (map->data.mux.group) {
                 bool found = false;
                 group = map->data.mux.group;
@@ -340,15 +362,23 @@ int pinmux_map_to_setting(struct pinctrl_map const *map,
                                 break;
                         }
                 }
-                if (!found)
+                if (!found) {
+                        dev_err(pctldev->dev,
+                                "invalid group \"%s\" for function \"%s\"\n",
+                                group, map->data.mux.function);
                         return -EINVAL;
+                }
         } else {
                 group = groups[0];
         }
 
-        setting->data.mux.group = pinctrl_get_group_selector(pctldev, group);
-        if (setting->data.mux.group < 0)
-                return setting->data.mux.group;
+        ret = pinctrl_get_group_selector(pctldev, group);
+        if (ret < 0) {
+                dev_err(pctldev->dev, "invalid group %s in map table\n",
+                        map->data.mux.group);
+                return ret;
+        }
+        setting->data.mux.group = ret;
 
         ret = pctlops->get_group_pins(pctldev, setting->data.mux.group, &pins,
                                       &num_pins);
@@ -364,7 +394,7 @@ int pinmux_map_to_setting(struct pinctrl_map const *map,
                 ret = pin_request(pctldev, pins[i], map->dev_name, NULL);
                 if (ret) {
                         dev_err(pctldev->dev,
-                                "could not get request pin %d on device %s\n",
+                                "could not request pin %d on device %s\n",
                                 pins[i], pinctrl_dev_get_name(pctldev));
                         /* On error release all taken pins */
                         i--; /* this pin just failed */
@@ -477,11 +507,15 @@ static int pinmux_functions_show(struct seq_file *s, void *what)
 {
         struct pinctrl_dev *pctldev = s->private;
         const struct pinmux_ops *pmxops = pctldev->desc->pmxops;
+        unsigned nfuncs;
         unsigned func_selector = 0;
 
-        mutex_lock(&pinctrl_mutex);
+        if (!pmxops)
+                return 0;
 
-        while (pmxops->list_functions(pctldev, func_selector) >= 0) {
+        mutex_lock(&pinctrl_mutex);
+        nfuncs = pmxops->get_functions_count(pctldev);
+        while (func_selector < nfuncs) {
                 const char *func = pmxops->get_function_name(pctldev,
                                                           func_selector);
                 const char * const *groups;
@@ -515,6 +549,9 @@ static int pinmux_pins_show(struct seq_file *s, void *what)
         const struct pinmux_ops *pmxops = pctldev->desc->pmxops;
         unsigned i, pin;
 
+        if (!pmxops)
+                return 0;
+
         seq_puts(s, "Pinmux settings per pin\n");
         seq_puts(s, "Format: pin (name): mux_owner gpio_owner hog?\n");
 
diff --git a/drivers/pinctrl/pinmux.h b/drivers/pinctrl/pinmux.h
index 6fc47003e95d..d1a98b1c9fce 100644
--- a/drivers/pinctrl/pinmux.h
+++ b/drivers/pinctrl/pinmux.h
@@ -31,12 +31,6 @@ void pinmux_free_setting(struct pinctrl_setting const *setting);
 int pinmux_enable_setting(struct pinctrl_setting const *setting);
 void pinmux_disable_setting(struct pinctrl_setting const *setting);
 
-void pinmux_show_map(struct seq_file *s, struct pinctrl_map const *map);
-void pinmux_show_setting(struct seq_file *s,
-                         struct pinctrl_setting const *setting);
-void pinmux_init_device_debugfs(struct dentry *devroot,
-                                struct pinctrl_dev *pctldev);
-
 #else
 
 static inline int pinmux_check_ops(struct pinctrl_dev *pctldev)
@@ -89,6 +83,18 @@ static inline void pinmux_disable_setting(
 {
 }
 
+#endif
+
+#if defined(CONFIG_PINMUX) && defined(CONFIG_DEBUG_FS)
+
+void pinmux_show_map(struct seq_file *s, struct pinctrl_map const *map);
+void pinmux_show_setting(struct seq_file *s,
+                         struct pinctrl_setting const *setting);
+void pinmux_init_device_debugfs(struct dentry *devroot,
+                                struct pinctrl_dev *pctldev);
+
+#else
+
 static inline void pinmux_show_map(struct seq_file *s,
                                    struct pinctrl_map const *map)
 {
diff --git a/drivers/pinctrl/spear/Kconfig b/drivers/pinctrl/spear/Kconfig
new file mode 100644
index 000000000000..91558791e766
--- /dev/null
+++ b/drivers/pinctrl/spear/Kconfig
@@ -0,0 +1,44 @@
+#
+# ST Microelectronics SPEAr PINCTRL drivers
+#
+
+if PLAT_SPEAR
+
+config PINCTRL_SPEAR
+        bool
+        depends on OF
+        select PINMUX
+        help
+          This enables pin control drivers for SPEAr Platform
+
+config PINCTRL_SPEAR3XX
+        bool
+        depends on ARCH_SPEAR3XX
+        select PINCTRL_SPEAR
+
+config PINCTRL_SPEAR300
+        bool "ST Microelectronics SPEAr300 SoC pin controller driver"
+        depends on MACH_SPEAR300
+        select PINCTRL_SPEAR3XX
+
+config PINCTRL_SPEAR310
+        bool "ST Microelectronics SPEAr310 SoC pin controller driver"
+        depends on MACH_SPEAR310
+        select PINCTRL_SPEAR3XX
+
+config PINCTRL_SPEAR320
+        bool "ST Microelectronics SPEAr320 SoC pin controller driver"
+        depends on MACH_SPEAR320
+        select PINCTRL_SPEAR3XX
+
+config PINCTRL_SPEAR1310
+        bool "ST Microelectronics SPEAr1310 SoC pin controller driver"
+        depends on MACH_SPEAR1310
+        select PINCTRL_SPEAR
+
+config PINCTRL_SPEAR1340
+        bool "ST Microelectronics SPEAr1340 SoC pin controller driver"
+        depends on MACH_SPEAR1340
+        select PINCTRL_SPEAR
+
+endif
diff --git a/drivers/pinctrl/spear/Makefile b/drivers/pinctrl/spear/Makefile
new file mode 100644
index 000000000000..b28a7ba22443
--- /dev/null
+++ b/drivers/pinctrl/spear/Makefile
@@ -0,0 +1,9 @@
+# SPEAr pinmux support
+
+obj-$(CONFIG_PINCTRL_SPEAR)     += pinctrl-spear.o
+obj-$(CONFIG_PINCTRL_SPEAR3XX)  += pinctrl-spear3xx.o
+obj-$(CONFIG_PINCTRL_SPEAR300)  += pinctrl-spear300.o
+obj-$(CONFIG_PINCTRL_SPEAR310)  += pinctrl-spear310.o
+obj-$(CONFIG_PINCTRL_SPEAR320)  += pinctrl-spear320.o
+obj-$(CONFIG_PINCTRL_SPEAR1310) += pinctrl-spear1310.o
+obj-$(CONFIG_PINCTRL_SPEAR1340) += pinctrl-spear1340.o
diff --git a/drivers/pinctrl/spear/pinctrl-spear.c b/drivers/pinctrl/spear/pinctrl-spear.c
new file mode 100644
index 000000000000..5ae50aadf885
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear.c
@@ -0,0 +1,354 @@
+/*
+ * Driver for the ST Microelectronics SPEAr pinmux
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * Inspired from:
+ * - U300 Pinctl drivers
+ * - Tegra Pinctl drivers
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include "pinctrl-spear.h"
+
+#define DRIVER_NAME "spear-pinmux"
+
+static inline u32 pmx_readl(struct spear_pmx *pmx, u32 reg)
+{
+        return readl_relaxed(pmx->vbase + reg);
+}
+
+static inline void pmx_writel(struct spear_pmx *pmx, u32 val, u32 reg)
+{
+        writel_relaxed(val, pmx->vbase + reg);
+}
+
+static int set_mode(struct spear_pmx *pmx, int mode)
+{
+        struct spear_pmx_mode *pmx_mode = NULL;
+        int i;
+        u32 val;
+
+        if (!pmx->machdata->pmx_modes || !pmx->machdata->npmx_modes)
+                return -EINVAL;
+
+        for (i = 0; i < pmx->machdata->npmx_modes; i++) {
+                if (pmx->machdata->pmx_modes[i]->mode == (1 << mode)) {
+                        pmx_mode = pmx->machdata->pmx_modes[i];
+                        break;
+                }
+        }
+
+        if (!pmx_mode)
+                return -EINVAL;
+
+        val = pmx_readl(pmx, pmx_mode->reg);
+        val &= ~pmx_mode->mask;
+        val |= pmx_mode->val;
+        pmx_writel(pmx, val, pmx_mode->reg);
+
+        pmx->machdata->mode = pmx_mode->mode;
+        dev_info(pmx->dev, "Configured Mode: %s with id: %x\n\n",
+                        pmx_mode->name ? pmx_mode->name : "no_name",
+                        pmx_mode->reg);
+
+        return 0;
+}
+
+void __devinit pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg)
+{
+        struct spear_pingroup *pgroup;
+        struct spear_modemux *modemux;
+        int i, j, group;
+
+        for (group = 0; group < machdata->ngroups; group++) {
+                pgroup = machdata->groups[group];
+
+                for (i = 0; i < pgroup->nmodemuxs; i++) {
+                        modemux = &pgroup->modemuxs[i];
+
+                        for (j = 0; j < modemux->nmuxregs; j++)
+                                if (modemux->muxregs[j].reg == 0xFFFF)
+                                        modemux->muxregs[j].reg = reg;
+                }
+        }
+}
+
+static int spear_pinctrl_get_groups_cnt(struct pinctrl_dev *pctldev)
+{
+        struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
+
+        return pmx->machdata->ngroups;
+}
+
+static const char *spear_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
+                unsigned group)
+{
+        struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
+
+        return pmx->machdata->groups[group]->name;
+}
+
+static int spear_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
+                unsigned group, const unsigned **pins, unsigned *num_pins)
+{
+        struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
+
+        *pins = pmx->machdata->groups[group]->pins;
+        *num_pins = pmx->machdata->groups[group]->npins;
+
+        return 0;
+}
+
+static void spear_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
+                struct seq_file *s, unsigned offset)
+{
+        seq_printf(s, " " DRIVER_NAME);
+}
+
+int spear_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
+                                 struct device_node *np_config,
+                                 struct pinctrl_map **map, unsigned *num_maps)
+{
+        struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
+        struct device_node *np;
+        struct property *prop;
+        const char *function, *group;
+        int ret, index = 0, count = 0;
+
+        /* calculate number of maps required */
+        for_each_child_of_node(np_config, np) {
+                ret = of_property_read_string(np, "st,function", &function);
+                if (ret < 0)
+                        return ret;
+
+                ret = of_property_count_strings(np, "st,pins");
+                if (ret < 0)
+                        return ret;
+
+                count += ret;
+        }
+
+        if (!count) {
+                dev_err(pmx->dev, "No child nodes passed via DT\n");
+                return -ENODEV;
+        }
+
+        *map = kzalloc(sizeof(**map) * count, GFP_KERNEL);
+        if (!*map)
+                return -ENOMEM;
+
+        for_each_child_of_node(np_config, np) {
+                of_property_read_string(np, "st,function", &function);
+                of_property_for_each_string(np, "st,pins", prop, group) {
+                        (*map)[index].type = PIN_MAP_TYPE_MUX_GROUP;
+                        (*map)[index].data.mux.group = group;
+                        (*map)[index].data.mux.function = function;
+                        index++;
+                }
+        }
+
+        *num_maps = count;
+
+        return 0;
+}
+
+void spear_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
+                struct pinctrl_map *map, unsigned num_maps)
+{
+        kfree(map);
+}
+
+static struct pinctrl_ops spear_pinctrl_ops = {
+        .get_groups_count = spear_pinctrl_get_groups_cnt,
+        .get_group_name = spear_pinctrl_get_group_name,
+        .get_group_pins = spear_pinctrl_get_group_pins,
+        .pin_dbg_show = spear_pinctrl_pin_dbg_show,
+        .dt_node_to_map = spear_pinctrl_dt_node_to_map,
+        .dt_free_map = spear_pinctrl_dt_free_map,
+};
+
+static int spear_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
+{
+        struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
+
+        return pmx->machdata->nfunctions;
+}
+
+static const char *spear_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
+                unsigned function)
+{
+        struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
+
+        return pmx->machdata->functions[function]->name;
+}
+
+static int spear_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
+                unsigned function, const char *const **groups,
+                unsigned * const ngroups)
+{
+        struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
+
+        *groups = pmx->machdata->functions[function]->groups;
+        *ngroups = pmx->machdata->functions[function]->ngroups;
+
+        return 0;
+}
+
+static int spear_pinctrl_endisable(struct pinctrl_dev *pctldev,
+                unsigned function, unsigned group, bool enable)
+{
+        struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
+        const struct spear_pingroup *pgroup;
+        const struct spear_modemux *modemux;
+        struct spear_muxreg *muxreg;
+        u32 val, temp;
+        int i, j;
+        bool found = false;
+
+        pgroup = pmx->machdata->groups[group];
+
+        for (i = 0; i < pgroup->nmodemuxs; i++) {
+                modemux = &pgroup->modemuxs[i];
+
+                /* SoC have any modes */
+                if (pmx->machdata->modes_supported) {
+                        if (!(pmx->machdata->mode & modemux->modes))
+                                continue;
+                }
+
+                found = true;
+                for (j = 0; j < modemux->nmuxregs; j++) {
+                        muxreg = &modemux->muxregs[j];
+
+                        val = pmx_readl(pmx, muxreg->reg);
+                        val &= ~muxreg->mask;
+
+                        if (enable)
+                                temp = muxreg->val;
+                        else
+                                temp = ~muxreg->val;
+
+                        val |= temp;
+                        pmx_writel(pmx, val, muxreg->reg);
+                }
+        }
+
+        if (!found) {
+                dev_err(pmx->dev, "pinmux group: %s not supported\n",
+                                pgroup->name);
+                return -ENODEV;
+        }
+
+        return 0;
+}
+
+static int spear_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
+                unsigned group)
+{
+        return spear_pinctrl_endisable(pctldev, function, group, true);
+}
+
+static void spear_pinctrl_disable(struct pinctrl_dev *pctldev,
+                unsigned function, unsigned group)
+{
+        spear_pinctrl_endisable(pctldev, function, group, false);
+}
+
+static struct pinmux_ops spear_pinmux_ops = {
+        .get_functions_count = spear_pinctrl_get_funcs_count,
+        .get_function_name = spear_pinctrl_get_func_name,
+        .get_function_groups = spear_pinctrl_get_func_groups,
+        .enable = spear_pinctrl_enable,
+        .disable = spear_pinctrl_disable,
+};
+
+static struct pinctrl_desc spear_pinctrl_desc = {
+        .name = DRIVER_NAME,
+        .pctlops = &spear_pinctrl_ops,
+        .pmxops = &spear_pinmux_ops,
+        .owner = THIS_MODULE,
+};
+
+int __devinit spear_pinctrl_probe(struct platform_device *pdev,
+                struct spear_pinctrl_machdata *machdata)
+{
+        struct device_node *np = pdev->dev.of_node;
+        struct resource *res;
+        struct spear_pmx *pmx;
+
+        if (!machdata)
+                return -ENODEV;
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!res)
+                return -EINVAL;
+
+        pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
+        if (!pmx) {
+                dev_err(&pdev->dev, "Can't alloc spear_pmx\n");
+                return -ENOMEM;
+        }
+
+        pmx->vbase = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+        if (!pmx->vbase) {
+                dev_err(&pdev->dev, "Couldn't ioremap at index 0\n");
+                return -ENODEV;
+        }
+
+        pmx->dev = &pdev->dev;
+        pmx->machdata = machdata;
+
+        /* configure mode, if supported by SoC */
+        if (machdata->modes_supported) {
+                int mode = 0;
+
+                if (of_property_read_u32(np, "st,pinmux-mode", &mode)) {
+                        dev_err(&pdev->dev, "OF: pinmux mode not passed\n");
+                        return -EINVAL;
+                }
+
+                if (set_mode(pmx, mode)) {
+                        dev_err(&pdev->dev, "OF: Couldn't configure mode: %x\n",
+                                        mode);
+                        return -EINVAL;
+                }
+        }
+
+        platform_set_drvdata(pdev, pmx);
+
+        spear_pinctrl_desc.pins = machdata->pins;
+        spear_pinctrl_desc.npins = machdata->npins;
+
+        pmx->pctl = pinctrl_register(&spear_pinctrl_desc, &pdev->dev, pmx);
+        if (IS_ERR(pmx->pctl)) {
+                dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
+                return PTR_ERR(pmx->pctl);
+        }
+
+        return 0;
+}
+
+int __devexit spear_pinctrl_remove(struct platform_device *pdev)
+{
+        struct spear_pmx *pmx = platform_get_drvdata(pdev);
+
+        pinctrl_unregister(pmx->pctl);
+
+        return 0;
+}
diff --git a/drivers/pinctrl/spear/pinctrl-spear.h b/drivers/pinctrl/spear/pinctrl-spear.h
new file mode 100644
index 000000000000..9155783bb47f
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear.h
@@ -0,0 +1,393 @@
+/*
+ * Driver header file for the ST Microelectronics SPEAr pinmux
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PINMUX_SPEAR_H__
+#define __PINMUX_SPEAR_H__
+
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/types.h>
+
+struct platform_device;
+struct device;
+
+/**
+ * struct spear_pmx_mode - SPEAr pmx mode
+ * @name: name of pmx mode
+ * @mode: mode id
+ * @reg: register for configuring this mode
+ * @mask: mask of this mode in reg
+ * @val: val to be configured at reg after doing (val & mask)
+ */
+struct spear_pmx_mode {
+        const char *const name;
+        u16 mode;
+        u16 reg;
+        u16 mask;
+        u32 val;
+};
+
+/**
+ * struct spear_muxreg - SPEAr mux reg configuration
+ * @reg: register offset
+ * @mask: mask bits
+ * @val: val to be written on mask bits
+ */
+struct spear_muxreg {
+        u16 reg;
+        u32 mask;
+        u32 val;
+};
+
+/**
+ * struct spear_modemux - SPEAr mode mux configuration
+ * @modes: mode ids supported by this group of muxregs
+ * @nmuxregs: number of muxreg configurations to be done for modes
+ * @muxregs: array of muxreg configurations to be done for modes
+ */
+struct spear_modemux {
+        u16 modes;
+        u8 nmuxregs;
+        struct spear_muxreg *muxregs;
+};
+
+/**
+ * struct spear_pingroup - SPEAr pin group configurations
+ * @name: name of pin group
+ * @pins: array containing pin numbers
+ * @npins: size of pins array
+ * @modemuxs: array of modemux configurations for this pin group
+ * @nmodemuxs: size of array modemuxs
+ *
+ * A representation of a group of pins in the SPEAr pin controller. Each group
+ * allows some parameter or parameters to be configured.
+ */
+struct spear_pingroup {
+        const char *name;
+        const unsigned *pins;
+        unsigned npins;
+        struct spear_modemux *modemuxs;
+        unsigned nmodemuxs;
+};
+
+/**
+ * struct spear_function - SPEAr pinctrl mux function
+ * @name: The name of the function, exported to pinctrl core.
+ * @groups: An array of pin groups that may select this function.
+ * @ngroups: The number of entries in @groups.
+ */
+struct spear_function {
+        const char *name;
+        const char *const *groups;
+        unsigned ngroups;
+};
+
+/**
+ * struct spear_pinctrl_machdata - SPEAr pin controller machine driver
+ *      configuration
+ * @pins: An array describing all pins the pin controller affects.
+ *      All pins which are also GPIOs must be listed first within the *array,
+ *      and be numbered identically to the GPIO controller's *numbering.
+ * @npins: The numbmer of entries in @pins.
+ * @functions: An array describing all mux functions the SoC supports.
+ * @nfunctions: The numbmer of entries in @functions.
+ * @groups: An array describing all pin groups the pin SoC supports.
+ * @ngroups: The numbmer of entries in @groups.
+ *
+ * @modes_supported: Does SoC support modes
+ * @mode: mode configured from probe
+ * @pmx_modes: array of modes supported by SoC
+ * @npmx_modes: number of entries in pmx_modes.
+ */
+struct spear_pinctrl_machdata {
+        const struct pinctrl_pin_desc *pins;
+        unsigned npins;
+        struct spear_function **functions;
+        unsigned nfunctions;
+        struct spear_pingroup **groups;
+        unsigned ngroups;
+
+        bool modes_supported;
+        u16 mode;
+        struct spear_pmx_mode **pmx_modes;
+        unsigned npmx_modes;
+};
+
+/**
+ * struct spear_pmx - SPEAr pinctrl mux
+ * @dev: pointer to struct dev of platform_device registered
+ * @pctl: pointer to struct pinctrl_dev
+ * @machdata: pointer to SoC or machine specific structure
+ * @vbase: virtual base address of pinmux controller
+ */
+struct spear_pmx {
+        struct device *dev;
+        struct pinctrl_dev *pctl;
+        struct spear_pinctrl_machdata *machdata;
+        void __iomem *vbase;
+};
+
+/* exported routines */
+void __devinit pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg);
+int __devinit spear_pinctrl_probe(struct platform_device *pdev,
+                struct spear_pinctrl_machdata *machdata);
+int __devexit spear_pinctrl_remove(struct platform_device *pdev);
+
+#define SPEAR_PIN_0_TO_101              \
+        PINCTRL_PIN(0, "PLGPIO0"),      \
+        PINCTRL_PIN(1, "PLGPIO1"),      \
+        PINCTRL_PIN(2, "PLGPIO2"),      \
+        PINCTRL_PIN(3, "PLGPIO3"),      \
+        PINCTRL_PIN(4, "PLGPIO4"),      \
+        PINCTRL_PIN(5, "PLGPIO5"),      \
+        PINCTRL_PIN(6, "PLGPIO6"),      \
+        PINCTRL_PIN(7, "PLGPIO7"),      \
+        PINCTRL_PIN(8, "PLGPIO8"),      \
+        PINCTRL_PIN(9, "PLGPIO9"),      \
+        PINCTRL_PIN(10, "PLGPIO10"),    \
+        PINCTRL_PIN(11, "PLGPIO11"),    \
+        PINCTRL_PIN(12, "PLGPIO12"),    \
+        PINCTRL_PIN(13, "PLGPIO13"),    \
+        PINCTRL_PIN(14, "PLGPIO14"),    \
+        PINCTRL_PIN(15, "PLGPIO15"),    \
+        PINCTRL_PIN(16, "PLGPIO16"),    \
+        PINCTRL_PIN(17, "PLGPIO17"),    \
+        PINCTRL_PIN(18, "PLGPIO18"),    \
+        PINCTRL_PIN(19, "PLGPIO19"),    \
+        PINCTRL_PIN(20, "PLGPIO20"),    \
+        PINCTRL_PIN(21, "PLGPIO21"),    \
+        PINCTRL_PIN(22, "PLGPIO22"),    \
+        PINCTRL_PIN(23, "PLGPIO23"),    \
+        PINCTRL_PIN(24, "PLGPIO24"),    \
+        PINCTRL_PIN(25, "PLGPIO25"),    \
+        PINCTRL_PIN(26, "PLGPIO26"),    \
+        PINCTRL_PIN(27, "PLGPIO27"),    \
+        PINCTRL_PIN(28, "PLGPIO28"),    \
+        PINCTRL_PIN(29, "PLGPIO29"),    \
+        PINCTRL_PIN(30, "PLGPIO30"),    \
+        PINCTRL_PIN(31, "PLGPIO31"),    \
+        PINCTRL_PIN(32, "PLGPIO32"),    \
+        PINCTRL_PIN(33, "PLGPIO33"),    \
+        PINCTRL_PIN(34, "PLGPIO34"),    \
+        PINCTRL_PIN(35, "PLGPIO35"),    \
+        PINCTRL_PIN(36, "PLGPIO36"),    \
+        PINCTRL_PIN(37, "PLGPIO37"),    \
+        PINCTRL_PIN(38, "PLGPIO38"),    \
+        PINCTRL_PIN(39, "PLGPIO39"),    \
+        PINCTRL_PIN(40, "PLGPIO40"),    \
+        PINCTRL_PIN(41, "PLGPIO41"),    \
+        PINCTRL_PIN(42, "PLGPIO42"),    \
+        PINCTRL_PIN(43, "PLGPIO43"),    \
+        PINCTRL_PIN(44, "PLGPIO44"),    \
+        PINCTRL_PIN(45, "PLGPIO45"),    \
+        PINCTRL_PIN(46, "PLGPIO46"),    \
+        PINCTRL_PIN(47, "PLGPIO47"),    \
+        PINCTRL_PIN(48, "PLGPIO48"),    \
+        PINCTRL_PIN(49, "PLGPIO49"),    \
+        PINCTRL_PIN(50, "PLGPIO50"),    \
+        PINCTRL_PIN(51, "PLGPIO51"),    \
+        PINCTRL_PIN(52, "PLGPIO52"),    \
+        PINCTRL_PIN(53, "PLGPIO53"),    \
+        PINCTRL_PIN(54, "PLGPIO54"),    \
+        PINCTRL_PIN(55, "PLGPIO55"),    \
+        PINCTRL_PIN(56, "PLGPIO56"),    \
+        PINCTRL_PIN(57, "PLGPIO57"),    \
+        PINCTRL_PIN(58, "PLGPIO58"),    \
+        PINCTRL_PIN(59, "PLGPIO59"),    \
+        PINCTRL_PIN(60, "PLGPIO60"),    \
+        PINCTRL_PIN(61, "PLGPIO61"),    \
+        PINCTRL_PIN(62, "PLGPIO62"),    \
+        PINCTRL_PIN(63, "PLGPIO63"),    \
+        PINCTRL_PIN(64, "PLGPIO64"),    \
+        PINCTRL_PIN(65, "PLGPIO65"),    \
+        PINCTRL_PIN(66, "PLGPIO66"),    \
+        PINCTRL_PIN(67, "PLGPIO67"),    \
+        PINCTRL_PIN(68, "PLGPIO68"),    \
+        PINCTRL_PIN(69, "PLGPIO69"),    \
+        PINCTRL_PIN(70, "PLGPIO70"),    \
+        PINCTRL_PIN(71, "PLGPIO71"),    \
+        PINCTRL_PIN(72, "PLGPIO72"),    \
+        PINCTRL_PIN(73, "PLGPIO73"),    \
+        PINCTRL_PIN(74, "PLGPIO74"),    \
+        PINCTRL_PIN(75, "PLGPIO75"),    \
+        PINCTRL_PIN(76, "PLGPIO76"),    \
+        PINCTRL_PIN(77, "PLGPIO77"),    \
+        PINCTRL_PIN(78, "PLGPIO78"),    \
+        PINCTRL_PIN(79, "PLGPIO79"),    \
+        PINCTRL_PIN(80, "PLGPIO80"),    \
+        PINCTRL_PIN(81, "PLGPIO81"),    \
+        PINCTRL_PIN(82, "PLGPIO82"),    \
+        PINCTRL_PIN(83, "PLGPIO83"),    \
+        PINCTRL_PIN(84, "PLGPIO84"),    \
+        PINCTRL_PIN(85, "PLGPIO85"),    \
+        PINCTRL_PIN(86, "PLGPIO86"),    \
+        PINCTRL_PIN(87, "PLGPIO87"),    \
+        PINCTRL_PIN(88, "PLGPIO88"),    \
+        PINCTRL_PIN(89, "PLGPIO89"),    \
+        PINCTRL_PIN(90, "PLGPIO90"),    \
+        PINCTRL_PIN(91, "PLGPIO91"),    \
+        PINCTRL_PIN(92, "PLGPIO92"),    \
+        PINCTRL_PIN(93, "PLGPIO93"),    \
+        PINCTRL_PIN(94, "PLGPIO94"),    \
+        PINCTRL_PIN(95, "PLGPIO95"),    \
+        PINCTRL_PIN(96, "PLGPIO96"),    \
+        PINCTRL_PIN(97, "PLGPIO97"),    \
+        PINCTRL_PIN(98, "PLGPIO98"),    \
+        PINCTRL_PIN(99, "PLGPIO99"),    \
+        PINCTRL_PIN(100, "PLGPIO100"),  \
+        PINCTRL_PIN(101, "PLGPIO101")
+
+#define SPEAR_PIN_102_TO_245            \
+        PINCTRL_PIN(102, "PLGPIO102"),  \
+        PINCTRL_PIN(103, "PLGPIO103"),  \
+        PINCTRL_PIN(104, "PLGPIO104"),  \
+        PINCTRL_PIN(105, "PLGPIO105"),  \
+        PINCTRL_PIN(106, "PLGPIO106"),  \
+        PINCTRL_PIN(107, "PLGPIO107"),  \
+        PINCTRL_PIN(108, "PLGPIO108"),  \
+        PINCTRL_PIN(109, "PLGPIO109"),  \
+        PINCTRL_PIN(110, "PLGPIO110"),  \
+        PINCTRL_PIN(111, "PLGPIO111"),  \
+        PINCTRL_PIN(112, "PLGPIO112"),  \
+        PINCTRL_PIN(113, "PLGPIO113"),  \
+        PINCTRL_PIN(114, "PLGPIO114"),  \
+        PINCTRL_PIN(115, "PLGPIO115"),  \
+        PINCTRL_PIN(116, "PLGPIO116"),  \
+        PINCTRL_PIN(117, "PLGPIO117"),  \
+        PINCTRL_PIN(118, "PLGPIO118"),  \
+        PINCTRL_PIN(119, "PLGPIO119"),  \
+        PINCTRL_PIN(120, "PLGPIO120"),  \
+        PINCTRL_PIN(121, "PLGPIO121"),  \
+        PINCTRL_PIN(122, "PLGPIO122"),  \
+        PINCTRL_PIN(123, "PLGPIO123"),  \
+        PINCTRL_PIN(124, "PLGPIO124"),  \
+        PINCTRL_PIN(125, "PLGPIO125"),  \
+        PINCTRL_PIN(126, "PLGPIO126"),  \
+        PINCTRL_PIN(127, "PLGPIO127"),  \
+        PINCTRL_PIN(128, "PLGPIO128"),  \
+        PINCTRL_PIN(129, "PLGPIO129"),  \
+        PINCTRL_PIN(130, "PLGPIO130"),  \
+        PINCTRL_PIN(131, "PLGPIO131"),  \
+        PINCTRL_PIN(132, "PLGPIO132"),  \
+        PINCTRL_PIN(133, "PLGPIO133"),  \
+        PINCTRL_PIN(134, "PLGPIO134"),  \
+        PINCTRL_PIN(135, "PLGPIO135"),  \
+        PINCTRL_PIN(136, "PLGPIO136"),  \
+        PINCTRL_PIN(137, "PLGPIO137"),  \
+        PINCTRL_PIN(138, "PLGPIO138"),  \
+        PINCTRL_PIN(139, "PLGPIO139"),  \
+        PINCTRL_PIN(140, "PLGPIO140"),  \
+        PINCTRL_PIN(141, "PLGPIO141"),  \
+        PINCTRL_PIN(142, "PLGPIO142"),  \
+        PINCTRL_PIN(143, "PLGPIO143"),  \
+        PINCTRL_PIN(144, "PLGPIO144"),  \
+        PINCTRL_PIN(145, "PLGPIO145"),  \
+        PINCTRL_PIN(146, "PLGPIO146"),  \
+        PINCTRL_PIN(147, "PLGPIO147"),  \
+        PINCTRL_PIN(148, "PLGPIO148"),  \
+        PINCTRL_PIN(149, "PLGPIO149"),  \
+        PINCTRL_PIN(150, "PLGPIO150"),  \
+        PINCTRL_PIN(151, "PLGPIO151"),  \
+        PINCTRL_PIN(152, "PLGPIO152"),  \
+        PINCTRL_PIN(153, "PLGPIO153"),  \
+        PINCTRL_PIN(154, "PLGPIO154"),  \
+        PINCTRL_PIN(155, "PLGPIO155"),  \
+        PINCTRL_PIN(156, "PLGPIO156"),  \
+        PINCTRL_PIN(157, "PLGPIO157"),  \
+        PINCTRL_PIN(158, "PLGPIO158"),  \
+        PINCTRL_PIN(159, "PLGPIO159"),  \
+        PINCTRL_PIN(160, "PLGPIO160"),  \
+        PINCTRL_PIN(161, "PLGPIO161"),  \
+        PINCTRL_PIN(162, "PLGPIO162"),  \
+        PINCTRL_PIN(163, "PLGPIO163"),  \
+        PINCTRL_PIN(164, "PLGPIO164"),  \
+        PINCTRL_PIN(165, "PLGPIO165"),  \
+        PINCTRL_PIN(166, "PLGPIO166"),  \
+        PINCTRL_PIN(167, "PLGPIO167"),  \
+        PINCTRL_PIN(168, "PLGPIO168"),  \
+        PINCTRL_PIN(169, "PLGPIO169"),  \
+        PINCTRL_PIN(170, "PLGPIO170"),  \
+        PINCTRL_PIN(171, "PLGPIO171"),  \
+        PINCTRL_PIN(172, "PLGPIO172"),  \
+        PINCTRL_PIN(173, "PLGPIO173"),  \
+        PINCTRL_PIN(174, "PLGPIO174"),  \
+        PINCTRL_PIN(175, "PLGPIO175"),  \
+        PINCTRL_PIN(176, "PLGPIO176"),  \
+        PINCTRL_PIN(177, "PLGPIO177"),  \
+        PINCTRL_PIN(178, "PLGPIO178"),  \
+        PINCTRL_PIN(179, "PLGPIO179"),  \
+        PINCTRL_PIN(180, "PLGPIO180"),  \
+        PINCTRL_PIN(181, "PLGPIO181"),  \
+        PINCTRL_PIN(182, "PLGPIO182"),  \
+        PINCTRL_PIN(183, "PLGPIO183"),  \
+        PINCTRL_PIN(184, "PLGPIO184"),  \
+        PINCTRL_PIN(185, "PLGPIO185"),  \
+        PINCTRL_PIN(186, "PLGPIO186"),  \
+        PINCTRL_PIN(187, "PLGPIO187"),  \
+        PINCTRL_PIN(188, "PLGPIO188"),  \
+        PINCTRL_PIN(189, "PLGPIO189"),  \
+        PINCTRL_PIN(190, "PLGPIO190"),  \
+        PINCTRL_PIN(191, "PLGPIO191"),  \
+        PINCTRL_PIN(192, "PLGPIO192"),  \
+        PINCTRL_PIN(193, "PLGPIO193"),  \
+        PINCTRL_PIN(194, "PLGPIO194"),  \
+        PINCTRL_PIN(195, "PLGPIO195"),  \
+        PINCTRL_PIN(196, "PLGPIO196"),  \
+        PINCTRL_PIN(197, "PLGPIO197"),  \
+        PINCTRL_PIN(198, "PLGPIO198"),  \
+        PINCTRL_PIN(199, "PLGPIO199"),  \
+        PINCTRL_PIN(200, "PLGPIO200"),  \
+        PINCTRL_PIN(201, "PLGPIO201"),  \
+        PINCTRL_PIN(202, "PLGPIO202"),  \
+        PINCTRL_PIN(203, "PLGPIO203"),  \
+        PINCTRL_PIN(204, "PLGPIO204"),  \
+        PINCTRL_PIN(205, "PLGPIO205"),  \
+        PINCTRL_PIN(206, "PLGPIO206"),  \
+        PINCTRL_PIN(207, "PLGPIO207"),  \
+        PINCTRL_PIN(208, "PLGPIO208"),  \
+        PINCTRL_PIN(209, "PLGPIO209"),  \
+        PINCTRL_PIN(210, "PLGPIO210"),  \
+        PINCTRL_PIN(211, "PLGPIO211"),  \
+        PINCTRL_PIN(212, "PLGPIO212"),  \
+        PINCTRL_PIN(213, "PLGPIO213"),  \
+        PINCTRL_PIN(214, "PLGPIO214"),  \
+        PINCTRL_PIN(215, "PLGPIO215"),  \
+        PINCTRL_PIN(216, "PLGPIO216"),  \
+        PINCTRL_PIN(217, "PLGPIO217"),  \
+        PINCTRL_PIN(218, "PLGPIO218"),  \
+        PINCTRL_PIN(219, "PLGPIO219"),  \
+        PINCTRL_PIN(220, "PLGPIO220"),  \
+        PINCTRL_PIN(221, "PLGPIO221"),  \
+        PINCTRL_PIN(222, "PLGPIO222"),  \
+        PINCTRL_PIN(223, "PLGPIO223"),  \
+        PINCTRL_PIN(224, "PLGPIO224"),  \
+        PINCTRL_PIN(225, "PLGPIO225"),  \
+        PINCTRL_PIN(226, "PLGPIO226"),  \
+        PINCTRL_PIN(227, "PLGPIO227"),  \
+        PINCTRL_PIN(228, "PLGPIO228"),  \
+        PINCTRL_PIN(229, "PLGPIO229"),  \
+        PINCTRL_PIN(230, "PLGPIO230"),  \
+        PINCTRL_PIN(231, "PLGPIO231"),  \
+        PINCTRL_PIN(232, "PLGPIO232"),  \
+        PINCTRL_PIN(233, "PLGPIO233"),  \
+        PINCTRL_PIN(234, "PLGPIO234"),  \
+        PINCTRL_PIN(235, "PLGPIO235"),  \
+        PINCTRL_PIN(236, "PLGPIO236"),  \
+        PINCTRL_PIN(237, "PLGPIO237"),  \
+        PINCTRL_PIN(238, "PLGPIO238"),  \
+        PINCTRL_PIN(239, "PLGPIO239"),  \
+        PINCTRL_PIN(240, "PLGPIO240"),  \
+        PINCTRL_PIN(241, "PLGPIO241"),  \
+        PINCTRL_PIN(242, "PLGPIO242"),  \
+        PINCTRL_PIN(243, "PLGPIO243"),  \
+        PINCTRL_PIN(244, "PLGPIO244"),  \
+        PINCTRL_PIN(245, "PLGPIO245")
+
+#endif /* __PINMUX_SPEAR_H__ */
diff --git a/drivers/pinctrl/spear/pinctrl-spear1310.c b/drivers/pinctrl/spear/pinctrl-spear1310.c
new file mode 100644
index 000000000000..fff168be7f00
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear1310.c
@@ -0,0 +1,2198 @@
+/*
+ * Driver for the ST Microelectronics SPEAr1310 pinmux
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include "pinctrl-spear.h"
+
+#define DRIVER_NAME "spear1310-pinmux"
+
+/* pins */
+static const struct pinctrl_pin_desc spear1310_pins[] = {
+        SPEAR_PIN_0_TO_101,
+        SPEAR_PIN_102_TO_245,
+};
+
+/* registers */
+#define PERIP_CFG                                       0x32C
+        #define MCIF_SEL_SHIFT                          3
+        #define MCIF_SEL_SD                             (0x1 << MCIF_SEL_SHIFT)
+        #define MCIF_SEL_CF                             (0x2 << MCIF_SEL_SHIFT)
+        #define MCIF_SEL_XD                             (0x3 << MCIF_SEL_SHIFT)
+        #define MCIF_SEL_MASK                           (0x3 << MCIF_SEL_SHIFT)
+
+#define PCIE_SATA_CFG                                   0x3A4
+        #define PCIE_SATA2_SEL_PCIE                     (0 << 31)
+        #define PCIE_SATA1_SEL_PCIE                     (0 << 30)
+        #define PCIE_SATA0_SEL_PCIE                     (0 << 29)
+        #define PCIE_SATA2_SEL_SATA                     (1 << 31)
+        #define PCIE_SATA1_SEL_SATA                     (1 << 30)
+        #define PCIE_SATA0_SEL_SATA                     (1 << 29)
+        #define SATA2_CFG_TX_CLK_EN                     (1 << 27)
+        #define SATA2_CFG_RX_CLK_EN                     (1 << 26)
+        #define SATA2_CFG_POWERUP_RESET                 (1 << 25)
+        #define SATA2_CFG_PM_CLK_EN                     (1 << 24)
+        #define SATA1_CFG_TX_CLK_EN                     (1 << 23)
+        #define SATA1_CFG_RX_CLK_EN                     (1 << 22)
+        #define SATA1_CFG_POWERUP_RESET                 (1 << 21)
+        #define SATA1_CFG_PM_CLK_EN                     (1 << 20)
+        #define SATA0_CFG_TX_CLK_EN                     (1 << 19)
+        #define SATA0_CFG_RX_CLK_EN                     (1 << 18)
+        #define SATA0_CFG_POWERUP_RESET                 (1 << 17)
+        #define SATA0_CFG_PM_CLK_EN                     (1 << 16)
+        #define PCIE2_CFG_DEVICE_PRESENT                (1 << 11)
+        #define PCIE2_CFG_POWERUP_RESET                 (1 << 10)
+        #define PCIE2_CFG_CORE_CLK_EN                   (1 << 9)
+        #define PCIE2_CFG_AUX_CLK_EN                    (1 << 8)
+        #define PCIE1_CFG_DEVICE_PRESENT                (1 << 7)
+        #define PCIE1_CFG_POWERUP_RESET                 (1 << 6)
+        #define PCIE1_CFG_CORE_CLK_EN                   (1 << 5)
+        #define PCIE1_CFG_AUX_CLK_EN                    (1 << 4)
+        #define PCIE0_CFG_DEVICE_PRESENT                (1 << 3)
+        #define PCIE0_CFG_POWERUP_RESET                 (1 << 2)
+        #define PCIE0_CFG_CORE_CLK_EN                   (1 << 1)
+        #define PCIE0_CFG_AUX_CLK_EN                    (1 << 0)
+
+#define PAD_FUNCTION_EN_0                               0x650
+        #define PMX_UART0_MASK                          (1 << 1)
+        #define PMX_I2C0_MASK                           (1 << 2)
+        #define PMX_I2S0_MASK                           (1 << 3)
+        #define PMX_SSP0_MASK                           (1 << 4)
+        #define PMX_CLCD1_MASK                          (1 << 5)
+        #define PMX_EGPIO00_MASK                        (1 << 6)
+        #define PMX_EGPIO01_MASK                        (1 << 7)
+        #define PMX_EGPIO02_MASK                        (1 << 8)
+        #define PMX_EGPIO03_MASK                        (1 << 9)
+        #define PMX_EGPIO04_MASK                        (1 << 10)
+        #define PMX_EGPIO05_MASK                        (1 << 11)
+        #define PMX_EGPIO06_MASK                        (1 << 12)
+        #define PMX_EGPIO07_MASK                        (1 << 13)
+        #define PMX_EGPIO08_MASK                        (1 << 14)
+        #define PMX_EGPIO09_MASK                        (1 << 15)
+        #define PMX_SMI_MASK                            (1 << 16)
+        #define PMX_NAND8_MASK                          (1 << 17)
+        #define PMX_GMIICLK_MASK                        (1 << 18)
+        #define PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK    (1 << 19)
+        #define PMX_RXCLK_RDV_TXEN_D03_MASK             (1 << 20)
+        #define PMX_GMIID47_MASK                        (1 << 21)
+        #define PMX_MDC_MDIO_MASK                       (1 << 22)
+        #define PMX_MCI_DATA8_15_MASK                   (1 << 23)
+        #define PMX_NFAD23_MASK                         (1 << 24)
+        #define PMX_NFAD24_MASK                         (1 << 25)
+        #define PMX_NFAD25_MASK                         (1 << 26)
+        #define PMX_NFCE3_MASK                          (1 << 27)
+        #define PMX_NFWPRT3_MASK                        (1 << 28)
+        #define PMX_NFRSTPWDWN0_MASK                    (1 << 29)
+        #define PMX_NFRSTPWDWN1_MASK                    (1 << 30)
+        #define PMX_NFRSTPWDWN2_MASK                    (1 << 31)
+
+#define PAD_FUNCTION_EN_1                               0x654
+        #define PMX_NFRSTPWDWN3_MASK                    (1 << 0)
+        #define PMX_SMINCS2_MASK                        (1 << 1)
+        #define PMX_SMINCS3_MASK                        (1 << 2)
+        #define PMX_CLCD2_MASK                          (1 << 3)
+        #define PMX_KBD_ROWCOL68_MASK                   (1 << 4)
+        #define PMX_EGPIO10_MASK                        (1 << 5)
+        #define PMX_EGPIO11_MASK                        (1 << 6)
+        #define PMX_EGPIO12_MASK                        (1 << 7)
+        #define PMX_EGPIO13_MASK                        (1 << 8)
+        #define PMX_EGPIO14_MASK                        (1 << 9)
+        #define PMX_EGPIO15_MASK                        (1 << 10)
+        #define PMX_UART0_MODEM_MASK                    (1 << 11)
+        #define PMX_GPT0_TMR0_MASK                      (1 << 12)
+        #define PMX_GPT0_TMR1_MASK                      (1 << 13)
+        #define PMX_GPT1_TMR0_MASK                      (1 << 14)
+        #define PMX_GPT1_TMR1_MASK                      (1 << 15)
+        #define PMX_I2S1_MASK                           (1 << 16)
+        #define PMX_KBD_ROWCOL25_MASK                   (1 << 17)
+        #define PMX_NFIO8_15_MASK                       (1 << 18)
+        #define PMX_KBD_COL1_MASK                       (1 << 19)
+        #define PMX_NFCE1_MASK                          (1 << 20)
+        #define PMX_KBD_COL0_MASK                       (1 << 21)
+        #define PMX_NFCE2_MASK                          (1 << 22)
+        #define PMX_KBD_ROW1_MASK                       (1 << 23)
+        #define PMX_NFWPRT1_MASK                        (1 << 24)
+        #define PMX_KBD_ROW0_MASK                       (1 << 25)
+        #define PMX_NFWPRT2_MASK                        (1 << 26)
+        #define PMX_MCIDATA0_MASK                       (1 << 27)
+        #define PMX_MCIDATA1_MASK                       (1 << 28)
+        #define PMX_MCIDATA2_MASK                       (1 << 29)
+        #define PMX_MCIDATA3_MASK                       (1 << 30)
+        #define PMX_MCIDATA4_MASK                       (1 << 31)
+
+#define PAD_FUNCTION_EN_2                               0x658
+        #define PMX_MCIDATA5_MASK                       (1 << 0)
+        #define PMX_MCIDATA6_MASK                       (1 << 1)
+        #define PMX_MCIDATA7_MASK                       (1 << 2)
+        #define PMX_MCIDATA1SD_MASK                     (1 << 3)
+        #define PMX_MCIDATA2SD_MASK                     (1 << 4)
+        #define PMX_MCIDATA3SD_MASK                     (1 << 5)
+        #define PMX_MCIADDR0ALE_MASK                    (1 << 6)
+        #define PMX_MCIADDR1CLECLK_MASK                 (1 << 7)
+        #define PMX_MCIADDR2_MASK                       (1 << 8)
+        #define PMX_MCICECF_MASK                        (1 << 9)
+        #define PMX_MCICEXD_MASK                        (1 << 10)
+        #define PMX_MCICESDMMC_MASK                     (1 << 11)
+        #define PMX_MCICDCF1_MASK                       (1 << 12)
+        #define PMX_MCICDCF2_MASK                       (1 << 13)
+        #define PMX_MCICDXD_MASK                        (1 << 14)
+        #define PMX_MCICDSDMMC_MASK                     (1 << 15)
+        #define PMX_MCIDATADIR_MASK                     (1 << 16)
+        #define PMX_MCIDMARQWP_MASK                     (1 << 17)
+        #define PMX_MCIIORDRE_MASK                      (1 << 18)
+        #define PMX_MCIIOWRWE_MASK                      (1 << 19)
+        #define PMX_MCIRESETCF_MASK                     (1 << 20)
+        #define PMX_MCICS0CE_MASK                       (1 << 21)
+        #define PMX_MCICFINTR_MASK                      (1 << 22)
+        #define PMX_MCIIORDY_MASK                       (1 << 23)
+        #define PMX_MCICS1_MASK                         (1 << 24)
+        #define PMX_MCIDMAACK_MASK                      (1 << 25)
+        #define PMX_MCISDCMD_MASK                       (1 << 26)
+        #define PMX_MCILEDS_MASK                        (1 << 27)
+        #define PMX_TOUCH_XY_MASK                       (1 << 28)
+        #define PMX_SSP0_CS0_MASK                       (1 << 29)
+        #define PMX_SSP0_CS1_2_MASK                     (1 << 30)
+
+/* combined macros */
+#define PMX_GMII_MASK           (PMX_GMIICLK_MASK |                     \
+                                PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK |  \
+                                PMX_RXCLK_RDV_TXEN_D03_MASK |           \
+                                PMX_GMIID47_MASK | PMX_MDC_MDIO_MASK)
+
+#define PMX_EGPIO_0_GRP_MASK    (PMX_EGPIO00_MASK | PMX_EGPIO01_MASK |  \
+                                PMX_EGPIO02_MASK |                      \
+                                PMX_EGPIO03_MASK | PMX_EGPIO04_MASK |   \
+                                PMX_EGPIO05_MASK | PMX_EGPIO06_MASK |   \
+                                PMX_EGPIO07_MASK | PMX_EGPIO08_MASK |   \
+                                PMX_EGPIO09_MASK)
+#define PMX_EGPIO_1_GRP_MASK    (PMX_EGPIO10_MASK | PMX_EGPIO11_MASK |  \
+                                PMX_EGPIO12_MASK | PMX_EGPIO13_MASK |   \
+                                PMX_EGPIO14_MASK | PMX_EGPIO15_MASK)
+
+#define PMX_KEYBOARD_6X6_MASK   (PMX_KBD_ROW0_MASK | PMX_KBD_ROW1_MASK | \
+                                PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL0_MASK | \
+                                PMX_KBD_COL1_MASK)
+
+#define PMX_NAND8BIT_0_MASK     (PMX_NAND8_MASK | PMX_NFAD23_MASK |     \
+                                PMX_NFAD24_MASK | PMX_NFAD25_MASK |     \
+                                PMX_NFWPRT3_MASK | PMX_NFRSTPWDWN0_MASK | \
+                                PMX_NFRSTPWDWN1_MASK | PMX_NFRSTPWDWN2_MASK | \
+                                PMX_NFCE3_MASK)
+#define PMX_NAND8BIT_1_MASK     PMX_NFRSTPWDWN3_MASK
+
+#define PMX_NAND16BIT_1_MASK    (PMX_KBD_ROWCOL25_MASK | PMX_NFIO8_15_MASK)
+#define PMX_NAND_4CHIPS_MASK    (PMX_NFCE1_MASK | PMX_NFCE2_MASK |      \
+                                PMX_NFWPRT1_MASK | PMX_NFWPRT2_MASK |   \
+                                PMX_KBD_ROW0_MASK | PMX_KBD_ROW1_MASK | \
+                                PMX_KBD_COL0_MASK | PMX_KBD_COL1_MASK)
+
+#define PMX_MCIFALL_1_MASK      0xF8000000
+#define PMX_MCIFALL_2_MASK      0x0FFFFFFF
+
+#define PMX_PCI_REG1_MASK       (PMX_SMINCS2_MASK | PMX_SMINCS3_MASK |  \
+                                PMX_CLCD2_MASK | PMX_KBD_ROWCOL68_MASK | \
+                                PMX_EGPIO_1_GRP_MASK | PMX_GPT0_TMR0_MASK | \
+                                PMX_GPT0_TMR1_MASK | PMX_GPT1_TMR0_MASK | \
+                                PMX_GPT1_TMR1_MASK | PMX_I2S1_MASK |    \
+                                PMX_NFCE2_MASK)
+#define PMX_PCI_REG2_MASK       (PMX_TOUCH_XY_MASK | PMX_SSP0_CS0_MASK | \
+                                PMX_SSP0_CS1_2_MASK)
+
+#define PMX_SMII_0_1_2_MASK     (PMX_CLCD2_MASK | PMX_KBD_ROWCOL68_MASK)
+#define PMX_RGMII_REG0_MASK     (PMX_MCI_DATA8_15_MASK |                \
+                                PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK |  \
+                                PMX_GMIID47_MASK)
+#define PMX_RGMII_REG1_MASK     (PMX_KBD_ROWCOL68_MASK | PMX_EGPIO_1_GRP_MASK |\
+                                PMX_KBD_ROW1_MASK | PMX_NFWPRT1_MASK |  \
+                                PMX_KBD_ROW0_MASK | PMX_NFWPRT2_MASK)
+#define PMX_RGMII_REG2_MASK     (PMX_TOUCH_XY_MASK | PMX_SSP0_CS0_MASK | \
+                                PMX_SSP0_CS1_2_MASK)
+
+#define PCIE_CFG_VAL(x)         (PCIE_SATA##x##_SEL_PCIE |      \
+                                PCIE##x##_CFG_AUX_CLK_EN |      \
+                                PCIE##x##_CFG_CORE_CLK_EN |     \
+                                PCIE##x##_CFG_POWERUP_RESET |   \
+                                PCIE##x##_CFG_DEVICE_PRESENT)
+#define SATA_CFG_VAL(x)         (PCIE_SATA##x##_SEL_SATA |      \
+                                SATA##x##_CFG_PM_CLK_EN |       \
+                                SATA##x##_CFG_POWERUP_RESET |   \
+                                SATA##x##_CFG_RX_CLK_EN |       \
+                                SATA##x##_CFG_TX_CLK_EN)
+
+/* Pad multiplexing for i2c0 device */
+static const unsigned i2c0_pins[] = { 102, 103 };
+static struct spear_muxreg i2c0_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_0,
+                .mask = PMX_I2C0_MASK,
+                .val = PMX_I2C0_MASK,
+        },
+};
+
+static struct spear_modemux i2c0_modemux[] = {
+        {
+                .muxregs = i2c0_muxreg,
+                .nmuxregs = ARRAY_SIZE(i2c0_muxreg),
+        },
+};
+
+static struct spear_pingroup i2c0_pingroup = {
+        .name = "i2c0_grp",
+        .pins = i2c0_pins,
+        .npins = ARRAY_SIZE(i2c0_pins),
+        .modemuxs = i2c0_modemux,
+        .nmodemuxs = ARRAY_SIZE(i2c0_modemux),
+};
+
+static const char *const i2c0_grps[] = { "i2c0_grp" };
+static struct spear_function i2c0_function = {
+        .name = "i2c0",
+        .groups = i2c0_grps,
+        .ngroups = ARRAY_SIZE(i2c0_grps),
+};
+
+/* Pad multiplexing for ssp0 device */
+static const unsigned ssp0_pins[] = { 109, 110, 111, 112 };
+static struct spear_muxreg ssp0_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_0,
+                .mask = PMX_SSP0_MASK,
+                .val = PMX_SSP0_MASK,
+        },
+};
+
+static struct spear_modemux ssp0_modemux[] = {
+        {
+                .muxregs = ssp0_muxreg,
+                .nmuxregs = ARRAY_SIZE(ssp0_muxreg),
+        },
+};
+
+static struct spear_pingroup ssp0_pingroup = {
+        .name = "ssp0_grp",
+        .pins = ssp0_pins,
+        .npins = ARRAY_SIZE(ssp0_pins),
+        .modemuxs = ssp0_modemux,
+        .nmodemuxs = ARRAY_SIZE(ssp0_modemux),
+};
+
+/* Pad multiplexing for ssp0_cs0 device */
+static const unsigned ssp0_cs0_pins[] = { 96 };
+static struct spear_muxreg ssp0_cs0_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_2,
+                .mask = PMX_SSP0_CS0_MASK,
+                .val = PMX_SSP0_CS0_MASK,
+        },
+};
+
+static struct spear_modemux ssp0_cs0_modemux[] = {
+        {
+                .muxregs = ssp0_cs0_muxreg,
+                .nmuxregs = ARRAY_SIZE(ssp0_cs0_muxreg),
+        },
+};
+
+static struct spear_pingroup ssp0_cs0_pingroup = {
+        .name = "ssp0_cs0_grp",
+        .pins = ssp0_cs0_pins,
+        .npins = ARRAY_SIZE(ssp0_cs0_pins),
+        .modemuxs = ssp0_cs0_modemux,
+        .nmodemuxs = ARRAY_SIZE(ssp0_cs0_modemux),
+};
+
+/* ssp0_cs1_2 device */
+static const unsigned ssp0_cs1_2_pins[] = { 94, 95 };
+static struct spear_muxreg ssp0_cs1_2_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_2,
+                .mask = PMX_SSP0_CS1_2_MASK,
+                .val = PMX_SSP0_CS1_2_MASK,
+        },
+};
+
+static struct spear_modemux ssp0_cs1_2_modemux[] = {
+        {
+                .muxregs = ssp0_cs1_2_muxreg,
+                .nmuxregs = ARRAY_SIZE(ssp0_cs1_2_muxreg),
+        },
+};
+
+static struct spear_pingroup ssp0_cs1_2_pingroup = {
+        .name = "ssp0_cs1_2_grp",
+        .pins = ssp0_cs1_2_pins,
+        .npins = ARRAY_SIZE(ssp0_cs1_2_pins),
+        .modemuxs = ssp0_cs1_2_modemux,
+        .nmodemuxs = ARRAY_SIZE(ssp0_cs1_2_modemux),
+};
+
+static const char *const ssp0_grps[] = { "ssp0_grp", "ssp0_cs0_grp",
+        "ssp0_cs1_2_grp" };
+static struct spear_function ssp0_function = {
+        .name = "ssp0",
+        .groups = ssp0_grps,
+        .ngroups = ARRAY_SIZE(ssp0_grps),
+};
+
+/* Pad multiplexing for i2s0 device */
+static const unsigned i2s0_pins[] = { 104, 105, 106, 107, 108 };
+static struct spear_muxreg i2s0_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_0,
+                .mask = PMX_I2S0_MASK,
+                .val = PMX_I2S0_MASK,
+        },
+};
+
+static struct spear_modemux i2s0_modemux[] = {
+        {
+                .muxregs = i2s0_muxreg,
+                .nmuxregs = ARRAY_SIZE(i2s0_muxreg),
+        },
+};
+
+static struct spear_pingroup i2s0_pingroup = {
+        .name = "i2s0_grp",
+        .pins = i2s0_pins,
+        .npins = ARRAY_SIZE(i2s0_pins),
+        .modemuxs = i2s0_modemux,
+        .nmodemuxs = ARRAY_SIZE(i2s0_modemux),
+};
+
+static const char *const i2s0_grps[] = { "i2s0_grp" };
+static struct spear_function i2s0_function = {
+        .name = "i2s0",
+        .groups = i2s0_grps,
+        .ngroups = ARRAY_SIZE(i2s0_grps),
+};
+
+/* Pad multiplexing for i2s1 device */
+static const unsigned i2s1_pins[] = { 0, 1, 2, 3 };
+static struct spear_muxreg i2s1_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_1,
+                .mask = PMX_I2S1_MASK,
+                .val = PMX_I2S1_MASK,
+        },
+};
+
+static struct spear_modemux i2s1_modemux[] = {
+        {
+                .muxregs = i2s1_muxreg,
+                .nmuxregs = ARRAY_SIZE(i2s1_muxreg),
+        },
+};
+
+static struct spear_pingroup i2s1_pingroup = {
+        .name = "i2s1_grp",
+        .pins = i2s1_pins,
+        .npins = ARRAY_SIZE(i2s1_pins),
+        .modemuxs = i2s1_modemux,
+        .nmodemuxs = ARRAY_SIZE(i2s1_modemux),
+};
+
+static const char *const i2s1_grps[] = { "i2s1_grp" };
+static struct spear_function i2s1_function = {
+        .name = "i2s1",
+        .groups = i2s1_grps,
+        .ngroups = ARRAY_SIZE(i2s1_grps),
+};
+
+/* Pad multiplexing for clcd device */
+static const unsigned clcd_pins[] = { 113, 114, 115, 116, 117, 118, 119, 120,
+        121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134,
+        135, 136, 137, 138, 139, 140, 141, 142 };
+static struct spear_muxreg clcd_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_0,
+                .mask = PMX_CLCD1_MASK,
+                .val = PMX_CLCD1_MASK,
+        },
+};
+
+static struct spear_modemux clcd_modemux[] = {
+        {
+                .muxregs = clcd_muxreg,
+                .nmuxregs = ARRAY_SIZE(clcd_muxreg),
+        },
+};
+
+static struct spear_pingroup clcd_pingroup = {
+        .name = "clcd_grp",
+        .pins = clcd_pins,
+        .npins = ARRAY_SIZE(clcd_pins),
+        .modemuxs = clcd_modemux,
+        .nmodemuxs = ARRAY_SIZE(clcd_modemux),
+};
+
+static const unsigned clcd_high_res_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37,
+        38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53 };
+static struct spear_muxreg clcd_high_res_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_1,
+                .mask = PMX_CLCD2_MASK,
+                .val = PMX_CLCD2_MASK,
+        },
+};
+
+static struct spear_modemux clcd_high_res_modemux[] = {
+        {
+                .muxregs = clcd_high_res_muxreg,
+                .nmuxregs = ARRAY_SIZE(clcd_high_res_muxreg),
+        },
+};
+
+static struct spear_pingroup clcd_high_res_pingroup = {
+        .name = "clcd_high_res_grp",
+        .pins = clcd_high_res_pins,
+        .npins = ARRAY_SIZE(clcd_high_res_pins),
+        .modemuxs = clcd_high_res_modemux,
+        .nmodemuxs = ARRAY_SIZE(clcd_high_res_modemux),
+};
+
+static const char *const clcd_grps[] = { "clcd_grp", "clcd_high_res" };
+static struct spear_function clcd_function = {
+        .name = "clcd",
+        .groups = clcd_grps,
+        .ngroups = ARRAY_SIZE(clcd_grps),
+};
+
+static const unsigned arm_gpio_pins[] = { 18, 19, 20, 21, 22, 23, 143, 144, 145,
+        146, 147, 148, 149, 150, 151, 152 };
+static struct spear_muxreg arm_gpio_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_0,
+                .mask = PMX_EGPIO_0_GRP_MASK,
+                .val = PMX_EGPIO_0_GRP_MASK,
+        }, {
+                .reg = PAD_FUNCTION_EN_1,
+                .mask = PMX_EGPIO_1_GRP_MASK,
+                .val = PMX_EGPIO_1_GRP_MASK,
+        },
+};
+
+static struct spear_modemux arm_gpio_modemux[] = {
+        {
+                .muxregs = arm_gpio_muxreg,
+                .nmuxregs = ARRAY_SIZE(arm_gpio_muxreg),
+        },
+};
+
+static struct spear_pingroup arm_gpio_pingroup = {
+        .name = "arm_gpio_grp",
+        .pins = arm_gpio_pins,
+        .npins = ARRAY_SIZE(arm_gpio_pins),
+        .modemuxs = arm_gpio_modemux,
+        .nmodemuxs = ARRAY_SIZE(arm_gpio_modemux),
+};
+
+static const char *const arm_gpio_grps[] = { "arm_gpio_grp" };
+static struct spear_function arm_gpio_function = {
+        .name = "arm_gpio",
+        .groups = arm_gpio_grps,
+        .ngroups = ARRAY_SIZE(arm_gpio_grps),
+};
+
+/* Pad multiplexing for smi 2 chips device */
+static const unsigned smi_2_chips_pins[] = { 153, 154, 155, 156, 157 };
+static struct spear_muxreg smi_2_chips_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_0,
+                .mask = PMX_SMI_MASK,
+                .val = PMX_SMI_MASK,
+        },
+};
+
+static struct spear_modemux smi_2_chips_modemux[] = {
+        {
+                .muxregs = smi_2_chips_muxreg,
+                .nmuxregs = ARRAY_SIZE(smi_2_chips_muxreg),
+        },
+};
+
+static struct spear_pingroup smi_2_chips_pingroup = {
+        .name = "smi_2_chips_grp",
+        .pins = smi_2_chips_pins,
+        .npins = ARRAY_SIZE(smi_2_chips_pins),
+        .modemuxs = smi_2_chips_modemux,
+        .nmodemuxs = ARRAY_SIZE(smi_2_chips_modemux),
+};
+
+static const unsigned smi_4_chips_pins[] = { 54, 55 };
+static struct spear_muxreg smi_4_chips_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_0,
+                .mask = PMX_SMI_MASK,
+                .val = PMX_SMI_MASK,
+        }, {
+                .reg = PAD_FUNCTION_EN_1,
+                .mask = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
+                .val = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
+        },
+};
+
+static struct spear_modemux smi_4_chips_modemux[] = {
+        {
+                .muxregs = smi_4_chips_muxreg,
+                .nmuxregs = ARRAY_SIZE(smi_4_chips_muxreg),
+        },
+};
+
+static struct spear_pingroup smi_4_chips_pingroup = {
+        .name = "smi_4_chips_grp",
+        .pins = smi_4_chips_pins,
+        .npins = ARRAY_SIZE(smi_4_chips_pins),
+        .modemuxs = smi_4_chips_modemux,
+        .nmodemuxs = ARRAY_SIZE(smi_4_chips_modemux),
+};
+
+static const char *const smi_grps[] = { "smi_2_chips_grp", "smi_4_chips_grp" };
+static struct spear_function smi_function = {
+        .name = "smi",
+        .groups = smi_grps,
+        .ngroups = ARRAY_SIZE(smi_grps),
+};
+
+/* Pad multiplexing for gmii device */
+static const unsigned gmii_pins[] = { 173, 174, 175, 176, 177, 178, 179, 180,
+        181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194,
+        195, 196, 197, 198, 199, 200 };
+static struct spear_muxreg gmii_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_0,
+                .mask = PMX_GMII_MASK,
+                .val = PMX_GMII_MASK,
+        },
+};
+
+static struct spear_modemux gmii_modemux[] = {
+        {
+                .muxregs = gmii_muxreg,
+                .nmuxregs = ARRAY_SIZE(gmii_muxreg),
+        },
+};
+
+static struct spear_pingroup gmii_pingroup = {
+        .name = "gmii_grp",
+        .pins = gmii_pins,
+        .npins = ARRAY_SIZE(gmii_pins),
+        .modemuxs = gmii_modemux,
+        .nmodemuxs = ARRAY_SIZE(gmii_modemux),
+};
+
+static const char *const gmii_grps[] = { "gmii_grp" };
+static struct spear_function gmii_function = {
+        .name = "gmii",
+        .groups = gmii_grps,
+        .ngroups = ARRAY_SIZE(gmii_grps),
+};
+
+/* Pad multiplexing for rgmii device */
+static const unsigned rgmii_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,
+        28, 29, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 175,
+        180, 181, 182, 183, 185, 188, 193, 194, 195, 196, 197, 198, 211, 212 };
+static struct spear_muxreg rgmii_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_0,
+                .mask = PMX_RGMII_REG0_MASK,
+                .val = 0,
+        }, {
+                .reg = PAD_FUNCTION_EN_1,
+                .mask = PMX_RGMII_REG1_MASK,
+                .val = 0,
+        }, {
+                .reg = PAD_FUNCTION_EN_2,
+                .mask = PMX_RGMII_REG2_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux rgmii_modemux[] = {
+        {
+                .muxregs = rgmii_muxreg,
+                .nmuxregs = ARRAY_SIZE(rgmii_muxreg),
+        },
+};
+
+static struct spear_pingroup rgmii_pingroup = {
+        .name = "rgmii_grp",
+        .pins = rgmii_pins,
+        .npins = ARRAY_SIZE(rgmii_pins),
+        .modemuxs = rgmii_modemux,
+        .nmodemuxs = ARRAY_SIZE(rgmii_modemux),
+};
+
+static const char *const rgmii_grps[] = { "rgmii_grp" };
+static struct spear_function rgmii_function = {
+        .name = "rgmii",
+        .groups = rgmii_grps,
+        .ngroups = ARRAY_SIZE(rgmii_grps),
+};
+
+/* Pad multiplexing for smii_0_1_2 device */
+static const unsigned smii_0_1_2_pins[] = { 24, 25, 26, 27, 28, 29, 30, 31, 32,
+        33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50,
+        51, 52, 53, 54, 55 };
+static struct spear_muxreg smii_0_1_2_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_1,
+                .mask = PMX_SMII_0_1_2_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux smii_0_1_2_modemux[] = {
+        {
+                .muxregs = smii_0_1_2_muxreg,
+                .nmuxregs = ARRAY_SIZE(smii_0_1_2_muxreg),
+        },
+};
+
+static struct spear_pingroup smii_0_1_2_pingroup = {
+        .name = "smii_0_1_2_grp",
+        .pins = smii_0_1_2_pins,
+        .npins = ARRAY_SIZE(smii_0_1_2_pins),
+        .modemuxs = smii_0_1_2_modemux,
+        .nmodemuxs = ARRAY_SIZE(smii_0_1_2_modemux),
+};
+
+static const char *const smii_0_1_2_grps[] = { "smii_0_1_2_grp" };
+static struct spear_function smii_0_1_2_function = {
+        .name = "smii_0_1_2",
+        .groups = smii_0_1_2_grps,
+        .ngroups = ARRAY_SIZE(smii_0_1_2_grps),
+};
+
+/* Pad multiplexing for ras_mii_txclk device */
+static const unsigned ras_mii_txclk_pins[] = { 98, 99 };
+static struct spear_muxreg ras_mii_txclk_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_1,
+                .mask = PMX_NFCE2_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux ras_mii_txclk_modemux[] = {
+        {
+                .muxregs = ras_mii_txclk_muxreg,
+                .nmuxregs = ARRAY_SIZE(ras_mii_txclk_muxreg),
+        },
+};
+
+static struct spear_pingroup ras_mii_txclk_pingroup = {
+        .name = "ras_mii_txclk_grp",
+        .pins = ras_mii_txclk_pins,
+        .npins = ARRAY_SIZE(ras_mii_txclk_pins),
+        .modemuxs = ras_mii_txclk_modemux,
+        .nmodemuxs = ARRAY_SIZE(ras_mii_txclk_modemux),
+};
+
+static const char *const ras_mii_txclk_grps[] = { "ras_mii_txclk_grp" };
+static struct spear_function ras_mii_txclk_function = {
+        .name = "ras_mii_txclk",
+        .groups = ras_mii_txclk_grps,
+        .ngroups = ARRAY_SIZE(ras_mii_txclk_grps),
+};
+
+/* Pad multiplexing for nand 8bit device (cs0 only) */
+static const unsigned nand_8bit_pins[] = { 56, 57, 58, 59, 60, 61, 62, 63, 64,
+        65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82,
+        83, 84, 85, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169,
+        170, 171, 172, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211,
+        212 };
+static struct spear_muxreg nand_8bit_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_0,
+                .mask = PMX_NAND8BIT_0_MASK,
+                .val = PMX_NAND8BIT_0_MASK,
+        }, {
+                .reg = PAD_FUNCTION_EN_1,
+                .mask = PMX_NAND8BIT_1_MASK,
+                .val = PMX_NAND8BIT_1_MASK,
+        },
+};
+
+static struct spear_modemux nand_8bit_modemux[] = {
+        {
+                .muxregs = nand_8bit_muxreg,
+                .nmuxregs = ARRAY_SIZE(nand_8bit_muxreg),
+        },
+};
+
+static struct spear_pingroup nand_8bit_pingroup = {
+        .name = "nand_8bit_grp",
+        .pins = nand_8bit_pins,
+        .npins = ARRAY_SIZE(nand_8bit_pins),
+        .modemuxs = nand_8bit_modemux,
+        .nmodemuxs = ARRAY_SIZE(nand_8bit_modemux),
+};
+
+/* Pad multiplexing for nand 16bit device */
+static const unsigned nand_16bit_pins[] = { 201, 202, 203, 204, 207, 208, 209,
+        210 };
+static struct spear_muxreg nand_16bit_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_1,
+                .mask = PMX_NAND16BIT_1_MASK,
+                .val = PMX_NAND16BIT_1_MASK,
+        },
+};
+
+static struct spear_modemux nand_16bit_modemux[] = {
+        {
+                .muxregs = nand_16bit_muxreg,
+                .nmuxregs = ARRAY_SIZE(nand_16bit_muxreg),
+        },
+};
+
+static struct spear_pingroup nand_16bit_pingroup = {
+        .name = "nand_16bit_grp",
+        .pins = nand_16bit_pins,
+        .npins = ARRAY_SIZE(nand_16bit_pins),
+        .modemuxs = nand_16bit_modemux,
+        .nmodemuxs = ARRAY_SIZE(nand_16bit_modemux),
+};
+
+/* Pad multiplexing for nand 4 chips */
+static const unsigned nand_4_chips_pins[] = { 205, 206, 211, 212 };
+static struct spear_muxreg nand_4_chips_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_1,
+                .mask = PMX_NAND_4CHIPS_MASK,
+                .val = PMX_NAND_4CHIPS_MASK,
+        },
+};
+
+static struct spear_modemux nand_4_chips_modemux[] = {
+        {
+                .muxregs = nand_4_chips_muxreg,
+                .nmuxregs = ARRAY_SIZE(nand_4_chips_muxreg),
+        },
+};
+
+static struct spear_pingroup nand_4_chips_pingroup = {
+        .name = "nand_4_chips_grp",
+        .pins = nand_4_chips_pins,
+        .npins = ARRAY_SIZE(nand_4_chips_pins),
+        .modemuxs = nand_4_chips_modemux,
+        .nmodemuxs = ARRAY_SIZE(nand_4_chips_modemux),
+};
+
+static const char *const nand_grps[] = { "nand_8bit_grp", "nand_16bit_grp",
+        "nand_4_chips_grp" };
+static struct spear_function nand_function = {
+        .name = "nand",
+        .groups = nand_grps,
+        .ngroups = ARRAY_SIZE(nand_grps),
+};
+
+/* Pad multiplexing for keyboard_6x6 device */
+static const unsigned keyboard_6x6_pins[] = { 201, 202, 203, 204, 205, 206, 207,
+        208, 209, 210, 211, 212 };
+static struct spear_muxreg keyboard_6x6_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_1,
+                .mask = PMX_KEYBOARD_6X6_MASK | PMX_NFIO8_15_MASK |
+                        PMX_NFCE1_MASK | PMX_NFCE2_MASK | PMX_NFWPRT1_MASK |
+                        PMX_NFWPRT2_MASK,
+                .val = PMX_KEYBOARD_6X6_MASK,
+        },
+};
+
+static struct spear_modemux keyboard_6x6_modemux[] = {
+        {
+                .muxregs = keyboard_6x6_muxreg,
+                .nmuxregs = ARRAY_SIZE(keyboard_6x6_muxreg),
+        },
+};
+
+static struct spear_pingroup keyboard_6x6_pingroup = {
+        .name = "keyboard_6x6_grp",
+        .pins = keyboard_6x6_pins,
+        .npins = ARRAY_SIZE(keyboard_6x6_pins),
+        .modemuxs = keyboard_6x6_modemux,
+        .nmodemuxs = ARRAY_SIZE(keyboard_6x6_modemux),
+};
+
+/* Pad multiplexing for keyboard_rowcol6_8 device */
+static const unsigned keyboard_rowcol6_8_pins[] = { 24, 25, 26, 27, 28, 29 };
+static struct spear_muxreg keyboard_rowcol6_8_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_1,
+                .mask = PMX_KBD_ROWCOL68_MASK,
+                .val = PMX_KBD_ROWCOL68_MASK,
+        },
+};
+
+static struct spear_modemux keyboard_rowcol6_8_modemux[] = {
+        {
+                .muxregs = keyboard_rowcol6_8_muxreg,
+                .nmuxregs = ARRAY_SIZE(keyboard_rowcol6_8_muxreg),
+        },
+};
+
+static struct spear_pingroup keyboard_rowcol6_8_pingroup = {
+        .name = "keyboard_rowcol6_8_grp",
+        .pins = keyboard_rowcol6_8_pins,
+        .npins = ARRAY_SIZE(keyboard_rowcol6_8_pins),
+        .modemuxs = keyboard_rowcol6_8_modemux,
+        .nmodemuxs = ARRAY_SIZE(keyboard_rowcol6_8_modemux),
+};
+
+static const char *const keyboard_grps[] = { "keyboard_6x6_grp",
+        "keyboard_rowcol6_8_grp" };
+static struct spear_function keyboard_function = {
+        .name = "keyboard",
+        .groups = keyboard_grps,
+        .ngroups = ARRAY_SIZE(keyboard_grps),
+};
+
+/* Pad multiplexing for uart0 device */
+static const unsigned uart0_pins[] = { 100, 101 };
+static struct spear_muxreg uart0_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_0,
+                .mask = PMX_UART0_MASK,
+                .val = PMX_UART0_MASK,
+        },
+};
+
+static struct spear_modemux uart0_modemux[] = {
+        {
+                .muxregs = uart0_muxreg,
+                .nmuxregs = ARRAY_SIZE(uart0_muxreg),
+        },
+};
+
+static struct spear_pingroup uart0_pingroup = {
+        .name = "uart0_grp",
+        .pins = uart0_pins,
+        .npins = ARRAY_SIZE(uart0_pins),
+        .modemuxs = uart0_modemux,
+        .nmodemuxs = ARRAY_SIZE(uart0_modemux),
+};
+
+/* Pad multiplexing for uart0_modem device */
+static const unsigned uart0_modem_pins[] = { 12, 13, 14, 15, 16, 17 };
+static struct spear_muxreg uart0_modem_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_1,
+                .mask = PMX_UART0_MODEM_MASK,
+                .val = PMX_UART0_MODEM_MASK,
+        },
+};
+
+static struct spear_modemux uart0_modem_modemux[] = {
+        {
+                .muxregs = uart0_modem_muxreg,
+                .nmuxregs = ARRAY_SIZE(uart0_modem_muxreg),
+        },
+};
+
+static struct spear_pingroup uart0_modem_pingroup = {
+        .name = "uart0_modem_grp",
+        .pins = uart0_modem_pins,
+        .npins = ARRAY_SIZE(uart0_modem_pins),
+        .modemuxs = uart0_modem_modemux,
+        .nmodemuxs = ARRAY_SIZE(uart0_modem_modemux),
+};
+
+static const char *const uart0_grps[] = { "uart0_grp", "uart0_modem_grp" };
+static struct spear_function uart0_function = {
+        .name = "uart0",
+        .groups = uart0_grps,
+        .ngroups = ARRAY_SIZE(uart0_grps),
+};
+
+/* Pad multiplexing for gpt0_tmr0 device */
+static const unsigned gpt0_tmr0_pins[] = { 10, 11 };
+static struct spear_muxreg gpt0_tmr0_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_1,
+                .mask = PMX_GPT0_TMR0_MASK,
+                .val = PMX_GPT0_TMR0_MASK,
+        },
+};
+
+static struct spear_modemux gpt0_tmr0_modemux[] = {
+        {
+                .muxregs = gpt0_tmr0_muxreg,
+                .nmuxregs = ARRAY_SIZE(gpt0_tmr0_muxreg),
+        },
+};
+
+static struct spear_pingroup gpt0_tmr0_pingroup = {
+        .name = "gpt0_tmr0_grp",
+        .pins = gpt0_tmr0_pins,
+        .npins = ARRAY_SIZE(gpt0_tmr0_pins),
+        .modemuxs = gpt0_tmr0_modemux,
+        .nmodemuxs = ARRAY_SIZE(gpt0_tmr0_modemux),
+};
+
+/* Pad multiplexing for gpt0_tmr1 device */
+static const unsigned gpt0_tmr1_pins[] = { 8, 9 };
+static struct spear_muxreg gpt0_tmr1_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_1,
+                .mask = PMX_GPT0_TMR1_MASK,
+                .val = PMX_GPT0_TMR1_MASK,
+        },
+};
+
+static struct spear_modemux gpt0_tmr1_modemux[] = {
+        {
+                .muxregs = gpt0_tmr1_muxreg,
+                .nmuxregs = ARRAY_SIZE(gpt0_tmr1_muxreg),
+        },
+};
+
+static struct spear_pingroup gpt0_tmr1_pingroup = {
+        .name = "gpt0_tmr1_grp",
+        .pins = gpt0_tmr1_pins,
+        .npins = ARRAY_SIZE(gpt0_tmr1_pins),
+        .modemuxs = gpt0_tmr1_modemux,
+        .nmodemuxs = ARRAY_SIZE(gpt0_tmr1_modemux),
+};
+
+static const char *const gpt0_grps[] = { "gpt0_tmr0_grp", "gpt0_tmr1_grp" };
+static struct spear_function gpt0_function = {
+        .name = "gpt0",
+        .groups = gpt0_grps,
+        .ngroups = ARRAY_SIZE(gpt0_grps),
+};
+
+/* Pad multiplexing for gpt1_tmr0 device */
+static const unsigned gpt1_tmr0_pins[] = { 6, 7 };
+static struct spear_muxreg gpt1_tmr0_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_1,
+                .mask = PMX_GPT1_TMR0_MASK,
+                .val = PMX_GPT1_TMR0_MASK,
+        },
+};
+
+static struct spear_modemux gpt1_tmr0_modemux[] = {
+        {
+                .muxregs = gpt1_tmr0_muxreg,
+                .nmuxregs = ARRAY_SIZE(gpt1_tmr0_muxreg),
+        },
+};
+
+static struct spear_pingroup gpt1_tmr0_pingroup = {
+        .name = "gpt1_tmr0_grp",
+        .pins = gpt1_tmr0_pins,
+        .npins = ARRAY_SIZE(gpt1_tmr0_pins),
+        .modemuxs = gpt1_tmr0_modemux,
+        .nmodemuxs = ARRAY_SIZE(gpt1_tmr0_modemux),
+};
+
+/* Pad multiplexing for gpt1_tmr1 device */
+static const unsigned gpt1_tmr1_pins[] = { 4, 5 };
+static struct spear_muxreg gpt1_tmr1_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_1,
+                .mask = PMX_GPT1_TMR1_MASK,
+                .val = PMX_GPT1_TMR1_MASK,
+        },
+};
+
+static struct spear_modemux gpt1_tmr1_modemux[] = {
+        {
+                .muxregs = gpt1_tmr1_muxreg,
+                .nmuxregs = ARRAY_SIZE(gpt1_tmr1_muxreg),
+        },
+};
+
+static struct spear_pingroup gpt1_tmr1_pingroup = {
+        .name = "gpt1_tmr1_grp",
+        .pins = gpt1_tmr1_pins,
+        .npins = ARRAY_SIZE(gpt1_tmr1_pins),
+        .modemuxs = gpt1_tmr1_modemux,
+        .nmodemuxs = ARRAY_SIZE(gpt1_tmr1_modemux),
+};
+
+static const char *const gpt1_grps[] = { "gpt1_tmr1_grp", "gpt1_tmr0_grp" };
+static struct spear_function gpt1_function = {
+        .name = "gpt1",
+        .groups = gpt1_grps,
+        .ngroups = ARRAY_SIZE(gpt1_grps),
+};
+
+/* Pad multiplexing for mcif device */
+static const unsigned mcif_pins[] = { 86, 87, 88, 89, 90, 91, 92, 93, 213, 214,
+        215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228,
+        229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242,
+        243, 244, 245 };
+#define MCIF_MUXREG                                             \
+        {                                                       \
+                .reg = PAD_FUNCTION_EN_0,                       \
+                .mask = PMX_MCI_DATA8_15_MASK,                  \
+                .val = PMX_MCI_DATA8_15_MASK,                   \
+        }, {                                                    \
+                .reg = PAD_FUNCTION_EN_1,                       \
+                .mask = PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK | \
+                        PMX_NFWPRT2_MASK,                       \
+                .val = PMX_MCIFALL_1_MASK,                      \
+        }, {                                                    \
+                .reg = PAD_FUNCTION_EN_2,                       \
+                .mask = PMX_MCIFALL_2_MASK,                     \
+                .val = PMX_MCIFALL_2_MASK,                      \
+        }
+
+/* sdhci device */
+static struct spear_muxreg sdhci_muxreg[] = {
+        MCIF_MUXREG,
+        {
+                .reg = PERIP_CFG,
+                .mask = MCIF_SEL_MASK,
+                .val = MCIF_SEL_SD,
+        },
+};
+
+static struct spear_modemux sdhci_modemux[] = {
+        {
+                .muxregs = sdhci_muxreg,
+                .nmuxregs = ARRAY_SIZE(sdhci_muxreg),
+        },
+};
+
+static struct spear_pingroup sdhci_pingroup = {
+        .name = "sdhci_grp",
+        .pins = mcif_pins,
+        .npins = ARRAY_SIZE(mcif_pins),
+        .modemuxs = sdhci_modemux,
+        .nmodemuxs = ARRAY_SIZE(sdhci_modemux),
+};
+
+static const char *const sdhci_grps[] = { "sdhci_grp" };
+static struct spear_function sdhci_function = {
+        .name = "sdhci",
+        .groups = sdhci_grps,
+        .ngroups = ARRAY_SIZE(sdhci_grps),
+};
+
+/* cf device */
+static struct spear_muxreg cf_muxreg[] = {
+        MCIF_MUXREG,
+        {
+                .reg = PERIP_CFG,
+                .mask = MCIF_SEL_MASK,
+                .val = MCIF_SEL_CF,
+        },
+};
+
+static struct spear_modemux cf_modemux[] = {
+        {
+                .muxregs = cf_muxreg,
+                .nmuxregs = ARRAY_SIZE(cf_muxreg),
+        },
+};
+
+static struct spear_pingroup cf_pingroup = {
+        .name = "cf_grp",
+        .pins = mcif_pins,
+        .npins = ARRAY_SIZE(mcif_pins),
+        .modemuxs = cf_modemux,
+        .nmodemuxs = ARRAY_SIZE(cf_modemux),
+};
+
+static const char *const cf_grps[] = { "cf_grp" };
+static struct spear_function cf_function = {
+        .name = "cf",
+        .groups = cf_grps,
+        .ngroups = ARRAY_SIZE(cf_grps),
+};
+
+/* xd device */
+static struct spear_muxreg xd_muxreg[] = {
+        MCIF_MUXREG,
+        {
+                .reg = PERIP_CFG,
+                .mask = MCIF_SEL_MASK,
+                .val = MCIF_SEL_XD,
+        },
+};
+
+static struct spear_modemux xd_modemux[] = {
+        {
+                .muxregs = xd_muxreg,
+                .nmuxregs = ARRAY_SIZE(xd_muxreg),
+        },
+};
+
+static struct spear_pingroup xd_pingroup = {
+        .name = "xd_grp",
+        .pins = mcif_pins,
+        .npins = ARRAY_SIZE(mcif_pins),
+        .modemuxs = xd_modemux,
+        .nmodemuxs = ARRAY_SIZE(xd_modemux),
+};
+
+static const char *const xd_grps[] = { "xd_grp" };
+static struct spear_function xd_function = {
+        .name = "xd",
+        .groups = xd_grps,
+        .ngroups = ARRAY_SIZE(xd_grps),
+};
+
+/* Pad multiplexing for touch_xy device */
+static const unsigned touch_xy_pins[] = { 97 };
+static struct spear_muxreg touch_xy_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_2,
+                .mask = PMX_TOUCH_XY_MASK,
+                .val = PMX_TOUCH_XY_MASK,
+        },
+};
+
+static struct spear_modemux touch_xy_modemux[] = {
+        {
+                .muxregs = touch_xy_muxreg,
+                .nmuxregs = ARRAY_SIZE(touch_xy_muxreg),
+        },
+};
+
+static struct spear_pingroup touch_xy_pingroup = {
+        .name = "touch_xy_grp",
+        .pins = touch_xy_pins,
+        .npins = ARRAY_SIZE(touch_xy_pins),
+        .modemuxs = touch_xy_modemux,
+        .nmodemuxs = ARRAY_SIZE(touch_xy_modemux),
+};
+
+static const char *const touch_xy_grps[] = { "touch_xy_grp" };
+static struct spear_function touch_xy_function = {
+        .name = "touchscreen",
+        .groups = touch_xy_grps,
+        .ngroups = ARRAY_SIZE(touch_xy_grps),
+};
+
+/* Pad multiplexing for uart1 device */
+/* Muxed with I2C */
+static const unsigned uart1_dis_i2c_pins[] = { 102, 103 };
+static struct spear_muxreg uart1_dis_i2c_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_0,
+                .mask = PMX_I2C0_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux uart1_dis_i2c_modemux[] = {
+        {
+                .muxregs = uart1_dis_i2c_muxreg,
+                .nmuxregs = ARRAY_SIZE(uart1_dis_i2c_muxreg),
+        },
+};
+
+static struct spear_pingroup uart_1_dis_i2c_pingroup = {
+        .name = "uart1_disable_i2c_grp",
+        .pins = uart1_dis_i2c_pins,
+        .npins = ARRAY_SIZE(uart1_dis_i2c_pins),
+        .modemuxs = uart1_dis_i2c_modemux,
+        .nmodemuxs = ARRAY_SIZE(uart1_dis_i2c_modemux),
+};
+
+/* Muxed with SD/MMC */
+static const unsigned uart1_dis_sd_pins[] = { 214, 215 };
+static struct spear_muxreg uart1_dis_sd_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_1,
+                .mask = PMX_MCIDATA1_MASK |
+                        PMX_MCIDATA2_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux uart1_dis_sd_modemux[] = {
+        {
+                .muxregs = uart1_dis_sd_muxreg,
+                .nmuxregs = ARRAY_SIZE(uart1_dis_sd_muxreg),
+        },
+};
+
+static struct spear_pingroup uart_1_dis_sd_pingroup = {
+        .name = "uart1_disable_sd_grp",
+        .pins = uart1_dis_sd_pins,
+        .npins = ARRAY_SIZE(uart1_dis_sd_pins),
+        .modemuxs = uart1_dis_sd_modemux,
+        .nmodemuxs = ARRAY_SIZE(uart1_dis_sd_modemux),
+};
+
+static const char *const uart1_grps[] = { "uart1_disable_i2c_grp",
+        "uart1_disable_sd_grp" };
+static struct spear_function uart1_function = {
+        .name = "uart1",
+        .groups = uart1_grps,
+        .ngroups = ARRAY_SIZE(uart1_grps),
+};
+
+/* Pad multiplexing for uart2_3 device */
+static const unsigned uart2_3_pins[] = { 104, 105, 106, 107 };
+static struct spear_muxreg uart2_3_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_0,
+                .mask = PMX_I2S0_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux uart2_3_modemux[] = {
+        {
+                .muxregs = uart2_3_muxreg,
+                .nmuxregs = ARRAY_SIZE(uart2_3_muxreg),
+        },
+};
+
+static struct spear_pingroup uart_2_3_pingroup = {
+        .name = "uart2_3_grp",
+        .pins = uart2_3_pins,
+        .npins = ARRAY_SIZE(uart2_3_pins),
+        .modemuxs = uart2_3_modemux,
+        .nmodemuxs = ARRAY_SIZE(uart2_3_modemux),
+};
+
+static const char *const uart2_3_grps[] = { "uart2_3_grp" };
+static struct spear_function uart2_3_function = {
+        .name = "uart2_3",
+        .groups = uart2_3_grps,
+        .ngroups = ARRAY_SIZE(uart2_3_grps),
+};
+
+/* Pad multiplexing for uart4 device */
+static const unsigned uart4_pins[] = { 108, 113 };
+static struct spear_muxreg uart4_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_0,
+                .mask = PMX_I2S0_MASK | PMX_CLCD1_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux uart4_modemux[] = {
+        {
+                .muxregs = uart4_muxreg,
+                .nmuxregs = ARRAY_SIZE(uart4_muxreg),
+        },
+};
+
+static struct spear_pingroup uart_4_pingroup = {
+        .name = "uart4_grp",
+        .pins = uart4_pins,
+        .npins = ARRAY_SIZE(uart4_pins),
+        .modemuxs = uart4_modemux,
+        .nmodemuxs = ARRAY_SIZE(uart4_modemux),
+};
+
+static const char *const uart4_grps[] = { "uart4_grp" };
+static struct spear_function uart4_function = {
+        .name = "uart4",
+        .groups = uart4_grps,
+        .ngroups = ARRAY_SIZE(uart4_grps),
+};
+
+/* Pad multiplexing for uart5 device */
+static const unsigned uart5_pins[] = { 114, 115 };
+static struct spear_muxreg uart5_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_0,
+                .mask = PMX_CLCD1_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux uart5_modemux[] = {
+        {
+                .muxregs = uart5_muxreg,
+                .nmuxregs = ARRAY_SIZE(uart5_muxreg),
+        },
+};
+
+static struct spear_pingroup uart_5_pingroup = {
+        .name = "uart5_grp",
+        .pins = uart5_pins,
+        .npins = ARRAY_SIZE(uart5_pins),
+        .modemuxs = uart5_modemux,
+        .nmodemuxs = ARRAY_SIZE(uart5_modemux),
+};
+
+static const char *const uart5_grps[] = { "uart5_grp" };
+static struct spear_function uart5_function = {
+        .name = "uart5",
+        .groups = uart5_grps,
+        .ngroups = ARRAY_SIZE(uart5_grps),
+};
+
+/* Pad multiplexing for rs485_0_1_tdm_0_1 device */
+static const unsigned rs485_0_1_tdm_0_1_pins[] = { 116, 117, 118, 119, 120, 121,
+        122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135,
+        136, 137 };
+static struct spear_muxreg rs485_0_1_tdm_0_1_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_0,
+                .mask = PMX_CLCD1_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux rs485_0_1_tdm_0_1_modemux[] = {
+        {
+                .muxregs = rs485_0_1_tdm_0_1_muxreg,
+                .nmuxregs = ARRAY_SIZE(rs485_0_1_tdm_0_1_muxreg),
+        },
+};
+
+static struct spear_pingroup rs485_0_1_tdm_0_1_pingroup = {
+        .name = "rs485_0_1_tdm_0_1_grp",
+        .pins = rs485_0_1_tdm_0_1_pins,
+        .npins = ARRAY_SIZE(rs485_0_1_tdm_0_1_pins),
+        .modemuxs = rs485_0_1_tdm_0_1_modemux,
+        .nmodemuxs = ARRAY_SIZE(rs485_0_1_tdm_0_1_modemux),
+};
+
+static const char *const rs485_0_1_tdm_0_1_grps[] = { "rs485_0_1_tdm_0_1_grp" };
+static struct spear_function rs485_0_1_tdm_0_1_function = {
+        .name = "rs485_0_1_tdm_0_1",
+        .groups = rs485_0_1_tdm_0_1_grps,
+        .ngroups = ARRAY_SIZE(rs485_0_1_tdm_0_1_grps),
+};
+
+/* Pad multiplexing for i2c_1_2 device */
+static const unsigned i2c_1_2_pins[] = { 138, 139, 140, 141 };
+static struct spear_muxreg i2c_1_2_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_0,
+                .mask = PMX_CLCD1_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux i2c_1_2_modemux[] = {
+        {
+                .muxregs = i2c_1_2_muxreg,
+                .nmuxregs = ARRAY_SIZE(i2c_1_2_muxreg),
+        },
+};
+
+static struct spear_pingroup i2c_1_2_pingroup = {
+        .name = "i2c_1_2_grp",
+        .pins = i2c_1_2_pins,
+        .npins = ARRAY_SIZE(i2c_1_2_pins),
+        .modemuxs = i2c_1_2_modemux,
+        .nmodemuxs = ARRAY_SIZE(i2c_1_2_modemux),
+};
+
+static const char *const i2c_1_2_grps[] = { "i2c_1_2_grp" };
+static struct spear_function i2c_1_2_function = {
+        .name = "i2c_1_2",
+        .groups = i2c_1_2_grps,
+        .ngroups = ARRAY_SIZE(i2c_1_2_grps),
+};
+
+/* Pad multiplexing for i2c3_dis_smi_clcd device */
+/* Muxed with SMI & CLCD */
+static const unsigned i2c3_dis_smi_clcd_pins[] = { 142, 153 };
+static struct spear_muxreg i2c3_dis_smi_clcd_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_0,
+                .mask = PMX_CLCD1_MASK | PMX_SMI_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux i2c3_dis_smi_clcd_modemux[] = {
+        {
+                .muxregs = i2c3_dis_smi_clcd_muxreg,
+                .nmuxregs = ARRAY_SIZE(i2c3_dis_smi_clcd_muxreg),
+        },
+};
+
+static struct spear_pingroup i2c3_dis_smi_clcd_pingroup = {
+        .name = "i2c3_dis_smi_clcd_grp",
+        .pins = i2c3_dis_smi_clcd_pins,
+        .npins = ARRAY_SIZE(i2c3_dis_smi_clcd_pins),
+        .modemuxs = i2c3_dis_smi_clcd_modemux,
+        .nmodemuxs = ARRAY_SIZE(i2c3_dis_smi_clcd_modemux),
+};
+
+/* Pad multiplexing for i2c3_dis_sd_i2s0 device */
+/* Muxed with SD/MMC & I2S1 */
+static const unsigned i2c3_dis_sd_i2s0_pins[] = { 0, 216 };
+static struct spear_muxreg i2c3_dis_sd_i2s0_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_1,
+                .mask = PMX_I2S1_MASK | PMX_MCIDATA3_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux i2c3_dis_sd_i2s0_modemux[] = {
+        {
+                .muxregs = i2c3_dis_sd_i2s0_muxreg,
+                .nmuxregs = ARRAY_SIZE(i2c3_dis_sd_i2s0_muxreg),
+        },
+};
+
+static struct spear_pingroup i2c3_dis_sd_i2s0_pingroup = {
+        .name = "i2c3_dis_sd_i2s0_grp",
+        .pins = i2c3_dis_sd_i2s0_pins,
+        .npins = ARRAY_SIZE(i2c3_dis_sd_i2s0_pins),
+        .modemuxs = i2c3_dis_sd_i2s0_modemux,
+        .nmodemuxs = ARRAY_SIZE(i2c3_dis_sd_i2s0_modemux),
+};
+
+static const char *const i2c3_grps[] = { "i2c3_dis_smi_clcd_grp",
+        "i2c3_dis_sd_i2s0_grp" };
+static struct spear_function i2c3_unction = {
+        .name = "i2c3_i2s1",
+        .groups = i2c3_grps,
+        .ngroups = ARRAY_SIZE(i2c3_grps),
+};
+
+/* Pad multiplexing for i2c_4_5_dis_smi device */
+/* Muxed with SMI */
+static const unsigned i2c_4_5_dis_smi_pins[] = { 154, 155, 156, 157 };
+static struct spear_muxreg i2c_4_5_dis_smi_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_0,
+                .mask = PMX_SMI_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux i2c_4_5_dis_smi_modemux[] = {
+        {
+                .muxregs = i2c_4_5_dis_smi_muxreg,
+                .nmuxregs = ARRAY_SIZE(i2c_4_5_dis_smi_muxreg),
+        },
+};
+
+static struct spear_pingroup i2c_4_5_dis_smi_pingroup = {
+        .name = "i2c_4_5_dis_smi_grp",
+        .pins = i2c_4_5_dis_smi_pins,
+        .npins = ARRAY_SIZE(i2c_4_5_dis_smi_pins),
+        .modemuxs = i2c_4_5_dis_smi_modemux,
+        .nmodemuxs = ARRAY_SIZE(i2c_4_5_dis_smi_modemux),
+};
+
+/* Pad multiplexing for i2c4_dis_sd device */
+/* Muxed with SD/MMC */
+static const unsigned i2c4_dis_sd_pins[] = { 217, 218 };
+static struct spear_muxreg i2c4_dis_sd_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_1,
+                .mask = PMX_MCIDATA4_MASK,
+                .val = 0,
+        }, {
+                .reg = PAD_FUNCTION_EN_2,
+                .mask = PMX_MCIDATA5_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux i2c4_dis_sd_modemux[] = {
+        {
+                .muxregs = i2c4_dis_sd_muxreg,
+                .nmuxregs = ARRAY_SIZE(i2c4_dis_sd_muxreg),
+        },
+};
+
+static struct spear_pingroup i2c4_dis_sd_pingroup = {
+        .name = "i2c4_dis_sd_grp",
+        .pins = i2c4_dis_sd_pins,
+        .npins = ARRAY_SIZE(i2c4_dis_sd_pins),
+        .modemuxs = i2c4_dis_sd_modemux,
+        .nmodemuxs = ARRAY_SIZE(i2c4_dis_sd_modemux),
+};
+
+/* Pad multiplexing for i2c5_dis_sd device */
+/* Muxed with SD/MMC */
+static const unsigned i2c5_dis_sd_pins[] = { 219, 220 };
+static struct spear_muxreg i2c5_dis_sd_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_2,
+                .mask = PMX_MCIDATA6_MASK |
+                        PMX_MCIDATA7_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux i2c5_dis_sd_modemux[] = {
+        {
+                .muxregs = i2c5_dis_sd_muxreg,
+                .nmuxregs = ARRAY_SIZE(i2c5_dis_sd_muxreg),
+        },
+};
+
+static struct spear_pingroup i2c5_dis_sd_pingroup = {
+        .name = "i2c5_dis_sd_grp",
+        .pins = i2c5_dis_sd_pins,
+        .npins = ARRAY_SIZE(i2c5_dis_sd_pins),
+        .modemuxs = i2c5_dis_sd_modemux,
+        .nmodemuxs = ARRAY_SIZE(i2c5_dis_sd_modemux),
+};
+
+static const char *const i2c_4_5_grps[] = { "i2c5_dis_sd_grp",
+        "i2c4_dis_sd_grp", "i2c_4_5_dis_smi_grp" };
+static struct spear_function i2c_4_5_function = {
+        .name = "i2c_4_5",
+        .groups = i2c_4_5_grps,
+        .ngroups = ARRAY_SIZE(i2c_4_5_grps),
+};
+
+/* Pad multiplexing for i2c_6_7_dis_kbd device */
+/* Muxed with KBD */
+static const unsigned i2c_6_7_dis_kbd_pins[] = { 207, 208, 209, 210 };
+static struct spear_muxreg i2c_6_7_dis_kbd_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_1,
+                .mask = PMX_KBD_ROWCOL25_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux i2c_6_7_dis_kbd_modemux[] = {
+        {
+                .muxregs = i2c_6_7_dis_kbd_muxreg,
+                .nmuxregs = ARRAY_SIZE(i2c_6_7_dis_kbd_muxreg),
+        },
+};
+
+static struct spear_pingroup i2c_6_7_dis_kbd_pingroup = {
+        .name = "i2c_6_7_dis_kbd_grp",
+        .pins = i2c_6_7_dis_kbd_pins,
+        .npins = ARRAY_SIZE(i2c_6_7_dis_kbd_pins),
+        .modemuxs = i2c_6_7_dis_kbd_modemux,
+        .nmodemuxs = ARRAY_SIZE(i2c_6_7_dis_kbd_modemux),
+};
+
+/* Pad multiplexing for i2c6_dis_sd device */
+/* Muxed with SD/MMC */
+static const unsigned i2c6_dis_sd_pins[] = { 236, 237 };
+static struct spear_muxreg i2c6_dis_sd_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_2,
+                .mask = PMX_MCIIORDRE_MASK |
+                        PMX_MCIIOWRWE_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux i2c6_dis_sd_modemux[] = {
+        {
+                .muxregs = i2c6_dis_sd_muxreg,
+                .nmuxregs = ARRAY_SIZE(i2c6_dis_sd_muxreg),
+        },
+};
+
+static struct spear_pingroup i2c6_dis_sd_pingroup = {
+        .name = "i2c6_dis_sd_grp",
+        .pins = i2c6_dis_sd_pins,
+        .npins = ARRAY_SIZE(i2c6_dis_sd_pins),
+        .modemuxs = i2c6_dis_sd_modemux,
+        .nmodemuxs = ARRAY_SIZE(i2c6_dis_sd_modemux),
+};
+
+/* Pad multiplexing for i2c7_dis_sd device */
+static const unsigned i2c7_dis_sd_pins[] = { 238, 239 };
+static struct spear_muxreg i2c7_dis_sd_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_2,
+                .mask = PMX_MCIRESETCF_MASK |
+                        PMX_MCICS0CE_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux i2c7_dis_sd_modemux[] = {
+        {
+                .muxregs = i2c7_dis_sd_muxreg,
+                .nmuxregs = ARRAY_SIZE(i2c7_dis_sd_muxreg),
+        },
+};
+
+static struct spear_pingroup i2c7_dis_sd_pingroup = {
+        .name = "i2c7_dis_sd_grp",
+        .pins = i2c7_dis_sd_pins,
+        .npins = ARRAY_SIZE(i2c7_dis_sd_pins),
+        .modemuxs = i2c7_dis_sd_modemux,
+        .nmodemuxs = ARRAY_SIZE(i2c7_dis_sd_modemux),
+};
+
+static const char *const i2c_6_7_grps[] = { "i2c6_dis_sd_grp",
+        "i2c7_dis_sd_grp", "i2c_6_7_dis_kbd_grp" };
+static struct spear_function i2c_6_7_function = {
+        .name = "i2c_6_7",
+        .groups = i2c_6_7_grps,
+        .ngroups = ARRAY_SIZE(i2c_6_7_grps),
+};
+
+/* Pad multiplexing for can0_dis_nor device */
+/* Muxed with NOR */
+static const unsigned can0_dis_nor_pins[] = { 56, 57 };
+static struct spear_muxreg can0_dis_nor_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_0,
+                .mask = PMX_NFRSTPWDWN2_MASK,
+                .val = 0,
+        }, {
+                .reg = PAD_FUNCTION_EN_1,
+                .mask = PMX_NFRSTPWDWN3_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux can0_dis_nor_modemux[] = {
+        {
+                .muxregs = can0_dis_nor_muxreg,
+                .nmuxregs = ARRAY_SIZE(can0_dis_nor_muxreg),
+        },
+};
+
+static struct spear_pingroup can0_dis_nor_pingroup = {
+        .name = "can0_dis_nor_grp",
+        .pins = can0_dis_nor_pins,
+        .npins = ARRAY_SIZE(can0_dis_nor_pins),
+        .modemuxs = can0_dis_nor_modemux,
+        .nmodemuxs = ARRAY_SIZE(can0_dis_nor_modemux),
+};
+
+/* Pad multiplexing for can0_dis_sd device */
+/* Muxed with SD/MMC */
+static const unsigned can0_dis_sd_pins[] = { 240, 241 };
+static struct spear_muxreg can0_dis_sd_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_2,
+                .mask = PMX_MCICFINTR_MASK | PMX_MCIIORDY_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux can0_dis_sd_modemux[] = {
+        {
+                .muxregs = can0_dis_sd_muxreg,
+                .nmuxregs = ARRAY_SIZE(can0_dis_sd_muxreg),
+        },
+};
+
+static struct spear_pingroup can0_dis_sd_pingroup = {
+        .name = "can0_dis_sd_grp",
+        .pins = can0_dis_sd_pins,
+        .npins = ARRAY_SIZE(can0_dis_sd_pins),
+        .modemuxs = can0_dis_sd_modemux,
+        .nmodemuxs = ARRAY_SIZE(can0_dis_sd_modemux),
+};
+
+static const char *const can0_grps[] = { "can0_dis_nor_grp", "can0_dis_sd_grp"
+};
+static struct spear_function can0_function = {
+        .name = "can0",
+        .groups = can0_grps,
+        .ngroups = ARRAY_SIZE(can0_grps),
+};
+
+/* Pad multiplexing for can1_dis_sd device */
+/* Muxed with SD/MMC */
+static const unsigned can1_dis_sd_pins[] = { 242, 243 };
+static struct spear_muxreg can1_dis_sd_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_2,
+                .mask = PMX_MCICS1_MASK | PMX_MCIDMAACK_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux can1_dis_sd_modemux[] = {
+        {
+                .muxregs = can1_dis_sd_muxreg,
+                .nmuxregs = ARRAY_SIZE(can1_dis_sd_muxreg),
+        },
+};
+
+static struct spear_pingroup can1_dis_sd_pingroup = {
+        .name = "can1_dis_sd_grp",
+        .pins = can1_dis_sd_pins,
+        .npins = ARRAY_SIZE(can1_dis_sd_pins),
+        .modemuxs = can1_dis_sd_modemux,
+        .nmodemuxs = ARRAY_SIZE(can1_dis_sd_modemux),
+};
+
+/* Pad multiplexing for can1_dis_kbd device */
+/* Muxed with KBD */
+static const unsigned can1_dis_kbd_pins[] = { 201, 202 };
+static struct spear_muxreg can1_dis_kbd_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_1,
+                .mask = PMX_KBD_ROWCOL25_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux can1_dis_kbd_modemux[] = {
+        {
+                .muxregs = can1_dis_kbd_muxreg,
+                .nmuxregs = ARRAY_SIZE(can1_dis_kbd_muxreg),
+        },
+};
+
+static struct spear_pingroup can1_dis_kbd_pingroup = {
+        .name = "can1_dis_kbd_grp",
+        .pins = can1_dis_kbd_pins,
+        .npins = ARRAY_SIZE(can1_dis_kbd_pins),
+        .modemuxs = can1_dis_kbd_modemux,
+        .nmodemuxs = ARRAY_SIZE(can1_dis_kbd_modemux),
+};
+
+static const char *const can1_grps[] = { "can1_dis_sd_grp", "can1_dis_kbd_grp"
+};
+static struct spear_function can1_function = {
+        .name = "can1",
+        .groups = can1_grps,
+        .ngroups = ARRAY_SIZE(can1_grps),
+};
+
+/* Pad multiplexing for pci device */
+static const unsigned pci_sata_pins[] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 18,
+        19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36,
+        37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54,
+        55, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99 };
+#define PCI_SATA_MUXREG                         \
+        {                                       \
+                .reg = PAD_FUNCTION_EN_0,       \
+                .mask = PMX_MCI_DATA8_15_MASK,  \
+                .val = 0,                       \
+        }, {                                    \
+                .reg = PAD_FUNCTION_EN_1,       \
+                .mask = PMX_PCI_REG1_MASK,      \
+                .val = 0,                       \
+        }, {                                    \
+                .reg = PAD_FUNCTION_EN_2,       \
+                .mask = PMX_PCI_REG2_MASK,      \
+                .val = 0,                       \
+        }
+
+/* pad multiplexing for pcie0 device */
+static struct spear_muxreg pcie0_muxreg[] = {
+        PCI_SATA_MUXREG,
+        {
+                .reg = PCIE_SATA_CFG,
+                .mask = PCIE_CFG_VAL(0),
+                .val = PCIE_CFG_VAL(0),
+        },
+};
+
+static struct spear_modemux pcie0_modemux[] = {
+        {
+                .muxregs = pcie0_muxreg,
+                .nmuxregs = ARRAY_SIZE(pcie0_muxreg),
+        },
+};
+
+static struct spear_pingroup pcie0_pingroup = {
+        .name = "pcie0_grp",
+        .pins = pci_sata_pins,
+        .npins = ARRAY_SIZE(pci_sata_pins),
+        .modemuxs = pcie0_modemux,
+        .nmodemuxs = ARRAY_SIZE(pcie0_modemux),
+};
+
+/* pad multiplexing for pcie1 device */
+static struct spear_muxreg pcie1_muxreg[] = {
+        PCI_SATA_MUXREG,
+        {
+                .reg = PCIE_SATA_CFG,
+                .mask = PCIE_CFG_VAL(1),
+                .val = PCIE_CFG_VAL(1),
+        },
+};
+
+static struct spear_modemux pcie1_modemux[] = {
+        {
+                .muxregs = pcie1_muxreg,
+                .nmuxregs = ARRAY_SIZE(pcie1_muxreg),
+        },
+};
+
+static struct spear_pingroup pcie1_pingroup = {
+        .name = "pcie1_grp",
+        .pins = pci_sata_pins,
+        .npins = ARRAY_SIZE(pci_sata_pins),
+        .modemuxs = pcie1_modemux,
+        .nmodemuxs = ARRAY_SIZE(pcie1_modemux),
+};
+
+/* pad multiplexing for pcie2 device */
+static struct spear_muxreg pcie2_muxreg[] = {
+        PCI_SATA_MUXREG,
+        {
+                .reg = PCIE_SATA_CFG,
+                .mask = PCIE_CFG_VAL(2),
+                .val = PCIE_CFG_VAL(2),
+        },
+};
+
+static struct spear_modemux pcie2_modemux[] = {
+        {
+                .muxregs = pcie2_muxreg,
+                .nmuxregs = ARRAY_SIZE(pcie2_muxreg),
+        },
+};
+
+static struct spear_pingroup pcie2_pingroup = {
+        .name = "pcie2_grp",
+        .pins = pci_sata_pins,
+        .npins = ARRAY_SIZE(pci_sata_pins),
+        .modemuxs = pcie2_modemux,
+        .nmodemuxs = ARRAY_SIZE(pcie2_modemux),
+};
+
+static const char *const pci_grps[] = { "pcie0_grp", "pcie1_grp", "pcie2_grp" };
+static struct spear_function pci_function = {
+        .name = "pci",
+        .groups = pci_grps,
+        .ngroups = ARRAY_SIZE(pci_grps),
+};
+
+/* pad multiplexing for sata0 device */
+static struct spear_muxreg sata0_muxreg[] = {
+        PCI_SATA_MUXREG,
+        {
+                .reg = PCIE_SATA_CFG,
+                .mask = SATA_CFG_VAL(0),
+                .val = SATA_CFG_VAL(0),
+        },
+};
+
+static struct spear_modemux sata0_modemux[] = {
+        {
+                .muxregs = sata0_muxreg,
+                .nmuxregs = ARRAY_SIZE(sata0_muxreg),
+        },
+};
+
+static struct spear_pingroup sata0_pingroup = {
+        .name = "sata0_grp",
+        .pins = pci_sata_pins,
+        .npins = ARRAY_SIZE(pci_sata_pins),
+        .modemuxs = sata0_modemux,
+        .nmodemuxs = ARRAY_SIZE(sata0_modemux),
+};
+
+/* pad multiplexing for sata1 device */
+static struct spear_muxreg sata1_muxreg[] = {
+        PCI_SATA_MUXREG,
+        {
+                .reg = PCIE_SATA_CFG,
+                .mask = SATA_CFG_VAL(1),
+                .val = SATA_CFG_VAL(1),
+        },
+};
+
+static struct spear_modemux sata1_modemux[] = {
+        {
+                .muxregs = sata1_muxreg,
+                .nmuxregs = ARRAY_SIZE(sata1_muxreg),
+        },
+};
+
+static struct spear_pingroup sata1_pingroup = {
+        .name = "sata1_grp",
+        .pins = pci_sata_pins,
+        .npins = ARRAY_SIZE(pci_sata_pins),
+        .modemuxs = sata1_modemux,
+        .nmodemuxs = ARRAY_SIZE(sata1_modemux),
+};
+
+/* pad multiplexing for sata2 device */
+static struct spear_muxreg sata2_muxreg[] = {
+        PCI_SATA_MUXREG,
+        {
+                .reg = PCIE_SATA_CFG,
+                .mask = SATA_CFG_VAL(2),
+                .val = SATA_CFG_VAL(2),
+        },
+};
+
+static struct spear_modemux sata2_modemux[] = {
+        {
+                .muxregs = sata2_muxreg,
+                .nmuxregs = ARRAY_SIZE(sata2_muxreg),
+        },
+};
+
+static struct spear_pingroup sata2_pingroup = {
+        .name = "sata2_grp",
+        .pins = pci_sata_pins,
+        .npins = ARRAY_SIZE(pci_sata_pins),
+        .modemuxs = sata2_modemux,
+        .nmodemuxs = ARRAY_SIZE(sata2_modemux),
+};
+
+static const char *const sata_grps[] = { "sata0_grp", "sata1_grp", "sata2_grp"
+};
+static struct spear_function sata_function = {
+        .name = "sata",
+        .groups = sata_grps,
+        .ngroups = ARRAY_SIZE(sata_grps),
+};
+
+/* Pad multiplexing for ssp1_dis_kbd device */
+static const unsigned ssp1_dis_kbd_pins[] = { 203, 204, 205, 206 };
+static struct spear_muxreg ssp1_dis_kbd_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_1,
+                .mask = PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK |
+                        PMX_KBD_COL0_MASK | PMX_NFIO8_15_MASK | PMX_NFCE1_MASK |
+                        PMX_NFCE2_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux ssp1_dis_kbd_modemux[] = {
+        {
+                .muxregs = ssp1_dis_kbd_muxreg,
+                .nmuxregs = ARRAY_SIZE(ssp1_dis_kbd_muxreg),
+        },
+};
+
+static struct spear_pingroup ssp1_dis_kbd_pingroup = {
+        .name = "ssp1_dis_kbd_grp",
+        .pins = ssp1_dis_kbd_pins,
+        .npins = ARRAY_SIZE(ssp1_dis_kbd_pins),
+        .modemuxs = ssp1_dis_kbd_modemux,
+        .nmodemuxs = ARRAY_SIZE(ssp1_dis_kbd_modemux),
+};
+
+/* Pad multiplexing for ssp1_dis_sd device */
+static const unsigned ssp1_dis_sd_pins[] = { 224, 226, 227, 228 };
+static struct spear_muxreg ssp1_dis_sd_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_2,
+                .mask = PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK |
+                        PMX_MCICECF_MASK | PMX_MCICEXD_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux ssp1_dis_sd_modemux[] = {
+        {
+                .muxregs = ssp1_dis_sd_muxreg,
+                .nmuxregs = ARRAY_SIZE(ssp1_dis_sd_muxreg),
+        },
+};
+
+static struct spear_pingroup ssp1_dis_sd_pingroup = {
+        .name = "ssp1_dis_sd_grp",
+        .pins = ssp1_dis_sd_pins,
+        .npins = ARRAY_SIZE(ssp1_dis_sd_pins),
+        .modemuxs = ssp1_dis_sd_modemux,
+        .nmodemuxs = ARRAY_SIZE(ssp1_dis_sd_modemux),
+};
+
+static const char *const ssp1_grps[] = { "ssp1_dis_kbd_grp",
+        "ssp1_dis_sd_grp" };
+static struct spear_function ssp1_function = {
+        .name = "ssp1",
+        .groups = ssp1_grps,
+        .ngroups = ARRAY_SIZE(ssp1_grps),
+};
+
+/* Pad multiplexing for gpt64 device */
+static const unsigned gpt64_pins[] = { 230, 231, 232, 245 };
+static struct spear_muxreg gpt64_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_2,
+                .mask = PMX_MCICDCF1_MASK | PMX_MCICDCF2_MASK | PMX_MCICDXD_MASK
+                        | PMX_MCILEDS_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux gpt64_modemux[] = {
+        {
+                .muxregs = gpt64_muxreg,
+                .nmuxregs = ARRAY_SIZE(gpt64_muxreg),
+        },
+};
+
+static struct spear_pingroup gpt64_pingroup = {
+        .name = "gpt64_grp",
+        .pins = gpt64_pins,
+        .npins = ARRAY_SIZE(gpt64_pins),
+        .modemuxs = gpt64_modemux,
+        .nmodemuxs = ARRAY_SIZE(gpt64_modemux),
+};
+
+static const char *const gpt64_grps[] = { "gpt64_grp" };
+static struct spear_function gpt64_function = {
+        .name = "gpt64",
+        .groups = gpt64_grps,
+        .ngroups = ARRAY_SIZE(gpt64_grps),
+};
+
+/* pingroups */
+static struct spear_pingroup *spear1310_pingroups[] = {
+        &i2c0_pingroup,
+        &ssp0_pingroup,
+        &i2s0_pingroup,
+        &i2s1_pingroup,
+        &clcd_pingroup,
+        &clcd_high_res_pingroup,
+        &arm_gpio_pingroup,
+        &smi_2_chips_pingroup,
+        &smi_4_chips_pingroup,
+        &gmii_pingroup,
+        &rgmii_pingroup,
+        &smii_0_1_2_pingroup,
+        &ras_mii_txclk_pingroup,
+        &nand_8bit_pingroup,
+        &nand_16bit_pingroup,
+        &nand_4_chips_pingroup,
+        &keyboard_6x6_pingroup,
+        &keyboard_rowcol6_8_pingroup,
+        &uart0_pingroup,
+        &uart0_modem_pingroup,
+        &gpt0_tmr0_pingroup,
+        &gpt0_tmr1_pingroup,
+        &gpt1_tmr0_pingroup,
+        &gpt1_tmr1_pingroup,
+        &sdhci_pingroup,
+        &cf_pingroup,
+        &xd_pingroup,
+        &touch_xy_pingroup,
+        &ssp0_cs0_pingroup,
+        &ssp0_cs1_2_pingroup,
+        &uart_1_dis_i2c_pingroup,
+        &uart_1_dis_sd_pingroup,
+        &uart_2_3_pingroup,
+        &uart_4_pingroup,
+        &uart_5_pingroup,
+        &rs485_0_1_tdm_0_1_pingroup,
+        &i2c_1_2_pingroup,
+        &i2c3_dis_smi_clcd_pingroup,
+        &i2c3_dis_sd_i2s0_pingroup,
+        &i2c_4_5_dis_smi_pingroup,
+        &i2c4_dis_sd_pingroup,
+        &i2c5_dis_sd_pingroup,
+        &i2c_6_7_dis_kbd_pingroup,
+        &i2c6_dis_sd_pingroup,
+        &i2c7_dis_sd_pingroup,
+        &can0_dis_nor_pingroup,
+        &can0_dis_sd_pingroup,
+        &can1_dis_sd_pingroup,
+        &can1_dis_kbd_pingroup,
+        &pcie0_pingroup,
+        &pcie1_pingroup,
+        &pcie2_pingroup,
+        &sata0_pingroup,
+        &sata1_pingroup,
+        &sata2_pingroup,
+        &ssp1_dis_kbd_pingroup,
+        &ssp1_dis_sd_pingroup,
+        &gpt64_pingroup,
+};
+
+/* functions */
+static struct spear_function *spear1310_functions[] = {
+        &i2c0_function,
+        &ssp0_function,
+        &i2s0_function,
+        &i2s1_function,
+        &clcd_function,
+        &arm_gpio_function,
+        &smi_function,
+        &gmii_function,
+        &rgmii_function,
+        &smii_0_1_2_function,
+        &ras_mii_txclk_function,
+        &nand_function,
+        &keyboard_function,
+        &uart0_function,
+        &gpt0_function,
+        &gpt1_function,
+        &sdhci_function,
+        &cf_function,
+        &xd_function,
+        &touch_xy_function,
+        &uart1_function,
+        &uart2_3_function,
+        &uart4_function,
+        &uart5_function,
+        &rs485_0_1_tdm_0_1_function,
+        &i2c_1_2_function,
+        &i2c3_unction,
+        &i2c_4_5_function,
+        &i2c_6_7_function,
+        &can0_function,
+        &can1_function,
+        &pci_function,
+        &sata_function,
+        &ssp1_function,
+        &gpt64_function,
+};
+
+static struct spear_pinctrl_machdata spear1310_machdata = {
+        .pins = spear1310_pins,
+        .npins = ARRAY_SIZE(spear1310_pins),
+        .groups = spear1310_pingroups,
+        .ngroups = ARRAY_SIZE(spear1310_pingroups),
+        .functions = spear1310_functions,
+        .nfunctions = ARRAY_SIZE(spear1310_functions),
+        .modes_supported = false,
+};
+
+static struct of_device_id spear1310_pinctrl_of_match[] __devinitdata = {
+        {
+                .compatible = "st,spear1310-pinmux",
+        },
+        {},
+};
+
+static int __devinit spear1310_pinctrl_probe(struct platform_device *pdev)
+{
+        return spear_pinctrl_probe(pdev, &spear1310_machdata);
+}
+
+static int __devexit spear1310_pinctrl_remove(struct platform_device *pdev)
+{
+        return spear_pinctrl_remove(pdev);
+}
+
+static struct platform_driver spear1310_pinctrl_driver = {
+        .driver = {
+                .name = DRIVER_NAME,
+                .owner = THIS_MODULE,
+                .of_match_table = spear1310_pinctrl_of_match,
+        },
+        .probe = spear1310_pinctrl_probe,
+        .remove = __devexit_p(spear1310_pinctrl_remove),
+};
+
+static int __init spear1310_pinctrl_init(void)
+{
+        return platform_driver_register(&spear1310_pinctrl_driver);
+}
+arch_initcall(spear1310_pinctrl_init);
+
+static void __exit spear1310_pinctrl_exit(void)
+{
+        platform_driver_unregister(&spear1310_pinctrl_driver);
+}
+module_exit(spear1310_pinctrl_exit);
+
+MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>");
+MODULE_DESCRIPTION("ST Microelectronics SPEAr1310 pinctrl driver");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, spear1310_pinctrl_of_match);
diff --git a/drivers/pinctrl/spear/pinctrl-spear1340.c b/drivers/pinctrl/spear/pinctrl-spear1340.c
new file mode 100644
index 000000000000..a8ab2a6f51bf
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear1340.c
@@ -0,0 +1,1989 @@
+/*
+ * Driver for the ST Microelectronics SPEAr1340 pinmux
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include "pinctrl-spear.h"
+
+#define DRIVER_NAME "spear1340-pinmux"
+
+/* pins */
+static const struct pinctrl_pin_desc spear1340_pins[] = {
+        SPEAR_PIN_0_TO_101,
+        SPEAR_PIN_102_TO_245,
+        PINCTRL_PIN(246, "PLGPIO246"),
+        PINCTRL_PIN(247, "PLGPIO247"),
+        PINCTRL_PIN(248, "PLGPIO248"),
+        PINCTRL_PIN(249, "PLGPIO249"),
+        PINCTRL_PIN(250, "PLGPIO250"),
+        PINCTRL_PIN(251, "PLGPIO251"),
+};
+
+/* In SPEAr1340 there are two levels of pad muxing */
+/* - pads as gpio OR peripherals */
+#define PAD_FUNCTION_EN_1                       0x668
+#define PAD_FUNCTION_EN_2                       0x66C
+#define PAD_FUNCTION_EN_3                       0x670
+#define PAD_FUNCTION_EN_4                       0x674
+#define PAD_FUNCTION_EN_5                       0x690
+#define PAD_FUNCTION_EN_6                       0x694
+#define PAD_FUNCTION_EN_7                       0x698
+#define PAD_FUNCTION_EN_8                       0x69C
+
+/* - If peripherals, then primary OR alternate peripheral */
+#define PAD_SHARED_IP_EN_1                      0x6A0
+#define PAD_SHARED_IP_EN_2                      0x6A4
+
+/*
+ * Macro's for first level of pmx - pads as gpio OR peripherals. There are 8
+ * registers with 32 bits each for handling gpio pads, register 8 has only 26
+ * relevant bits.
+ */
+/* macro's for making pads as gpio's */
+#define PADS_AS_GPIO_REG0_MASK                  0xFFFFFFFE
+#define PADS_AS_GPIO_REGS_MASK                  0xFFFFFFFF
+#define PADS_AS_GPIO_REG7_MASK                  0x07FFFFFF
+
+/* macro's for making pads as peripherals */
+#define FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK   0x00000FFE
+#define UART0_ENH_AND_GPT_REG0_MASK             0x0003F000
+#define PWM1_AND_KBD_COL5_REG0_MASK             0x00040000
+#define I2C1_REG0_MASK                          0x01080000
+#define SPDIF_IN_REG0_MASK                      0x00100000
+#define PWM2_AND_GPT0_TMR0_CPT_REG0_MASK        0x00400000
+#define PWM3_AND_GPT0_TMR1_CLK_REG0_MASK        0x00800000
+#define PWM0_AND_SSP0_CS1_REG0_MASK             0x02000000
+#define VIP_AND_CAM3_REG0_MASK                  0xFC200000
+#define VIP_AND_CAM3_REG1_MASK                  0x0000000F
+#define VIP_REG1_MASK                           0x00001EF0
+#define VIP_AND_CAM2_REG1_MASK                  0x007FE100
+#define VIP_AND_CAM1_REG1_MASK                  0xFF800000
+#define VIP_AND_CAM1_REG2_MASK                  0x00000003
+#define VIP_AND_CAM0_REG2_MASK                  0x00001FFC
+#define SMI_REG2_MASK                           0x0021E000
+#define SSP0_REG2_MASK                          0x001E0000
+#define TS_AND_SSP0_CS2_REG2_MASK               0x00400000
+#define UART0_REG2_MASK                         0x01800000
+#define UART1_REG2_MASK                         0x06000000
+#define I2S_IN_REG2_MASK                        0xF8000000
+#define DEVS_GRP_AND_MIPHY_DBG_REG3_MASK        0x000001FE
+#define I2S_OUT_REG3_MASK                       0x000001EF
+#define I2S_IN_REG3_MASK                        0x00000010
+#define GMAC_REG3_MASK                          0xFFFFFE00
+#define GMAC_REG4_MASK                          0x0000001F
+#define DEVS_GRP_AND_MIPHY_DBG_REG4_MASK        0x7FFFFF20
+#define SSP0_CS3_REG4_MASK                      0x00000020
+#define I2C0_REG4_MASK                          0x000000C0
+#define CEC0_REG4_MASK                          0x00000100
+#define CEC1_REG4_MASK                          0x00000200
+#define SPDIF_OUT_REG4_MASK                     0x00000400
+#define CLCD_REG4_MASK                          0x7FFFF800
+#define CLCD_AND_ARM_TRACE_REG4_MASK            0x80000000
+#define CLCD_AND_ARM_TRACE_REG5_MASK            0xFFFFFFFF
+#define CLCD_AND_ARM_TRACE_REG6_MASK            0x00000001
+#define FSMC_PNOR_AND_MCIF_REG6_MASK            0x073FFFFE
+#define MCIF_REG6_MASK                          0xF8C00000
+#define MCIF_REG7_MASK                          0x000043FF
+#define FSMC_8BIT_REG7_MASK                     0x07FFBC00
+
+/* other registers */
+#define PERIP_CFG                               0x42C
+        /* PERIP_CFG register masks */
+        #define SSP_CS_CTL_HW                   0
+        #define SSP_CS_CTL_SW                   1
+        #define SSP_CS_CTL_MASK                 1
+        #define SSP_CS_CTL_SHIFT                21
+        #define SSP_CS_VAL_MASK                 1
+        #define SSP_CS_VAL_SHIFT                20
+        #define SSP_CS_SEL_CS0                  0
+        #define SSP_CS_SEL_CS1                  1
+        #define SSP_CS_SEL_CS2                  2
+        #define SSP_CS_SEL_MASK                 3
+        #define SSP_CS_SEL_SHIFT                18
+
+        #define I2S_CHNL_2_0                    (0)
+        #define I2S_CHNL_3_1                    (1)
+        #define I2S_CHNL_5_1                    (2)
+        #define I2S_CHNL_7_1                    (3)
+        #define I2S_CHNL_PLAY_SHIFT             (4)
+        #define I2S_CHNL_PLAY_MASK              (3 << 4)
+        #define I2S_CHNL_REC_SHIFT              (6)
+        #define I2S_CHNL_REC_MASK               (3 << 6)
+
+        #define SPDIF_OUT_ENB_MASK              (1 << 2)
+        #define SPDIF_OUT_ENB_SHIFT             2
+
+        #define MCIF_SEL_SD                     1
+        #define MCIF_SEL_CF                     2
+        #define MCIF_SEL_XD                     3
+        #define MCIF_SEL_MASK                   3
+        #define MCIF_SEL_SHIFT                  0
+
+#define GMAC_CLK_CFG                            0x248
+        #define GMAC_PHY_IF_GMII_VAL            (0 << 3)
+        #define GMAC_PHY_IF_RGMII_VAL           (1 << 3)
+        #define GMAC_PHY_IF_SGMII_VAL           (2 << 3)
+        #define GMAC_PHY_IF_RMII_VAL            (4 << 3)
+        #define GMAC_PHY_IF_SEL_MASK            (7 << 3)
+        #define GMAC_PHY_INPUT_ENB_VAL          0
+        #define GMAC_PHY_SYNT_ENB_VAL           1
+        #define GMAC_PHY_CLK_MASK               1
+        #define GMAC_PHY_CLK_SHIFT              2
+        #define GMAC_PHY_125M_PAD_VAL           0
+        #define GMAC_PHY_PLL2_VAL               1
+        #define GMAC_PHY_OSC3_VAL               2
+        #define GMAC_PHY_INPUT_CLK_MASK         3
+        #define GMAC_PHY_INPUT_CLK_SHIFT        0
+
+#define PCIE_SATA_CFG                           0x424
+        /* PCIE CFG MASks */
+        #define PCIE_CFG_DEVICE_PRESENT         (1 << 11)
+        #define PCIE_CFG_POWERUP_RESET          (1 << 10)
+        #define PCIE_CFG_CORE_CLK_EN            (1 << 9)
+        #define PCIE_CFG_AUX_CLK_EN             (1 << 8)
+        #define SATA_CFG_TX_CLK_EN              (1 << 4)
+        #define SATA_CFG_RX_CLK_EN              (1 << 3)
+        #define SATA_CFG_POWERUP_RESET          (1 << 2)
+        #define SATA_CFG_PM_CLK_EN              (1 << 1)
+        #define PCIE_SATA_SEL_PCIE              (0)
+        #define PCIE_SATA_SEL_SATA              (1)
+        #define SATA_PCIE_CFG_MASK              0xF1F
+        #define PCIE_CFG_VAL    (PCIE_SATA_SEL_PCIE | PCIE_CFG_AUX_CLK_EN | \
+                                PCIE_CFG_CORE_CLK_EN | PCIE_CFG_POWERUP_RESET |\
+                                PCIE_CFG_DEVICE_PRESENT)
+        #define SATA_CFG_VAL    (PCIE_SATA_SEL_SATA | SATA_CFG_PM_CLK_EN | \
+                                SATA_CFG_POWERUP_RESET | SATA_CFG_RX_CLK_EN | \
+                                SATA_CFG_TX_CLK_EN)
+
+/* Macro's for second level of pmx - pads as primary OR alternate peripheral */
+/* Write 0 to enable FSMC_16_BIT */
+#define KBD_ROW_COL_MASK                        (1 << 0)
+
+/* Write 0 to enable UART0_ENH */
+#define GPT_MASK                                (1 << 1) /* Only clk & cpt */
+
+/* Write 0 to enable PWM1 */
+#define KBD_COL5_MASK                           (1 << 2)
+
+/* Write 0 to enable PWM2 */
+#define GPT0_TMR0_CPT_MASK                      (1 << 3) /* Only clk & cpt */
+
+/* Write 0 to enable PWM3 */
+#define GPT0_TMR1_CLK_MASK                      (1 << 4) /* Only clk & cpt */
+
+/* Write 0 to enable PWM0 */
+#define SSP0_CS1_MASK                           (1 << 5)
+
+/* Write 0 to enable VIP */
+#define CAM3_MASK                               (1 << 6)
+
+/* Write 0 to enable VIP */
+#define CAM2_MASK                               (1 << 7)
+
+/* Write 0 to enable VIP */
+#define CAM1_MASK                               (1 << 8)
+
+/* Write 0 to enable VIP */
+#define CAM0_MASK                               (1 << 9)
+
+/* Write 0 to enable TS */
+#define SSP0_CS2_MASK                           (1 << 10)
+
+/* Write 0 to enable FSMC PNOR */
+#define MCIF_MASK                               (1 << 11)
+
+/* Write 0 to enable CLCD */
+#define ARM_TRACE_MASK                          (1 << 12)
+
+/* Write 0 to enable I2S, SSP0_CS2, CEC0, 1, SPDIF out, CLCD */
+#define MIPHY_DBG_MASK                          (1 << 13)
+
+/*
+ * Pad multiplexing for making all pads as gpio's. This is done to override the
+ * values passed from bootloader and start from scratch.
+ */
+static const unsigned pads_as_gpio_pins[] = { 251 };
+static struct spear_muxreg pads_as_gpio_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_1,
+                .mask = PADS_AS_GPIO_REG0_MASK,
+                .val = 0x0,
+        }, {
+                .reg = PAD_FUNCTION_EN_2,
+                .mask = PADS_AS_GPIO_REGS_MASK,
+                .val = 0x0,
+        }, {
+                .reg = PAD_FUNCTION_EN_3,
+                .mask = PADS_AS_GPIO_REGS_MASK,
+                .val = 0x0,
+        }, {
+                .reg = PAD_FUNCTION_EN_4,
+                .mask = PADS_AS_GPIO_REGS_MASK,
+                .val = 0x0,
+        }, {
+                .reg = PAD_FUNCTION_EN_5,
+                .mask = PADS_AS_GPIO_REGS_MASK,
+                .val = 0x0,
+        }, {
+                .reg = PAD_FUNCTION_EN_6,
+                .mask = PADS_AS_GPIO_REGS_MASK,
+                .val = 0x0,
+        }, {
+                .reg = PAD_FUNCTION_EN_7,
+                .mask = PADS_AS_GPIO_REGS_MASK,
+                .val = 0x0,
+        }, {
+                .reg = PAD_FUNCTION_EN_8,
+                .mask = PADS_AS_GPIO_REG7_MASK,
+                .val = 0x0,
+        },
+};
+
+static struct spear_modemux pads_as_gpio_modemux[] = {
+        {
+                .muxregs = pads_as_gpio_muxreg,
+                .nmuxregs = ARRAY_SIZE(pads_as_gpio_muxreg),
+        },
+};
+
+static struct spear_pingroup pads_as_gpio_pingroup = {
+        .name = "pads_as_gpio_grp",
+        .pins = pads_as_gpio_pins,
+        .npins = ARRAY_SIZE(pads_as_gpio_pins),
+        .modemuxs = pads_as_gpio_modemux,
+        .nmodemuxs = ARRAY_SIZE(pads_as_gpio_modemux),
+};
+
+static const char *const pads_as_gpio_grps[] = { "pads_as_gpio_grp" };
+static struct spear_function pads_as_gpio_function = {
+        .name = "pads_as_gpio",
+        .groups = pads_as_gpio_grps,
+        .ngroups = ARRAY_SIZE(pads_as_gpio_grps),
+};
+
+/* Pad multiplexing for fsmc_8bit device */
+static const unsigned fsmc_8bit_pins[] = { 233, 234, 235, 236, 238, 239, 240,
+        241, 242, 243, 244, 245, 246, 247, 248, 249 };
+static struct spear_muxreg fsmc_8bit_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_8,
+                .mask = FSMC_8BIT_REG7_MASK,
+                .val = FSMC_8BIT_REG7_MASK,
+        }
+};
+
+static struct spear_modemux fsmc_8bit_modemux[] = {
+        {
+                .muxregs = fsmc_8bit_muxreg,
+                .nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg),
+        },
+};
+
+static struct spear_pingroup fsmc_8bit_pingroup = {
+        .name = "fsmc_8bit_grp",
+        .pins = fsmc_8bit_pins,
+        .npins = ARRAY_SIZE(fsmc_8bit_pins),
+        .modemuxs = fsmc_8bit_modemux,
+        .nmodemuxs = ARRAY_SIZE(fsmc_8bit_modemux),
+};
+
+/* Pad multiplexing for fsmc_16bit device */
+static const unsigned fsmc_16bit_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 };
+static struct spear_muxreg fsmc_16bit_muxreg[] = {
+        {
+                .reg = PAD_SHARED_IP_EN_1,
+                .mask = KBD_ROW_COL_MASK,
+                .val = 0,
+        }, {
+                .reg = PAD_FUNCTION_EN_1,
+                .mask = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK,
+                .val = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK,
+        },
+};
+
+static struct spear_modemux fsmc_16bit_modemux[] = {
+        {
+                .muxregs = fsmc_16bit_muxreg,
+                .nmuxregs = ARRAY_SIZE(fsmc_16bit_muxreg),
+        },
+};
+
+static struct spear_pingroup fsmc_16bit_pingroup = {
+        .name = "fsmc_16bit_grp",
+        .pins = fsmc_16bit_pins,
+        .npins = ARRAY_SIZE(fsmc_16bit_pins),
+        .modemuxs = fsmc_16bit_modemux,
+        .nmodemuxs = ARRAY_SIZE(fsmc_16bit_modemux),
+};
+
+/* pad multiplexing for fsmc_pnor device */
+static const unsigned fsmc_pnor_pins[] = { 192, 193, 194, 195, 196, 197, 198,
+        199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212,
+        215, 216, 217 };
+static struct spear_muxreg fsmc_pnor_muxreg[] = {
+        {
+                .reg = PAD_SHARED_IP_EN_1,
+                .mask = MCIF_MASK,
+                .val = 0,
+        }, {
+                .reg = PAD_FUNCTION_EN_7,
+                .mask = FSMC_PNOR_AND_MCIF_REG6_MASK,
+                .val = FSMC_PNOR_AND_MCIF_REG6_MASK,
+        },
+};
+
+static struct spear_modemux fsmc_pnor_modemux[] = {
+        {
+                .muxregs = fsmc_pnor_muxreg,
+                .nmuxregs = ARRAY_SIZE(fsmc_pnor_muxreg),
+        },
+};
+
+static struct spear_pingroup fsmc_pnor_pingroup = {
+        .name = "fsmc_pnor_grp",
+        .pins = fsmc_pnor_pins,
+        .npins = ARRAY_SIZE(fsmc_pnor_pins),
+        .modemuxs = fsmc_pnor_modemux,
+        .nmodemuxs = ARRAY_SIZE(fsmc_pnor_modemux),
+};
+
+static const char *const fsmc_grps[] = { "fsmc_8bit_grp", "fsmc_16bit_grp",
+        "fsmc_pnor_grp" };
+static struct spear_function fsmc_function = {
+        .name = "fsmc",
+        .groups = fsmc_grps,
+        .ngroups = ARRAY_SIZE(fsmc_grps),
+};
+
+/* pad multiplexing for keyboard rows-cols device */
+static const unsigned keyboard_row_col_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
+        10 };
+static struct spear_muxreg keyboard_row_col_muxreg[] = {
+        {
+                .reg = PAD_SHARED_IP_EN_1,
+                .mask = KBD_ROW_COL_MASK,
+                .val = KBD_ROW_COL_MASK,
+        }, {
+                .reg = PAD_FUNCTION_EN_1,
+                .mask = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK,
+                .val = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK,
+        },
+};
+
+static struct spear_modemux keyboard_row_col_modemux[] = {
+        {
+                .muxregs = keyboard_row_col_muxreg,
+                .nmuxregs = ARRAY_SIZE(keyboard_row_col_muxreg),
+        },
+};
+
+static struct spear_pingroup keyboard_row_col_pingroup = {
+        .name = "keyboard_row_col_grp",
+        .pins = keyboard_row_col_pins,
+        .npins = ARRAY_SIZE(keyboard_row_col_pins),
+        .modemuxs = keyboard_row_col_modemux,
+        .nmodemuxs = ARRAY_SIZE(keyboard_row_col_modemux),
+};
+
+/* pad multiplexing for keyboard col5 device */
+static const unsigned keyboard_col5_pins[] = { 17 };
+static struct spear_muxreg keyboard_col5_muxreg[] = {
+        {
+                .reg = PAD_SHARED_IP_EN_1,
+                .mask = KBD_COL5_MASK,
+                .val = KBD_COL5_MASK,
+        }, {
+                .reg = PAD_FUNCTION_EN_1,
+                .mask = PWM1_AND_KBD_COL5_REG0_MASK,
+                .val = PWM1_AND_KBD_COL5_REG0_MASK,
+        },
+};
+
+static struct spear_modemux keyboard_col5_modemux[] = {
+        {
+                .muxregs = keyboard_col5_muxreg,
+                .nmuxregs = ARRAY_SIZE(keyboard_col5_muxreg),
+        },
+};
+
+static struct spear_pingroup keyboard_col5_pingroup = {
+        .name = "keyboard_col5_grp",
+        .pins = keyboard_col5_pins,
+        .npins = ARRAY_SIZE(keyboard_col5_pins),
+        .modemuxs = keyboard_col5_modemux,
+        .nmodemuxs = ARRAY_SIZE(keyboard_col5_modemux),
+};
+
+static const char *const keyboard_grps[] = { "keyboard_row_col_grp",
+        "keyboard_col5_grp" };
+static struct spear_function keyboard_function = {
+        .name = "keyboard",
+        .groups = keyboard_grps,
+        .ngroups = ARRAY_SIZE(keyboard_grps),
+};
+
+/* pad multiplexing for spdif_in device */
+static const unsigned spdif_in_pins[] = { 19 };
+static struct spear_muxreg spdif_in_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_1,
+                .mask = SPDIF_IN_REG0_MASK,
+                .val = SPDIF_IN_REG0_MASK,
+        },
+};
+
+static struct spear_modemux spdif_in_modemux[] = {
+        {
+                .muxregs = spdif_in_muxreg,
+                .nmuxregs = ARRAY_SIZE(spdif_in_muxreg),
+        },
+};
+
+static struct spear_pingroup spdif_in_pingroup = {
+        .name = "spdif_in_grp",
+        .pins = spdif_in_pins,
+        .npins = ARRAY_SIZE(spdif_in_pins),
+        .modemuxs = spdif_in_modemux,
+        .nmodemuxs = ARRAY_SIZE(spdif_in_modemux),
+};
+
+static const char *const spdif_in_grps[] = { "spdif_in_grp" };
+static struct spear_function spdif_in_function = {
+        .name = "spdif_in",
+        .groups = spdif_in_grps,
+        .ngroups = ARRAY_SIZE(spdif_in_grps),
+};
+
+/* pad multiplexing for spdif_out device */
+static const unsigned spdif_out_pins[] = { 137 };
+static struct spear_muxreg spdif_out_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_5,
+                .mask = SPDIF_OUT_REG4_MASK,
+                .val = SPDIF_OUT_REG4_MASK,
+        }, {
+                .reg = PERIP_CFG,
+                .mask = SPDIF_OUT_ENB_MASK,
+                .val = SPDIF_OUT_ENB_MASK,
+        }
+};
+
+static struct spear_modemux spdif_out_modemux[] = {
+        {
+                .muxregs = spdif_out_muxreg,
+                .nmuxregs = ARRAY_SIZE(spdif_out_muxreg),
+        },
+};
+
+static struct spear_pingroup spdif_out_pingroup = {
+        .name = "spdif_out_grp",
+        .pins = spdif_out_pins,
+        .npins = ARRAY_SIZE(spdif_out_pins),
+        .modemuxs = spdif_out_modemux,
+        .nmodemuxs = ARRAY_SIZE(spdif_out_modemux),
+};
+
+static const char *const spdif_out_grps[] = { "spdif_out_grp" };
+static struct spear_function spdif_out_function = {
+        .name = "spdif_out",
+        .groups = spdif_out_grps,
+        .ngroups = ARRAY_SIZE(spdif_out_grps),
+};
+
+/* pad multiplexing for gpt_0_1 device */
+static const unsigned gpt_0_1_pins[] = { 11, 12, 13, 14, 15, 16, 21, 22 };
+static struct spear_muxreg gpt_0_1_muxreg[] = {
+        {
+                .reg = PAD_SHARED_IP_EN_1,
+                .mask = GPT_MASK | GPT0_TMR0_CPT_MASK | GPT0_TMR1_CLK_MASK,
+                .val = GPT_MASK | GPT0_TMR0_CPT_MASK | GPT0_TMR1_CLK_MASK,
+        }, {
+                .reg = PAD_FUNCTION_EN_1,
+                .mask = UART0_ENH_AND_GPT_REG0_MASK |
+                        PWM2_AND_GPT0_TMR0_CPT_REG0_MASK |
+                        PWM3_AND_GPT0_TMR1_CLK_REG0_MASK,
+                .val = UART0_ENH_AND_GPT_REG0_MASK |
+                        PWM2_AND_GPT0_TMR0_CPT_REG0_MASK |
+                        PWM3_AND_GPT0_TMR1_CLK_REG0_MASK,
+        },
+};
+
+static struct spear_modemux gpt_0_1_modemux[] = {
+        {
+                .muxregs = gpt_0_1_muxreg,
+                .nmuxregs = ARRAY_SIZE(gpt_0_1_muxreg),
+        },
+};
+
+static struct spear_pingroup gpt_0_1_pingroup = {
+        .name = "gpt_0_1_grp",
+        .pins = gpt_0_1_pins,
+        .npins = ARRAY_SIZE(gpt_0_1_pins),
+        .modemuxs = gpt_0_1_modemux,
+        .nmodemuxs = ARRAY_SIZE(gpt_0_1_modemux),
+};
+
+static const char *const gpt_0_1_grps[] = { "gpt_0_1_grp" };
+static struct spear_function gpt_0_1_function = {
+        .name = "gpt_0_1",
+        .groups = gpt_0_1_grps,
+        .ngroups = ARRAY_SIZE(gpt_0_1_grps),
+};
+
+/* pad multiplexing for pwm0 device */
+static const unsigned pwm0_pins[] = { 24 };
+static struct spear_muxreg pwm0_muxreg[] = {
+        {
+                .reg = PAD_SHARED_IP_EN_1,
+                .mask = SSP0_CS1_MASK,
+                .val = 0,
+        }, {
+                .reg = PAD_FUNCTION_EN_1,
+                .mask = PWM0_AND_SSP0_CS1_REG0_MASK,
+                .val = PWM0_AND_SSP0_CS1_REG0_MASK,
+        },
+};
+
+static struct spear_modemux pwm0_modemux[] = {
+        {
+                .muxregs = pwm0_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm0_muxreg),
+        },
+};
+
+static struct spear_pingroup pwm0_pingroup = {
+        .name = "pwm0_grp",
+        .pins = pwm0_pins,
+        .npins = ARRAY_SIZE(pwm0_pins),
+        .modemuxs = pwm0_modemux,
+        .nmodemuxs = ARRAY_SIZE(pwm0_modemux),
+};
+
+/* pad multiplexing for pwm1 device */
+static const unsigned pwm1_pins[] = { 17 };
+static struct spear_muxreg pwm1_muxreg[] = {
+        {
+                .reg = PAD_SHARED_IP_EN_1,
+                .mask = KBD_COL5_MASK,
+                .val = 0,
+        }, {
+                .reg = PAD_FUNCTION_EN_1,
+                .mask = PWM1_AND_KBD_COL5_REG0_MASK,
+                .val = PWM1_AND_KBD_COL5_REG0_MASK,
+        },
+};
+
+static struct spear_modemux pwm1_modemux[] = {
+        {
+                .muxregs = pwm1_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm1_muxreg),
+        },
+};
+
+static struct spear_pingroup pwm1_pingroup = {
+        .name = "pwm1_grp",
+        .pins = pwm1_pins,
+        .npins = ARRAY_SIZE(pwm1_pins),
+        .modemuxs = pwm1_modemux,
+        .nmodemuxs = ARRAY_SIZE(pwm1_modemux),
+};
+
+/* pad multiplexing for pwm2 device */
+static const unsigned pwm2_pins[] = { 21 };
+static struct spear_muxreg pwm2_muxreg[] = {
+        {
+                .reg = PAD_SHARED_IP_EN_1,
+                .mask = GPT0_TMR0_CPT_MASK,
+                .val = 0,
+        }, {
+                .reg = PAD_FUNCTION_EN_1,
+                .mask = PWM2_AND_GPT0_TMR0_CPT_REG0_MASK,
+                .val = PWM2_AND_GPT0_TMR0_CPT_REG0_MASK,
+        },
+};
+
+static struct spear_modemux pwm2_modemux[] = {
+        {
+                .muxregs = pwm2_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm2_muxreg),
+        },
+};
+
+static struct spear_pingroup pwm2_pingroup = {
+        .name = "pwm2_grp",
+        .pins = pwm2_pins,
+        .npins = ARRAY_SIZE(pwm2_pins),
+        .modemuxs = pwm2_modemux,
+        .nmodemuxs = ARRAY_SIZE(pwm2_modemux),
+};
+
+/* pad multiplexing for pwm3 device */
+static const unsigned pwm3_pins[] = { 22 };
+static struct spear_muxreg pwm3_muxreg[] = {
+        {
+                .reg = PAD_SHARED_IP_EN_1,
+                .mask = GPT0_TMR1_CLK_MASK,
+                .val = 0,
+        }, {
+                .reg = PAD_FUNCTION_EN_1,
+                .mask = PWM3_AND_GPT0_TMR1_CLK_REG0_MASK,
+                .val = PWM3_AND_GPT0_TMR1_CLK_REG0_MASK,
+        },
+};
+
+static struct spear_modemux pwm3_modemux[] = {
+        {
+                .muxregs = pwm3_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm3_muxreg),
+        },
+};
+
+static struct spear_pingroup pwm3_pingroup = {
+        .name = "pwm3_grp",
+        .pins = pwm3_pins,
+        .npins = ARRAY_SIZE(pwm3_pins),
+        .modemuxs = pwm3_modemux,
+        .nmodemuxs = ARRAY_SIZE(pwm3_modemux),
+};
+
+static const char *const pwm_grps[] = { "pwm0_grp", "pwm1_grp", "pwm2_grp",
+        "pwm3_grp" };
+static struct spear_function pwm_function = {
+        .name = "pwm",
+        .groups = pwm_grps,
+        .ngroups = ARRAY_SIZE(pwm_grps),
+};
+
+/* pad multiplexing for vip_mux device */
+static const unsigned vip_mux_pins[] = { 35, 36, 37, 38, 40, 41, 42, 43 };
+static struct spear_muxreg vip_mux_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_2,
+                .mask = VIP_REG1_MASK,
+                .val = VIP_REG1_MASK,
+        },
+};
+
+static struct spear_modemux vip_mux_modemux[] = {
+        {
+                .muxregs = vip_mux_muxreg,
+                .nmuxregs = ARRAY_SIZE(vip_mux_muxreg),
+        },
+};
+
+static struct spear_pingroup vip_mux_pingroup = {
+        .name = "vip_mux_grp",
+        .pins = vip_mux_pins,
+        .npins = ARRAY_SIZE(vip_mux_pins),
+        .modemuxs = vip_mux_modemux,
+        .nmodemuxs = ARRAY_SIZE(vip_mux_modemux),
+};
+
+/* pad multiplexing for vip_mux_cam0 (disables cam0) device */
+static const unsigned vip_mux_cam0_pins[] = { 65, 66, 67, 68, 69, 70, 71, 72,
+        73, 74, 75 };
+static struct spear_muxreg vip_mux_cam0_muxreg[] = {
+        {
+                .reg = PAD_SHARED_IP_EN_1,
+                .mask = CAM0_MASK,
+                .val = 0,
+        }, {
+                .reg = PAD_FUNCTION_EN_3,
+                .mask = VIP_AND_CAM0_REG2_MASK,
+                .val = VIP_AND_CAM0_REG2_MASK,
+        },
+};
+
+static struct spear_modemux vip_mux_cam0_modemux[] = {
+        {
+                .muxregs = vip_mux_cam0_muxreg,
+                .nmuxregs = ARRAY_SIZE(vip_mux_cam0_muxreg),
+        },
+};
+
+static struct spear_pingroup vip_mux_cam0_pingroup = {
+        .name = "vip_mux_cam0_grp",
+        .pins = vip_mux_cam0_pins,
+        .npins = ARRAY_SIZE(vip_mux_cam0_pins),
+        .modemuxs = vip_mux_cam0_modemux,
+        .nmodemuxs = ARRAY_SIZE(vip_mux_cam0_modemux),
+};
+
+/* pad multiplexing for vip_mux_cam1 (disables cam1) device */
+static const unsigned vip_mux_cam1_pins[] = { 54, 55, 56, 57, 58, 59, 60, 61,
+        62, 63, 64 };
+static struct spear_muxreg vip_mux_cam1_muxreg[] = {
+        {
+                .reg = PAD_SHARED_IP_EN_1,
+                .mask = CAM1_MASK,
+                .val = 0,
+        }, {
+                .reg = PAD_FUNCTION_EN_2,
+                .mask = VIP_AND_CAM1_REG1_MASK,
+                .val = VIP_AND_CAM1_REG1_MASK,
+        }, {
+                .reg = PAD_FUNCTION_EN_3,
+                .mask = VIP_AND_CAM1_REG2_MASK,
+                .val = VIP_AND_CAM1_REG2_MASK,
+        },
+};
+
+static struct spear_modemux vip_mux_cam1_modemux[] = {
+        {
+                .muxregs = vip_mux_cam1_muxreg,
+                .nmuxregs = ARRAY_SIZE(vip_mux_cam1_muxreg),
+        },
+};
+
+static struct spear_pingroup vip_mux_cam1_pingroup = {
+        .name = "vip_mux_cam1_grp",
+        .pins = vip_mux_cam1_pins,
+        .npins = ARRAY_SIZE(vip_mux_cam1_pins),
+        .modemuxs = vip_mux_cam1_modemux,
+        .nmodemuxs = ARRAY_SIZE(vip_mux_cam1_modemux),
+};
+
+/* pad multiplexing for vip_mux_cam2 (disables cam2) device */
+static const unsigned vip_mux_cam2_pins[] = { 39, 44, 45, 46, 47, 48, 49, 50,
+        51, 52, 53 };
+static struct spear_muxreg vip_mux_cam2_muxreg[] = {
+        {
+                .reg = PAD_SHARED_IP_EN_1,
+                .mask = CAM2_MASK,
+                .val = 0,
+        }, {
+                .reg = PAD_FUNCTION_EN_2,
+                .mask = VIP_AND_CAM2_REG1_MASK,
+                .val = VIP_AND_CAM2_REG1_MASK,
+        },
+};
+
+static struct spear_modemux vip_mux_cam2_modemux[] = {
+        {
+                .muxregs = vip_mux_cam2_muxreg,
+                .nmuxregs = ARRAY_SIZE(vip_mux_cam2_muxreg),
+        },
+};
+
+static struct spear_pingroup vip_mux_cam2_pingroup = {
+        .name = "vip_mux_cam2_grp",
+        .pins = vip_mux_cam2_pins,
+        .npins = ARRAY_SIZE(vip_mux_cam2_pins),
+        .modemuxs = vip_mux_cam2_modemux,
+        .nmodemuxs = ARRAY_SIZE(vip_mux_cam2_modemux),
+};
+
+/* pad multiplexing for vip_mux_cam3 (disables cam3) device */
+static const unsigned vip_mux_cam3_pins[] = { 20, 25, 26, 27, 28, 29, 30, 31,
+        32, 33, 34 };
+static struct spear_muxreg vip_mux_cam3_muxreg[] = {
+        {
+                .reg = PAD_SHARED_IP_EN_1,
+                .mask = CAM3_MASK,
+                .val = 0,
+        }, {
+                .reg = PAD_FUNCTION_EN_1,
+                .mask = VIP_AND_CAM3_REG0_MASK,
+                .val = VIP_AND_CAM3_REG0_MASK,
+        }, {
+                .reg = PAD_FUNCTION_EN_2,
+                .mask = VIP_AND_CAM3_REG1_MASK,
+                .val = VIP_AND_CAM3_REG1_MASK,
+        },
+};
+
+static struct spear_modemux vip_mux_cam3_modemux[] = {
+        {
+                .muxregs = vip_mux_cam3_muxreg,
+                .nmuxregs = ARRAY_SIZE(vip_mux_cam3_muxreg),
+        },
+};
+
+static struct spear_pingroup vip_mux_cam3_pingroup = {
+        .name = "vip_mux_cam3_grp",
+        .pins = vip_mux_cam3_pins,
+        .npins = ARRAY_SIZE(vip_mux_cam3_pins),
+        .modemuxs = vip_mux_cam3_modemux,
+        .nmodemuxs = ARRAY_SIZE(vip_mux_cam3_modemux),
+};
+
+static const char *const vip_grps[] = { "vip_mux_grp", "vip_mux_cam0_grp" ,
+        "vip_mux_cam1_grp" , "vip_mux_cam2_grp", "vip_mux_cam3_grp" };
+static struct spear_function vip_function = {
+        .name = "vip",
+        .groups = vip_grps,
+        .ngroups = ARRAY_SIZE(vip_grps),
+};
+
+/* pad multiplexing for cam0 device */
+static const unsigned cam0_pins[] = { 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75
+};
+static struct spear_muxreg cam0_muxreg[] = {
+        {
+                .reg = PAD_SHARED_IP_EN_1,
+                .mask = CAM0_MASK,
+                .val = CAM0_MASK,
+        }, {
+                .reg = PAD_FUNCTION_EN_3,
+                .mask = VIP_AND_CAM0_REG2_MASK,
+                .val = VIP_AND_CAM0_REG2_MASK,
+        },
+};
+
+static struct spear_modemux cam0_modemux[] = {
+        {
+                .muxregs = cam0_muxreg,
+                .nmuxregs = ARRAY_SIZE(cam0_muxreg),
+        },
+};
+
+static struct spear_pingroup cam0_pingroup = {
+        .name = "cam0_grp",
+        .pins = cam0_pins,
+        .npins = ARRAY_SIZE(cam0_pins),
+        .modemuxs = cam0_modemux,
+        .nmodemuxs = ARRAY_SIZE(cam0_modemux),
+};
+
+static const char *const cam0_grps[] = { "cam0_grp" };
+static struct spear_function cam0_function = {
+        .name = "cam0",
+        .groups = cam0_grps,
+        .ngroups = ARRAY_SIZE(cam0_grps),
+};
+
+/* pad multiplexing for cam1 device */
+static const unsigned cam1_pins[] = { 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64
+};
+static struct spear_muxreg cam1_muxreg[] = {
+        {
+                .reg = PAD_SHARED_IP_EN_1,
+                .mask = CAM1_MASK,
+                .val = CAM1_MASK,
+        }, {
+                .reg = PAD_FUNCTION_EN_2,
+                .mask = VIP_AND_CAM1_REG1_MASK,
+                .val = VIP_AND_CAM1_REG1_MASK,
+        }, {
+                .reg = PAD_FUNCTION_EN_3,
+                .mask = VIP_AND_CAM1_REG2_MASK,
+                .val = VIP_AND_CAM1_REG2_MASK,
+        },
+};
+
+static struct spear_modemux cam1_modemux[] = {
+        {
+                .muxregs = cam1_muxreg,
+                .nmuxregs = ARRAY_SIZE(cam1_muxreg),
+        },
+};
+
+static struct spear_pingroup cam1_pingroup = {
+        .name = "cam1_grp",
+        .pins = cam1_pins,
+        .npins = ARRAY_SIZE(cam1_pins),
+        .modemuxs = cam1_modemux,
+        .nmodemuxs = ARRAY_SIZE(cam1_modemux),
+};
+
+static const char *const cam1_grps[] = { "cam1_grp" };
+static struct spear_function cam1_function = {
+        .name = "cam1",
+        .groups = cam1_grps,
+        .ngroups = ARRAY_SIZE(cam1_grps),
+};
+
+/* pad multiplexing for cam2 device */
+static const unsigned cam2_pins[] = { 39, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53
+};
+static struct spear_muxreg cam2_muxreg[] = {
+        {
+                .reg = PAD_SHARED_IP_EN_1,
+                .mask = CAM2_MASK,
+                .val = CAM2_MASK,
+        }, {
+                .reg = PAD_FUNCTION_EN_2,
+                .mask = VIP_AND_CAM2_REG1_MASK,
+                .val = VIP_AND_CAM2_REG1_MASK,
+        },
+};
+
+static struct spear_modemux cam2_modemux[] = {
+        {
+                .muxregs = cam2_muxreg,
+                .nmuxregs = ARRAY_SIZE(cam2_muxreg),
+        },
+};
+
+static struct spear_pingroup cam2_pingroup = {
+        .name = "cam2_grp",
+        .pins = cam2_pins,
+        .npins = ARRAY_SIZE(cam2_pins),
+        .modemuxs = cam2_modemux,
+        .nmodemuxs = ARRAY_SIZE(cam2_modemux),
+};
+
+static const char *const cam2_grps[] = { "cam2_grp" };
+static struct spear_function cam2_function = {
+        .name = "cam2",
+        .groups = cam2_grps,
+        .ngroups = ARRAY_SIZE(cam2_grps),
+};
+
+/* pad multiplexing for cam3 device */
+static const unsigned cam3_pins[] = { 20, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34
+};
+static struct spear_muxreg cam3_muxreg[] = {
+        {
+                .reg = PAD_SHARED_IP_EN_1,
+                .mask = CAM3_MASK,
+                .val = CAM3_MASK,
+        }, {
+                .reg = PAD_FUNCTION_EN_1,
+                .mask = VIP_AND_CAM3_REG0_MASK,
+                .val = VIP_AND_CAM3_REG0_MASK,
+        }, {
+                .reg = PAD_FUNCTION_EN_2,
+                .mask = VIP_AND_CAM3_REG1_MASK,
+                .val = VIP_AND_CAM3_REG1_MASK,
+        },
+};
+
+static struct spear_modemux cam3_modemux[] = {
+        {
+                .muxregs = cam3_muxreg,
+                .nmuxregs = ARRAY_SIZE(cam3_muxreg),
+        },
+};
+
+static struct spear_pingroup cam3_pingroup = {
+        .name = "cam3_grp",
+        .pins = cam3_pins,
+        .npins = ARRAY_SIZE(cam3_pins),
+        .modemuxs = cam3_modemux,
+        .nmodemuxs = ARRAY_SIZE(cam3_modemux),
+};
+
+static const char *const cam3_grps[] = { "cam3_grp" };
+static struct spear_function cam3_function = {
+        .name = "cam3",
+        .groups = cam3_grps,
+        .ngroups = ARRAY_SIZE(cam3_grps),
+};
+
+/* pad multiplexing for smi device */
+static const unsigned smi_pins[] = { 76, 77, 78, 79, 84 };
+static struct spear_muxreg smi_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_3,
+                .mask = SMI_REG2_MASK,
+                .val = SMI_REG2_MASK,
+        },
+};
+
+static struct spear_modemux smi_modemux[] = {
+        {
+                .muxregs = smi_muxreg,
+                .nmuxregs = ARRAY_SIZE(smi_muxreg),
+        },
+};
+
+static struct spear_pingroup smi_pingroup = {
+        .name = "smi_grp",
+        .pins = smi_pins,
+        .npins = ARRAY_SIZE(smi_pins),
+        .modemuxs = smi_modemux,
+        .nmodemuxs = ARRAY_SIZE(smi_modemux),
+};
+
+static const char *const smi_grps[] = { "smi_grp" };
+static struct spear_function smi_function = {
+        .name = "smi",
+        .groups = smi_grps,
+        .ngroups = ARRAY_SIZE(smi_grps),
+};
+
+/* pad multiplexing for ssp0 device */
+static const unsigned ssp0_pins[] = { 80, 81, 82, 83 };
+static struct spear_muxreg ssp0_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_3,
+                .mask = SSP0_REG2_MASK,
+                .val = SSP0_REG2_MASK,
+        },
+};
+
+static struct spear_modemux ssp0_modemux[] = {
+        {
+                .muxregs = ssp0_muxreg,
+                .nmuxregs = ARRAY_SIZE(ssp0_muxreg),
+        },
+};
+
+static struct spear_pingroup ssp0_pingroup = {
+        .name = "ssp0_grp",
+        .pins = ssp0_pins,
+        .npins = ARRAY_SIZE(ssp0_pins),
+        .modemuxs = ssp0_modemux,
+        .nmodemuxs = ARRAY_SIZE(ssp0_modemux),
+};
+
+/* pad multiplexing for ssp0_cs1 device */
+static const unsigned ssp0_cs1_pins[] = { 24 };
+static struct spear_muxreg ssp0_cs1_muxreg[] = {
+        {
+                .reg = PAD_SHARED_IP_EN_1,
+                .mask = SSP0_CS1_MASK,
+                .val = SSP0_CS1_MASK,
+        }, {
+                .reg = PAD_FUNCTION_EN_1,
+                .mask = PWM0_AND_SSP0_CS1_REG0_MASK,
+                .val = PWM0_AND_SSP0_CS1_REG0_MASK,
+        },
+};
+
+static struct spear_modemux ssp0_cs1_modemux[] = {
+        {
+                .muxregs = ssp0_cs1_muxreg,
+                .nmuxregs = ARRAY_SIZE(ssp0_cs1_muxreg),
+        },
+};
+
+static struct spear_pingroup ssp0_cs1_pingroup = {
+        .name = "ssp0_cs1_grp",
+        .pins = ssp0_cs1_pins,
+        .npins = ARRAY_SIZE(ssp0_cs1_pins),
+        .modemuxs = ssp0_cs1_modemux,
+        .nmodemuxs = ARRAY_SIZE(ssp0_cs1_modemux),
+};
+
+/* pad multiplexing for ssp0_cs2 device */
+static const unsigned ssp0_cs2_pins[] = { 85 };
+static struct spear_muxreg ssp0_cs2_muxreg[] = {
+        {
+                .reg = PAD_SHARED_IP_EN_1,
+                .mask = SSP0_CS2_MASK,
+                .val = SSP0_CS2_MASK,
+        }, {
+                .reg = PAD_FUNCTION_EN_3,
+                .mask = TS_AND_SSP0_CS2_REG2_MASK,
+                .val = TS_AND_SSP0_CS2_REG2_MASK,
+        },
+};
+
+static struct spear_modemux ssp0_cs2_modemux[] = {
+        {
+                .muxregs = ssp0_cs2_muxreg,
+                .nmuxregs = ARRAY_SIZE(ssp0_cs2_muxreg),
+        },
+};
+
+static struct spear_pingroup ssp0_cs2_pingroup = {
+        .name = "ssp0_cs2_grp",
+        .pins = ssp0_cs2_pins,
+        .npins = ARRAY_SIZE(ssp0_cs2_pins),
+        .modemuxs = ssp0_cs2_modemux,
+        .nmodemuxs = ARRAY_SIZE(ssp0_cs2_modemux),
+};
+
+/* pad multiplexing for ssp0_cs3 device */
+static const unsigned ssp0_cs3_pins[] = { 132 };
+static struct spear_muxreg ssp0_cs3_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_5,
+                .mask = SSP0_CS3_REG4_MASK,
+                .val = SSP0_CS3_REG4_MASK,
+        },
+};
+
+static struct spear_modemux ssp0_cs3_modemux[] = {
+        {
+                .muxregs = ssp0_cs3_muxreg,
+                .nmuxregs = ARRAY_SIZE(ssp0_cs3_muxreg),
+        },
+};
+
+static struct spear_pingroup ssp0_cs3_pingroup = {
+        .name = "ssp0_cs3_grp",
+        .pins = ssp0_cs3_pins,
+        .npins = ARRAY_SIZE(ssp0_cs3_pins),
+        .modemuxs = ssp0_cs3_modemux,
+        .nmodemuxs = ARRAY_SIZE(ssp0_cs3_modemux),
+};
+
+static const char *const ssp0_grps[] = { "ssp0_grp", "ssp0_cs1_grp",
+        "ssp0_cs2_grp", "ssp0_cs3_grp" };
+static struct spear_function ssp0_function = {
+        .name = "ssp0",
+        .groups = ssp0_grps,
+        .ngroups = ARRAY_SIZE(ssp0_grps),
+};
+
+/* pad multiplexing for uart0 device */
+static const unsigned uart0_pins[] = { 86, 87 };
+static struct spear_muxreg uart0_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_3,
+                .mask = UART0_REG2_MASK,
+                .val = UART0_REG2_MASK,
+        },
+};
+
+static struct spear_modemux uart0_modemux[] = {
+        {
+                .muxregs = uart0_muxreg,
+                .nmuxregs = ARRAY_SIZE(uart0_muxreg),
+        },
+};
+
+static struct spear_pingroup uart0_pingroup = {
+        .name = "uart0_grp",
+        .pins = uart0_pins,
+        .npins = ARRAY_SIZE(uart0_pins),
+        .modemuxs = uart0_modemux,
+        .nmodemuxs = ARRAY_SIZE(uart0_modemux),
+};
+
+/* pad multiplexing for uart0_enh device */
+static const unsigned uart0_enh_pins[] = { 11, 12, 13, 14, 15, 16 };
+static struct spear_muxreg uart0_enh_muxreg[] = {
+        {
+                .reg = PAD_SHARED_IP_EN_1,
+                .mask = GPT_MASK,
+                .val = 0,
+        }, {
+                .reg = PAD_FUNCTION_EN_1,
+                .mask = UART0_ENH_AND_GPT_REG0_MASK,
+                .val = UART0_ENH_AND_GPT_REG0_MASK,
+        },
+};
+
+static struct spear_modemux uart0_enh_modemux[] = {
+        {
+                .muxregs = uart0_enh_muxreg,
+                .nmuxregs = ARRAY_SIZE(uart0_enh_muxreg),
+        },
+};
+
+static struct spear_pingroup uart0_enh_pingroup = {
+        .name = "uart0_enh_grp",
+        .pins = uart0_enh_pins,
+        .npins = ARRAY_SIZE(uart0_enh_pins),
+        .modemuxs = uart0_enh_modemux,
+        .nmodemuxs = ARRAY_SIZE(uart0_enh_modemux),
+};
+
+static const char *const uart0_grps[] = { "uart0_grp", "uart0_enh_grp" };
+static struct spear_function uart0_function = {
+        .name = "uart0",
+        .groups = uart0_grps,
+        .ngroups = ARRAY_SIZE(uart0_grps),
+};
+
+/* pad multiplexing for uart1 device */
+static const unsigned uart1_pins[] = { 88, 89 };
+static struct spear_muxreg uart1_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_3,
+                .mask = UART1_REG2_MASK,
+                .val = UART1_REG2_MASK,
+        },
+};
+
+static struct spear_modemux uart1_modemux[] = {
+        {
+                .muxregs = uart1_muxreg,
+                .nmuxregs = ARRAY_SIZE(uart1_muxreg),
+        },
+};
+
+static struct spear_pingroup uart1_pingroup = {
+        .name = "uart1_grp",
+        .pins = uart1_pins,
+        .npins = ARRAY_SIZE(uart1_pins),
+        .modemuxs = uart1_modemux,
+        .nmodemuxs = ARRAY_SIZE(uart1_modemux),
+};
+
+static const char *const uart1_grps[] = { "uart1_grp" };
+static struct spear_function uart1_function = {
+        .name = "uart1",
+        .groups = uart1_grps,
+        .ngroups = ARRAY_SIZE(uart1_grps),
+};
+
+/* pad multiplexing for i2s_in device */
+static const unsigned i2s_in_pins[] = { 90, 91, 92, 93, 94, 99 };
+static struct spear_muxreg i2s_in_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_3,
+                .mask = I2S_IN_REG2_MASK,
+                .val = I2S_IN_REG2_MASK,
+        }, {
+                .reg = PAD_FUNCTION_EN_4,
+                .mask = I2S_IN_REG3_MASK,
+                .val = I2S_IN_REG3_MASK,
+        },
+};
+
+static struct spear_modemux i2s_in_modemux[] = {
+        {
+                .muxregs = i2s_in_muxreg,
+                .nmuxregs = ARRAY_SIZE(i2s_in_muxreg),
+        },
+};
+
+static struct spear_pingroup i2s_in_pingroup = {
+        .name = "i2s_in_grp",
+        .pins = i2s_in_pins,
+        .npins = ARRAY_SIZE(i2s_in_pins),
+        .modemuxs = i2s_in_modemux,
+        .nmodemuxs = ARRAY_SIZE(i2s_in_modemux),
+};
+
+/* pad multiplexing for i2s_out device */
+static const unsigned i2s_out_pins[] = { 95, 96, 97, 98, 100, 101, 102, 103 };
+static struct spear_muxreg i2s_out_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_4,
+                .mask = I2S_OUT_REG3_MASK,
+                .val = I2S_OUT_REG3_MASK,
+        },
+};
+
+static struct spear_modemux i2s_out_modemux[] = {
+        {
+                .muxregs = i2s_out_muxreg,
+                .nmuxregs = ARRAY_SIZE(i2s_out_muxreg),
+        },
+};
+
+static struct spear_pingroup i2s_out_pingroup = {
+        .name = "i2s_out_grp",
+        .pins = i2s_out_pins,
+        .npins = ARRAY_SIZE(i2s_out_pins),
+        .modemuxs = i2s_out_modemux,
+        .nmodemuxs = ARRAY_SIZE(i2s_out_modemux),
+};
+
+static const char *const i2s_grps[] = { "i2s_in_grp", "i2s_out_grp" };
+static struct spear_function i2s_function = {
+        .name = "i2s",
+        .groups = i2s_grps,
+        .ngroups = ARRAY_SIZE(i2s_grps),
+};
+
+/* pad multiplexing for gmac device */
+static const unsigned gmac_pins[] = { 104, 105, 106, 107, 108, 109, 110, 111,
+        112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125,
+        126, 127, 128, 129, 130, 131 };
+#define GMAC_MUXREG                             \
+        {                                       \
+                .reg = PAD_FUNCTION_EN_4,       \
+                .mask = GMAC_REG3_MASK,         \
+                .val = GMAC_REG3_MASK,          \
+        }, {                                    \
+                .reg = PAD_FUNCTION_EN_5,       \
+                .mask = GMAC_REG4_MASK,         \
+                .val = GMAC_REG4_MASK,          \
+        }
+
+/* pad multiplexing for gmii device */
+static struct spear_muxreg gmii_muxreg[] = {
+        GMAC_MUXREG,
+        {
+                .reg = GMAC_CLK_CFG,
+                .mask = GMAC_PHY_IF_SEL_MASK,
+                .val = GMAC_PHY_IF_GMII_VAL,
+        },
+};
+
+static struct spear_modemux gmii_modemux[] = {
+        {
+                .muxregs = gmii_muxreg,
+                .nmuxregs = ARRAY_SIZE(gmii_muxreg),
+        },
+};
+
+static struct spear_pingroup gmii_pingroup = {
+        .name = "gmii_grp",
+        .pins = gmac_pins,
+        .npins = ARRAY_SIZE(gmac_pins),
+        .modemuxs = gmii_modemux,
+        .nmodemuxs = ARRAY_SIZE(gmii_modemux),
+};
+
+/* pad multiplexing for rgmii device */
+static struct spear_muxreg rgmii_muxreg[] = {
+        GMAC_MUXREG,
+        {
+                .reg = GMAC_CLK_CFG,
+                .mask = GMAC_PHY_IF_SEL_MASK,
+                .val = GMAC_PHY_IF_RGMII_VAL,
+        },
+};
+
+static struct spear_modemux rgmii_modemux[] = {
+        {
+                .muxregs = rgmii_muxreg,
+                .nmuxregs = ARRAY_SIZE(rgmii_muxreg),
+        },
+};
+
+static struct spear_pingroup rgmii_pingroup = {
+        .name = "rgmii_grp",
+        .pins = gmac_pins,
+        .npins = ARRAY_SIZE(gmac_pins),
+        .modemuxs = rgmii_modemux,
+        .nmodemuxs = ARRAY_SIZE(rgmii_modemux),
+};
+
+/* pad multiplexing for rmii device */
+static struct spear_muxreg rmii_muxreg[] = {
+        GMAC_MUXREG,
+        {
+                .reg = GMAC_CLK_CFG,
+                .mask = GMAC_PHY_IF_SEL_MASK,
+                .val = GMAC_PHY_IF_RMII_VAL,
+        },
+};
+
+static struct spear_modemux rmii_modemux[] = {
+        {
+                .muxregs = rmii_muxreg,
+                .nmuxregs = ARRAY_SIZE(rmii_muxreg),
+        },
+};
+
+static struct spear_pingroup rmii_pingroup = {
+        .name = "rmii_grp",
+        .pins = gmac_pins,
+        .npins = ARRAY_SIZE(gmac_pins),
+        .modemuxs = rmii_modemux,
+        .nmodemuxs = ARRAY_SIZE(rmii_modemux),
+};
+
+/* pad multiplexing for sgmii device */
+static struct spear_muxreg sgmii_muxreg[] = {
+        GMAC_MUXREG,
+        {
+                .reg = GMAC_CLK_CFG,
+                .mask = GMAC_PHY_IF_SEL_MASK,
+                .val = GMAC_PHY_IF_SGMII_VAL,
+        },
+};
+
+static struct spear_modemux sgmii_modemux[] = {
+        {
+                .muxregs = sgmii_muxreg,
+                .nmuxregs = ARRAY_SIZE(sgmii_muxreg),
+        },
+};
+
+static struct spear_pingroup sgmii_pingroup = {
+        .name = "sgmii_grp",
+        .pins = gmac_pins,
+        .npins = ARRAY_SIZE(gmac_pins),
+        .modemuxs = sgmii_modemux,
+        .nmodemuxs = ARRAY_SIZE(sgmii_modemux),
+};
+
+static const char *const gmac_grps[] = { "gmii_grp", "rgmii_grp", "rmii_grp",
+        "sgmii_grp" };
+static struct spear_function gmac_function = {
+        .name = "gmac",
+        .groups = gmac_grps,
+        .ngroups = ARRAY_SIZE(gmac_grps),
+};
+
+/* pad multiplexing for i2c0 device */
+static const unsigned i2c0_pins[] = { 133, 134 };
+static struct spear_muxreg i2c0_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_5,
+                .mask = I2C0_REG4_MASK,
+                .val = I2C0_REG4_MASK,
+        },
+};
+
+static struct spear_modemux i2c0_modemux[] = {
+        {
+                .muxregs = i2c0_muxreg,
+                .nmuxregs = ARRAY_SIZE(i2c0_muxreg),
+        },
+};
+
+static struct spear_pingroup i2c0_pingroup = {
+        .name = "i2c0_grp",
+        .pins = i2c0_pins,
+        .npins = ARRAY_SIZE(i2c0_pins),
+        .modemuxs = i2c0_modemux,
+        .nmodemuxs = ARRAY_SIZE(i2c0_modemux),
+};
+
+static const char *const i2c0_grps[] = { "i2c0_grp" };
+static struct spear_function i2c0_function = {
+        .name = "i2c0",
+        .groups = i2c0_grps,
+        .ngroups = ARRAY_SIZE(i2c0_grps),
+};
+
+/* pad multiplexing for i2c1 device */
+static const unsigned i2c1_pins[] = { 18, 23 };
+static struct spear_muxreg i2c1_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_1,
+                .mask = I2C1_REG0_MASK,
+                .val = I2C1_REG0_MASK,
+        },
+};
+
+static struct spear_modemux i2c1_modemux[] = {
+        {
+                .muxregs = i2c1_muxreg,
+                .nmuxregs = ARRAY_SIZE(i2c1_muxreg),
+        },
+};
+
+static struct spear_pingroup i2c1_pingroup = {
+        .name = "i2c1_grp",
+        .pins = i2c1_pins,
+        .npins = ARRAY_SIZE(i2c1_pins),
+        .modemuxs = i2c1_modemux,
+        .nmodemuxs = ARRAY_SIZE(i2c1_modemux),
+};
+
+static const char *const i2c1_grps[] = { "i2c1_grp" };
+static struct spear_function i2c1_function = {
+        .name = "i2c1",
+        .groups = i2c1_grps,
+        .ngroups = ARRAY_SIZE(i2c1_grps),
+};
+
+/* pad multiplexing for cec0 device */
+static const unsigned cec0_pins[] = { 135 };
+static struct spear_muxreg cec0_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_5,
+                .mask = CEC0_REG4_MASK,
+                .val = CEC0_REG4_MASK,
+        },
+};
+
+static struct spear_modemux cec0_modemux[] = {
+        {
+                .muxregs = cec0_muxreg,
+                .nmuxregs = ARRAY_SIZE(cec0_muxreg),
+        },
+};
+
+static struct spear_pingroup cec0_pingroup = {
+        .name = "cec0_grp",
+        .pins = cec0_pins,
+        .npins = ARRAY_SIZE(cec0_pins),
+        .modemuxs = cec0_modemux,
+        .nmodemuxs = ARRAY_SIZE(cec0_modemux),
+};
+
+static const char *const cec0_grps[] = { "cec0_grp" };
+static struct spear_function cec0_function = {
+        .name = "cec0",
+        .groups = cec0_grps,
+        .ngroups = ARRAY_SIZE(cec0_grps),
+};
+
+/* pad multiplexing for cec1 device */
+static const unsigned cec1_pins[] = { 136 };
+static struct spear_muxreg cec1_muxreg[] = {
+        {
+                .reg = PAD_FUNCTION_EN_5,
+                .mask = CEC1_REG4_MASK,
+                .val = CEC1_REG4_MASK,
+        },
+};
+
+static struct spear_modemux cec1_modemux[] = {
+        {
+                .muxregs = cec1_muxreg,
+                .nmuxregs = ARRAY_SIZE(cec1_muxreg),
+        },
+};
+
+static struct spear_pingroup cec1_pingroup = {
+        .name = "cec1_grp",
+        .pins = cec1_pins,
+        .npins = ARRAY_SIZE(cec1_pins),
+        .modemuxs = cec1_modemux,
+        .nmodemuxs = ARRAY_SIZE(cec1_modemux),
+};
+
+static const char *const cec1_grps[] = { "cec1_grp" };
+static struct spear_function cec1_function = {
+        .name = "cec1",
+        .groups = cec1_grps,
+        .ngroups = ARRAY_SIZE(cec1_grps),
+};
+
+/* pad multiplexing for mcif devices */
+static const unsigned mcif_pins[] = { 193, 194, 195, 196, 197, 198, 199, 200,
+        201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214,
+        215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228,
+        229, 230, 231, 232, 237 };
+#define MCIF_MUXREG                                                     \
+        {                                                               \
+                .reg = PAD_SHARED_IP_EN_1,                              \
+                .mask = MCIF_MASK,                                      \
+                .val = MCIF_MASK,                                       \
+        }, {                                                            \
+                .reg = PAD_FUNCTION_EN_7,                               \
+                .mask = FSMC_PNOR_AND_MCIF_REG6_MASK | MCIF_REG6_MASK,  \
+                .val = FSMC_PNOR_AND_MCIF_REG6_MASK | MCIF_REG6_MASK,   \
+        }, {                                                            \
+                .reg = PAD_FUNCTION_EN_8,                               \
+                .mask = MCIF_REG7_MASK,                                 \
+                .val = MCIF_REG7_MASK,                                  \
+        }
+
+/* Pad multiplexing for sdhci device */
+static struct spear_muxreg sdhci_muxreg[] = {
+        MCIF_MUXREG,
+        {
+                .reg = PERIP_CFG,
+                .mask = MCIF_SEL_MASK,
+                .val = MCIF_SEL_SD,
+        },
+};
+
+static struct spear_modemux sdhci_modemux[] = {
+        {
+                .muxregs = sdhci_muxreg,
+                .nmuxregs = ARRAY_SIZE(sdhci_muxreg),
+        },
+};
+
+static struct spear_pingroup sdhci_pingroup = {
+        .name = "sdhci_grp",
+        .pins = mcif_pins,
+        .npins = ARRAY_SIZE(mcif_pins),
+        .modemuxs = sdhci_modemux,
+        .nmodemuxs = ARRAY_SIZE(sdhci_modemux),
+};
+
+static const char *const sdhci_grps[] = { "sdhci_grp" };
+static struct spear_function sdhci_function = {
+        .name = "sdhci",
+        .groups = sdhci_grps,
+        .ngroups = ARRAY_SIZE(sdhci_grps),
+};
+
+/* Pad multiplexing for cf device */
+static struct spear_muxreg cf_muxreg[] = {
+        MCIF_MUXREG,
+        {
+                .reg = PERIP_CFG,
+                .mask = MCIF_SEL_MASK,
+                .val = MCIF_SEL_CF,
+        },
+};
+
+static struct spear_modemux cf_modemux[] = {
+        {
+                .muxregs = cf_muxreg,
+                .nmuxregs = ARRAY_SIZE(cf_muxreg),
+        },
+};
+
+static struct spear_pingroup cf_pingroup = {
+        .name = "cf_grp",
+        .pins = mcif_pins,
+        .npins = ARRAY_SIZE(mcif_pins),
+        .modemuxs = cf_modemux,
+        .nmodemuxs = ARRAY_SIZE(cf_modemux),
+};
+
+static const char *const cf_grps[] = { "cf_grp" };
+static struct spear_function cf_function = {
+        .name = "cf",
+        .groups = cf_grps,
+        .ngroups = ARRAY_SIZE(cf_grps),
+};
+
+/* Pad multiplexing for xd device */
+static struct spear_muxreg xd_muxreg[] = {
+        MCIF_MUXREG,
+        {
+                .reg = PERIP_CFG,
+                .mask = MCIF_SEL_MASK,
+                .val = MCIF_SEL_XD,
+        },
+};
+
+static struct spear_modemux xd_modemux[] = {
+        {
+                .muxregs = xd_muxreg,
+                .nmuxregs = ARRAY_SIZE(xd_muxreg),
+        },
+};
+
+static struct spear_pingroup xd_pingroup = {
+        .name = "xd_grp",
+        .pins = mcif_pins,
+        .npins = ARRAY_SIZE(mcif_pins),
+        .modemuxs = xd_modemux,
+        .nmodemuxs = ARRAY_SIZE(xd_modemux),
+};
+
+static const char *const xd_grps[] = { "xd_grp" };
+static struct spear_function xd_function = {
+        .name = "xd",
+        .groups = xd_grps,
+        .ngroups = ARRAY_SIZE(xd_grps),
+};
+
+/* pad multiplexing for clcd device */
+static const unsigned clcd_pins[] = { 138, 139, 140, 141, 142, 143, 144, 145,
+        146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159,
+        160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173,
+        174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187,
+        188, 189, 190, 191 };
+static struct spear_muxreg clcd_muxreg[] = {
+        {
+                .reg = PAD_SHARED_IP_EN_1,
+                .mask = ARM_TRACE_MASK | MIPHY_DBG_MASK,
+                .val = 0,
+        }, {
+                .reg = PAD_FUNCTION_EN_5,
+                .mask = CLCD_REG4_MASK | CLCD_AND_ARM_TRACE_REG4_MASK,
+                .val = CLCD_REG4_MASK | CLCD_AND_ARM_TRACE_REG4_MASK,
+        }, {
+                .reg = PAD_FUNCTION_EN_6,
+                .mask = CLCD_AND_ARM_TRACE_REG5_MASK,
+                .val = CLCD_AND_ARM_TRACE_REG5_MASK,
+        }, {
+                .reg = PAD_FUNCTION_EN_7,
+                .mask = CLCD_AND_ARM_TRACE_REG6_MASK,
+                .val = CLCD_AND_ARM_TRACE_REG6_MASK,
+        },
+};
+
+static struct spear_modemux clcd_modemux[] = {
+        {
+                .muxregs = clcd_muxreg,
+                .nmuxregs = ARRAY_SIZE(clcd_muxreg),
+        },
+};
+
+static struct spear_pingroup clcd_pingroup = {
+        .name = "clcd_grp",
+        .pins = clcd_pins,
+        .npins = ARRAY_SIZE(clcd_pins),
+        .modemuxs = clcd_modemux,
+        .nmodemuxs = ARRAY_SIZE(clcd_modemux),
+};
+
+static const char *const clcd_grps[] = { "clcd_grp" };
+static struct spear_function clcd_function = {
+        .name = "clcd",
+        .groups = clcd_grps,
+        .ngroups = ARRAY_SIZE(clcd_grps),
+};
+
+/* pad multiplexing for arm_trace device */
+static const unsigned arm_trace_pins[] = { 158, 159, 160, 161, 162, 163, 164,
+        165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178,
+        179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192,
+        193, 194, 195, 196, 197, 198, 199, 200 };
+static struct spear_muxreg arm_trace_muxreg[] = {
+        {
+                .reg = PAD_SHARED_IP_EN_1,
+                .mask = ARM_TRACE_MASK,
+                .val = ARM_TRACE_MASK,
+        }, {
+                .reg = PAD_FUNCTION_EN_5,
+                .mask = CLCD_AND_ARM_TRACE_REG4_MASK,
+                .val = CLCD_AND_ARM_TRACE_REG4_MASK,
+        }, {
+                .reg = PAD_FUNCTION_EN_6,
+                .mask = CLCD_AND_ARM_TRACE_REG5_MASK,
+                .val = CLCD_AND_ARM_TRACE_REG5_MASK,
+        }, {
+                .reg = PAD_FUNCTION_EN_7,
+                .mask = CLCD_AND_ARM_TRACE_REG6_MASK,
+                .val = CLCD_AND_ARM_TRACE_REG6_MASK,
+        },
+};
+
+static struct spear_modemux arm_trace_modemux[] = {
+        {
+                .muxregs = arm_trace_muxreg,
+                .nmuxregs = ARRAY_SIZE(arm_trace_muxreg),
+        },
+};
+
+static struct spear_pingroup arm_trace_pingroup = {
+        .name = "arm_trace_grp",
+        .pins = arm_trace_pins,
+        .npins = ARRAY_SIZE(arm_trace_pins),
+        .modemuxs = arm_trace_modemux,
+        .nmodemuxs = ARRAY_SIZE(arm_trace_modemux),
+};
+
+static const char *const arm_trace_grps[] = { "arm_trace_grp" };
+static struct spear_function arm_trace_function = {
+        .name = "arm_trace",
+        .groups = arm_trace_grps,
+        .ngroups = ARRAY_SIZE(arm_trace_grps),
+};
+
+/* pad multiplexing for miphy_dbg device */
+static const unsigned miphy_dbg_pins[] = { 96, 97, 98, 99, 100, 101, 102, 103,
+        132, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147,
+        148, 149, 150, 151, 152, 153, 154, 155, 156, 157 };
+static struct spear_muxreg miphy_dbg_muxreg[] = {
+        {
+                .reg = PAD_SHARED_IP_EN_1,
+                .mask = MIPHY_DBG_MASK,
+                .val = MIPHY_DBG_MASK,
+        }, {
+                .reg = PAD_FUNCTION_EN_5,
+                .mask = DEVS_GRP_AND_MIPHY_DBG_REG4_MASK,
+                .val = DEVS_GRP_AND_MIPHY_DBG_REG4_MASK,
+        },
+};
+
+static struct spear_modemux miphy_dbg_modemux[] = {
+        {
+                .muxregs = miphy_dbg_muxreg,
+                .nmuxregs = ARRAY_SIZE(miphy_dbg_muxreg),
+        },
+};
+
+static struct spear_pingroup miphy_dbg_pingroup = {
+        .name = "miphy_dbg_grp",
+        .pins = miphy_dbg_pins,
+        .npins = ARRAY_SIZE(miphy_dbg_pins),
+        .modemuxs = miphy_dbg_modemux,
+        .nmodemuxs = ARRAY_SIZE(miphy_dbg_modemux),
+};
+
+static const char *const miphy_dbg_grps[] = { "miphy_dbg_grp" };
+static struct spear_function miphy_dbg_function = {
+        .name = "miphy_dbg",
+        .groups = miphy_dbg_grps,
+        .ngroups = ARRAY_SIZE(miphy_dbg_grps),
+};
+
+/* pad multiplexing for pcie device */
+static const unsigned pcie_pins[] = { 250 };
+static struct spear_muxreg pcie_muxreg[] = {
+        {
+                .reg = PCIE_SATA_CFG,
+                .mask = SATA_PCIE_CFG_MASK,
+                .val = PCIE_CFG_VAL,
+        },
+};
+
+static struct spear_modemux pcie_modemux[] = {
+        {
+                .muxregs = pcie_muxreg,
+                .nmuxregs = ARRAY_SIZE(pcie_muxreg),
+        },
+};
+
+static struct spear_pingroup pcie_pingroup = {
+        .name = "pcie_grp",
+        .pins = pcie_pins,
+        .npins = ARRAY_SIZE(pcie_pins),
+        .modemuxs = pcie_modemux,
+        .nmodemuxs = ARRAY_SIZE(pcie_modemux),
+};
+
+static const char *const pcie_grps[] = { "pcie_grp" };
+static struct spear_function pcie_function = {
+        .name = "pcie",
+        .groups = pcie_grps,
+        .ngroups = ARRAY_SIZE(pcie_grps),
+};
+
+/* pad multiplexing for sata device */
+static const unsigned sata_pins[] = { 250 };
+static struct spear_muxreg sata_muxreg[] = {
+        {
+                .reg = PCIE_SATA_CFG,
+                .mask = SATA_PCIE_CFG_MASK,
+                .val = SATA_CFG_VAL,
+        },
+};
+
+static struct spear_modemux sata_modemux[] = {
+        {
+                .muxregs = sata_muxreg,
+                .nmuxregs = ARRAY_SIZE(sata_muxreg),
+        },
+};
+
+static struct spear_pingroup sata_pingroup = {
+        .name = "sata_grp",
+        .pins = sata_pins,
+        .npins = ARRAY_SIZE(sata_pins),
+        .modemuxs = sata_modemux,
+        .nmodemuxs = ARRAY_SIZE(sata_modemux),
+};
+
+static const char *const sata_grps[] = { "sata_grp" };
+static struct spear_function sata_function = {
+        .name = "sata",
+        .groups = sata_grps,
+        .ngroups = ARRAY_SIZE(sata_grps),
+};
+
+/* pingroups */
+static struct spear_pingroup *spear1340_pingroups[] = {
+        &pads_as_gpio_pingroup,
+        &fsmc_8bit_pingroup,
+        &fsmc_16bit_pingroup,
+        &fsmc_pnor_pingroup,
+        &keyboard_row_col_pingroup,
+        &keyboard_col5_pingroup,
+        &spdif_in_pingroup,
+        &spdif_out_pingroup,
+        &gpt_0_1_pingroup,
+        &pwm0_pingroup,
+        &pwm1_pingroup,
+        &pwm2_pingroup,
+        &pwm3_pingroup,
+        &vip_mux_pingroup,
+        &vip_mux_cam0_pingroup,
+        &vip_mux_cam1_pingroup,
+        &vip_mux_cam2_pingroup,
+        &vip_mux_cam3_pingroup,
+        &cam0_pingroup,
+        &cam1_pingroup,
+        &cam2_pingroup,
+        &cam3_pingroup,
+        &smi_pingroup,
+        &ssp0_pingroup,
+        &ssp0_cs1_pingroup,
+        &ssp0_cs2_pingroup,
+        &ssp0_cs3_pingroup,
+        &uart0_pingroup,
+        &uart0_enh_pingroup,
+        &uart1_pingroup,
+        &i2s_in_pingroup,
+        &i2s_out_pingroup,
+        &gmii_pingroup,
+        &rgmii_pingroup,
+        &rmii_pingroup,
+        &sgmii_pingroup,
+        &i2c0_pingroup,
+        &i2c1_pingroup,
+        &cec0_pingroup,
+        &cec1_pingroup,
+        &sdhci_pingroup,
+        &cf_pingroup,
+        &xd_pingroup,
+        &clcd_pingroup,
+        &arm_trace_pingroup,
+        &miphy_dbg_pingroup,
+        &pcie_pingroup,
+        &sata_pingroup,
+};
+
+/* functions */
+static struct spear_function *spear1340_functions[] = {
+        &pads_as_gpio_function,
+        &fsmc_function,
+        &keyboard_function,
+        &spdif_in_function,
+        &spdif_out_function,
+        &gpt_0_1_function,
+        &pwm_function,
+        &vip_function,
+        &cam0_function,
+        &cam1_function,
+        &cam2_function,
+        &cam3_function,
+        &smi_function,
+        &ssp0_function,
+        &uart0_function,
+        &uart1_function,
+        &i2s_function,
+        &gmac_function,
+        &i2c0_function,
+        &i2c1_function,
+        &cec0_function,
+        &cec1_function,
+        &sdhci_function,
+        &cf_function,
+        &xd_function,
+        &clcd_function,
+        &arm_trace_function,
+        &miphy_dbg_function,
+        &pcie_function,
+        &sata_function,
+};
+
+static struct spear_pinctrl_machdata spear1340_machdata = {
+        .pins = spear1340_pins,
+        .npins = ARRAY_SIZE(spear1340_pins),
+        .groups = spear1340_pingroups,
+        .ngroups = ARRAY_SIZE(spear1340_pingroups),
+        .functions = spear1340_functions,
+        .nfunctions = ARRAY_SIZE(spear1340_functions),
+        .modes_supported = false,
+};
+
+static struct of_device_id spear1340_pinctrl_of_match[] __devinitdata = {
+        {
+                .compatible = "st,spear1340-pinmux",
+        },
+        {},
+};
+
+static int __devinit spear1340_pinctrl_probe(struct platform_device *pdev)
+{
+        return spear_pinctrl_probe(pdev, &spear1340_machdata);
+}
+
+static int __devexit spear1340_pinctrl_remove(struct platform_device *pdev)
+{
+        return spear_pinctrl_remove(pdev);
+}
+
+static struct platform_driver spear1340_pinctrl_driver = {
+        .driver = {
+                .name = DRIVER_NAME,
+                .owner = THIS_MODULE,
+                .of_match_table = spear1340_pinctrl_of_match,
+        },
+        .probe = spear1340_pinctrl_probe,
+        .remove = __devexit_p(spear1340_pinctrl_remove),
+};
+
+static int __init spear1340_pinctrl_init(void)
+{
+        return platform_driver_register(&spear1340_pinctrl_driver);
+}
+arch_initcall(spear1340_pinctrl_init);
+
+static void __exit spear1340_pinctrl_exit(void)
+{
+        platform_driver_unregister(&spear1340_pinctrl_driver);
+}
+module_exit(spear1340_pinctrl_exit);
+
+MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>");
+MODULE_DESCRIPTION("ST Microelectronics SPEAr1340 pinctrl driver");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, spear1340_pinctrl_of_match);
diff --git a/drivers/pinctrl/spear/pinctrl-spear300.c b/drivers/pinctrl/spear/pinctrl-spear300.c
new file mode 100644
index 000000000000..9c82a35e4e78
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear300.c
@@ -0,0 +1,708 @@
+/*
+ * Driver for the ST Microelectronics SPEAr300 pinmux
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include "pinctrl-spear3xx.h"
+
+#define DRIVER_NAME "spear300-pinmux"
+
+/* addresses */
+#define PMX_CONFIG_REG                  0x00
+#define MODE_CONFIG_REG                 0x04
+
+/* modes */
+#define NAND_MODE                       (1 << 0)
+#define NOR_MODE                        (1 << 1)
+#define PHOTO_FRAME_MODE                (1 << 2)
+#define LEND_IP_PHONE_MODE              (1 << 3)
+#define HEND_IP_PHONE_MODE              (1 << 4)
+#define LEND_WIFI_PHONE_MODE            (1 << 5)
+#define HEND_WIFI_PHONE_MODE            (1 << 6)
+#define ATA_PABX_WI2S_MODE              (1 << 7)
+#define ATA_PABX_I2S_MODE               (1 << 8)
+#define CAML_LCDW_MODE                  (1 << 9)
+#define CAMU_LCD_MODE                   (1 << 10)
+#define CAMU_WLCD_MODE                  (1 << 11)
+#define CAML_LCD_MODE                   (1 << 12)
+
+static struct spear_pmx_mode pmx_mode_nand = {
+        .name = "nand",
+        .mode = NAND_MODE,
+        .reg = MODE_CONFIG_REG,
+        .mask = 0x0000000F,
+        .val = 0x00,
+};
+
+static struct spear_pmx_mode pmx_mode_nor = {
+        .name = "nor",
+        .mode = NOR_MODE,
+        .reg = MODE_CONFIG_REG,
+        .mask = 0x0000000F,
+        .val = 0x01,
+};
+
+static struct spear_pmx_mode pmx_mode_photo_frame = {
+        .name = "photo frame mode",
+        .mode = PHOTO_FRAME_MODE,
+        .reg = MODE_CONFIG_REG,
+        .mask = 0x0000000F,
+        .val = 0x02,
+};
+
+static struct spear_pmx_mode pmx_mode_lend_ip_phone = {
+        .name = "lend ip phone mode",
+        .mode = LEND_IP_PHONE_MODE,
+        .reg = MODE_CONFIG_REG,
+        .mask = 0x0000000F,
+        .val = 0x03,
+};
+
+static struct spear_pmx_mode pmx_mode_hend_ip_phone = {
+        .name = "hend ip phone mode",
+        .mode = HEND_IP_PHONE_MODE,
+        .reg = MODE_CONFIG_REG,
+        .mask = 0x0000000F,
+        .val = 0x04,
+};
+
+static struct spear_pmx_mode pmx_mode_lend_wifi_phone = {
+        .name = "lend wifi phone mode",
+        .mode = LEND_WIFI_PHONE_MODE,
+        .reg = MODE_CONFIG_REG,
+        .mask = 0x0000000F,
+        .val = 0x05,
+};
+
+static struct spear_pmx_mode pmx_mode_hend_wifi_phone = {
+        .name = "hend wifi phone mode",
+        .mode = HEND_WIFI_PHONE_MODE,
+        .reg = MODE_CONFIG_REG,
+        .mask = 0x0000000F,
+        .val = 0x06,
+};
+
+static struct spear_pmx_mode pmx_mode_ata_pabx_wi2s = {
+        .name = "ata pabx wi2s mode",
+        .mode = ATA_PABX_WI2S_MODE,
+        .reg = MODE_CONFIG_REG,
+        .mask = 0x0000000F,
+        .val = 0x07,
+};
+
+static struct spear_pmx_mode pmx_mode_ata_pabx_i2s = {
+        .name = "ata pabx i2s mode",
+        .mode = ATA_PABX_I2S_MODE,
+        .reg = MODE_CONFIG_REG,
+        .mask = 0x0000000F,
+        .val = 0x08,
+};
+
+static struct spear_pmx_mode pmx_mode_caml_lcdw = {
+        .name = "caml lcdw mode",
+        .mode = CAML_LCDW_MODE,
+        .reg = MODE_CONFIG_REG,
+        .mask = 0x0000000F,
+        .val = 0x0C,
+};
+
+static struct spear_pmx_mode pmx_mode_camu_lcd = {
+        .name = "camu lcd mode",
+        .mode = CAMU_LCD_MODE,
+        .reg = MODE_CONFIG_REG,
+        .mask = 0x0000000F,
+        .val = 0x0D,
+};
+
+static struct spear_pmx_mode pmx_mode_camu_wlcd = {
+        .name = "camu wlcd mode",
+        .mode = CAMU_WLCD_MODE,
+        .reg = MODE_CONFIG_REG,
+        .mask = 0x0000000F,
+        .val = 0xE,
+};
+
+static struct spear_pmx_mode pmx_mode_caml_lcd = {
+        .name = "caml lcd mode",
+        .mode = CAML_LCD_MODE,
+        .reg = MODE_CONFIG_REG,
+        .mask = 0x0000000F,
+        .val = 0x0F,
+};
+
+static struct spear_pmx_mode *spear300_pmx_modes[] = {
+        &pmx_mode_nand,
+        &pmx_mode_nor,
+        &pmx_mode_photo_frame,
+        &pmx_mode_lend_ip_phone,
+        &pmx_mode_hend_ip_phone,
+        &pmx_mode_lend_wifi_phone,
+        &pmx_mode_hend_wifi_phone,
+        &pmx_mode_ata_pabx_wi2s,
+        &pmx_mode_ata_pabx_i2s,
+        &pmx_mode_caml_lcdw,
+        &pmx_mode_camu_lcd,
+        &pmx_mode_camu_wlcd,
+        &pmx_mode_caml_lcd,
+};
+
+/* fsmc_2chips_pins */
+static const unsigned fsmc_2chips_pins[] = { 1, 97 };
+static struct spear_muxreg fsmc_2chips_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_FIRDA_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux fsmc_2chips_modemux[] = {
+        {
+                .modes = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
+                        ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
+                .muxregs = fsmc_2chips_muxreg,
+                .nmuxregs = ARRAY_SIZE(fsmc_2chips_muxreg),
+        },
+};
+
+static struct spear_pingroup fsmc_2chips_pingroup = {
+        .name = "fsmc_2chips_grp",
+        .pins = fsmc_2chips_pins,
+        .npins = ARRAY_SIZE(fsmc_2chips_pins),
+        .modemuxs = fsmc_2chips_modemux,
+        .nmodemuxs = ARRAY_SIZE(fsmc_2chips_modemux),
+};
+
+/* fsmc_4chips_pins */
+static const unsigned fsmc_4chips_pins[] = { 1, 2, 3, 97 };
+static struct spear_muxreg fsmc_4chips_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_FIRDA_MASK | PMX_UART0_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux fsmc_4chips_modemux[] = {
+        {
+                .modes = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
+                        ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
+                .muxregs = fsmc_4chips_muxreg,
+                .nmuxregs = ARRAY_SIZE(fsmc_4chips_muxreg),
+        },
+};
+
+static struct spear_pingroup fsmc_4chips_pingroup = {
+        .name = "fsmc_4chips_grp",
+        .pins = fsmc_4chips_pins,
+        .npins = ARRAY_SIZE(fsmc_4chips_pins),
+        .modemuxs = fsmc_4chips_modemux,
+        .nmodemuxs = ARRAY_SIZE(fsmc_4chips_modemux),
+};
+
+static const char *const fsmc_grps[] = { "fsmc_2chips_grp", "fsmc_4chips_grp"
+};
+static struct spear_function fsmc_function = {
+        .name = "fsmc",
+        .groups = fsmc_grps,
+        .ngroups = ARRAY_SIZE(fsmc_grps),
+};
+
+/* clcd_lcdmode_pins */
+static const unsigned clcd_lcdmode_pins[] = { 49, 50 };
+static struct spear_muxreg clcd_lcdmode_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux clcd_lcdmode_modemux[] = {
+        {
+                .modes = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE |
+                        CAMU_LCD_MODE | CAML_LCD_MODE,
+                .muxregs = clcd_lcdmode_muxreg,
+                .nmuxregs = ARRAY_SIZE(clcd_lcdmode_muxreg),
+        },
+};
+
+static struct spear_pingroup clcd_lcdmode_pingroup = {
+        .name = "clcd_lcdmode_grp",
+        .pins = clcd_lcdmode_pins,
+        .npins = ARRAY_SIZE(clcd_lcdmode_pins),
+        .modemuxs = clcd_lcdmode_modemux,
+        .nmodemuxs = ARRAY_SIZE(clcd_lcdmode_modemux),
+};
+
+/* clcd_pfmode_pins */
+static const unsigned clcd_pfmode_pins[] = { 47, 48, 49, 50 };
+static struct spear_muxreg clcd_pfmode_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_TIMER_2_3_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux clcd_pfmode_modemux[] = {
+        {
+                .modes = PHOTO_FRAME_MODE,
+                .muxregs = clcd_pfmode_muxreg,
+                .nmuxregs = ARRAY_SIZE(clcd_pfmode_muxreg),
+        },
+};
+
+static struct spear_pingroup clcd_pfmode_pingroup = {
+        .name = "clcd_pfmode_grp",
+        .pins = clcd_pfmode_pins,
+        .npins = ARRAY_SIZE(clcd_pfmode_pins),
+        .modemuxs = clcd_pfmode_modemux,
+        .nmodemuxs = ARRAY_SIZE(clcd_pfmode_modemux),
+};
+
+static const char *const clcd_grps[] = { "clcd_lcdmode_grp", "clcd_pfmode_grp"
+};
+static struct spear_function clcd_function = {
+        .name = "clcd",
+        .groups = clcd_grps,
+        .ngroups = ARRAY_SIZE(clcd_grps),
+};
+
+/* tdm_pins */
+static const unsigned tdm_pins[] = { 34, 35, 36, 37, 38 };
+static struct spear_muxreg tdm_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux tdm_modemux[] = {
+        {
+                .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
+                        HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE
+                        | HEND_WIFI_PHONE_MODE | ATA_PABX_WI2S_MODE
+                        | ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
+                        | CAMU_WLCD_MODE | CAML_LCD_MODE,
+                .muxregs = tdm_muxreg,
+                .nmuxregs = ARRAY_SIZE(tdm_muxreg),
+        },
+};
+
+static struct spear_pingroup tdm_pingroup = {
+        .name = "tdm_grp",
+        .pins = tdm_pins,
+        .npins = ARRAY_SIZE(tdm_pins),
+        .modemuxs = tdm_modemux,
+        .nmodemuxs = ARRAY_SIZE(tdm_modemux),
+};
+
+static const char *const tdm_grps[] = { "tdm_grp" };
+static struct spear_function tdm_function = {
+        .name = "tdm",
+        .groups = tdm_grps,
+        .ngroups = ARRAY_SIZE(tdm_grps),
+};
+
+/* i2c_clk_pins */
+static const unsigned i2c_clk_pins[] = { 45, 46, 47, 48 };
+static struct spear_muxreg i2c_clk_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux i2c_clk_modemux[] = {
+        {
+                .modes = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
+                        LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
+                        ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE | CAML_LCDW_MODE
+                        | CAML_LCD_MODE,
+                .muxregs = i2c_clk_muxreg,
+                .nmuxregs = ARRAY_SIZE(i2c_clk_muxreg),
+        },
+};
+
+static struct spear_pingroup i2c_clk_pingroup = {
+        .name = "i2c_clk_grp_grp",
+        .pins = i2c_clk_pins,
+        .npins = ARRAY_SIZE(i2c_clk_pins),
+        .modemuxs = i2c_clk_modemux,
+        .nmodemuxs = ARRAY_SIZE(i2c_clk_modemux),
+};
+
+static const char *const i2c_grps[] = { "i2c_clk_grp" };
+static struct spear_function i2c_function = {
+        .name = "i2c1",
+        .groups = i2c_grps,
+        .ngroups = ARRAY_SIZE(i2c_grps),
+};
+
+/* caml_pins */
+static const unsigned caml_pins[] = { 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 };
+static struct spear_muxreg caml_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_MII_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux caml_modemux[] = {
+        {
+                .modes = CAML_LCDW_MODE | CAML_LCD_MODE,
+                .muxregs = caml_muxreg,
+                .nmuxregs = ARRAY_SIZE(caml_muxreg),
+        },
+};
+
+static struct spear_pingroup caml_pingroup = {
+        .name = "caml_grp",
+        .pins = caml_pins,
+        .npins = ARRAY_SIZE(caml_pins),
+        .modemuxs = caml_modemux,
+        .nmodemuxs = ARRAY_SIZE(caml_modemux),
+};
+
+/* camu_pins */
+static const unsigned camu_pins[] = { 16, 17, 18, 19, 20, 21, 45, 46, 47, 48 };
+static struct spear_muxreg camu_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK | PMX_MII_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux camu_modemux[] = {
+        {
+                .modes = CAMU_LCD_MODE | CAMU_WLCD_MODE,
+                .muxregs = camu_muxreg,
+                .nmuxregs = ARRAY_SIZE(camu_muxreg),
+        },
+};
+
+static struct spear_pingroup camu_pingroup = {
+        .name = "camu_grp",
+        .pins = camu_pins,
+        .npins = ARRAY_SIZE(camu_pins),
+        .modemuxs = camu_modemux,
+        .nmodemuxs = ARRAY_SIZE(camu_modemux),
+};
+
+static const char *const cam_grps[] = { "caml_grp", "camu_grp" };
+static struct spear_function cam_function = {
+        .name = "cam",
+        .groups = cam_grps,
+        .ngroups = ARRAY_SIZE(cam_grps),
+};
+
+/* dac_pins */
+static const unsigned dac_pins[] = { 43, 44 };
+static struct spear_muxreg dac_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_TIMER_0_1_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux dac_modemux[] = {
+        {
+                .modes = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
+                        | CAMU_WLCD_MODE | CAML_LCD_MODE,
+                .muxregs = dac_muxreg,
+                .nmuxregs = ARRAY_SIZE(dac_muxreg),
+        },
+};
+
+static struct spear_pingroup dac_pingroup = {
+        .name = "dac_grp",
+        .pins = dac_pins,
+        .npins = ARRAY_SIZE(dac_pins),
+        .modemuxs = dac_modemux,
+        .nmodemuxs = ARRAY_SIZE(dac_modemux),
+};
+
+static const char *const dac_grps[] = { "dac_grp" };
+static struct spear_function dac_function = {
+        .name = "dac",
+        .groups = dac_grps,
+        .ngroups = ARRAY_SIZE(dac_grps),
+};
+
+/* i2s_pins */
+static const unsigned i2s_pins[] = { 39, 40, 41, 42 };
+static struct spear_muxreg i2s_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_UART0_MODEM_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux i2s_modemux[] = {
+        {
+                .modes = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE
+                        | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
+                        ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
+                        | CAMU_WLCD_MODE | CAML_LCD_MODE,
+                .muxregs = i2s_muxreg,
+                .nmuxregs = ARRAY_SIZE(i2s_muxreg),
+        },
+};
+
+static struct spear_pingroup i2s_pingroup = {
+        .name = "i2s_grp",
+        .pins = i2s_pins,
+        .npins = ARRAY_SIZE(i2s_pins),
+        .modemuxs = i2s_modemux,
+        .nmodemuxs = ARRAY_SIZE(i2s_modemux),
+};
+
+static const char *const i2s_grps[] = { "i2s_grp" };
+static struct spear_function i2s_function = {
+        .name = "i2s",
+        .groups = i2s_grps,
+        .ngroups = ARRAY_SIZE(i2s_grps),
+};
+
+/* sdhci_4bit_pins */
+static const unsigned sdhci_4bit_pins[] = { 28, 29, 30, 31, 32, 33 };
+static struct spear_muxreg sdhci_4bit_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
+                        PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
+                        PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux sdhci_4bit_modemux[] = {
+        {
+                .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
+                        HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
+                        HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
+                        CAMU_WLCD_MODE | CAML_LCD_MODE | ATA_PABX_WI2S_MODE,
+                .muxregs = sdhci_4bit_muxreg,
+                .nmuxregs = ARRAY_SIZE(sdhci_4bit_muxreg),
+        },
+};
+
+static struct spear_pingroup sdhci_4bit_pingroup = {
+        .name = "sdhci_4bit_grp",
+        .pins = sdhci_4bit_pins,
+        .npins = ARRAY_SIZE(sdhci_4bit_pins),
+        .modemuxs = sdhci_4bit_modemux,
+        .nmodemuxs = ARRAY_SIZE(sdhci_4bit_modemux),
+};
+
+/* sdhci_8bit_pins */
+static const unsigned sdhci_8bit_pins[] = { 24, 25, 26, 27, 28, 29, 30, 31, 32,
+        33 };
+static struct spear_muxreg sdhci_8bit_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
+                        PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
+                        PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux sdhci_8bit_modemux[] = {
+        {
+                .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
+                        HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
+                        HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
+                        CAMU_WLCD_MODE | CAML_LCD_MODE,
+                .muxregs = sdhci_8bit_muxreg,
+                .nmuxregs = ARRAY_SIZE(sdhci_8bit_muxreg),
+        },
+};
+
+static struct spear_pingroup sdhci_8bit_pingroup = {
+        .name = "sdhci_8bit_grp",
+        .pins = sdhci_8bit_pins,
+        .npins = ARRAY_SIZE(sdhci_8bit_pins),
+        .modemuxs = sdhci_8bit_modemux,
+        .nmodemuxs = ARRAY_SIZE(sdhci_8bit_modemux),
+};
+
+static const char *const sdhci_grps[] = { "sdhci_4bit_grp", "sdhci_8bit_grp" };
+static struct spear_function sdhci_function = {
+        .name = "sdhci",
+        .groups = sdhci_grps,
+        .ngroups = ARRAY_SIZE(sdhci_grps),
+};
+
+/* gpio1_0_to_3_pins */
+static const unsigned gpio1_0_to_3_pins[] = { 39, 40, 41, 42 };
+static struct spear_muxreg gpio1_0_to_3_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_UART0_MODEM_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux gpio1_0_to_3_modemux[] = {
+        {
+                .modes = PHOTO_FRAME_MODE,
+                .muxregs = gpio1_0_to_3_muxreg,
+                .nmuxregs = ARRAY_SIZE(gpio1_0_to_3_muxreg),
+        },
+};
+
+static struct spear_pingroup gpio1_0_to_3_pingroup = {
+        .name = "gpio1_0_to_3_grp",
+        .pins = gpio1_0_to_3_pins,
+        .npins = ARRAY_SIZE(gpio1_0_to_3_pins),
+        .modemuxs = gpio1_0_to_3_modemux,
+        .nmodemuxs = ARRAY_SIZE(gpio1_0_to_3_modemux),
+};
+
+/* gpio1_4_to_7_pins */
+static const unsigned gpio1_4_to_7_pins[] = { 43, 44, 45, 46 };
+
+static struct spear_muxreg gpio1_4_to_7_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux gpio1_4_to_7_modemux[] = {
+        {
+                .modes = PHOTO_FRAME_MODE,
+                .muxregs = gpio1_4_to_7_muxreg,
+                .nmuxregs = ARRAY_SIZE(gpio1_4_to_7_muxreg),
+        },
+};
+
+static struct spear_pingroup gpio1_4_to_7_pingroup = {
+        .name = "gpio1_4_to_7_grp",
+        .pins = gpio1_4_to_7_pins,
+        .npins = ARRAY_SIZE(gpio1_4_to_7_pins),
+        .modemuxs = gpio1_4_to_7_modemux,
+        .nmodemuxs = ARRAY_SIZE(gpio1_4_to_7_modemux),
+};
+
+static const char *const gpio1_grps[] = { "gpio1_0_to_3_grp", "gpio1_4_to_7_grp"
+};
+static struct spear_function gpio1_function = {
+        .name = "gpio1",
+        .groups = gpio1_grps,
+        .ngroups = ARRAY_SIZE(gpio1_grps),
+};
+
+/* pingroups */
+static struct spear_pingroup *spear300_pingroups[] = {
+        SPEAR3XX_COMMON_PINGROUPS,
+        &fsmc_2chips_pingroup,
+        &fsmc_4chips_pingroup,
+        &clcd_lcdmode_pingroup,
+        &clcd_pfmode_pingroup,
+        &tdm_pingroup,
+        &i2c_clk_pingroup,
+        &caml_pingroup,
+        &camu_pingroup,
+        &dac_pingroup,
+        &i2s_pingroup,
+        &sdhci_4bit_pingroup,
+        &sdhci_8bit_pingroup,
+        &gpio1_0_to_3_pingroup,
+        &gpio1_4_to_7_pingroup,
+};
+
+/* functions */
+static struct spear_function *spear300_functions[] = {
+        SPEAR3XX_COMMON_FUNCTIONS,
+        &fsmc_function,
+        &clcd_function,
+        &tdm_function,
+        &i2c_function,
+        &cam_function,
+        &dac_function,
+        &i2s_function,
+        &sdhci_function,
+        &gpio1_function,
+};
+
+static struct of_device_id spear300_pinctrl_of_match[] __devinitdata = {
+        {
+                .compatible = "st,spear300-pinmux",
+        },
+        {},
+};
+
+static int __devinit spear300_pinctrl_probe(struct platform_device *pdev)
+{
+        int ret;
+
+        spear3xx_machdata.groups = spear300_pingroups;
+        spear3xx_machdata.ngroups = ARRAY_SIZE(spear300_pingroups);
+        spear3xx_machdata.functions = spear300_functions;
+        spear3xx_machdata.nfunctions = ARRAY_SIZE(spear300_functions);
+
+        spear3xx_machdata.modes_supported = true;
+        spear3xx_machdata.pmx_modes = spear300_pmx_modes;
+        spear3xx_machdata.npmx_modes = ARRAY_SIZE(spear300_pmx_modes);
+
+        pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG);
+
+        ret = spear_pinctrl_probe(pdev, &spear3xx_machdata);
+        if (ret)
+                return ret;
+
+        return 0;
+}
+
+static int __devexit spear300_pinctrl_remove(struct platform_device *pdev)
+{
+        return spear_pinctrl_remove(pdev);
+}
+
+static struct platform_driver spear300_pinctrl_driver = {
+        .driver = {
+                .name = DRIVER_NAME,
+                .owner = THIS_MODULE,
+                .of_match_table = spear300_pinctrl_of_match,
+        },
+        .probe = spear300_pinctrl_probe,
+        .remove = __devexit_p(spear300_pinctrl_remove),
+};
+
+static int __init spear300_pinctrl_init(void)
+{
+        return platform_driver_register(&spear300_pinctrl_driver);
+}
+arch_initcall(spear300_pinctrl_init);
+
+static void __exit spear300_pinctrl_exit(void)
+{
+        platform_driver_unregister(&spear300_pinctrl_driver);
+}
+module_exit(spear300_pinctrl_exit);
+
+MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>");
+MODULE_DESCRIPTION("ST Microelectronics SPEAr300 pinctrl driver");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, spear300_pinctrl_of_match);
diff --git a/drivers/pinctrl/spear/pinctrl-spear310.c b/drivers/pinctrl/spear/pinctrl-spear310.c
new file mode 100644
index 000000000000..1a9707605125
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear310.c
@@ -0,0 +1,431 @@
+/*
+ * Driver for the ST Microelectronics SPEAr310 pinmux
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include "pinctrl-spear3xx.h"
+
+#define DRIVER_NAME "spear310-pinmux"
+
+/* addresses */
+#define PMX_CONFIG_REG                  0x08
+
+/* emi_cs_0_to_5_pins */
+static const unsigned emi_cs_0_to_5_pins[] = { 45, 46, 47, 48, 49, 50 };
+static struct spear_muxreg emi_cs_0_to_5_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux emi_cs_0_to_5_modemux[] = {
+        {
+                .muxregs = emi_cs_0_to_5_muxreg,
+                .nmuxregs = ARRAY_SIZE(emi_cs_0_to_5_muxreg),
+        },
+};
+
+static struct spear_pingroup emi_cs_0_to_5_pingroup = {
+        .name = "emi_cs_0_to_5_grp",
+        .pins = emi_cs_0_to_5_pins,
+        .npins = ARRAY_SIZE(emi_cs_0_to_5_pins),
+        .modemuxs = emi_cs_0_to_5_modemux,
+        .nmodemuxs = ARRAY_SIZE(emi_cs_0_to_5_modemux),
+};
+
+static const char *const emi_cs_0_to_5_grps[] = { "emi_cs_0_to_5_grp" };
+static struct spear_function emi_cs_0_to_5_function = {
+        .name = "emi",
+        .groups = emi_cs_0_to_5_grps,
+        .ngroups = ARRAY_SIZE(emi_cs_0_to_5_grps),
+};
+
+/* uart1_pins */
+static const unsigned uart1_pins[] = { 0, 1 };
+static struct spear_muxreg uart1_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_FIRDA_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux uart1_modemux[] = {
+        {
+                .muxregs = uart1_muxreg,
+                .nmuxregs = ARRAY_SIZE(uart1_muxreg),
+        },
+};
+
+static struct spear_pingroup uart1_pingroup = {
+        .name = "uart1_grp",
+        .pins = uart1_pins,
+        .npins = ARRAY_SIZE(uart1_pins),
+        .modemuxs = uart1_modemux,
+        .nmodemuxs = ARRAY_SIZE(uart1_modemux),
+};
+
+static const char *const uart1_grps[] = { "uart1_grp" };
+static struct spear_function uart1_function = {
+        .name = "uart1",
+        .groups = uart1_grps,
+        .ngroups = ARRAY_SIZE(uart1_grps),
+};
+
+/* uart2_pins */
+static const unsigned uart2_pins[] = { 43, 44 };
+static struct spear_muxreg uart2_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_TIMER_0_1_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux uart2_modemux[] = {
+        {
+                .muxregs = uart2_muxreg,
+                .nmuxregs = ARRAY_SIZE(uart2_muxreg),
+        },
+};
+
+static struct spear_pingroup uart2_pingroup = {
+        .name = "uart2_grp",
+        .pins = uart2_pins,
+        .npins = ARRAY_SIZE(uart2_pins),
+        .modemuxs = uart2_modemux,
+        .nmodemuxs = ARRAY_SIZE(uart2_modemux),
+};
+
+static const char *const uart2_grps[] = { "uart2_grp" };
+static struct spear_function uart2_function = {
+        .name = "uart2",
+        .groups = uart2_grps,
+        .ngroups = ARRAY_SIZE(uart2_grps),
+};
+
+/* uart3_pins */
+static const unsigned uart3_pins[] = { 37, 38 };
+static struct spear_muxreg uart3_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_UART0_MODEM_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux uart3_modemux[] = {
+        {
+                .muxregs = uart3_muxreg,
+                .nmuxregs = ARRAY_SIZE(uart3_muxreg),
+        },
+};
+
+static struct spear_pingroup uart3_pingroup = {
+        .name = "uart3_grp",
+        .pins = uart3_pins,
+        .npins = ARRAY_SIZE(uart3_pins),
+        .modemuxs = uart3_modemux,
+        .nmodemuxs = ARRAY_SIZE(uart3_modemux),
+};
+
+static const char *const uart3_grps[] = { "uart3_grp" };
+static struct spear_function uart3_function = {
+        .name = "uart3",
+        .groups = uart3_grps,
+        .ngroups = ARRAY_SIZE(uart3_grps),
+};
+
+/* uart4_pins */
+static const unsigned uart4_pins[] = { 39, 40 };
+static struct spear_muxreg uart4_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_UART0_MODEM_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux uart4_modemux[] = {
+        {
+                .muxregs = uart4_muxreg,
+                .nmuxregs = ARRAY_SIZE(uart4_muxreg),
+        },
+};
+
+static struct spear_pingroup uart4_pingroup = {
+        .name = "uart4_grp",
+        .pins = uart4_pins,
+        .npins = ARRAY_SIZE(uart4_pins),
+        .modemuxs = uart4_modemux,
+        .nmodemuxs = ARRAY_SIZE(uart4_modemux),
+};
+
+static const char *const uart4_grps[] = { "uart4_grp" };
+static struct spear_function uart4_function = {
+        .name = "uart4",
+        .groups = uart4_grps,
+        .ngroups = ARRAY_SIZE(uart4_grps),
+};
+
+/* uart5_pins */
+static const unsigned uart5_pins[] = { 41, 42 };
+static struct spear_muxreg uart5_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_UART0_MODEM_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux uart5_modemux[] = {
+        {
+                .muxregs = uart5_muxreg,
+                .nmuxregs = ARRAY_SIZE(uart5_muxreg),
+        },
+};
+
+static struct spear_pingroup uart5_pingroup = {
+        .name = "uart5_grp",
+        .pins = uart5_pins,
+        .npins = ARRAY_SIZE(uart5_pins),
+        .modemuxs = uart5_modemux,
+        .nmodemuxs = ARRAY_SIZE(uart5_modemux),
+};
+
+static const char *const uart5_grps[] = { "uart5_grp" };
+static struct spear_function uart5_function = {
+        .name = "uart5",
+        .groups = uart5_grps,
+        .ngroups = ARRAY_SIZE(uart5_grps),
+};
+
+/* fsmc_pins */
+static const unsigned fsmc_pins[] = { 34, 35, 36 };
+static struct spear_muxreg fsmc_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_SSP_CS_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux fsmc_modemux[] = {
+        {
+                .muxregs = fsmc_muxreg,
+                .nmuxregs = ARRAY_SIZE(fsmc_muxreg),
+        },
+};
+
+static struct spear_pingroup fsmc_pingroup = {
+        .name = "fsmc_grp",
+        .pins = fsmc_pins,
+        .npins = ARRAY_SIZE(fsmc_pins),
+        .modemuxs = fsmc_modemux,
+        .nmodemuxs = ARRAY_SIZE(fsmc_modemux),
+};
+
+static const char *const fsmc_grps[] = { "fsmc_grp" };
+static struct spear_function fsmc_function = {
+        .name = "fsmc",
+        .groups = fsmc_grps,
+        .ngroups = ARRAY_SIZE(fsmc_grps),
+};
+
+/* rs485_0_pins */
+static const unsigned rs485_0_pins[] = { 19, 20, 21, 22, 23 };
+static struct spear_muxreg rs485_0_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_MII_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux rs485_0_modemux[] = {
+        {
+                .muxregs = rs485_0_muxreg,
+                .nmuxregs = ARRAY_SIZE(rs485_0_muxreg),
+        },
+};
+
+static struct spear_pingroup rs485_0_pingroup = {
+        .name = "rs485_0_grp",
+        .pins = rs485_0_pins,
+        .npins = ARRAY_SIZE(rs485_0_pins),
+        .modemuxs = rs485_0_modemux,
+        .nmodemuxs = ARRAY_SIZE(rs485_0_modemux),
+};
+
+static const char *const rs485_0_grps[] = { "rs485_0" };
+static struct spear_function rs485_0_function = {
+        .name = "rs485_0",
+        .groups = rs485_0_grps,
+        .ngroups = ARRAY_SIZE(rs485_0_grps),
+};
+
+/* rs485_1_pins */
+static const unsigned rs485_1_pins[] = { 14, 15, 16, 17, 18 };
+static struct spear_muxreg rs485_1_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_MII_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux rs485_1_modemux[] = {
+        {
+                .muxregs = rs485_1_muxreg,
+                .nmuxregs = ARRAY_SIZE(rs485_1_muxreg),
+        },
+};
+
+static struct spear_pingroup rs485_1_pingroup = {
+        .name = "rs485_1_grp",
+        .pins = rs485_1_pins,
+        .npins = ARRAY_SIZE(rs485_1_pins),
+        .modemuxs = rs485_1_modemux,
+        .nmodemuxs = ARRAY_SIZE(rs485_1_modemux),
+};
+
+static const char *const rs485_1_grps[] = { "rs485_1" };
+static struct spear_function rs485_1_function = {
+        .name = "rs485_1",
+        .groups = rs485_1_grps,
+        .ngroups = ARRAY_SIZE(rs485_1_grps),
+};
+
+/* tdm_pins */
+static const unsigned tdm_pins[] = { 10, 11, 12, 13 };
+static struct spear_muxreg tdm_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_MII_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_modemux tdm_modemux[] = {
+        {
+                .muxregs = tdm_muxreg,
+                .nmuxregs = ARRAY_SIZE(tdm_muxreg),
+        },
+};
+
+static struct spear_pingroup tdm_pingroup = {
+        .name = "tdm_grp",
+        .pins = tdm_pins,
+        .npins = ARRAY_SIZE(tdm_pins),
+        .modemuxs = tdm_modemux,
+        .nmodemuxs = ARRAY_SIZE(tdm_modemux),
+};
+
+static const char *const tdm_grps[] = { "tdm_grp" };
+static struct spear_function tdm_function = {
+        .name = "tdm",
+        .groups = tdm_grps,
+        .ngroups = ARRAY_SIZE(tdm_grps),
+};
+
+/* pingroups */
+static struct spear_pingroup *spear310_pingroups[] = {
+        SPEAR3XX_COMMON_PINGROUPS,
+        &emi_cs_0_to_5_pingroup,
+        &uart1_pingroup,
+        &uart2_pingroup,
+        &uart3_pingroup,
+        &uart4_pingroup,
+        &uart5_pingroup,
+        &fsmc_pingroup,
+        &rs485_0_pingroup,
+        &rs485_1_pingroup,
+        &tdm_pingroup,
+};
+
+/* functions */
+static struct spear_function *spear310_functions[] = {
+        SPEAR3XX_COMMON_FUNCTIONS,
+        &emi_cs_0_to_5_function,
+        &uart1_function,
+        &uart2_function,
+        &uart3_function,
+        &uart4_function,
+        &uart5_function,
+        &fsmc_function,
+        &rs485_0_function,
+        &rs485_1_function,
+        &tdm_function,
+};
+
+static struct of_device_id spear310_pinctrl_of_match[] __devinitdata = {
+        {
+                .compatible = "st,spear310-pinmux",
+        },
+        {},
+};
+
+static int __devinit spear310_pinctrl_probe(struct platform_device *pdev)
+{
+        int ret;
+
+        spear3xx_machdata.groups = spear310_pingroups;
+        spear3xx_machdata.ngroups = ARRAY_SIZE(spear310_pingroups);
+        spear3xx_machdata.functions = spear310_functions;
+        spear3xx_machdata.nfunctions = ARRAY_SIZE(spear310_functions);
+
+        pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG);
+
+        spear3xx_machdata.modes_supported = false;
+
+        ret = spear_pinctrl_probe(pdev, &spear3xx_machdata);
+        if (ret)
+                return ret;
+
+        return 0;
+}
+
+static int __devexit spear310_pinctrl_remove(struct platform_device *pdev)
+{
+        return spear_pinctrl_remove(pdev);
+}
+
+static struct platform_driver spear310_pinctrl_driver = {
+        .driver = {
+                .name = DRIVER_NAME,
+                .owner = THIS_MODULE,
+                .of_match_table = spear310_pinctrl_of_match,
+        },
+        .probe = spear310_pinctrl_probe,
+        .remove = __devexit_p(spear310_pinctrl_remove),
+};
+
+static int __init spear310_pinctrl_init(void)
+{
+        return platform_driver_register(&spear310_pinctrl_driver);
+}
+arch_initcall(spear310_pinctrl_init);
+
+static void __exit spear310_pinctrl_exit(void)
+{
+        platform_driver_unregister(&spear310_pinctrl_driver);
+}
+module_exit(spear310_pinctrl_exit);
+
+MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>");
+MODULE_DESCRIPTION("ST Microelectronics SPEAr310 pinctrl driver");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, SPEAr310_pinctrl_of_match);
diff --git a/drivers/pinctrl/spear/pinctrl-spear320.c b/drivers/pinctrl/spear/pinctrl-spear320.c
new file mode 100644
index 000000000000..de726e6c283a
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear320.c
@@ -0,0 +1,3468 @@
+/*
+ * Driver for the ST Microelectronics SPEAr320 pinmux
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include "pinctrl-spear3xx.h"
+
+#define DRIVER_NAME "spear320-pinmux"
+
+/* addresses */
+#define PMX_CONFIG_REG                  0x0C
+#define MODE_CONFIG_REG                 0x10
+#define MODE_EXT_CONFIG_REG             0x18
+
+/* modes */
+#define AUTO_NET_SMII_MODE      (1 << 0)
+#define AUTO_NET_MII_MODE       (1 << 1)
+#define AUTO_EXP_MODE           (1 << 2)
+#define SMALL_PRINTERS_MODE     (1 << 3)
+#define EXTENDED_MODE           (1 << 4)
+
+static struct spear_pmx_mode pmx_mode_auto_net_smii = {
+        .name = "Automation Networking SMII mode",
+        .mode = AUTO_NET_SMII_MODE,
+        .reg = MODE_CONFIG_REG,
+        .mask = 0x00000007,
+        .val = 0x0,
+};
+
+static struct spear_pmx_mode pmx_mode_auto_net_mii = {
+        .name = "Automation Networking MII mode",
+        .mode = AUTO_NET_MII_MODE,
+        .reg = MODE_CONFIG_REG,
+        .mask = 0x00000007,
+        .val = 0x1,
+};
+
+static struct spear_pmx_mode pmx_mode_auto_exp = {
+        .name = "Automation Expanded mode",
+        .mode = AUTO_EXP_MODE,
+        .reg = MODE_CONFIG_REG,
+        .mask = 0x00000007,
+        .val = 0x2,
+};
+
+static struct spear_pmx_mode pmx_mode_small_printers = {
+        .name = "Small Printers mode",
+        .mode = SMALL_PRINTERS_MODE,
+        .reg = MODE_CONFIG_REG,
+        .mask = 0x00000007,
+        .val = 0x3,
+};
+
+static struct spear_pmx_mode pmx_mode_extended = {
+        .name = "extended mode",
+        .mode = EXTENDED_MODE,
+        .reg = MODE_EXT_CONFIG_REG,
+        .mask = 0x00000001,
+        .val = 0x1,
+};
+
+static struct spear_pmx_mode *spear320_pmx_modes[] = {
+        &pmx_mode_auto_net_smii,
+        &pmx_mode_auto_net_mii,
+        &pmx_mode_auto_exp,
+        &pmx_mode_small_printers,
+        &pmx_mode_extended,
+};
+
+/* Extended mode registers and their offsets */
+#define EXT_CTRL_REG                            0x0018
+        #define MII_MDIO_MASK                   (1 << 4)
+        #define MII_MDIO_10_11_VAL              0
+        #define MII_MDIO_81_VAL                 (1 << 4)
+        #define EMI_FSMC_DYNAMIC_MUX_MASK       (1 << 5)
+        #define MAC_MODE_MII                    0
+        #define MAC_MODE_RMII                   1
+        #define MAC_MODE_SMII                   2
+        #define MAC_MODE_SS_SMII                3
+        #define MAC_MODE_MASK                   0x3
+        #define MAC1_MODE_SHIFT                 16
+        #define MAC2_MODE_SHIFT                 18
+
+#define IP_SEL_PAD_0_9_REG                      0x00A4
+        #define PMX_PL_0_1_MASK                 (0x3F << 0)
+        #define PMX_UART2_PL_0_1_VAL            0x0
+        #define PMX_I2C2_PL_0_1_VAL             (0x4 | (0x4 << 3))
+
+        #define PMX_PL_2_3_MASK                 (0x3F << 6)
+        #define PMX_I2C2_PL_2_3_VAL             0x0
+        #define PMX_UART6_PL_2_3_VAL            ((0x1 << 6) | (0x1 << 9))
+        #define PMX_UART1_ENH_PL_2_3_VAL        ((0x4 << 6) | (0x4 << 9))
+
+        #define PMX_PL_4_5_MASK                 (0x3F << 12)
+        #define PMX_UART5_PL_4_5_VAL            ((0x1 << 12) | (0x1 << 15))
+        #define PMX_UART1_ENH_PL_4_5_VAL        ((0x4 << 12) | (0x4 << 15))
+        #define PMX_PL_5_MASK                   (0x7 << 15)
+        #define PMX_TOUCH_Y_PL_5_VAL            0x0
+
+        #define PMX_PL_6_7_MASK                 (0x3F << 18)
+        #define PMX_PL_6_MASK                   (0x7 << 18)
+        #define PMX_PL_7_MASK                   (0x7 << 21)
+        #define PMX_UART4_PL_6_7_VAL            ((0x1 << 18) | (0x1 << 21))
+        #define PMX_PWM_3_PL_6_VAL              (0x2 << 18)
+        #define PMX_PWM_2_PL_7_VAL              (0x2 << 21)
+        #define PMX_UART1_ENH_PL_6_7_VAL        ((0x4 << 18) | (0x4 << 21))
+
+        #define PMX_PL_8_9_MASK                 (0x3F << 24)
+        #define PMX_UART3_PL_8_9_VAL            ((0x1 << 24) | (0x1 << 27))
+        #define PMX_PWM_0_1_PL_8_9_VAL          ((0x2 << 24) | (0x2 << 27))
+        #define PMX_I2C1_PL_8_9_VAL             ((0x4 << 24) | (0x4 << 27))
+
+#define IP_SEL_PAD_10_19_REG                    0x00A8
+        #define PMX_PL_10_11_MASK               (0x3F << 0)
+        #define PMX_SMII_PL_10_11_VAL           0
+        #define PMX_RMII_PL_10_11_VAL           ((0x4 << 0) | (0x4 << 3))
+
+        #define PMX_PL_12_MASK                  (0x7 << 6)
+        #define PMX_PWM3_PL_12_VAL              0
+        #define PMX_SDHCI_CD_PL_12_VAL          (0x4 << 6)
+
+        #define PMX_PL_13_14_MASK               (0x3F << 9)
+        #define PMX_PL_13_MASK                  (0x7 << 9)
+        #define PMX_PL_14_MASK                  (0x7 << 12)
+        #define PMX_SSP2_PL_13_14_15_16_VAL     0
+        #define PMX_UART4_PL_13_14_VAL          ((0x1 << 9) | (0x1 << 12))
+        #define PMX_RMII_PL_13_14_VAL           ((0x4 << 9) | (0x4 << 12))
+        #define PMX_PWM2_PL_13_VAL              (0x2 << 9)
+        #define PMX_PWM1_PL_14_VAL              (0x2 << 12)
+
+        #define PMX_PL_15_MASK                  (0x7 << 15)
+        #define PMX_PWM0_PL_15_VAL              (0x2 << 15)
+        #define PMX_PL_15_16_MASK               (0x3F << 15)
+        #define PMX_UART3_PL_15_16_VAL          ((0x1 << 15) | (0x1 << 18))
+        #define PMX_RMII_PL_15_16_VAL           ((0x4 << 15) | (0x4 << 18))
+
+        #define PMX_PL_17_18_MASK               (0x3F << 21)
+        #define PMX_SSP1_PL_17_18_19_20_VAL     0
+        #define PMX_RMII_PL_17_18_VAL           ((0x4 << 21) | (0x4 << 24))
+
+        #define PMX_PL_19_MASK                  (0x7 << 27)
+        #define PMX_I2C2_PL_19_VAL              (0x1 << 27)
+        #define PMX_RMII_PL_19_VAL              (0x4 << 27)
+
+#define IP_SEL_PAD_20_29_REG                    0x00AC
+        #define PMX_PL_20_MASK                  (0x7 << 0)
+        #define PMX_I2C2_PL_20_VAL              (0x1 << 0)
+        #define PMX_RMII_PL_20_VAL              (0x4 << 0)
+
+        #define PMX_PL_21_TO_27_MASK            (0x1FFFFF << 3)
+        #define PMX_SMII_PL_21_TO_27_VAL        0
+        #define PMX_RMII_PL_21_TO_27_VAL        ((0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12) | (0x4 << 15) | (0x4 << 18) | (0x4 << 21))
+
+        #define PMX_PL_28_29_MASK               (0x3F << 24)
+        #define PMX_PL_28_MASK                  (0x7 << 24)
+        #define PMX_PL_29_MASK                  (0x7 << 27)
+        #define PMX_UART1_PL_28_29_VAL          0
+        #define PMX_PWM_3_PL_28_VAL             (0x4 << 24)
+        #define PMX_PWM_2_PL_29_VAL             (0x4 << 27)
+
+#define IP_SEL_PAD_30_39_REG                    0x00B0
+        #define PMX_PL_30_31_MASK               (0x3F << 0)
+        #define PMX_CAN1_PL_30_31_VAL           (0)
+        #define PMX_PL_30_MASK                  (0x7 << 0)
+        #define PMX_PL_31_MASK                  (0x7 << 3)
+        #define PMX_PWM1_EXT_PL_30_VAL          (0x4 << 0)
+        #define PMX_PWM0_EXT_PL_31_VAL          (0x4 << 3)
+        #define PMX_UART1_ENH_PL_31_VAL         (0x3 << 3)
+
+        #define PMX_PL_32_33_MASK               (0x3F << 6)
+        #define PMX_CAN0_PL_32_33_VAL           0
+        #define PMX_UART1_ENH_PL_32_33_VAL      ((0x3 << 6) | (0x3 << 9))
+        #define PMX_SSP2_PL_32_33_VAL           ((0x4 << 6) | (0x4 << 9))
+
+        #define PMX_PL_34_MASK                  (0x7 << 12)
+        #define PMX_PWM2_PL_34_VAL              0
+        #define PMX_UART1_ENH_PL_34_VAL         (0x2 << 12)
+        #define PMX_SSP2_PL_34_VAL              (0x4 << 12)
+
+        #define PMX_PL_35_MASK                  (0x7 << 15)
+        #define PMX_I2S_REF_CLK_PL_35_VAL       0
+        #define PMX_UART1_ENH_PL_35_VAL         (0x2 << 15)
+        #define PMX_SSP2_PL_35_VAL              (0x4 << 15)
+
+        #define PMX_PL_36_MASK                  (0x7 << 18)
+        #define PMX_TOUCH_X_PL_36_VAL           0
+        #define PMX_UART1_ENH_PL_36_VAL         (0x2 << 18)
+        #define PMX_SSP1_PL_36_VAL              (0x4 << 18)
+
+        #define PMX_PL_37_38_MASK               (0x3F << 21)
+        #define PMX_PWM0_1_PL_37_38_VAL         0
+        #define PMX_UART5_PL_37_38_VAL          ((0x2 << 21) | (0x2 << 24))
+        #define PMX_SSP1_PL_37_38_VAL           ((0x4 << 21) | (0x4 << 24))
+
+        #define PMX_PL_39_MASK                  (0x7 << 27)
+        #define PMX_I2S_PL_39_VAL               0
+        #define PMX_UART4_PL_39_VAL             (0x2 << 27)
+        #define PMX_SSP1_PL_39_VAL              (0x4 << 27)
+
+#define IP_SEL_PAD_40_49_REG                    0x00B4
+        #define PMX_PL_40_MASK                  (0x7 << 0)
+        #define PMX_I2S_PL_40_VAL               0
+        #define PMX_UART4_PL_40_VAL             (0x2 << 0)
+        #define PMX_PWM3_PL_40_VAL              (0x4 << 0)
+
+        #define PMX_PL_41_42_MASK               (0x3F << 3)
+        #define PMX_PL_41_MASK                  (0x7 << 3)
+        #define PMX_PL_42_MASK                  (0x7 << 6)
+        #define PMX_I2S_PL_41_42_VAL            0
+        #define PMX_UART3_PL_41_42_VAL          ((0x2 << 3) | (0x2 << 6))
+        #define PMX_PWM2_PL_41_VAL              (0x4 << 3)
+        #define PMX_PWM1_PL_42_VAL              (0x4 << 6)
+
+        #define PMX_PL_43_MASK                  (0x7 << 9)
+        #define PMX_SDHCI_PL_43_VAL             0
+        #define PMX_UART1_ENH_PL_43_VAL         (0x2 << 9)
+        #define PMX_PWM0_PL_43_VAL              (0x4 << 9)
+
+        #define PMX_PL_44_45_MASK               (0x3F << 12)
+        #define PMX_SDHCI_PL_44_45_VAL  0
+        #define PMX_UART1_ENH_PL_44_45_VAL      ((0x2 << 12) | (0x2 << 15))
+        #define PMX_SSP2_PL_44_45_VAL           ((0x4 << 12) | (0x4 << 15))
+
+        #define PMX_PL_46_47_MASK               (0x3F << 18)
+        #define PMX_SDHCI_PL_46_47_VAL  0
+        #define PMX_FSMC_EMI_PL_46_47_VAL       ((0x2 << 18) | (0x2 << 21))
+        #define PMX_SSP2_PL_46_47_VAL           ((0x4 << 18) | (0x4 << 21))
+
+        #define PMX_PL_48_49_MASK               (0x3F << 24)
+        #define PMX_SDHCI_PL_48_49_VAL  0
+        #define PMX_FSMC_EMI_PL_48_49_VAL       ((0x2 << 24) | (0x2 << 27))
+        #define PMX_SSP1_PL_48_49_VAL           ((0x4 << 24) | (0x4 << 27))
+
+#define IP_SEL_PAD_50_59_REG                    0x00B8
+        #define PMX_PL_50_51_MASK               (0x3F << 0)
+        #define PMX_EMI_PL_50_51_VAL            ((0x2 << 0) | (0x2 << 3))
+        #define PMX_SSP1_PL_50_51_VAL           ((0x4 << 0) | (0x4 << 3))
+        #define PMX_PL_50_MASK                  (0x7 << 0)
+        #define PMX_PL_51_MASK                  (0x7 << 3)
+        #define PMX_SDHCI_PL_50_VAL             0
+        #define PMX_SDHCI_CD_PL_51_VAL          0
+
+        #define PMX_PL_52_53_MASK               (0x3F << 6)
+        #define PMX_FSMC_PL_52_53_VAL           0
+        #define PMX_EMI_PL_52_53_VAL            ((0x2 << 6) | (0x2 << 9))
+        #define PMX_UART3_PL_52_53_VAL          ((0x4 << 6) | (0x4 << 9))
+
+        #define PMX_PL_54_55_56_MASK            (0x1FF << 12)
+        #define PMX_FSMC_EMI_PL_54_55_56_VAL    ((0x2 << 12) | (0x2 << 15) | (0x2 << 18))
+
+        #define PMX_PL_57_MASK                  (0x7 << 21)
+        #define PMX_FSMC_PL_57_VAL              0
+        #define PMX_PWM3_PL_57_VAL              (0x4 << 21)
+
+        #define PMX_PL_58_59_MASK               (0x3F << 24)
+        #define PMX_PL_58_MASK                  (0x7 << 24)
+        #define PMX_PL_59_MASK                  (0x7 << 27)
+        #define PMX_FSMC_EMI_PL_58_59_VAL       ((0x2 << 24) | (0x2 << 27))
+        #define PMX_PWM2_PL_58_VAL              (0x4 << 24)
+        #define PMX_PWM1_PL_59_VAL              (0x4 << 27)
+
+#define IP_SEL_PAD_60_69_REG                    0x00BC
+        #define PMX_PL_60_MASK                  (0x7 << 0)
+        #define PMX_FSMC_PL_60_VAL              0
+        #define PMX_PWM0_PL_60_VAL              (0x4 << 0)
+
+        #define PMX_PL_61_TO_64_MASK            (0xFFF << 3)
+        #define PMX_FSMC_PL_61_TO_64_VAL        ((0x2 << 3) | (0x2 << 6) | (0x2 << 9) | (0x2 << 12))
+        #define PMX_SSP2_PL_61_TO_64_VAL        ((0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12))
+
+        #define PMX_PL_65_TO_68_MASK            (0xFFF << 15)
+        #define PMX_FSMC_PL_65_TO_68_VAL        ((0x2 << 15) | (0x2 << 18) | (0x2 << 21) | (0x2 << 24))
+        #define PMX_SSP1_PL_65_TO_68_VAL        ((0x4 << 15) | (0x4 << 18) | (0x4 << 21) | (0x4 << 24))
+
+        #define PMX_PL_69_MASK                  (0x7 << 27)
+        #define PMX_CLCD_PL_69_VAL              (0)
+        #define PMX_EMI_PL_69_VAL               (0x2 << 27)
+        #define PMX_SPP_PL_69_VAL               (0x3 << 27)
+        #define PMX_UART5_PL_69_VAL             (0x4 << 27)
+
+#define IP_SEL_PAD_70_79_REG                    0x00C0
+        #define PMX_PL_70_MASK                  (0x7 << 0)
+        #define PMX_CLCD_PL_70_VAL              (0)
+        #define PMX_FSMC_EMI_PL_70_VAL          (0x2 << 0)
+        #define PMX_SPP_PL_70_VAL               (0x3 << 0)
+        #define PMX_UART5_PL_70_VAL             (0x4 << 0)
+
+        #define PMX_PL_71_72_MASK               (0x3F << 3)
+        #define PMX_CLCD_PL_71_72_VAL           (0)
+        #define PMX_FSMC_EMI_PL_71_72_VAL       ((0x2 << 3) | (0x2 << 6))
+        #define PMX_SPP_PL_71_72_VAL            ((0x3 << 3) | (0x3 << 6))
+        #define PMX_UART4_PL_71_72_VAL          ((0x4 << 3) | (0x4 << 6))
+
+        #define PMX_PL_73_MASK                  (0x7 << 9)
+        #define PMX_CLCD_PL_73_VAL              (0)
+        #define PMX_FSMC_EMI_PL_73_VAL          (0x2 << 9)
+        #define PMX_SPP_PL_73_VAL               (0x3 << 9)
+        #define PMX_UART3_PL_73_VAL             (0x4 << 9)
+
+        #define PMX_PL_74_MASK                  (0x7 << 12)
+        #define PMX_CLCD_PL_74_VAL              (0)
+        #define PMX_EMI_PL_74_VAL               (0x2 << 12)
+        #define PMX_SPP_PL_74_VAL               (0x3 << 12)
+        #define PMX_UART3_PL_74_VAL             (0x4 << 12)
+
+        #define PMX_PL_75_76_MASK               (0x3F << 15)
+        #define PMX_CLCD_PL_75_76_VAL           (0)
+        #define PMX_EMI_PL_75_76_VAL            ((0x2 << 15) | (0x2 << 18))
+        #define PMX_SPP_PL_75_76_VAL            ((0x3 << 15) | (0x3 << 18))
+        #define PMX_I2C2_PL_75_76_VAL           ((0x4 << 15) | (0x4 << 18))
+
+        #define PMX_PL_77_78_79_MASK            (0x1FF << 21)
+        #define PMX_CLCD_PL_77_78_79_VAL        (0)
+        #define PMX_EMI_PL_77_78_79_VAL         ((0x2 << 21) | (0x2 << 24) | (0x2 << 27))
+        #define PMX_SPP_PL_77_78_79_VAL         ((0x3 << 21) | (0x3 << 24) | (0x3 << 27))
+        #define PMX_RS485_PL_77_78_79_VAL       ((0x4 << 21) | (0x4 << 24) | (0x4 << 27))
+
+#define IP_SEL_PAD_80_89_REG                    0x00C4
+        #define PMX_PL_80_TO_85_MASK            (0x3FFFF << 0)
+        #define PMX_CLCD_PL_80_TO_85_VAL        0
+        #define PMX_MII2_PL_80_TO_85_VAL        ((0x1 << 0) | (0x1 << 3) | (0x1 << 6) | (0x1 << 9) | (0x1 << 12) | (0x1 << 15))
+        #define PMX_EMI_PL_80_TO_85_VAL         ((0x2 << 0) | (0x2 << 3) | (0x2 << 6) | (0x2 << 9) | (0x2 << 12) | (0x2 << 15))
+        #define PMX_SPP_PL_80_TO_85_VAL         ((0x3 << 0) | (0x3 << 3) | (0x3 << 6) | (0x3 << 9) | (0x3 << 12) | (0x3 << 15))
+        #define PMX_UART1_ENH_PL_80_TO_85_VAL   ((0x4 << 0) | (0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12) | (0x4 << 15))
+
+        #define PMX_PL_86_87_MASK               (0x3F << 18)
+        #define PMX_PL_86_MASK                  (0x7 << 18)
+        #define PMX_PL_87_MASK                  (0x7 << 21)
+        #define PMX_CLCD_PL_86_87_VAL           0
+        #define PMX_MII2_PL_86_87_VAL           ((0x1 << 18) | (0x1 << 21))
+        #define PMX_EMI_PL_86_87_VAL            ((0x2 << 18) | (0x2 << 21))
+        #define PMX_PWM3_PL_86_VAL              (0x4 << 18)
+        #define PMX_PWM2_PL_87_VAL              (0x4 << 21)
+
+        #define PMX_PL_88_89_MASK               (0x3F << 24)
+        #define PMX_CLCD_PL_88_89_VAL           0
+        #define PMX_MII2_PL_88_89_VAL           ((0x1 << 24) | (0x1 << 27))
+        #define PMX_EMI_PL_88_89_VAL            ((0x2 << 24) | (0x2 << 27))
+        #define PMX_UART6_PL_88_89_VAL          ((0x3 << 24) | (0x3 << 27))
+        #define PMX_PWM0_1_PL_88_89_VAL         ((0x4 << 24) | (0x4 << 27))
+
+#define IP_SEL_PAD_90_99_REG                    0x00C8
+        #define PMX_PL_90_91_MASK               (0x3F << 0)
+        #define PMX_CLCD_PL_90_91_VAL           0
+        #define PMX_MII2_PL_90_91_VAL           ((0x1 << 0) | (0x1 << 3))
+        #define PMX_EMI1_PL_90_91_VAL           ((0x2 << 0) | (0x2 << 3))
+        #define PMX_UART5_PL_90_91_VAL          ((0x3 << 0) | (0x3 << 3))
+        #define PMX_SSP2_PL_90_91_VAL           ((0x4 << 0) | (0x4 << 3))
+
+        #define PMX_PL_92_93_MASK               (0x3F << 6)
+        #define PMX_CLCD_PL_92_93_VAL           0
+        #define PMX_MII2_PL_92_93_VAL           ((0x1 << 6) | (0x1 << 9))
+        #define PMX_EMI1_PL_92_93_VAL           ((0x2 << 6) | (0x2 << 9))
+        #define PMX_UART4_PL_92_93_VAL          ((0x3 << 6) | (0x3 << 9))
+        #define PMX_SSP2_PL_92_93_VAL           ((0x4 << 6) | (0x4 << 9))
+
+        #define PMX_PL_94_95_MASK               (0x3F << 12)
+        #define PMX_CLCD_PL_94_95_VAL           0
+        #define PMX_MII2_PL_94_95_VAL           ((0x1 << 12) | (0x1 << 15))
+        #define PMX_EMI1_PL_94_95_VAL           ((0x2 << 12) | (0x2 << 15))
+        #define PMX_UART3_PL_94_95_VAL          ((0x3 << 12) | (0x3 << 15))
+        #define PMX_SSP1_PL_94_95_VAL           ((0x4 << 12) | (0x4 << 15))
+
+        #define PMX_PL_96_97_MASK               (0x3F << 18)
+        #define PMX_CLCD_PL_96_97_VAL           0
+        #define PMX_MII2_PL_96_97_VAL           ((0x1 << 18) | (0x1 << 21))
+        #define PMX_EMI1_PL_96_97_VAL           ((0x2 << 18) | (0x2 << 21))
+        #define PMX_I2C2_PL_96_97_VAL           ((0x3 << 18) | (0x3 << 21))
+        #define PMX_SSP1_PL_96_97_VAL           ((0x4 << 18) | (0x4 << 21))
+
+        #define PMX_PL_98_MASK                  (0x7 << 24)
+        #define PMX_CLCD_PL_98_VAL              0
+        #define PMX_I2C1_PL_98_VAL              (0x2 << 24)
+        #define PMX_UART3_PL_98_VAL             (0x4 << 24)
+
+        #define PMX_PL_99_MASK                  (0x7 << 27)
+        #define PMX_SDHCI_PL_99_VAL             0
+        #define PMX_I2C1_PL_99_VAL              (0x2 << 27)
+        #define PMX_UART3_PL_99_VAL             (0x4 << 27)
+
+#define IP_SEL_MIX_PAD_REG                      0x00CC
+        #define PMX_PL_100_101_MASK             (0x3F << 0)
+        #define PMX_SDHCI_PL_100_101_VAL        0
+        #define PMX_UART4_PL_100_101_VAL        ((0x4 << 0) | (0x4 << 3))
+
+        #define PMX_SSP1_PORT_SEL_MASK          (0x7 << 8)
+        #define PMX_SSP1_PORT_94_TO_97_VAL      0
+        #define PMX_SSP1_PORT_65_TO_68_VAL      (0x1 << 8)
+        #define PMX_SSP1_PORT_48_TO_51_VAL      (0x2 << 8)
+        #define PMX_SSP1_PORT_36_TO_39_VAL      (0x3 << 8)
+        #define PMX_SSP1_PORT_17_TO_20_VAL      (0x4 << 8)
+
+        #define PMX_SSP2_PORT_SEL_MASK          (0x7 << 11)
+        #define PMX_SSP2_PORT_90_TO_93_VAL      0
+        #define PMX_SSP2_PORT_61_TO_64_VAL      (0x1 << 11)
+        #define PMX_SSP2_PORT_44_TO_47_VAL      (0x2 << 11)
+        #define PMX_SSP2_PORT_32_TO_35_VAL      (0x3 << 11)
+        #define PMX_SSP2_PORT_13_TO_16_VAL      (0x4 << 11)
+
+        #define PMX_UART1_ENH_PORT_SEL_MASK             (0x3 << 14)
+        #define PMX_UART1_ENH_PORT_81_TO_85_VAL         0
+        #define PMX_UART1_ENH_PORT_44_45_34_36_VAL      (0x1 << 14)
+        #define PMX_UART1_ENH_PORT_32_TO_34_36_VAL      (0x2 << 14)
+        #define PMX_UART1_ENH_PORT_3_TO_5_7_VAL         (0x3 << 14)
+
+        #define PMX_UART3_PORT_SEL_MASK         (0x7 << 16)
+        #define PMX_UART3_PORT_94_VAL           0
+        #define PMX_UART3_PORT_73_VAL           (0x1 << 16)
+        #define PMX_UART3_PORT_52_VAL           (0x2 << 16)
+        #define PMX_UART3_PORT_41_VAL           (0x3 << 16)
+        #define PMX_UART3_PORT_15_VAL           (0x4 << 16)
+        #define PMX_UART3_PORT_8_VAL            (0x5 << 16)
+        #define PMX_UART3_PORT_99_VAL           (0x6 << 16)
+
+        #define PMX_UART4_PORT_SEL_MASK         (0x7 << 19)
+        #define PMX_UART4_PORT_92_VAL           0
+        #define PMX_UART4_PORT_71_VAL           (0x1 << 19)
+        #define PMX_UART4_PORT_39_VAL           (0x2 << 19)
+        #define PMX_UART4_PORT_13_VAL           (0x3 << 19)
+        #define PMX_UART4_PORT_6_VAL            (0x4 << 19)
+        #define PMX_UART4_PORT_101_VAL          (0x5 << 19)
+
+        #define PMX_UART5_PORT_SEL_MASK         (0x3 << 22)
+        #define PMX_UART5_PORT_90_VAL           0
+        #define PMX_UART5_PORT_69_VAL           (0x1 << 22)
+        #define PMX_UART5_PORT_37_VAL           (0x2 << 22)
+        #define PMX_UART5_PORT_4_VAL            (0x3 << 22)
+
+        #define PMX_UART6_PORT_SEL_MASK         (0x1 << 24)
+        #define PMX_UART6_PORT_88_VAL           0
+        #define PMX_UART6_PORT_2_VAL            (0x1 << 24)
+
+        #define PMX_I2C1_PORT_SEL_MASK          (0x1 << 25)
+        #define PMX_I2C1_PORT_8_9_VAL           0
+        #define PMX_I2C1_PORT_98_99_VAL         (0x1 << 25)
+
+        #define PMX_I2C2_PORT_SEL_MASK          (0x3 << 26)
+        #define PMX_I2C2_PORT_96_97_VAL         0
+        #define PMX_I2C2_PORT_75_76_VAL         (0x1 << 26)
+        #define PMX_I2C2_PORT_19_20_VAL         (0x2 << 26)
+        #define PMX_I2C2_PORT_2_3_VAL           (0x3 << 26)
+        #define PMX_I2C2_PORT_0_1_VAL           (0x4 << 26)
+
+        #define PMX_SDHCI_CD_PORT_SEL_MASK      (0x1 << 29)
+        #define PMX_SDHCI_CD_PORT_12_VAL        0
+        #define PMX_SDHCI_CD_PORT_51_VAL        (0x1 << 29)
+
+/* Pad multiplexing for CLCD device */
+static const unsigned clcd_pins[] = { 69, 70, 71, 72, 73, 74, 75, 76, 77, 78,
+        79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96,
+        97 };
+static struct spear_muxreg clcd_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_60_69_REG,
+                .mask = PMX_PL_69_MASK,
+                .val = PMX_CLCD_PL_69_VAL,
+        }, {
+                .reg = IP_SEL_PAD_70_79_REG,
+                .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
+                        PMX_PL_74_MASK | PMX_PL_75_76_MASK |
+                        PMX_PL_77_78_79_MASK,
+                .val = PMX_CLCD_PL_70_VAL | PMX_CLCD_PL_71_72_VAL |
+                        PMX_CLCD_PL_73_VAL | PMX_CLCD_PL_74_VAL |
+                        PMX_CLCD_PL_75_76_VAL | PMX_CLCD_PL_77_78_79_VAL,
+        }, {
+                .reg = IP_SEL_PAD_80_89_REG,
+                .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
+                        PMX_PL_88_89_MASK,
+                .val = PMX_CLCD_PL_80_TO_85_VAL | PMX_CLCD_PL_86_87_VAL |
+                        PMX_CLCD_PL_88_89_VAL,
+        }, {
+                .reg = IP_SEL_PAD_90_99_REG,
+                .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
+                        PMX_PL_94_95_MASK | PMX_PL_96_97_MASK | PMX_PL_98_MASK,
+                .val = PMX_CLCD_PL_90_91_VAL | PMX_CLCD_PL_92_93_VAL |
+                        PMX_CLCD_PL_94_95_VAL | PMX_CLCD_PL_96_97_VAL |
+                        PMX_CLCD_PL_98_VAL,
+        },
+};
+
+static struct spear_modemux clcd_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = clcd_muxreg,
+                .nmuxregs = ARRAY_SIZE(clcd_muxreg),
+        },
+};
+
+static struct spear_pingroup clcd_pingroup = {
+        .name = "clcd_grp",
+        .pins = clcd_pins,
+        .npins = ARRAY_SIZE(clcd_pins),
+        .modemuxs = clcd_modemux,
+        .nmodemuxs = ARRAY_SIZE(clcd_modemux),
+};
+
+static const char *const clcd_grps[] = { "clcd_grp" };
+static struct spear_function clcd_function = {
+        .name = "clcd",
+        .groups = clcd_grps,
+        .ngroups = ARRAY_SIZE(clcd_grps),
+};
+
+/* Pad multiplexing for EMI (Parallel NOR flash) device */
+static const unsigned emi_pins[] = { 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56,
+        57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74,
+        75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92,
+        93, 94, 95, 96, 97 };
+static struct spear_muxreg emi_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_muxreg emi_ext_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_40_49_REG,
+                .mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK,
+                .val = PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL,
+        }, {
+                .reg = IP_SEL_PAD_50_59_REG,
+                .mask = PMX_PL_50_51_MASK | PMX_PL_52_53_MASK |
+                        PMX_PL_54_55_56_MASK | PMX_PL_58_59_MASK,
+                .val = PMX_EMI_PL_50_51_VAL | PMX_EMI_PL_52_53_VAL |
+                        PMX_FSMC_EMI_PL_54_55_56_VAL |
+                        PMX_FSMC_EMI_PL_58_59_VAL,
+        }, {
+                .reg = IP_SEL_PAD_60_69_REG,
+                .mask = PMX_PL_69_MASK,
+                .val = PMX_EMI_PL_69_VAL,
+        }, {
+                .reg = IP_SEL_PAD_70_79_REG,
+                .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
+                        PMX_PL_74_MASK | PMX_PL_75_76_MASK |
+                        PMX_PL_77_78_79_MASK,
+                .val = PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL |
+                        PMX_FSMC_EMI_PL_73_VAL | PMX_EMI_PL_74_VAL |
+                        PMX_EMI_PL_75_76_VAL | PMX_EMI_PL_77_78_79_VAL,
+        }, {
+                .reg = IP_SEL_PAD_80_89_REG,
+                .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
+                        PMX_PL_88_89_MASK,
+                .val = PMX_EMI_PL_80_TO_85_VAL | PMX_EMI_PL_86_87_VAL |
+                        PMX_EMI_PL_88_89_VAL,
+        }, {
+                .reg = IP_SEL_PAD_90_99_REG,
+                .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
+                        PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
+                .val = PMX_EMI1_PL_90_91_VAL | PMX_EMI1_PL_92_93_VAL |
+                        PMX_EMI1_PL_94_95_VAL | PMX_EMI1_PL_96_97_VAL,
+        }, {
+                .reg = EXT_CTRL_REG,
+                .mask = EMI_FSMC_DYNAMIC_MUX_MASK,
+                .val = EMI_FSMC_DYNAMIC_MUX_MASK,
+        },
+};
+
+static struct spear_modemux emi_modemux[] = {
+        {
+                .modes = AUTO_EXP_MODE | EXTENDED_MODE,
+                .muxregs = emi_muxreg,
+                .nmuxregs = ARRAY_SIZE(emi_muxreg),
+        }, {
+                .modes = EXTENDED_MODE,
+                .muxregs = emi_ext_muxreg,
+                .nmuxregs = ARRAY_SIZE(emi_ext_muxreg),
+        },
+};
+
+static struct spear_pingroup emi_pingroup = {
+        .name = "emi_grp",
+        .pins = emi_pins,
+        .npins = ARRAY_SIZE(emi_pins),
+        .modemuxs = emi_modemux,
+        .nmodemuxs = ARRAY_SIZE(emi_modemux),
+};
+
+static const char *const emi_grps[] = { "emi_grp" };
+static struct spear_function emi_function = {
+        .name = "emi",
+        .groups = emi_grps,
+        .ngroups = ARRAY_SIZE(emi_grps),
+};
+
+/* Pad multiplexing for FSMC (NAND flash) device */
+static const unsigned fsmc_8bit_pins[] = { 52, 53, 54, 55, 56, 57, 58, 59, 60,
+        61, 62, 63, 64, 65, 66, 67, 68 };
+static struct spear_muxreg fsmc_8bit_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_50_59_REG,
+                .mask = PMX_PL_52_53_MASK | PMX_PL_54_55_56_MASK |
+                        PMX_PL_57_MASK | PMX_PL_58_59_MASK,
+                .val = PMX_FSMC_PL_52_53_VAL | PMX_FSMC_EMI_PL_54_55_56_VAL |
+                        PMX_FSMC_PL_57_VAL | PMX_FSMC_EMI_PL_58_59_VAL,
+        }, {
+                .reg = IP_SEL_PAD_60_69_REG,
+                .mask = PMX_PL_60_MASK | PMX_PL_61_TO_64_MASK |
+                        PMX_PL_65_TO_68_MASK,
+                .val = PMX_FSMC_PL_60_VAL | PMX_FSMC_PL_61_TO_64_VAL |
+                        PMX_FSMC_PL_65_TO_68_VAL,
+        }, {
+                .reg = EXT_CTRL_REG,
+                .mask = EMI_FSMC_DYNAMIC_MUX_MASK,
+                .val = EMI_FSMC_DYNAMIC_MUX_MASK,
+        },
+};
+
+static struct spear_modemux fsmc_8bit_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = fsmc_8bit_muxreg,
+                .nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg),
+        },
+};
+
+static struct spear_pingroup fsmc_8bit_pingroup = {
+        .name = "fsmc_8bit_grp",
+        .pins = fsmc_8bit_pins,
+        .npins = ARRAY_SIZE(fsmc_8bit_pins),
+        .modemuxs = fsmc_8bit_modemux,
+        .nmodemuxs = ARRAY_SIZE(fsmc_8bit_modemux),
+};
+
+static const unsigned fsmc_16bit_pins[] = { 46, 47, 48, 49, 52, 53, 54, 55, 56,
+        57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 70, 71, 72, 73 };
+static struct spear_muxreg fsmc_16bit_autoexp_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_muxreg fsmc_16bit_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_40_49_REG,
+                .mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK,
+                .val = PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL,
+        }, {
+                .reg = IP_SEL_PAD_70_79_REG,
+                .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK,
+                .val = PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL |
+                        PMX_FSMC_EMI_PL_73_VAL,
+        }
+};
+
+static struct spear_modemux fsmc_16bit_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = fsmc_8bit_muxreg,
+                .nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg),
+        }, {
+                .modes = AUTO_EXP_MODE | EXTENDED_MODE,
+                .muxregs = fsmc_16bit_autoexp_muxreg,
+                .nmuxregs = ARRAY_SIZE(fsmc_16bit_autoexp_muxreg),
+        }, {
+                .modes = EXTENDED_MODE,
+                .muxregs = fsmc_16bit_muxreg,
+                .nmuxregs = ARRAY_SIZE(fsmc_16bit_muxreg),
+        },
+};
+
+static struct spear_pingroup fsmc_16bit_pingroup = {
+        .name = "fsmc_16bit_grp",
+        .pins = fsmc_16bit_pins,
+        .npins = ARRAY_SIZE(fsmc_16bit_pins),
+        .modemuxs = fsmc_16bit_modemux,
+        .nmodemuxs = ARRAY_SIZE(fsmc_16bit_modemux),
+};
+
+static const char *const fsmc_grps[] = { "fsmc_8bit_grp", "fsmc_16bit_grp" };
+static struct spear_function fsmc_function = {
+        .name = "fsmc",
+        .groups = fsmc_grps,
+        .ngroups = ARRAY_SIZE(fsmc_grps),
+};
+
+/* Pad multiplexing for SPP device */
+static const unsigned spp_pins[] = { 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79,
+        80, 81, 82, 83, 84, 85 };
+static struct spear_muxreg spp_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_60_69_REG,
+                .mask = PMX_PL_69_MASK,
+                .val = PMX_SPP_PL_69_VAL,
+        }, {
+                .reg = IP_SEL_PAD_70_79_REG,
+                .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
+                        PMX_PL_74_MASK | PMX_PL_75_76_MASK |
+                        PMX_PL_77_78_79_MASK,
+                .val = PMX_SPP_PL_70_VAL | PMX_SPP_PL_71_72_VAL |
+                        PMX_SPP_PL_73_VAL | PMX_SPP_PL_74_VAL |
+                        PMX_SPP_PL_75_76_VAL | PMX_SPP_PL_77_78_79_VAL,
+        }, {
+                .reg = IP_SEL_PAD_80_89_REG,
+                .mask = PMX_PL_80_TO_85_MASK,
+                .val = PMX_SPP_PL_80_TO_85_VAL,
+        },
+};
+
+static struct spear_modemux spp_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = spp_muxreg,
+                .nmuxregs = ARRAY_SIZE(spp_muxreg),
+        },
+};
+
+static struct spear_pingroup spp_pingroup = {
+        .name = "spp_grp",
+        .pins = spp_pins,
+        .npins = ARRAY_SIZE(spp_pins),
+        .modemuxs = spp_modemux,
+        .nmodemuxs = ARRAY_SIZE(spp_modemux),
+};
+
+static const char *const spp_grps[] = { "spp_grp" };
+static struct spear_function spp_function = {
+        .name = "spp",
+        .groups = spp_grps,
+        .ngroups = ARRAY_SIZE(spp_grps),
+};
+
+/* Pad multiplexing for SDHCI device */
+static const unsigned sdhci_led_pins[] = { 34 };
+static struct spear_muxreg sdhci_led_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_SSP_CS_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_muxreg sdhci_led_ext_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_30_39_REG,
+                .mask = PMX_PL_34_MASK,
+                .val = PMX_PWM2_PL_34_VAL,
+        },
+};
+
+static struct spear_modemux sdhci_led_modemux[] = {
+        {
+                .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
+                .muxregs = sdhci_led_muxreg,
+                .nmuxregs = ARRAY_SIZE(sdhci_led_muxreg),
+        }, {
+                .modes = EXTENDED_MODE,
+                .muxregs = sdhci_led_ext_muxreg,
+                .nmuxregs = ARRAY_SIZE(sdhci_led_ext_muxreg),
+        },
+};
+
+static struct spear_pingroup sdhci_led_pingroup = {
+        .name = "sdhci_led_grp",
+        .pins = sdhci_led_pins,
+        .npins = ARRAY_SIZE(sdhci_led_pins),
+        .modemuxs = sdhci_led_modemux,
+        .nmodemuxs = ARRAY_SIZE(sdhci_led_modemux),
+};
+
+static const unsigned sdhci_cd_12_pins[] = { 12, 43, 44, 45, 46, 47, 48, 49,
+        50};
+static const unsigned sdhci_cd_51_pins[] = { 43, 44, 45, 46, 47, 48, 49, 50, 51
+};
+static struct spear_muxreg sdhci_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_muxreg sdhci_ext_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_40_49_REG,
+                .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK | PMX_PL_46_47_MASK |
+                        PMX_PL_48_49_MASK,
+                .val = PMX_SDHCI_PL_43_VAL | PMX_SDHCI_PL_44_45_VAL |
+                        PMX_SDHCI_PL_46_47_VAL | PMX_SDHCI_PL_48_49_VAL,
+        }, {
+                .reg = IP_SEL_PAD_50_59_REG,
+                .mask = PMX_PL_50_MASK,
+                .val = PMX_SDHCI_PL_50_VAL,
+        }, {
+                .reg = IP_SEL_PAD_90_99_REG,
+                .mask = PMX_PL_99_MASK,
+                .val = PMX_SDHCI_PL_99_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_PL_100_101_MASK,
+                .val = PMX_SDHCI_PL_100_101_VAL,
+        },
+};
+
+static struct spear_muxreg sdhci_cd_12_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_MII_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_10_19_REG,
+                .mask = PMX_PL_12_MASK,
+                .val = PMX_SDHCI_CD_PL_12_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_SDHCI_CD_PORT_SEL_MASK,
+                .val = PMX_SDHCI_CD_PORT_12_VAL,
+        },
+};
+
+static struct spear_muxreg sdhci_cd_51_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_50_59_REG,
+                .mask = PMX_PL_51_MASK,
+                .val = PMX_SDHCI_CD_PL_51_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_SDHCI_CD_PORT_SEL_MASK,
+                .val = PMX_SDHCI_CD_PORT_51_VAL,
+        },
+};
+
+#define pmx_sdhci_common_modemux                                        \
+        {                                                               \
+                .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE |       \
+                        SMALL_PRINTERS_MODE | EXTENDED_MODE,            \
+                .muxregs = sdhci_muxreg,                                \
+                .nmuxregs = ARRAY_SIZE(sdhci_muxreg),                   \
+        }, {                                                            \
+                .modes = EXTENDED_MODE,                                 \
+                .muxregs = sdhci_ext_muxreg,                            \
+                .nmuxregs = ARRAY_SIZE(sdhci_ext_muxreg),               \
+        }
+
+static struct spear_modemux sdhci_modemux[][3] = {
+        {
+                /* select pin 12 for cd */
+                pmx_sdhci_common_modemux,
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = sdhci_cd_12_muxreg,
+                        .nmuxregs = ARRAY_SIZE(sdhci_cd_12_muxreg),
+                },
+        }, {
+                /* select pin 51 for cd */
+                pmx_sdhci_common_modemux,
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = sdhci_cd_51_muxreg,
+                        .nmuxregs = ARRAY_SIZE(sdhci_cd_51_muxreg),
+                },
+        }
+};
+
+static struct spear_pingroup sdhci_pingroup[] = {
+        {
+                .name = "sdhci_cd_12_grp",
+                .pins = sdhci_cd_12_pins,
+                .npins = ARRAY_SIZE(sdhci_cd_12_pins),
+                .modemuxs = sdhci_modemux[0],
+                .nmodemuxs = ARRAY_SIZE(sdhci_modemux[0]),
+        }, {
+                .name = "sdhci_cd_51_grp",
+                .pins = sdhci_cd_51_pins,
+                .npins = ARRAY_SIZE(sdhci_cd_51_pins),
+                .modemuxs = sdhci_modemux[1],
+                .nmodemuxs = ARRAY_SIZE(sdhci_modemux[1]),
+        },
+};
+
+static const char *const sdhci_grps[] = { "sdhci_cd_12_grp", "sdhci_cd_51_grp",
+        "sdhci_led_grp" };
+
+static struct spear_function sdhci_function = {
+        .name = "sdhci",
+        .groups = sdhci_grps,
+        .ngroups = ARRAY_SIZE(sdhci_grps),
+};
+
+/* Pad multiplexing for I2S device */
+static const unsigned i2s_pins[] = { 35, 39, 40, 41, 42 };
+static struct spear_muxreg i2s_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_SSP_CS_MASK,
+                .val = 0,
+        }, {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_UART0_MODEM_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_muxreg i2s_ext_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_30_39_REG,
+                .mask = PMX_PL_35_MASK | PMX_PL_39_MASK,
+                .val = PMX_I2S_REF_CLK_PL_35_VAL | PMX_I2S_PL_39_VAL,
+        }, {
+                .reg = IP_SEL_PAD_40_49_REG,
+                .mask = PMX_PL_40_MASK | PMX_PL_41_42_MASK,
+                .val = PMX_I2S_PL_40_VAL | PMX_I2S_PL_41_42_VAL,
+        },
+};
+
+static struct spear_modemux i2s_modemux[] = {
+        {
+                .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
+                .muxregs = i2s_muxreg,
+                .nmuxregs = ARRAY_SIZE(i2s_muxreg),
+        }, {
+                .modes = EXTENDED_MODE,
+                .muxregs = i2s_ext_muxreg,
+                .nmuxregs = ARRAY_SIZE(i2s_ext_muxreg),
+        },
+};
+
+static struct spear_pingroup i2s_pingroup = {
+        .name = "i2s_grp",
+        .pins = i2s_pins,
+        .npins = ARRAY_SIZE(i2s_pins),
+        .modemuxs = i2s_modemux,
+        .nmodemuxs = ARRAY_SIZE(i2s_modemux),
+};
+
+static const char *const i2s_grps[] = { "i2s_grp" };
+static struct spear_function i2s_function = {
+        .name = "i2s",
+        .groups = i2s_grps,
+        .ngroups = ARRAY_SIZE(i2s_grps),
+};
+
+/* Pad multiplexing for UART1 device */
+static const unsigned uart1_pins[] = { 28, 29 };
+static struct spear_muxreg uart1_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_muxreg uart1_ext_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_20_29_REG,
+                .mask = PMX_PL_28_29_MASK,
+                .val = PMX_UART1_PL_28_29_VAL,
+        },
+};
+
+static struct spear_modemux uart1_modemux[] = {
+        {
+                .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
+                        | SMALL_PRINTERS_MODE | EXTENDED_MODE,
+                .muxregs = uart1_muxreg,
+                .nmuxregs = ARRAY_SIZE(uart1_muxreg),
+        }, {
+                .modes = EXTENDED_MODE,
+                .muxregs = uart1_ext_muxreg,
+                .nmuxregs = ARRAY_SIZE(uart1_ext_muxreg),
+        },
+};
+
+static struct spear_pingroup uart1_pingroup = {
+        .name = "uart1_grp",
+        .pins = uart1_pins,
+        .npins = ARRAY_SIZE(uart1_pins),
+        .modemuxs = uart1_modemux,
+        .nmodemuxs = ARRAY_SIZE(uart1_modemux),
+};
+
+static const char *const uart1_grps[] = { "uart1_grp" };
+static struct spear_function uart1_function = {
+        .name = "uart1",
+        .groups = uart1_grps,
+        .ngroups = ARRAY_SIZE(uart1_grps),
+};
+
+/* Pad multiplexing for UART1 Modem device */
+static const unsigned uart1_modem_2_to_7_pins[] = { 2, 3, 4, 5, 6, 7 };
+static const unsigned uart1_modem_31_to_36_pins[] = { 31, 32, 33, 34, 35, 36 };
+static const unsigned uart1_modem_34_to_45_pins[] = { 34, 35, 36, 43, 44, 45 };
+static const unsigned uart1_modem_80_to_85_pins[] = { 80, 81, 82, 83, 84, 85 };
+
+static struct spear_muxreg uart1_modem_ext_2_to_7_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_UART0_MASK | PMX_I2C_MASK | PMX_SSP_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_0_9_REG,
+                .mask = PMX_PL_2_3_MASK | PMX_PL_6_7_MASK,
+                .val = PMX_UART1_ENH_PL_2_3_VAL | PMX_UART1_ENH_PL_4_5_VAL |
+                        PMX_UART1_ENH_PL_6_7_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_UART1_ENH_PORT_SEL_MASK,
+                .val = PMX_UART1_ENH_PORT_3_TO_5_7_VAL,
+        },
+};
+
+static struct spear_muxreg uart1_modem_31_to_36_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
+                        PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_muxreg uart1_modem_ext_31_to_36_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_30_39_REG,
+                .mask = PMX_PL_31_MASK | PMX_PL_32_33_MASK | PMX_PL_34_MASK |
+                        PMX_PL_35_MASK | PMX_PL_36_MASK,
+                .val = PMX_UART1_ENH_PL_31_VAL | PMX_UART1_ENH_PL_32_33_VAL |
+                        PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL |
+                        PMX_UART1_ENH_PL_36_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_UART1_ENH_PORT_SEL_MASK,
+                .val = PMX_UART1_ENH_PORT_32_TO_34_36_VAL,
+        },
+};
+
+static struct spear_muxreg uart1_modem_34_to_45_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK |
+                        PMX_SSP_CS_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_muxreg uart1_modem_ext_34_to_45_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_30_39_REG,
+                .mask = PMX_PL_34_MASK | PMX_PL_35_MASK | PMX_PL_36_MASK,
+                .val = PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL |
+                        PMX_UART1_ENH_PL_36_VAL,
+        }, {
+                .reg = IP_SEL_PAD_40_49_REG,
+                .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK,
+                .val = PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_UART1_ENH_PORT_SEL_MASK,
+                .val = PMX_UART1_ENH_PORT_44_45_34_36_VAL,
+        },
+};
+
+static struct spear_muxreg uart1_modem_ext_80_to_85_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_80_89_REG,
+                .mask = PMX_PL_80_TO_85_MASK,
+                .val = PMX_UART1_ENH_PL_80_TO_85_VAL,
+        }, {
+                .reg = IP_SEL_PAD_40_49_REG,
+                .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK,
+                .val = PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_UART1_ENH_PORT_SEL_MASK,
+                .val = PMX_UART1_ENH_PORT_81_TO_85_VAL,
+        },
+};
+
+static struct spear_modemux uart1_modem_2_to_7_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = uart1_modem_ext_2_to_7_muxreg,
+                .nmuxregs = ARRAY_SIZE(uart1_modem_ext_2_to_7_muxreg),
+        },
+};
+
+static struct spear_modemux uart1_modem_31_to_36_modemux[] = {
+        {
+                .modes = SMALL_PRINTERS_MODE | EXTENDED_MODE,
+                .muxregs = uart1_modem_31_to_36_muxreg,
+                .nmuxregs = ARRAY_SIZE(uart1_modem_31_to_36_muxreg),
+        }, {
+                .modes = EXTENDED_MODE,
+                .muxregs = uart1_modem_ext_31_to_36_muxreg,
+                .nmuxregs = ARRAY_SIZE(uart1_modem_ext_31_to_36_muxreg),
+        },
+};
+
+static struct spear_modemux uart1_modem_34_to_45_modemux[] = {
+        {
+                .modes = AUTO_EXP_MODE | EXTENDED_MODE,
+                .muxregs = uart1_modem_34_to_45_muxreg,
+                .nmuxregs = ARRAY_SIZE(uart1_modem_34_to_45_muxreg),
+        }, {
+                .modes = EXTENDED_MODE,
+                .muxregs = uart1_modem_ext_34_to_45_muxreg,
+                .nmuxregs = ARRAY_SIZE(uart1_modem_ext_34_to_45_muxreg),
+        },
+};
+
+static struct spear_modemux uart1_modem_80_to_85_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = uart1_modem_ext_80_to_85_muxreg,
+                .nmuxregs = ARRAY_SIZE(uart1_modem_ext_80_to_85_muxreg),
+        },
+};
+
+static struct spear_pingroup uart1_modem_pingroup[] = {
+        {
+                .name = "uart1_modem_2_to_7_grp",
+                .pins = uart1_modem_2_to_7_pins,
+                .npins = ARRAY_SIZE(uart1_modem_2_to_7_pins),
+                .modemuxs = uart1_modem_2_to_7_modemux,
+                .nmodemuxs = ARRAY_SIZE(uart1_modem_2_to_7_modemux),
+        }, {
+                .name = "uart1_modem_31_to_36_grp",
+                .pins = uart1_modem_31_to_36_pins,
+                .npins = ARRAY_SIZE(uart1_modem_31_to_36_pins),
+                .modemuxs = uart1_modem_31_to_36_modemux,
+                .nmodemuxs = ARRAY_SIZE(uart1_modem_31_to_36_modemux),
+        }, {
+                .name = "uart1_modem_34_to_45_grp",
+                .pins = uart1_modem_34_to_45_pins,
+                .npins = ARRAY_SIZE(uart1_modem_34_to_45_pins),
+                .modemuxs = uart1_modem_34_to_45_modemux,
+                .nmodemuxs = ARRAY_SIZE(uart1_modem_34_to_45_modemux),
+        }, {
+                .name = "uart1_modem_80_to_85_grp",
+                .pins = uart1_modem_80_to_85_pins,
+                .npins = ARRAY_SIZE(uart1_modem_80_to_85_pins),
+                .modemuxs = uart1_modem_80_to_85_modemux,
+                .nmodemuxs = ARRAY_SIZE(uart1_modem_80_to_85_modemux),
+        },
+};
+
+static const char *const uart1_modem_grps[] = { "uart1_modem_2_to_7_grp",
+        "uart1_modem_31_to_36_grp", "uart1_modem_34_to_45_grp",
+        "uart1_modem_80_to_85_grp" };
+static struct spear_function uart1_modem_function = {
+        .name = "uart1_modem",
+        .groups = uart1_modem_grps,
+        .ngroups = ARRAY_SIZE(uart1_modem_grps),
+};
+
+/* Pad multiplexing for UART2 device */
+static const unsigned uart2_pins[] = { 0, 1 };
+static struct spear_muxreg uart2_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_FIRDA_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_muxreg uart2_ext_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_0_9_REG,
+                .mask = PMX_PL_0_1_MASK,
+                .val = PMX_UART2_PL_0_1_VAL,
+        },
+};
+
+static struct spear_modemux uart2_modemux[] = {
+        {
+                .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
+                        | SMALL_PRINTERS_MODE | EXTENDED_MODE,
+                .muxregs = uart2_muxreg,
+                .nmuxregs = ARRAY_SIZE(uart2_muxreg),
+        }, {
+                .modes = EXTENDED_MODE,
+                .muxregs = uart2_ext_muxreg,
+                .nmuxregs = ARRAY_SIZE(uart2_ext_muxreg),
+        },
+};
+
+static struct spear_pingroup uart2_pingroup = {
+        .name = "uart2_grp",
+        .pins = uart2_pins,
+        .npins = ARRAY_SIZE(uart2_pins),
+        .modemuxs = uart2_modemux,
+        .nmodemuxs = ARRAY_SIZE(uart2_modemux),
+};
+
+static const char *const uart2_grps[] = { "uart2_grp" };
+static struct spear_function uart2_function = {
+        .name = "uart2",
+        .groups = uart2_grps,
+        .ngroups = ARRAY_SIZE(uart2_grps),
+};
+
+/* Pad multiplexing for uart3 device */
+static const unsigned uart3_pins[][2] = { { 8, 9 }, { 15, 16 }, { 41, 42 },
+        { 52, 53 }, { 73, 74 }, { 94, 95 }, { 98, 99 } };
+
+static struct spear_muxreg uart3_ext_8_9_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_SSP_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_0_9_REG,
+                .mask = PMX_PL_8_9_MASK,
+                .val = PMX_UART3_PL_8_9_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_UART3_PORT_SEL_MASK,
+                .val = PMX_UART3_PORT_8_VAL,
+        },
+};
+
+static struct spear_muxreg uart3_ext_15_16_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_MII_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_10_19_REG,
+                .mask = PMX_PL_15_16_MASK,
+                .val = PMX_UART3_PL_15_16_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_UART3_PORT_SEL_MASK,
+                .val = PMX_UART3_PORT_15_VAL,
+        },
+};
+
+static struct spear_muxreg uart3_ext_41_42_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_UART0_MODEM_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_40_49_REG,
+                .mask = PMX_PL_41_42_MASK,
+                .val = PMX_UART3_PL_41_42_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_UART3_PORT_SEL_MASK,
+                .val = PMX_UART3_PORT_41_VAL,
+        },
+};
+
+static struct spear_muxreg uart3_ext_52_53_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_50_59_REG,
+                .mask = PMX_PL_52_53_MASK,
+                .val = PMX_UART3_PL_52_53_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_UART3_PORT_SEL_MASK,
+                .val = PMX_UART3_PORT_52_VAL,
+        },
+};
+
+static struct spear_muxreg uart3_ext_73_74_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_70_79_REG,
+                .mask = PMX_PL_73_MASK | PMX_PL_74_MASK,
+                .val = PMX_UART3_PL_73_VAL | PMX_UART3_PL_74_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_UART3_PORT_SEL_MASK,
+                .val = PMX_UART3_PORT_73_VAL,
+        },
+};
+
+static struct spear_muxreg uart3_ext_94_95_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_90_99_REG,
+                .mask = PMX_PL_94_95_MASK,
+                .val = PMX_UART3_PL_94_95_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_UART3_PORT_SEL_MASK,
+                .val = PMX_UART3_PORT_94_VAL,
+        },
+};
+
+static struct spear_muxreg uart3_ext_98_99_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_90_99_REG,
+                .mask = PMX_PL_98_MASK | PMX_PL_99_MASK,
+                .val = PMX_UART3_PL_98_VAL | PMX_UART3_PL_99_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_UART3_PORT_SEL_MASK,
+                .val = PMX_UART3_PORT_99_VAL,
+        },
+};
+
+static struct spear_modemux uart3_modemux[][1] = {
+        {
+                /* Select signals on pins 8_9 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = uart3_ext_8_9_muxreg,
+                        .nmuxregs = ARRAY_SIZE(uart3_ext_8_9_muxreg),
+                },
+        }, {
+                /* Select signals on pins 15_16 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = uart3_ext_15_16_muxreg,
+                        .nmuxregs = ARRAY_SIZE(uart3_ext_15_16_muxreg),
+                },
+        }, {
+                /* Select signals on pins 41_42 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = uart3_ext_41_42_muxreg,
+                        .nmuxregs = ARRAY_SIZE(uart3_ext_41_42_muxreg),
+                },
+        }, {
+                /* Select signals on pins 52_53 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = uart3_ext_52_53_muxreg,
+                        .nmuxregs = ARRAY_SIZE(uart3_ext_52_53_muxreg),
+                },
+        }, {
+                /* Select signals on pins 73_74 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = uart3_ext_73_74_muxreg,
+                        .nmuxregs = ARRAY_SIZE(uart3_ext_73_74_muxreg),
+                },
+        }, {
+                /* Select signals on pins 94_95 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = uart3_ext_94_95_muxreg,
+                        .nmuxregs = ARRAY_SIZE(uart3_ext_94_95_muxreg),
+                },
+        }, {
+                /* Select signals on pins 98_99 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = uart3_ext_98_99_muxreg,
+                        .nmuxregs = ARRAY_SIZE(uart3_ext_98_99_muxreg),
+                },
+        },
+};
+
+static struct spear_pingroup uart3_pingroup[] = {
+        {
+                .name = "uart3_8_9_grp",
+                .pins = uart3_pins[0],
+                .npins = ARRAY_SIZE(uart3_pins[0]),
+                .modemuxs = uart3_modemux[0],
+                .nmodemuxs = ARRAY_SIZE(uart3_modemux[0]),
+        }, {
+                .name = "uart3_15_16_grp",
+                .pins = uart3_pins[1],
+                .npins = ARRAY_SIZE(uart3_pins[1]),
+                .modemuxs = uart3_modemux[1],
+                .nmodemuxs = ARRAY_SIZE(uart3_modemux[1]),
+        }, {
+                .name = "uart3_41_42_grp",
+                .pins = uart3_pins[2],
+                .npins = ARRAY_SIZE(uart3_pins[2]),
+                .modemuxs = uart3_modemux[2],
+                .nmodemuxs = ARRAY_SIZE(uart3_modemux[2]),
+        }, {
+                .name = "uart3_52_53_grp",
+                .pins = uart3_pins[3],
+                .npins = ARRAY_SIZE(uart3_pins[3]),
+                .modemuxs = uart3_modemux[3],
+                .nmodemuxs = ARRAY_SIZE(uart3_modemux[3]),
+        }, {
+                .name = "uart3_73_74_grp",
+                .pins = uart3_pins[4],
+                .npins = ARRAY_SIZE(uart3_pins[4]),
+                .modemuxs = uart3_modemux[4],
+                .nmodemuxs = ARRAY_SIZE(uart3_modemux[4]),
+        }, {
+                .name = "uart3_94_95_grp",
+                .pins = uart3_pins[5],
+                .npins = ARRAY_SIZE(uart3_pins[5]),
+                .modemuxs = uart3_modemux[5],
+                .nmodemuxs = ARRAY_SIZE(uart3_modemux[5]),
+        }, {
+                .name = "uart3_98_99_grp",
+                .pins = uart3_pins[6],
+                .npins = ARRAY_SIZE(uart3_pins[6]),
+                .modemuxs = uart3_modemux[6],
+                .nmodemuxs = ARRAY_SIZE(uart3_modemux[6]),
+        },
+};
+
+static const char *const uart3_grps[] = { "uart3_8_9_grp", "uart3_15_16_grp",
+        "uart3_41_42_grp", "uart3_52_53_grp", "uart3_73_74_grp",
+        "uart3_94_95_grp", "uart3_98_99_grp" };
+
+static struct spear_function uart3_function = {
+        .name = "uart3",
+        .groups = uart3_grps,
+        .ngroups = ARRAY_SIZE(uart3_grps),
+};
+
+/* Pad multiplexing for uart4 device */
+static const unsigned uart4_pins[][2] = { { 6, 7 }, { 13, 14 }, { 39, 40 },
+        { 71, 72 }, { 92, 93 }, { 100, 101 } };
+
+static struct spear_muxreg uart4_ext_6_7_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_SSP_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_0_9_REG,
+                .mask = PMX_PL_6_7_MASK,
+                .val = PMX_UART4_PL_6_7_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_UART4_PORT_SEL_MASK,
+                .val = PMX_UART4_PORT_6_VAL,
+        },
+};
+
+static struct spear_muxreg uart4_ext_13_14_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_MII_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_10_19_REG,
+                .mask = PMX_PL_13_14_MASK,
+                .val = PMX_UART4_PL_13_14_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_UART4_PORT_SEL_MASK,
+                .val = PMX_UART4_PORT_13_VAL,
+        },
+};
+
+static struct spear_muxreg uart4_ext_39_40_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_UART0_MODEM_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_30_39_REG,
+                .mask = PMX_PL_39_MASK,
+                .val = PMX_UART4_PL_39_VAL,
+        }, {
+                .reg = IP_SEL_PAD_40_49_REG,
+                .mask = PMX_PL_40_MASK,
+                .val = PMX_UART4_PL_40_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_UART4_PORT_SEL_MASK,
+                .val = PMX_UART4_PORT_39_VAL,
+        },
+};
+
+static struct spear_muxreg uart4_ext_71_72_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_70_79_REG,
+                .mask = PMX_PL_71_72_MASK,
+                .val = PMX_UART4_PL_71_72_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_UART4_PORT_SEL_MASK,
+                .val = PMX_UART4_PORT_71_VAL,
+        },
+};
+
+static struct spear_muxreg uart4_ext_92_93_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_90_99_REG,
+                .mask = PMX_PL_92_93_MASK,
+                .val = PMX_UART4_PL_92_93_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_UART4_PORT_SEL_MASK,
+                .val = PMX_UART4_PORT_92_VAL,
+        },
+};
+
+static struct spear_muxreg uart4_ext_100_101_muxreg[] = {
+        {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_PL_100_101_MASK |
+                        PMX_UART4_PORT_SEL_MASK,
+                .val = PMX_UART4_PL_100_101_VAL |
+                        PMX_UART4_PORT_101_VAL,
+        },
+};
+
+static struct spear_modemux uart4_modemux[][1] = {
+        {
+                /* Select signals on pins 6_7 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = uart4_ext_6_7_muxreg,
+                        .nmuxregs = ARRAY_SIZE(uart4_ext_6_7_muxreg),
+                },
+        }, {
+                /* Select signals on pins 13_14 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = uart4_ext_13_14_muxreg,
+                        .nmuxregs = ARRAY_SIZE(uart4_ext_13_14_muxreg),
+                },
+        }, {
+                /* Select signals on pins 39_40 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = uart4_ext_39_40_muxreg,
+                        .nmuxregs = ARRAY_SIZE(uart4_ext_39_40_muxreg),
+                },
+        }, {
+                /* Select signals on pins 71_72 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = uart4_ext_71_72_muxreg,
+                        .nmuxregs = ARRAY_SIZE(uart4_ext_71_72_muxreg),
+                },
+        }, {
+                /* Select signals on pins 92_93 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = uart4_ext_92_93_muxreg,
+                        .nmuxregs = ARRAY_SIZE(uart4_ext_92_93_muxreg),
+                },
+        }, {
+                /* Select signals on pins 100_101_ */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = uart4_ext_100_101_muxreg,
+                        .nmuxregs = ARRAY_SIZE(uart4_ext_100_101_muxreg),
+                },
+        },
+};
+
+static struct spear_pingroup uart4_pingroup[] = {
+        {
+                .name = "uart4_6_7_grp",
+                .pins = uart4_pins[0],
+                .npins = ARRAY_SIZE(uart4_pins[0]),
+                .modemuxs = uart4_modemux[0],
+                .nmodemuxs = ARRAY_SIZE(uart4_modemux[0]),
+        }, {
+                .name = "uart4_13_14_grp",
+                .pins = uart4_pins[1],
+                .npins = ARRAY_SIZE(uart4_pins[1]),
+                .modemuxs = uart4_modemux[1],
+                .nmodemuxs = ARRAY_SIZE(uart4_modemux[1]),
+        }, {
+                .name = "uart4_39_40_grp",
+                .pins = uart4_pins[2],
+                .npins = ARRAY_SIZE(uart4_pins[2]),
+                .modemuxs = uart4_modemux[2],
+                .nmodemuxs = ARRAY_SIZE(uart4_modemux[2]),
+        }, {
+                .name = "uart4_71_72_grp",
+                .pins = uart4_pins[3],
+                .npins = ARRAY_SIZE(uart4_pins[3]),
+                .modemuxs = uart4_modemux[3],
+                .nmodemuxs = ARRAY_SIZE(uart4_modemux[3]),
+        }, {
+                .name = "uart4_92_93_grp",
+                .pins = uart4_pins[4],
+                .npins = ARRAY_SIZE(uart4_pins[4]),
+                .modemuxs = uart4_modemux[4],
+                .nmodemuxs = ARRAY_SIZE(uart4_modemux[4]),
+        }, {
+                .name = "uart4_100_101_grp",
+                .pins = uart4_pins[5],
+                .npins = ARRAY_SIZE(uart4_pins[5]),
+                .modemuxs = uart4_modemux[5],
+                .nmodemuxs = ARRAY_SIZE(uart4_modemux[5]),
+        },
+};
+
+static const char *const uart4_grps[] = { "uart4_6_7_grp", "uart4_13_14_grp",
+        "uart4_39_40_grp", "uart4_71_72_grp", "uart4_92_93_grp",
+        "uart4_100_101_grp" };
+
+static struct spear_function uart4_function = {
+        .name = "uart4",
+        .groups = uart4_grps,
+        .ngroups = ARRAY_SIZE(uart4_grps),
+};
+
+/* Pad multiplexing for uart5 device */
+static const unsigned uart5_pins[][2] = { { 4, 5 }, { 37, 38 }, { 69, 70 },
+        { 90, 91 } };
+
+static struct spear_muxreg uart5_ext_4_5_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_I2C_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_0_9_REG,
+                .mask = PMX_PL_4_5_MASK,
+                .val = PMX_UART5_PL_4_5_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_UART5_PORT_SEL_MASK,
+                .val = PMX_UART5_PORT_4_VAL,
+        },
+};
+
+static struct spear_muxreg uart5_ext_37_38_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_UART0_MODEM_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_30_39_REG,
+                .mask = PMX_PL_37_38_MASK,
+                .val = PMX_UART5_PL_37_38_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_UART5_PORT_SEL_MASK,
+                .val = PMX_UART5_PORT_37_VAL,
+        },
+};
+
+static struct spear_muxreg uart5_ext_69_70_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_60_69_REG,
+                .mask = PMX_PL_69_MASK,
+                .val = PMX_UART5_PL_69_VAL,
+        }, {
+                .reg = IP_SEL_PAD_70_79_REG,
+                .mask = PMX_PL_70_MASK,
+                .val = PMX_UART5_PL_70_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_UART5_PORT_SEL_MASK,
+                .val = PMX_UART5_PORT_69_VAL,
+        },
+};
+
+static struct spear_muxreg uart5_ext_90_91_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_90_99_REG,
+                .mask = PMX_PL_90_91_MASK,
+                .val = PMX_UART5_PL_90_91_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_UART5_PORT_SEL_MASK,
+                .val = PMX_UART5_PORT_90_VAL,
+        },
+};
+
+static struct spear_modemux uart5_modemux[][1] = {
+        {
+                /* Select signals on pins 4_5 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = uart5_ext_4_5_muxreg,
+                        .nmuxregs = ARRAY_SIZE(uart5_ext_4_5_muxreg),
+                },
+        }, {
+                /* Select signals on pins 37_38 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = uart5_ext_37_38_muxreg,
+                        .nmuxregs = ARRAY_SIZE(uart5_ext_37_38_muxreg),
+                },
+        }, {
+                /* Select signals on pins 69_70 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = uart5_ext_69_70_muxreg,
+                        .nmuxregs = ARRAY_SIZE(uart5_ext_69_70_muxreg),
+                },
+        }, {
+                /* Select signals on pins 90_91 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = uart5_ext_90_91_muxreg,
+                        .nmuxregs = ARRAY_SIZE(uart5_ext_90_91_muxreg),
+                },
+        },
+};
+
+static struct spear_pingroup uart5_pingroup[] = {
+        {
+                .name = "uart5_4_5_grp",
+                .pins = uart5_pins[0],
+                .npins = ARRAY_SIZE(uart5_pins[0]),
+                .modemuxs = uart5_modemux[0],
+                .nmodemuxs = ARRAY_SIZE(uart5_modemux[0]),
+        }, {
+                .name = "uart5_37_38_grp",
+                .pins = uart5_pins[1],
+                .npins = ARRAY_SIZE(uart5_pins[1]),
+                .modemuxs = uart5_modemux[1],
+                .nmodemuxs = ARRAY_SIZE(uart5_modemux[1]),
+        }, {
+                .name = "uart5_69_70_grp",
+                .pins = uart5_pins[2],
+                .npins = ARRAY_SIZE(uart5_pins[2]),
+                .modemuxs = uart5_modemux[2],
+                .nmodemuxs = ARRAY_SIZE(uart5_modemux[2]),
+        }, {
+                .name = "uart5_90_91_grp",
+                .pins = uart5_pins[3],
+                .npins = ARRAY_SIZE(uart5_pins[3]),
+                .modemuxs = uart5_modemux[3],
+                .nmodemuxs = ARRAY_SIZE(uart5_modemux[3]),
+        },
+};
+
+static const char *const uart5_grps[] = { "uart5_4_5_grp", "uart5_37_38_grp",
+        "uart5_69_70_grp", "uart5_90_91_grp" };
+static struct spear_function uart5_function = {
+        .name = "uart5",
+        .groups = uart5_grps,
+        .ngroups = ARRAY_SIZE(uart5_grps),
+};
+
+/* Pad multiplexing for uart6 device */
+static const unsigned uart6_pins[][2] = { { 2, 3 }, { 88, 89 } };
+static struct spear_muxreg uart6_ext_2_3_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_UART0_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_0_9_REG,
+                .mask = PMX_PL_2_3_MASK,
+                .val = PMX_UART6_PL_2_3_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_UART6_PORT_SEL_MASK,
+                .val = PMX_UART6_PORT_2_VAL,
+        },
+};
+
+static struct spear_muxreg uart6_ext_88_89_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_80_89_REG,
+                .mask = PMX_PL_88_89_MASK,
+                .val = PMX_UART6_PL_88_89_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_UART6_PORT_SEL_MASK,
+                .val = PMX_UART6_PORT_88_VAL,
+        },
+};
+
+static struct spear_modemux uart6_modemux[][1] = {
+        {
+                /* Select signals on pins 2_3 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = uart6_ext_2_3_muxreg,
+                        .nmuxregs = ARRAY_SIZE(uart6_ext_2_3_muxreg),
+                },
+        }, {
+                /* Select signals on pins 88_89 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = uart6_ext_88_89_muxreg,
+                        .nmuxregs = ARRAY_SIZE(uart6_ext_88_89_muxreg),
+                },
+        },
+};
+
+static struct spear_pingroup uart6_pingroup[] = {
+        {
+                .name = "uart6_2_3_grp",
+                .pins = uart6_pins[0],
+                .npins = ARRAY_SIZE(uart6_pins[0]),
+                .modemuxs = uart6_modemux[0],
+                .nmodemuxs = ARRAY_SIZE(uart6_modemux[0]),
+        }, {
+                .name = "uart6_88_89_grp",
+                .pins = uart6_pins[1],
+                .npins = ARRAY_SIZE(uart6_pins[1]),
+                .modemuxs = uart6_modemux[1],
+                .nmodemuxs = ARRAY_SIZE(uart6_modemux[1]),
+        },
+};
+
+static const char *const uart6_grps[] = { "uart6_2_3_grp", "uart6_88_89_grp" };
+static struct spear_function uart6_function = {
+        .name = "uart6",
+        .groups = uart6_grps,
+        .ngroups = ARRAY_SIZE(uart6_grps),
+};
+
+/* UART - RS485 pmx */
+static const unsigned rs485_pins[] = { 77, 78, 79 };
+static struct spear_muxreg rs485_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_70_79_REG,
+                .mask = PMX_PL_77_78_79_MASK,
+                .val = PMX_RS485_PL_77_78_79_VAL,
+        },
+};
+
+static struct spear_modemux rs485_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = rs485_muxreg,
+                .nmuxregs = ARRAY_SIZE(rs485_muxreg),
+        },
+};
+
+static struct spear_pingroup rs485_pingroup = {
+        .name = "rs485_grp",
+        .pins = rs485_pins,
+        .npins = ARRAY_SIZE(rs485_pins),
+        .modemuxs = rs485_modemux,
+        .nmodemuxs = ARRAY_SIZE(rs485_modemux),
+};
+
+static const char *const rs485_grps[] = { "rs485_grp" };
+static struct spear_function rs485_function = {
+        .name = "rs485",
+        .groups = rs485_grps,
+        .ngroups = ARRAY_SIZE(rs485_grps),
+};
+
+/* Pad multiplexing for Touchscreen device */
+static const unsigned touchscreen_pins[] = { 5, 36 };
+static struct spear_muxreg touchscreen_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_I2C_MASK | PMX_SSP_CS_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_muxreg touchscreen_ext_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_0_9_REG,
+                .mask = PMX_PL_5_MASK,
+                .val = PMX_TOUCH_Y_PL_5_VAL,
+        }, {
+                .reg = IP_SEL_PAD_30_39_REG,
+                .mask = PMX_PL_36_MASK,
+                .val = PMX_TOUCH_X_PL_36_VAL,
+        },
+};
+
+static struct spear_modemux touchscreen_modemux[] = {
+        {
+                .modes = AUTO_NET_SMII_MODE | EXTENDED_MODE,
+                .muxregs = touchscreen_muxreg,
+                .nmuxregs = ARRAY_SIZE(touchscreen_muxreg),
+        }, {
+                .modes = EXTENDED_MODE,
+                .muxregs = touchscreen_ext_muxreg,
+                .nmuxregs = ARRAY_SIZE(touchscreen_ext_muxreg),
+        },
+};
+
+static struct spear_pingroup touchscreen_pingroup = {
+        .name = "touchscreen_grp",
+        .pins = touchscreen_pins,
+        .npins = ARRAY_SIZE(touchscreen_pins),
+        .modemuxs = touchscreen_modemux,
+        .nmodemuxs = ARRAY_SIZE(touchscreen_modemux),
+};
+
+static const char *const touchscreen_grps[] = { "touchscreen_grp" };
+static struct spear_function touchscreen_function = {
+        .name = "touchscreen",
+        .groups = touchscreen_grps,
+        .ngroups = ARRAY_SIZE(touchscreen_grps),
+};
+
+/* Pad multiplexing for CAN device */
+static const unsigned can0_pins[] = { 32, 33 };
+static struct spear_muxreg can0_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_muxreg can0_ext_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_30_39_REG,
+                .mask = PMX_PL_32_33_MASK,
+                .val = PMX_CAN0_PL_32_33_VAL,
+        },
+};
+
+static struct spear_modemux can0_modemux[] = {
+        {
+                .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
+                        | EXTENDED_MODE,
+                .muxregs = can0_muxreg,
+                .nmuxregs = ARRAY_SIZE(can0_muxreg),
+        }, {
+                .modes = EXTENDED_MODE,
+                .muxregs = can0_ext_muxreg,
+                .nmuxregs = ARRAY_SIZE(can0_ext_muxreg),
+        },
+};
+
+static struct spear_pingroup can0_pingroup = {
+        .name = "can0_grp",
+        .pins = can0_pins,
+        .npins = ARRAY_SIZE(can0_pins),
+        .modemuxs = can0_modemux,
+        .nmodemuxs = ARRAY_SIZE(can0_modemux),
+};
+
+static const char *const can0_grps[] = { "can0_grp" };
+static struct spear_function can0_function = {
+        .name = "can0",
+        .groups = can0_grps,
+        .ngroups = ARRAY_SIZE(can0_grps),
+};
+
+static const unsigned can1_pins[] = { 30, 31 };
+static struct spear_muxreg can1_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_muxreg can1_ext_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_30_39_REG,
+                .mask = PMX_PL_30_31_MASK,
+                .val = PMX_CAN1_PL_30_31_VAL,
+        },
+};
+
+static struct spear_modemux can1_modemux[] = {
+        {
+                .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
+                        | EXTENDED_MODE,
+                .muxregs = can1_muxreg,
+                .nmuxregs = ARRAY_SIZE(can1_muxreg),
+        }, {
+                .modes = EXTENDED_MODE,
+                .muxregs = can1_ext_muxreg,
+                .nmuxregs = ARRAY_SIZE(can1_ext_muxreg),
+        },
+};
+
+static struct spear_pingroup can1_pingroup = {
+        .name = "can1_grp",
+        .pins = can1_pins,
+        .npins = ARRAY_SIZE(can1_pins),
+        .modemuxs = can1_modemux,
+        .nmodemuxs = ARRAY_SIZE(can1_modemux),
+};
+
+static const char *const can1_grps[] = { "can1_grp" };
+static struct spear_function can1_function = {
+        .name = "can1",
+        .groups = can1_grps,
+        .ngroups = ARRAY_SIZE(can1_grps),
+};
+
+/* Pad multiplexing for PWM0_1 device */
+static const unsigned pwm0_1_pins[][2] = { { 37, 38 }, { 14, 15 }, { 8, 9 },
+        { 30, 31 }, { 42, 43 }, { 59, 60 }, { 88, 89 } };
+
+static struct spear_muxreg pwm0_1_pin_8_9_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_SSP_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_0_9_REG,
+                .mask = PMX_PL_8_9_MASK,
+                .val = PMX_PWM_0_1_PL_8_9_VAL,
+        },
+};
+
+static struct spear_muxreg pwm0_1_autoexpsmallpri_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_MII_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_muxreg pwm0_1_pin_14_15_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_10_19_REG,
+                .mask = PMX_PL_14_MASK | PMX_PL_15_MASK,
+                .val = PMX_PWM1_PL_14_VAL | PMX_PWM0_PL_15_VAL,
+        },
+};
+
+static struct spear_muxreg pwm0_1_pin_30_31_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_30_39_REG,
+                .mask = PMX_PL_30_MASK | PMX_PL_31_MASK,
+                .val = PMX_PWM1_EXT_PL_30_VAL | PMX_PWM0_EXT_PL_31_VAL,
+        },
+};
+
+static struct spear_muxreg pwm0_1_net_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_UART0_MODEM_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_muxreg pwm0_1_pin_37_38_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_30_39_REG,
+                .mask = PMX_PL_37_38_MASK,
+                .val = PMX_PWM0_1_PL_37_38_VAL,
+        },
+};
+
+static struct spear_muxreg pwm0_1_pin_42_43_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_0_1_MASK ,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_40_49_REG,
+                .mask = PMX_PL_42_MASK | PMX_PL_43_MASK,
+                .val = PMX_PWM1_PL_42_VAL |
+                        PMX_PWM0_PL_43_VAL,
+        },
+};
+
+static struct spear_muxreg pwm0_1_pin_59_60_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_50_59_REG,
+                .mask = PMX_PL_59_MASK,
+                .val = PMX_PWM1_PL_59_VAL,
+        }, {
+                .reg = IP_SEL_PAD_60_69_REG,
+                .mask = PMX_PL_60_MASK,
+                .val = PMX_PWM0_PL_60_VAL,
+        },
+};
+
+static struct spear_muxreg pwm0_1_pin_88_89_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_80_89_REG,
+                .mask = PMX_PL_88_89_MASK,
+                .val = PMX_PWM0_1_PL_88_89_VAL,
+        },
+};
+
+static struct spear_modemux pwm0_1_pin_8_9_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = pwm0_1_pin_8_9_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm0_1_pin_8_9_muxreg),
+        },
+};
+
+static struct spear_modemux pwm0_1_pin_14_15_modemux[] = {
+        {
+                .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | EXTENDED_MODE,
+                .muxregs = pwm0_1_autoexpsmallpri_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm0_1_autoexpsmallpri_muxreg),
+        }, {
+                .modes = EXTENDED_MODE,
+                .muxregs = pwm0_1_pin_14_15_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm0_1_pin_14_15_muxreg),
+        },
+};
+
+static struct spear_modemux pwm0_1_pin_30_31_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = pwm0_1_pin_30_31_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm0_1_pin_30_31_muxreg),
+        },
+};
+
+static struct spear_modemux pwm0_1_pin_37_38_modemux[] = {
+        {
+                .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
+                .muxregs = pwm0_1_net_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm0_1_net_muxreg),
+        }, {
+                .modes = EXTENDED_MODE,
+                .muxregs = pwm0_1_pin_37_38_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm0_1_pin_37_38_muxreg),
+        },
+};
+
+static struct spear_modemux pwm0_1_pin_42_43_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = pwm0_1_pin_42_43_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm0_1_pin_42_43_muxreg),
+        },
+};
+
+static struct spear_modemux pwm0_1_pin_59_60_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = pwm0_1_pin_59_60_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm0_1_pin_59_60_muxreg),
+        },
+};
+
+static struct spear_modemux pwm0_1_pin_88_89_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = pwm0_1_pin_88_89_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm0_1_pin_88_89_muxreg),
+        },
+};
+
+static struct spear_pingroup pwm0_1_pingroup[] = {
+        {
+                .name = "pwm0_1_pin_8_9_grp",
+                .pins = pwm0_1_pins[0],
+                .npins = ARRAY_SIZE(pwm0_1_pins[0]),
+                .modemuxs = pwm0_1_pin_8_9_modemux,
+                .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_8_9_modemux),
+        }, {
+                .name = "pwm0_1_pin_14_15_grp",
+                .pins = pwm0_1_pins[1],
+                .npins = ARRAY_SIZE(pwm0_1_pins[1]),
+                .modemuxs = pwm0_1_pin_14_15_modemux,
+                .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_14_15_modemux),
+        }, {
+                .name = "pwm0_1_pin_30_31_grp",
+                .pins = pwm0_1_pins[2],
+                .npins = ARRAY_SIZE(pwm0_1_pins[2]),
+                .modemuxs = pwm0_1_pin_30_31_modemux,
+                .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_30_31_modemux),
+        }, {
+                .name = "pwm0_1_pin_37_38_grp",
+                .pins = pwm0_1_pins[3],
+                .npins = ARRAY_SIZE(pwm0_1_pins[3]),
+                .modemuxs = pwm0_1_pin_37_38_modemux,
+                .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_37_38_modemux),
+        }, {
+                .name = "pwm0_1_pin_42_43_grp",
+                .pins = pwm0_1_pins[4],
+                .npins = ARRAY_SIZE(pwm0_1_pins[4]),
+                .modemuxs = pwm0_1_pin_42_43_modemux,
+                .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_42_43_modemux),
+        }, {
+                .name = "pwm0_1_pin_59_60_grp",
+                .pins = pwm0_1_pins[5],
+                .npins = ARRAY_SIZE(pwm0_1_pins[5]),
+                .modemuxs = pwm0_1_pin_59_60_modemux,
+                .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_59_60_modemux),
+        }, {
+                .name = "pwm0_1_pin_88_89_grp",
+                .pins = pwm0_1_pins[6],
+                .npins = ARRAY_SIZE(pwm0_1_pins[6]),
+                .modemuxs = pwm0_1_pin_88_89_modemux,
+                .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_88_89_modemux),
+        },
+};
+
+static const char *const pwm0_1_grps[] = { "pwm0_1_pin_8_9_grp",
+        "pwm0_1_pin_14_15_grp", "pwm0_1_pin_30_31_grp", "pwm0_1_pin_37_38_grp",
+        "pwm0_1_pin_42_43_grp", "pwm0_1_pin_59_60_grp", "pwm0_1_pin_88_89_grp"
+};
+
+static struct spear_function pwm0_1_function = {
+        .name = "pwm0_1",
+        .groups = pwm0_1_grps,
+        .ngroups = ARRAY_SIZE(pwm0_1_grps),
+};
+
+/* Pad multiplexing for PWM2 device */
+static const unsigned pwm2_pins[][1] = { { 7 }, { 13 }, { 29 }, { 34 }, { 41 },
+        { 58 }, { 87 } };
+static struct spear_muxreg pwm2_net_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_SSP_CS_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_muxreg pwm2_pin_7_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_0_9_REG,
+                .mask = PMX_PL_7_MASK,
+                .val = PMX_PWM_2_PL_7_VAL,
+        },
+};
+
+static struct spear_muxreg pwm2_autoexpsmallpri_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_MII_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_muxreg pwm2_pin_13_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_10_19_REG,
+                .mask = PMX_PL_13_MASK,
+                .val = PMX_PWM2_PL_13_VAL,
+        },
+};
+
+static struct spear_muxreg pwm2_pin_29_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_GPIO_PIN1_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_20_29_REG,
+                .mask = PMX_PL_29_MASK,
+                .val = PMX_PWM_2_PL_29_VAL,
+        },
+};
+
+static struct spear_muxreg pwm2_pin_34_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_SSP_CS_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_30_39_REG,
+                .mask = PMX_PL_34_MASK,
+                .val = PMX_PWM2_PL_34_VAL,
+        },
+};
+
+static struct spear_muxreg pwm2_pin_41_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_UART0_MODEM_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_40_49_REG,
+                .mask = PMX_PL_41_MASK,
+                .val = PMX_PWM2_PL_41_VAL,
+        },
+};
+
+static struct spear_muxreg pwm2_pin_58_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_50_59_REG,
+                .mask = PMX_PL_58_MASK,
+                .val = PMX_PWM2_PL_58_VAL,
+        },
+};
+
+static struct spear_muxreg pwm2_pin_87_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_80_89_REG,
+                .mask = PMX_PL_87_MASK,
+                .val = PMX_PWM2_PL_87_VAL,
+        },
+};
+
+static struct spear_modemux pwm2_pin_7_modemux[] = {
+        {
+                .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
+                .muxregs = pwm2_net_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm2_net_muxreg),
+        }, {
+                .modes = EXTENDED_MODE,
+                .muxregs = pwm2_pin_7_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm2_pin_7_muxreg),
+        },
+};
+static struct spear_modemux pwm2_pin_13_modemux[] = {
+        {
+                .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | EXTENDED_MODE,
+                .muxregs = pwm2_autoexpsmallpri_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm2_autoexpsmallpri_muxreg),
+        }, {
+                .modes = EXTENDED_MODE,
+                .muxregs = pwm2_pin_13_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm2_pin_13_muxreg),
+        },
+};
+static struct spear_modemux pwm2_pin_29_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = pwm2_pin_29_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm2_pin_29_muxreg),
+        },
+};
+static struct spear_modemux pwm2_pin_34_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = pwm2_pin_34_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm2_pin_34_muxreg),
+        },
+};
+
+static struct spear_modemux pwm2_pin_41_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = pwm2_pin_41_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm2_pin_41_muxreg),
+        },
+};
+
+static struct spear_modemux pwm2_pin_58_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = pwm2_pin_58_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm2_pin_58_muxreg),
+        },
+};
+
+static struct spear_modemux pwm2_pin_87_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = pwm2_pin_87_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm2_pin_87_muxreg),
+        },
+};
+
+static struct spear_pingroup pwm2_pingroup[] = {
+        {
+                .name = "pwm2_pin_7_grp",
+                .pins = pwm2_pins[0],
+                .npins = ARRAY_SIZE(pwm2_pins[0]),
+                .modemuxs = pwm2_pin_7_modemux,
+                .nmodemuxs = ARRAY_SIZE(pwm2_pin_7_modemux),
+        }, {
+                .name = "pwm2_pin_13_grp",
+                .pins = pwm2_pins[1],
+                .npins = ARRAY_SIZE(pwm2_pins[1]),
+                .modemuxs = pwm2_pin_13_modemux,
+                .nmodemuxs = ARRAY_SIZE(pwm2_pin_13_modemux),
+        }, {
+                .name = "pwm2_pin_29_grp",
+                .pins = pwm2_pins[2],
+                .npins = ARRAY_SIZE(pwm2_pins[2]),
+                .modemuxs = pwm2_pin_29_modemux,
+                .nmodemuxs = ARRAY_SIZE(pwm2_pin_29_modemux),
+        }, {
+                .name = "pwm2_pin_34_grp",
+                .pins = pwm2_pins[3],
+                .npins = ARRAY_SIZE(pwm2_pins[3]),
+                .modemuxs = pwm2_pin_34_modemux,
+                .nmodemuxs = ARRAY_SIZE(pwm2_pin_34_modemux),
+        }, {
+                .name = "pwm2_pin_41_grp",
+                .pins = pwm2_pins[4],
+                .npins = ARRAY_SIZE(pwm2_pins[4]),
+                .modemuxs = pwm2_pin_41_modemux,
+                .nmodemuxs = ARRAY_SIZE(pwm2_pin_41_modemux),
+        }, {
+                .name = "pwm2_pin_58_grp",
+                .pins = pwm2_pins[5],
+                .npins = ARRAY_SIZE(pwm2_pins[5]),
+                .modemuxs = pwm2_pin_58_modemux,
+                .nmodemuxs = ARRAY_SIZE(pwm2_pin_58_modemux),
+        }, {
+                .name = "pwm2_pin_87_grp",
+                .pins = pwm2_pins[6],
+                .npins = ARRAY_SIZE(pwm2_pins[6]),
+                .modemuxs = pwm2_pin_87_modemux,
+                .nmodemuxs = ARRAY_SIZE(pwm2_pin_87_modemux),
+        },
+};
+
+static const char *const pwm2_grps[] = { "pwm2_pin_7_grp", "pwm2_pin_13_grp",
+        "pwm2_pin_29_grp", "pwm2_pin_34_grp", "pwm2_pin_41_grp",
+        "pwm2_pin_58_grp", "pwm2_pin_87_grp" };
+static struct spear_function pwm2_function = {
+        .name = "pwm2",
+        .groups = pwm2_grps,
+        .ngroups = ARRAY_SIZE(pwm2_grps),
+};
+
+/* Pad multiplexing for PWM3 device */
+static const unsigned pwm3_pins[][1] = { { 6 }, { 12 }, { 28 }, { 40 }, { 57 },
+        { 86 } };
+static struct spear_muxreg pwm3_pin_6_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_SSP_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_0_9_REG,
+                .mask = PMX_PL_6_MASK,
+                .val = PMX_PWM_3_PL_6_VAL,
+        },
+};
+
+static struct spear_muxreg pwm3_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_MII_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_muxreg pwm3_pin_12_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_10_19_REG,
+                .mask = PMX_PL_12_MASK,
+                .val = PMX_PWM3_PL_12_VAL,
+        },
+};
+
+static struct spear_muxreg pwm3_pin_28_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_GPIO_PIN0_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_20_29_REG,
+                .mask = PMX_PL_28_MASK,
+                .val = PMX_PWM_3_PL_28_VAL,
+        },
+};
+
+static struct spear_muxreg pwm3_pin_40_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_UART0_MODEM_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_40_49_REG,
+                .mask = PMX_PL_40_MASK,
+                .val = PMX_PWM3_PL_40_VAL,
+        },
+};
+
+static struct spear_muxreg pwm3_pin_57_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_50_59_REG,
+                .mask = PMX_PL_57_MASK,
+                .val = PMX_PWM3_PL_57_VAL,
+        },
+};
+
+static struct spear_muxreg pwm3_pin_86_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_80_89_REG,
+                .mask = PMX_PL_86_MASK,
+                .val = PMX_PWM3_PL_86_VAL,
+        },
+};
+
+static struct spear_modemux pwm3_pin_6_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = pwm3_pin_6_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm3_pin_6_muxreg),
+        },
+};
+
+static struct spear_modemux pwm3_pin_12_modemux[] = {
+        {
+                .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE |
+                        AUTO_NET_SMII_MODE | EXTENDED_MODE,
+                .muxregs = pwm3_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm3_muxreg),
+        }, {
+                .modes = EXTENDED_MODE,
+                .muxregs = pwm3_pin_12_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm3_pin_12_muxreg),
+        },
+};
+
+static struct spear_modemux pwm3_pin_28_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = pwm3_pin_28_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm3_pin_28_muxreg),
+        },
+};
+
+static struct spear_modemux pwm3_pin_40_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = pwm3_pin_40_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm3_pin_40_muxreg),
+        },
+};
+
+static struct spear_modemux pwm3_pin_57_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = pwm3_pin_57_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm3_pin_57_muxreg),
+        },
+};
+
+static struct spear_modemux pwm3_pin_86_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = pwm3_pin_86_muxreg,
+                .nmuxregs = ARRAY_SIZE(pwm3_pin_86_muxreg),
+        },
+};
+
+static struct spear_pingroup pwm3_pingroup[] = {
+        {
+                .name = "pwm3_pin_6_grp",
+                .pins = pwm3_pins[0],
+                .npins = ARRAY_SIZE(pwm3_pins[0]),
+                .modemuxs = pwm3_pin_6_modemux,
+                .nmodemuxs = ARRAY_SIZE(pwm3_pin_6_modemux),
+        }, {
+                .name = "pwm3_pin_12_grp",
+                .pins = pwm3_pins[1],
+                .npins = ARRAY_SIZE(pwm3_pins[1]),
+                .modemuxs = pwm3_pin_12_modemux,
+                .nmodemuxs = ARRAY_SIZE(pwm3_pin_12_modemux),
+        }, {
+                .name = "pwm3_pin_28_grp",
+                .pins = pwm3_pins[2],
+                .npins = ARRAY_SIZE(pwm3_pins[2]),
+                .modemuxs = pwm3_pin_28_modemux,
+                .nmodemuxs = ARRAY_SIZE(pwm3_pin_28_modemux),
+        }, {
+                .name = "pwm3_pin_40_grp",
+                .pins = pwm3_pins[3],
+                .npins = ARRAY_SIZE(pwm3_pins[3]),
+                .modemuxs = pwm3_pin_40_modemux,
+                .nmodemuxs = ARRAY_SIZE(pwm3_pin_40_modemux),
+        }, {
+                .name = "pwm3_pin_57_grp",
+                .pins = pwm3_pins[4],
+                .npins = ARRAY_SIZE(pwm3_pins[4]),
+                .modemuxs = pwm3_pin_57_modemux,
+                .nmodemuxs = ARRAY_SIZE(pwm3_pin_57_modemux),
+        }, {
+                .name = "pwm3_pin_86_grp",
+                .pins = pwm3_pins[5],
+                .npins = ARRAY_SIZE(pwm3_pins[5]),
+                .modemuxs = pwm3_pin_86_modemux,
+                .nmodemuxs = ARRAY_SIZE(pwm3_pin_86_modemux),
+        },
+};
+
+static const char *const pwm3_grps[] = { "pwm3_pin_6_grp", "pwm3_pin_12_grp",
+        "pwm3_pin_28_grp", "pwm3_pin_40_grp", "pwm3_pin_57_grp",
+        "pwm3_pin_86_grp" };
+static struct spear_function pwm3_function = {
+        .name = "pwm3",
+        .groups = pwm3_grps,
+        .ngroups = ARRAY_SIZE(pwm3_grps),
+};
+
+/* Pad multiplexing for SSP1 device */
+static const unsigned ssp1_pins[][2] = { { 17, 20 }, { 36, 39 }, { 48, 51 },
+        { 65, 68 }, { 94, 97 } };
+static struct spear_muxreg ssp1_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_MII_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_muxreg ssp1_ext_17_20_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_10_19_REG,
+                .mask = PMX_PL_17_18_MASK | PMX_PL_19_MASK,
+                .val = PMX_SSP1_PL_17_18_19_20_VAL,
+        }, {
+                .reg = IP_SEL_PAD_20_29_REG,
+                .mask = PMX_PL_20_MASK,
+                .val = PMX_SSP1_PL_17_18_19_20_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_SSP1_PORT_SEL_MASK,
+                .val = PMX_SSP1_PORT_17_TO_20_VAL,
+        },
+};
+
+static struct spear_muxreg ssp1_ext_36_39_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_30_39_REG,
+                .mask = PMX_PL_36_MASK | PMX_PL_37_38_MASK | PMX_PL_39_MASK,
+                .val = PMX_SSP1_PL_36_VAL | PMX_SSP1_PL_37_38_VAL |
+                        PMX_SSP1_PL_39_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_SSP1_PORT_SEL_MASK,
+                .val = PMX_SSP1_PORT_36_TO_39_VAL,
+        },
+};
+
+static struct spear_muxreg ssp1_ext_48_51_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_40_49_REG,
+                .mask = PMX_PL_48_49_MASK,
+                .val = PMX_SSP1_PL_48_49_VAL,
+        }, {
+                .reg = IP_SEL_PAD_50_59_REG,
+                .mask = PMX_PL_50_51_MASK,
+                .val = PMX_SSP1_PL_50_51_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_SSP1_PORT_SEL_MASK,
+                .val = PMX_SSP1_PORT_48_TO_51_VAL,
+        },
+};
+
+static struct spear_muxreg ssp1_ext_65_68_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_60_69_REG,
+                .mask = PMX_PL_65_TO_68_MASK,
+                .val = PMX_SSP1_PL_65_TO_68_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_SSP1_PORT_SEL_MASK,
+                .val = PMX_SSP1_PORT_65_TO_68_VAL,
+        },
+};
+
+static struct spear_muxreg ssp1_ext_94_97_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_90_99_REG,
+                .mask = PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
+                .val = PMX_SSP1_PL_94_95_VAL | PMX_SSP1_PL_96_97_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_SSP1_PORT_SEL_MASK,
+                .val = PMX_SSP1_PORT_94_TO_97_VAL,
+        },
+};
+
+static struct spear_modemux ssp1_17_20_modemux[] = {
+        {
+                .modes = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE |
+                        EXTENDED_MODE,
+                .muxregs = ssp1_muxreg,
+                .nmuxregs = ARRAY_SIZE(ssp1_muxreg),
+        }, {
+                .modes = EXTENDED_MODE,
+                .muxregs = ssp1_ext_17_20_muxreg,
+                .nmuxregs = ARRAY_SIZE(ssp1_ext_17_20_muxreg),
+        },
+};
+
+static struct spear_modemux ssp1_36_39_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = ssp1_ext_36_39_muxreg,
+                .nmuxregs = ARRAY_SIZE(ssp1_ext_36_39_muxreg),
+        },
+};
+
+static struct spear_modemux ssp1_48_51_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = ssp1_ext_48_51_muxreg,
+                .nmuxregs = ARRAY_SIZE(ssp1_ext_48_51_muxreg),
+        },
+};
+static struct spear_modemux ssp1_65_68_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = ssp1_ext_65_68_muxreg,
+                .nmuxregs = ARRAY_SIZE(ssp1_ext_65_68_muxreg),
+        },
+};
+
+static struct spear_modemux ssp1_94_97_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = ssp1_ext_94_97_muxreg,
+                .nmuxregs = ARRAY_SIZE(ssp1_ext_94_97_muxreg),
+        },
+};
+
+static struct spear_pingroup ssp1_pingroup[] = {
+        {
+                .name = "ssp1_17_20_grp",
+                .pins = ssp1_pins[0],
+                .npins = ARRAY_SIZE(ssp1_pins[0]),
+                .modemuxs = ssp1_17_20_modemux,
+                .nmodemuxs = ARRAY_SIZE(ssp1_17_20_modemux),
+        }, {
+                .name = "ssp1_36_39_grp",
+                .pins = ssp1_pins[1],
+                .npins = ARRAY_SIZE(ssp1_pins[1]),
+                .modemuxs = ssp1_36_39_modemux,
+                .nmodemuxs = ARRAY_SIZE(ssp1_36_39_modemux),
+        }, {
+                .name = "ssp1_48_51_grp",
+                .pins = ssp1_pins[2],
+                .npins = ARRAY_SIZE(ssp1_pins[2]),
+                .modemuxs = ssp1_48_51_modemux,
+                .nmodemuxs = ARRAY_SIZE(ssp1_48_51_modemux),
+        }, {
+                .name = "ssp1_65_68_grp",
+                .pins = ssp1_pins[3],
+                .npins = ARRAY_SIZE(ssp1_pins[3]),
+                .modemuxs = ssp1_65_68_modemux,
+                .nmodemuxs = ARRAY_SIZE(ssp1_65_68_modemux),
+        }, {
+                .name = "ssp1_94_97_grp",
+                .pins = ssp1_pins[4],
+                .npins = ARRAY_SIZE(ssp1_pins[4]),
+                .modemuxs = ssp1_94_97_modemux,
+                .nmodemuxs = ARRAY_SIZE(ssp1_94_97_modemux),
+        },
+};
+
+static const char *const ssp1_grps[] = { "ssp1_17_20_grp", "ssp1_36_39_grp",
+        "ssp1_48_51_grp", "ssp1_65_68_grp", "ssp1_94_97_grp"
+};
+static struct spear_function ssp1_function = {
+        .name = "ssp1",
+        .groups = ssp1_grps,
+        .ngroups = ARRAY_SIZE(ssp1_grps),
+};
+
+/* Pad multiplexing for SSP2 device */
+static const unsigned ssp2_pins[][2] = { { 13, 16 }, { 32, 35 }, { 44, 47 },
+        { 61, 64 }, { 90, 93 } };
+static struct spear_muxreg ssp2_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_MII_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_muxreg ssp2_ext_13_16_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_10_19_REG,
+                .mask = PMX_PL_13_14_MASK | PMX_PL_15_16_MASK,
+                .val = PMX_SSP2_PL_13_14_15_16_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_SSP2_PORT_SEL_MASK,
+                .val = PMX_SSP2_PORT_13_TO_16_VAL,
+        },
+};
+
+static struct spear_muxreg ssp2_ext_32_35_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_SSP_CS_MASK | PMX_GPIO_PIN4_MASK |
+                        PMX_GPIO_PIN5_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_30_39_REG,
+                .mask = PMX_PL_32_33_MASK | PMX_PL_34_MASK | PMX_PL_35_MASK,
+                .val = PMX_SSP2_PL_32_33_VAL | PMX_SSP2_PL_34_VAL |
+                        PMX_SSP2_PL_35_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_SSP2_PORT_SEL_MASK,
+                .val = PMX_SSP2_PORT_32_TO_35_VAL,
+        },
+};
+
+static struct spear_muxreg ssp2_ext_44_47_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_40_49_REG,
+                .mask = PMX_PL_44_45_MASK | PMX_PL_46_47_MASK,
+                .val = PMX_SSP2_PL_44_45_VAL | PMX_SSP2_PL_46_47_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_SSP2_PORT_SEL_MASK,
+                .val = PMX_SSP2_PORT_44_TO_47_VAL,
+        },
+};
+
+static struct spear_muxreg ssp2_ext_61_64_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_60_69_REG,
+                .mask = PMX_PL_61_TO_64_MASK,
+                .val = PMX_SSP2_PL_61_TO_64_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_SSP2_PORT_SEL_MASK,
+                .val = PMX_SSP2_PORT_61_TO_64_VAL,
+        },
+};
+
+static struct spear_muxreg ssp2_ext_90_93_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_90_99_REG,
+                .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK,
+                .val = PMX_SSP2_PL_90_91_VAL | PMX_SSP2_PL_92_93_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_SSP2_PORT_SEL_MASK,
+                .val = PMX_SSP2_PORT_90_TO_93_VAL,
+        },
+};
+
+static struct spear_modemux ssp2_13_16_modemux[] = {
+        {
+                .modes = AUTO_NET_SMII_MODE | EXTENDED_MODE,
+                .muxregs = ssp2_muxreg,
+                .nmuxregs = ARRAY_SIZE(ssp2_muxreg),
+        }, {
+                .modes = EXTENDED_MODE,
+                .muxregs = ssp2_ext_13_16_muxreg,
+                .nmuxregs = ARRAY_SIZE(ssp2_ext_13_16_muxreg),
+        },
+};
+
+static struct spear_modemux ssp2_32_35_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = ssp2_ext_32_35_muxreg,
+                .nmuxregs = ARRAY_SIZE(ssp2_ext_32_35_muxreg),
+        },
+};
+
+static struct spear_modemux ssp2_44_47_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = ssp2_ext_44_47_muxreg,
+                .nmuxregs = ARRAY_SIZE(ssp2_ext_44_47_muxreg),
+        },
+};
+
+static struct spear_modemux ssp2_61_64_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = ssp2_ext_61_64_muxreg,
+                .nmuxregs = ARRAY_SIZE(ssp2_ext_61_64_muxreg),
+        },
+};
+
+static struct spear_modemux ssp2_90_93_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = ssp2_ext_90_93_muxreg,
+                .nmuxregs = ARRAY_SIZE(ssp2_ext_90_93_muxreg),
+        },
+};
+
+static struct spear_pingroup ssp2_pingroup[] = {
+        {
+                .name = "ssp2_13_16_grp",
+                .pins = ssp2_pins[0],
+                .npins = ARRAY_SIZE(ssp2_pins[0]),
+                .modemuxs = ssp2_13_16_modemux,
+                .nmodemuxs = ARRAY_SIZE(ssp2_13_16_modemux),
+        }, {
+                .name = "ssp2_32_35_grp",
+                .pins = ssp2_pins[1],
+                .npins = ARRAY_SIZE(ssp2_pins[1]),
+                .modemuxs = ssp2_32_35_modemux,
+                .nmodemuxs = ARRAY_SIZE(ssp2_32_35_modemux),
+        }, {
+                .name = "ssp2_44_47_grp",
+                .pins = ssp2_pins[2],
+                .npins = ARRAY_SIZE(ssp2_pins[2]),
+                .modemuxs = ssp2_44_47_modemux,
+                .nmodemuxs = ARRAY_SIZE(ssp2_44_47_modemux),
+        }, {
+                .name = "ssp2_61_64_grp",
+                .pins = ssp2_pins[3],
+                .npins = ARRAY_SIZE(ssp2_pins[3]),
+                .modemuxs = ssp2_61_64_modemux,
+                .nmodemuxs = ARRAY_SIZE(ssp2_61_64_modemux),
+        }, {
+                .name = "ssp2_90_93_grp",
+                .pins = ssp2_pins[4],
+                .npins = ARRAY_SIZE(ssp2_pins[4]),
+                .modemuxs = ssp2_90_93_modemux,
+                .nmodemuxs = ARRAY_SIZE(ssp2_90_93_modemux),
+        },
+};
+
+static const char *const ssp2_grps[] = { "ssp2_13_16_grp", "ssp2_32_35_grp",
+        "ssp2_44_47_grp", "ssp2_61_64_grp", "ssp2_90_93_grp" };
+static struct spear_function ssp2_function = {
+        .name = "ssp2",
+        .groups = ssp2_grps,
+        .ngroups = ARRAY_SIZE(ssp2_grps),
+};
+
+/* Pad multiplexing for cadence mii2 as mii device */
+static const unsigned mii2_pins[] = { 80, 81, 82, 83, 84, 85, 86, 87, 88, 89,
+        90, 91, 92, 93, 94, 95, 96, 97 };
+static struct spear_muxreg mii2_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_80_89_REG,
+                .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
+                        PMX_PL_88_89_MASK,
+                .val = PMX_MII2_PL_80_TO_85_VAL | PMX_MII2_PL_86_87_VAL |
+                        PMX_MII2_PL_88_89_VAL,
+        }, {
+                .reg = IP_SEL_PAD_90_99_REG,
+                .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
+                        PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
+                .val = PMX_MII2_PL_90_91_VAL | PMX_MII2_PL_92_93_VAL |
+                        PMX_MII2_PL_94_95_VAL | PMX_MII2_PL_96_97_VAL,
+        }, {
+                .reg = EXT_CTRL_REG,
+                .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
+                        (MAC_MODE_MASK << MAC1_MODE_SHIFT) |
+                        MII_MDIO_MASK,
+                .val = (MAC_MODE_MII << MAC2_MODE_SHIFT) |
+                        (MAC_MODE_MII << MAC1_MODE_SHIFT) |
+                        MII_MDIO_81_VAL,
+        },
+};
+
+static struct spear_modemux mii2_modemux[] = {
+        {
+                .modes = EXTENDED_MODE,
+                .muxregs = mii2_muxreg,
+                .nmuxregs = ARRAY_SIZE(mii2_muxreg),
+        },
+};
+
+static struct spear_pingroup mii2_pingroup = {
+        .name = "mii2_grp",
+        .pins = mii2_pins,
+        .npins = ARRAY_SIZE(mii2_pins),
+        .modemuxs = mii2_modemux,
+        .nmodemuxs = ARRAY_SIZE(mii2_modemux),
+};
+
+static const char *const mii2_grps[] = { "mii2_grp" };
+static struct spear_function mii2_function = {
+        .name = "mii2",
+        .groups = mii2_grps,
+        .ngroups = ARRAY_SIZE(mii2_grps),
+};
+
+/* Pad multiplexing for cadence mii 1_2 as smii or rmii device */
+static const unsigned smii0_1_pins[] = { 10, 11, 13, 14, 15, 16, 17, 18, 19, 20,
+        21, 22, 23, 24, 25, 26, 27 };
+static const unsigned rmii0_1_pins[] = { 10, 11, 21, 22, 23, 24, 25, 26, 27 };
+static struct spear_muxreg mii0_1_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_MII_MASK,
+                .val = 0,
+        },
+};
+
+static struct spear_muxreg smii0_1_ext_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_10_19_REG,
+                .mask = PMX_PL_10_11_MASK,
+                .val = PMX_SMII_PL_10_11_VAL,
+        }, {
+                .reg = IP_SEL_PAD_20_29_REG,
+                .mask = PMX_PL_21_TO_27_MASK,
+                .val = PMX_SMII_PL_21_TO_27_VAL,
+        }, {
+                .reg = EXT_CTRL_REG,
+                .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
+                        (MAC_MODE_MASK << MAC1_MODE_SHIFT) |
+                        MII_MDIO_MASK,
+                .val = (MAC_MODE_SMII << MAC2_MODE_SHIFT)
+                        | (MAC_MODE_SMII << MAC1_MODE_SHIFT)
+                        | MII_MDIO_10_11_VAL,
+        },
+};
+
+static struct spear_muxreg rmii0_1_ext_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_10_19_REG,
+                .mask = PMX_PL_10_11_MASK | PMX_PL_13_14_MASK |
+                        PMX_PL_15_16_MASK | PMX_PL_17_18_MASK | PMX_PL_19_MASK,
+                .val = PMX_RMII_PL_10_11_VAL | PMX_RMII_PL_13_14_VAL |
+                        PMX_RMII_PL_15_16_VAL | PMX_RMII_PL_17_18_VAL |
+                        PMX_RMII_PL_19_VAL,
+        }, {
+                .reg = IP_SEL_PAD_20_29_REG,
+                .mask = PMX_PL_20_MASK | PMX_PL_21_TO_27_MASK,
+                .val = PMX_RMII_PL_20_VAL | PMX_RMII_PL_21_TO_27_VAL,
+        }, {
+                .reg = EXT_CTRL_REG,
+                .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
+                        (MAC_MODE_MASK << MAC1_MODE_SHIFT) |
+                        MII_MDIO_MASK,
+                .val = (MAC_MODE_RMII << MAC2_MODE_SHIFT)
+                        | (MAC_MODE_RMII << MAC1_MODE_SHIFT)
+                        | MII_MDIO_10_11_VAL,
+        },
+};
+
+static struct spear_modemux mii0_1_modemux[][2] = {
+        {
+                /* configure as smii */
+                {
+                        .modes = AUTO_NET_SMII_MODE | AUTO_EXP_MODE |
+                                SMALL_PRINTERS_MODE | EXTENDED_MODE,
+                        .muxregs = mii0_1_muxreg,
+                        .nmuxregs = ARRAY_SIZE(mii0_1_muxreg),
+                }, {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = smii0_1_ext_muxreg,
+                        .nmuxregs = ARRAY_SIZE(smii0_1_ext_muxreg),
+                },
+        }, {
+                /* configure as rmii */
+                {
+                        .modes = AUTO_NET_SMII_MODE | AUTO_EXP_MODE |
+                                SMALL_PRINTERS_MODE | EXTENDED_MODE,
+                        .muxregs = mii0_1_muxreg,
+                        .nmuxregs = ARRAY_SIZE(mii0_1_muxreg),
+                }, {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = rmii0_1_ext_muxreg,
+                        .nmuxregs = ARRAY_SIZE(rmii0_1_ext_muxreg),
+                },
+        },
+};
+
+static struct spear_pingroup mii0_1_pingroup[] = {
+        {
+                .name = "smii0_1_grp",
+                .pins = smii0_1_pins,
+                .npins = ARRAY_SIZE(smii0_1_pins),
+                .modemuxs = mii0_1_modemux[0],
+                .nmodemuxs = ARRAY_SIZE(mii0_1_modemux[0]),
+        }, {
+                .name = "rmii0_1_grp",
+                .pins = rmii0_1_pins,
+                .npins = ARRAY_SIZE(rmii0_1_pins),
+                .modemuxs = mii0_1_modemux[1],
+                .nmodemuxs = ARRAY_SIZE(mii0_1_modemux[1]),
+        },
+};
+
+static const char *const mii0_1_grps[] = { "smii0_1_grp", "rmii0_1_grp" };
+static struct spear_function mii0_1_function = {
+        .name = "mii0_1",
+        .groups = mii0_1_grps,
+        .ngroups = ARRAY_SIZE(mii0_1_grps),
+};
+
+/* Pad multiplexing for i2c1 device */
+static const unsigned i2c1_pins[][2] = { { 8, 9 }, { 98, 99 } };
+static struct spear_muxreg i2c1_ext_8_9_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_SSP_CS_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_0_9_REG,
+                .mask = PMX_PL_8_9_MASK,
+                .val = PMX_I2C1_PL_8_9_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_I2C1_PORT_SEL_MASK,
+                .val = PMX_I2C1_PORT_8_9_VAL,
+        },
+};
+
+static struct spear_muxreg i2c1_ext_98_99_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_90_99_REG,
+                .mask = PMX_PL_98_MASK | PMX_PL_99_MASK,
+                .val = PMX_I2C1_PL_98_VAL | PMX_I2C1_PL_99_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_I2C1_PORT_SEL_MASK,
+                .val = PMX_I2C1_PORT_98_99_VAL,
+        },
+};
+
+static struct spear_modemux i2c1_modemux[][1] = {
+        {
+                /* Select signals on pins 8-9 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = i2c1_ext_8_9_muxreg,
+                        .nmuxregs = ARRAY_SIZE(i2c1_ext_8_9_muxreg),
+                },
+        }, {
+                /* Select signals on pins 98-99 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = i2c1_ext_98_99_muxreg,
+                        .nmuxregs = ARRAY_SIZE(i2c1_ext_98_99_muxreg),
+                },
+        },
+};
+
+static struct spear_pingroup i2c1_pingroup[] = {
+        {
+                .name = "i2c1_8_9_grp",
+                .pins = i2c1_pins[0],
+                .npins = ARRAY_SIZE(i2c1_pins[0]),
+                .modemuxs = i2c1_modemux[0],
+                .nmodemuxs = ARRAY_SIZE(i2c1_modemux[0]),
+        }, {
+                .name = "i2c1_98_99_grp",
+                .pins = i2c1_pins[1],
+                .npins = ARRAY_SIZE(i2c1_pins[1]),
+                .modemuxs = i2c1_modemux[1],
+                .nmodemuxs = ARRAY_SIZE(i2c1_modemux[1]),
+        },
+};
+
+static const char *const i2c1_grps[] = { "i2c1_8_9_grp", "i2c1_98_99_grp" };
+static struct spear_function i2c1_function = {
+        .name = "i2c1",
+        .groups = i2c1_grps,
+        .ngroups = ARRAY_SIZE(i2c1_grps),
+};
+
+/* Pad multiplexing for i2c2 device */
+static const unsigned i2c2_pins[][2] = { { 0, 1 }, { 2, 3 }, { 19, 20 },
+        { 75, 76 }, { 96, 97 } };
+static struct spear_muxreg i2c2_ext_0_1_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_FIRDA_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_0_9_REG,
+                .mask = PMX_PL_0_1_MASK,
+                .val = PMX_I2C2_PL_0_1_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_I2C2_PORT_SEL_MASK,
+                .val = PMX_I2C2_PORT_0_1_VAL,
+        },
+};
+
+static struct spear_muxreg i2c2_ext_2_3_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_UART0_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_0_9_REG,
+                .mask = PMX_PL_2_3_MASK,
+                .val = PMX_I2C2_PL_2_3_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_I2C2_PORT_SEL_MASK,
+                .val = PMX_I2C2_PORT_2_3_VAL,
+        },
+};
+
+static struct spear_muxreg i2c2_ext_19_20_muxreg[] = {
+        {
+                .reg = PMX_CONFIG_REG,
+                .mask = PMX_MII_MASK,
+                .val = 0,
+        }, {
+                .reg = IP_SEL_PAD_10_19_REG,
+                .mask = PMX_PL_19_MASK,
+                .val = PMX_I2C2_PL_19_VAL,
+        }, {
+                .reg = IP_SEL_PAD_20_29_REG,
+                .mask = PMX_PL_20_MASK,
+                .val = PMX_I2C2_PL_20_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_I2C2_PORT_SEL_MASK,
+                .val = PMX_I2C2_PORT_19_20_VAL,
+        },
+};
+
+static struct spear_muxreg i2c2_ext_75_76_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_70_79_REG,
+                .mask = PMX_PL_75_76_MASK,
+                .val = PMX_I2C2_PL_75_76_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_I2C2_PORT_SEL_MASK,
+                .val = PMX_I2C2_PORT_75_76_VAL,
+        },
+};
+
+static struct spear_muxreg i2c2_ext_96_97_muxreg[] = {
+        {
+                .reg = IP_SEL_PAD_90_99_REG,
+                .mask = PMX_PL_96_97_MASK,
+                .val = PMX_I2C2_PL_96_97_VAL,
+        }, {
+                .reg = IP_SEL_MIX_PAD_REG,
+                .mask = PMX_I2C2_PORT_SEL_MASK,
+                .val = PMX_I2C2_PORT_96_97_VAL,
+        },
+};
+
+static struct spear_modemux i2c2_modemux[][1] = {
+        {
+                /* Select signals on pins 0_1 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = i2c2_ext_0_1_muxreg,
+                        .nmuxregs = ARRAY_SIZE(i2c2_ext_0_1_muxreg),
+                },
+        }, {
+                /* Select signals on pins 2_3 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = i2c2_ext_2_3_muxreg,
+                        .nmuxregs = ARRAY_SIZE(i2c2_ext_2_3_muxreg),
+                },
+        }, {
+                /* Select signals on pins 19_20 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = i2c2_ext_19_20_muxreg,
+                        .nmuxregs = ARRAY_SIZE(i2c2_ext_19_20_muxreg),
+                },
+        }, {
+                /* Select signals on pins 75_76 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = i2c2_ext_75_76_muxreg,
+                        .nmuxregs = ARRAY_SIZE(i2c2_ext_75_76_muxreg),
+                },
+        }, {
+                /* Select signals on pins 96_97 */
+                {
+                        .modes = EXTENDED_MODE,
+                        .muxregs = i2c2_ext_96_97_muxreg,
+                        .nmuxregs = ARRAY_SIZE(i2c2_ext_96_97_muxreg),
+                },
+        },
+};
+
+static struct spear_pingroup i2c2_pingroup[] = {
+        {
+                .name = "i2c2_0_1_grp",
+                .pins = i2c2_pins[0],
+                .npins = ARRAY_SIZE(i2c2_pins[0]),
+                .modemuxs = i2c2_modemux[0],
+                .nmodemuxs = ARRAY_SIZE(i2c2_modemux[0]),
+        }, {
+                .name = "i2c2_2_3_grp",
+                .pins = i2c2_pins[1],
+                .npins = ARRAY_SIZE(i2c2_pins[1]),
+                .modemuxs = i2c2_modemux[1],
+                .nmodemuxs = ARRAY_SIZE(i2c2_modemux[1]),
+        }, {
+                .name = "i2c2_19_20_grp",
+                .pins = i2c2_pins[2],
+                .npins = ARRAY_SIZE(i2c2_pins[2]),
+                .modemuxs = i2c2_modemux[2],
+                .nmodemuxs = ARRAY_SIZE(i2c2_modemux[2]),
+        }, {
+                .name = "i2c2_75_76_grp",
+                .pins = i2c2_pins[3],
+                .npins = ARRAY_SIZE(i2c2_pins[3]),
+                .modemuxs = i2c2_modemux[3],
+                .nmodemuxs = ARRAY_SIZE(i2c2_modemux[3]),
+        }, {
+                .name = "i2c2_96_97_grp",
+                .pins = i2c2_pins[4],
+                .npins = ARRAY_SIZE(i2c2_pins[4]),
+                .modemuxs = i2c2_modemux[4],
+                .nmodemuxs = ARRAY_SIZE(i2c2_modemux[4]),
+        },
+};
+
+static const char *const i2c2_grps[] = { "i2c2_0_1_grp", "i2c2_2_3_grp",
+        "i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp" };
+static struct spear_function i2c2_function = {
+        .name = "i2c2",
+        .groups = i2c2_grps,
+        .ngroups = ARRAY_SIZE(i2c2_grps),
+};
+
+/* pingroups */
+static struct spear_pingroup *spear320_pingroups[] = {
+        SPEAR3XX_COMMON_PINGROUPS,
+        &clcd_pingroup,
+        &emi_pingroup,
+        &fsmc_8bit_pingroup,
+        &fsmc_16bit_pingroup,
+        &spp_pingroup,
+        &sdhci_led_pingroup,
+        &sdhci_pingroup[0],
+        &sdhci_pingroup[1],
+        &i2s_pingroup,
+        &uart1_pingroup,
+        &uart1_modem_pingroup[0],
+        &uart1_modem_pingroup[1],
+        &uart1_modem_pingroup[2],
+        &uart1_modem_pingroup[3],
+        &uart2_pingroup,
+        &uart3_pingroup[0],
+        &uart3_pingroup[1],
+        &uart3_pingroup[2],
+        &uart3_pingroup[3],
+        &uart3_pingroup[4],
+        &uart3_pingroup[5],
+        &uart3_pingroup[6],
+        &uart4_pingroup[0],
+        &uart4_pingroup[1],
+        &uart4_pingroup[2],
+        &uart4_pingroup[3],
+        &uart4_pingroup[4],
+        &uart4_pingroup[5],
+        &uart5_pingroup[0],
+        &uart5_pingroup[1],
+        &uart5_pingroup[2],
+        &uart5_pingroup[3],
+        &uart6_pingroup[0],
+        &uart6_pingroup[1],
+        &rs485_pingroup,
+        &touchscreen_pingroup,
+        &can0_pingroup,
+        &can1_pingroup,
+        &pwm0_1_pingroup[0],
+        &pwm0_1_pingroup[1],
+        &pwm0_1_pingroup[2],
+        &pwm0_1_pingroup[3],
+        &pwm0_1_pingroup[4],
+        &pwm0_1_pingroup[5],
+        &pwm0_1_pingroup[6],
+        &pwm2_pingroup[0],
+        &pwm2_pingroup[1],
+        &pwm2_pingroup[2],
+        &pwm2_pingroup[3],
+        &pwm2_pingroup[4],
+        &pwm2_pingroup[5],
+        &pwm2_pingroup[6],
+        &pwm3_pingroup[0],
+        &pwm3_pingroup[1],
+        &pwm3_pingroup[2],
+        &pwm3_pingroup[3],
+        &pwm3_pingroup[4],
+        &pwm3_pingroup[5],
+        &ssp1_pingroup[0],
+        &ssp1_pingroup[1],
+        &ssp1_pingroup[2],
+        &ssp1_pingroup[3],
+        &ssp1_pingroup[4],
+        &ssp2_pingroup[0],
+        &ssp2_pingroup[1],
+        &ssp2_pingroup[2],
+        &ssp2_pingroup[3],
+        &ssp2_pingroup[4],
+        &mii2_pingroup,
+        &mii0_1_pingroup[0],
+        &mii0_1_pingroup[1],
+        &i2c1_pingroup[0],
+        &i2c1_pingroup[1],
+        &i2c2_pingroup[0],
+        &i2c2_pingroup[1],
+        &i2c2_pingroup[2],
+        &i2c2_pingroup[3],
+        &i2c2_pingroup[4],
+};
+
+/* functions */
+static struct spear_function *spear320_functions[] = {
+        SPEAR3XX_COMMON_FUNCTIONS,
+        &clcd_function,
+        &emi_function,
+        &fsmc_function,
+        &spp_function,
+        &sdhci_function,
+        &i2s_function,
+        &uart1_function,
+        &uart1_modem_function,
+        &uart2_function,
+        &uart3_function,
+        &uart4_function,
+        &uart5_function,
+        &uart6_function,
+        &rs485_function,
+        &touchscreen_function,
+        &can0_function,
+        &can1_function,
+        &pwm0_1_function,
+        &pwm2_function,
+        &pwm3_function,
+        &ssp1_function,
+        &ssp2_function,
+        &mii2_function,
+        &mii0_1_function,
+        &i2c1_function,
+        &i2c2_function,
+};
+
+static struct of_device_id spear320_pinctrl_of_match[] __devinitdata = {
+        {
+                .compatible = "st,spear320-pinmux",
+        },
+        {},
+};
+
+static int __devinit spear320_pinctrl_probe(struct platform_device *pdev)
+{
+        int ret;
+
+        spear3xx_machdata.groups = spear320_pingroups;
+        spear3xx_machdata.ngroups = ARRAY_SIZE(spear320_pingroups);
+        spear3xx_machdata.functions = spear320_functions;
+        spear3xx_machdata.nfunctions = ARRAY_SIZE(spear320_functions);
+
+        spear3xx_machdata.modes_supported = true;
+        spear3xx_machdata.pmx_modes = spear320_pmx_modes;
+        spear3xx_machdata.npmx_modes = ARRAY_SIZE(spear320_pmx_modes);
+
+        pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG);
+
+        ret = spear_pinctrl_probe(pdev, &spear3xx_machdata);
+        if (ret)
+                return ret;
+
+        return 0;
+}
+
+static int __devexit spear320_pinctrl_remove(struct platform_device *pdev)
+{
+        return spear_pinctrl_remove(pdev);
+}
+
+static struct platform_driver spear320_pinctrl_driver = {
+        .driver = {
+                .name = DRIVER_NAME,
+                .owner = THIS_MODULE,
+                .of_match_table = spear320_pinctrl_of_match,
+        },
+        .probe = spear320_pinctrl_probe,
+        .remove = __devexit_p(spear320_pinctrl_remove),
+};
+
+static int __init spear320_pinctrl_init(void)
+{
+        return platform_driver_register(&spear320_pinctrl_driver);
+}
+arch_initcall(spear320_pinctrl_init);
+
+static void __exit spear320_pinctrl_exit(void)
+{
+        platform_driver_unregister(&spear320_pinctrl_driver);
+}
+module_exit(spear320_pinctrl_exit);
+
+MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>");
+MODULE_DESCRIPTION("ST Microelectronics SPEAr320 pinctrl driver");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, spear320_pinctrl_of_match);
diff --git a/drivers/pinctrl/spear/pinctrl-spear3xx.c b/drivers/pinctrl/spear/pinctrl-spear3xx.c
new file mode 100644
index 000000000000..91c883bc46a6
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear3xx.c
@@ -0,0 +1,487 @@
+/*
+ * Driver for the ST Microelectronics SPEAr3xx pinmux
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-spear3xx.h"
+
+/* pins */
+static const struct pinctrl_pin_desc spear3xx_pins[] = {
+        SPEAR_PIN_0_TO_101,
+};
+
+/* firda_pins */
+static const unsigned firda_pins[] = { 0, 1 };
+static struct spear_muxreg firda_muxreg[] = {
+        {
+                .reg = -1,
+                .mask = PMX_FIRDA_MASK,
+                .val = PMX_FIRDA_MASK,
+        },
+};
+
+static struct spear_modemux firda_modemux[] = {
+        {
+                .modes = ~0,
+                .muxregs = firda_muxreg,
+                .nmuxregs = ARRAY_SIZE(firda_muxreg),
+        },
+};
+
+struct spear_pingroup spear3xx_firda_pingroup = {
+        .name = "firda_grp",
+        .pins = firda_pins,
+        .npins = ARRAY_SIZE(firda_pins),
+        .modemuxs = firda_modemux,
+        .nmodemuxs = ARRAY_SIZE(firda_modemux),
+};
+
+static const char *const firda_grps[] = { "firda_grp" };
+struct spear_function spear3xx_firda_function = {
+        .name = "firda",
+        .groups = firda_grps,
+        .ngroups = ARRAY_SIZE(firda_grps),
+};
+
+/* i2c_pins */
+static const unsigned i2c_pins[] = { 4, 5 };
+static struct spear_muxreg i2c_muxreg[] = {
+        {
+                .reg = -1,
+                .mask = PMX_I2C_MASK,
+                .val = PMX_I2C_MASK,
+        },
+};
+
+static struct spear_modemux i2c_modemux[] = {
+        {
+                .modes = ~0,
+                .muxregs = i2c_muxreg,
+                .nmuxregs = ARRAY_SIZE(i2c_muxreg),
+        },
+};
+
+struct spear_pingroup spear3xx_i2c_pingroup = {
+        .name = "i2c0_grp",
+        .pins = i2c_pins,
+        .npins = ARRAY_SIZE(i2c_pins),
+        .modemuxs = i2c_modemux,
+        .nmodemuxs = ARRAY_SIZE(i2c_modemux),
+};
+
+static const char *const i2c_grps[] = { "i2c0_grp" };
+struct spear_function spear3xx_i2c_function = {
+        .name = "i2c0",
+        .groups = i2c_grps,
+        .ngroups = ARRAY_SIZE(i2c_grps),
+};
+
+/* ssp_cs_pins */
+static const unsigned ssp_cs_pins[] = { 34, 35, 36 };
+static struct spear_muxreg ssp_cs_muxreg[] = {
+        {
+                .reg = -1,
+                .mask = PMX_SSP_CS_MASK,
+                .val = PMX_SSP_CS_MASK,
+        },
+};
+
+static struct spear_modemux ssp_cs_modemux[] = {
+        {
+                .modes = ~0,
+                .muxregs = ssp_cs_muxreg,
+                .nmuxregs = ARRAY_SIZE(ssp_cs_muxreg),
+        },
+};
+
+struct spear_pingroup spear3xx_ssp_cs_pingroup = {
+        .name = "ssp_cs_grp",
+        .pins = ssp_cs_pins,
+        .npins = ARRAY_SIZE(ssp_cs_pins),
+        .modemuxs = ssp_cs_modemux,
+        .nmodemuxs = ARRAY_SIZE(ssp_cs_modemux),
+};
+
+static const char *const ssp_cs_grps[] = { "ssp_cs_grp" };
+struct spear_function spear3xx_ssp_cs_function = {
+        .name = "ssp_cs",
+        .groups = ssp_cs_grps,
+        .ngroups = ARRAY_SIZE(ssp_cs_grps),
+};
+
+/* ssp_pins */
+static const unsigned ssp_pins[] = { 6, 7, 8, 9 };
+static struct spear_muxreg ssp_muxreg[] = {
+        {
+                .reg = -1,
+                .mask = PMX_SSP_MASK,
+                .val = PMX_SSP_MASK,
+        },
+};
+
+static struct spear_modemux ssp_modemux[] = {
+        {
+                .modes = ~0,
+                .muxregs = ssp_muxreg,
+                .nmuxregs = ARRAY_SIZE(ssp_muxreg),
+        },
+};
+
+struct spear_pingroup spear3xx_ssp_pingroup = {
+        .name = "ssp0_grp",
+        .pins = ssp_pins,
+        .npins = ARRAY_SIZE(ssp_pins),
+        .modemuxs = ssp_modemux,
+        .nmodemuxs = ARRAY_SIZE(ssp_modemux),
+};
+
+static const char *const ssp_grps[] = { "ssp0_grp" };
+struct spear_function spear3xx_ssp_function = {
+        .name = "ssp0",
+        .groups = ssp_grps,
+        .ngroups = ARRAY_SIZE(ssp_grps),
+};
+
+/* mii_pins */
+static const unsigned mii_pins[] = { 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
+        21, 22, 23, 24, 25, 26, 27 };
+static struct spear_muxreg mii_muxreg[] = {
+        {
+                .reg = -1,
+                .mask = PMX_MII_MASK,
+                .val = PMX_MII_MASK,
+        },
+};
+
+static struct spear_modemux mii_modemux[] = {
+        {
+                .modes = ~0,
+                .muxregs = mii_muxreg,
+                .nmuxregs = ARRAY_SIZE(mii_muxreg),
+        },
+};
+
+struct spear_pingroup spear3xx_mii_pingroup = {
+        .name = "mii0_grp",
+        .pins = mii_pins,
+        .npins = ARRAY_SIZE(mii_pins),
+        .modemuxs = mii_modemux,
+        .nmodemuxs = ARRAY_SIZE(mii_modemux),
+};
+
+static const char *const mii_grps[] = { "mii0_grp" };
+struct spear_function spear3xx_mii_function = {
+        .name = "mii0",
+        .groups = mii_grps,
+        .ngroups = ARRAY_SIZE(mii_grps),
+};
+
+/* gpio0_pin0_pins */
+static const unsigned gpio0_pin0_pins[] = { 28 };
+static struct spear_muxreg gpio0_pin0_muxreg[] = {
+        {
+                .reg = -1,
+                .mask = PMX_GPIO_PIN0_MASK,
+                .val = PMX_GPIO_PIN0_MASK,
+        },
+};
+
+static struct spear_modemux gpio0_pin0_modemux[] = {
+        {
+                .modes = ~0,
+                .muxregs = gpio0_pin0_muxreg,
+                .nmuxregs = ARRAY_SIZE(gpio0_pin0_muxreg),
+        },
+};
+
+struct spear_pingroup spear3xx_gpio0_pin0_pingroup = {
+        .name = "gpio0_pin0_grp",
+        .pins = gpio0_pin0_pins,
+        .npins = ARRAY_SIZE(gpio0_pin0_pins),
+        .modemuxs = gpio0_pin0_modemux,
+        .nmodemuxs = ARRAY_SIZE(gpio0_pin0_modemux),
+};
+
+/* gpio0_pin1_pins */
+static const unsigned gpio0_pin1_pins[] = { 29 };
+static struct spear_muxreg gpio0_pin1_muxreg[] = {
+        {
+                .reg = -1,
+                .mask = PMX_GPIO_PIN1_MASK,
+                .val = PMX_GPIO_PIN1_MASK,
+        },
+};
+
+static struct spear_modemux gpio0_pin1_modemux[] = {
+        {
+                .modes = ~0,
+                .muxregs = gpio0_pin1_muxreg,
+                .nmuxregs = ARRAY_SIZE(gpio0_pin1_muxreg),
+        },
+};
+
+struct spear_pingroup spear3xx_gpio0_pin1_pingroup = {
+        .name = "gpio0_pin1_grp",
+        .pins = gpio0_pin1_pins,
+        .npins = ARRAY_SIZE(gpio0_pin1_pins),
+        .modemuxs = gpio0_pin1_modemux,
+        .nmodemuxs = ARRAY_SIZE(gpio0_pin1_modemux),
+};
+
+/* gpio0_pin2_pins */
+static const unsigned gpio0_pin2_pins[] = { 30 };
+static struct spear_muxreg gpio0_pin2_muxreg[] = {
+        {
+                .reg = -1,
+                .mask = PMX_GPIO_PIN2_MASK,
+                .val = PMX_GPIO_PIN2_MASK,
+        },
+};
+
+static struct spear_modemux gpio0_pin2_modemux[] = {
+        {
+                .modes = ~0,
+                .muxregs = gpio0_pin2_muxreg,
+                .nmuxregs = ARRAY_SIZE(gpio0_pin2_muxreg),
+        },
+};
+
+struct spear_pingroup spear3xx_gpio0_pin2_pingroup = {
+        .name = "gpio0_pin2_grp",
+        .pins = gpio0_pin2_pins,
+        .npins = ARRAY_SIZE(gpio0_pin2_pins),
+        .modemuxs = gpio0_pin2_modemux,
+        .nmodemuxs = ARRAY_SIZE(gpio0_pin2_modemux),
+};
+
+/* gpio0_pin3_pins */
+static const unsigned gpio0_pin3_pins[] = { 31 };
+static struct spear_muxreg gpio0_pin3_muxreg[] = {
+        {
+                .reg = -1,
+                .mask = PMX_GPIO_PIN3_MASK,
+                .val = PMX_GPIO_PIN3_MASK,
+        },
+};
+
+static struct spear_modemux gpio0_pin3_modemux[] = {
+        {
+                .modes = ~0,
+                .muxregs = gpio0_pin3_muxreg,
+                .nmuxregs = ARRAY_SIZE(gpio0_pin3_muxreg),
+        },
+};
+
+struct spear_pingroup spear3xx_gpio0_pin3_pingroup = {
+        .name = "gpio0_pin3_grp",
+        .pins = gpio0_pin3_pins,
+        .npins = ARRAY_SIZE(gpio0_pin3_pins),
+        .modemuxs = gpio0_pin3_modemux,
+        .nmodemuxs = ARRAY_SIZE(gpio0_pin3_modemux),
+};
+
+/* gpio0_pin4_pins */
+static const unsigned gpio0_pin4_pins[] = { 32 };
+static struct spear_muxreg gpio0_pin4_muxreg[] = {
+        {
+                .reg = -1,
+                .mask = PMX_GPIO_PIN4_MASK,
+                .val = PMX_GPIO_PIN4_MASK,
+        },
+};
+
+static struct spear_modemux gpio0_pin4_modemux[] = {
+        {
+                .modes = ~0,
+                .muxregs = gpio0_pin4_muxreg,
+                .nmuxregs = ARRAY_SIZE(gpio0_pin4_muxreg),
+        },
+};
+
+struct spear_pingroup spear3xx_gpio0_pin4_pingroup = {
+        .name = "gpio0_pin4_grp",
+        .pins = gpio0_pin4_pins,
+        .npins = ARRAY_SIZE(gpio0_pin4_pins),
+        .modemuxs = gpio0_pin4_modemux,
+        .nmodemuxs = ARRAY_SIZE(gpio0_pin4_modemux),
+};
+
+/* gpio0_pin5_pins */
+static const unsigned gpio0_pin5_pins[] = { 33 };
+static struct spear_muxreg gpio0_pin5_muxreg[] = {
+        {
+                .reg = -1,
+                .mask = PMX_GPIO_PIN5_MASK,
+                .val = PMX_GPIO_PIN5_MASK,
+        },
+};
+
+static struct spear_modemux gpio0_pin5_modemux[] = {
+        {
+                .modes = ~0,
+                .muxregs = gpio0_pin5_muxreg,
+                .nmuxregs = ARRAY_SIZE(gpio0_pin5_muxreg),
+        },
+};
+
+struct spear_pingroup spear3xx_gpio0_pin5_pingroup = {
+        .name = "gpio0_pin5_grp",
+        .pins = gpio0_pin5_pins,
+        .npins = ARRAY_SIZE(gpio0_pin5_pins),
+        .modemuxs = gpio0_pin5_modemux,
+        .nmodemuxs = ARRAY_SIZE(gpio0_pin5_modemux),
+};
+
+static const char *const gpio0_grps[] = { "gpio0_pin0_grp", "gpio0_pin1_grp",
+        "gpio0_pin2_grp", "gpio0_pin3_grp", "gpio0_pin4_grp", "gpio0_pin5_grp",
+};
+struct spear_function spear3xx_gpio0_function = {
+        .name = "gpio0",
+        .groups = gpio0_grps,
+        .ngroups = ARRAY_SIZE(gpio0_grps),
+};
+
+/* uart0_ext_pins */
+static const unsigned uart0_ext_pins[] = { 37, 38, 39, 40, 41, 42 };
+static struct spear_muxreg uart0_ext_muxreg[] = {
+        {
+                .reg = -1,
+                .mask = PMX_UART0_MODEM_MASK,
+                .val = PMX_UART0_MODEM_MASK,
+        },
+};
+
+static struct spear_modemux uart0_ext_modemux[] = {
+        {
+                .modes = ~0,
+                .muxregs = uart0_ext_muxreg,
+                .nmuxregs = ARRAY_SIZE(uart0_ext_muxreg),
+        },
+};
+
+struct spear_pingroup spear3xx_uart0_ext_pingroup = {
+        .name = "uart0_ext_grp",
+        .pins = uart0_ext_pins,
+        .npins = ARRAY_SIZE(uart0_ext_pins),
+        .modemuxs = uart0_ext_modemux,
+        .nmodemuxs = ARRAY_SIZE(uart0_ext_modemux),
+};
+
+static const char *const uart0_ext_grps[] = { "uart0_ext_grp" };
+struct spear_function spear3xx_uart0_ext_function = {
+        .name = "uart0_ext",
+        .groups = uart0_ext_grps,
+        .ngroups = ARRAY_SIZE(uart0_ext_grps),
+};
+
+/* uart0_pins */
+static const unsigned uart0_pins[] = { 2, 3 };
+static struct spear_muxreg uart0_muxreg[] = {
+        {
+                .reg = -1,
+                .mask = PMX_UART0_MASK,
+                .val = PMX_UART0_MASK,
+        },
+};
+
+static struct spear_modemux uart0_modemux[] = {
+        {
+                .modes = ~0,
+                .muxregs = uart0_muxreg,
+                .nmuxregs = ARRAY_SIZE(uart0_muxreg),
+        },
+};
+
+struct spear_pingroup spear3xx_uart0_pingroup = {
+        .name = "uart0_grp",
+        .pins = uart0_pins,
+        .npins = ARRAY_SIZE(uart0_pins),
+        .modemuxs = uart0_modemux,
+        .nmodemuxs = ARRAY_SIZE(uart0_modemux),
+};
+
+static const char *const uart0_grps[] = { "uart0_grp" };
+struct spear_function spear3xx_uart0_function = {
+        .name = "uart0",
+        .groups = uart0_grps,
+        .ngroups = ARRAY_SIZE(uart0_grps),
+};
+
+/* timer_0_1_pins */
+static const unsigned timer_0_1_pins[] = { 43, 44, 47, 48 };
+static struct spear_muxreg timer_0_1_muxreg[] = {
+        {
+                .reg = -1,
+                .mask = PMX_TIMER_0_1_MASK,
+                .val = PMX_TIMER_0_1_MASK,
+        },
+};
+
+static struct spear_modemux timer_0_1_modemux[] = {
+        {
+                .modes = ~0,
+                .muxregs = timer_0_1_muxreg,
+                .nmuxregs = ARRAY_SIZE(timer_0_1_muxreg),
+        },
+};
+
+struct spear_pingroup spear3xx_timer_0_1_pingroup = {
+        .name = "timer_0_1_grp",
+        .pins = timer_0_1_pins,
+        .npins = ARRAY_SIZE(timer_0_1_pins),
+        .modemuxs = timer_0_1_modemux,
+        .nmodemuxs = ARRAY_SIZE(timer_0_1_modemux),
+};
+
+static const char *const timer_0_1_grps[] = { "timer_0_1_grp" };
+struct spear_function spear3xx_timer_0_1_function = {
+        .name = "timer_0_1",
+        .groups = timer_0_1_grps,
+        .ngroups = ARRAY_SIZE(timer_0_1_grps),
+};
+
+/* timer_2_3_pins */
+static const unsigned timer_2_3_pins[] = { 45, 46, 49, 50 };
+static struct spear_muxreg timer_2_3_muxreg[] = {
+        {
+                .reg = -1,
+                .mask = PMX_TIMER_2_3_MASK,
+                .val = PMX_TIMER_2_3_MASK,
+        },
+};
+
+static struct spear_modemux timer_2_3_modemux[] = {
+        {
+                .modes = ~0,
+                .muxregs = timer_2_3_muxreg,
+                .nmuxregs = ARRAY_SIZE(timer_2_3_muxreg),
+        },
+};
+
+struct spear_pingroup spear3xx_timer_2_3_pingroup = {
+        .name = "timer_2_3_grp",
+        .pins = timer_2_3_pins,
+        .npins = ARRAY_SIZE(timer_2_3_pins),
+        .modemuxs = timer_2_3_modemux,
+        .nmodemuxs = ARRAY_SIZE(timer_2_3_modemux),
+};
+
+static const char *const timer_2_3_grps[] = { "timer_2_3_grp" };
+struct spear_function spear3xx_timer_2_3_function = {
+        .name = "timer_2_3",
+        .groups = timer_2_3_grps,
+        .ngroups = ARRAY_SIZE(timer_2_3_grps),
+};
+
+struct spear_pinctrl_machdata spear3xx_machdata = {
+        .pins = spear3xx_pins,
+        .npins = ARRAY_SIZE(spear3xx_pins),
+};
diff --git a/drivers/pinctrl/spear/pinctrl-spear3xx.h b/drivers/pinctrl/spear/pinctrl-spear3xx.h
new file mode 100644
index 000000000000..5d5fdd8df7b8
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear3xx.h
@@ -0,0 +1,92 @@
+/*
+ * Header file for the ST Microelectronics SPEAr3xx pinmux
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PINMUX_SPEAR3XX_H__
+#define __PINMUX_SPEAR3XX_H__
+
+#include "pinctrl-spear.h"
+
+/* pad mux declarations */
+#define PMX_FIRDA_MASK          (1 << 14)
+#define PMX_I2C_MASK            (1 << 13)
+#define PMX_SSP_CS_MASK         (1 << 12)
+#define PMX_SSP_MASK            (1 << 11)
+#define PMX_MII_MASK            (1 << 10)
+#define PMX_GPIO_PIN0_MASK      (1 << 9)
+#define PMX_GPIO_PIN1_MASK      (1 << 8)
+#define PMX_GPIO_PIN2_MASK      (1 << 7)
+#define PMX_GPIO_PIN3_MASK      (1 << 6)
+#define PMX_GPIO_PIN4_MASK      (1 << 5)
+#define PMX_GPIO_PIN5_MASK      (1 << 4)
+#define PMX_UART0_MODEM_MASK    (1 << 3)
+#define PMX_UART0_MASK          (1 << 2)
+#define PMX_TIMER_2_3_MASK      (1 << 1)
+#define PMX_TIMER_0_1_MASK      (1 << 0)
+
+extern struct spear_pingroup spear3xx_firda_pingroup;
+extern struct spear_pingroup spear3xx_gpio0_pin0_pingroup;
+extern struct spear_pingroup spear3xx_gpio0_pin1_pingroup;
+extern struct spear_pingroup spear3xx_gpio0_pin2_pingroup;
+extern struct spear_pingroup spear3xx_gpio0_pin3_pingroup;
+extern struct spear_pingroup spear3xx_gpio0_pin4_pingroup;
+extern struct spear_pingroup spear3xx_gpio0_pin5_pingroup;
+extern struct spear_pingroup spear3xx_i2c_pingroup;
+extern struct spear_pingroup spear3xx_mii_pingroup;
+extern struct spear_pingroup spear3xx_ssp_cs_pingroup;
+extern struct spear_pingroup spear3xx_ssp_pingroup;
+extern struct spear_pingroup spear3xx_timer_0_1_pingroup;
+extern struct spear_pingroup spear3xx_timer_2_3_pingroup;
+extern struct spear_pingroup spear3xx_uart0_ext_pingroup;
+extern struct spear_pingroup spear3xx_uart0_pingroup;
+
+#define SPEAR3XX_COMMON_PINGROUPS               \
+        &spear3xx_firda_pingroup,               \
+        &spear3xx_gpio0_pin0_pingroup,          \
+        &spear3xx_gpio0_pin1_pingroup,          \
+        &spear3xx_gpio0_pin2_pingroup,          \
+        &spear3xx_gpio0_pin3_pingroup,          \
+        &spear3xx_gpio0_pin4_pingroup,          \
+        &spear3xx_gpio0_pin5_pingroup,          \
+        &spear3xx_i2c_pingroup,                 \
+        &spear3xx_mii_pingroup,                 \
+        &spear3xx_ssp_cs_pingroup,              \
+        &spear3xx_ssp_pingroup,                 \
+        &spear3xx_timer_0_1_pingroup,           \
+        &spear3xx_timer_2_3_pingroup,           \
+        &spear3xx_uart0_ext_pingroup,           \
+        &spear3xx_uart0_pingroup
+
+extern struct spear_function spear3xx_firda_function;
+extern struct spear_function spear3xx_gpio0_function;
+extern struct spear_function spear3xx_i2c_function;
+extern struct spear_function spear3xx_mii_function;
+extern struct spear_function spear3xx_ssp_cs_function;
+extern struct spear_function spear3xx_ssp_function;
+extern struct spear_function spear3xx_timer_0_1_function;
+extern struct spear_function spear3xx_timer_2_3_function;
+extern struct spear_function spear3xx_uart0_ext_function;
+extern struct spear_function spear3xx_uart0_function;
+
+#define SPEAR3XX_COMMON_FUNCTIONS               \
+        &spear3xx_firda_function,               \
+        &spear3xx_gpio0_function,               \
+        &spear3xx_i2c_function,                 \
+        &spear3xx_mii_function,                 \
+        &spear3xx_ssp_cs_function,              \
+        &spear3xx_ssp_function,                 \
+        &spear3xx_timer_0_1_function,           \
+        &spear3xx_timer_2_3_function,           \
+        &spear3xx_uart0_ext_function,           \
+        &spear3xx_uart0_function
+
+extern struct spear_pinctrl_machdata spear3xx_machdata;
+
+#endif /* __PINMUX_SPEAR3XX_H__ */
diff --git a/include/linux/clk-private.h b/include/linux/clk-private.h
index 5e4312b6f5cc..eb3f84bc5325 100644
--- a/include/linux/clk-private.h
+++ b/include/linux/clk-private.h
@@ -30,7 +30,7 @@ struct clk {
         const struct clk_ops    *ops;
         struct clk_hw           *hw;
         struct clk              *parent;
-        char                    **parent_names;
+        const char              **parent_names;
         struct clk              **parents;
         u8                      num_parents;
         unsigned long           rate;
@@ -55,12 +55,22 @@ struct clk {
  * alternative macro for static initialization
  */
 
-extern struct clk_ops clk_fixed_rate_ops;
+#define DEFINE_CLK(_name, _ops, _flags, _parent_names,          \
+                _parents)                                       \
+        static struct clk _name = {                             \
+                .name = #_name,                                 \
+                .ops = &_ops,                                   \
+                .hw = &_name##_hw.hw,                           \
+                .parent_names = _parent_names,                  \
+                .num_parents = ARRAY_SIZE(_parent_names),       \
+                .parents = _parents,                            \
+                .flags = _flags,                                \
+        }
 
 #define DEFINE_CLK_FIXED_RATE(_name, _flags, _rate,             \
                                 _fixed_rate_flags)              \
         static struct clk _name;                                \
-        static char *_name##_parent_names[] = {};               \
+        static const char *_name##_parent_names[] = {};         \
         static struct clk_fixed_rate _name##_hw = {             \
                 .hw = {                                         \
                         .clk = &_name,                          \
@@ -68,23 +78,14 @@ extern struct clk_ops clk_fixed_rate_ops;
                 .fixed_rate = _rate,                            \
                 .flags = _fixed_rate_flags,                     \
         };                                                      \
-        static struct clk _name = {                             \
-                .name = #_name,                                 \
-                .ops = &clk_fixed_rate_ops,                     \
-                .hw = &_name##_hw.hw,                           \
-                .parent_names = _name##_parent_names,           \
-                .num_parents =                                  \
-                        ARRAY_SIZE(_name##_parent_names),       \
-                .flags = _flags,                                \
-        };
-
-extern struct clk_ops clk_gate_ops;
+        DEFINE_CLK(_name, clk_fixed_rate_ops, _flags,           \
+                        _name##_parent_names, NULL);
 
 #define DEFINE_CLK_GATE(_name, _parent_name, _parent_ptr,       \
                                 _flags, _reg, _bit_idx,         \
                                 _gate_flags, _lock)             \
         static struct clk _name;                                \
-        static char *_name##_parent_names[] = {                 \
+        static const char *_name##_parent_names[] = {           \
                 _parent_name,                                   \
         };                                                      \
         static struct clk *_name##_parents[] = {                \
@@ -99,24 +100,14 @@ extern struct clk_ops clk_gate_ops;
                 .flags = _gate_flags,                           \
                 .lock = _lock,                                  \
         };                                                      \
-        static struct clk _name = {                             \
-                .name = #_name,                                 \
-                .ops = &clk_gate_ops,                           \
-                .hw = &_name##_hw.hw,                           \
-                .parent_names = _name##_parent_names,           \
-                .num_parents =                                  \
-                        ARRAY_SIZE(_name##_parent_names),       \
-                .parents = _name##_parents,                     \
-                .flags = _flags,                                \
-        };
-
-extern struct clk_ops clk_divider_ops;
+        DEFINE_CLK(_name, clk_gate_ops, _flags,                 \
+                        _name##_parent_names, _name##_parents);
 
 #define DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr,    \
                                 _flags, _reg, _shift, _width,   \
                                 _divider_flags, _lock)          \
         static struct clk _name;                                \
-        static char *_name##_parent_names[] = {                 \
+        static const char *_name##_parent_names[] = {           \
                 _parent_name,                                   \
         };                                                      \
         static struct clk *_name##_parents[] = {                \
@@ -132,18 +123,8 @@ extern struct clk_ops clk_divider_ops;
                 .flags = _divider_flags,                        \
                 .lock = _lock,                                  \
         };                                                      \
-        static struct clk _name = {                             \
-                .name = #_name,                                 \
-                .ops = &clk_divider_ops,                        \
-                .hw = &_name##_hw.hw,                           \
-                .parent_names = _name##_parent_names,           \
-                .num_parents =                                  \
-                        ARRAY_SIZE(_name##_parent_names),       \
-                .parents = _name##_parents,                     \
-                .flags = _flags,                                \
-        };
-
-extern struct clk_ops clk_mux_ops;
+        DEFINE_CLK(_name, clk_divider_ops, _flags,              \
+                        _name##_parent_names, _name##_parents);
 
 #define DEFINE_CLK_MUX(_name, _parent_names, _parents, _flags,  \
                                 _reg, _shift, _width,           \
@@ -159,16 +140,28 @@ extern struct clk_ops clk_mux_ops;
                 .flags = _mux_flags,                            \
                 .lock = _lock,                                  \
         };                                                      \
-        static struct clk _name = {                             \
-                .name = #_name,                                 \
-                .ops = &clk_mux_ops,                            \
-                .hw = &_name##_hw.hw,                           \
-                .parent_names = _parent_names,                  \
-                .num_parents =                                  \
-                        ARRAY_SIZE(_parent_names),              \
-                .parents = _parents,                            \
-                .flags = _flags,                                \
-        };
+        DEFINE_CLK(_name, clk_mux_ops, _flags, _parent_names,   \
+                        _parents);
+
+#define DEFINE_CLK_FIXED_FACTOR(_name, _parent_name,            \
+                                _parent_ptr, _flags,            \
+                                _mult, _div)                    \
+        static struct clk _name;                                \
+        static const char *_name##_parent_names[] = {           \
+                _parent_name,                                   \
+        };                                                      \
+        static struct clk *_name##_parents[] = {                \
+                _parent_ptr,                                    \
+        };                                                      \
+        static struct clk_fixed_factor _name##_hw = {           \
+                .hw = {                                         \
+                        .clk = &_name,                          \
+                },                                              \
+                .mult = _mult,                                  \
+                .div = _div,                                    \
+        };                                                      \
+        DEFINE_CLK(_name, clk_fixed_factor_ops, _flags,         \
+                        _name##_parent_names, _name##_parents);
 
 /**
  * __clk_init - initialize the data structures in a struct clk
@@ -189,8 +182,12 @@ extern struct clk_ops clk_mux_ops;
  *
  * It is not necessary to call clk_register if __clk_init is used directly with
  * statically initialized clock data.
+ *
+ * Returns 0 on success, otherwise an error code.
  */
-void __clk_init(struct device *dev, struct clk *clk);
+int __clk_init(struct device *dev, struct clk *clk);
+
+struct clk *__clk_register(struct device *dev, struct clk_hw *hw);
 
 #endif /* CONFIG_COMMON_CLK */
 #endif /* CLK_PRIVATE_H */
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 5508897ad376..c1c23b9ec368 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -15,19 +15,6 @@
 
 #ifdef CONFIG_COMMON_CLK
 
-/**
- * struct clk_hw - handle for traversing from a struct clk to its corresponding
- * hardware-specific structure.  struct clk_hw should be declared within struct
- * clk_foo and then referenced by the struct clk instance that uses struct
- * clk_foo's clk_ops
- *
- * clk: pointer to the struct clk instance that points back to this struct
- * clk_hw instance
- */
-struct clk_hw {
-        struct clk *clk;
-};
-
 /*
  * flags used across common struct clk.  these flags should only affect the
  * top-level framework.  custom flags for dealing with hardware specifics
@@ -39,6 +26,8 @@ struct clk_hw {
 #define CLK_IGNORE_UNUSED       BIT(3) /* do not gate even if unused */
 #define CLK_IS_ROOT             BIT(4) /* root clk, has no parent */
 
+struct clk_hw;
+
 /**
  * struct clk_ops -  Callback operations for hardware clocks; these are to
  * be provided by the clock implementation, and will be called by drivers
@@ -88,19 +77,11 @@ struct clk_hw {
  *              array index into the value programmed into the hardware.
  *              Returns 0 on success, -EERROR otherwise.
  *
- * @set_rate:   Change the rate of this clock. If this callback returns
- *              CLK_SET_RATE_PARENT, the rate change will be propagated to the
- *              parent clock (which may propagate again if the parent clock
- *              also sets this flag). The requested rate of the parent is
- *              passed back from the callback in the second 'unsigned long *'
- *              argument.  Note that it is up to the hardware clock's set_rate
- *              implementation to insure that clocks do not run out of spec
- *              when propgating the call to set_rate up to the parent.  One way
- *              to do this is to gate the clock (via clk_disable and/or
- *              clk_unprepare) before calling clk_set_rate, then ungating it
- *              afterward.  If your clock also has the CLK_GATE_SET_RATE flag
- *              set then this will insure safety.  Returns 0 on success,
- *              -EERROR otherwise.
+ * @set_rate:   Change the rate of this clock. The requested rate is specified
+ *              by the second argument, which should typically be the return
+ *              of .round_rate call.  The third argument gives the parent rate
+ *              which is likely helpful for most .set_rate implementation.
+ *              Returns 0 on success, -EERROR otherwise.
  *
  * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
  * implementations to split any work between atomic (enable) and sleepable
@@ -125,10 +106,46 @@ struct clk_ops {
                                         unsigned long *);
         int             (*set_parent)(struct clk_hw *hw, u8 index);
         u8              (*get_parent)(struct clk_hw *hw);
-        int             (*set_rate)(struct clk_hw *hw, unsigned long);
+        int             (*set_rate)(struct clk_hw *hw, unsigned long,
+                                    unsigned long);
         void            (*init)(struct clk_hw *hw);
 };
 
+/**
+ * struct clk_init_data - holds init data that's common to all clocks and is
+ * shared between the clock provider and the common clock framework.
+ *
+ * @name: clock name
+ * @ops: operations this clock supports
+ * @parent_names: array of string names for all possible parents
+ * @num_parents: number of possible parents
+ * @flags: framework-level hints and quirks
+ */
+struct clk_init_data {
+        const char              *name;
+        const struct clk_ops    *ops;
+        const char              **parent_names;
+        u8                      num_parents;
+        unsigned long           flags;
+};
+
+/**
+ * struct clk_hw - handle for traversing from a struct clk to its corresponding
+ * hardware-specific structure.  struct clk_hw should be declared within struct
+ * clk_foo and then referenced by the struct clk instance that uses struct
+ * clk_foo's clk_ops
+ *
+ * @clk: pointer to the struct clk instance that points back to this struct
+ * clk_hw instance
+ *
+ * @init: pointer to struct clk_init_data that contains the init data shared
+ * with the common clock framework.
+ */
+struct clk_hw {
+        struct clk *clk;
+        struct clk_init_data *init;
+};
+
 /*
  * DOC: Basic clock implementations common to many platforms
  *
@@ -149,6 +166,7 @@ struct clk_fixed_rate {
         u8              flags;
 };
 
+extern const struct clk_ops clk_fixed_rate_ops;
 struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
                 const char *parent_name, unsigned long flags,
                 unsigned long fixed_rate);
@@ -165,7 +183,7 @@ struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
  * Clock which can gate its output.  Implements .enable & .disable
  *
  * Flags:
- * CLK_GATE_SET_DISABLE - by default this clock sets the bit at bit_idx to
+ * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
  *      enable the clock.  Setting this flag does the opposite: setting the bit
  *      disable the clock and clearing it enables the clock
  */
@@ -175,11 +193,11 @@ struct clk_gate {
         u8              bit_idx;
         u8              flags;
         spinlock_t      *lock;
-        char            *parent[1];
 };
 
 #define CLK_GATE_SET_TO_DISABLE         BIT(0)
 
+extern const struct clk_ops clk_gate_ops;
 struct clk *clk_register_gate(struct device *dev, const char *name,
                 const char *parent_name, unsigned long flags,
                 void __iomem *reg, u8 bit_idx,
@@ -212,12 +230,12 @@ struct clk_divider {
         u8              width;
         u8              flags;
         spinlock_t      *lock;
-        char            *parent[1];
 };
 
 #define CLK_DIVIDER_ONE_BASED           BIT(0)
 #define CLK_DIVIDER_POWER_OF_TWO        BIT(1)
 
+extern const struct clk_ops clk_divider_ops;
 struct clk *clk_register_divider(struct device *dev, const char *name,
                 const char *parent_name, unsigned long flags,
                 void __iomem *reg, u8 shift, u8 width,
@@ -238,7 +256,7 @@ struct clk *clk_register_divider(struct device *dev, const char *name,
  *
  * Flags:
  * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
- * CLK_MUX_INDEX_BITWISE - register index is a single bit (power of two)
+ * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
  */
 struct clk_mux {
         struct clk_hw   hw;
@@ -252,29 +270,47 @@ struct clk_mux {
 #define CLK_MUX_INDEX_ONE               BIT(0)
 #define CLK_MUX_INDEX_BIT               BIT(1)
 
+extern const struct clk_ops clk_mux_ops;
 struct clk *clk_register_mux(struct device *dev, const char *name,
-                char **parent_names, u8 num_parents, unsigned long flags,
+                const char **parent_names, u8 num_parents, unsigned long flags,
                 void __iomem *reg, u8 shift, u8 width,
                 u8 clk_mux_flags, spinlock_t *lock);
 
 /**
+ * struct clk_fixed_factor - fixed multiplier and divider clock
+ *
+ * @hw:         handle between common and hardware-specific interfaces
+ * @mult:       multiplier
+ * @div:        divider
+ *
+ * Clock with a fixed multiplier and divider. The output frequency is the
+ * parent clock rate divided by div and multiplied by mult.
+ * Implements .recalc_rate, .set_rate and .round_rate
+ */
+
+struct clk_fixed_factor {
+        struct clk_hw   hw;
+        unsigned int    mult;
+        unsigned int    div;
+};
+
+extern struct clk_ops clk_fixed_factor_ops;
+struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
+                const char *parent_name, unsigned long flags,
+                unsigned int mult, unsigned int div);
+
+/**
  * clk_register - allocate a new clock, register it and return an opaque cookie
  * @dev: device that is registering this clock
- * @name: clock name
- * @ops: operations this clock supports
  * @hw: link to hardware-specific clock data
- * @parent_names: array of string names for all possible parents
- * @num_parents: number of possible parents
- * @flags: framework-level hints and quirks
  *
  * clk_register is the primary interface for populating the clock tree with new
  * clock nodes.  It returns a pointer to the newly allocated struct clk which
  * cannot be dereferenced by driver code but may be used in conjuction with the
- * rest of the clock API.
+ * rest of the clock API.  In the event of an error clk_register will return an
+ * error code; drivers must test for an error code after calling clk_register.
  */
-struct clk *clk_register(struct device *dev, const char *name,
-                const struct clk_ops *ops, struct clk_hw *hw,
-                char **parent_names, u8 num_parents, unsigned long flags);
+struct clk *clk_register(struct device *dev, struct clk_hw *hw);
 
 /* helper functions */
 const char *__clk_get_name(struct clk *clk);
diff --git a/include/linux/clk.h b/include/linux/clk.h
index b0252726df61..ad5c43e8ae8a 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -81,7 +81,7 @@ int clk_notifier_register(struct clk *clk, struct notifier_block *nb);
 
 int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb);
 
-#endif /* !CONFIG_COMMON_CLK */
+#endif
 
 /**
  * clk_get - lookup and obtain a reference to a clock producer.
@@ -101,6 +101,26 @@ int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb);
 struct clk *clk_get(struct device *dev, const char *id);
 
 /**
+ * devm_clk_get - lookup and obtain a managed reference to a clock producer.
+ * @dev: device for clock "consumer"
+ * @id: clock comsumer ID
+ *
+ * Returns a struct clk corresponding to the clock producer, or
+ * valid IS_ERR() condition containing errno.  The implementation
+ * uses @dev and @id to determine the clock consumer, and thereby
+ * the clock producer.  (IOW, @id may be identical strings, but
+ * clk_get may return different clock producers depending on @dev.)
+ *
+ * Drivers must assume that the clock source is not enabled.
+ *
+ * devm_clk_get should not be called from within interrupt context.
+ *
+ * The clock will automatically be freed when the device is unbound
+ * from the bus.
+ */
+struct clk *devm_clk_get(struct device *dev, const char *id);
+
+/**
  * clk_prepare - prepare a clock source
  * @clk: clock source
  *
@@ -206,6 +226,18 @@ unsigned long clk_get_rate(struct clk *clk);
  */
 void clk_put(struct clk *clk);
 
+/**
+ * devm_clk_put - "free" a managed clock source
+ * @dev: device used to acuqire the clock
+ * @clk: clock source acquired with devm_clk_get()
+ *
+ * Note: drivers must ensure that all clk_enable calls made on this
+ * clock source are balanced by clk_disable calls prior to calling
+ * this function.
+ *
+ * clk_put should not be called from within interrupt context.
+ */
+void devm_clk_put(struct device *dev, struct clk *clk);
 
 /*
  * The remaining APIs are optional for machine class support.
@@ -220,7 +252,7 @@ void clk_put(struct clk *clk);
  * Returns rounded clock rate in Hz, or negative errno.
  */
 long clk_round_rate(struct clk *clk, unsigned long rate);
- 
+
 /**
  * clk_set_rate - set the clock rate for a clock source
  * @clk: clock source
@@ -229,7 +261,7 @@ long clk_round_rate(struct clk *clk, unsigned long rate);
  * Returns success (0) or negative errno.
  */
 int clk_set_rate(struct clk *clk, unsigned long rate);
- 
+
 /**
  * clk_set_parent - set the parent clock source for this clock
  * @clk: clock source
diff --git a/include/linux/clkdev.h b/include/linux/clkdev.h
index d9a4fd028c9d..a6a6f603103b 100644
--- a/include/linux/clkdev.h
+++ b/include/linux/clkdev.h
@@ -40,4 +40,7 @@ void clkdev_drop(struct clk_lookup *cl);
 void clkdev_add_table(struct clk_lookup *, size_t);
 int clk_add_alias(const char *, const char *, char *, struct device *);
 
+int clk_register_clkdev(struct clk *, const char *, const char *, ...);
+int clk_register_clkdevs(struct clk *, struct clk_lookup *, size_t);
+
 #endif
diff --git a/include/linux/of.h b/include/linux/of.h
index fa7fb1d97458..2ec1083af7ff 100644
--- a/include/linux/of.h
+++ b/include/linux/of.h
@@ -193,6 +193,17 @@ extern struct device_node *of_get_next_child(const struct device_node *node,
         for (child = of_get_next_child(parent, NULL); child != NULL; \
              child = of_get_next_child(parent, child))
 
+static inline int of_get_child_count(const struct device_node *np)
+{
+        struct device_node *child;
+        int num = 0;
+
+        for_each_child_of_node(np, child)
+                num++;
+
+        return num;
+}
+
 extern struct device_node *of_find_node_with_property(
         struct device_node *from, const char *prop_name);
 #define for_each_node_with_property(dn, prop_name) \
@@ -259,6 +270,37 @@ extern void of_detach_node(struct device_node *);
 #endif
 
 #define of_match_ptr(_ptr)      (_ptr)
+
+/*
+ * struct property *prop;
+ * const __be32 *p;
+ * u32 u;
+ *
+ * of_property_for_each_u32(np, "propname", prop, p, u)
+ *         printk("U32 value: %x\n", u);
+ */
+const __be32 *of_prop_next_u32(struct property *prop, const __be32 *cur,
+                               u32 *pu);
+#define of_property_for_each_u32(np, propname, prop, p, u)      \
+        for (prop = of_find_property(np, propname, NULL),       \
+                p = of_prop_next_u32(prop, NULL, &u);           \
+                p;                                              \
+                p = of_prop_next_u32(prop, p, &u))
+
+/*
+ * struct property *prop;
+ * const char *s;
+ *
+ * of_property_for_each_string(np, "propname", prop, s)
+ *         printk("String value: %s\n", s);
+ */
+const char *of_prop_next_string(struct property *prop, const char *cur);
+#define of_property_for_each_string(np, propname, prop, s)      \
+        for (prop = of_find_property(np, propname, NULL),       \
+                s = of_prop_next_string(prop, NULL);            \
+                s;                                              \
+                s = of_prop_next_string(prop, s))
+
 #else /* CONFIG_OF */
 
 static inline bool of_have_populated_dt(void)
@@ -269,6 +311,11 @@ static inline bool of_have_populated_dt(void)
 #define for_each_child_of_node(parent, child) \
         while (0)
 
+static inline int of_get_child_count(const struct device_node *np)
+{
+        return 0;
+}
+
 static inline int of_device_is_compatible(const struct device_node *device,
                                           const char *name)
 {
@@ -349,6 +396,10 @@ static inline int of_machine_is_compatible(const char *compat)
 
 #define of_match_ptr(_ptr)      NULL
 #define of_match_node(_matches, _node)  NULL
+#define of_property_for_each_u32(np, propname, prop, p, u) \
+        while (0)
+#define of_property_for_each_string(np, propname, prop, s) \
+        while (0)
 #endif /* CONFIG_OF */
 
 /**
diff --git a/include/linux/pinctrl/consumer.h b/include/linux/pinctrl/consumer.h
index 191e72688481..6dd96fb45482 100644
--- a/include/linux/pinctrl/consumer.h
+++ b/include/linux/pinctrl/consumer.h
@@ -36,6 +36,9 @@ extern struct pinctrl_state * __must_check pinctrl_lookup_state(
                                                         const char *name);
 extern int pinctrl_select_state(struct pinctrl *p, struct pinctrl_state *s);
 
+extern struct pinctrl * __must_check devm_pinctrl_get(struct device *dev);
+extern void devm_pinctrl_put(struct pinctrl *p);
+
 #else /* !CONFIG_PINCTRL */
 
 static inline int pinctrl_request_gpio(unsigned gpio)
@@ -79,6 +82,15 @@ static inline int pinctrl_select_state(struct pinctrl *p,
         return 0;
 }
 
+static inline struct pinctrl * __must_check devm_pinctrl_get(struct device *dev)
+{
+        return NULL;
+}
+
+static inline void devm_pinctrl_put(struct pinctrl *p)
+{
+}
+
 #endif /* CONFIG_PINCTRL */
 
 static inline struct pinctrl * __must_check pinctrl_get_select(
@@ -113,6 +125,38 @@ static inline struct pinctrl * __must_check pinctrl_get_select_default(
         return pinctrl_get_select(dev, PINCTRL_STATE_DEFAULT);
 }
 
+static inline struct pinctrl * __must_check devm_pinctrl_get_select(
+                                        struct device *dev, const char *name)
+{
+        struct pinctrl *p;
+        struct pinctrl_state *s;
+        int ret;
+
+        p = devm_pinctrl_get(dev);
+        if (IS_ERR(p))
+                return p;
+
+        s = pinctrl_lookup_state(p, name);
+        if (IS_ERR(s)) {
+                devm_pinctrl_put(p);
+                return ERR_PTR(PTR_ERR(s));
+        }
+
+        ret = pinctrl_select_state(p, s);
+        if (ret < 0) {
+                devm_pinctrl_put(p);
+                return ERR_PTR(ret);
+        }
+
+        return p;
+}
+
+static inline struct pinctrl * __must_check devm_pinctrl_get_select_default(
+                                        struct device *dev)
+{
+        return devm_pinctrl_get_select(dev, PINCTRL_STATE_DEFAULT);
+}
+
 #ifdef CONFIG_PINCONF
 
 extern int pin_config_get(const char *dev_name, const char *name,
diff --git a/include/linux/pinctrl/machine.h b/include/linux/pinctrl/machine.h
index e4d1de742502..7d22ab00343f 100644
--- a/include/linux/pinctrl/machine.h
+++ b/include/linux/pinctrl/machine.h
@@ -154,7 +154,7 @@ struct pinctrl_map {
 
 extern int pinctrl_register_mappings(struct pinctrl_map const *map,
                                 unsigned num_maps);
-
+extern void pinctrl_provide_dummies(void);
 #else
 
 static inline int pinctrl_register_mappings(struct pinctrl_map const *map,
@@ -163,5 +163,8 @@ static inline int pinctrl_register_mappings(struct pinctrl_map const *map,
         return 0;
 }
 
-#endif /* !CONFIG_PINMUX */
+static inline void pinctrl_provide_dummies(void)
+{
+}
+#endif /* !CONFIG_PINCTRL */
 #endif
diff --git a/include/linux/pinctrl/pinconf.h b/include/linux/pinctrl/pinconf.h
index ec431f03362d..e7a720104a47 100644
--- a/include/linux/pinctrl/pinconf.h
+++ b/include/linux/pinctrl/pinconf.h
@@ -25,7 +25,6 @@ struct seq_file;
  * @pin_config_get: get the config of a certain pin, if the requested config
  *      is not available on this controller this should return -ENOTSUPP
  *      and if it is available but disabled it should return -EINVAL
- * @pin_config_get: get the config of a certain pin
  * @pin_config_set: configure an individual pin
  * @pin_config_group_get: get configurations for an entire pin group
  * @pin_config_group_set: configure all pins in a group
@@ -33,6 +32,8 @@ struct seq_file;
  *      per-device info for a certain pin in debugfs
  * @pin_config_group_dbg_show: optional debugfs display hook that will provide
  *      per-device info for a certain group in debugfs
+ * @pin_config_config_dbg_show: optional debugfs display hook that will decode
+ *      and display a driver's pin configuration parameter
  */
 struct pinconf_ops {
 #ifdef CONFIG_GENERIC_PINCONF
@@ -56,6 +57,9 @@ struct pinconf_ops {
         void (*pin_config_group_dbg_show) (struct pinctrl_dev *pctldev,
                                            struct seq_file *s,
                                            unsigned selector);
+        void (*pin_config_config_dbg_show) (struct pinctrl_dev *pctldev,
+                                            struct seq_file *s,
+                                            unsigned long config);
 };
 
 #endif
diff --git a/include/linux/pinctrl/pinctrl.h b/include/linux/pinctrl/pinctrl.h
index 4e9f0788c221..3b894a668d32 100644
--- a/include/linux/pinctrl/pinctrl.h
+++ b/include/linux/pinctrl/pinctrl.h
@@ -21,9 +21,11 @@
 
 struct device;
 struct pinctrl_dev;
+struct pinctrl_map;
 struct pinmux_ops;
 struct pinconf_ops;
 struct gpio_chip;
+struct device_node;
 
 /**
  * struct pinctrl_pin_desc - boards/machines provide information on their
@@ -64,17 +66,24 @@ struct pinctrl_gpio_range {
 /**
  * struct pinctrl_ops - global pin control operations, to be implemented by
  * pin controller drivers.
- * @list_groups: list the number of selectable named groups available
- *      in this pinmux driver, the core will begin on 0 and call this
- *      repeatedly as long as it returns >= 0 to enumerate the groups
+ * @get_groups_count: Returns the count of total number of groups registered.
  * @get_group_name: return the group name of the pin group
  * @get_group_pins: return an array of pins corresponding to a certain
  *      group selector @pins, and the size of the array in @num_pins
  * @pin_dbg_show: optional debugfs display hook that will provide per-device
  *      info for a certain pin in debugfs
+ * @dt_node_to_map: parse a device tree "pin configuration node", and create
+ *      mapping table entries for it. These are returned through the @map and
+ *      @num_maps output parameters. This function is optional, and may be
+ *      omitted for pinctrl drivers that do not support device tree.
+ * @dt_free_map: free mapping table entries created via @dt_node_to_map. The
+ *      top-level @map pointer must be freed, along with any dynamically
+ *      allocated members of the mapping table entries themselves. This
+ *      function is optional, and may be omitted for pinctrl drivers that do
+ *      not support device tree.
  */
 struct pinctrl_ops {
-        int (*list_groups) (struct pinctrl_dev *pctldev, unsigned selector);
+        int (*get_groups_count) (struct pinctrl_dev *pctldev);
         const char *(*get_group_name) (struct pinctrl_dev *pctldev,
                                        unsigned selector);
         int (*get_group_pins) (struct pinctrl_dev *pctldev,
@@ -83,6 +92,11 @@ struct pinctrl_ops {
                                unsigned *num_pins);
         void (*pin_dbg_show) (struct pinctrl_dev *pctldev, struct seq_file *s,
                           unsigned offset);
+        int (*dt_node_to_map) (struct pinctrl_dev *pctldev,
+                               struct device_node *np_config,
+                               struct pinctrl_map **map, unsigned *num_maps);
+        void (*dt_free_map) (struct pinctrl_dev *pctldev,
+                             struct pinctrl_map *map, unsigned num_maps);
 };
 
 /**
diff --git a/include/linux/pinctrl/pinmux.h b/include/linux/pinctrl/pinmux.h
index 47e9237edd47..1818dcbdd9ab 100644
--- a/include/linux/pinctrl/pinmux.h
+++ b/include/linux/pinctrl/pinmux.h
@@ -23,15 +23,14 @@ struct pinctrl_dev;
 /**
  * struct pinmux_ops - pinmux operations, to be implemented by pin controller
  * drivers that support pinmuxing
- * @request: called by the core to see if a certain pin can be made available
+ * @request: called by the core to see if a certain pin can be made
  *      available for muxing. This is called by the core to acquire the pins
  *      before selecting any actual mux setting across a function. The driver
  *      is allowed to answer "no" by returning a negative error code
  * @free: the reverse function of the request() callback, frees a pin after
  *      being requested
- * @list_functions: list the number of selectable named functions available
- *      in this pinmux driver, the core will begin on 0 and call this
- *      repeatedly as long as it returns >= 0 to enumerate mux settings
+ * @get_functions_count: returns number of selectable named functions available
+ *      in this pinmux driver
  * @get_function_name: return the function name of the muxing selector,
  *      called by the core to figure out which mux setting it shall map a
  *      certain device to
@@ -62,7 +61,7 @@ struct pinctrl_dev;
 struct pinmux_ops {
         int (*request) (struct pinctrl_dev *pctldev, unsigned offset);
         int (*free) (struct pinctrl_dev *pctldev, unsigned offset);
-        int (*list_functions) (struct pinctrl_dev *pctldev, unsigned selector);
+        int (*get_functions_count) (struct pinctrl_dev *pctldev);
         const char *(*get_function_name) (struct pinctrl_dev *pctldev,
                                           unsigned selector);
         int (*get_function_groups) (struct pinctrl_dev *pctldev,