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authorAlex Deucher <alexander.deucher@amd.com>2013-08-08 18:00:10 -0400
committerAlex Deucher <alexander.deucher@amd.com>2013-08-30 16:30:49 -0400
commit0116e1efafe09a2d99042943a850deaa1d9b069c (patch)
tree04054fb3c4bd40024997c20cacc4bdf78802dc47
parent64d8a728c7deb40e8db3c09b614ffe90415c7664 (diff)
drm/radeon: use new cg/pg flags for SI
Allows us finer grained control over clock and powergating on SI. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.c98
-rw-r--r--drivers/gpu/drm/radeon/si.c59
2 files changed, 128 insertions, 29 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index 69f3122779c3..dcdf5e07490d 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -2335,6 +2335,104 @@ int radeon_asic_init(struct radeon_device *rdev)
2335 rdev->has_uvd = false; 2335 rdev->has_uvd = false;
2336 else 2336 else
2337 rdev->has_uvd = true; 2337 rdev->has_uvd = true;
2338 switch (rdev->family) {
2339 case CHIP_TAHITI:
2340 rdev->cg_flags =
2341 RADEON_CG_SUPPORT_GFX_MGCG |
2342 RADEON_CG_SUPPORT_GFX_MGLS |
2343 RADEON_CG_SUPPORT_GFX_CGCG |
2344 RADEON_CG_SUPPORT_GFX_CGLS |
2345 RADEON_CG_SUPPORT_GFX_CGTS |
2346 RADEON_CG_SUPPORT_GFX_CP_LS |
2347 RADEON_CG_SUPPORT_MC_MGCG |
2348 RADEON_CG_SUPPORT_SDMA_MGCG |
2349 RADEON_CG_SUPPORT_BIF_LS |
2350 RADEON_CG_SUPPORT_VCE_MGCG |
2351 RADEON_CG_SUPPORT_UVD_MGCG |
2352 RADEON_CG_SUPPORT_HDP_LS |
2353 RADEON_CG_SUPPORT_HDP_MGCG;
2354 rdev->pg_flags = 0;
2355 break;
2356 case CHIP_PITCAIRN:
2357 rdev->cg_flags =
2358 RADEON_CG_SUPPORT_GFX_MGCG |
2359 RADEON_CG_SUPPORT_GFX_MGLS |
2360 RADEON_CG_SUPPORT_GFX_CGCG |
2361 RADEON_CG_SUPPORT_GFX_CGLS |
2362 RADEON_CG_SUPPORT_GFX_CGTS |
2363 RADEON_CG_SUPPORT_GFX_CP_LS |
2364 RADEON_CG_SUPPORT_GFX_RLC_LS |
2365 RADEON_CG_SUPPORT_MC_LS |
2366 RADEON_CG_SUPPORT_MC_MGCG |
2367 RADEON_CG_SUPPORT_SDMA_MGCG |
2368 RADEON_CG_SUPPORT_BIF_LS |
2369 RADEON_CG_SUPPORT_VCE_MGCG |
2370 RADEON_CG_SUPPORT_UVD_MGCG |
2371 RADEON_CG_SUPPORT_HDP_LS |
2372 RADEON_CG_SUPPORT_HDP_MGCG;
2373 rdev->pg_flags = 0;
2374 break;
2375 case CHIP_VERDE:
2376 rdev->cg_flags =
2377 RADEON_CG_SUPPORT_GFX_MGCG |
2378 RADEON_CG_SUPPORT_GFX_MGLS |
2379 RADEON_CG_SUPPORT_GFX_CGCG |
2380 RADEON_CG_SUPPORT_GFX_CGLS |
2381 RADEON_CG_SUPPORT_GFX_CGTS |
2382 RADEON_CG_SUPPORT_GFX_CP_LS |
2383 RADEON_CG_SUPPORT_GFX_RLC_LS |
2384 RADEON_CG_SUPPORT_MC_LS |
2385 RADEON_CG_SUPPORT_MC_MGCG |
2386 RADEON_CG_SUPPORT_SDMA_MGCG |
2387 RADEON_CG_SUPPORT_BIF_LS |
2388 RADEON_CG_SUPPORT_VCE_MGCG |
2389 RADEON_CG_SUPPORT_UVD_MGCG |
2390 RADEON_CG_SUPPORT_HDP_LS |
2391 RADEON_CG_SUPPORT_HDP_MGCG;
2392 rdev->pg_flags = 0;
2393 /*RADEON_PG_SUPPORT_GFX_CG |
2394 RADEON_PG_SUPPORT_SDMA;*/
2395 break;
2396 case CHIP_OLAND:
2397 rdev->cg_flags =
2398 RADEON_CG_SUPPORT_GFX_MGCG |
2399 RADEON_CG_SUPPORT_GFX_MGLS |
2400 RADEON_CG_SUPPORT_GFX_CGCG |
2401 RADEON_CG_SUPPORT_GFX_CGLS |
2402 RADEON_CG_SUPPORT_GFX_CGTS |
2403 RADEON_CG_SUPPORT_GFX_CP_LS |
2404 RADEON_CG_SUPPORT_GFX_RLC_LS |
2405 RADEON_CG_SUPPORT_MC_LS |
2406 RADEON_CG_SUPPORT_MC_MGCG |
2407 RADEON_CG_SUPPORT_SDMA_MGCG |
2408 RADEON_CG_SUPPORT_BIF_LS |
2409 RADEON_CG_SUPPORT_UVD_MGCG |
2410 RADEON_CG_SUPPORT_HDP_LS |
2411 RADEON_CG_SUPPORT_HDP_MGCG;
2412 rdev->pg_flags = 0;
2413 break;
2414 case CHIP_HAINAN:
2415 rdev->cg_flags =
2416 RADEON_CG_SUPPORT_GFX_MGCG |
2417 RADEON_CG_SUPPORT_GFX_MGLS |
2418 RADEON_CG_SUPPORT_GFX_CGCG |
2419 RADEON_CG_SUPPORT_GFX_CGLS |
2420 RADEON_CG_SUPPORT_GFX_CGTS |
2421 RADEON_CG_SUPPORT_GFX_CP_LS |
2422 RADEON_CG_SUPPORT_GFX_RLC_LS |
2423 RADEON_CG_SUPPORT_MC_LS |
2424 RADEON_CG_SUPPORT_MC_MGCG |
2425 RADEON_CG_SUPPORT_SDMA_MGCG |
2426 RADEON_CG_SUPPORT_BIF_LS |
2427 RADEON_CG_SUPPORT_HDP_LS |
2428 RADEON_CG_SUPPORT_HDP_MGCG;
2429 rdev->pg_flags = 0;
2430 break;
2431 default:
2432 rdev->cg_flags = 0;
2433 rdev->pg_flags = 0;
2434 break;
2435 }
2338 break; 2436 break;
2339 case CHIP_BONAIRE: 2437 case CHIP_BONAIRE:
2340 rdev->asic = &ci_asic; 2438 rdev->asic = &ci_asic;
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index fb2058c9670d..e116128f3d8f 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -5121,39 +5121,44 @@ static void si_enable_mc_ls(struct radeon_device *rdev,
5121 5121
5122static void si_init_cg(struct radeon_device *rdev) 5122static void si_init_cg(struct radeon_device *rdev)
5123{ 5123{
5124 si_enable_mgcg(rdev, true); 5124 if (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_MGCG)
5125 si_enable_cgcg(rdev, false); 5125 si_enable_mgcg(rdev, true);
5126 /* disable MC LS on Tahiti */ 5126 if (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CGCG)
5127 if (rdev->family == CHIP_TAHITI) 5127 si_enable_cgcg(rdev, false/*true*/);
5128 /* Disable MC LS on tahiti */
5129 if (!(rdev->cg_flags & RADEON_CG_SUPPORT_MC_LS))
5128 si_enable_mc_ls(rdev, false); 5130 si_enable_mc_ls(rdev, false);
5129 if (rdev->has_uvd) { 5131 if (rdev->has_uvd) {
5130 si_enable_uvd_mgcg(rdev, true); 5132 if (rdev->cg_flags & RADEON_CG_SUPPORT_UVD_MGCG)
5133 si_enable_uvd_mgcg(rdev, true);
5131 si_init_uvd_internal_cg(rdev); 5134 si_init_uvd_internal_cg(rdev);
5132 } 5135 }
5133} 5136}
5134 5137
5135static void si_fini_cg(struct radeon_device *rdev) 5138static void si_fini_cg(struct radeon_device *rdev)
5136{ 5139{
5137 if (rdev->has_uvd) 5140 if (rdev->has_uvd) {
5138 si_enable_uvd_mgcg(rdev, false); 5141 if (rdev->cg_flags & RADEON_CG_SUPPORT_UVD_MGCG)
5139 si_enable_cgcg(rdev, false); 5142 si_enable_uvd_mgcg(rdev, false);
5140 si_enable_mgcg(rdev, false); 5143 }
5144 if (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CGCG)
5145 si_enable_cgcg(rdev, false);
5146 if (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_MGCG)
5147 si_enable_mgcg(rdev, false);
5141} 5148}
5142 5149
5143static void si_init_pg(struct radeon_device *rdev) 5150static void si_init_pg(struct radeon_device *rdev)
5144{ 5151{
5145 bool has_pg = false; 5152 if (rdev->pg_flags) {
5146#if 0 5153 if (rdev->pg_flags & RADEON_PG_SUPPORT_SDMA) {
5147 /* only cape verde supports PG */ 5154 si_init_dma_pg(rdev);
5148 if (rdev->family == CHIP_VERDE) 5155 si_enable_dma_pg(rdev, true);
5149 has_pg = true; 5156 }
5150#endif
5151 if (has_pg) {
5152 si_init_ao_cu_mask(rdev); 5157 si_init_ao_cu_mask(rdev);
5153 si_init_dma_pg(rdev); 5158 if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_CG) {
5154 si_enable_dma_pg(rdev, true); 5159 si_init_gfx_cgpg(rdev);
5155 si_init_gfx_cgpg(rdev); 5160 si_enable_gfx_cgpg(rdev, true);
5156 si_enable_gfx_cgpg(rdev, true); 5161 }
5157 } else { 5162 } else {
5158 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); 5163 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
5159 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); 5164 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
@@ -5162,15 +5167,11 @@ static void si_init_pg(struct radeon_device *rdev)
5162 5167
5163static void si_fini_pg(struct radeon_device *rdev) 5168static void si_fini_pg(struct radeon_device *rdev)
5164{ 5169{
5165 bool has_pg = false; 5170 if (rdev->pg_flags) {
5166 5171 if (rdev->pg_flags & RADEON_PG_SUPPORT_SDMA)
5167 /* only cape verde supports PG */ 5172 si_enable_dma_pg(rdev, false);
5168 if (rdev->family == CHIP_VERDE) 5173 if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_CG)
5169 has_pg = true; 5174 si_enable_gfx_cgpg(rdev, false);
5170
5171 if (has_pg) {
5172 si_enable_dma_pg(rdev, false);
5173 si_enable_gfx_cgpg(rdev, false);
5174 } 5175 }
5175} 5176}
5176 5177
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-22 17:35:09 -0500