diff options
author | Grant Likely <grant.likely@secretlab.ca> | 2009-06-17 09:16:04 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2009-06-17 21:46:43 -0400 |
commit | f3a32500ba8f3ec9ee0c12836fcfd315f1256db4 (patch) | |
tree | fecc1148c135213d6f82130de46e6196e57a59a8 | |
parent | 603a8bbe62e54108055fca46ecdd611c10c6cd0a (diff) |
Revert "net/ucc_geth: Add SGMII support for UEC GETH driver"
This reverts commit 047584ce94108012288554a5f84585d792cc7f8f.
This patch meshes badly with "net: Rework ucc_geth driver to use
of_mdio infrastructure" (0b9da337dca972e7a4144e298ec3adb8f244d4a4).
Since most of the patch needs to be reworked, it is clearer to revert
the patch and then apply the corrected version
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r-- | arch/powerpc/include/asm/qe.h | 2 | ||||
-rw-r--r-- | drivers/net/ucc_geth.c | 79 | ||||
-rw-r--r-- | drivers/net/ucc_geth.h | 28 |
3 files changed, 2 insertions, 107 deletions
diff --git a/arch/powerpc/include/asm/qe.h b/arch/powerpc/include/asm/qe.h index 4459d20dc76a..2701753d9937 100644 --- a/arch/powerpc/include/asm/qe.h +++ b/arch/powerpc/include/asm/qe.h | |||
@@ -668,8 +668,6 @@ struct ucc_slow_pram { | |||
668 | #define UCC_GETH_UPSMR_RMM 0x00001000 | 668 | #define UCC_GETH_UPSMR_RMM 0x00001000 |
669 | #define UCC_GETH_UPSMR_CAM 0x00000400 | 669 | #define UCC_GETH_UPSMR_CAM 0x00000400 |
670 | #define UCC_GETH_UPSMR_BRO 0x00000200 | 670 | #define UCC_GETH_UPSMR_BRO 0x00000200 |
671 | #define UCC_GETH_UPSMR_SMM 0x00000080 | ||
672 | #define UCC_GETH_UPSMR_SGMM 0x00000020 | ||
673 | 671 | ||
674 | /* UCC Transmit On Demand Register (UTODR) */ | 672 | /* UCC Transmit On Demand Register (UTODR) */ |
675 | #define UCC_SLOW_TOD 0x8000 | 673 | #define UCC_SLOW_TOD 0x8000 |
diff --git a/drivers/net/ucc_geth.c b/drivers/net/ucc_geth.c index fd6140bd9aae..0cf22c4f123b 100644 --- a/drivers/net/ucc_geth.c +++ b/drivers/net/ucc_geth.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (C) 2006-2009 Freescale Semicondutor, Inc. All rights reserved. | 2 | * Copyright (C) 2006-2007 Freescale Semicondutor, Inc. All rights reserved. |
3 | * | 3 | * |
4 | * Author: Shlomi Gridish <gridish@freescale.com> | 4 | * Author: Shlomi Gridish <gridish@freescale.com> |
5 | * Li Yang <leoli@freescale.com> | 5 | * Li Yang <leoli@freescale.com> |
@@ -65,8 +65,6 @@ | |||
65 | 65 | ||
66 | static DEFINE_SPINLOCK(ugeth_lock); | 66 | static DEFINE_SPINLOCK(ugeth_lock); |
67 | 67 | ||
68 | static void uec_configure_serdes(struct net_device *dev); | ||
69 | |||
70 | static struct { | 68 | static struct { |
71 | u32 msg_enable; | 69 | u32 msg_enable; |
72 | } debug = { -1 }; | 70 | } debug = { -1 }; |
@@ -1412,9 +1410,6 @@ static int adjust_enet_interface(struct ucc_geth_private *ugeth) | |||
1412 | (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) { | 1410 | (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) { |
1413 | upsmr |= UCC_GETH_UPSMR_TBIM; | 1411 | upsmr |= UCC_GETH_UPSMR_TBIM; |
1414 | } | 1412 | } |
1415 | if ((ugeth->phy_interface == PHY_INTERFACE_MODE_SGMII)) | ||
1416 | upsmr |= UCC_GETH_UPSMR_SGMM; | ||
1417 | |||
1418 | out_be32(&uf_regs->upsmr, upsmr); | 1413 | out_be32(&uf_regs->upsmr, upsmr); |
1419 | 1414 | ||
1420 | /* Disable autonegotiation in tbi mode, because by default it | 1415 | /* Disable autonegotiation in tbi mode, because by default it |
@@ -1559,9 +1554,6 @@ static int init_phy(struct net_device *dev) | |||
1559 | return -ENODEV; | 1554 | return -ENODEV; |
1560 | } | 1555 | } |
1561 | 1556 | ||
1562 | if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII) | ||
1563 | uec_configure_serdes(dev); | ||
1564 | |||
1565 | phydev->supported &= (ADVERTISED_10baseT_Half | | 1557 | phydev->supported &= (ADVERTISED_10baseT_Half | |
1566 | ADVERTISED_10baseT_Full | | 1558 | ADVERTISED_10baseT_Full | |
1567 | ADVERTISED_100baseT_Half | | 1559 | ADVERTISED_100baseT_Half | |
@@ -1577,41 +1569,7 @@ static int init_phy(struct net_device *dev) | |||
1577 | return 0; | 1569 | return 0; |
1578 | } | 1570 | } |
1579 | 1571 | ||
1580 | /* Initialize TBI PHY interface for communicating with the | ||
1581 | * SERDES lynx PHY on the chip. We communicate with this PHY | ||
1582 | * through the MDIO bus on each controller, treating it as a | ||
1583 | * "normal" PHY at the address found in the UTBIPA register. We assume | ||
1584 | * that the UTBIPA register is valid. Either the MDIO bus code will set | ||
1585 | * it to a value that doesn't conflict with other PHYs on the bus, or the | ||
1586 | * value doesn't matter, as there are no other PHYs on the bus. | ||
1587 | */ | ||
1588 | static void uec_configure_serdes(struct net_device *dev) | ||
1589 | { | ||
1590 | struct ucc_geth_private *ugeth = netdev_priv(dev); | ||
1591 | |||
1592 | if (!ugeth->tbiphy) { | ||
1593 | printk(KERN_WARNING "SGMII mode requires that the device " | ||
1594 | "tree specify a tbi-handle\n"); | ||
1595 | return; | ||
1596 | } | ||
1597 | |||
1598 | /* | ||
1599 | * If the link is already up, we must already be ok, and don't need to | ||
1600 | * configure and reset the TBI<->SerDes link. Maybe U-Boot configured | ||
1601 | * everything for us? Resetting it takes the link down and requires | ||
1602 | * several seconds for it to come back. | ||
1603 | */ | ||
1604 | if (phy_read(ugeth->tbiphy, ENET_TBI_MII_SR) & TBISR_LSTATUS) | ||
1605 | return; | ||
1606 | |||
1607 | /* Single clk mode, mii mode off(for serdes communication) */ | ||
1608 | phy_write(ugeth->tbiphy, ENET_TBI_MII_ANA, TBIANA_SETTINGS); | ||
1609 | 1572 | ||
1610 | phy_write(ugeth->tbiphy, ENET_TBI_MII_TBICON, TBICON_CLK_SELECT); | ||
1611 | |||
1612 | phy_write(ugeth->tbiphy, ENET_TBI_MII_CR, TBICR_SETTINGS); | ||
1613 | |||
1614 | } | ||
1615 | 1573 | ||
1616 | static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth) | 1574 | static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth) |
1617 | { | 1575 | { |
@@ -3565,8 +3523,6 @@ static phy_interface_t to_phy_interface(const char *phy_connection_type) | |||
3565 | return PHY_INTERFACE_MODE_RGMII_RXID; | 3523 | return PHY_INTERFACE_MODE_RGMII_RXID; |
3566 | if (strcasecmp(phy_connection_type, "rtbi") == 0) | 3524 | if (strcasecmp(phy_connection_type, "rtbi") == 0) |
3567 | return PHY_INTERFACE_MODE_RTBI; | 3525 | return PHY_INTERFACE_MODE_RTBI; |
3568 | if (strcasecmp(phy_connection_type, "sgmii") == 0) | ||
3569 | return PHY_INTERFACE_MODE_SGMII; | ||
3570 | 3526 | ||
3571 | return PHY_INTERFACE_MODE_MII; | 3527 | return PHY_INTERFACE_MODE_MII; |
3572 | } | 3528 | } |
@@ -3611,7 +3567,6 @@ static int ucc_geth_probe(struct of_device* ofdev, const struct of_device_id *ma | |||
3611 | PHY_INTERFACE_MODE_RMII, PHY_INTERFACE_MODE_RGMII, | 3567 | PHY_INTERFACE_MODE_RMII, PHY_INTERFACE_MODE_RGMII, |
3612 | PHY_INTERFACE_MODE_GMII, PHY_INTERFACE_MODE_RGMII, | 3568 | PHY_INTERFACE_MODE_GMII, PHY_INTERFACE_MODE_RGMII, |
3613 | PHY_INTERFACE_MODE_TBI, PHY_INTERFACE_MODE_RTBI, | 3569 | PHY_INTERFACE_MODE_TBI, PHY_INTERFACE_MODE_RTBI, |
3614 | PHY_INTERFACE_MODE_SGMII, | ||
3615 | }; | 3570 | }; |
3616 | 3571 | ||
3617 | ugeth_vdbg("%s: IN", __func__); | 3572 | ugeth_vdbg("%s: IN", __func__); |
@@ -3727,7 +3682,6 @@ static int ucc_geth_probe(struct of_device* ofdev, const struct of_device_id *ma | |||
3727 | case PHY_INTERFACE_MODE_RGMII_TXID: | 3682 | case PHY_INTERFACE_MODE_RGMII_TXID: |
3728 | case PHY_INTERFACE_MODE_TBI: | 3683 | case PHY_INTERFACE_MODE_TBI: |
3729 | case PHY_INTERFACE_MODE_RTBI: | 3684 | case PHY_INTERFACE_MODE_RTBI: |
3730 | case PHY_INTERFACE_MODE_SGMII: | ||
3731 | max_speed = SPEED_1000; | 3685 | max_speed = SPEED_1000; |
3732 | break; | 3686 | break; |
3733 | default: | 3687 | default: |
@@ -3802,37 +3756,6 @@ static int ucc_geth_probe(struct of_device* ofdev, const struct of_device_id *ma | |||
3802 | ugeth->ndev = dev; | 3756 | ugeth->ndev = dev; |
3803 | ugeth->node = np; | 3757 | ugeth->node = np; |
3804 | 3758 | ||
3805 | /* Find the TBI PHY. If it's not there, we don't support SGMII */ | ||
3806 | ph = of_get_property(np, "tbi-handle", NULL); | ||
3807 | if (ph) { | ||
3808 | struct device_node *tbi = of_find_node_by_phandle(*ph); | ||
3809 | struct of_device *ofdev; | ||
3810 | struct mii_bus *bus; | ||
3811 | const unsigned int *id; | ||
3812 | |||
3813 | if (!tbi) | ||
3814 | return 0; | ||
3815 | |||
3816 | mdio = of_get_parent(tbi); | ||
3817 | if (!mdio) | ||
3818 | return 0; | ||
3819 | |||
3820 | ofdev = of_find_device_by_node(mdio); | ||
3821 | |||
3822 | of_node_put(mdio); | ||
3823 | |||
3824 | id = of_get_property(tbi, "reg", NULL); | ||
3825 | if (!id) | ||
3826 | return 0; | ||
3827 | of_node_put(tbi); | ||
3828 | |||
3829 | bus = dev_get_drvdata(&ofdev->dev); | ||
3830 | if (!bus) | ||
3831 | return 0; | ||
3832 | |||
3833 | ugeth->tbiphy = bus->phy_map[*id]; | ||
3834 | } | ||
3835 | |||
3836 | return 0; | 3759 | return 0; |
3837 | } | 3760 | } |
3838 | 3761 | ||
diff --git a/drivers/net/ucc_geth.h b/drivers/net/ucc_geth.h index deb962bb68ef..dca628a922ba 100644 --- a/drivers/net/ucc_geth.h +++ b/drivers/net/ucc_geth.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (C) Freescale Semicondutor, Inc. 2006-2009. All rights reserved. | 2 | * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved. |
3 | * | 3 | * |
4 | * Author: Shlomi Gridish <gridish@freescale.com> | 4 | * Author: Shlomi Gridish <gridish@freescale.com> |
5 | * | 5 | * |
@@ -193,31 +193,6 @@ struct ucc_geth { | |||
193 | #define ENET_TBI_MII_JD 0x10 /* Jitter diagnostics */ | 193 | #define ENET_TBI_MII_JD 0x10 /* Jitter diagnostics */ |
194 | #define ENET_TBI_MII_TBICON 0x11 /* TBI control */ | 194 | #define ENET_TBI_MII_TBICON 0x11 /* TBI control */ |
195 | 195 | ||
196 | /* TBI MDIO register bit fields*/ | ||
197 | #define TBISR_LSTATUS 0x0004 | ||
198 | #define TBICON_CLK_SELECT 0x0020 | ||
199 | #define TBIANA_ASYMMETRIC_PAUSE 0x0100 | ||
200 | #define TBIANA_SYMMETRIC_PAUSE 0x0080 | ||
201 | #define TBIANA_HALF_DUPLEX 0x0040 | ||
202 | #define TBIANA_FULL_DUPLEX 0x0020 | ||
203 | #define TBICR_PHY_RESET 0x8000 | ||
204 | #define TBICR_ANEG_ENABLE 0x1000 | ||
205 | #define TBICR_RESTART_ANEG 0x0200 | ||
206 | #define TBICR_FULL_DUPLEX 0x0100 | ||
207 | #define TBICR_SPEED1_SET 0x0040 | ||
208 | |||
209 | #define TBIANA_SETTINGS ( \ | ||
210 | TBIANA_ASYMMETRIC_PAUSE \ | ||
211 | | TBIANA_SYMMETRIC_PAUSE \ | ||
212 | | TBIANA_FULL_DUPLEX \ | ||
213 | ) | ||
214 | #define TBICR_SETTINGS ( \ | ||
215 | TBICR_PHY_RESET \ | ||
216 | | TBICR_ANEG_ENABLE \ | ||
217 | | TBICR_FULL_DUPLEX \ | ||
218 | | TBICR_SPEED1_SET \ | ||
219 | ) | ||
220 | |||
221 | /* UCC GETH MACCFG1 (MAC Configuration 1 Register) */ | 196 | /* UCC GETH MACCFG1 (MAC Configuration 1 Register) */ |
222 | #define MACCFG1_FLOW_RX 0x00000020 /* Flow Control | 197 | #define MACCFG1_FLOW_RX 0x00000020 /* Flow Control |
223 | Rx */ | 198 | Rx */ |
@@ -1213,7 +1188,6 @@ struct ucc_geth_private { | |||
1213 | 1188 | ||
1214 | struct ugeth_mii_info *mii_info; | 1189 | struct ugeth_mii_info *mii_info; |
1215 | struct phy_device *phydev; | 1190 | struct phy_device *phydev; |
1216 | struct phy_device *tbiphy; | ||
1217 | phy_interface_t phy_interface; | 1191 | phy_interface_t phy_interface; |
1218 | int max_speed; | 1192 | int max_speed; |
1219 | uint32_t msg_enable; | 1193 | uint32_t msg_enable; |