diff options
author | Andrew Victor <andrew@sanpeople.com> | 2006-03-24 04:50:17 -0500 |
---|---|---|
committer | Jeff Garzik <jeff@garzik.org> | 2006-03-24 12:10:55 -0500 |
commit | d4b7780ea1d2e08410fcc9963a57254147ae577a (patch) | |
tree | 3625bc3f6f0220b348793e9dc1e1a131899b49c9 | |
parent | e93252faca2eb1a14b44369705be7c79eba2f037 (diff) |
[PATCH] AT91RM9200 Ethernet driver
This patch adds support for the Ethernet controller integrated in the
Atmel AT91RM9200 SoC processor.
Changes since the previous submission (01/02/2006) are:
- Make use of the clk.h clock infrastructure.
- The multicast hash function is not crc32. [Patch by Pedro Perez]
Signed-off-by: Andrew Victor <andrew@sanpeople.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
-rw-r--r-- | drivers/net/arm/Kconfig | 8 | ||||
-rw-r--r-- | drivers/net/arm/Makefile | 1 | ||||
-rw-r--r-- | drivers/net/arm/at91_ether.c | 1110 | ||||
-rw-r--r-- | drivers/net/arm/at91_ether.h | 101 | ||||
-rw-r--r-- | include/asm-arm/arch-at91rm9200/at91rm9200_emac.h | 138 |
5 files changed, 1358 insertions, 0 deletions
diff --git a/drivers/net/arm/Kconfig b/drivers/net/arm/Kconfig index 625184b65e38..77fe20dbea35 100644 --- a/drivers/net/arm/Kconfig +++ b/drivers/net/arm/Kconfig | |||
@@ -31,3 +31,11 @@ config ARM_ETHERH | |||
31 | help | 31 | help |
32 | If you have an Acorn system with one of these network cards, you | 32 | If you have an Acorn system with one of these network cards, you |
33 | should say Y to this option if you wish to use it with Linux. | 33 | should say Y to this option if you wish to use it with Linux. |
34 | |||
35 | config ARM_AT91_ETHER | ||
36 | tristate "AT91RM9200 Ethernet support" | ||
37 | depends on NET_ETHERNET && ARM && ARCH_AT91RM9200 | ||
38 | select MII | ||
39 | help | ||
40 | If you wish to compile a kernel for the AT91RM9200 and enable | ||
41 | ethernet support, then you should always answer Y to this. | ||
diff --git a/drivers/net/arm/Makefile b/drivers/net/arm/Makefile index bc263edf06a7..42c95b79c261 100644 --- a/drivers/net/arm/Makefile +++ b/drivers/net/arm/Makefile | |||
@@ -7,3 +7,4 @@ obj-$(CONFIG_ARM_AM79C961A) += am79c961a.o | |||
7 | obj-$(CONFIG_ARM_ETHERH) += etherh.o | 7 | obj-$(CONFIG_ARM_ETHERH) += etherh.o |
8 | obj-$(CONFIG_ARM_ETHER3) += ether3.o | 8 | obj-$(CONFIG_ARM_ETHER3) += ether3.o |
9 | obj-$(CONFIG_ARM_ETHER1) += ether1.o | 9 | obj-$(CONFIG_ARM_ETHER1) += ether1.o |
10 | obj-$(CONFIG_ARM_AT91_ETHER) += at91_ether.o | ||
diff --git a/drivers/net/arm/at91_ether.c b/drivers/net/arm/at91_ether.c new file mode 100644 index 000000000000..5503dc8a66e4 --- /dev/null +++ b/drivers/net/arm/at91_ether.c | |||
@@ -0,0 +1,1110 @@ | |||
1 | /* | ||
2 | * Ethernet driver for the Atmel AT91RM9200 (Thunder) | ||
3 | * | ||
4 | * Copyright (C) 2003 SAN People (Pty) Ltd | ||
5 | * | ||
6 | * Based on an earlier Atmel EMAC macrocell driver by Atmel and Lineo Inc. | ||
7 | * Initial version by Rick Bronson 01/11/2003 | ||
8 | * | ||
9 | * Intel LXT971A PHY support by Christopher Bahns & David Knickerbocker | ||
10 | * (Polaroid Corporation) | ||
11 | * | ||
12 | * Realtek RTL8201(B)L PHY support by Roman Avramenko <roman@imsystems.ru> | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version | ||
17 | * 2 of the License, or (at your option) any later version. | ||
18 | */ | ||
19 | |||
20 | #include <linux/module.h> | ||
21 | #include <linux/init.h> | ||
22 | #include <linux/config.h> | ||
23 | #include <linux/mii.h> | ||
24 | #include <linux/netdevice.h> | ||
25 | #include <linux/etherdevice.h> | ||
26 | #include <linux/skbuff.h> | ||
27 | #include <linux/dma-mapping.h> | ||
28 | #include <linux/ethtool.h> | ||
29 | #include <linux/platform_device.h> | ||
30 | #include <linux/clk.h> | ||
31 | |||
32 | #include <asm/io.h> | ||
33 | #include <asm/uaccess.h> | ||
34 | #include <asm/mach-types.h> | ||
35 | |||
36 | #include <asm/arch/at91rm9200_emac.h> | ||
37 | #include <asm/arch/gpio.h> | ||
38 | #include <asm/arch/board.h> | ||
39 | |||
40 | #include "at91_ether.h" | ||
41 | |||
42 | #define DRV_NAME "at91_ether" | ||
43 | #define DRV_VERSION "1.0" | ||
44 | |||
45 | static struct net_device *at91_dev; | ||
46 | static struct clk *ether_clk; | ||
47 | |||
48 | /* ..................................................................... */ | ||
49 | |||
50 | /* | ||
51 | * Read from a EMAC register. | ||
52 | */ | ||
53 | static inline unsigned long at91_emac_read(unsigned int reg) | ||
54 | { | ||
55 | void __iomem *emac_base = (void __iomem *)AT91_VA_BASE_EMAC; | ||
56 | |||
57 | return __raw_readl(emac_base + reg); | ||
58 | } | ||
59 | |||
60 | /* | ||
61 | * Write to a EMAC register. | ||
62 | */ | ||
63 | static inline void at91_emac_write(unsigned int reg, unsigned long value) | ||
64 | { | ||
65 | void __iomem *emac_base = (void __iomem *)AT91_VA_BASE_EMAC; | ||
66 | |||
67 | __raw_writel(value, emac_base + reg); | ||
68 | } | ||
69 | |||
70 | /* ........................... PHY INTERFACE ........................... */ | ||
71 | |||
72 | /* | ||
73 | * Enable the MDIO bit in MAC control register | ||
74 | * When not called from an interrupt-handler, access to the PHY must be | ||
75 | * protected by a spinlock. | ||
76 | */ | ||
77 | static void enable_mdi(void) | ||
78 | { | ||
79 | unsigned long ctl; | ||
80 | |||
81 | ctl = at91_emac_read(AT91_EMAC_CTL); | ||
82 | at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_MPE); /* enable management port */ | ||
83 | } | ||
84 | |||
85 | /* | ||
86 | * Disable the MDIO bit in the MAC control register | ||
87 | */ | ||
88 | static void disable_mdi(void) | ||
89 | { | ||
90 | unsigned long ctl; | ||
91 | |||
92 | ctl = at91_emac_read(AT91_EMAC_CTL); | ||
93 | at91_emac_write(AT91_EMAC_CTL, ctl & ~AT91_EMAC_MPE); /* disable management port */ | ||
94 | } | ||
95 | |||
96 | /* | ||
97 | * Wait until the PHY operation is complete. | ||
98 | */ | ||
99 | static inline void at91_phy_wait(void) { | ||
100 | unsigned long timeout = jiffies + 2; | ||
101 | |||
102 | while (!(at91_emac_read(AT91_EMAC_SR) & AT91_EMAC_SR_IDLE)) { | ||
103 | if (time_after(jiffies, timeout)) { | ||
104 | printk("at91_ether: MIO timeout\n"); | ||
105 | break; | ||
106 | } | ||
107 | cpu_relax(); | ||
108 | } | ||
109 | } | ||
110 | |||
111 | /* | ||
112 | * Write value to the a PHY register | ||
113 | * Note: MDI interface is assumed to already have been enabled. | ||
114 | */ | ||
115 | static void write_phy(unsigned char phy_addr, unsigned char address, unsigned int value) | ||
116 | { | ||
117 | at91_emac_write(AT91_EMAC_MAN, AT91_EMAC_MAN_802_3 | AT91_EMAC_RW_W | ||
118 | | ((phy_addr & 0x1f) << 23) | (address << 18) | (value & AT91_EMAC_DATA)); | ||
119 | |||
120 | /* Wait until IDLE bit in Network Status register is cleared */ | ||
121 | at91_phy_wait(); | ||
122 | } | ||
123 | |||
124 | /* | ||
125 | * Read value stored in a PHY register. | ||
126 | * Note: MDI interface is assumed to already have been enabled. | ||
127 | */ | ||
128 | static void read_phy(unsigned char phy_addr, unsigned char address, unsigned int *value) | ||
129 | { | ||
130 | at91_emac_write(AT91_EMAC_MAN, AT91_EMAC_MAN_802_3 | AT91_EMAC_RW_R | ||
131 | | ((phy_addr & 0x1f) << 23) | (address << 18)); | ||
132 | |||
133 | /* Wait until IDLE bit in Network Status register is cleared */ | ||
134 | at91_phy_wait(); | ||
135 | |||
136 | *value = at91_emac_read(AT91_EMAC_MAN) & AT91_EMAC_DATA; | ||
137 | } | ||
138 | |||
139 | /* ........................... PHY MANAGEMENT .......................... */ | ||
140 | |||
141 | /* | ||
142 | * Access the PHY to determine the current link speed and mode, and update the | ||
143 | * MAC accordingly. | ||
144 | * If no link or auto-negotiation is busy, then no changes are made. | ||
145 | */ | ||
146 | static void update_linkspeed(struct net_device *dev) | ||
147 | { | ||
148 | struct at91_private *lp = (struct at91_private *) dev->priv; | ||
149 | unsigned int bmsr, bmcr, lpa, mac_cfg; | ||
150 | unsigned int speed, duplex; | ||
151 | |||
152 | if (!mii_link_ok(&lp->mii)) { /* no link */ | ||
153 | netif_carrier_off(dev); | ||
154 | printk(KERN_INFO "%s: Link down.\n", dev->name); | ||
155 | return; | ||
156 | } | ||
157 | |||
158 | /* Link up, or auto-negotiation still in progress */ | ||
159 | read_phy(lp->phy_address, MII_BMSR, &bmsr); | ||
160 | read_phy(lp->phy_address, MII_BMCR, &bmcr); | ||
161 | if (bmcr & BMCR_ANENABLE) { /* AutoNegotiation is enabled */ | ||
162 | if (!(bmsr & BMSR_ANEGCOMPLETE)) | ||
163 | return; /* Do nothing - another interrupt generated when negotiation complete */ | ||
164 | |||
165 | read_phy(lp->phy_address, MII_LPA, &lpa); | ||
166 | if ((lpa & LPA_100FULL) || (lpa & LPA_100HALF)) speed = SPEED_100; | ||
167 | else speed = SPEED_10; | ||
168 | if ((lpa & LPA_100FULL) || (lpa & LPA_10FULL)) duplex = DUPLEX_FULL; | ||
169 | else duplex = DUPLEX_HALF; | ||
170 | } else { | ||
171 | speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10; | ||
172 | duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF; | ||
173 | } | ||
174 | |||
175 | /* Update the MAC */ | ||
176 | mac_cfg = at91_emac_read(AT91_EMAC_CFG) & ~(AT91_EMAC_SPD | AT91_EMAC_FD); | ||
177 | if (speed == SPEED_100) { | ||
178 | if (duplex == DUPLEX_FULL) /* 100 Full Duplex */ | ||
179 | mac_cfg |= AT91_EMAC_SPD | AT91_EMAC_FD; | ||
180 | else /* 100 Half Duplex */ | ||
181 | mac_cfg |= AT91_EMAC_SPD; | ||
182 | } else { | ||
183 | if (duplex == DUPLEX_FULL) /* 10 Full Duplex */ | ||
184 | mac_cfg |= AT91_EMAC_FD; | ||
185 | else {} /* 10 Half Duplex */ | ||
186 | } | ||
187 | at91_emac_write(AT91_EMAC_CFG, mac_cfg); | ||
188 | |||
189 | printk(KERN_INFO "%s: Link now %i-%s\n", dev->name, speed, (duplex == DUPLEX_FULL) ? "FullDuplex" : "HalfDuplex"); | ||
190 | netif_carrier_on(dev); | ||
191 | } | ||
192 | |||
193 | /* | ||
194 | * Handle interrupts from the PHY | ||
195 | */ | ||
196 | static irqreturn_t at91ether_phy_interrupt(int irq, void *dev_id, struct pt_regs *regs) | ||
197 | { | ||
198 | struct net_device *dev = (struct net_device *) dev_id; | ||
199 | struct at91_private *lp = (struct at91_private *) dev->priv; | ||
200 | unsigned int phy; | ||
201 | |||
202 | /* | ||
203 | * This hander is triggered on both edges, but the PHY chips expect | ||
204 | * level-triggering. We therefore have to check if the PHY actually has | ||
205 | * an IRQ pending. | ||
206 | */ | ||
207 | enable_mdi(); | ||
208 | if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { | ||
209 | read_phy(lp->phy_address, MII_DSINTR_REG, &phy); /* ack interrupt in Davicom PHY */ | ||
210 | if (!(phy & (1 << 0))) | ||
211 | goto done; | ||
212 | } | ||
213 | else if (lp->phy_type == MII_LXT971A_ID) { | ||
214 | read_phy(lp->phy_address, MII_ISINTS_REG, &phy); /* ack interrupt in Intel PHY */ | ||
215 | if (!(phy & (1 << 2))) | ||
216 | goto done; | ||
217 | } | ||
218 | else if (lp->phy_type == MII_BCM5221_ID) { | ||
219 | read_phy(lp->phy_address, MII_BCMINTR_REG, &phy); /* ack interrupt in Broadcom PHY */ | ||
220 | if (!(phy & (1 << 0))) | ||
221 | goto done; | ||
222 | } | ||
223 | else if (lp->phy_type == MII_KS8721_ID) { | ||
224 | read_phy(lp->phy_address, MII_TPISTATUS, &phy); /* ack interrupt in Micrel PHY */ | ||
225 | if (!(phy & ((1 << 2) | 1))) | ||
226 | goto done; | ||
227 | } | ||
228 | |||
229 | update_linkspeed(dev); | ||
230 | |||
231 | done: | ||
232 | disable_mdi(); | ||
233 | |||
234 | return IRQ_HANDLED; | ||
235 | } | ||
236 | |||
237 | /* | ||
238 | * Initialize and enable the PHY interrupt for link-state changes | ||
239 | */ | ||
240 | static void enable_phyirq(struct net_device *dev) | ||
241 | { | ||
242 | struct at91_private *lp = (struct at91_private *) dev->priv; | ||
243 | unsigned int dsintr, irq_number; | ||
244 | int status; | ||
245 | |||
246 | if (lp->phy_type == MII_RTL8201_ID) /* RTL8201 does not have an interrupt */ | ||
247 | return; | ||
248 | if (lp->phy_type == MII_DP83847_ID) /* DP83847 does not have an interrupt */ | ||
249 | return; | ||
250 | if (lp->phy_type == MII_AC101L_ID) /* AC101L interrupt not supported yet */ | ||
251 | return; | ||
252 | |||
253 | irq_number = lp->board_data.phy_irq_pin; | ||
254 | status = request_irq(irq_number, at91ether_phy_interrupt, 0, dev->name, dev); | ||
255 | if (status) { | ||
256 | printk(KERN_ERR "at91_ether: PHY IRQ %d request failed - status %d!\n", irq_number, status); | ||
257 | return; | ||
258 | } | ||
259 | |||
260 | spin_lock_irq(&lp->lock); | ||
261 | enable_mdi(); | ||
262 | |||
263 | if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { /* for Davicom PHY */ | ||
264 | read_phy(lp->phy_address, MII_DSINTR_REG, &dsintr); | ||
265 | dsintr = dsintr & ~0xf00; /* clear bits 8..11 */ | ||
266 | write_phy(lp->phy_address, MII_DSINTR_REG, dsintr); | ||
267 | } | ||
268 | else if (lp->phy_type == MII_LXT971A_ID) { /* for Intel PHY */ | ||
269 | read_phy(lp->phy_address, MII_ISINTE_REG, &dsintr); | ||
270 | dsintr = dsintr | 0xf2; /* set bits 1, 4..7 */ | ||
271 | write_phy(lp->phy_address, MII_ISINTE_REG, dsintr); | ||
272 | } | ||
273 | else if (lp->phy_type == MII_BCM5221_ID) { /* for Broadcom PHY */ | ||
274 | dsintr = (1 << 15) | ( 1 << 14); | ||
275 | write_phy(lp->phy_address, MII_BCMINTR_REG, dsintr); | ||
276 | } | ||
277 | else if (lp->phy_type == MII_KS8721_ID) { /* for Micrel PHY */ | ||
278 | dsintr = (1 << 10) | ( 1 << 8); | ||
279 | write_phy(lp->phy_address, MII_TPISTATUS, dsintr); | ||
280 | } | ||
281 | |||
282 | disable_mdi(); | ||
283 | spin_unlock_irq(&lp->lock); | ||
284 | } | ||
285 | |||
286 | /* | ||
287 | * Disable the PHY interrupt | ||
288 | */ | ||
289 | static void disable_phyirq(struct net_device *dev) | ||
290 | { | ||
291 | struct at91_private *lp = (struct at91_private *) dev->priv; | ||
292 | unsigned int dsintr; | ||
293 | unsigned int irq_number; | ||
294 | |||
295 | if (lp->phy_type == MII_RTL8201_ID) /* RTL8201 does not have an interrupt */ | ||
296 | return; | ||
297 | if (lp->phy_type == MII_DP83847_ID) /* DP83847 does not have an interrupt */ | ||
298 | return; | ||
299 | if (lp->phy_type == MII_AC101L_ID) /* AC101L interrupt not supported yet */ | ||
300 | return; | ||
301 | |||
302 | spin_lock_irq(&lp->lock); | ||
303 | enable_mdi(); | ||
304 | |||
305 | if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { /* for Davicom PHY */ | ||
306 | read_phy(lp->phy_address, MII_DSINTR_REG, &dsintr); | ||
307 | dsintr = dsintr | 0xf00; /* set bits 8..11 */ | ||
308 | write_phy(lp->phy_address, MII_DSINTR_REG, dsintr); | ||
309 | } | ||
310 | else if (lp->phy_type == MII_LXT971A_ID) { /* for Intel PHY */ | ||
311 | read_phy(lp->phy_address, MII_ISINTE_REG, &dsintr); | ||
312 | dsintr = dsintr & ~0xf2; /* clear bits 1, 4..7 */ | ||
313 | write_phy(lp->phy_address, MII_ISINTE_REG, dsintr); | ||
314 | } | ||
315 | else if (lp->phy_type == MII_BCM5221_ID) { /* for Broadcom PHY */ | ||
316 | read_phy(lp->phy_address, MII_BCMINTR_REG, &dsintr); | ||
317 | dsintr = ~(1 << 14); | ||
318 | write_phy(lp->phy_address, MII_BCMINTR_REG, dsintr); | ||
319 | } | ||
320 | else if (lp->phy_type == MII_KS8721_ID) { /* for Micrel PHY */ | ||
321 | read_phy(lp->phy_address, MII_TPISTATUS, &dsintr); | ||
322 | dsintr = ~((1 << 10) | (1 << 8)); | ||
323 | write_phy(lp->phy_address, MII_TPISTATUS, dsintr); | ||
324 | } | ||
325 | |||
326 | disable_mdi(); | ||
327 | spin_unlock_irq(&lp->lock); | ||
328 | |||
329 | irq_number = lp->board_data.phy_irq_pin; | ||
330 | free_irq(irq_number, dev); /* Free interrupt handler */ | ||
331 | } | ||
332 | |||
333 | /* | ||
334 | * Perform a software reset of the PHY. | ||
335 | */ | ||
336 | #if 0 | ||
337 | static void reset_phy(struct net_device *dev) | ||
338 | { | ||
339 | struct at91_private *lp = (struct at91_private *) dev->priv; | ||
340 | unsigned int bmcr; | ||
341 | |||
342 | spin_lock_irq(&lp->lock); | ||
343 | enable_mdi(); | ||
344 | |||
345 | /* Perform PHY reset */ | ||
346 | write_phy(lp->phy_address, MII_BMCR, BMCR_RESET); | ||
347 | |||
348 | /* Wait until PHY reset is complete */ | ||
349 | do { | ||
350 | read_phy(lp->phy_address, MII_BMCR, &bmcr); | ||
351 | } while (!(bmcr && BMCR_RESET)); | ||
352 | |||
353 | disable_mdi(); | ||
354 | spin_unlock_irq(&lp->lock); | ||
355 | } | ||
356 | #endif | ||
357 | |||
358 | /* ......................... ADDRESS MANAGEMENT ........................ */ | ||
359 | |||
360 | /* | ||
361 | * NOTE: Your bootloader must always set the MAC address correctly before | ||
362 | * booting into Linux. | ||
363 | * | ||
364 | * - It must always set the MAC address after reset, even if it doesn't | ||
365 | * happen to access the Ethernet while it's booting. Some versions of | ||
366 | * U-Boot on the AT91RM9200-DK do not do this. | ||
367 | * | ||
368 | * - Likewise it must store the addresses in the correct byte order. | ||
369 | * MicroMonitor (uMon) on the CSB337 does this incorrectly (and | ||
370 | * continues to do so, for bug-compatibility). | ||
371 | */ | ||
372 | |||
373 | static short __init unpack_mac_address(struct net_device *dev, unsigned int hi, unsigned int lo) | ||
374 | { | ||
375 | char addr[6]; | ||
376 | |||
377 | if (machine_is_csb337()) { | ||
378 | addr[5] = (lo & 0xff); /* The CSB337 bootloader stores the MAC the wrong-way around */ | ||
379 | addr[4] = (lo & 0xff00) >> 8; | ||
380 | addr[3] = (lo & 0xff0000) >> 16; | ||
381 | addr[2] = (lo & 0xff000000) >> 24; | ||
382 | addr[1] = (hi & 0xff); | ||
383 | addr[0] = (hi & 0xff00) >> 8; | ||
384 | } | ||
385 | else { | ||
386 | addr[0] = (lo & 0xff); | ||
387 | addr[1] = (lo & 0xff00) >> 8; | ||
388 | addr[2] = (lo & 0xff0000) >> 16; | ||
389 | addr[3] = (lo & 0xff000000) >> 24; | ||
390 | addr[4] = (hi & 0xff); | ||
391 | addr[5] = (hi & 0xff00) >> 8; | ||
392 | } | ||
393 | |||
394 | if (is_valid_ether_addr(addr)) { | ||
395 | memcpy(dev->dev_addr, &addr, 6); | ||
396 | return 1; | ||
397 | } | ||
398 | return 0; | ||
399 | } | ||
400 | |||
401 | /* | ||
402 | * Set the ethernet MAC address in dev->dev_addr | ||
403 | */ | ||
404 | static void __init get_mac_address(struct net_device *dev) | ||
405 | { | ||
406 | /* Check Specific-Address 1 */ | ||
407 | if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA1H), at91_emac_read(AT91_EMAC_SA1L))) | ||
408 | return; | ||
409 | /* Check Specific-Address 2 */ | ||
410 | if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA2H), at91_emac_read(AT91_EMAC_SA2L))) | ||
411 | return; | ||
412 | /* Check Specific-Address 3 */ | ||
413 | if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA3H), at91_emac_read(AT91_EMAC_SA3L))) | ||
414 | return; | ||
415 | /* Check Specific-Address 4 */ | ||
416 | if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA4H), at91_emac_read(AT91_EMAC_SA4L))) | ||
417 | return; | ||
418 | |||
419 | printk(KERN_ERR "at91_ether: Your bootloader did not configure a MAC address.\n"); | ||
420 | } | ||
421 | |||
422 | /* | ||
423 | * Program the hardware MAC address from dev->dev_addr. | ||
424 | */ | ||
425 | static void update_mac_address(struct net_device *dev) | ||
426 | { | ||
427 | at91_emac_write(AT91_EMAC_SA1L, (dev->dev_addr[3] << 24) | (dev->dev_addr[2] << 16) | (dev->dev_addr[1] << 8) | (dev->dev_addr[0])); | ||
428 | at91_emac_write(AT91_EMAC_SA1H, (dev->dev_addr[5] << 8) | (dev->dev_addr[4])); | ||
429 | |||
430 | at91_emac_write(AT91_EMAC_SA2L, 0); | ||
431 | at91_emac_write(AT91_EMAC_SA2H, 0); | ||
432 | } | ||
433 | |||
434 | /* | ||
435 | * Store the new hardware address in dev->dev_addr, and update the MAC. | ||
436 | */ | ||
437 | static int set_mac_address(struct net_device *dev, void* addr) | ||
438 | { | ||
439 | struct sockaddr *address = addr; | ||
440 | |||
441 | if (!is_valid_ether_addr(address->sa_data)) | ||
442 | return -EADDRNOTAVAIL; | ||
443 | |||
444 | memcpy(dev->dev_addr, address->sa_data, dev->addr_len); | ||
445 | update_mac_address(dev); | ||
446 | |||
447 | printk("%s: Setting MAC address to %02x:%02x:%02x:%02x:%02x:%02x\n", dev->name, | ||
448 | dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], | ||
449 | dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]); | ||
450 | |||
451 | return 0; | ||
452 | } | ||
453 | |||
454 | static int inline hash_bit_value(int bitnr, __u8 *addr) | ||
455 | { | ||
456 | if (addr[bitnr / 8] & (1 << (bitnr % 8))) | ||
457 | return 1; | ||
458 | return 0; | ||
459 | } | ||
460 | |||
461 | /* | ||
462 | * The hash address register is 64 bits long and takes up two locations in the memory map. | ||
463 | * The least significant bits are stored in EMAC_HSL and the most significant | ||
464 | * bits in EMAC_HSH. | ||
465 | * | ||
466 | * The unicast hash enable and the multicast hash enable bits in the network configuration | ||
467 | * register enable the reception of hash matched frames. The destination address is | ||
468 | * reduced to a 6 bit index into the 64 bit hash register using the following hash function. | ||
469 | * The hash function is an exclusive or of every sixth bit of the destination address. | ||
470 | * hash_index[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47] | ||
471 | * hash_index[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46] | ||
472 | * hash_index[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45] | ||
473 | * hash_index[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44] | ||
474 | * hash_index[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43] | ||
475 | * hash_index[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42] | ||
476 | * da[0] represents the least significant bit of the first byte received, that is, the multicast/ | ||
477 | * unicast indicator, and da[47] represents the most significant bit of the last byte | ||
478 | * received. | ||
479 | * If the hash index points to a bit that is set in the hash register then the frame will be | ||
480 | * matched according to whether the frame is multicast or unicast. | ||
481 | * A multicast match will be signalled if the multicast hash enable bit is set, da[0] is 1 and | ||
482 | * the hash index points to a bit set in the hash register. | ||
483 | * A unicast match will be signalled if the unicast hash enable bit is set, da[0] is 0 and the | ||
484 | * hash index points to a bit set in the hash register. | ||
485 | * To receive all multicast frames, the hash register should be set with all ones and the | ||
486 | * multicast hash enable bit should be set in the network configuration register. | ||
487 | */ | ||
488 | |||
489 | /* | ||
490 | * Return the hash index value for the specified address. | ||
491 | */ | ||
492 | static int hash_get_index(__u8 *addr) | ||
493 | { | ||
494 | int i, j, bitval; | ||
495 | int hash_index = 0; | ||
496 | |||
497 | for (j = 0; j < 6; j++) { | ||
498 | for (i = 0, bitval = 0; i < 8; i++) | ||
499 | bitval ^= hash_bit_value(i*6 + j, addr); | ||
500 | |||
501 | hash_index |= (bitval << j); | ||
502 | } | ||
503 | |||
504 | return hash_index; | ||
505 | } | ||
506 | |||
507 | /* | ||
508 | * Add multicast addresses to the internal multicast-hash table. | ||
509 | */ | ||
510 | static void at91ether_sethashtable(struct net_device *dev) | ||
511 | { | ||
512 | struct dev_mc_list *curr; | ||
513 | unsigned long mc_filter[2]; | ||
514 | unsigned int i, bitnr; | ||
515 | |||
516 | mc_filter[0] = mc_filter[1] = 0; | ||
517 | |||
518 | curr = dev->mc_list; | ||
519 | for (i = 0; i < dev->mc_count; i++, curr = curr->next) { | ||
520 | if (!curr) break; /* unexpected end of list */ | ||
521 | |||
522 | bitnr = hash_get_index(curr->dmi_addr); | ||
523 | mc_filter[bitnr >> 5] |= 1 << (bitnr & 31); | ||
524 | } | ||
525 | |||
526 | at91_emac_write(AT91_EMAC_HSH, mc_filter[0]); | ||
527 | at91_emac_write(AT91_EMAC_HSL, mc_filter[1]); | ||
528 | } | ||
529 | |||
530 | /* | ||
531 | * Enable/Disable promiscuous and multicast modes. | ||
532 | */ | ||
533 | static void at91ether_set_rx_mode(struct net_device *dev) | ||
534 | { | ||
535 | unsigned long cfg; | ||
536 | |||
537 | cfg = at91_emac_read(AT91_EMAC_CFG); | ||
538 | |||
539 | if (dev->flags & IFF_PROMISC) /* Enable promiscuous mode */ | ||
540 | cfg |= AT91_EMAC_CAF; | ||
541 | else if (dev->flags & (~IFF_PROMISC)) /* Disable promiscuous mode */ | ||
542 | cfg &= ~AT91_EMAC_CAF; | ||
543 | |||
544 | if (dev->flags & IFF_ALLMULTI) { /* Enable all multicast mode */ | ||
545 | at91_emac_write(AT91_EMAC_HSH, -1); | ||
546 | at91_emac_write(AT91_EMAC_HSL, -1); | ||
547 | cfg |= AT91_EMAC_MTI; | ||
548 | } else if (dev->mc_count > 0) { /* Enable specific multicasts */ | ||
549 | at91ether_sethashtable(dev); | ||
550 | cfg |= AT91_EMAC_MTI; | ||
551 | } else if (dev->flags & (~IFF_ALLMULTI)) { /* Disable all multicast mode */ | ||
552 | at91_emac_write(AT91_EMAC_HSH, 0); | ||
553 | at91_emac_write(AT91_EMAC_HSL, 0); | ||
554 | cfg &= ~AT91_EMAC_MTI; | ||
555 | } | ||
556 | |||
557 | at91_emac_write(AT91_EMAC_CFG, cfg); | ||
558 | } | ||
559 | |||
560 | |||
561 | /* ......................... ETHTOOL SUPPORT ........................... */ | ||
562 | |||
563 | |||
564 | static int mdio_read(struct net_device *dev, int phy_id, int location) | ||
565 | { | ||
566 | unsigned int value; | ||
567 | |||
568 | read_phy(phy_id, location, &value); | ||
569 | return value; | ||
570 | } | ||
571 | |||
572 | static void mdio_write(struct net_device *dev, int phy_id, int location, int value) | ||
573 | { | ||
574 | write_phy(phy_id, location, value); | ||
575 | } | ||
576 | |||
577 | static int at91ether_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | ||
578 | { | ||
579 | struct at91_private *lp = (struct at91_private *) dev->priv; | ||
580 | int ret; | ||
581 | |||
582 | spin_lock_irq(&lp->lock); | ||
583 | enable_mdi(); | ||
584 | |||
585 | ret = mii_ethtool_gset(&lp->mii, cmd); | ||
586 | |||
587 | disable_mdi(); | ||
588 | spin_unlock_irq(&lp->lock); | ||
589 | |||
590 | if (lp->phy_media == PORT_FIBRE) { /* override media type since mii.c doesn't know */ | ||
591 | cmd->supported = SUPPORTED_FIBRE; | ||
592 | cmd->port = PORT_FIBRE; | ||
593 | } | ||
594 | |||
595 | return ret; | ||
596 | } | ||
597 | |||
598 | static int at91ether_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | ||
599 | { | ||
600 | struct at91_private *lp = (struct at91_private *) dev->priv; | ||
601 | int ret; | ||
602 | |||
603 | spin_lock_irq(&lp->lock); | ||
604 | enable_mdi(); | ||
605 | |||
606 | ret = mii_ethtool_sset(&lp->mii, cmd); | ||
607 | |||
608 | disable_mdi(); | ||
609 | spin_unlock_irq(&lp->lock); | ||
610 | |||
611 | return ret; | ||
612 | } | ||
613 | |||
614 | static int at91ether_nwayreset(struct net_device *dev) | ||
615 | { | ||
616 | struct at91_private *lp = (struct at91_private *) dev->priv; | ||
617 | int ret; | ||
618 | |||
619 | spin_lock_irq(&lp->lock); | ||
620 | enable_mdi(); | ||
621 | |||
622 | ret = mii_nway_restart(&lp->mii); | ||
623 | |||
624 | disable_mdi(); | ||
625 | spin_unlock_irq(&lp->lock); | ||
626 | |||
627 | return ret; | ||
628 | } | ||
629 | |||
630 | static void at91ether_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) | ||
631 | { | ||
632 | strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); | ||
633 | strlcpy(info->version, DRV_VERSION, sizeof(info->version)); | ||
634 | strlcpy(info->bus_info, dev->class_dev.dev->bus_id, sizeof(info->bus_info)); | ||
635 | } | ||
636 | |||
637 | static struct ethtool_ops at91ether_ethtool_ops = { | ||
638 | .get_settings = at91ether_get_settings, | ||
639 | .set_settings = at91ether_set_settings, | ||
640 | .get_drvinfo = at91ether_get_drvinfo, | ||
641 | .nway_reset = at91ether_nwayreset, | ||
642 | .get_link = ethtool_op_get_link, | ||
643 | }; | ||
644 | |||
645 | |||
646 | /* ................................ MAC ................................ */ | ||
647 | |||
648 | /* | ||
649 | * Initialize and start the Receiver and Transmit subsystems | ||
650 | */ | ||
651 | static void at91ether_start(struct net_device *dev) | ||
652 | { | ||
653 | struct at91_private *lp = (struct at91_private *) dev->priv; | ||
654 | struct recv_desc_bufs *dlist, *dlist_phys; | ||
655 | int i; | ||
656 | unsigned long ctl; | ||
657 | |||
658 | dlist = lp->dlist; | ||
659 | dlist_phys = lp->dlist_phys; | ||
660 | |||
661 | for (i = 0; i < MAX_RX_DESCR; i++) { | ||
662 | dlist->descriptors[i].addr = (unsigned int) &dlist_phys->recv_buf[i][0]; | ||
663 | dlist->descriptors[i].size = 0; | ||
664 | } | ||
665 | |||
666 | /* Set the Wrap bit on the last descriptor */ | ||
667 | dlist->descriptors[i-1].addr |= EMAC_DESC_WRAP; | ||
668 | |||
669 | /* Reset buffer index */ | ||
670 | lp->rxBuffIndex = 0; | ||
671 | |||
672 | /* Program address of descriptor list in Rx Buffer Queue register */ | ||
673 | at91_emac_write(AT91_EMAC_RBQP, (unsigned long) dlist_phys); | ||
674 | |||
675 | /* Enable Receive and Transmit */ | ||
676 | ctl = at91_emac_read(AT91_EMAC_CTL); | ||
677 | at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_RE | AT91_EMAC_TE); | ||
678 | } | ||
679 | |||
680 | /* | ||
681 | * Open the ethernet interface | ||
682 | */ | ||
683 | static int at91ether_open(struct net_device *dev) | ||
684 | { | ||
685 | struct at91_private *lp = (struct at91_private *) dev->priv; | ||
686 | unsigned long ctl; | ||
687 | |||
688 | if (!is_valid_ether_addr(dev->dev_addr)) | ||
689 | return -EADDRNOTAVAIL; | ||
690 | |||
691 | clk_enable(ether_clk); /* Re-enable Peripheral clock */ | ||
692 | |||
693 | /* Clear internal statistics */ | ||
694 | ctl = at91_emac_read(AT91_EMAC_CTL); | ||
695 | at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_CSR); | ||
696 | |||
697 | /* Update the MAC address (incase user has changed it) */ | ||
698 | update_mac_address(dev); | ||
699 | |||
700 | /* Enable PHY interrupt */ | ||
701 | enable_phyirq(dev); | ||
702 | |||
703 | /* Enable MAC interrupts */ | ||
704 | at91_emac_write(AT91_EMAC_IER, AT91_EMAC_RCOM | AT91_EMAC_RBNA | ||
705 | | AT91_EMAC_TUND | AT91_EMAC_RTRY | AT91_EMAC_TCOM | ||
706 | | AT91_EMAC_ROVR | AT91_EMAC_ABT); | ||
707 | |||
708 | /* Determine current link speed */ | ||
709 | spin_lock_irq(&lp->lock); | ||
710 | enable_mdi(); | ||
711 | update_linkspeed(dev); | ||
712 | disable_mdi(); | ||
713 | spin_unlock_irq(&lp->lock); | ||
714 | |||
715 | at91ether_start(dev); | ||
716 | netif_start_queue(dev); | ||
717 | return 0; | ||
718 | } | ||
719 | |||
720 | /* | ||
721 | * Close the interface | ||
722 | */ | ||
723 | static int at91ether_close(struct net_device *dev) | ||
724 | { | ||
725 | unsigned long ctl; | ||
726 | |||
727 | /* Disable Receiver and Transmitter */ | ||
728 | ctl = at91_emac_read(AT91_EMAC_CTL); | ||
729 | at91_emac_write(AT91_EMAC_CTL, ctl & ~(AT91_EMAC_TE | AT91_EMAC_RE)); | ||
730 | |||
731 | /* Disable PHY interrupt */ | ||
732 | disable_phyirq(dev); | ||
733 | |||
734 | /* Disable MAC interrupts */ | ||
735 | at91_emac_write(AT91_EMAC_IDR, AT91_EMAC_RCOM | AT91_EMAC_RBNA | ||
736 | | AT91_EMAC_TUND | AT91_EMAC_RTRY | AT91_EMAC_TCOM | ||
737 | | AT91_EMAC_ROVR | AT91_EMAC_ABT); | ||
738 | |||
739 | netif_stop_queue(dev); | ||
740 | |||
741 | clk_disable(ether_clk); /* Disable Peripheral clock */ | ||
742 | |||
743 | return 0; | ||
744 | } | ||
745 | |||
746 | /* | ||
747 | * Transmit packet. | ||
748 | */ | ||
749 | static int at91ether_tx(struct sk_buff *skb, struct net_device *dev) | ||
750 | { | ||
751 | struct at91_private *lp = (struct at91_private *) dev->priv; | ||
752 | |||
753 | if (at91_emac_read(AT91_EMAC_TSR) & AT91_EMAC_TSR_BNQ) { | ||
754 | netif_stop_queue(dev); | ||
755 | |||
756 | /* Store packet information (to free when Tx completed) */ | ||
757 | lp->skb = skb; | ||
758 | lp->skb_length = skb->len; | ||
759 | lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE); | ||
760 | lp->stats.tx_bytes += skb->len; | ||
761 | |||
762 | /* Set address of the data in the Transmit Address register */ | ||
763 | at91_emac_write(AT91_EMAC_TAR, lp->skb_physaddr); | ||
764 | /* Set length of the packet in the Transmit Control register */ | ||
765 | at91_emac_write(AT91_EMAC_TCR, skb->len); | ||
766 | |||
767 | dev->trans_start = jiffies; | ||
768 | } else { | ||
769 | printk(KERN_ERR "at91_ether.c: at91ether_tx() called, but device is busy!\n"); | ||
770 | return 1; /* if we return anything but zero, dev.c:1055 calls kfree_skb(skb) | ||
771 | on this skb, he also reports -ENETDOWN and printk's, so either | ||
772 | we free and return(0) or don't free and return 1 */ | ||
773 | } | ||
774 | |||
775 | return 0; | ||
776 | } | ||
777 | |||
778 | /* | ||
779 | * Update the current statistics from the internal statistics registers. | ||
780 | */ | ||
781 | static struct net_device_stats *at91ether_stats(struct net_device *dev) | ||
782 | { | ||
783 | struct at91_private *lp = (struct at91_private *) dev->priv; | ||
784 | int ale, lenerr, seqe, lcol, ecol; | ||
785 | |||
786 | if (netif_running(dev)) { | ||
787 | lp->stats.rx_packets += at91_emac_read(AT91_EMAC_OK); /* Good frames received */ | ||
788 | ale = at91_emac_read(AT91_EMAC_ALE); | ||
789 | lp->stats.rx_frame_errors += ale; /* Alignment errors */ | ||
790 | lenerr = at91_emac_read(AT91_EMAC_ELR) + at91_emac_read(AT91_EMAC_USF); | ||
791 | lp->stats.rx_length_errors += lenerr; /* Excessive Length or Undersize Frame error */ | ||
792 | seqe = at91_emac_read(AT91_EMAC_SEQE); | ||
793 | lp->stats.rx_crc_errors += seqe; /* CRC error */ | ||
794 | lp->stats.rx_fifo_errors += at91_emac_read(AT91_EMAC_DRFC); /* Receive buffer not available */ | ||
795 | lp->stats.rx_errors += (ale + lenerr + seqe | ||
796 | + at91_emac_read(AT91_EMAC_CDE) + at91_emac_read(AT91_EMAC_RJB)); | ||
797 | |||
798 | lp->stats.tx_packets += at91_emac_read(AT91_EMAC_FRA); /* Frames successfully transmitted */ | ||
799 | lp->stats.tx_fifo_errors += at91_emac_read(AT91_EMAC_TUE); /* Transmit FIFO underruns */ | ||
800 | lp->stats.tx_carrier_errors += at91_emac_read(AT91_EMAC_CSE); /* Carrier Sense errors */ | ||
801 | lp->stats.tx_heartbeat_errors += at91_emac_read(AT91_EMAC_SQEE);/* Heartbeat error */ | ||
802 | |||
803 | lcol = at91_emac_read(AT91_EMAC_LCOL); | ||
804 | ecol = at91_emac_read(AT91_EMAC_ECOL); | ||
805 | lp->stats.tx_window_errors += lcol; /* Late collisions */ | ||
806 | lp->stats.tx_aborted_errors += ecol; /* 16 collisions */ | ||
807 | |||
808 | lp->stats.collisions += (at91_emac_read(AT91_EMAC_SCOL) + at91_emac_read(AT91_EMAC_MCOL) + lcol + ecol); | ||
809 | } | ||
810 | return &lp->stats; | ||
811 | } | ||
812 | |||
813 | /* | ||
814 | * Extract received frame from buffer descriptors and sent to upper layers. | ||
815 | * (Called from interrupt context) | ||
816 | */ | ||
817 | static void at91ether_rx(struct net_device *dev) | ||
818 | { | ||
819 | struct at91_private *lp = (struct at91_private *) dev->priv; | ||
820 | struct recv_desc_bufs *dlist; | ||
821 | unsigned char *p_recv; | ||
822 | struct sk_buff *skb; | ||
823 | unsigned int pktlen; | ||
824 | |||
825 | dlist = lp->dlist; | ||
826 | while (dlist->descriptors[lp->rxBuffIndex].addr & EMAC_DESC_DONE) { | ||
827 | p_recv = dlist->recv_buf[lp->rxBuffIndex]; | ||
828 | pktlen = dlist->descriptors[lp->rxBuffIndex].size & 0x7ff; /* Length of frame including FCS */ | ||
829 | skb = alloc_skb(pktlen + 2, GFP_ATOMIC); | ||
830 | if (skb != NULL) { | ||
831 | skb_reserve(skb, 2); | ||
832 | memcpy(skb_put(skb, pktlen), p_recv, pktlen); | ||
833 | |||
834 | skb->dev = dev; | ||
835 | skb->protocol = eth_type_trans(skb, dev); | ||
836 | skb->len = pktlen; | ||
837 | dev->last_rx = jiffies; | ||
838 | lp->stats.rx_bytes += pktlen; | ||
839 | netif_rx(skb); | ||
840 | } | ||
841 | else { | ||
842 | lp->stats.rx_dropped += 1; | ||
843 | printk(KERN_NOTICE "%s: Memory squeeze, dropping packet.\n", dev->name); | ||
844 | } | ||
845 | |||
846 | if (dlist->descriptors[lp->rxBuffIndex].size & EMAC_MULTICAST) | ||
847 | lp->stats.multicast++; | ||
848 | |||
849 | dlist->descriptors[lp->rxBuffIndex].addr &= ~EMAC_DESC_DONE; /* reset ownership bit */ | ||
850 | if (lp->rxBuffIndex == MAX_RX_DESCR-1) /* wrap after last buffer */ | ||
851 | lp->rxBuffIndex = 0; | ||
852 | else | ||
853 | lp->rxBuffIndex++; | ||
854 | } | ||
855 | } | ||
856 | |||
857 | /* | ||
858 | * MAC interrupt handler | ||
859 | */ | ||
860 | static irqreturn_t at91ether_interrupt(int irq, void *dev_id, struct pt_regs *regs) | ||
861 | { | ||
862 | struct net_device *dev = (struct net_device *) dev_id; | ||
863 | struct at91_private *lp = (struct at91_private *) dev->priv; | ||
864 | unsigned long intstatus, ctl; | ||
865 | |||
866 | /* MAC Interrupt Status register indicates what interrupts are pending. | ||
867 | It is automatically cleared once read. */ | ||
868 | intstatus = at91_emac_read(AT91_EMAC_ISR); | ||
869 | |||
870 | if (intstatus & AT91_EMAC_RCOM) /* Receive complete */ | ||
871 | at91ether_rx(dev); | ||
872 | |||
873 | if (intstatus & AT91_EMAC_TCOM) { /* Transmit complete */ | ||
874 | /* The TCOM bit is set even if the transmission failed. */ | ||
875 | if (intstatus & (AT91_EMAC_TUND | AT91_EMAC_RTRY)) | ||
876 | lp->stats.tx_errors += 1; | ||
877 | |||
878 | if (lp->skb) { | ||
879 | dev_kfree_skb_irq(lp->skb); | ||
880 | lp->skb = NULL; | ||
881 | dma_unmap_single(NULL, lp->skb_physaddr, lp->skb_length, DMA_TO_DEVICE); | ||
882 | } | ||
883 | netif_wake_queue(dev); | ||
884 | } | ||
885 | |||
886 | /* Work-around for Errata #11 */ | ||
887 | if (intstatus & AT91_EMAC_RBNA) { | ||
888 | ctl = at91_emac_read(AT91_EMAC_CTL); | ||
889 | at91_emac_write(AT91_EMAC_CTL, ctl & ~AT91_EMAC_RE); | ||
890 | at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_RE); | ||
891 | } | ||
892 | |||
893 | if (intstatus & AT91_EMAC_ROVR) | ||
894 | printk("%s: ROVR error\n", dev->name); | ||
895 | |||
896 | return IRQ_HANDLED; | ||
897 | } | ||
898 | |||
899 | /* | ||
900 | * Initialize the ethernet interface | ||
901 | */ | ||
902 | static int __init at91ether_setup(unsigned long phy_type, unsigned short phy_address, struct platform_device *pdev) | ||
903 | { | ||
904 | struct at91_eth_data *board_data = pdev->dev.platform_data; | ||
905 | struct net_device *dev; | ||
906 | struct at91_private *lp; | ||
907 | unsigned int val; | ||
908 | int res; | ||
909 | |||
910 | if (at91_dev) /* already initialized */ | ||
911 | return 0; | ||
912 | |||
913 | dev = alloc_etherdev(sizeof(struct at91_private)); | ||
914 | if (!dev) | ||
915 | return -ENOMEM; | ||
916 | |||
917 | dev->base_addr = AT91_VA_BASE_EMAC; | ||
918 | dev->irq = AT91_ID_EMAC; | ||
919 | SET_MODULE_OWNER(dev); | ||
920 | |||
921 | /* Install the interrupt handler */ | ||
922 | if (request_irq(dev->irq, at91ether_interrupt, 0, dev->name, dev)) { | ||
923 | free_netdev(dev); | ||
924 | return -EBUSY; | ||
925 | } | ||
926 | |||
927 | /* Allocate memory for DMA Receive descriptors */ | ||
928 | lp = (struct at91_private *)dev->priv; | ||
929 | lp->dlist = (struct recv_desc_bufs *) dma_alloc_coherent(NULL, sizeof(struct recv_desc_bufs), (dma_addr_t *) &lp->dlist_phys, GFP_KERNEL); | ||
930 | if (lp->dlist == NULL) { | ||
931 | free_irq(dev->irq, dev); | ||
932 | free_netdev(dev); | ||
933 | return -ENOMEM; | ||
934 | } | ||
935 | lp->board_data = *board_data; | ||
936 | platform_set_drvdata(pdev, dev); | ||
937 | |||
938 | spin_lock_init(&lp->lock); | ||
939 | |||
940 | ether_setup(dev); | ||
941 | dev->open = at91ether_open; | ||
942 | dev->stop = at91ether_close; | ||
943 | dev->hard_start_xmit = at91ether_tx; | ||
944 | dev->get_stats = at91ether_stats; | ||
945 | dev->set_multicast_list = at91ether_set_rx_mode; | ||
946 | dev->set_mac_address = set_mac_address; | ||
947 | dev->ethtool_ops = &at91ether_ethtool_ops; | ||
948 | |||
949 | SET_NETDEV_DEV(dev, &pdev->dev); | ||
950 | |||
951 | get_mac_address(dev); /* Get ethernet address and store it in dev->dev_addr */ | ||
952 | update_mac_address(dev); /* Program ethernet address into MAC */ | ||
953 | |||
954 | at91_emac_write(AT91_EMAC_CTL, 0); | ||
955 | |||
956 | if (lp->board_data.is_rmii) | ||
957 | at91_emac_write(AT91_EMAC_CFG, AT91_EMAC_CLK_DIV32 | AT91_EMAC_BIG | AT91_EMAC_RMII); | ||
958 | else | ||
959 | at91_emac_write(AT91_EMAC_CFG, AT91_EMAC_CLK_DIV32 | AT91_EMAC_BIG); | ||
960 | |||
961 | /* Perform PHY-specific initialization */ | ||
962 | spin_lock_irq(&lp->lock); | ||
963 | enable_mdi(); | ||
964 | if ((phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { | ||
965 | read_phy(phy_address, MII_DSCR_REG, &val); | ||
966 | if ((val & (1 << 10)) == 0) /* DSCR bit 10 is 0 -- fiber mode */ | ||
967 | lp->phy_media = PORT_FIBRE; | ||
968 | } else if (machine_is_csb337()) { | ||
969 | /* mix link activity status into LED2 link state */ | ||
970 | write_phy(phy_address, MII_LEDCTRL_REG, 0x0d22); | ||
971 | } | ||
972 | disable_mdi(); | ||
973 | spin_unlock_irq(&lp->lock); | ||
974 | |||
975 | lp->mii.dev = dev; /* Support for ethtool */ | ||
976 | lp->mii.mdio_read = mdio_read; | ||
977 | lp->mii.mdio_write = mdio_write; | ||
978 | |||
979 | lp->phy_type = phy_type; /* Type of PHY connected */ | ||
980 | lp->phy_address = phy_address; /* MDI address of PHY */ | ||
981 | |||
982 | /* Register the network interface */ | ||
983 | res = register_netdev(dev); | ||
984 | if (res) { | ||
985 | free_irq(dev->irq, dev); | ||
986 | free_netdev(dev); | ||
987 | dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys); | ||
988 | return res; | ||
989 | } | ||
990 | at91_dev = dev; | ||
991 | |||
992 | /* Determine current link speed */ | ||
993 | spin_lock_irq(&lp->lock); | ||
994 | enable_mdi(); | ||
995 | update_linkspeed(dev); | ||
996 | disable_mdi(); | ||
997 | spin_unlock_irq(&lp->lock); | ||
998 | netif_carrier_off(dev); /* will be enabled in open() */ | ||
999 | |||
1000 | /* Display ethernet banner */ | ||
1001 | printk(KERN_INFO "%s: AT91 ethernet at 0x%08x int=%d %s%s (%02x:%02x:%02x:%02x:%02x:%02x)\n", | ||
1002 | dev->name, (uint) dev->base_addr, dev->irq, | ||
1003 | at91_emac_read(AT91_EMAC_CFG) & AT91_EMAC_SPD ? "100-" : "10-", | ||
1004 | at91_emac_read(AT91_EMAC_CFG) & AT91_EMAC_FD ? "FullDuplex" : "HalfDuplex", | ||
1005 | dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], | ||
1006 | dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]); | ||
1007 | if ((phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) | ||
1008 | printk(KERN_INFO "%s: Davicom 9196 PHY %s\n", dev->name, (lp->phy_media == PORT_FIBRE) ? "(Fiber)" : "(Copper)"); | ||
1009 | else if (phy_type == MII_LXT971A_ID) | ||
1010 | printk(KERN_INFO "%s: Intel LXT971A PHY\n", dev->name); | ||
1011 | else if (phy_type == MII_RTL8201_ID) | ||
1012 | printk(KERN_INFO "%s: Realtek RTL8201(B)L PHY\n", dev->name); | ||
1013 | else if (phy_type == MII_BCM5221_ID) | ||
1014 | printk(KERN_INFO "%s: Broadcom BCM5221 PHY\n", dev->name); | ||
1015 | else if (phy_type == MII_DP83847_ID) | ||
1016 | printk(KERN_INFO "%s: National Semiconductor DP83847 PHY\n", dev->name); | ||
1017 | else if (phy_type == MII_AC101L_ID) | ||
1018 | printk(KERN_INFO "%s: Altima AC101L PHY\n", dev->name); | ||
1019 | else if (phy_type == MII_KS8721_ID) | ||
1020 | printk(KERN_INFO "%s: Micrel KS8721 PHY\n", dev->name); | ||
1021 | |||
1022 | return 0; | ||
1023 | } | ||
1024 | |||
1025 | /* | ||
1026 | * Detect MAC and PHY and perform initialization | ||
1027 | */ | ||
1028 | static int __init at91ether_probe(struct platform_device *pdev) | ||
1029 | { | ||
1030 | unsigned int phyid1, phyid2; | ||
1031 | int detected = -1; | ||
1032 | unsigned long phy_id; | ||
1033 | unsigned short phy_address = 0; | ||
1034 | |||
1035 | ether_clk = clk_get(&pdev->dev, "ether_clk"); | ||
1036 | if (!ether_clk) { | ||
1037 | printk(KERN_ERR "at91_ether: no clock defined\n"); | ||
1038 | return -ENODEV; | ||
1039 | } | ||
1040 | clk_enable(ether_clk); /* Enable Peripheral clock */ | ||
1041 | |||
1042 | while ((detected != 0) && (phy_address < 32)) { | ||
1043 | /* Read the PHY ID registers */ | ||
1044 | enable_mdi(); | ||
1045 | read_phy(phy_address, MII_PHYSID1, &phyid1); | ||
1046 | read_phy(phy_address, MII_PHYSID2, &phyid2); | ||
1047 | disable_mdi(); | ||
1048 | |||
1049 | phy_id = (phyid1 << 16) | (phyid2 & 0xfff0); | ||
1050 | switch (phy_id) { | ||
1051 | case MII_DM9161_ID: /* Davicom 9161: PHY_ID1 = 0x181, PHY_ID2 = B881 */ | ||
1052 | case MII_DM9161A_ID: /* Davicom 9161A: PHY_ID1 = 0x181, PHY_ID2 = B8A0 */ | ||
1053 | case MII_LXT971A_ID: /* Intel LXT971A: PHY_ID1 = 0x13, PHY_ID2 = 78E0 */ | ||
1054 | case MII_RTL8201_ID: /* Realtek RTL8201: PHY_ID1 = 0, PHY_ID2 = 0x8201 */ | ||
1055 | case MII_BCM5221_ID: /* Broadcom BCM5221: PHY_ID1 = 0x40, PHY_ID2 = 0x61e0 */ | ||
1056 | case MII_DP83847_ID: /* National Semiconductor DP83847: */ | ||
1057 | case MII_AC101L_ID: /* Altima AC101L: PHY_ID1 = 0x22, PHY_ID2 = 0x5520 */ | ||
1058 | case MII_KS8721_ID: /* Micrel KS8721: PHY_ID1 = 0x22, PHY_ID2 = 0x1610 */ | ||
1059 | detected = at91ether_setup(phy_id, phy_address, pdev); | ||
1060 | break; | ||
1061 | } | ||
1062 | |||
1063 | phy_address++; | ||
1064 | } | ||
1065 | |||
1066 | clk_disable(ether_clk); /* Disable Peripheral clock */ | ||
1067 | |||
1068 | return detected; | ||
1069 | } | ||
1070 | |||
1071 | static int __devexit at91ether_remove(struct platform_device *pdev) | ||
1072 | { | ||
1073 | struct at91_private *lp = (struct at91_private *) at91_dev->priv; | ||
1074 | |||
1075 | unregister_netdev(at91_dev); | ||
1076 | free_irq(at91_dev->irq, at91_dev); | ||
1077 | dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys); | ||
1078 | clk_put(ether_clk); | ||
1079 | |||
1080 | free_netdev(at91_dev); | ||
1081 | at91_dev = NULL; | ||
1082 | return 0; | ||
1083 | } | ||
1084 | |||
1085 | static struct platform_driver at91ether_driver = { | ||
1086 | .probe = at91ether_probe, | ||
1087 | .remove = __devexit_p(at91ether_remove), | ||
1088 | /* FIXME: support suspend and resume */ | ||
1089 | .driver = { | ||
1090 | .name = DRV_NAME, | ||
1091 | .owner = THIS_MODULE, | ||
1092 | }, | ||
1093 | }; | ||
1094 | |||
1095 | static int __init at91ether_init(void) | ||
1096 | { | ||
1097 | return platform_driver_register(&at91ether_driver); | ||
1098 | } | ||
1099 | |||
1100 | static void __exit at91ether_exit(void) | ||
1101 | { | ||
1102 | platform_driver_unregister(&at91ether_driver); | ||
1103 | } | ||
1104 | |||
1105 | module_init(at91ether_init) | ||
1106 | module_exit(at91ether_exit) | ||
1107 | |||
1108 | MODULE_LICENSE("GPL"); | ||
1109 | MODULE_DESCRIPTION("AT91RM9200 EMAC Ethernet driver"); | ||
1110 | MODULE_AUTHOR("Andrew Victor"); | ||
diff --git a/drivers/net/arm/at91_ether.h b/drivers/net/arm/at91_ether.h new file mode 100644 index 000000000000..9885735c9c8a --- /dev/null +++ b/drivers/net/arm/at91_ether.h | |||
@@ -0,0 +1,101 @@ | |||
1 | /* | ||
2 | * Ethernet driver for the Atmel AT91RM9200 (Thunder) | ||
3 | * | ||
4 | * Copyright (C) SAN People (Pty) Ltd | ||
5 | * | ||
6 | * Based on an earlier Atmel EMAC macrocell driver by Atmel and Lineo Inc. | ||
7 | * Initial version by Rick Bronson. | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or | ||
10 | * modify it under the terms of the GNU General Public License | ||
11 | * as published by the Free Software Foundation; either version | ||
12 | * 2 of the License, or (at your option) any later version. | ||
13 | */ | ||
14 | |||
15 | #ifndef AT91_ETHERNET | ||
16 | #define AT91_ETHERNET | ||
17 | |||
18 | |||
19 | /* Davicom 9161 PHY */ | ||
20 | #define MII_DM9161_ID 0x0181b880 | ||
21 | #define MII_DM9161A_ID 0x0181b8a0 | ||
22 | |||
23 | /* Davicom specific registers */ | ||
24 | #define MII_DSCR_REG 16 | ||
25 | #define MII_DSCSR_REG 17 | ||
26 | #define MII_DSINTR_REG 21 | ||
27 | |||
28 | /* Intel LXT971A PHY */ | ||
29 | #define MII_LXT971A_ID 0x001378E0 | ||
30 | |||
31 | /* Intel specific registers */ | ||
32 | #define MII_ISINTE_REG 18 | ||
33 | #define MII_ISINTS_REG 19 | ||
34 | #define MII_LEDCTRL_REG 20 | ||
35 | |||
36 | /* Realtek RTL8201 PHY */ | ||
37 | #define MII_RTL8201_ID 0x00008200 | ||
38 | |||
39 | /* Broadcom BCM5221 PHY */ | ||
40 | #define MII_BCM5221_ID 0x004061e0 | ||
41 | |||
42 | /* Broadcom specific registers */ | ||
43 | #define MII_BCMINTR_REG 26 | ||
44 | |||
45 | /* National Semiconductor DP83847 */ | ||
46 | #define MII_DP83847_ID 0x20005c30 | ||
47 | |||
48 | /* Altima AC101L PHY */ | ||
49 | #define MII_AC101L_ID 0x00225520 | ||
50 | |||
51 | /* Micrel KS8721 PHY */ | ||
52 | #define MII_KS8721_ID 0x00221610 | ||
53 | |||
54 | /* ........................................................................ */ | ||
55 | |||
56 | #define MAX_RBUFF_SZ 0x600 /* 1518 rounded up */ | ||
57 | #define MAX_RX_DESCR 9 /* max number of receive buffers */ | ||
58 | |||
59 | #define EMAC_DESC_DONE 0x00000001 /* bit for if DMA is done */ | ||
60 | #define EMAC_DESC_WRAP 0x00000002 /* bit for wrap */ | ||
61 | |||
62 | #define EMAC_BROADCAST 0x80000000 /* broadcast address */ | ||
63 | #define EMAC_MULTICAST 0x40000000 /* multicast address */ | ||
64 | #define EMAC_UNICAST 0x20000000 /* unicast address */ | ||
65 | |||
66 | struct rbf_t | ||
67 | { | ||
68 | unsigned int addr; | ||
69 | unsigned long size; | ||
70 | }; | ||
71 | |||
72 | struct recv_desc_bufs | ||
73 | { | ||
74 | struct rbf_t descriptors[MAX_RX_DESCR]; /* must be on sizeof (rbf_t) boundary */ | ||
75 | char recv_buf[MAX_RX_DESCR][MAX_RBUFF_SZ]; /* must be on long boundary */ | ||
76 | }; | ||
77 | |||
78 | struct at91_private | ||
79 | { | ||
80 | struct net_device_stats stats; | ||
81 | struct mii_if_info mii; /* ethtool support */ | ||
82 | struct at91_eth_data board_data; /* board-specific configuration */ | ||
83 | |||
84 | /* PHY */ | ||
85 | unsigned long phy_type; /* type of PHY (PHY_ID) */ | ||
86 | spinlock_t lock; /* lock for MDI interface */ | ||
87 | short phy_media; /* media interface type */ | ||
88 | unsigned short phy_address; /* 5-bit MDI address of PHY (0..31) */ | ||
89 | |||
90 | /* Transmit */ | ||
91 | struct sk_buff *skb; /* holds skb until xmit interrupt completes */ | ||
92 | dma_addr_t skb_physaddr; /* phys addr from pci_map_single */ | ||
93 | int skb_length; /* saved skb length for pci_unmap_single */ | ||
94 | |||
95 | /* Receive */ | ||
96 | int rxBuffIndex; /* index into receive descriptor list */ | ||
97 | struct recv_desc_bufs *dlist; /* descriptor list address */ | ||
98 | struct recv_desc_bufs *dlist_phys; /* descriptor list physical address */ | ||
99 | }; | ||
100 | |||
101 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_emac.h b/include/asm-arm/arch-at91rm9200/at91rm9200_emac.h new file mode 100644 index 000000000000..fbc091e61e2f --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91rm9200_emac.h | |||
@@ -0,0 +1,138 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-at91rm9200/at91rm9200_emac.h | ||
3 | * | ||
4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
5 | * Copyright (C) SAN People | ||
6 | * | ||
7 | * Ethernet MAC registers. | ||
8 | * Based on AT91RM9200 datasheet revision E. | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License as published by | ||
12 | * the Free Software Foundation; either version 2 of the License, or | ||
13 | * (at your option) any later version. | ||
14 | */ | ||
15 | |||
16 | #ifndef AT91RM9200_EMAC_H | ||
17 | #define AT91RM9200_EMAC_H | ||
18 | |||
19 | #define AT91_EMAC_CTL 0x00 /* Control Register */ | ||
20 | #define AT91_EMAC_LB (1 << 0) /* Loopback */ | ||
21 | #define AT91_EMAC_LBL (1 << 1) /* Loopback Local */ | ||
22 | #define AT91_EMAC_RE (1 << 2) /* Receive Enable */ | ||
23 | #define AT91_EMAC_TE (1 << 3) /* Transmit Enable */ | ||
24 | #define AT91_EMAC_MPE (1 << 4) /* Management Port Enable */ | ||
25 | #define AT91_EMAC_CSR (1 << 5) /* Clear Statistics Registers */ | ||
26 | #define AT91_EMAC_INCSTAT (1 << 6) /* Increment Statistics Registers */ | ||
27 | #define AT91_EMAC_WES (1 << 7) /* Write Enable for Statistics Registers */ | ||
28 | #define AT91_EMAC_BP (1 << 8) /* Back Pressure */ | ||
29 | |||
30 | #define AT91_EMAC_CFG 0x04 /* Configuration Register */ | ||
31 | #define AT91_EMAC_SPD (1 << 0) /* Speed */ | ||
32 | #define AT91_EMAC_FD (1 << 1) /* Full Duplex */ | ||
33 | #define AT91_EMAC_BR (1 << 2) /* Bit Rate */ | ||
34 | #define AT91_EMAC_CAF (1 << 4) /* Copy All Frames */ | ||
35 | #define AT91_EMAC_NBC (1 << 5) /* No Broadcast */ | ||
36 | #define AT91_EMAC_MTI (1 << 6) /* Multicast Hash Enable */ | ||
37 | #define AT91_EMAC_UNI (1 << 7) /* Unicast Hash Enable */ | ||
38 | #define AT91_EMAC_BIG (1 << 8) /* Receive 1522 Bytes */ | ||
39 | #define AT91_EMAC_EAE (1 << 9) /* External Address Match Enable */ | ||
40 | #define AT91_EMAC_CLK (3 << 10) /* MDC Clock Divisor */ | ||
41 | #define AT91_EMAC_CLK_DIV8 (0 << 10) | ||
42 | #define AT91_EMAC_CLK_DIV16 (1 << 10) | ||
43 | #define AT91_EMAC_CLK_DIV32 (2 << 10) | ||
44 | #define AT91_EMAC_CLK_DIV64 (3 << 10) | ||
45 | #define AT91_EMAC_RTY (1 << 12) /* Retry Test */ | ||
46 | #define AT91_EMAC_RMII (1 << 13) /* Reduce MII (RMII) */ | ||
47 | |||
48 | #define AT91_EMAC_SR 0x08 /* Status Register */ | ||
49 | #define AT91_EMAC_SR_LINK (1 << 0) /* Link */ | ||
50 | #define AT91_EMAC_SR_MDIO (1 << 1) /* MDIO pin */ | ||
51 | #define AT91_EMAC_SR_IDLE (1 << 2) /* PHY idle */ | ||
52 | |||
53 | #define AT91_EMAC_TAR 0x0c /* Transmit Address Register */ | ||
54 | |||
55 | #define AT91_EMAC_TCR 0x10 /* Transmit Control Register */ | ||
56 | #define AT91_EMAC_LEN (0x7ff << 0) /* Transmit Frame Length */ | ||
57 | #define AT91_EMAC_NCRC (1 << 15) /* No CRC */ | ||
58 | |||
59 | #define AT91_EMAC_TSR 0x14 /* Transmit Status Register */ | ||
60 | #define AT91_EMAC_TSR_OVR (1 << 0) /* Transmit Buffer Overrun */ | ||
61 | #define AT91_EMAC_TSR_COL (1 << 1) /* Collision Occurred */ | ||
62 | #define AT91_EMAC_TSR_RLE (1 << 2) /* Retry Limit Exceeded */ | ||
63 | #define AT91_EMAC_TSR_IDLE (1 << 3) /* Transmitter Idle */ | ||
64 | #define AT91_EMAC_TSR_BNQ (1 << 4) /* Transmit Buffer not Queued */ | ||
65 | #define AT91_EMAC_TSR_COMP (1 << 5) /* Transmit Complete */ | ||
66 | #define AT91_EMAC_TSR_UND (1 << 6) /* Transmit Underrun */ | ||
67 | |||
68 | #define AT91_EMAC_RBQP 0x18 /* Receive Buffer Queue Pointer */ | ||
69 | |||
70 | #define AT91_EMAC_RSR 0x20 /* Receive Status Register */ | ||
71 | #define AT91_EMAC_RSR_BNA (1 << 0) /* Buffer Not Available */ | ||
72 | #define AT91_EMAC_RSR_REC (1 << 1) /* Frame Received */ | ||
73 | #define AT91_EMAC_RSR_OVR (1 << 2) /* RX Overrun */ | ||
74 | |||
75 | #define AT91_EMAC_ISR 0x24 /* Interrupt Status Register */ | ||
76 | #define AT91_EMAC_DONE (1 << 0) /* Management Done */ | ||
77 | #define AT91_EMAC_RCOM (1 << 1) /* Receive Complete */ | ||
78 | #define AT91_EMAC_RBNA (1 << 2) /* Receive Buffer Not Available */ | ||
79 | #define AT91_EMAC_TOVR (1 << 3) /* Transmit Buffer Overrun */ | ||
80 | #define AT91_EMAC_TUND (1 << 4) /* Transmit Buffer Underrun */ | ||
81 | #define AT91_EMAC_RTRY (1 << 5) /* Retry Limit */ | ||
82 | #define AT91_EMAC_TBRE (1 << 6) /* Transmit Buffer Register Empty */ | ||
83 | #define AT91_EMAC_TCOM (1 << 7) /* Transmit Complete */ | ||
84 | #define AT91_EMAC_TIDLE (1 << 8) /* Transmit Idle */ | ||
85 | #define AT91_EMAC_LINK (1 << 9) /* Link */ | ||
86 | #define AT91_EMAC_ROVR (1 << 10) /* RX Overrun */ | ||
87 | #define AT91_EMAC_ABT (1 << 11) /* Abort */ | ||
88 | |||
89 | #define AT91_EMAC_IER 0x28 /* Interrupt Enable Register */ | ||
90 | #define AT91_EMAC_IDR 0x2c /* Interrupt Disable Register */ | ||
91 | #define AT91_EMAC_IMR 0x30 /* Interrupt Mask Register */ | ||
92 | |||
93 | #define AT91_EMAC_MAN 0x34 /* PHY Maintenance Register */ | ||
94 | #define AT91_EMAC_DATA (0xffff << 0) /* MDIO Data */ | ||
95 | #define AT91_EMAC_REGA (0x1f << 18) /* MDIO Register */ | ||
96 | #define AT91_EMAC_PHYA (0x1f << 23) /* MDIO PHY Address */ | ||
97 | #define AT91_EMAC_RW (3 << 28) /* Read/Write operation */ | ||
98 | #define AT91_EMAC_RW_W (1 << 28) | ||
99 | #define AT91_EMAC_RW_R (2 << 28) | ||
100 | #define AT91_EMAC_MAN_802_3 0x40020000 /* IEEE 802.3 value */ | ||
101 | |||
102 | /* | ||
103 | * Statistics Registers. | ||
104 | */ | ||
105 | #define AT91_EMAC_FRA 0x40 /* Frames Transmitted OK */ | ||
106 | #define AT91_EMAC_SCOL 0x44 /* Single Collision Frame */ | ||
107 | #define AT91_EMAC_MCOL 0x48 /* Multiple Collision Frame */ | ||
108 | #define AT91_EMAC_OK 0x4c /* Frames Received OK */ | ||
109 | #define AT91_EMAC_SEQE 0x50 /* Frame Check Sequence Error */ | ||
110 | #define AT91_EMAC_ALE 0x54 /* Alignmemt Error */ | ||
111 | #define AT91_EMAC_DTE 0x58 /* Deffered Transmission Frame */ | ||
112 | #define AT91_EMAC_LCOL 0x5c /* Late Collision */ | ||
113 | #define AT91_EMAC_ECOL 0x60 /* Excessive Collision */ | ||
114 | #define AT91_EMAC_TUE 0x64 /* Transmit Underrun Error */ | ||
115 | #define AT91_EMAC_CSE 0x68 /* Carrier Sense Error */ | ||
116 | #define AT91_EMAC_DRFC 0x6c /* Discard RX Frame */ | ||
117 | #define AT91_EMAC_ROV 0x70 /* Receive Overrun */ | ||
118 | #define AT91_EMAC_CDE 0x74 /* Code Error */ | ||
119 | #define AT91_EMAC_ELR 0x78 /* Excessive Length Error */ | ||
120 | #define AT91_EMAC_RJB 0x7c /* Receive Jabber */ | ||
121 | #define AT91_EMAC_USF 0x80 /* Undersize Frame */ | ||
122 | #define AT91_EMAC_SQEE 0x84 /* SQE Test Error */ | ||
123 | |||
124 | /* | ||
125 | * Address Registers. | ||
126 | */ | ||
127 | #define AT91_EMAC_HSL 0x90 /* Hash Address Low [31:0] */ | ||
128 | #define AT91_EMAC_HSH 0x94 /* Hash Address High [63:32] */ | ||
129 | #define AT91_EMAC_SA1L 0x98 /* Specific Address 1 Low, bytes 0-3 */ | ||
130 | #define AT91_EMAC_SA1H 0x9c /* Specific Address 1 High, bytes 4-5 */ | ||
131 | #define AT91_EMAC_SA2L 0xa0 /* Specific Address 2 Low, bytes 0-3 */ | ||
132 | #define AT91_EMAC_SA2H 0xa4 /* Specific Address 2 High, bytes 4-5 */ | ||
133 | #define AT91_EMAC_SA3L 0xa8 /* Specific Address 3 Low, bytes 0-3 */ | ||
134 | #define AT91_EMAC_SA3H 0xac /* Specific Address 3 High, bytes 4-5 */ | ||
135 | #define AT91_EMAC_SA4L 0xb0 /* Specific Address 4 Low, bytes 0-3 */ | ||
136 | #define AT91_EMAC_SA4H 0xb4 /* Specific Address 4 High, bytes 4-5 */ | ||
137 | |||
138 | #endif | ||