diff options
author | Sascha Hauer <s.hauer@pengutronix.de> | 2009-06-23 06:04:36 -0400 |
---|---|---|
committer | Sascha Hauer <s.hauer@pengutronix.de> | 2009-08-07 06:10:55 -0400 |
commit | bf50bcc242db7f8d2fb6bc099c1693149d9fb5d5 (patch) | |
tree | 173f484a81f7b0b951ead7f69475e6e1599437ac | |
parent | aa68c02777702f05ea5f075e3001288c30ffcb1c (diff) |
mx2: Codingstyle: Let the compiler count arrays
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
-rw-r--r-- | arch/arm/mach-mx2/devices.c | 165 |
1 files changed, 73 insertions, 92 deletions
diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-mx2/devices.c index e6f0f4f15584..cbf42467466d 100644 --- a/arch/arm/mach-mx2/devices.c +++ b/arch/arm/mach-mx2/devices.c | |||
@@ -41,20 +41,18 @@ | |||
41 | 41 | ||
42 | /* | 42 | /* |
43 | * General Purpose Timer | 43 | * General Purpose Timer |
44 | * - i.MX1: 2 timer (slighly different register handling) | 44 | * - i.MX21: 3 timers |
45 | * - i.MX21: 3 timer | 45 | * - i.MX27: 6 timers |
46 | * - i.MX27: 6 timer | ||
47 | */ | 46 | */ |
48 | 47 | ||
49 | /* We use gpt0 as system timer, so do not add a device for this one */ | 48 | /* We use gpt0 as system timer, so do not add a device for this one */ |
50 | 49 | ||
51 | static struct resource timer1_resources[] = { | 50 | static struct resource timer1_resources[] = { |
52 | [0] = { | 51 | { |
53 | .start = GPT2_BASE_ADDR, | 52 | .start = GPT2_BASE_ADDR, |
54 | .end = GPT2_BASE_ADDR + 0x17, | 53 | .end = GPT2_BASE_ADDR + 0x17, |
55 | .flags = IORESOURCE_MEM | 54 | .flags = IORESOURCE_MEM, |
56 | }, | 55 | }, { |
57 | [1] = { | ||
58 | .start = MXC_INT_GPT2, | 56 | .start = MXC_INT_GPT2, |
59 | .end = MXC_INT_GPT2, | 57 | .end = MXC_INT_GPT2, |
60 | .flags = IORESOURCE_IRQ, | 58 | .flags = IORESOURCE_IRQ, |
@@ -65,16 +63,15 @@ struct platform_device mxc_gpt1 = { | |||
65 | .name = "imx_gpt", | 63 | .name = "imx_gpt", |
66 | .id = 1, | 64 | .id = 1, |
67 | .num_resources = ARRAY_SIZE(timer1_resources), | 65 | .num_resources = ARRAY_SIZE(timer1_resources), |
68 | .resource = timer1_resources | 66 | .resource = timer1_resources, |
69 | }; | 67 | }; |
70 | 68 | ||
71 | static struct resource timer2_resources[] = { | 69 | static struct resource timer2_resources[] = { |
72 | [0] = { | 70 | { |
73 | .start = GPT3_BASE_ADDR, | 71 | .start = GPT3_BASE_ADDR, |
74 | .end = GPT3_BASE_ADDR + 0x17, | 72 | .end = GPT3_BASE_ADDR + 0x17, |
75 | .flags = IORESOURCE_MEM | 73 | .flags = IORESOURCE_MEM, |
76 | }, | 74 | }, { |
77 | [1] = { | ||
78 | .start = MXC_INT_GPT3, | 75 | .start = MXC_INT_GPT3, |
79 | .end = MXC_INT_GPT3, | 76 | .end = MXC_INT_GPT3, |
80 | .flags = IORESOURCE_IRQ, | 77 | .flags = IORESOURCE_IRQ, |
@@ -85,17 +82,16 @@ struct platform_device mxc_gpt2 = { | |||
85 | .name = "imx_gpt", | 82 | .name = "imx_gpt", |
86 | .id = 2, | 83 | .id = 2, |
87 | .num_resources = ARRAY_SIZE(timer2_resources), | 84 | .num_resources = ARRAY_SIZE(timer2_resources), |
88 | .resource = timer2_resources | 85 | .resource = timer2_resources, |
89 | }; | 86 | }; |
90 | 87 | ||
91 | #ifdef CONFIG_MACH_MX27 | 88 | #ifdef CONFIG_MACH_MX27 |
92 | static struct resource timer3_resources[] = { | 89 | static struct resource timer3_resources[] = { |
93 | [0] = { | 90 | { |
94 | .start = GPT4_BASE_ADDR, | 91 | .start = GPT4_BASE_ADDR, |
95 | .end = GPT4_BASE_ADDR + 0x17, | 92 | .end = GPT4_BASE_ADDR + 0x17, |
96 | .flags = IORESOURCE_MEM | 93 | .flags = IORESOURCE_MEM, |
97 | }, | 94 | }, { |
98 | [1] = { | ||
99 | .start = MXC_INT_GPT4, | 95 | .start = MXC_INT_GPT4, |
100 | .end = MXC_INT_GPT4, | 96 | .end = MXC_INT_GPT4, |
101 | .flags = IORESOURCE_IRQ, | 97 | .flags = IORESOURCE_IRQ, |
@@ -106,16 +102,15 @@ struct platform_device mxc_gpt3 = { | |||
106 | .name = "imx_gpt", | 102 | .name = "imx_gpt", |
107 | .id = 3, | 103 | .id = 3, |
108 | .num_resources = ARRAY_SIZE(timer3_resources), | 104 | .num_resources = ARRAY_SIZE(timer3_resources), |
109 | .resource = timer3_resources | 105 | .resource = timer3_resources, |
110 | }; | 106 | }; |
111 | 107 | ||
112 | static struct resource timer4_resources[] = { | 108 | static struct resource timer4_resources[] = { |
113 | [0] = { | 109 | { |
114 | .start = GPT5_BASE_ADDR, | 110 | .start = GPT5_BASE_ADDR, |
115 | .end = GPT5_BASE_ADDR + 0x17, | 111 | .end = GPT5_BASE_ADDR + 0x17, |
116 | .flags = IORESOURCE_MEM | 112 | .flags = IORESOURCE_MEM, |
117 | }, | 113 | }, { |
118 | [1] = { | ||
119 | .start = MXC_INT_GPT5, | 114 | .start = MXC_INT_GPT5, |
120 | .end = MXC_INT_GPT5, | 115 | .end = MXC_INT_GPT5, |
121 | .flags = IORESOURCE_IRQ, | 116 | .flags = IORESOURCE_IRQ, |
@@ -126,16 +121,15 @@ struct platform_device mxc_gpt4 = { | |||
126 | .name = "imx_gpt", | 121 | .name = "imx_gpt", |
127 | .id = 4, | 122 | .id = 4, |
128 | .num_resources = ARRAY_SIZE(timer4_resources), | 123 | .num_resources = ARRAY_SIZE(timer4_resources), |
129 | .resource = timer4_resources | 124 | .resource = timer4_resources, |
130 | }; | 125 | }; |
131 | 126 | ||
132 | static struct resource timer5_resources[] = { | 127 | static struct resource timer5_resources[] = { |
133 | [0] = { | 128 | { |
134 | .start = GPT6_BASE_ADDR, | 129 | .start = GPT6_BASE_ADDR, |
135 | .end = GPT6_BASE_ADDR + 0x17, | 130 | .end = GPT6_BASE_ADDR + 0x17, |
136 | .flags = IORESOURCE_MEM | 131 | .flags = IORESOURCE_MEM, |
137 | }, | 132 | }, { |
138 | [1] = { | ||
139 | .start = MXC_INT_GPT6, | 133 | .start = MXC_INT_GPT6, |
140 | .end = MXC_INT_GPT6, | 134 | .end = MXC_INT_GPT6, |
141 | .flags = IORESOURCE_IRQ, | 135 | .flags = IORESOURCE_IRQ, |
@@ -146,7 +140,7 @@ struct platform_device mxc_gpt5 = { | |||
146 | .name = "imx_gpt", | 140 | .name = "imx_gpt", |
147 | .id = 5, | 141 | .id = 5, |
148 | .num_resources = ARRAY_SIZE(timer5_resources), | 142 | .num_resources = ARRAY_SIZE(timer5_resources), |
149 | .resource = timer5_resources | 143 | .resource = timer5_resources, |
150 | }; | 144 | }; |
151 | #endif | 145 | #endif |
152 | 146 | ||
@@ -190,11 +184,11 @@ static struct resource mxc_nand_resources[] = { | |||
190 | { | 184 | { |
191 | .start = NFC_BASE_ADDR, | 185 | .start = NFC_BASE_ADDR, |
192 | .end = NFC_BASE_ADDR + 0xfff, | 186 | .end = NFC_BASE_ADDR + 0xfff, |
193 | .flags = IORESOURCE_MEM | 187 | .flags = IORESOURCE_MEM, |
194 | }, { | 188 | }, { |
195 | .start = MXC_INT_NANDFC, | 189 | .start = MXC_INT_NANDFC, |
196 | .end = MXC_INT_NANDFC, | 190 | .end = MXC_INT_NANDFC, |
197 | .flags = IORESOURCE_IRQ | 191 | .flags = IORESOURCE_IRQ, |
198 | }, | 192 | }, |
199 | }; | 193 | }; |
200 | 194 | ||
@@ -216,8 +210,7 @@ static struct resource mxc_fb[] = { | |||
216 | .start = LCDC_BASE_ADDR, | 210 | .start = LCDC_BASE_ADDR, |
217 | .end = LCDC_BASE_ADDR + 0xFFF, | 211 | .end = LCDC_BASE_ADDR + 0xFFF, |
218 | .flags = IORESOURCE_MEM, | 212 | .flags = IORESOURCE_MEM, |
219 | }, | 213 | }, { |
220 | { | ||
221 | .start = MXC_INT_LCDC, | 214 | .start = MXC_INT_LCDC, |
222 | .end = MXC_INT_LCDC, | 215 | .end = MXC_INT_LCDC, |
223 | .flags = IORESOURCE_IRQ, | 216 | .flags = IORESOURCE_IRQ, |
@@ -240,11 +233,11 @@ static struct resource mxc_fec_resources[] = { | |||
240 | { | 233 | { |
241 | .start = FEC_BASE_ADDR, | 234 | .start = FEC_BASE_ADDR, |
242 | .end = FEC_BASE_ADDR + 0xfff, | 235 | .end = FEC_BASE_ADDR + 0xfff, |
243 | .flags = IORESOURCE_MEM | 236 | .flags = IORESOURCE_MEM, |
244 | }, { | 237 | }, { |
245 | .start = MXC_INT_FEC, | 238 | .start = MXC_INT_FEC, |
246 | .end = MXC_INT_FEC, | 239 | .end = MXC_INT_FEC, |
247 | .flags = IORESOURCE_IRQ | 240 | .flags = IORESOURCE_IRQ, |
248 | }, | 241 | }, |
249 | }; | 242 | }; |
250 | 243 | ||
@@ -257,15 +250,14 @@ struct platform_device mxc_fec_device = { | |||
257 | #endif | 250 | #endif |
258 | 251 | ||
259 | static struct resource mxc_i2c_1_resources[] = { | 252 | static struct resource mxc_i2c_1_resources[] = { |
260 | [0] = { | 253 | { |
261 | .start = I2C_BASE_ADDR, | 254 | .start = I2C_BASE_ADDR, |
262 | .end = I2C_BASE_ADDR + 0x0fff, | 255 | .end = I2C_BASE_ADDR + 0x0fff, |
263 | .flags = IORESOURCE_MEM | 256 | .flags = IORESOURCE_MEM, |
264 | }, | 257 | }, { |
265 | [1] = { | ||
266 | .start = MXC_INT_I2C, | 258 | .start = MXC_INT_I2C, |
267 | .end = MXC_INT_I2C, | 259 | .end = MXC_INT_I2C, |
268 | .flags = IORESOURCE_IRQ | 260 | .flags = IORESOURCE_IRQ, |
269 | } | 261 | } |
270 | }; | 262 | }; |
271 | 263 | ||
@@ -273,20 +265,19 @@ struct platform_device mxc_i2c_device0 = { | |||
273 | .name = "imx-i2c", | 265 | .name = "imx-i2c", |
274 | .id = 0, | 266 | .id = 0, |
275 | .num_resources = ARRAY_SIZE(mxc_i2c_1_resources), | 267 | .num_resources = ARRAY_SIZE(mxc_i2c_1_resources), |
276 | .resource = mxc_i2c_1_resources | 268 | .resource = mxc_i2c_1_resources, |
277 | }; | 269 | }; |
278 | 270 | ||
279 | #ifdef CONFIG_MACH_MX27 | 271 | #ifdef CONFIG_MACH_MX27 |
280 | static struct resource mxc_i2c_2_resources[] = { | 272 | static struct resource mxc_i2c_2_resources[] = { |
281 | [0] = { | 273 | { |
282 | .start = I2C2_BASE_ADDR, | 274 | .start = I2C2_BASE_ADDR, |
283 | .end = I2C2_BASE_ADDR + 0x0fff, | 275 | .end = I2C2_BASE_ADDR + 0x0fff, |
284 | .flags = IORESOURCE_MEM | 276 | .flags = IORESOURCE_MEM, |
285 | }, | 277 | }, { |
286 | [1] = { | ||
287 | .start = MXC_INT_I2C2, | 278 | .start = MXC_INT_I2C2, |
288 | .end = MXC_INT_I2C2, | 279 | .end = MXC_INT_I2C2, |
289 | .flags = IORESOURCE_IRQ | 280 | .flags = IORESOURCE_IRQ, |
290 | } | 281 | } |
291 | }; | 282 | }; |
292 | 283 | ||
@@ -294,17 +285,16 @@ struct platform_device mxc_i2c_device1 = { | |||
294 | .name = "imx-i2c", | 285 | .name = "imx-i2c", |
295 | .id = 1, | 286 | .id = 1, |
296 | .num_resources = ARRAY_SIZE(mxc_i2c_2_resources), | 287 | .num_resources = ARRAY_SIZE(mxc_i2c_2_resources), |
297 | .resource = mxc_i2c_2_resources | 288 | .resource = mxc_i2c_2_resources, |
298 | }; | 289 | }; |
299 | #endif | 290 | #endif |
300 | 291 | ||
301 | static struct resource mxc_pwm_resources[] = { | 292 | static struct resource mxc_pwm_resources[] = { |
302 | [0] = { | 293 | { |
303 | .start = PWM_BASE_ADDR, | 294 | .start = PWM_BASE_ADDR, |
304 | .end = PWM_BASE_ADDR + 0x0fff, | 295 | .end = PWM_BASE_ADDR + 0x0fff, |
305 | .flags = IORESOURCE_MEM | 296 | .flags = IORESOURCE_MEM, |
306 | }, | 297 | }, { |
307 | [1] = { | ||
308 | .start = MXC_INT_PWM, | 298 | .start = MXC_INT_PWM, |
309 | .end = MXC_INT_PWM, | 299 | .end = MXC_INT_PWM, |
310 | .flags = IORESOURCE_IRQ, | 300 | .flags = IORESOURCE_IRQ, |
@@ -315,28 +305,26 @@ struct platform_device mxc_pwm_device = { | |||
315 | .name = "mxc_pwm", | 305 | .name = "mxc_pwm", |
316 | .id = 0, | 306 | .id = 0, |
317 | .num_resources = ARRAY_SIZE(mxc_pwm_resources), | 307 | .num_resources = ARRAY_SIZE(mxc_pwm_resources), |
318 | .resource = mxc_pwm_resources | 308 | .resource = mxc_pwm_resources, |
319 | }; | 309 | }; |
320 | 310 | ||
321 | /* | 311 | /* |
322 | * Resource definition for the MXC SDHC | 312 | * Resource definition for the MXC SDHC |
323 | */ | 313 | */ |
324 | static struct resource mxc_sdhc1_resources[] = { | 314 | static struct resource mxc_sdhc1_resources[] = { |
325 | [0] = { | 315 | { |
326 | .start = SDHC1_BASE_ADDR, | 316 | .start = SDHC1_BASE_ADDR, |
327 | .end = SDHC1_BASE_ADDR + SZ_4K - 1, | 317 | .end = SDHC1_BASE_ADDR + SZ_4K - 1, |
328 | .flags = IORESOURCE_MEM, | 318 | .flags = IORESOURCE_MEM, |
329 | }, | 319 | }, { |
330 | [1] = { | 320 | .start = MXC_INT_SDHC1, |
331 | .start = MXC_INT_SDHC1, | 321 | .end = MXC_INT_SDHC1, |
332 | .end = MXC_INT_SDHC1, | 322 | .flags = IORESOURCE_IRQ, |
333 | .flags = IORESOURCE_IRQ, | 323 | }, { |
334 | }, | 324 | .start = DMA_REQ_SDHC1, |
335 | [2] = { | 325 | .end = DMA_REQ_SDHC1, |
336 | .start = DMA_REQ_SDHC1, | 326 | .flags = IORESOURCE_DMA, |
337 | .end = DMA_REQ_SDHC1, | 327 | }, |
338 | .flags = IORESOURCE_DMA | ||
339 | }, | ||
340 | }; | 328 | }; |
341 | 329 | ||
342 | static u64 mxc_sdhc1_dmamask = 0xffffffffUL; | 330 | static u64 mxc_sdhc1_dmamask = 0xffffffffUL; |
@@ -353,21 +341,19 @@ struct platform_device mxc_sdhc_device0 = { | |||
353 | }; | 341 | }; |
354 | 342 | ||
355 | static struct resource mxc_sdhc2_resources[] = { | 343 | static struct resource mxc_sdhc2_resources[] = { |
356 | [0] = { | 344 | { |
357 | .start = SDHC2_BASE_ADDR, | 345 | .start = SDHC2_BASE_ADDR, |
358 | .end = SDHC2_BASE_ADDR + SZ_4K - 1, | 346 | .end = SDHC2_BASE_ADDR + SZ_4K - 1, |
359 | .flags = IORESOURCE_MEM, | 347 | .flags = IORESOURCE_MEM, |
360 | }, | 348 | }, { |
361 | [1] = { | 349 | .start = MXC_INT_SDHC2, |
362 | .start = MXC_INT_SDHC2, | 350 | .end = MXC_INT_SDHC2, |
363 | .end = MXC_INT_SDHC2, | 351 | .flags = IORESOURCE_IRQ, |
364 | .flags = IORESOURCE_IRQ, | 352 | }, { |
365 | }, | 353 | .start = DMA_REQ_SDHC2, |
366 | [2] = { | 354 | .end = DMA_REQ_SDHC2, |
367 | .start = DMA_REQ_SDHC2, | 355 | .flags = IORESOURCE_DMA, |
368 | .end = DMA_REQ_SDHC2, | 356 | }, |
369 | .flags = IORESOURCE_DMA | ||
370 | }, | ||
371 | }; | 357 | }; |
372 | 358 | ||
373 | static u64 mxc_sdhc2_dmamask = 0xffffffffUL; | 359 | static u64 mxc_sdhc2_dmamask = 0xffffffffUL; |
@@ -385,33 +371,28 @@ struct platform_device mxc_sdhc_device1 = { | |||
385 | 371 | ||
386 | /* GPIO port description */ | 372 | /* GPIO port description */ |
387 | static struct mxc_gpio_port imx_gpio_ports[] = { | 373 | static struct mxc_gpio_port imx_gpio_ports[] = { |
388 | [0] = { | 374 | { |
389 | .chip.label = "gpio-0", | 375 | .chip.label = "gpio-0", |
390 | .irq = MXC_INT_GPIO, | 376 | .irq = MXC_INT_GPIO, |
391 | .base = IO_ADDRESS(GPIO_BASE_ADDR), | 377 | .base = IO_ADDRESS(GPIO_BASE_ADDR), |
392 | .virtual_irq_start = MXC_GPIO_IRQ_START, | 378 | .virtual_irq_start = MXC_GPIO_IRQ_START, |
393 | }, | 379 | }, { |
394 | [1] = { | ||
395 | .chip.label = "gpio-1", | 380 | .chip.label = "gpio-1", |
396 | .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100), | 381 | .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100), |
397 | .virtual_irq_start = MXC_GPIO_IRQ_START + 32, | 382 | .virtual_irq_start = MXC_GPIO_IRQ_START + 32, |
398 | }, | 383 | }, { |
399 | [2] = { | ||
400 | .chip.label = "gpio-2", | 384 | .chip.label = "gpio-2", |
401 | .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200), | 385 | .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200), |
402 | .virtual_irq_start = MXC_GPIO_IRQ_START + 64, | 386 | .virtual_irq_start = MXC_GPIO_IRQ_START + 64, |
403 | }, | 387 | }, { |
404 | [3] = { | ||
405 | .chip.label = "gpio-3", | 388 | .chip.label = "gpio-3", |
406 | .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300), | 389 | .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300), |
407 | .virtual_irq_start = MXC_GPIO_IRQ_START + 96, | 390 | .virtual_irq_start = MXC_GPIO_IRQ_START + 96, |
408 | }, | 391 | }, { |
409 | [4] = { | ||
410 | .chip.label = "gpio-4", | 392 | .chip.label = "gpio-4", |
411 | .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400), | 393 | .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400), |
412 | .virtual_irq_start = MXC_GPIO_IRQ_START + 128, | 394 | .virtual_irq_start = MXC_GPIO_IRQ_START + 128, |
413 | }, | 395 | }, { |
414 | [5] = { | ||
415 | .chip.label = "gpio-5", | 396 | .chip.label = "gpio-5", |
416 | .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500), | 397 | .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500), |
417 | .virtual_irq_start = MXC_GPIO_IRQ_START + 160, | 398 | .virtual_irq_start = MXC_GPIO_IRQ_START + 160, |