diff options
| author | Meihui Fan <mhfan@hhcn.com> | 2008-04-22 20:50:53 -0400 |
|---|---|---|
| committer | Bryan Wu <cooloney@kernel.org> | 2008-04-22 20:50:53 -0400 |
| commit | a8a46a269e05190d18e4e36f51477d59bd0b29f6 (patch) | |
| tree | 1fdd3493a48ead53e8882075b6f615d6c398de76 | |
| parent | 37167e6411f15fc8d8da8acabfd7cdd17668ffad (diff) | |
[Blackfin] arch: fix obvious bfin_write typos
Signed-off-by: Meihui Fan <mhfan@hhcn.com>
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
| -rw-r--r-- | include/asm-blackfin/mach-bf548/cdefBF54x_base.h | 348 |
1 files changed, 174 insertions, 174 deletions
diff --git a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h index d8d2f1f127db..33c67500717c 100644 --- a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h +++ b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h | |||
| @@ -290,7 +290,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
| 290 | #define bfin_read_EBIU_DDRQUE() bfin_read32(EBIU_DDRQUE) | 290 | #define bfin_read_EBIU_DDRQUE() bfin_read32(EBIU_DDRQUE) |
| 291 | #define bfin_write_EBIU_DDRQUE(val) bfin_write32(EBIU_DDRQUE, val) | 291 | #define bfin_write_EBIU_DDRQUE(val) bfin_write32(EBIU_DDRQUE, val) |
| 292 | #define bfin_read_EBIU_ERRADD() bfin_read32(EBIU_ERRADD) | 292 | #define bfin_read_EBIU_ERRADD() bfin_read32(EBIU_ERRADD) |
| 293 | #define bfin_write_EBIU_ERRADD(val) bfin_write32(EBIU_ERRADD) | 293 | #define bfin_write_EBIU_ERRADD(val) bfin_write32(EBIU_ERRADD, val) |
| 294 | #define bfin_read_EBIU_ERRMST() bfin_read16(EBIU_ERRMST) | 294 | #define bfin_read_EBIU_ERRMST() bfin_read16(EBIU_ERRMST) |
| 295 | #define bfin_write_EBIU_ERRMST(val) bfin_write16(EBIU_ERRMST, val) | 295 | #define bfin_write_EBIU_ERRMST(val) bfin_write16(EBIU_ERRMST, val) |
| 296 | #define bfin_read_EBIU_RSTCTL() bfin_read16(EBIU_RSTCTL) | 296 | #define bfin_read_EBIU_RSTCTL() bfin_read16(EBIU_RSTCTL) |
| @@ -359,23 +359,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
| 359 | /* DMA Channel 0 Registers */ | 359 | /* DMA Channel 0 Registers */ |
| 360 | 360 | ||
| 361 | #define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR) | 361 | #define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR) |
| 362 | #define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR) | 362 | #define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val) |
| 363 | #define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR) | 363 | #define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR) |
| 364 | #define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR) | 364 | #define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val) |
| 365 | #define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) | 365 | #define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) |
| 366 | #define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) | 366 | #define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) |
| 367 | #define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) | 367 | #define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) |
| 368 | #define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) | 368 | #define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) |
| 369 | #define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) | 369 | #define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) |
| 370 | #define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY) | 370 | #define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val) |
| 371 | #define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) | 371 | #define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) |
| 372 | #define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) | 372 | #define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) |
| 373 | #define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) | 373 | #define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) |
| 374 | #define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY) | 374 | #define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val) |
| 375 | #define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR) | 375 | #define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR) |
| 376 | #define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR) | 376 | #define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val) |
| 377 | #define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR) | 377 | #define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR) |
| 378 | #define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR) | 378 | #define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val) |
| 379 | #define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) | 379 | #define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) |
| 380 | #define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) | 380 | #define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) |
| 381 | #define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) | 381 | #define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) |
| @@ -388,23 +388,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
| 388 | /* DMA Channel 1 Registers */ | 388 | /* DMA Channel 1 Registers */ |
| 389 | 389 | ||
| 390 | #define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR) | 390 | #define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR) |
| 391 | #define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR) | 391 | #define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val) |
| 392 | #define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR) | 392 | #define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR) |
| 393 | #define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR) | 393 | #define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val) |
| 394 | #define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) | 394 | #define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) |
| 395 | #define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) | 395 | #define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) |
| 396 | #define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) | 396 | #define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) |
| 397 | #define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) | 397 | #define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) |
| 398 | #define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) | 398 | #define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) |
| 399 | #define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY) | 399 | #define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val) |
| 400 | #define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) | 400 | #define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) |
| 401 | #define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) | 401 | #define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) |
| 402 | #define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) | 402 | #define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) |
| 403 | #define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY) | 403 | #define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val) |
| 404 | #define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR) | 404 | #define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR) |
| 405 | #define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR) | 405 | #define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val) |
| 406 | #define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR) | 406 | #define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR) |
| 407 | #define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR) | 407 | #define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val) |
| 408 | #define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) | 408 | #define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) |
| 409 | #define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) | 409 | #define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) |
| 410 | #define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) | 410 | #define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) |
| @@ -417,23 +417,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
| 417 | /* DMA Channel 2 Registers */ | 417 | /* DMA Channel 2 Registers */ |
| 418 | 418 | ||
| 419 | #define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR) | 419 | #define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR) |
| 420 | #define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR) | 420 | #define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val) |
| 421 | #define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR) | 421 | #define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR) |
| 422 | #define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR) | 422 | #define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val) |
| 423 | #define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) | 423 | #define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) |
| 424 | #define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) | 424 | #define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) |
| 425 | #define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) | 425 | #define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) |
| 426 | #define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) | 426 | #define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) |
| 427 | #define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) | 427 | #define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) |
| 428 | #define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY) | 428 | #define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val) |
| 429 | #define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) | 429 | #define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) |
| 430 | #define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) | 430 | #define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) |
| 431 | #define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) | 431 | #define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) |
| 432 | #define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY) | 432 | #define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val) |
| 433 | #define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR) | 433 | #define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR) |
| 434 | #define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR) | 434 | #define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val) |
| 435 | #define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR) | 435 | #define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR) |
| 436 | #define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR) | 436 | #define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val) |
| 437 | #define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) | 437 | #define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) |
| 438 | #define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) | 438 | #define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) |
| 439 | #define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) | 439 | #define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) |
| @@ -446,23 +446,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
| 446 | /* DMA Channel 3 Registers */ | 446 | /* DMA Channel 3 Registers */ |
| 447 | 447 | ||
| 448 | #define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR) | 448 | #define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR) |
| 449 | #define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR) | 449 | #define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val) |
| 450 | #define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR) | 450 | #define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR) |
| 451 | #define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR) | 451 | #define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val) |
| 452 | #define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) | 452 | #define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) |
| 453 | #define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) | 453 | #define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) |
| 454 | #define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) | 454 | #define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) |
| 455 | #define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) | 455 | #define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) |
| 456 | #define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) | 456 | #define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) |
| 457 | #define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY) | 457 | #define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val) |
| 458 | #define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) | 458 | #define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) |
| 459 | #define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) | 459 | #define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) |
| 460 | #define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) | 460 | #define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) |
| 461 | #define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY) | 461 | #define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val) |
| 462 | #define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR) | 462 | #define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR) |
| 463 | #define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR) | 463 | #define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val) |
| 464 | #define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR) | 464 | #define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR) |
| 465 | #define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR) | 465 | #define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val) |
| 466 | #define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) | 466 | #define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) |
| 467 | #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) | 467 | #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) |
| 468 | #define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) | 468 | #define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) |
| @@ -475,23 +475,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
| 475 | /* DMA Channel 4 Registers */ | 475 | /* DMA Channel 4 Registers */ |
| 476 | 476 | ||
| 477 | #define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR) | 477 | #define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR) |
| 478 | #define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR) | 478 | #define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val) |
| 479 | #define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR) | 479 | #define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR) |
| 480 | #define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR) | 480 | #define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val) |
| 481 | #define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) | 481 | #define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) |
| 482 | #define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) | 482 | #define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) |
| 483 | #define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) | 483 | #define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) |
| 484 | #define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) | 484 | #define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) |
| 485 | #define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) | 485 | #define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) |
| 486 | #define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY) | 486 | #define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val) |
| 487 | #define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) | 487 | #define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) |
| 488 | #define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) | 488 | #define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) |
| 489 | #define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) | 489 | #define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) |
| 490 | #define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY) | 490 | #define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val) |
| 491 | #define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR) | 491 | #define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR) |
| 492 | #define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR) | 492 | #define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val) |
| 493 | #define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR) | 493 | #define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR) |
| 494 | #define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR) | 494 | #define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val) |
| 495 | #define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) | 495 | #define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) |
| 496 | #define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) | 496 | #define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) |
| 497 | #define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) | 497 | #define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) |
| @@ -504,23 +504,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
| 504 | /* DMA Channel 5 Registers */ | 504 | /* DMA Channel 5 Registers */ |
| 505 | 505 | ||
| 506 | #define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR) | 506 | #define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR) |
| 507 | #define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR) | 507 | #define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val) |
| 508 | #define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR) | 508 | #define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR) |
| 509 | #define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR) | 509 | #define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val) |
| 510 | #define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) | 510 | #define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) |
| 511 | #define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) | 511 | #define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) |
| 512 | #define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) | 512 | #define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) |
| 513 | #define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) | 513 | #define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) |
| 514 | #define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) | 514 | #define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) |
| 515 | #define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY) | 515 | #define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val) |
| 516 | #define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) | 516 | #define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) |
| 517 | #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) | 517 | #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) |
| 518 | #define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) | 518 | #define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) |
| 519 | #define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY) | 519 | #define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val) |
| 520 | #define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR) | 520 | #define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR) |
| 521 | #define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR) | 521 | #define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val) |
| 522 | #define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR) | 522 | #define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR) |
| 523 | #define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR) | 523 | #define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val) |
| 524 | #define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) | 524 | #define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) |
| 525 | #define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) | 525 | #define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) |
| 526 | #define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) | 526 | #define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) |
| @@ -533,23 +533,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
| 533 | /* DMA Channel 6 Registers */ | 533 | /* DMA Channel 6 Registers */ |
| 534 | 534 | ||
| 535 | #define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) | 535 | #define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) |
| 536 | #define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR) | 536 | #define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val) |
| 537 | #define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR) | 537 | #define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR) |
| 538 | #define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR) | 538 | #define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val) |
| 539 | #define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) | 539 | #define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) |
| 540 | #define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) | 540 | #define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) |
| 541 | #define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) | 541 | #define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) |
| 542 | #define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) | 542 | #define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) |
| 543 | #define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) | 543 | #define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) |
| 544 | #define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY) | 544 | #define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val) |
| 545 | #define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) | 545 | #define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) |
| 546 | #define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) | 546 | #define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) |
| 547 | #define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) | 547 | #define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) |
| 548 | #define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY) | 548 | #define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val) |
| 549 | #define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR) | 549 | #define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR) |
| 550 | #define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR) | 550 | #define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val) |
| 551 | #define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR) | 551 | #define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR) |
| 552 | #define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR) | 552 | #define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val) |
| 553 | #define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) | 553 | #define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) |
| 554 | #define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) | 554 | #define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) |
| 555 | #define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) | 555 | #define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) |
| @@ -562,23 +562,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
| 562 | /* DMA Channel 7 Registers */ | 562 | /* DMA Channel 7 Registers */ |
| 563 | 563 | ||
| 564 | #define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR) | 564 | #define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR) |
| 565 | #define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR) | 565 | #define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val) |
| 566 | #define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR) | 566 | #define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR) |
| 567 | #define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR) | 567 | #define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val) |
| 568 | #define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) | 568 | #define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) |
| 569 | #define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) | 569 | #define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) |
| 570 | #define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) | 570 | #define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) |
| 571 | #define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) | 571 | #define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) |
| 572 | #define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) | 572 | #define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) |
| 573 | #define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY) | 573 | #define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val) |
| 574 | #define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) | 574 | #define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) |
| 575 | #define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) | 575 | #define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) |
| 576 | #define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) | 576 | #define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) |
| 577 | #define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY) | 577 | #define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val) |
| 578 | #define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR) | 578 | #define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR) |
| 579 | #define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR) | 579 | #define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val) |
| 580 | #define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR) | 580 | #define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR) |
| 581 | #define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR) | 581 | #define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val) |
| 582 | #define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) | 582 | #define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) |
| 583 | #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) | 583 | #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) |
| 584 | #define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) | 584 | #define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) |
| @@ -591,23 +591,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
| 591 | /* DMA Channel 8 Registers */ | 591 | /* DMA Channel 8 Registers */ |
| 592 | 592 | ||
| 593 | #define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR) | 593 | #define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR) |
| 594 | #define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR) | 594 | #define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val) |
| 595 | #define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR) | 595 | #define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR) |
| 596 | #define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR) | 596 | #define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val) |
| 597 | #define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG) | 597 | #define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG) |
| 598 | #define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val) | 598 | #define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val) |
| 599 | #define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT) | 599 | #define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT) |
| 600 | #define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val) | 600 | #define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val) |
| 601 | #define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY) | 601 | #define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY) |
| 602 | #define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY) | 602 | #define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val) |
| 603 | #define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT) | 603 | #define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT) |
| 604 | #define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val) | 604 | #define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val) |
| 605 | #define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY) | 605 | #define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY) |
| 606 | #define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY) | 606 | #define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val) |
| 607 | #define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR) | 607 | #define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR) |
| 608 | #define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR) | 608 | #define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val) |
| 609 | #define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR) | 609 | #define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR) |
| 610 | #define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR) | 610 | #define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val) |
| 611 | #define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS) | 611 | #define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS) |
| 612 | #define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val) | 612 | #define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val) |
| 613 | #define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP) | 613 | #define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP) |
| @@ -620,23 +620,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
| 620 | /* DMA Channel 9 Registers */ | 620 | /* DMA Channel 9 Registers */ |
| 621 | 621 | ||
| 622 | #define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR) | 622 | #define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR) |
| 623 | #define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR) | 623 | #define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val) |
| 624 | #define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR) | 624 | #define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR) |
| 625 | #define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR) | 625 | #define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val) |
| 626 | #define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG) | 626 | #define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG) |
| 627 | #define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val) | 627 | #define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val) |
| 628 | #define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT) | 628 | #define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT) |
| 629 | #define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val) | 629 | #define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val) |
| 630 | #define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY) | 630 | #define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY) |
| 631 | #define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY) | 631 | #define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val) |
| 632 | #define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT) | 632 | #define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT) |
| 633 | #define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val) | 633 | #define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val) |
| 634 | #define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY) | 634 | #define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY) |
| 635 | #define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY) | 635 | #define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val) |
| 636 | #define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR) | 636 | #define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR) |
| 637 | #define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR) | 637 | #define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val) |
| 638 | #define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR) | 638 | #define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR) |
| 639 | #define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR) | 639 | #define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val) |
| 640 | #define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS) | 640 | #define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS) |
| 641 | #define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val) | 641 | #define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val) |
| 642 | #define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP) | 642 | #define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP) |
| @@ -649,23 +649,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
| 649 | /* DMA Channel 10 Registers */ | 649 | /* DMA Channel 10 Registers */ |
| 650 | 650 | ||
| 651 | #define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR) | 651 | #define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR) |
| 652 | #define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR) | 652 | #define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val) |
| 653 | #define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR) | 653 | #define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR) |
| 654 | #define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR) | 654 | #define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val) |
| 655 | #define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG) | 655 | #define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG) |
| 656 | #define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val) | 656 | #define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val) |
| 657 | #define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT) | 657 | #define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT) |
| 658 | #define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val) | 658 | #define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val) |
| 659 | #define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY) | 659 | #define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY) |
| 660 | #define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY) | 660 | #define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val) |
| 661 | #define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT) | 661 | #define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT) |
| 662 | #define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val) | 662 | #define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val) |
| 663 | #define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY) | 663 | #define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY) |
| 664 | #define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY) | 664 | #define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val) |
| 665 | #define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR) | 665 | #define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR) |
| 666 | #define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR) | 666 | #define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val) |
| 667 | #define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR) | 667 | #define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR) |
| 668 | #define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR) | 668 | #define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val) |
| 669 | #define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS) | 669 | #define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS) |
| 670 | #define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val) | 670 | #define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val) |
| 671 | #define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP) | 671 | #define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP) |
| @@ -678,23 +678,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
| 678 | /* DMA Channel 11 Registers */ | 678 | /* DMA Channel 11 Registers */ |
| 679 | 679 | ||
| 680 | #define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR) | 680 | #define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR) |
| 681 | #define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR) | 681 | #define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val) |
| 682 | #define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR) | 682 | #define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR) |
| 683 | #define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR) | 683 | #define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val) |
| 684 | #define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG) | 684 | #define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG) |
| 685 | #define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val) | 685 | #define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val) |
| 686 | #define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT) | 686 | #define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT) |
| 687 | #define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val) | 687 | #define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val) |
| 688 | #define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY) | 688 | #define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY) |
| 689 | #define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY) | 689 | #define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val) |
| 690 | #define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT) | 690 | #define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT) |
| 691 | #define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val) | 691 | #define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val) |
| 692 | #define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY) | 692 | #define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY) |
| 693 | #define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY) | 693 | #define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val) |
| 694 | #define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR) | 694 | #define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR) |
| 695 | #define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR) | 695 | #define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val) |
| 696 | #define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR) | 696 | #define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR) |
| 697 | #define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR) | 697 | #define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val) |
| 698 | #define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS) | 698 | #define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS) |
| 699 | #define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val) | 699 | #define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val) |
| 700 | #define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP) | 700 | #define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP) |
| @@ -707,7 +707,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
| 707 | /* MDMA Stream 0 Registers */ | 707 | /* MDMA Stream 0 Registers */ |
| 708 | 708 | ||
| 709 | #define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR) | 709 | #define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR) |
| 710 | #define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR) | 710 | #define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val) |
| 711 | #define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR) | 711 | #define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR) |
| 712 | #define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val) | 712 | #define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val) |
| 713 | #define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) | 713 | #define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) |
| @@ -770,11 +770,11 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
| 770 | #define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) | 770 | #define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) |
| 771 | #define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) | 771 | #define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) |
| 772 | #define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) | 772 | #define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) |
| 773 | #define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY) | 773 | #define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val) |
| 774 | #define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) | 774 | #define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) |
| 775 | #define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) | 775 | #define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) |
| 776 | #define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) | 776 | #define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) |
| 777 | #define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY) | 777 | #define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val) |
| 778 | #define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR) | 778 | #define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR) |
| 779 | #define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val) | 779 | #define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val) |
| 780 | #define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR) | 780 | #define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR) |
| @@ -796,11 +796,11 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
| 796 | #define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) | 796 | #define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) |
| 797 | #define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) | 797 | #define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) |
| 798 | #define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) | 798 | #define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) |
| 799 | #define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY) | 799 | #define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val) |
| 800 | #define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) | 800 | #define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) |
| 801 | #define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) | 801 | #define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) |
| 802 | #define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) | 802 | #define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) |
| 803 | #define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY) | 803 | #define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val) |
| 804 | #define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR) | 804 | #define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR) |
| 805 | #define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val) | 805 | #define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val) |
| 806 | #define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR) | 806 | #define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR) |
| @@ -1213,23 +1213,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
| 1213 | /* DMA Channel 12 Registers */ | 1213 | /* DMA Channel 12 Registers */ |
| 1214 | 1214 | ||
| 1215 | #define bfin_read_DMA12_NEXT_DESC_PTR() bfin_read32(DMA12_NEXT_DESC_PTR) | 1215 | #define bfin_read_DMA12_NEXT_DESC_PTR() bfin_read32(DMA12_NEXT_DESC_PTR) |
| 1216 | #define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_write32(DMA12_NEXT_DESC_PTR) | 1216 | #define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_write32(DMA12_NEXT_DESC_PTR, val) |
| 1217 | #define bfin_read_DMA12_START_ADDR() bfin_read32(DMA12_START_ADDR) | 1217 | #define bfin_read_DMA12_START_ADDR() bfin_read32(DMA12_START_ADDR) |
| 1218 | #define bfin_write_DMA12_START_ADDR(val) bfin_write32(DMA12_START_ADDR) | 1218 | #define bfin_write_DMA12_START_ADDR(val) bfin_write32(DMA12_START_ADDR, val) |
| 1219 | #define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG) | 1219 | #define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG) |
| 1220 | #define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val) | 1220 | #define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val) |
| 1221 | #define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT) | 1221 | #define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT) |
| 1222 | #define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val) | 1222 | #define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val) |
| 1223 | #define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY) | 1223 | #define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY) |
| 1224 | #define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY) | 1224 | #define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val) |
| 1225 | #define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT) | 1225 | #define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT) |
| 1226 | #define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val) | 1226 | #define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val) |
| 1227 | #define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY) | 1227 | #define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY) |
| 1228 | #define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY) | 1228 | #define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val) |
| 1229 | #define bfin_read_DMA12_CURR_DESC_PTR() bfin_read32(DMA12_CURR_DESC_PTR) | 1229 | #define bfin_read_DMA12_CURR_DESC_PTR() bfin_read32(DMA12_CURR_DESC_PTR) |
| 1230 | #define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_write32(DMA12_CURR_DESC_PTR) | 1230 | #define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_write32(DMA12_CURR_DESC_PTR, val) |
| 1231 | #define bfin_read_DMA12_CURR_ADDR() bfin_read32(DMA12_CURR_ADDR) | 1231 | #define bfin_read_DMA12_CURR_ADDR() bfin_read32(DMA12_CURR_ADDR) |
| 1232 | #define bfin_write_DMA12_CURR_ADDR(val) bfin_write32(DMA12_CURR_ADDR) | 1232 | #define bfin_write_DMA12_CURR_ADDR(val) bfin_write32(DMA12_CURR_ADDR, val) |
| 1233 | #define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS) | 1233 | #define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS) |
| 1234 | #define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val) | 1234 | #define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val) |
| 1235 | #define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP) | 1235 | #define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP) |
| @@ -1242,23 +1242,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
| 1242 | /* DMA Channel 13 Registers */ | 1242 | /* DMA Channel 13 Registers */ |
| 1243 | 1243 | ||
| 1244 | #define bfin_read_DMA13_NEXT_DESC_PTR() bfin_read32(DMA13_NEXT_DESC_PTR) | 1244 | #define bfin_read_DMA13_NEXT_DESC_PTR() bfin_read32(DMA13_NEXT_DESC_PTR) |
| 1245 | #define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_write32(DMA13_NEXT_DESC_PTR) | 1245 | #define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_write32(DMA13_NEXT_DESC_PTR, val) |
| 1246 | #define bfin_read_DMA13_START_ADDR() bfin_read32(DMA13_START_ADDR) | 1246 | #define bfin_read_DMA13_START_ADDR() bfin_read32(DMA13_START_ADDR) |
| 1247 | #define bfin_write_DMA13_START_ADDR(val) bfin_write32(DMA13_START_ADDR) | 1247 | #define bfin_write_DMA13_START_ADDR(val) bfin_write32(DMA13_START_ADDR, val) |
| 1248 | #define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG) | 1248 | #define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG) |
| 1249 | #define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val) | 1249 | #define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val) |
| 1250 | #define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT) | 1250 | #define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT) |
| 1251 | #define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val) | 1251 | #define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val) |
| 1252 | #define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY) | 1252 | #define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY) |
| 1253 | #define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY) | 1253 | #define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val) |
| 1254 | #define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT) | 1254 | #define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT) |
| 1255 | #define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val) | 1255 | #define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val) |
| 1256 | #define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY) | 1256 | #define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY) |
| 1257 | #define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY) | 1257 | #define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val) |
| 1258 | #define bfin_read_DMA13_CURR_DESC_PTR() bfin_read32(DMA13_CURR_DESC_PTR) | 1258 | #define bfin_read_DMA13_CURR_DESC_PTR() bfin_read32(DMA13_CURR_DESC_PTR) |
| 1259 | #define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_write32(DMA13_CURR_DESC_PTR) | 1259 | #define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_write32(DMA13_CURR_DESC_PTR, val) |
| 1260 | #define bfin_read_DMA13_CURR_ADDR() bfin_read32(DMA13_CURR_ADDR) | 1260 | #define bfin_read_DMA13_CURR_ADDR() bfin_read32(DMA13_CURR_ADDR) |
| 1261 | #define bfin_write_DMA13_CURR_ADDR(val) bfin_write32(DMA13_CURR_ADDR) | 1261 | #define bfin_write_DMA13_CURR_ADDR(val) bfin_write32(DMA13_CURR_ADDR, val) |
| 1262 | #define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS) | 1262 | #define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS) |
| 1263 | #define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val) | 1263 | #define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val) |
| 1264 | #define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP) | 1264 | #define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP) |
| @@ -1271,23 +1271,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
| 1271 | /* DMA Channel 14 Registers */ | 1271 | /* DMA Channel 14 Registers */ |
| 1272 | 1272 | ||
| 1273 | #define bfin_read_DMA14_NEXT_DESC_PTR() bfin_read32(DMA14_NEXT_DESC_PTR) | 1273 | #define bfin_read_DMA14_NEXT_DESC_PTR() bfin_read32(DMA14_NEXT_DESC_PTR) |
| 1274 | #define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_write32(DMA14_NEXT_DESC_PTR) | 1274 | #define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_write32(DMA14_NEXT_DESC_PTR, val) |
| 1275 | #define bfin_read_DMA14_START_ADDR() bfin_read32(DMA14_START_ADDR) | 1275 | #define bfin_read_DMA14_START_ADDR() bfin_read32(DMA14_START_ADDR) |
| 1276 | #define bfin_write_DMA14_START_ADDR(val) bfin_write32(DMA14_START_ADDR) | 1276 | #define bfin_write_DMA14_START_ADDR(val) bfin_write32(DMA14_START_ADDR, val) |
| 1277 | #define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG) | 1277 | #define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG) |
| 1278 | #define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val) | 1278 | #define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val) |
| 1279 | #define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT) | 1279 | #define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT) |
| 1280 | #define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val) | 1280 | #define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val) |
| 1281 | #define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY) | 1281 | #define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY) |
| 1282 | #define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY) | 1282 | #define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val) |
| 1283 | #define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT) | 1283 | #define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT) |
| 1284 | #define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val) | 1284 | #define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val) |
| 1285 | #define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY) | 1285 | #define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY) |
| 1286 | #define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY) | 1286 | #define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val) |
| 1287 | #define bfin_read_DMA14_CURR_DESC_PTR() bfin_read32(DMA14_CURR_DESC_PTR) | 1287 | #define bfin_read_DMA14_CURR_DESC_PTR() bfin_read32(DMA14_CURR_DESC_PTR) |
| 1288 | #define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_write32(DMA14_CURR_DESC_PTR) | 1288 | #define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_write32(DMA14_CURR_DESC_PTR, val) |
| 1289 | #define bfin_read_DMA14_CURR_ADDR() bfin_read32(DMA14_CURR_ADDR) | 1289 | #define bfin_read_DMA14_CURR_ADDR() bfin_read32(DMA14_CURR_ADDR) |
| 1290 | #define bfin_write_DMA14_CURR_ADDR(val) bfin_write32(DMA14_CURR_ADDR) | 1290 | #define bfin_write_DMA14_CURR_ADDR(val) bfin_write32(DMA14_CURR_ADDR, val) |
| 1291 | #define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS) | 1291 | #define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS) |
| 1292 | #define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val) | 1292 | #define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val) |
| 1293 | #define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP) | 1293 | #define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP) |
| @@ -1300,23 +1300,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
| 1300 | /* DMA Channel 15 Registers */ | 1300 | /* DMA Channel 15 Registers */ |
| 1301 | 1301 | ||
| 1302 | #define bfin_read_DMA15_NEXT_DESC_PTR() bfin_read32(DMA15_NEXT_DESC_PTR) | 1302 | #define bfin_read_DMA15_NEXT_DESC_PTR() bfin_read32(DMA15_NEXT_DESC_PTR) |
| 1303 | #define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_write32(DMA15_NEXT_DESC_PTR) | 1303 | #define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_write32(DMA15_NEXT_DESC_PTR, val) |
| 1304 | #define bfin_read_DMA15_START_ADDR() bfin_read32(DMA15_START_ADDR) | 1304 | #define bfin_read_DMA15_START_ADDR() bfin_read32(DMA15_START_ADDR) |
| 1305 | #define bfin_write_DMA15_START_ADDR(val) bfin_write32(DMA15_START_ADDR) | 1305 | #define bfin_write_DMA15_START_ADDR(val) bfin_write32(DMA15_START_ADDR, val) |
| 1306 | #define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG) | 1306 | #define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG) |
| 1307 | #define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val) | 1307 | #define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val) |
| 1308 | #define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT) | 1308 | #define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT) |
| 1309 | #define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val) | 1309 | #define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val) |
| 1310 | #define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY) | 1310 | #define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY) |
| 1311 | #define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY) | 1311 | #define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val) |
| 1312 | #define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT) | 1312 | #define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT) |
| 1313 | #define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val) | 1313 | #define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val) |
| 1314 | #define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY) | 1314 | #define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY) |
| 1315 | #define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY) | 1315 | #define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val) |
| 1316 | #define bfin_read_DMA15_CURR_DESC_PTR() bfin_read32(DMA15_CURR_DESC_PTR) | 1316 | #define bfin_read_DMA15_CURR_DESC_PTR() bfin_read32(DMA15_CURR_DESC_PTR) |
| 1317 | #define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_write32(DMA15_CURR_DESC_PTR) | 1317 | #define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_write32(DMA15_CURR_DESC_PTR, val) |
| 1318 | #define bfin_read_DMA15_CURR_ADDR() bfin_read32(DMA15_CURR_ADDR) | 1318 | #define bfin_read_DMA15_CURR_ADDR() bfin_read32(DMA15_CURR_ADDR) |
| 1319 | #define bfin_write_DMA15_CURR_ADDR(val) bfin_write32(DMA15_CURR_ADDR) | 1319 | #define bfin_write_DMA15_CURR_ADDR(val) bfin_write32(DMA15_CURR_ADDR, val) |
| 1320 | #define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS) | 1320 | #define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS) |
| 1321 | #define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val) | 1321 | #define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val) |
| 1322 | #define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP) | 1322 | #define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP) |
| @@ -1329,23 +1329,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
| 1329 | /* DMA Channel 16 Registers */ | 1329 | /* DMA Channel 16 Registers */ |
| 1330 | 1330 | ||
| 1331 | #define bfin_read_DMA16_NEXT_DESC_PTR() bfin_read32(DMA16_NEXT_DESC_PTR) | 1331 | #define bfin_read_DMA16_NEXT_DESC_PTR() bfin_read32(DMA16_NEXT_DESC_PTR) |
| 1332 | #define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_write32(DMA16_NEXT_DESC_PTR) | 1332 | #define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_write32(DMA16_NEXT_DESC_PTR, val) |
| 1333 | #define bfin_read_DMA16_START_ADDR() bfin_read32(DMA16_START_ADDR) | 1333 | #define bfin_read_DMA16_START_ADDR() bfin_read32(DMA16_START_ADDR) |
| 1334 | #define bfin_write_DMA16_START_ADDR(val) bfin_write32(DMA16_START_ADDR) | 1334 | #define bfin_write_DMA16_START_ADDR(val) bfin_write32(DMA16_START_ADDR, val) |
| 1335 | #define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG) | 1335 | #define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG) |
| 1336 | #define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val) | 1336 | #define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val) |
| 1337 | #define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT) | 1337 | #define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT) |
| 1338 | #define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val) | 1338 | #define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val) |
| 1339 | #define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY) | 1339 | #define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY) |
| 1340 | #define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY) | 1340 | #define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val) |
| 1341 | #define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT) | 1341 | #define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT) |
| 1342 | #define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val) | 1342 | #define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val) |
| 1343 | #define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY) | 1343 | #define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY) |
| 1344 | #define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY) | 1344 | #define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val) |
| 1345 | #define bfin_read_DMA16_CURR_DESC_PTR() bfin_read32(DMA16_CURR_DESC_PTR) | 1345 | #define bfin_read_DMA16_CURR_DESC_PTR() bfin_read32(DMA16_CURR_DESC_PTR) |
| 1346 | #define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_write32(DMA16_CURR_DESC_PTR) | 1346 | #define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_write32(DMA16_CURR_DESC_PTR, val) |
| 1347 | #define bfin_read_DMA16_CURR_ADDR() bfin_read32(DMA16_CURR_ADDR) | 1347 | #define bfin_read_DMA16_CURR_ADDR() bfin_read32(DMA16_CURR_ADDR) |
| 1348 | #define bfin_write_DMA16_CURR_ADDR(val) bfin_write32(DMA16_CURR_ADDR) | 1348 | #define bfin_write_DMA16_CURR_ADDR(val) bfin_write32(DMA16_CURR_ADDR, val) |
| 1349 | #define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS) | 1349 | #define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS) |
| 1350 | #define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val) | 1350 | #define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val) |
| 1351 | #define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP) | 1351 | #define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP) |
| @@ -1358,23 +1358,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
| 1358 | /* DMA Channel 17 Registers */ | 1358 | /* DMA Channel 17 Registers */ |
| 1359 | 1359 | ||
| 1360 | #define bfin_read_DMA17_NEXT_DESC_PTR() bfin_read32(DMA17_NEXT_DESC_PTR) | 1360 | #define bfin_read_DMA17_NEXT_DESC_PTR() bfin_read32(DMA17_NEXT_DESC_PTR) |
| 1361 | #define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_write32(DMA17_NEXT_DESC_PTR) | 1361 | #define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_write32(DMA17_NEXT_DESC_PTR, val) |
| 1362 | #define bfin_read_DMA17_START_ADDR() bfin_read32(DMA17_START_ADDR) | 1362 | #define bfin_read_DMA17_START_ADDR() bfin_read32(DMA17_START_ADDR) |
| 1363 | #define bfin_write_DMA17_START_ADDR(val) bfin_write32(DMA17_START_ADDR) | 1363 | #define bfin_write_DMA17_START_ADDR(val) bfin_write32(DMA17_START_ADDR, val) |
| 1364 | #define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG) | 1364 | #define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG) |
| 1365 | #define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val) | 1365 | #define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val) |
| 1366 | #define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT) | 1366 | #define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT) |
| 1367 | #define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val) | 1367 | #define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val) |
| 1368 | #define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY) | 1368 | #define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY) |
| 1369 | #define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY) | 1369 | #define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val) |
| 1370 | #define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT) | 1370 | #define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT) |
| 1371 | #define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val) | 1371 | #define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val) |
| 1372 | #define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY) | 1372 | #define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY) |
| 1373 | #define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY) | 1373 | #define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val) |
| 1374 | #define bfin_read_DMA17_CURR_DESC_PTR() bfin_read32(DMA17_CURR_DESC_PTR) | 1374 | #define bfin_read_DMA17_CURR_DESC_PTR() bfin_read32(DMA17_CURR_DESC_PTR) |
| 1375 | #define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_write32(DMA17_CURR_DESC_PTR) | 1375 | #define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_write32(DMA17_CURR_DESC_PTR, val) |
| 1376 | #define bfin_read_DMA17_CURR_ADDR() bfin_read32(DMA17_CURR_ADDR) | 1376 | #define bfin_read_DMA17_CURR_ADDR() bfin_read32(DMA17_CURR_ADDR) |
| 1377 | #define bfin_write_DMA17_CURR_ADDR(val) bfin_write32(DMA17_CURR_ADDR) | 1377 | #define bfin_write_DMA17_CURR_ADDR(val) bfin_write32(DMA17_CURR_ADDR, val) |
| 1378 | #define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS) | 1378 | #define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS) |
| 1379 | #define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val) | 1379 | #define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val) |
| 1380 | #define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP) | 1380 | #define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP) |
| @@ -1387,23 +1387,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
| 1387 | /* DMA Channel 18 Registers */ | 1387 | /* DMA Channel 18 Registers */ |
| 1388 | 1388 | ||
| 1389 | #define bfin_read_DMA18_NEXT_DESC_PTR() bfin_read32(DMA18_NEXT_DESC_PTR) | 1389 | #define bfin_read_DMA18_NEXT_DESC_PTR() bfin_read32(DMA18_NEXT_DESC_PTR) |
| 1390 | #define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_write32(DMA18_NEXT_DESC_PTR) | 1390 | #define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_write32(DMA18_NEXT_DESC_PTR, val) |
| 1391 | #define bfin_read_DMA18_START_ADDR() bfin_read32(DMA18_START_ADDR) | 1391 | #define bfin_read_DMA18_START_ADDR() bfin_read32(DMA18_START_ADDR) |
| 1392 | #define bfin_write_DMA18_START_ADDR(val) bfin_write32(DMA18_START_ADDR) | 1392 | #define bfin_write_DMA18_START_ADDR(val) bfin_write32(DMA18_START_ADDR, val) |
| 1393 | #define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG) | 1393 | #define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG) |
| 1394 | #define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val) | 1394 | #define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val) |
| 1395 | #define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT) | 1395 | #define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT) |
| 1396 | #define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val) | 1396 | #define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val) |
| 1397 | #define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY) | 1397 | #define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY) |
| 1398 | #define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY) | 1398 | #define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val) |
| 1399 | #define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT) | 1399 | #define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT) |
| 1400 | #define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val) | 1400 | #define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val) |
| 1401 | #define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY) | 1401 | #define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY) |
| 1402 | #define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY) | 1402 | #define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val) |
| 1403 | #define bfin_read_DMA18_CURR_DESC_PTR() bfin_read32(DMA18_CURR_DESC_PTR) | 1403 | #define bfin_read_DMA18_CURR_DESC_PTR() bfin_read32(DMA18_CURR_DESC_PTR) |
| 1404 | #define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_write32(DMA18_CURR_DESC_PTR) | 1404 | #define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_write32(DMA18_CURR_DESC_PTR, val) |
| 1405 | #define bfin_read_DMA18_CURR_ADDR() bfin_read32(DMA18_CURR_ADDR) | 1405 | #define bfin_read_DMA18_CURR_ADDR() bfin_read32(DMA18_CURR_ADDR) |
| 1406 | #define bfin_write_DMA18_CURR_ADDR(val) bfin_write32(DMA18_CURR_ADDR) | 1406 | #define bfin_write_DMA18_CURR_ADDR(val) bfin_write32(DMA18_CURR_ADDR, val) |
| 1407 | #define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS) | 1407 | #define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS) |
| 1408 | #define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val) | 1408 | #define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val) |
| 1409 | #define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP) | 1409 | #define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP) |
| @@ -1416,23 +1416,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
| 1416 | /* DMA Channel 19 Registers */ | 1416 | /* DMA Channel 19 Registers */ |
| 1417 | 1417 | ||
| 1418 | #define bfin_read_DMA19_NEXT_DESC_PTR() bfin_read32(DMA19_NEXT_DESC_PTR) | 1418 | #define bfin_read_DMA19_NEXT_DESC_PTR() bfin_read32(DMA19_NEXT_DESC_PTR) |
| 1419 | #define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_write32(DMA19_NEXT_DESC_PTR) | 1419 | #define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_write32(DMA19_NEXT_DESC_PTR, val) |
| 1420 | #define bfin_read_DMA19_START_ADDR() bfin_read32(DMA19_START_ADDR) | 1420 | #define bfin_read_DMA19_START_ADDR() bfin_read32(DMA19_START_ADDR) |
| 1421 | #define bfin_write_DMA19_START_ADDR(val) bfin_write32(DMA19_START_ADDR) | 1421 | #define bfin_write_DMA19_START_ADDR(val) bfin_write32(DMA19_START_ADDR, val) |
| 1422 | #define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG) | 1422 | #define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG) |
| 1423 | #define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val) | 1423 | #define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val) |
| 1424 | #define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT) | 1424 | #define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT) |
| 1425 | #define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val) | 1425 | #define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val) |
| 1426 | #define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY) | 1426 | #define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY) |
| 1427 | #define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY) | 1427 | #define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val) |
| 1428 | #define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT) | 1428 | #define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT) |
| 1429 | #define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val) | 1429 | #define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val) |
| 1430 | #define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY) | 1430 | #define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY) |
| 1431 | #define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY) | 1431 | #define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val) |
| 1432 | #define bfin_read_DMA19_CURR_DESC_PTR() bfin_read32(DMA19_CURR_DESC_PTR) | 1432 | #define bfin_read_DMA19_CURR_DESC_PTR() bfin_read32(DMA19_CURR_DESC_PTR) |
| 1433 | #define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_write32(DMA19_CURR_DESC_PTR) | 1433 | #define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_write32(DMA19_CURR_DESC_PTR, val) |
| 1434 | #define bfin_read_DMA19_CURR_ADDR() bfin_read32(DMA19_CURR_ADDR) | 1434 | #define bfin_read_DMA19_CURR_ADDR() bfin_read32(DMA19_CURR_ADDR) |
| 1435 | #define bfin_write_DMA19_CURR_ADDR(val) bfin_write32(DMA19_CURR_ADDR) | 1435 | #define bfin_write_DMA19_CURR_ADDR(val) bfin_write32(DMA19_CURR_ADDR, val) |
| 1436 | #define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS) | 1436 | #define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS) |
| 1437 | #define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val) | 1437 | #define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val) |
| 1438 | #define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP) | 1438 | #define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP) |
| @@ -1445,23 +1445,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
| 1445 | /* DMA Channel 20 Registers */ | 1445 | /* DMA Channel 20 Registers */ |
| 1446 | 1446 | ||
| 1447 | #define bfin_read_DMA20_NEXT_DESC_PTR() bfin_read32(DMA20_NEXT_DESC_PTR) | 1447 | #define bfin_read_DMA20_NEXT_DESC_PTR() bfin_read32(DMA20_NEXT_DESC_PTR) |
| 1448 | #define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_write32(DMA20_NEXT_DESC_PTR) | 1448 | #define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_write32(DMA20_NEXT_DESC_PTR, val) |
| 1449 | #define bfin_read_DMA20_START_ADDR() bfin_read32(DMA20_START_ADDR) | 1449 | #define bfin_read_DMA20_START_ADDR() bfin_read32(DMA20_START_ADDR) |
| 1450 | #define bfin_write_DMA20_START_ADDR(val) bfin_write32(DMA20_START_ADDR) | 1450 | #define bfin_write_DMA20_START_ADDR(val) bfin_write32(DMA20_START_ADDR, val) |
| 1451 | #define bfin_read_DMA20_CONFIG() bfin_read16(DMA20_CONFIG) | 1451 | #define bfin_read_DMA20_CONFIG() bfin_read16(DMA20_CONFIG) |
| 1452 | #define bfin_write_DMA20_CONFIG(val) bfin_write16(DMA20_CONFIG, val) | 1452 | #define bfin_write_DMA20_CONFIG(val) bfin_write16(DMA20_CONFIG, val) |
| 1453 | #define bfin_read_DMA20_X_COUNT() bfin_read16(DMA20_X_COUNT) | 1453 | #define bfin_read_DMA20_X_COUNT() bfin_read16(DMA20_X_COUNT) |
| 1454 | #define bfin_write_DMA20_X_COUNT(val) bfin_write16(DMA20_X_COUNT, val) | 1454 | #define bfin_write_DMA20_X_COUNT(val) bfin_write16(DMA20_X_COUNT, val) |
| 1455 | #define bfin_read_DMA20_X_MODIFY() bfin_read16(DMA20_X_MODIFY) | 1455 | #define bfin_read_DMA20_X_MODIFY() bfin_read16(DMA20_X_MODIFY) |
| 1456 | #define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY) | 1456 | #define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val) |
| 1457 | #define bfin_read_DMA20_Y_COUNT() bfin_read16(DMA20_Y_COUNT) | 1457 | #define bfin_read_DMA20_Y_COUNT() bfin_read16(DMA20_Y_COUNT) |
| 1458 | #define bfin_write_DMA20_Y_COUNT(val) bfin_write16(DMA20_Y_COUNT, val) | 1458 | #define bfin_write_DMA20_Y_COUNT(val) bfin_write16(DMA20_Y_COUNT, val) |
| 1459 | #define bfin_read_DMA20_Y_MODIFY() bfin_read16(DMA20_Y_MODIFY) | 1459 | #define bfin_read_DMA20_Y_MODIFY() bfin_read16(DMA20_Y_MODIFY) |
| 1460 | #define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY) | 1460 | #define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val) |
| 1461 | #define bfin_read_DMA20_CURR_DESC_PTR() bfin_read32(DMA20_CURR_DESC_PTR) | 1461 | #define bfin_read_DMA20_CURR_DESC_PTR() bfin_read32(DMA20_CURR_DESC_PTR) |
| 1462 | #define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_write32(DMA20_CURR_DESC_PTR) | 1462 | #define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_write32(DMA20_CURR_DESC_PTR, val) |
| 1463 | #define bfin_read_DMA20_CURR_ADDR() bfin_read32(DMA20_CURR_ADDR) | 1463 | #define bfin_read_DMA20_CURR_ADDR() bfin_read32(DMA20_CURR_ADDR) |
| 1464 | #define bfin_write_DMA20_CURR_ADDR(val) bfin_write32(DMA20_CURR_ADDR) | 1464 | #define bfin_write_DMA20_CURR_ADDR(val) bfin_write32(DMA20_CURR_ADDR, val) |
| 1465 | #define bfin_read_DMA20_IRQ_STATUS() bfin_read16(DMA20_IRQ_STATUS) | 1465 | #define bfin_read_DMA20_IRQ_STATUS() bfin_read16(DMA20_IRQ_STATUS) |
| 1466 | #define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val) | 1466 | #define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val) |
| 1467 | #define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP) | 1467 | #define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP) |
| @@ -1474,23 +1474,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
| 1474 | /* DMA Channel 21 Registers */ | 1474 | /* DMA Channel 21 Registers */ |
| 1475 | 1475 | ||
| 1476 | #define bfin_read_DMA21_NEXT_DESC_PTR() bfin_read32(DMA21_NEXT_DESC_PTR) | 1476 | #define bfin_read_DMA21_NEXT_DESC_PTR() bfin_read32(DMA21_NEXT_DESC_PTR) |
| 1477 | #define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_write32(DMA21_NEXT_DESC_PTR) | 1477 | #define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_write32(DMA21_NEXT_DESC_PTR, val) |
| 1478 | #define bfin_read_DMA21_START_ADDR() bfin_read32(DMA21_START_ADDR) | 1478 | #define bfin_read_DMA21_START_ADDR() bfin_read32(DMA21_START_ADDR) |
| 1479 | #define bfin_write_DMA21_START_ADDR(val) bfin_write32(DMA21_START_ADDR) | 1479 | #define bfin_write_DMA21_START_ADDR(val) bfin_write32(DMA21_START_ADDR, val) |
| 1480 | #define bfin_read_DMA21_CONFIG() bfin_read16(DMA21_CONFIG) | 1480 | #define bfin_read_DMA21_CONFIG() bfin_read16(DMA21_CONFIG) |
| 1481 | #define bfin_write_DMA21_CONFIG(val) bfin_write16(DMA21_CONFIG, val) | 1481 | #define bfin_write_DMA21_CONFIG(val) bfin_write16(DMA21_CONFIG, val) |
| 1482 | #define bfin_read_DMA21_X_COUNT() bfin_read16(DMA21_X_COUNT) | 1482 | #define bfin_read_DMA21_X_COUNT() bfin_read16(DMA21_X_COUNT) |
| 1483 | #define bfin_write_DMA21_X_COUNT(val) bfin_write16(DMA21_X_COUNT, val) | 1483 | #define bfin_write_DMA21_X_COUNT(val) bfin_write16(DMA21_X_COUNT, val) |
| 1484 | #define bfin_read_DMA21_X_MODIFY() bfin_read16(DMA21_X_MODIFY) | 1484 | #define bfin_read_DMA21_X_MODIFY() bfin_read16(DMA21_X_MODIFY) |
| 1485 | #define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY) | 1485 | #define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val) |
| 1486 | #define bfin_read_DMA21_Y_COUNT() bfin_read16(DMA21_Y_COUNT) | 1486 | #define bfin_read_DMA21_Y_COUNT() bfin_read16(DMA21_Y_COUNT) |
| 1487 | #define bfin_write_DMA21_Y_COUNT(val) bfin_write16(DMA21_Y_COUNT, val) | 1487 | #define bfin_write_DMA21_Y_COUNT(val) bfin_write16(DMA21_Y_COUNT, val) |
| 1488 | #define bfin_read_DMA21_Y_MODIFY() bfin_read16(DMA21_Y_MODIFY) | 1488 | #define bfin_read_DMA21_Y_MODIFY() bfin_read16(DMA21_Y_MODIFY) |
| 1489 | #define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY) | 1489 | #define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val) |
| 1490 | #define bfin_read_DMA21_CURR_DESC_PTR() bfin_read32(DMA21_CURR_DESC_PTR) | 1490 | #define bfin_read_DMA21_CURR_DESC_PTR() bfin_read32(DMA21_CURR_DESC_PTR) |
| 1491 | #define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_write32(DMA21_CURR_DESC_PTR) | 1491 | #define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_write32(DMA21_CURR_DESC_PTR, val) |
| 1492 | #define bfin_read_DMA21_CURR_ADDR() bfin_read32(DMA21_CURR_ADDR) | 1492 | #define bfin_read_DMA21_CURR_ADDR() bfin_read32(DMA21_CURR_ADDR) |
| 1493 | #define bfin_write_DMA21_CURR_ADDR(val) bfin_write32(DMA21_CURR_ADDR) | 1493 | #define bfin_write_DMA21_CURR_ADDR(val) bfin_write32(DMA21_CURR_ADDR, val) |
| 1494 | #define bfin_read_DMA21_IRQ_STATUS() bfin_read16(DMA21_IRQ_STATUS) | 1494 | #define bfin_read_DMA21_IRQ_STATUS() bfin_read16(DMA21_IRQ_STATUS) |
| 1495 | #define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val) | 1495 | #define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val) |
| 1496 | #define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP) | 1496 | #define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP) |
| @@ -1503,23 +1503,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
| 1503 | /* DMA Channel 22 Registers */ | 1503 | /* DMA Channel 22 Registers */ |
| 1504 | 1504 | ||
| 1505 | #define bfin_read_DMA22_NEXT_DESC_PTR() bfin_read32(DMA22_NEXT_DESC_PTR) | 1505 | #define bfin_read_DMA22_NEXT_DESC_PTR() bfin_read32(DMA22_NEXT_DESC_PTR) |
| 1506 | #define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_write32(DMA22_NEXT_DESC_PTR) | 1506 | #define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_write32(DMA22_NEXT_DESC_PTR, val) |
| 1507 | #define bfin_read_DMA22_START_ADDR() bfin_read32(DMA22_START_ADDR) | 1507 | #define bfin_read_DMA22_START_ADDR() bfin_read32(DMA22_START_ADDR) |
| 1508 | #define bfin_write_DMA22_START_ADDR(val) bfin_write32(DMA22_START_ADDR) | 1508 | #define bfin_write_DMA22_START_ADDR(val) bfin_write32(DMA22_START_ADDR, val) |
| 1509 | #define bfin_read_DMA22_CONFIG() bfin_read16(DMA22_CONFIG) | 1509 | #define bfin_read_DMA22_CONFIG() bfin_read16(DMA22_CONFIG) |
| 1510 | #define bfin_write_DMA22_CONFIG(val) bfin_write16(DMA22_CONFIG, val) | 1510 | #define bfin_write_DMA22_CONFIG(val) bfin_write16(DMA22_CONFIG, val) |
| 1511 | #define bfin_read_DMA22_X_COUNT() bfin_read16(DMA22_X_COUNT) | 1511 | #define bfin_read_DMA22_X_COUNT() bfin_read16(DMA22_X_COUNT) |
| 1512 | #define bfin_write_DMA22_X_COUNT(val) bfin_write16(DMA22_X_COUNT, val) | 1512 | #define bfin_write_DMA22_X_COUNT(val) bfin_write16(DMA22_X_COUNT, val) |
| 1513 | #define bfin_read_DMA22_X_MODIFY() bfin_read16(DMA22_X_MODIFY) | 1513 | #define bfin_read_DMA22_X_MODIFY() bfin_read16(DMA22_X_MODIFY) |
| 1514 | #define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY) | 1514 | #define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val) |
| 1515 | #define bfin_read_DMA22_Y_COUNT() bfin_read16(DMA22_Y_COUNT) | 1515 | #define bfin_read_DMA22_Y_COUNT() bfin_read16(DMA22_Y_COUNT) |
| 1516 | #define bfin_write_DMA22_Y_COUNT(val) bfin_write16(DMA22_Y_COUNT, val) | 1516 | #define bfin_write_DMA22_Y_COUNT(val) bfin_write16(DMA22_Y_COUNT, val) |
| 1517 | #define bfin_read_DMA22_Y_MODIFY() bfin_read16(DMA22_Y_MODIFY) | 1517 | #define bfin_read_DMA22_Y_MODIFY() bfin_read16(DMA22_Y_MODIFY) |
| 1518 | #define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY) | 1518 | #define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val) |
| 1519 | #define bfin_read_DMA22_CURR_DESC_PTR() bfin_read32(DMA22_CURR_DESC_PTR) | 1519 | #define bfin_read_DMA22_CURR_DESC_PTR() bfin_read32(DMA22_CURR_DESC_PTR) |
| 1520 | #define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_write32(DMA22_CURR_DESC_PTR) | 1520 | #define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_write32(DMA22_CURR_DESC_PTR, val) |
| 1521 | #define bfin_read_DMA22_CURR_ADDR() bfin_read32(DMA22_CURR_ADDR) | 1521 | #define bfin_read_DMA22_CURR_ADDR() bfin_read32(DMA22_CURR_ADDR) |
| 1522 | #define bfin_write_DMA22_CURR_ADDR(val) bfin_write32(DMA22_CURR_ADDR) | 1522 | #define bfin_write_DMA22_CURR_ADDR(val) bfin_write32(DMA22_CURR_ADDR, val) |
| 1523 | #define bfin_read_DMA22_IRQ_STATUS() bfin_read16(DMA22_IRQ_STATUS) | 1523 | #define bfin_read_DMA22_IRQ_STATUS() bfin_read16(DMA22_IRQ_STATUS) |
| 1524 | #define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val) | 1524 | #define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val) |
| 1525 | #define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP) | 1525 | #define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP) |
| @@ -1532,23 +1532,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
| 1532 | /* DMA Channel 23 Registers */ | 1532 | /* DMA Channel 23 Registers */ |
| 1533 | 1533 | ||
| 1534 | #define bfin_read_DMA23_NEXT_DESC_PTR() bfin_read32(DMA23_NEXT_DESC_PTR) | 1534 | #define bfin_read_DMA23_NEXT_DESC_PTR() bfin_read32(DMA23_NEXT_DESC_PTR) |
| 1535 | #define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_write32(DMA23_NEXT_DESC_PTR) | 1535 | #define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_write32(DMA23_NEXT_DESC_PTR, val) |
| 1536 | #define bfin_read_DMA23_START_ADDR() bfin_read32(DMA23_START_ADDR) | 1536 | #define bfin_read_DMA23_START_ADDR() bfin_read32(DMA23_START_ADDR) |
| 1537 | #define bfin_write_DMA23_START_ADDR(val) bfin_write32(DMA23_START_ADDR) | 1537 | #define bfin_write_DMA23_START_ADDR(val) bfin_write32(DMA23_START_ADDR, val) |
| 1538 | #define bfin_read_DMA23_CONFIG() bfin_read16(DMA23_CONFIG) | 1538 | #define bfin_read_DMA23_CONFIG() bfin_read16(DMA23_CONFIG) |
| 1539 | #define bfin_write_DMA23_CONFIG(val) bfin_write16(DMA23_CONFIG, val) | 1539 | #define bfin_write_DMA23_CONFIG(val) bfin_write16(DMA23_CONFIG, val) |
| 1540 | #define bfin_read_DMA23_X_COUNT() bfin_read16(DMA23_X_COUNT) | 1540 | #define bfin_read_DMA23_X_COUNT() bfin_read16(DMA23_X_COUNT) |
| 1541 | #define bfin_write_DMA23_X_COUNT(val) bfin_write16(DMA23_X_COUNT, val) | 1541 | #define bfin_write_DMA23_X_COUNT(val) bfin_write16(DMA23_X_COUNT, val) |
| 1542 | #define bfin_read_DMA23_X_MODIFY() bfin_read16(DMA23_X_MODIFY) | 1542 | #define bfin_read_DMA23_X_MODIFY() bfin_read16(DMA23_X_MODIFY) |
| 1543 | #define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY) | 1543 | #define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val) |
| 1544 | #define bfin_read_DMA23_Y_COUNT() bfin_read16(DMA23_Y_COUNT) | 1544 | #define bfin_read_DMA23_Y_COUNT() bfin_read16(DMA23_Y_COUNT) |
| 1545 | #define bfin_write_DMA23_Y_COUNT(val) bfin_write16(DMA23_Y_COUNT, val) | 1545 | #define bfin_write_DMA23_Y_COUNT(val) bfin_write16(DMA23_Y_COUNT, val) |
| 1546 | #define bfin_read_DMA23_Y_MODIFY() bfin_read16(DMA23_Y_MODIFY) | 1546 | #define bfin_read_DMA23_Y_MODIFY() bfin_read16(DMA23_Y_MODIFY) |
| 1547 | #define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY) | 1547 | #define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val) |
| 1548 | #define bfin_read_DMA23_CURR_DESC_PTR() bfin_read32(DMA23_CURR_DESC_PTR) | 1548 | #define bfin_read_DMA23_CURR_DESC_PTR() bfin_read32(DMA23_CURR_DESC_PTR) |
| 1549 | #define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_write32(DMA23_CURR_DESC_PTR) | 1549 | #define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_write32(DMA23_CURR_DESC_PTR, val) |
| 1550 | #define bfin_read_DMA23_CURR_ADDR() bfin_read32(DMA23_CURR_ADDR) | 1550 | #define bfin_read_DMA23_CURR_ADDR() bfin_read32(DMA23_CURR_ADDR) |
| 1551 | #define bfin_write_DMA23_CURR_ADDR(val) bfin_write32(DMA23_CURR_ADDR) | 1551 | #define bfin_write_DMA23_CURR_ADDR(val) bfin_write32(DMA23_CURR_ADDR, val) |
| 1552 | #define bfin_read_DMA23_IRQ_STATUS() bfin_read16(DMA23_IRQ_STATUS) | 1552 | #define bfin_read_DMA23_IRQ_STATUS() bfin_read16(DMA23_IRQ_STATUS) |
| 1553 | #define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val) | 1553 | #define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val) |
| 1554 | #define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP) | 1554 | #define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP) |
| @@ -1561,23 +1561,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
| 1561 | /* MDMA Stream 2 Registers */ | 1561 | /* MDMA Stream 2 Registers */ |
| 1562 | 1562 | ||
| 1563 | #define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_read32(MDMA_D2_NEXT_DESC_PTR) | 1563 | #define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_read32(MDMA_D2_NEXT_DESC_PTR) |
| 1564 | #define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_write32(MDMA_D2_NEXT_DESC_PTR) | 1564 | #define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_write32(MDMA_D2_NEXT_DESC_PTR, val) |
| 1565 | #define bfin_read_MDMA_D2_START_ADDR() bfin_read32(MDMA_D2_START_ADDR) | 1565 | #define bfin_read_MDMA_D2_START_ADDR() bfin_read32(MDMA_D2_START_ADDR) |
| 1566 | #define bfin_write_MDMA_D2_START_ADDR(val) bfin_write32(MDMA_D2_START_ADDR) | 1566 | #define bfin_write_MDMA_D2_START_ADDR(val) bfin_write32(MDMA_D2_START_ADDR, val) |
| 1567 | #define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG) | 1567 | #define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG) |
| 1568 | #define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val) | 1568 | #define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val) |
| 1569 | #define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT) | 1569 | #define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT) |
| 1570 | #define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val) | 1570 | #define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val) |
| 1571 | #define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY) | 1571 | #define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY) |
| 1572 | #define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY) | 1572 | #define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val) |
| 1573 | #define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT) | 1573 | #define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT) |
| 1574 | #define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val) | 1574 | #define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val) |
| 1575 | #define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY) | 1575 | #define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY) |
| 1576 | #define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY) | 1576 | #define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val) |
| 1577 | #define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_read32(MDMA_D2_CURR_DESC_PTR) | 1577 | #define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_read32(MDMA_D2_CURR_DESC_PTR) |
| 1578 | #define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_write32(MDMA_D2_CURR_DESC_PTR) | 1578 | #define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_write32(MDMA_D2_CURR_DESC_PTR, val) |
| 1579 | #define bfin_read_MDMA_D2_CURR_ADDR() bfin_read32(MDMA_D2_CURR_ADDR) | 1579 | #define bfin_read_MDMA_D2_CURR_ADDR() bfin_read32(MDMA_D2_CURR_ADDR) |
| 1580 | #define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_write32(MDMA_D2_CURR_ADDR) | 1580 | #define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_write32(MDMA_D2_CURR_ADDR, val) |
| 1581 | #define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS) | 1581 | #define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS) |
| 1582 | #define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val) | 1582 | #define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val) |
| 1583 | #define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP) | 1583 | #define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP) |
| @@ -1587,23 +1587,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
| 1587 | #define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT) | 1587 | #define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT) |
| 1588 | #define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val) | 1588 | #define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val) |
| 1589 | #define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_read32(MDMA_S2_NEXT_DESC_PTR) | 1589 | #define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_read32(MDMA_S2_NEXT_DESC_PTR) |
| 1590 | #define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_write32(MDMA_S2_NEXT_DESC_PTR) | 1590 | #define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_write32(MDMA_S2_NEXT_DESC_PTR, val) |
| 1591 | #define bfin_read_MDMA_S2_START_ADDR() bfin_read32(MDMA_S2_START_ADDR) | 1591 | #define bfin_read_MDMA_S2_START_ADDR() bfin_read32(MDMA_S2_START_ADDR) |
| 1592 | #define bfin_write_MDMA_S2_START_ADDR(val) bfin_write32(MDMA_S2_START_ADDR) | 1592 | #define bfin_write_MDMA_S2_START_ADDR(val) bfin_write32(MDMA_S2_START_ADDR, val) |
| 1593 | #define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG) | 1593 | #define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG) |
| 1594 | #define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val) | 1594 | #define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val) |
| 1595 | #define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT) | 1595 | #define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT) |
| 1596 | #define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val) | 1596 | #define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val) |
| 1597 | #define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY) | 1597 | #define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY) |
| 1598 | #define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY) | 1598 | #define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val) |
| 1599 | #define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT) | 1599 | #define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT) |
| 1600 | #define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val) | 1600 | #define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val) |
| 1601 | #define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY) | 1601 | #define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY) |
| 1602 | #define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY) | 1602 | #define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val) |
| 1603 | #define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_read32(MDMA_S2_CURR_DESC_PTR) | 1603 | #define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_read32(MDMA_S2_CURR_DESC_PTR) |
| 1604 | #define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_write32(MDMA_S2_CURR_DESC_PTR) | 1604 | #define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_write32(MDMA_S2_CURR_DESC_PTR, val) |
| 1605 | #define bfin_read_MDMA_S2_CURR_ADDR() bfin_read32(MDMA_S2_CURR_ADDR) | 1605 | #define bfin_read_MDMA_S2_CURR_ADDR() bfin_read32(MDMA_S2_CURR_ADDR) |
| 1606 | #define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_write32(MDMA_S2_CURR_ADDR) | 1606 | #define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_write32(MDMA_S2_CURR_ADDR, val) |
| 1607 | #define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS) | 1607 | #define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS) |
| 1608 | #define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val) | 1608 | #define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val) |
| 1609 | #define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP) | 1609 | #define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP) |
| @@ -1616,23 +1616,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
| 1616 | /* MDMA Stream 3 Registers */ | 1616 | /* MDMA Stream 3 Registers */ |
| 1617 | 1617 | ||
| 1618 | #define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_read32(MDMA_D3_NEXT_DESC_PTR) | 1618 | #define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_read32(MDMA_D3_NEXT_DESC_PTR) |
| 1619 | #define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_write32(MDMA_D3_NEXT_DESC_PTR) | 1619 | #define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_write32(MDMA_D3_NEXT_DESC_PTR, val) |
| 1620 | #define bfin_read_MDMA_D3_START_ADDR() bfin_read32(MDMA_D3_START_ADDR) | 1620 | #define bfin_read_MDMA_D3_START_ADDR() bfin_read32(MDMA_D3_START_ADDR) |
| 1621 | #define bfin_write_MDMA_D3_START_ADDR(val) bfin_write32(MDMA_D3_START_ADDR) | 1621 | #define bfin_write_MDMA_D3_START_ADDR(val) bfin_write32(MDMA_D3_START_ADDR, val) |
| 1622 | #define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG) | 1622 | #define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG) |
| 1623 | #define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val) | 1623 | #define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val) |
| 1624 | #define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT) | 1624 | #define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT) |
| 1625 | #define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val) | 1625 | #define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val) |
| 1626 | #define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY) | 1626 | #define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY) |
| 1627 | #define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY) | 1627 | #define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val) |
| 1628 | #define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT) | 1628 | #define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT) |
| 1629 | #define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val) | 1629 | #define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val) |
| 1630 | #define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY) | 1630 | #define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY) |
| 1631 | #define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY) | 1631 | #define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val) |
| 1632 | #define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_read32(MDMA_D3_CURR_DESC_PTR) | 1632 | #define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_read32(MDMA_D3_CURR_DESC_PTR) |
| 1633 | #define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_write32(MDMA_D3_CURR_DESC_PTR) | 1633 | #define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_write32(MDMA_D3_CURR_DESC_PTR, val) |
| 1634 | #define bfin_read_MDMA_D3_CURR_ADDR() bfin_read32(MDMA_D3_CURR_ADDR) | 1634 | #define bfin_read_MDMA_D3_CURR_ADDR() bfin_read32(MDMA_D3_CURR_ADDR) |
| 1635 | #define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_write32(MDMA_D3_CURR_ADDR) | 1635 | #define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_write32(MDMA_D3_CURR_ADDR, val) |
| 1636 | #define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS) | 1636 | #define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS) |
| 1637 | #define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val) | 1637 | #define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val) |
| 1638 | #define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP) | 1638 | #define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP) |
| @@ -1642,23 +1642,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
| 1642 | #define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT) | 1642 | #define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT) |
| 1643 | #define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val) | 1643 | #define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val) |
| 1644 | #define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_read32(MDMA_S3_NEXT_DESC_PTR) | 1644 | #define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_read32(MDMA_S3_NEXT_DESC_PTR) |
| 1645 | #define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_write32(MDMA_S3_NEXT_DESC_PTR) | 1645 | #define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_write32(MDMA_S3_NEXT_DESC_PTR, val) |
| 1646 | #define bfin_read_MDMA_S3_START_ADDR() bfin_read32(MDMA_S3_START_ADDR) | 1646 | #define bfin_read_MDMA_S3_START_ADDR() bfin_read32(MDMA_S3_START_ADDR) |
| 1647 | #define bfin_write_MDMA_S3_START_ADDR(val) bfin_write32(MDMA_S3_START_ADDR) | 1647 | #define bfin_write_MDMA_S3_START_ADDR(val) bfin_write32(MDMA_S3_START_ADDR, val) |
| 1648 | #define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG) | 1648 | #define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG) |
| 1649 | #define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val) | 1649 | #define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val) |
| 1650 | #define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT) | 1650 | #define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT) |
| 1651 | #define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val) | 1651 | #define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val) |
| 1652 | #define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY) | 1652 | #define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY) |
| 1653 | #define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY) | 1653 | #define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val) |
| 1654 | #define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT) | 1654 | #define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT) |
| 1655 | #define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val) | 1655 | #define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val) |
| 1656 | #define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY) | 1656 | #define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY) |
| 1657 | #define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY) | 1657 | #define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val) |
| 1658 | #define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_read32(MDMA_S3_CURR_DESC_PTR) | 1658 | #define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_read32(MDMA_S3_CURR_DESC_PTR) |
| 1659 | #define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_write32(MDMA_S3_CURR_DESC_PTR) | 1659 | #define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_write32(MDMA_S3_CURR_DESC_PTR, val) |
| 1660 | #define bfin_read_MDMA_S3_CURR_ADDR() bfin_read32(MDMA_S3_CURR_ADDR) | 1660 | #define bfin_read_MDMA_S3_CURR_ADDR() bfin_read32(MDMA_S3_CURR_ADDR) |
| 1661 | #define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_write32(MDMA_S3_CURR_ADDR) | 1661 | #define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_write32(MDMA_S3_CURR_ADDR, val) |
| 1662 | #define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS) | 1662 | #define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS) |
| 1663 | #define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val) | 1663 | #define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val) |
| 1664 | #define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP) | 1664 | #define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP) |